From 982383e46f139566ca38a083a35b2a0e52fb0acb Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tapani=20P=C3=A4lli?= Date: Thu, 21 Feb 2019 15:00:10 +0200 Subject: [PATCH 01/27] UPSTREAM: android: add liblog to libmesa_intel_common build MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Tapani Pälli Reviewed-by: Jordan Justen (cherry picked from commit a3c366c4b22993731b5d39a8387f30a09de10e38) --- src/intel/Android.common.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/Android.common.mk b/src/intel/Android.common.mk index 12cea6e5472..faec6b3ea4e 100644 --- a/src/intel/Android.common.mk +++ b/src/intel/Android.common.mk @@ -38,7 +38,7 @@ LOCAL_C_INCLUDES := \ $(MESA_TOP)/src/mapi \ $(MESA_TOP)/src/mesa -LOCAL_SHARED_LIBRARIES := libexpat libz +LOCAL_SHARED_LIBRARIES := libexpat libz liblog LOCAL_WHOLE_STATIC_LIBRARIES := libmesa_genxml From 91c07ca03eb85477a78753f850041a485620b8fa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tapani=20P=C3=A4lli?= Date: Tue, 26 Feb 2019 10:27:15 +0200 Subject: [PATCH 02/27] UPSTREAM: android: make libbacktrace optional on USE_LIBBACKTRACE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Otherwise with VNDK enabled we fail linking: src/gallium/targets/dri/Android.mk: error: gallium_dri (native:vendor) should not link to libbacktrace.vendor (native:vndk_private) Option makes it possible to use libbacktrace only when VNDK is not enabled. Signed-off-by: Tapani Pälli Reviewed-by: Jordan Justen (cherry picked from commit 5e52184f722b70c024bec6dc0872cbf6553a1d82) --- src/gallium/auxiliary/Android.mk | 7 +++++-- src/gallium/targets/dri/Android.mk | 5 ++++- 2 files changed, 9 insertions(+), 3 deletions(-) diff --git a/src/gallium/auxiliary/Android.mk b/src/gallium/auxiliary/Android.mk index 7618c6fcd93..fe976501451 100644 --- a/src/gallium/auxiliary/Android.mk +++ b/src/gallium/auxiliary/Android.mk @@ -32,8 +32,11 @@ LOCAL_SRC_FILES := \ $(C_SOURCES) \ $(NIR_SOURCES) \ $(RENDERONLY_SOURCES) \ - $(VL_STUB_SOURCES) \ - util/u_debug_stack_android.cpp + $(VL_STUB_SOURCES) + +ifeq ($(USE_LIBBACKTRACE),true) + LOCAL_SRC_FILES += util/u_debug_stack_android.cpp +endif LOCAL_C_INCLUDES := \ $(GALLIUM_TOP)/auxiliary/util \ diff --git a/src/gallium/targets/dri/Android.mk b/src/gallium/targets/dri/Android.mk index 9c43fa1e8fd..7638a67b26f 100644 --- a/src/gallium/targets/dri/Android.mk +++ b/src/gallium/targets/dri/Android.mk @@ -40,12 +40,15 @@ LOCAL_LDFLAGS := \ -Wl,--undefined-version LOCAL_SHARED_LIBRARIES := \ - libbacktrace \ libdl \ libglapi \ libexpat \ libz +ifeq ($(USE_LIBBACKTRACE),true) + LOCAL_SHARED_LIBRARIES += libbacktrace +endif + $(foreach d, $(MESA_BUILD_GALLIUM), $(eval LOCAL_CFLAGS += $(patsubst HAVE_%,-D%,$(d)))) # sort GALLIUM_LIBS to remove any duplicates From 68e7173ac13e3393c027ec566dc078284f3adf05 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tapani=20P=C3=A4lli?= Date: Tue, 5 Mar 2019 09:24:16 +0200 Subject: [PATCH 03/27] UPSTREAM: android: Build fixes for OMR1 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some of the header file locations are changed between Android versions (when VNDK is used), patch makes sure we get all the required headers. v2: cleanups, put SDK version checks in all places (Tapani) Signed-off-by: Tapani Pälli Signed-off-by: Chen Lin Z Tested-by: Clayton Craft Acked-by: Eric Engestrom (cherry picked from commit 791198a54b1182860e240d57f35cb02b1bcceca3) --- src/egl/Android.mk | 7 +++++++ src/intel/Android.vulkan.mk | 20 ++++++++++++++++++++ src/vulkan/Android.mk | 8 ++++++++ 3 files changed, 35 insertions(+) diff --git a/src/egl/Android.mk b/src/egl/Android.mk index 42b391e6d86..8b03bd628af 100644 --- a/src/egl/Android.mk +++ b/src/egl/Android.mk @@ -59,6 +59,13 @@ LOCAL_SHARED_LIBRARIES := \ libcutils \ libsync +ifeq ($(shell test $(PLATFORM_SDK_VERSION) -ge 27; echo $$?), 0) +LOCAL_C_INCLUDES += \ + frameworks/native/libs/nativewindow/include \ + frameworks/native/libs/arect/include +LOCAL_HEADER_LIBRARIES += libnativebase_headers +endif + ifeq ($(BOARD_USES_DRM_GRALLOC),true) LOCAL_CFLAGS += -DHAVE_DRM_GRALLOC LOCAL_SHARED_LIBRARIES += libgralloc_drm diff --git a/src/intel/Android.vulkan.mk b/src/intel/Android.vulkan.mk index 49fb2826c54..76c206d079a 100644 --- a/src/intel/Android.vulkan.mk +++ b/src/intel/Android.vulkan.mk @@ -42,6 +42,18 @@ VULKAN_COMMON_INCLUDES := \ $(MESA_TOP)/src/compiler \ frameworks/native/vulkan/include +ifeq ($(shell test $(PLATFORM_SDK_VERSION) -ge 27; echo $$?), 0) +VULKAN_COMMON_INCLUDES += \ + frameworks/native/vulkan/include \ + frameworks/native/libs/nativebase/include \ + frameworks/native/libs/nativewindow/include \ + frameworks/native/libs/arect/include + +VULKAN_COMMON_HEADER_LIBRARIES := \ + libcutils_headers \ + libhardware_headers +endif + # libmesa_anv_entrypoints with header and dummy.c # # This static library is built to pull entrypoints header @@ -111,6 +123,7 @@ LOCAL_C_INCLUDES := $(ANV_INCLUDES) LOCAL_WHOLE_STATIC_LIBRARIES := libmesa_anv_entrypoints libmesa_genxml LOCAL_SHARED_LIBRARIES := $(ANV_SHARED_LIBRARIES) +LOCAL_HEADER_LIBRARIES += $(VULKAN_COMMON_HEADER_LIBRARIES) include $(MESA_COMMON_MK) include $(BUILD_STATIC_LIBRARY) @@ -131,6 +144,7 @@ LOCAL_C_INCLUDES := $(ANV_INCLUDES) LOCAL_WHOLE_STATIC_LIBRARIES := libmesa_anv_entrypoints libmesa_genxml LOCAL_SHARED_LIBRARIES := $(ANV_SHARED_LIBRARIES) +LOCAL_HEADER_LIBRARIES += $(VULKAN_COMMON_HEADER_LIBRARIES) include $(MESA_COMMON_MK) include $(BUILD_STATIC_LIBRARY) @@ -151,6 +165,7 @@ LOCAL_C_INCLUDES := $(ANV_INCLUDES) LOCAL_WHOLE_STATIC_LIBRARIES := libmesa_anv_entrypoints libmesa_genxml LOCAL_SHARED_LIBRARIES := $(ANV_SHARED_LIBRARIES) +LOCAL_HEADER_LIBRARIES += $(VULKAN_COMMON_HEADER_LIBRARIES) include $(MESA_COMMON_MK) include $(BUILD_STATIC_LIBRARY) @@ -171,6 +186,7 @@ LOCAL_C_INCLUDES := $(ANV_INCLUDES) LOCAL_WHOLE_STATIC_LIBRARIES := libmesa_anv_entrypoints libmesa_genxml LOCAL_SHARED_LIBRARIES := $(ANV_SHARED_LIBRARIES) +LOCAL_HEADER_LIBRARIES += $(VULKAN_COMMON_HEADER_LIBRARIES) include $(MESA_COMMON_MK) include $(BUILD_STATIC_LIBRARY) @@ -191,6 +207,7 @@ LOCAL_C_INCLUDES := $(ANV_INCLUDES) LOCAL_WHOLE_STATIC_LIBRARIES := libmesa_anv_entrypoints libmesa_genxml LOCAL_SHARED_LIBRARIES := $(ANV_SHARED_LIBRARIES) +LOCAL_HEADER_LIBRARIES += $(VULKAN_COMMON_HEADER_LIBRARIES) include $(MESA_COMMON_MK) include $(BUILD_STATIC_LIBRARY) @@ -211,6 +228,7 @@ LOCAL_C_INCLUDES := $(ANV_INCLUDES) LOCAL_WHOLE_STATIC_LIBRARIES := libmesa_anv_entrypoints libmesa_genxml LOCAL_SHARED_LIBRARIES := $(ANV_SHARED_LIBRARIES) +LOCAL_HEADER_LIBRARIES += $(VULKAN_COMMON_HEADER_LIBRARIES) include $(MESA_COMMON_MK) include $(BUILD_STATIC_LIBRARY) @@ -271,6 +289,7 @@ $(intermediates)/vulkan/anv_extensions.h: $(ANV_EXTENSIONS_GEN_SCRIPT) \ --out-h $@ LOCAL_SHARED_LIBRARIES := $(ANV_SHARED_LIBRARIES) +LOCAL_HEADER_LIBRARIES += $(VULKAN_COMMON_HEADER_LIBRARIES) include $(MESA_COMMON_MK) include $(BUILD_STATIC_LIBRARY) @@ -320,6 +339,7 @@ LOCAL_WHOLE_STATIC_LIBRARIES := \ libmesa_anv_entrypoints LOCAL_SHARED_LIBRARIES := $(ANV_SHARED_LIBRARIES) libexpat libz libsync liblog +LOCAL_HEADER_LIBRARIES += $(VULKAN_COMMON_HEADER_LIBRARIES) include $(MESA_COMMON_MK) include $(BUILD_SHARED_LIBRARY) diff --git a/src/vulkan/Android.mk b/src/vulkan/Android.mk index 6253f1c3be9..99dd3f56313 100644 --- a/src/vulkan/Android.mk +++ b/src/vulkan/Android.mk @@ -39,6 +39,14 @@ LOCAL_C_INCLUDES := \ $(MESA_TOP)/include/vulkan \ $(MESA_TOP)/src/vulkan/util +ifeq ($(shell test $(PLATFORM_SDK_VERSION) -ge 27; echo $$?), 0) +LOCAL_C_INCLUDES += \ + frameworks/native/libs/nativebase/include \ + frameworks/native/libs/nativewindow/include \ + frameworks/native/libs/arect/include +LOCAL_HEADER_LIBRARIES += libcutils_headers libsystem_headers +endif + LOCAL_GENERATED_SOURCES := $(addprefix $(intermediates)/, \ $(VULKAN_UTIL_GENERATED_FILES)) From 796412521c5f901dbabf8dbf2fc32473610a6c99 Mon Sep 17 00:00:00 2001 From: Kishore Kadiyala Date: Mon, 11 Mar 2019 11:23:03 +0200 Subject: [PATCH 04/27] UPSTREAM: android: static link with libexpat with Android O+ MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In Android O, MESA needs to statically link libexpat so that it's in same VNDK namespace. v2: apply change also to anv driver (Tapani) v3: use += in anv change (Eric Engestrom) Change-Id: I82b0be5c817c21e734dfdf5bfb6a9aa1d414ab33 Signed-off-by: Kishore Kadiyala Signed-off-by: Tapani Pälli Reviewed-by: Eric Engestrom (cherry picked from commit e1d80571606684af869317837902abc6f6e82017) --- src/gallium/targets/dri/Android.mk | 10 +++++++++- src/intel/Android.common.mk | 12 +++++++++++- src/intel/Android.vulkan.mk | 11 ++++++++++- src/mesa/drivers/dri/Android.mk | 10 +++++++++- src/util/Android.mk | 6 ++++++ 5 files changed, 45 insertions(+), 4 deletions(-) diff --git a/src/gallium/targets/dri/Android.mk b/src/gallium/targets/dri/Android.mk index 7638a67b26f..6134251b5ca 100644 --- a/src/gallium/targets/dri/Android.mk +++ b/src/gallium/targets/dri/Android.mk @@ -42,9 +42,17 @@ LOCAL_LDFLAGS := \ LOCAL_SHARED_LIBRARIES := \ libdl \ libglapi \ - libexpat \ libz +# If Android version >=8 MESA should static link libexpat else should dynamic link +ifeq ($(shell test $(PLATFORM_SDK_VERSION) -ge 27; echo $$?), 0) +LOCAL_STATIC_LIBRARIES := \ + libexpat +else +LOCAL_SHARED_LIBRARIES += \ + libexpat +endif + ifeq ($(USE_LIBBACKTRACE),true) LOCAL_SHARED_LIBRARIES += libbacktrace endif diff --git a/src/intel/Android.common.mk b/src/intel/Android.common.mk index faec6b3ea4e..79d9f1284a0 100644 --- a/src/intel/Android.common.mk +++ b/src/intel/Android.common.mk @@ -38,7 +38,17 @@ LOCAL_C_INCLUDES := \ $(MESA_TOP)/src/mapi \ $(MESA_TOP)/src/mesa -LOCAL_SHARED_LIBRARIES := libexpat libz liblog +LOCAL_SHARED_LIBRARIES := libz liblog + +# If Android version >=8 MESA should static link libexpat else should dynamic link +ifeq ($(shell test $(PLATFORM_SDK_VERSION) -ge 27; echo $$?), 0) +LOCAL_STATIC_LIBRARIES := \ + libexpat +else +LOCAL_SHARED_LIBRARIES += \ + libexpat +endif + LOCAL_WHOLE_STATIC_LIBRARIES := libmesa_genxml diff --git a/src/intel/Android.vulkan.mk b/src/intel/Android.vulkan.mk index 76c206d079a..0f00c586473 100644 --- a/src/intel/Android.vulkan.mk +++ b/src/intel/Android.vulkan.mk @@ -338,8 +338,17 @@ LOCAL_WHOLE_STATIC_LIBRARIES := \ libmesa_intel_compiler \ libmesa_anv_entrypoints -LOCAL_SHARED_LIBRARIES := $(ANV_SHARED_LIBRARIES) libexpat libz libsync liblog +LOCAL_SHARED_LIBRARIES := $(ANV_SHARED_LIBRARIES) libz libsync liblog LOCAL_HEADER_LIBRARIES += $(VULKAN_COMMON_HEADER_LIBRARIES) +# If Android version >=8 MESA should static link libexpat else should dynamic link +ifeq ($(shell test $(PLATFORM_SDK_VERSION) -ge 27; echo $$?), 0) +LOCAL_STATIC_LIBRARIES := \ + libexpat +else + LOCAL_SHARED_LIBRARIES += \ + libexpat +endif + include $(MESA_COMMON_MK) include $(BUILD_SHARED_LIBRARY) diff --git a/src/mesa/drivers/dri/Android.mk b/src/mesa/drivers/dri/Android.mk index 53ff4b4f632..60c8476a38a 100644 --- a/src/mesa/drivers/dri/Android.mk +++ b/src/mesa/drivers/dri/Android.mk @@ -49,11 +49,19 @@ MESA_DRI_WHOLE_STATIC_LIBRARIES := \ MESA_DRI_SHARED_LIBRARIES := \ libcutils \ libdl \ - libexpat \ libglapi \ liblog \ libz +# If Android version >=8 MESA should static link libexpat else should dynamic link +ifeq ($(shell test $(PLATFORM_SDK_VERSION) -ge 27; echo $$?), 0) +MESA_DRI_WHOLE_STATIC_LIBRARIES += \ + libexpat +else +MESA_DRI_SHARED_LIBRARIES += \ + libexpat +endif + #----------------------------------------------- # Build drivers and libmesa_dri_common diff --git a/src/util/Android.mk b/src/util/Android.mk index 2d59e1ae15e..6d770ca9575 100644 --- a/src/util/Android.mk +++ b/src/util/Android.mk @@ -41,8 +41,14 @@ LOCAL_C_INCLUDES := \ $(MESA_TOP)/src/gallium/include \ $(MESA_TOP)/src/gallium/auxiliary +# If Android version >=8 MESA should static link libexpat else should dynamic link +ifeq ($(shell test $(PLATFORM_SDK_VERSION) -ge 27; echo $$?), 0) +LOCAL_STATIC_LIBRARIES := \ + libexpat +else LOCAL_SHARED_LIBRARIES := \ libexpat +endif LOCAL_MODULE := libmesa_util From 09fe74bbd051ba78dd5cff6872176b18432b7d81 Mon Sep 17 00:00:00 2001 From: Munish Bhardwaj Date: Sun, 1 Jul 2018 03:12:19 -0700 Subject: [PATCH 05/27] INTERNAL: Adds support for gralloc1.0. --- src/egl/Android.mk | 4 + src/egl/drivers/dri2/egl_dri2.h | 13 +- src/egl/drivers/dri2/platform_android.c | 189 +++++++++++++++++++++--- 3 files changed, 186 insertions(+), 20 deletions(-) diff --git a/src/egl/Android.mk b/src/egl/Android.mk index 8b03bd628af..b753c184ab9 100644 --- a/src/egl/Android.mk +++ b/src/egl/Android.mk @@ -71,6 +71,10 @@ ifeq ($(BOARD_USES_DRM_GRALLOC),true) LOCAL_SHARED_LIBRARIES += libgralloc_drm endif +ifeq ($(strip $(BOARD_USES_GRALLOC1)),true) +LOCAL_CFLAGS += -DHAVE_GRALLOC1 +endif + ifeq ($(filter $(MESA_ANDROID_MAJOR_VERSION), 4 5 6 7),) LOCAL_SHARED_LIBRARIES += libnativewindow endif diff --git a/src/egl/drivers/dri2/egl_dri2.h b/src/egl/drivers/dri2/egl_dri2.h index a9ddadf11b1..4e80deb2038 100644 --- a/src/egl/drivers/dri2/egl_dri2.h +++ b/src/egl/drivers/dri2/egl_dri2.h @@ -69,6 +69,10 @@ struct zwp_linux_dmabuf_v1; #include #endif /* HAVE_ANDROID_PLATFORM */ +#ifdef HAVE_GRALLOC1 +#include +#endif + #include "eglconfig.h" #include "eglcontext.h" #include "egldevice.h" @@ -238,7 +242,14 @@ struct dri2_egl_display #endif #ifdef HAVE_ANDROID_PLATFORM - const gralloc_module_t *gralloc; + const hw_module_t *gralloc; + uint16_t gralloc_version; +#ifdef HAVE_GRALLOC1 + gralloc1_device_t *gralloc1_dvc; + GRALLOC1_PFN_LOCK_FLEX pfn_lockflex; + GRALLOC1_PFN_GET_FORMAT pfn_getFormat; + GRALLOC1_PFN_UNLOCK pfn_unlock; +#endif #endif bool is_render_node; diff --git a/src/egl/drivers/dri2/platform_android.c b/src/egl/drivers/dri2/platform_android.c index 366a9ec14e9..d9489630f51 100644 --- a/src/egl/drivers/dri2/platform_android.c +++ b/src/egl/drivers/dri2/platform_android.c @@ -49,6 +49,8 @@ #define ALIGN(val, align) (((val) + (align) - 1) & ~((align) - 1)) +#define GRALLOC_DRM_GET_FORMAT 1 + struct droid_yuv_format { /* Lookup keys */ int native; /* HAL_PIXEL_FORMAT_ */ @@ -59,6 +61,14 @@ struct droid_yuv_format { int fourcc; /* __DRI_IMAGE_FOURCC_ */ }; +/* This enumeration can be deleted if Android defined it in + * system/core/include/system/graphics.h + */ +enum { + HAL_PIXEL_FORMAT_NV12_Y_TILED_INTEL = 0x100, + HAL_PIXEL_FORMAT_NV12 = 0x10F, +}; + /* The following table is used to look up a DRI image FourCC based * on native format and information contained in android_ycbcr struct. */ static const struct droid_yuv_format droid_yuv_formats[] = { @@ -67,6 +77,8 @@ static const struct droid_yuv_format droid_yuv_formats[] = { { HAL_PIXEL_FORMAT_YCbCr_420_888, 0, 1, __DRI_IMAGE_FOURCC_YUV420 }, { HAL_PIXEL_FORMAT_YCbCr_420_888, 1, 1, __DRI_IMAGE_FOURCC_YVU420 }, { HAL_PIXEL_FORMAT_YV12, 1, 1, __DRI_IMAGE_FOURCC_YVU420 }, + { HAL_PIXEL_FORMAT_NV12, 0, 2, __DRI_IMAGE_FOURCC_NV12 }, + { HAL_PIXEL_FORMAT_NV12_Y_TILED_INTEL, 0, 2, __DRI_IMAGE_FOURCC_NV12 }, /* HACK: See droid_create_image_from_prime_fd() and * https://issuetracker.google.com/32077885. */ { HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED, 0, 2, __DRI_IMAGE_FOURCC_NV12 }, @@ -249,6 +261,51 @@ droid_window_dequeue_buffer(struct dri2_egl_surface *dri2_surf) return EGL_TRUE; } +static int +droid_resolve_format(struct dri2_egl_display *dri2_dpy, + struct ANativeWindowBuffer *buf) +{ + int format = -1; + int ret; + + if (buf->format != HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED) + return buf->format; +#ifdef HAVE_GRALLOC1 + if(dri2_dpy->gralloc_version == HARDWARE_MODULE_API_VERSION(1, 0)) { + + if (!dri2_dpy->pfn_getFormat) { + _eglLog(_EGL_WARNING, "Gralloc does not support getFormat"); + return -1; + } + ret = dri2_dpy->pfn_getFormat(dri2_dpy->gralloc1_dvc, buf->handle, + &format); + if (ret) { + _eglLog(_EGL_WARNING, "gralloc->getFormat failed: %d", ret); + return -1; + } + } else { +#else + const gralloc_module_t *gralloc0; + gralloc0 = dri2_dpy->gralloc; + + if (!gralloc0->perform) { + _eglLog(_EGL_WARNING, "gralloc->perform not supported"); + return -1; + } + ret = gralloc0->perform(dri2_dpy->gralloc, + GRALLOC_DRM_GET_FORMAT, + buf->handle, &format); + if (ret){ + _eglLog(_EGL_WARNING, "gralloc->perform failed with error: %d", ret); + return -1; + } +#endif +#ifdef HAVE_GRALLOC1 + } +#endif + return format; +} + static EGLBoolean droid_window_enqueue_buffer(_EGLDisplay *disp, struct dri2_egl_surface *dri2_surf) { @@ -731,6 +788,31 @@ droid_swap_buffers(_EGLDriver *drv, _EGLDisplay *disp, _EGLSurface *draw) return EGL_TRUE; } +static int get_ycbcr_from_flexlayout(struct android_flex_layout *outFlexLayout, struct android_ycbcr *ycbcr) +{ + + for( int i = 0; i < outFlexLayout->num_planes; i++) { + switch(outFlexLayout->planes[i].component){ + case FLEX_COMPONENT_Y: + ycbcr->y = outFlexLayout->planes[i].top_left; + ycbcr->ystride = outFlexLayout->planes[i].v_increment; + break; + case FLEX_COMPONENT_Cb: + ycbcr->cb = outFlexLayout->planes[i].top_left; + ycbcr->cstride = outFlexLayout->planes[i].v_increment; + break; + case FLEX_COMPONENT_Cr: + ycbcr->cr = outFlexLayout->planes[i].top_left; + ycbcr->chroma_step = outFlexLayout->planes[i].h_increment; + break; + default: + _eglLog(_EGL_WARNING,"unknown component 0x%x", __func__, outFlexLayout->planes[i].component); + break; + } + } + return 0; +} + #if ANDROID_API_LEVEL >= 23 static EGLBoolean droid_set_damage_region(_EGLDriver *drv, @@ -774,30 +856,70 @@ droid_create_image_from_prime_fd_yuv(_EGLDisplay *disp, _EGLContext *ctx, { struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp); struct android_ycbcr ycbcr; +#ifdef HAVE_GRALLOC1 + struct android_flex_layout outFlexLayout; + gralloc1_rect_t accessRegion; +#endif size_t offsets[3]; size_t pitches[3]; int is_ycrcb; int fourcc; int ret; - if (!dri2_dpy->gralloc->lock_ycbcr) { - _eglLog(_EGL_WARNING, "Gralloc does not support lock_ycbcr"); + int format = droid_resolve_format(dri2_dpy, buf); + if (format < 0) { + _eglError(EGL_BAD_PARAMETER, "eglCreateEGLImageKHR"); return NULL; } memset(&ycbcr, 0, sizeof(ycbcr)); - ret = dri2_dpy->gralloc->lock_ycbcr(dri2_dpy->gralloc, buf->handle, - 0, 0, 0, 0, 0, &ycbcr); - if (ret) { - /* HACK: See droid_create_image_from_prime_fd() and - * https://issuetracker.google.com/32077885.*/ - if (buf->format == HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED) - return NULL; - - _eglLog(_EGL_WARNING, "gralloc->lock_ycbcr failed: %d", ret); - return NULL; - } - dri2_dpy->gralloc->unlock(dri2_dpy->gralloc, buf->handle); +#ifdef HAVE_GRALLOC1 + if(dri2_dpy->gralloc_version == HARDWARE_MODULE_API_VERSION(1, 0)) { + if (!dri2_dpy->pfn_lockflex) { + _eglLog(_EGL_WARNING, "Gralloc does not support lockflex"); + return NULL; + } + + ret = dri2_dpy->pfn_lockflex(dri2_dpy->gralloc1_dvc, buf->handle, + 0, 0, &accessRegion, &outFlexLayout, -1); + if (ret) { + _eglLog(_EGL_WARNING, "gralloc->lockflex failed: %d", ret); + return NULL; + } + ret = get_ycbcr_from_flexlayout(&outFlexLayout, &ycbcr); + if (ret) { + _eglLog(_EGL_WARNING, "gralloc->lockflex failed: %d", ret); + return NULL; + } + int outReleaseFence = 0; + dri2_dpy->pfn_unlock(dri2_dpy->gralloc1_dvc, buf->handle, &outReleaseFence); + } else { +#endif + const gralloc_module_t *gralloc0; + gralloc0 = dri2_dpy->gralloc; + + if (!gralloc0->lock_ycbcr) { + _eglLog(_EGL_WARNING, "Gralloc does not support lock_ycbcr"); + return NULL; + } + + ret = gralloc0->lock_ycbcr(gralloc0, buf->handle, + 0, 0, 0, 0, 0, &ycbcr); + + if (ret) { + /* HACK: See droid_create_image_from_prime_fd() and + * https://issuetracker.google.com/32077885.*/ + if (buf->format == HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED) + return NULL; + + _eglLog(_EGL_WARNING, "gralloc->lock_ycbcr failed: %d", ret); + return NULL; + } + + gralloc0->unlock(dri2_dpy->gralloc, buf->handle); +#ifdef HAVE_GRALLOC1 + } +#endif /* When lock_ycbcr's usage argument contains no SW_READ/WRITE flags * it will return the .y/.cb/.cr pointers based on a NULL pointer, @@ -822,10 +944,10 @@ droid_create_image_from_prime_fd_yuv(_EGLDisplay *disp, _EGLContext *ctx, /* .chroma_step is the byte distance between the same chroma channel * values of subsequent pixels, assumed to be the same for Cb and Cr. */ - fourcc = get_fourcc_yuv(buf->format, is_ycrcb, ycbcr.chroma_step); + fourcc = get_fourcc_yuv(format, is_ycrcb, ycbcr.chroma_step); if (fourcc == -1) { _eglLog(_EGL_WARNING, "unsupported YUV format, native = %x, is_ycrcb = %d, chroma_step = %d", - buf->format, is_ycrcb, ycbcr.chroma_step); + format, is_ycrcb, ycbcr.chroma_step); return NULL; } @@ -871,9 +993,16 @@ static _EGLImage * droid_create_image_from_prime_fd(_EGLDisplay *disp, _EGLContext *ctx, struct ANativeWindowBuffer *buf, int fd) { + struct dri2_egl_display *dri2_dpy = dri2_egl_display(disp); unsigned int pitch; - if (is_yuv(buf->format)) { + int format = droid_resolve_format(dri2_dpy, buf); + if (format < 0) { + _eglLog(_EGL_WARNING, "Could not resolve buffer format"); + return NULL; + } + + if (is_yuv(format)) { _EGLImage *image; image = droid_create_image_from_prime_fd_yuv(disp, ctx, buf, fd); @@ -888,13 +1017,13 @@ droid_create_image_from_prime_fd(_EGLDisplay *disp, _EGLContext *ctx, return image; } - const int fourcc = get_fourcc(buf->format); + const int fourcc = get_fourcc(format); if (fourcc == -1) { _eglError(EGL_BAD_PARAMETER, "eglCreateEGLImageKHR"); return NULL; } - pitch = buf->stride * get_format_bpp(buf->format); + pitch = buf->stride * get_format_bpp(format); if (pitch == 0) { _eglError(EGL_BAD_PARAMETER, "eglCreateEGLImageKHR"); return NULL; @@ -1530,6 +1659,7 @@ dri2_initialize_android(_EGLDriver *drv, _EGLDisplay *disp) _EGLDevice *dev; struct dri2_egl_display *dri2_dpy; const char *err; + hw_device_t *device; int ret; /* Not supported yet */ @@ -1547,6 +1677,27 @@ dri2_initialize_android(_EGLDriver *drv, _EGLDisplay *disp) err = "DRI2: failed to get gralloc module"; goto cleanup; } + dri2_dpy->gralloc_version = dri2_dpy->gralloc->module_api_version; +#ifdef HAVE_GRALLOC1 + if (dri2_dpy->gralloc_version == HARDWARE_MODULE_API_VERSION(1, 0)) { + ret = dri2_dpy->gralloc->methods->open(dri2_dpy->gralloc, GRALLOC_HARDWARE_MODULE_ID, &device); + if (ret) { + err = "Failed to open hw_device device"; + goto cleanup; + } else { + dri2_dpy->gralloc1_dvc = (gralloc1_device_t *)device; + + dri2_dpy->pfn_lockflex = (GRALLOC1_PFN_LOCK_FLEX)\ + dri2_dpy->gralloc1_dvc->getFunction(dri2_dpy->gralloc1_dvc, GRALLOC1_FUNCTION_LOCK_FLEX); + + dri2_dpy->pfn_getFormat = (GRALLOC1_PFN_GET_FORMAT)\ + dri2_dpy->gralloc1_dvc->getFunction(dri2_dpy->gralloc1_dvc, GRALLOC1_FUNCTION_GET_FORMAT); + + dri2_dpy->pfn_unlock = (GRALLOC1_PFN_UNLOCK)\ + dri2_dpy->gralloc1_dvc->getFunction(dri2_dpy->gralloc1_dvc, GRALLOC1_FUNCTION_UNLOCK); + } + } +#endif disp->DriverData = (void *) dri2_dpy; From 4252199fe82e16a7df7174a09f9f6ba667188df8 Mon Sep 17 00:00:00 2001 From: "jenny.q.cao" Date: Tue, 29 May 2018 17:51:59 -0700 Subject: [PATCH 06/27] INTERNAL: ignore some compile warning on android. Signed-off-by: Qiming Shi Signed-off-by: Mingwei Wang Signed-off-by: jenny.q.cao Signed-off-by: Kishore Kadiyala Signed-off-by: Chen Lin Z --- Android.common.mk | 13 +++++++++++-- src/compiler/Android.glsl.mk | 2 +- src/compiler/Android.nir.mk | 3 +++ src/egl/Android.mk | 2 +- src/intel/Android.compiler.mk | 2 +- src/intel/Android.dev.mk | 3 +++ src/intel/Android.vulkan.mk | 2 +- src/mesa/drivers/dri/i965/Android.mk | 2 ++ src/mesa/program/Android.mk | 2 +- 9 files changed, 24 insertions(+), 7 deletions(-) diff --git a/Android.common.mk b/Android.common.mk index 60459d16eba..5a8277ada35 100644 --- a/Android.common.mk +++ b/Android.common.mk @@ -77,14 +77,23 @@ LOCAL_CFLAGS += \ -fvisibility=hidden \ -fno-math-errno \ -fno-trapping-math \ - -Wno-sign-compare + -Wno-sign-compare \ + -Wno-self-assign \ + -Wno-constant-logical-operand \ + -Wno-format \ + -Wno-incompatible-pointer-types \ + -Wno-enum-conversion LOCAL_CPPFLAGS += \ -D__STDC_CONSTANT_MACROS \ -D__STDC_FORMAT_MACROS \ -D__STDC_LIMIT_MACROS \ -Wno-error=non-virtual-dtor \ - -Wno-non-virtual-dtor + -Wno-non-virtual-dtor \ + -Wno-delete-non-virtual-dtor \ + -Wno-overloaded-virtual \ + -Wno-missing-braces \ + -Wno-deprecated-register # mesa requires at least c99 compiler LOCAL_CONLYFLAGS += \ diff --git a/src/compiler/Android.glsl.mk b/src/compiler/Android.glsl.mk index 0aabafa2673..37b3cb80251 100644 --- a/src/compiler/Android.glsl.mk +++ b/src/compiler/Android.glsl.mk @@ -48,7 +48,7 @@ LOCAL_STATIC_LIBRARIES := \ libmesa_nir LOCAL_MODULE := libmesa_glsl - +LOCAL_CFLAGS += -Wno-error include $(LOCAL_PATH)/Android.glsl.gen.mk include $(MESA_COMMON_MK) include $(BUILD_STATIC_LIBRARY) diff --git a/src/compiler/Android.nir.mk b/src/compiler/Android.nir.mk index 75a247a245d..59da5dbdc1c 100644 --- a/src/compiler/Android.nir.mk +++ b/src/compiler/Android.nir.mk @@ -41,6 +41,9 @@ LOCAL_C_INCLUDES := \ $(MESA_TOP)/src/gallium/include \ $(MESA_TOP)/src/gallium/auxiliary +LOCAL_CFLAGS := \ + -Wno-missing-braces + LOCAL_STATIC_LIBRARIES := libmesa_compiler LOCAL_MODULE := libmesa_nir diff --git a/src/egl/Android.mk b/src/egl/Android.mk index b753c184ab9..3c7f1366e34 100644 --- a/src/egl/Android.mk +++ b/src/egl/Android.mk @@ -92,6 +92,6 @@ endif LOCAL_MODULE := libGLES_mesa LOCAL_MODULE_RELATIVE_PATH := egl - +LOCAL_CFLAGS += -Wno-error include $(MESA_COMMON_MK) include $(BUILD_SHARED_LIBRARY) diff --git a/src/intel/Android.compiler.mk b/src/intel/Android.compiler.mk index c2b01221dfc..41af7b20b9c 100644 --- a/src/intel/Android.compiler.mk +++ b/src/intel/Android.compiler.mk @@ -28,7 +28,7 @@ # --------------------------------------- include $(CLEAR_VARS) - +LOCAL_CFLAGS += -Wno-error LOCAL_MODULE := libmesa_intel_compiler LOCAL_MODULE_CLASS := STATIC_LIBRARIES diff --git a/src/intel/Android.dev.mk b/src/intel/Android.dev.mk index cd2ed66a176..3011ee232ed 100644 --- a/src/intel/Android.dev.mk +++ b/src/intel/Android.dev.mk @@ -33,5 +33,8 @@ LOCAL_C_INCLUDES := $(MESA_TOP)/include/drm-uapi LOCAL_SRC_FILES := $(DEV_FILES) +LOCAL_CFLAGS := \ + -Wno-gnu-variable-sized-type-not-at-end + include $(MESA_COMMON_MK) include $(BUILD_STATIC_LIBRARY) diff --git a/src/intel/Android.vulkan.mk b/src/intel/Android.vulkan.mk index 0f00c586473..279a673de73 100644 --- a/src/intel/Android.vulkan.mk +++ b/src/intel/Android.vulkan.mk @@ -240,7 +240,7 @@ include $(BUILD_STATIC_LIBRARY) include $(CLEAR_VARS) LOCAL_MODULE := libmesa_vulkan_common LOCAL_MODULE_CLASS := STATIC_LIBRARIES - +LOCAL_CFLAGS += -Wno-error intermediates := $(call local-generated-sources-dir) LOCAL_SRC_FILES := $(VULKAN_FILES) diff --git a/src/mesa/drivers/dri/i965/Android.mk b/src/mesa/drivers/dri/i965/Android.mk index 1574c8834c9..97def8f03fe 100644 --- a/src/mesa/drivers/dri/i965/Android.mk +++ b/src/mesa/drivers/dri/i965/Android.mk @@ -274,6 +274,8 @@ LOCAL_LDFLAGS += $(MESA_DRI_LDFLAGS) LOCAL_CFLAGS := \ $(MESA_DRI_CFLAGS) +LOCAL_CFLAGS += -Wno-error + LOCAL_C_INCLUDES := \ $(MESA_DRI_C_INCLUDES) \ $(call generated-sources-dir-for,STATIC_LIBRARIES,libmesa_glsl,,) \ diff --git a/src/mesa/program/Android.mk b/src/mesa/program/Android.mk index c6470e6289e..13d0da85882 100644 --- a/src/mesa/program/Android.mk +++ b/src/mesa/program/Android.mk @@ -41,7 +41,7 @@ endef include $(MESA_TOP)/src/mesa/Makefile.sources include $(CLEAR_VARS) - +LOCAL_CFLAGS += -Wno-error LOCAL_MODULE := libmesa_program LOCAL_MODULE_CLASS := STATIC_LIBRARIES LOCAL_STATIC_LIBRARIES := libmesa_nir \ From dcc18d17b17c5ce1b4cd6dbbbf0dedd6ac74b988 Mon Sep 17 00:00:00 2001 From: Yogesh Marathe Date: Fri, 8 Dec 2017 13:02:39 -0800 Subject: [PATCH 07/27] INTERNAL: enable O3 for Mesa compilation. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Improves performance of graphics tests significantly. Signed-off-by: Yogesh Marathe Acked-by: Tapani Pälli --- Android.common.mk | 1 + 1 file changed, 1 insertion(+) diff --git a/Android.common.mk b/Android.common.mk index 5a8277ada35..8e9e10a238d 100644 --- a/Android.common.mk +++ b/Android.common.mk @@ -31,6 +31,7 @@ LOCAL_C_INCLUDES += \ MESA_VERSION := $(shell cat $(MESA_TOP)/VERSION) LOCAL_CFLAGS += \ + -O3 \ -Wno-error \ -Wno-unused-parameter \ -Wno-pointer-arith \ From 9b02fdd680d03912eb4faef055f8b2156655efd8 Mon Sep 17 00:00:00 2001 From: Kevin Strasser Date: Wed, 22 Mar 2017 03:38:07 -0700 Subject: [PATCH 08/27] INTERNAL: Enable sampling for imported dma_buf images MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The HWC Vulkan backend needs to be able to sample from source images, so for now enable that for all users of vkCreateDmaBufImageINTEL. We can revert this patch once we land support for VK_MESAX_external_image_dma_buf, which allows the application to fill the 'usage' field. Jira: IAHWC-40 Test: Enable Vulkan backend of IA-Hardware-Composer and try kmscube. The cube should be visible and animated, but at this time there is severe flickering. Signed-off-by: Kevin Strasser Acked-by: Tapani Pälli --- src/intel/vulkan/anv_intel.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_intel.c b/src/intel/vulkan/anv_intel.c index 08bff9585bc..f6b9584b410 100644 --- a/src/intel/vulkan/anv_intel.c +++ b/src/intel/vulkan/anv_intel.c @@ -64,7 +64,8 @@ VkResult anv_CreateDmaBufImageINTEL( .samples = 1, /* FIXME: Need a way to use X tiling to allow scanout */ .tiling = VK_IMAGE_TILING_OPTIMAL, - .usage = VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT, + .usage = VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT | + VK_IMAGE_USAGE_SAMPLED_BIT, .flags = 0, }}, pAllocator, &image_h); From bf741e0f4053f9490e8afb4adaab340057a56333 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Tapani=20P=C3=A4lli?= Date: Mon, 11 Feb 2019 09:25:18 +0200 Subject: [PATCH 09/27] UPSTREAM: SQUASH: Add P0x formats MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit UPSTREAM: nir: add option to use scaling factor when sampling planes YUV lowering Patch adds nir_lower_tex_options as parameter to sample_plane so that we don't need to extend nir_tex_instr for this. Signed-off-by: Tapani Pälli Reviewed-by: Lionel Landwerlin Reviewed-by: Jason Ekstrand (cherry picked from commit 19a85a704bb163c80e9c87aa5a03da1e6574a8dd) UPSTREAM: dri: add P010, P012, P016 for 10bit/12bit/16bit YUV420 formats Signed-off-by: Tapani Pälli Signed-off-by: Lin Johnson Reviewed-by: Lionel Landwerlin (cherry picked from commit 722f96bfc83b7ab2981756e5d887d0dc8ee1b4f0) UPSTREAM: intel/compiler: add scale_factors to sampler_prog_key_data Patch propagates given scale_factors to lowering options. Signed-off-by: Tapani Pälli Reviewed-by: Lionel Landwerlin Reviewed-by: Jason Ekstrand (cherry picked from commit 3da858a6b990c51615067df42d1fdc203bbe8ed5) UPSTREAM: i965: add P0x formats and propagate required scaling factors Signed-off-by: Tapani Pälli Signed-off-by: Lin Johnson Reviewed-by: Lionel Landwerlin (cherry picked from commit 2a2e69f975bd791d64a88553d5b1d5eda7e8abdf) UPSTREAM: i965: remove scaling factors from P010, P012 Patch removes scaling factors introduced in 2a2e69f975b but leaves option to use scaling in place as it could be useful with other upcoming YUV formats. We did this scaling because ffmpeg was shifting channel bits down, however it seems this is not the right place as compositor wants to flip same buffers directly to display as well and therefore bitshifting needs to be done by the client when receiving frame from ffmpeg. Now P0x formats are treated the same, e.g. P010 is same as P016 but with lower 6 bits set to zeros. Fixes: 2a2e69f975b "i965: add P0x formats and propagate required scaling factors" Signed-off-by: Tapani Pälli Reviewed-by: Lionel Landwerlin (cherry picked from commit 3b41175c22e14775656e13d11ca84cad83837b04) --- include/GL/internal/dri_interface.h | 4 ++ src/compiler/nir/nir.h | 3 ++ src/compiler/nir/nir_lower_tex.c | 53 ++++++++++++++---------- src/egl/drivers/dri2/egl_dri2.c | 17 ++++++++ src/intel/compiler/brw_compiler.h | 3 ++ src/intel/compiler/brw_nir.c | 4 ++ src/mesa/drivers/dri/i965/brw_wm.c | 5 +++ src/mesa/drivers/dri/i965/intel_image.h | 1 + src/mesa/drivers/dri/i965/intel_screen.c | 12 ++++++ 9 files changed, 81 insertions(+), 21 deletions(-) diff --git a/include/GL/internal/dri_interface.h b/include/GL/internal/dri_interface.h index f2e46f65f92..6d134e3a40f 100644 --- a/include/GL/internal/dri_interface.h +++ b/include/GL/internal/dri_interface.h @@ -1352,6 +1352,10 @@ struct __DRIdri2ExtensionRec { #define __DRI_IMAGE_FOURCC_YVU422 0x36315659 #define __DRI_IMAGE_FOURCC_YVU444 0x34325659 +#define __DRI_IMAGE_FOURCC_P010 0x30313050 +#define __DRI_IMAGE_FOURCC_P012 0x32313050 +#define __DRI_IMAGE_FOURCC_P016 0x36313050 + /** * Queryable on images created by createImageFromNames. * diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index 4aedd6e4602..c43226ba8df 100644 --- a/src/compiler/nir/nir.h +++ b/src/compiler/nir/nir.h @@ -3101,6 +3101,9 @@ typedef struct nir_lower_tex_options { */ uint8_t swizzles[32][4]; + /* Can be used to scale sampled values in range required by the format. */ + float scale_factors[32]; + /** * Bitmap of textures that need srgb to linear conversion. If * (lower_srgb & (1 << texture_index)) then the rgb (xyz) components diff --git a/src/compiler/nir/nir_lower_tex.c b/src/compiler/nir/nir_lower_tex.c index eedcc6b7b12..11afffe3dee 100644 --- a/src/compiler/nir/nir_lower_tex.c +++ b/src/compiler/nir/nir_lower_tex.c @@ -306,7 +306,8 @@ lower_implicit_lod(nir_builder *b, nir_tex_instr *tex) } static nir_ssa_def * -sample_plane(nir_builder *b, nir_tex_instr *tex, int plane) +sample_plane(nir_builder *b, nir_tex_instr *tex, int plane, + const nir_lower_tex_options *options) { assert(tex->dest.is_ssa); assert(nir_tex_instr_dest_size(tex) == 4); @@ -334,6 +335,11 @@ sample_plane(nir_builder *b, nir_tex_instr *tex, int plane) nir_builder_instr_insert(b, &plane_tex->instr); + /* If scaling_factor is set, return a scaled value. */ + if (options->scale_factors[tex->texture_index]) + return nir_fmul_imm(b, &plane_tex->dest.ssa, + options->scale_factors[tex->texture_index]); + return &plane_tex->dest.ssa; } @@ -366,12 +372,13 @@ convert_yuv_to_rgb(nir_builder *b, nir_tex_instr *tex, } static void -lower_y_uv_external(nir_builder *b, nir_tex_instr *tex) +lower_y_uv_external(nir_builder *b, nir_tex_instr *tex, + const nir_lower_tex_options *options) { b->cursor = nir_after_instr(&tex->instr); - nir_ssa_def *y = sample_plane(b, tex, 0); - nir_ssa_def *uv = sample_plane(b, tex, 1); + nir_ssa_def *y = sample_plane(b, tex, 0, options); + nir_ssa_def *uv = sample_plane(b, tex, 1, options); convert_yuv_to_rgb(b, tex, nir_channel(b, y, 0), @@ -381,13 +388,14 @@ lower_y_uv_external(nir_builder *b, nir_tex_instr *tex) } static void -lower_y_u_v_external(nir_builder *b, nir_tex_instr *tex) +lower_y_u_v_external(nir_builder *b, nir_tex_instr *tex, + const nir_lower_tex_options *options) { b->cursor = nir_after_instr(&tex->instr); - nir_ssa_def *y = sample_plane(b, tex, 0); - nir_ssa_def *u = sample_plane(b, tex, 1); - nir_ssa_def *v = sample_plane(b, tex, 2); + nir_ssa_def *y = sample_plane(b, tex, 0, options); + nir_ssa_def *u = sample_plane(b, tex, 1, options); + nir_ssa_def *v = sample_plane(b, tex, 2, options); convert_yuv_to_rgb(b, tex, nir_channel(b, y, 0), @@ -397,12 +405,13 @@ lower_y_u_v_external(nir_builder *b, nir_tex_instr *tex) } static void -lower_yx_xuxv_external(nir_builder *b, nir_tex_instr *tex) +lower_yx_xuxv_external(nir_builder *b, nir_tex_instr *tex, + const nir_lower_tex_options *options) { b->cursor = nir_after_instr(&tex->instr); - nir_ssa_def *y = sample_plane(b, tex, 0); - nir_ssa_def *xuxv = sample_plane(b, tex, 1); + nir_ssa_def *y = sample_plane(b, tex, 0, options); + nir_ssa_def *xuxv = sample_plane(b, tex, 1, options); convert_yuv_to_rgb(b, tex, nir_channel(b, y, 0), @@ -412,12 +421,13 @@ lower_yx_xuxv_external(nir_builder *b, nir_tex_instr *tex) } static void -lower_xy_uxvx_external(nir_builder *b, nir_tex_instr *tex) +lower_xy_uxvx_external(nir_builder *b, nir_tex_instr *tex, + const nir_lower_tex_options *options) { b->cursor = nir_after_instr(&tex->instr); - nir_ssa_def *y = sample_plane(b, tex, 0); - nir_ssa_def *uxvx = sample_plane(b, tex, 1); + nir_ssa_def *y = sample_plane(b, tex, 0, options); + nir_ssa_def *uxvx = sample_plane(b, tex, 1, options); convert_yuv_to_rgb(b, tex, nir_channel(b, y, 1), @@ -427,11 +437,12 @@ lower_xy_uxvx_external(nir_builder *b, nir_tex_instr *tex) } static void -lower_ayuv_external(nir_builder *b, nir_tex_instr *tex) +lower_ayuv_external(nir_builder *b, nir_tex_instr *tex, + const nir_lower_tex_options *options) { b->cursor = nir_after_instr(&tex->instr); - nir_ssa_def *ayuv = sample_plane(b, tex, 0); + nir_ssa_def *ayuv = sample_plane(b, tex, 0, options); convert_yuv_to_rgb(b, tex, nir_channel(b, ayuv, 2), @@ -942,27 +953,27 @@ nir_lower_tex_block(nir_block *block, nir_builder *b, } if ((1 << tex->texture_index) & options->lower_y_uv_external) { - lower_y_uv_external(b, tex); + lower_y_uv_external(b, tex, options); progress = true; } if ((1 << tex->texture_index) & options->lower_y_u_v_external) { - lower_y_u_v_external(b, tex); + lower_y_u_v_external(b, tex, options); progress = true; } if ((1 << tex->texture_index) & options->lower_yx_xuxv_external) { - lower_yx_xuxv_external(b, tex); + lower_yx_xuxv_external(b, tex, options); progress = true; } if ((1 << tex->texture_index) & options->lower_xy_uxvx_external) { - lower_xy_uxvx_external(b, tex); + lower_xy_uxvx_external(b, tex, options); progress = true; } if ((1 << tex->texture_index) & options->lower_ayuv_external) { - lower_ayuv_external(b, tex); + lower_ayuv_external(b, tex, options); progress = true; } diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c index 645d7257406..ca26e34daa3 100644 --- a/src/egl/drivers/dri2/egl_dri2.c +++ b/src/egl/drivers/dri2/egl_dri2.c @@ -66,6 +66,20 @@ #include "util/u_vector.h" #include "mapi/glapi/glapi.h" +/* Additional definitions not yet in the drm_fourcc.h. + */ +#ifndef DRM_FORMAT_P010 +#define DRM_FORMAT_P010 fourcc_code('P', '0', '1', '0') /* 2x2 subsampled Cb:Cr plane 10 bits per channel */ +#endif + +#ifndef DRM_FORMAT_P012 +#define DRM_FORMAT_P012 fourcc_code('P', '0', '1', '2') /* 2x2 subsampled Cb:Cr plane 12 bits per channel */ +#endif + +#ifndef DRM_FORMAT_P016 +#define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cb:Cr plane 16 bits per channel */ +#endif + #define NUM_ATTRIBS 12 static void @@ -2264,6 +2278,9 @@ dri2_num_fourcc_format_planes(EGLint format) case DRM_FORMAT_NV21: case DRM_FORMAT_NV16: case DRM_FORMAT_NV61: + case DRM_FORMAT_P010: + case DRM_FORMAT_P012: + case DRM_FORMAT_P016: return 2; case DRM_FORMAT_YUV410: diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h index 61a4528d372..560f2c3c6ba 100644 --- a/src/intel/compiler/brw_compiler.h +++ b/src/intel/compiler/brw_compiler.h @@ -196,6 +196,9 @@ struct brw_sampler_prog_key_data { uint32_t yx_xuxv_image_mask; uint32_t xy_uxvx_image_mask; uint32_t ayuv_image_mask; + + /* Scale factor for each texture. */ + float scale_factors[32]; }; /** diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index ca3d038b5b3..30c3f19fb4a 100644 --- a/src/intel/compiler/brw_nir.c +++ b/src/intel/compiler/brw_nir.c @@ -981,6 +981,10 @@ brw_nir_apply_sampler_key(nir_shader *nir, tex_options.lower_xy_uxvx_external = key_tex->xy_uxvx_image_mask; tex_options.lower_ayuv_external = key_tex->ayuv_image_mask; + /* Setup array of scaling factors for each texture. */ + memcpy(&tex_options.scale_factors, &key_tex->scale_factors, + sizeof(tex_options.scale_factors)); + if (nir_lower_tex(nir, &tex_options)) { nir_validate_shader(nir, "after nir_lower_tex"); nir = brw_nir_optimize(nir, compiler, is_scalar, false); diff --git a/src/mesa/drivers/dri/i965/brw_wm.c b/src/mesa/drivers/dri/i965/brw_wm.c index 7bbb6166344..9f88d625d63 100644 --- a/src/mesa/drivers/dri/i965/brw_wm.c +++ b/src/mesa/drivers/dri/i965/brw_wm.c @@ -309,6 +309,7 @@ brw_populate_sampler_prog_key_data(struct gl_context *ctx, const int s = u_bit_scan(&mask); key->swizzles[s] = SWIZZLE_NOOP; + key->scale_factors[s] = 0.0f; int unit_id = prog->SamplerUnits[s]; const struct gl_texture_unit *unit = &ctx->Texture.Unit[unit_id]; @@ -406,6 +407,10 @@ brw_populate_sampler_prog_key_data(struct gl_context *ctx, } if (t->Target == GL_TEXTURE_EXTERNAL_OES && intel_tex->planar_format) { + + /* Setup possible scaling factor. */ + key->scale_factors[s] = intel_tex->planar_format->scaling_factor; + switch (intel_tex->planar_format->components) { case __DRI_IMAGE_COMPONENTS_Y_UV: key->y_uv_image_mask |= 1 << s; diff --git a/src/mesa/drivers/dri/i965/intel_image.h b/src/mesa/drivers/dri/i965/intel_image.h index ca604159dc2..4ab8a49b8bb 100644 --- a/src/mesa/drivers/dri/i965/intel_image.h +++ b/src/mesa/drivers/dri/i965/intel_image.h @@ -62,6 +62,7 @@ struct intel_image_format { uint32_t dri_format; int cpp; } planes[3]; + float scaling_factor; }; struct __DRIimageRec { diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index 8838f977bb6..34c8f22abc3 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++ b/src/mesa/drivers/dri/i965/intel_screen.c @@ -282,6 +282,18 @@ static const struct intel_image_format intel_image_formats[] = { { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 1, 1, __DRI_IMAGE_FORMAT_GR88, 2 } } }, + { __DRI_IMAGE_FOURCC_P010, __DRI_IMAGE_COMPONENTS_Y_UV, 2, + { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 2 }, + { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616, 4 } } }, + + { __DRI_IMAGE_FOURCC_P012, __DRI_IMAGE_COMPONENTS_Y_UV, 2, + { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 2 }, + { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616, 4 } } }, + + { __DRI_IMAGE_FOURCC_P016, __DRI_IMAGE_COMPONENTS_Y_UV, 2, + { { 0, 0, 0, __DRI_IMAGE_FORMAT_R16, 2 }, + { 1, 1, 1, __DRI_IMAGE_FORMAT_GR1616, 4 } } }, + { __DRI_IMAGE_FOURCC_NV16, __DRI_IMAGE_COMPONENTS_Y_UV, 2, { { 0, 0, 0, __DRI_IMAGE_FORMAT_R8, 1 }, { 1, 1, 0, __DRI_IMAGE_FORMAT_GR88, 2 } } }, From 6fd71fa5390cef5f48205279cd4e35341cd3c9f2 Mon Sep 17 00:00:00 2001 From: Lin Johnson Date: Sun, 15 Oct 2017 00:09:09 +0800 Subject: [PATCH 10/27] INTERNAL: Add format P010 etc for 10bit/12bit/16bit YUV420 formats Add those definition in dri2_interface.h and in intel_screen.c This will make P010 formats be sampleable in OpenGL Signed-off-by: Lin Johnson [strassek: Paired down as much of the patch has gone upstream] Signed-off-by: Kevin Strasser --- src/egl/drivers/dri2/platform_android.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/egl/drivers/dri2/platform_android.c b/src/egl/drivers/dri2/platform_android.c index d9489630f51..8ad3d444715 100644 --- a/src/egl/drivers/dri2/platform_android.c +++ b/src/egl/drivers/dri2/platform_android.c @@ -67,6 +67,7 @@ struct droid_yuv_format { enum { HAL_PIXEL_FORMAT_NV12_Y_TILED_INTEL = 0x100, HAL_PIXEL_FORMAT_NV12 = 0x10F, + HAL_PIXEL_FORMAT_P010_INTEL = 0x110 }; /* The following table is used to look up a DRI image FourCC based @@ -74,6 +75,7 @@ enum { static const struct droid_yuv_format droid_yuv_formats[] = { /* Native format, YCrCb, Chroma step, DRI image FourCC */ { HAL_PIXEL_FORMAT_YCbCr_420_888, 0, 2, __DRI_IMAGE_FOURCC_NV12 }, + { HAL_PIXEL_FORMAT_P010_INTEL, 0, 4, __DRI_IMAGE_FOURCC_P010 }, { HAL_PIXEL_FORMAT_YCbCr_420_888, 0, 1, __DRI_IMAGE_FOURCC_YUV420 }, { HAL_PIXEL_FORMAT_YCbCr_420_888, 1, 1, __DRI_IMAGE_FOURCC_YVU420 }, { HAL_PIXEL_FORMAT_YV12, 1, 1, __DRI_IMAGE_FOURCC_YVU420 }, @@ -951,7 +953,8 @@ droid_create_image_from_prime_fd_yuv(_EGLDisplay *disp, _EGLContext *ctx, return NULL; } - if (ycbcr.chroma_step == 2) { + /* FIXME? we should not rely on chroma_step */ + if (ycbcr.chroma_step == 2 || ycbcr.chroma_step == 4) { /* Semi-planar Y + CbCr or Y + CrCb format. */ const EGLint attr_list_2plane[] = { EGL_WIDTH, buf->width, From da1eacc523cb2d165af37d382a98206348c5fb05 Mon Sep 17 00:00:00 2001 From: Kalyan Kondapally Date: Sat, 3 Feb 2018 17:51:04 -0800 Subject: [PATCH 11/27] INTERNAL: Relax permissions when we export prime handle for GEM. This is needed in case we want to use mmap with dma-buf and write into the buffer in CPU side. This is useful when layers are rendered using software and we will either need to scan or texture from these layers. Check: https://patchwork.freedesktop.org/patch/56380/ Signed-off-by: Kalyan Kondapally --- src/mesa/drivers/dri/i965/brw_bufmgr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c b/src/mesa/drivers/dri/i965/brw_bufmgr.c index d891a9f4332..43077e60da4 100644 --- a/src/mesa/drivers/dri/i965/brw_bufmgr.c +++ b/src/mesa/drivers/dri/i965/brw_bufmgr.c @@ -1489,7 +1489,7 @@ brw_bo_gem_export_to_prime(struct brw_bo *bo, int *prime_fd) brw_bo_make_external(bo); if (drmPrimeHandleToFD(bufmgr->fd, bo->gem_handle, - DRM_CLOEXEC, prime_fd) != 0) + DRM_CLOEXEC | DRM_RDWR, prime_fd) != 0) return -errno; bo->reusable = false; From 5ce51002ea8c23ded2d986aa5ea444605036e737 Mon Sep 17 00:00:00 2001 From: Iosif Antochi Date: Wed, 14 Jun 2017 14:49:55 +0100 Subject: [PATCH 12/27] INTERNAL: CHROMIUM: egl: automatically call eglReleaseThread on thread termination EGL thread cleanup conformance tests could run out of memory as the contexts were not freed even though the application requested to have them deleted. This was caused by the fact that the contexts were still current on their threads when delete was called and (in order not to block any potential pending renders) they were just marked for delete. Fix this by calling eglReleaseThread on thread termination. This is safe to do even if this was already called by the application since, according to the EGL 1.5 spec, eglReleaseThread can be called multiple times without error. Fixes: dEQP-EGL.functional.thread_cleanup.multi_context_* dEQP-EGL.functional.robustness.create_context.query_robust_access --- src/egl/main/eglcurrent.c | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/src/egl/main/eglcurrent.c b/src/egl/main/eglcurrent.c index 479f231fb8f..d20ec64e654 100644 --- a/src/egl/main/eglcurrent.c +++ b/src/egl/main/eglcurrent.c @@ -137,13 +137,37 @@ _eglDestroyThreadInfo(_EGLThreadInfo *t) } +/** + * Delete/free a _EGLThreadInfo object. + */ +static void +_eglDestroyThreadInfoCallback(_EGLThreadInfo *t) +{ + /* If this callback is called on thread termination then try to also give a + * chance to cleanup to the client drivers. If called for module termination + * then just release the thread information as calling eglReleaseThread + * would result in a deadlock. + */ + if (_egl_TSDInitialized) { + /* The callback handler has replaced the TLS entry, which is passed in as + * 't', with NULL. Restore it here so that the release thread finds it in + * the TLS entry. + */ + _eglSetTSD(t); + eglReleaseThread(); + } else { + _eglDestroyThreadInfo(t); + } +} + + /** * Make sure TSD is initialized and return current value. */ static inline _EGLThreadInfo * _eglCheckedGetTSD(void) { - if (_eglInitTSD(&_eglDestroyThreadInfo) != EGL_TRUE) { + if (_eglInitTSD(&_eglDestroyThreadInfoCallback) != EGL_TRUE) { _eglLog(_EGL_FATAL, "failed to initialize \"current\" system"); return NULL; } From 28e27d42df0f43668a9596779d280d1885747d69 Mon Sep 17 00:00:00 2001 From: Min He Date: Wed, 18 Apr 2018 10:34:50 +0800 Subject: [PATCH 13/27] INTERNAL: prevent deadlock in droid_query_buffer_age To avoid blocking other EGL calls, release the display mutex before calling update_buffers(), which will call droid_window_dequeue_buffer(). This patch fixes some failure cases in android graphics cts test. Signed-off-by: Min He Signed-off-by: Chenglei Ren --- src/egl/drivers/dri2/platform_android.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/egl/drivers/dri2/platform_android.c b/src/egl/drivers/dri2/platform_android.c index 8ad3d444715..f12d0b1ab14 100644 --- a/src/egl/drivers/dri2/platform_android.c +++ b/src/egl/drivers/dri2/platform_android.c @@ -723,11 +723,18 @@ droid_query_buffer_age(_EGLDriver *drv, { struct dri2_egl_surface *dri2_surf = dri2_egl_surface(surface); + /* To avoid blocking other EGL calls, release the display mutex before + * we enter droid_window_dequeue_buffer() and re-acquire the mutex upon + * return. + */ + mtx_unlock(&disp->Mutex); if (update_buffers(dri2_surf) < 0) { _eglError(EGL_BAD_ALLOC, "droid_query_buffer_age"); + mtx_lock(&disp->Mutex); return -1; } + mtx_lock(&disp->Mutex); return dri2_surf->back ? dri2_surf->back->age : 0; } From d5c63f6e1168cf6b97b4c40ff6458a470e04deb8 Mon Sep 17 00:00:00 2001 From: samiuddi Date: Wed, 25 Apr 2018 16:23:11 +0530 Subject: [PATCH 14/27] FROMLIST: Check if the window is non-NULL before setting swap interval. This fixes crash due to NULL window when swap interval is set for pbuffer surface. Jira: 61995 Test: CtsDisplayTestCases pass Signed-off-by: samiuddi (am from https://patchwork.freedesktop.org/patch/235697/) --- src/egl/drivers/dri2/platform_android.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/egl/drivers/dri2/platform_android.c b/src/egl/drivers/dri2/platform_android.c index f12d0b1ab14..a08723625fb 100644 --- a/src/egl/drivers/dri2/platform_android.c +++ b/src/egl/drivers/dri2/platform_android.c @@ -522,7 +522,7 @@ droid_swap_interval(_EGLDriver *drv, _EGLDisplay *dpy, struct dri2_egl_surface *dri2_surf = dri2_egl_surface(surf); struct ANativeWindow *window = dri2_surf->window; - if (window->setSwapInterval(window, interval)) + if (window && window->setSwapInterval(window, interval)) return EGL_FALSE; surf->SwapInterval = interval; From 53a093eea6e79c690642f0e52b2392b1ed99df03 Mon Sep 17 00:00:00 2001 From: Kalyan Kondapally Date: Wed, 23 May 2018 15:42:46 -0700 Subject: [PATCH 15/27] INTERNAL: Add ReadMe file. Signed-off-by: Kalyan Kondapally --- Readme.md | 2 ++ 1 file changed, 2 insertions(+) create mode 100644 Readme.md diff --git a/Readme.md b/Readme.md new file mode 100644 index 00000000000..5df295abc3a --- /dev/null +++ b/Readme.md @@ -0,0 +1,2 @@ +Any security related issues should be reported by following the instructions here: +https://01.org/security From 58001420d00a35ea6c95efd3f24e30d5c76885a3 Mon Sep 17 00:00:00 2001 From: Kenneth Graunke Date: Wed, 4 Oct 2017 10:32:26 +0300 Subject: [PATCH 16/27] INTERNAL: glcpp: Hack to handle expressions in #line directives. MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit GLSL ES 320 technically allows #line to have arbitrary expression trees rather than integer literal constants, unlike the C and C++ preprocessor. This is likely a completely unused feature that does not make sense. However, Android irritatingly mandates this useless behavior, so this patch implements a hack to try and support it. We handle a single expression: #line but we avoid handling the double expression: #line because this is an ambiguous grammar. Instead, we handle the case that wraps both in parenthesis, which is actually well defined: #line () () With this change following tests pass: dEQP-GLES3.functional.shaders.preprocessor.builtin.line_expression_vertex dEQP-GLES3.functional.shaders.preprocessor.builtin.line_expression_fragment dEQP-GLES3.functional.shaders.preprocessor.builtin.line_and_file_expression_vertex dEQP-GLES3.functional.shaders.preprocessor.builtin.line_and_file_expression_fragment Signed-off-by: Tapani Pälli Signed-off-by: Kenneth Graunke BUG=b:33352633 BUG=b:33247335 TEST=affected tests passing on CTS 7.1_r1 sentry Change-Id: I7afbbb386bd4a582e3f241014a83eaccad1d50d9 Reviewed-on: https://chromium-review.googlesource.com/427305 Tested-by: Haixia Shi Reviewed-by: Ilja H. Friedel Commit-Queue: Haixia Shi Trybot-Ready: Haixia Shi --- src/compiler/glsl/glcpp/glcpp-parse.y | 19 ++++++++++++++++--- 1 file changed, 16 insertions(+), 3 deletions(-) diff --git a/src/compiler/glsl/glcpp/glcpp-parse.y b/src/compiler/glsl/glcpp/glcpp-parse.y index 1c095cb66f9..c951d9526ac 100644 --- a/src/compiler/glsl/glcpp/glcpp-parse.y +++ b/src/compiler/glsl/glcpp/glcpp-parse.y @@ -224,10 +224,12 @@ expanded_line: glcpp_error(& @1, parser, "undefined macro %s in expression (illegal in GLES)", $2.undefined_macro); _glcpp_parser_skip_stack_change_if (parser, & @1, "elif", $2.value); } -| LINE_EXPANDED integer_constant NEWLINE { +| LINE_EXPANDED expression NEWLINE { + if (parser->is_gles && $2.undefined_macro) + glcpp_error(& @1, parser, "undefined macro %s in expression (illegal in GLES)", $2.undefined_macro); parser->has_new_line_number = 1; - parser->new_line_number = $2; - _mesa_string_buffer_printf(parser->output, "#line %" PRIiMAX "\n", $2); + parser->new_line_number = $2.value; + _mesa_string_buffer_printf(parser->output, "#line %" PRIiMAX "\n", $2.value); } | LINE_EXPANDED integer_constant integer_constant NEWLINE { parser->has_new_line_number = 1; @@ -238,6 +240,17 @@ expanded_line: "#line %" PRIiMAX " %" PRIiMAX "\n", $2, $3); } +| LINE_EXPANDED '(' expression ')' '(' expression ')' NEWLINE { + if (parser->is_gles && $3.undefined_macro) + glcpp_error(& @1, parser, "undefined macro %s in expression (illegal in GLES)", $3.undefined_macro); + if (parser->is_gles && $6.undefined_macro) + glcpp_error(& @1, parser, "undefined macro %s in expression (illegal in GLES)", $6.undefined_macro); + parser->has_new_line_number = 1; + parser->new_line_number = $3.value; + parser->has_new_source_number = 1; + parser->new_source_number = $6.value; + _mesa_string_buffer_printf(parser->output, "#line %" PRIiMAX " %" PRIiMAX "\n", $3.value, $6.value); + } ; define: From 31d0f608de9eb35403d46117c7aeafd89af880d0 Mon Sep 17 00:00:00 2001 From: Lionel Landwerlin Date: Thu, 8 Feb 2018 10:45:56 +0000 Subject: [PATCH 17/27] REVERTME: i965: perf: implement GPA's null renderer GPA requires a null renderer query which disables all rendering. This feels fairly at odds with the spirit of the INTEL_performance_query extension. Note: Considering the INTEL_blackhole_render implementation(https://www. khronos.org/registry/OpenGL/extensions/INTEL/INTEL_blackhole_render .txt, https://patchwork.freedesktop.org/series/40035/)need test case changes, and also need time to review in upstream, we keep this patch firstly for urgent project milestone. Test: Pass mdapi test_GfxDrv_DriverAcceptance test case GfxDrv_DriverAcceptanceQuery.GL_NULL_HARDWARE and has no reg issue Signed-off-by: Landwerlin, Lionel --- src/mesa/drivers/dri/i965/brw_context.h | 2 + src/mesa/drivers/dri/i965/brw_defines.h | 8 ++- .../drivers/dri/i965/brw_performance_query.c | 69 ++++++++++++++++++- 3 files changed, 77 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index ea961351f6f..7237f39d286 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -686,6 +686,7 @@ enum brw_query_kind { OA_COUNTERS, OA_COUNTERS_RAW, PIPELINE_STATS, + NULL_RENDERER, }; struct brw_perf_query_register_prog { @@ -1249,6 +1250,7 @@ struct brw_context int n_active_oa_queries; int n_active_pipeline_stats_queries; + int n_active_null_renderers; /* The number of queries depending on running OA counters which * extends beyond brw_end_perf_query() since we need to wait until diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 2729a54e144..cdfa435a1f5 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -1652,11 +1652,17 @@ enum brw_pixel_shader_coverage_mask_mode { #define GEN10_CACHE_MODE_SS 0x0e420 #define GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4) -#define INSTPM 0x20c0 +#define INSTPM 0x20c0 /* Gen6-8 */ # define INSTPM_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE (1 << 6) +# define INSTPM_GLOBAL_DEBUG_ENABLE (1 << 4) +# define INSTPM_MEDIA_INSTRUCTION_DISABLE (1 << 3) +# define INSTPM_3D_RENDERER_INSTRUCTION_DISABLE (1 << 2) +# define INSTPM_3D_STATE_INSTRUCTION_DISABLE (1 << 1) #define CS_DEBUG_MODE2 0x20d8 /* Gen9+ */ # define CSDBG2_CONSTANT_BUFFER_ADDRESS_OFFSET_DISABLE (1 << 4) +# define CSDBG2_MEDIA_INSTRUCTION_DISABLE (1 << 1) +# define CSDBG2_3D_RENDERER_INSTRUCTION_DISABLE (1 << 0) #define GEN7_RPSTAT1 0xA01C #define GEN7_RPSTAT1_CURR_GT_FREQ_SHIFT 7 diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c b/src/mesa/drivers/dri/i965/brw_performance_query.c index 10e3d024f17..85d14a83c7e 100644 --- a/src/mesa/drivers/dri/i965/brw_performance_query.c +++ b/src/mesa/drivers/dri/i965/brw_performance_query.c @@ -330,6 +330,12 @@ dump_perf_query_callback(GLuint id, void *query_void, void *brw_void) o->Active ? "Active," : (o->Ready ? "Ready," : "Pending,"), obj->pipeline_stats.bo ? "yes" : "no"); break; + case NULL_RENDERER: + DBG("%4d: %-6s %-8s NULL_RENDERER\n", + id, + o->Used ? "Dirty," : "New,", + o->Active ? "Active," : (o->Ready ? "Ready," : "Pending,")); + break; default: unreachable("Unknown query type"); break; @@ -431,6 +437,10 @@ brw_get_perf_query_info(struct gl_context *ctx, *n_active = brw->perfquery.n_active_pipeline_stats_queries; break; + case NULL_RENDERER: + *n_active = brw->perfquery.n_active_null_renderers; + break; + default: unreachable("Unknown query type"); break; @@ -1020,6 +1030,7 @@ brw_begin_perf_query(struct gl_context *ctx, struct brw_context *brw = brw_context(ctx); struct brw_perf_query_object *obj = brw_perf_query(o); const struct brw_perf_query_info *query = obj->query; + const struct gen_device_info *devinfo = &brw->screen->devinfo; /* We can assume the frontend hides mistaken attempts to Begin a * query object multiple times before its End. Similarly if an @@ -1104,7 +1115,6 @@ brw_begin_perf_query(struct gl_context *ctx, /* If the OA counters aren't already on, enable them. */ if (brw->perfquery.oa_stream_fd == -1) { __DRIscreen *screen = brw->screen->driScrnPriv; - const struct gen_device_info *devinfo = &brw->screen->devinfo; /* The period_exponent gives a sampling period as follows: * sample_period = timestamp_period * 2^(period_exponent + 1) @@ -1250,6 +1260,23 @@ brw_begin_perf_query(struct gl_context *ctx, ++brw->perfquery.n_active_pipeline_stats_queries; break; + case NULL_RENDERER: + ++brw->perfquery.n_active_null_renderers; + if (devinfo->gen >= 9) { + brw_load_register_imm32(brw, CS_DEBUG_MODE2, + REG_MASK(CSDBG2_3D_RENDERER_INSTRUCTION_DISABLE) | + CSDBG2_3D_RENDERER_INSTRUCTION_DISABLE); + } else { + brw_load_register_imm32(brw, INSTPM, + REG_MASK(INSTPM_3D_RENDERER_INSTRUCTION_DISABLE | + INSTPM_MEDIA_INSTRUCTION_DISABLE) | + INSTPM_3D_RENDERER_INSTRUCTION_DISABLE | + INSTPM_MEDIA_INSTRUCTION_DISABLE); + } + brw_emit_pipe_control_flush(brw, + PIPE_CONTROL_LRI_WRITE_IMMEDIATE); + break; + default: unreachable("Unknown query type"); break; @@ -1270,6 +1297,7 @@ brw_end_perf_query(struct gl_context *ctx, { struct brw_context *brw = brw_context(ctx); struct brw_perf_query_object *obj = brw_perf_query(o); + const struct gen_device_info *devinfo = &brw->screen->devinfo; DBG("End(%d)\n", o->Id); @@ -1312,6 +1340,21 @@ brw_end_perf_query(struct gl_context *ctx, --brw->perfquery.n_active_pipeline_stats_queries; break; + case NULL_RENDERER: + if (--brw->perfquery.n_active_null_renderers == 0) { + if (devinfo->gen >= 9) { + brw_load_register_imm32(brw, CS_DEBUG_MODE2, + REG_MASK(CSDBG2_3D_RENDERER_INSTRUCTION_DISABLE)); + } else { + brw_load_register_imm32(brw, INSTPM, + REG_MASK(INSTPM_3D_RENDERER_INSTRUCTION_DISABLE | + INSTPM_MEDIA_INSTRUCTION_DISABLE)); + } + brw_emit_pipe_control_flush(brw, + PIPE_CONTROL_LRI_WRITE_IMMEDIATE); + } + break; + default: unreachable("Unknown query type"); break; @@ -1337,6 +1380,9 @@ brw_wait_perf_query(struct gl_context *ctx, struct gl_perf_query_object *o) bo = obj->pipeline_stats.bo; break; + case NULL_RENDERER: + break; + default: unreachable("Unknown query type"); break; @@ -1387,6 +1433,8 @@ brw_is_perf_query_ready(struct gl_context *ctx, return (obj->pipeline_stats.bo && !brw_batch_references(&brw->batch, obj->pipeline_stats.bo) && !brw_bo_busy(obj->pipeline_stats.bo)); + case NULL_RENDERER: + return true; default: unreachable("Unknown query type"); @@ -1602,6 +1650,9 @@ brw_get_perf_query_data(struct gl_context *ctx, written = get_pipeline_stats_data(brw, obj, data_size, (uint8_t *)data); break; + case NULL_RENDERER: + break; + default: unreachable("Unknown query type"); break; @@ -1672,6 +1723,9 @@ brw_delete_perf_query(struct gl_context *ctx, } break; + case NULL_RENDERER: + break; + default: unreachable("Unknown query type"); break; @@ -2152,6 +2206,15 @@ get_register_queries_function(const struct gen_device_info *devinfo) return NULL; } +static void +fill_null_renderer_perf_query_info(struct brw_context *brw, + struct brw_perf_query_info *query) +{ + query->kind = NULL_RENDERER; + query->name = "Intel_Null_Hardware_Query"; + query->n_counters = 0; +} + static unsigned brw_init_perf_query_info(struct gl_context *ctx) { @@ -2210,6 +2273,10 @@ brw_init_perf_query_info(struct gl_context *ctx) enumerate_sysfs_metrics(brw); brw_perf_query_register_mdapi_oa_query(brw); + + struct brw_perf_query_info *null_query = + brw_perf_query_append_query_info(brw); + fill_null_renderer_perf_query_info(brw, null_query); } brw->perfquery.unaccumulated = From bc8d447d5c6ef1469ad5189500c38a1b652bc7a9 Mon Sep 17 00:00:00 2001 From: Kevin Strasser Date: Mon, 27 Aug 2018 12:31:37 +0300 Subject: [PATCH 18/27] INTERNAL: anv: disable extensions for Android CTS MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This change makes following test pass: dEQP-VK.api.info.device.extensions Originally-from: Tapani Pälli Test: [CTS 9.0_r8] dEQP-VK.api.info.device.extensions Signed-off-by: Kevin Strasser --- src/intel/vulkan/anv_extensions.py | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/intel/vulkan/anv_extensions.py b/src/intel/vulkan/anv_extensions.py index 24dd4003f2c..c898136e88e 100644 --- a/src/intel/vulkan/anv_extensions.py +++ b/src/intel/vulkan/anv_extensions.py @@ -71,18 +71,18 @@ def __init__(self, version, enable): EXTENSIONS = [ Extension('VK_ANDROID_external_memory_android_hardware_buffer', 3, 'ANDROID'), Extension('VK_ANDROID_native_buffer', 5, 'ANDROID'), - Extension('VK_KHR_8bit_storage', 1, 'device->info.gen >= 8'), + Extension('VK_KHR_8bit_storage', 1, 'device->info.gen >= 8 && !ANDROID'), Extension('VK_KHR_16bit_storage', 1, 'device->info.gen >= 8'), Extension('VK_KHR_bind_memory2', 1, True), - Extension('VK_KHR_create_renderpass2', 1, True), + Extension('VK_KHR_create_renderpass2', 1, '!ANDROID'), Extension('VK_KHR_dedicated_allocation', 1, True), - Extension('VK_KHR_depth_stencil_resolve', 1, True), + Extension('VK_KHR_depth_stencil_resolve', 1, '!ANDROID'), Extension('VK_KHR_descriptor_update_template', 1, True), Extension('VK_KHR_device_group', 1, True), Extension('VK_KHR_device_group_creation', 1, True), Extension('VK_KHR_display', 23, 'VK_USE_PLATFORM_DISPLAY_KHR'), Extension('VK_KHR_draw_indirect_count', 1, True), - Extension('VK_KHR_driver_properties', 1, True), + Extension('VK_KHR_driver_properties', 1, '!ANDROID'), Extension('VK_KHR_external_fence', 1, 'device->has_syncobj_wait'), Extension('VK_KHR_external_fence_capabilities', 1, True), @@ -135,8 +135,8 @@ def __init__(self, version, enable): Extension('VK_EXT_shader_stencil_export', 1, 'device->info.gen >= 9'), Extension('VK_EXT_transform_feedback', 1, True), Extension('VK_EXT_vertex_attribute_divisor', 3, True), - Extension('VK_GOOGLE_decorate_string', 1, True), - Extension('VK_GOOGLE_hlsl_functionality1', 1, True), + Extension('VK_GOOGLE_decorate_string', 1, '!ANDROID'), + Extension('VK_GOOGLE_hlsl_functionality1', 1, '!ANDROID'), ] class VkVersion: From 4e3aa37e73e974b438602059bf394e89dcc69267 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Toni=20L=C3=B6nnberg?= Date: Mon, 15 Oct 2018 16:19:52 +0300 Subject: [PATCH 19/27] FROMLIST: SQUASH: i965: SIMD32 selection heuristics (cover letter https://patchwork.freedesktop.org/series/51006/) FROMLIST: i965: SIMD32 heuristics debug flag Added a new DEBUG_HEUR32 flag to INTEL_DEBUG flags for enabling SIMD32 selection heuristics. (am from https://patchwork.freedesktop.org/patch/256764/) FROMLIST: i965: SIMD32 heuristics control data Added a new structure for holding SIMD32 heuristics control data. The control data itself will be fetched from drirc. (am from https://patchwork.freedesktop.org/patch/256806/) FROMLIST: i965: SIMD32 heuristics control data from drirc To be able to test the heuristics with different parameters, they can be controlled via environment variables through drirc. (am from https://patchwork.freedesktop.org/patch/256788/) FROMLIST: mesa: Helper functions for counting set bits in a mask (am from https://patchwork.freedesktop.org/patch/256765/) FROMLIST: i965/fs: Save the instruction count of each dispatch width The SIMD32 selection heuristics will use this information for deciding whether SIMD32 shaders should be used. (am from https://patchwork.freedesktop.org/patch/256793/) FROMLIST: i965/fs: SIMD32 selection heuristic based on grouped texture fetches The function goes through the compiled shader and checks how many grouped texture fetches there are. This is a simple heuristic which gets rid of most of the regressions when enabling SIMD32 shaders but still retains some of the benefits. (am from https://patchwork.freedesktop.org/patch/256798/) FROMLIST: i965/fs: Enable all SIMD32 heuristics There are three simple heuristics for SIMD32 shader enabling: - How many MRTs does the shader write into? - How many grouped texture fetches does the shader have? - How many instructions does the SIMD32 shader have compared to the SIMD16 shader? For testing purposes, the heuristics can be controlled via these environment variables: simd32_heuristic_mrt_check - Enables MRT write check - Default: true simd32_heuristic_max_mrts - How many MRT writes the heuristic allows - Default: 1 simd32_heuristic_grouped_check - Enables grouped texture fetch check - Default: true simd32_heuristic_grouped_sends - How many grouped texture fetches the heuristic allows - Default: 6 simd32_heuristic_inst_check - Enables SIMD32 vs. SIMD16 instruction count check - Default: true simd32_heuristic_inst_ratio - SIMD32 vs. SIMD16 instruction count ratio the heuristic allows - Default: 2.3 SIMD32 shaders will not be compiled also when SIMD16 compilation fails or spills. (am from https://patchwork.freedesktop.org/patch/256766/) --- src/intel/common/gen_debug.c | 1 + src/intel/common/gen_debug.h | 3 +- src/intel/compiler/brw_compiler.h | 11 +++++ src/intel/compiler/brw_fs.cpp | 63 +++++++++++++++++++++--- src/intel/compiler/brw_fs.h | 4 ++ src/intel/compiler/brw_fs_generator.cpp | 12 +++++ src/mesa/drivers/dri/i965/brw_context.c | 13 +++++ src/mesa/drivers/dri/i965/intel_screen.c | 27 ++++++++++ src/util/bitscan.h | 25 ++++++++++ 9 files changed, 152 insertions(+), 7 deletions(-) diff --git a/src/intel/common/gen_debug.c b/src/intel/common/gen_debug.c index a978f2f5818..8990d208207 100644 --- a/src/intel/common/gen_debug.c +++ b/src/intel/common/gen_debug.c @@ -85,6 +85,7 @@ static const struct debug_control debug_control[] = { { "nohiz", DEBUG_NO_HIZ }, { "color", DEBUG_COLOR }, { "reemit", DEBUG_REEMIT }, + { "heur32", DEBUG_HEUR32 }, { NULL, 0 } }; diff --git a/src/intel/common/gen_debug.h b/src/intel/common/gen_debug.h index 72d7ca20a39..c2ca2e2ebd6 100644 --- a/src/intel/common/gen_debug.h +++ b/src/intel/common/gen_debug.h @@ -83,6 +83,7 @@ extern uint64_t INTEL_DEBUG; #define DEBUG_NO_HIZ (1ull << 39) #define DEBUG_COLOR (1ull << 40) #define DEBUG_REEMIT (1ull << 41) +#define DEBUG_HEUR32 (1ull << 42) /* These flags are not compatible with the disk shader cache */ #define DEBUG_DISK_CACHE_DISABLE_MASK DEBUG_SHADER_TIME @@ -90,7 +91,7 @@ extern uint64_t INTEL_DEBUG; /* These flags may affect program generation */ #define DEBUG_DISK_CACHE_MASK \ (DEBUG_NO16 | DEBUG_NO_DUAL_OBJECT_GS | DEBUG_NO8 | DEBUG_SPILL_FS | \ - DEBUG_SPILL_VEC4 | DEBUG_NO_COMPACTION | DEBUG_DO32) + DEBUG_SPILL_VEC4 | DEBUG_NO_COMPACTION | DEBUG_DO32 | DEBUG_HEUR32) #ifdef HAVE_ANDROID_PLATFORM #define LOG_TAG "INTEL-MESA" diff --git a/src/intel/compiler/brw_compiler.h b/src/intel/compiler/brw_compiler.h index 560f2c3c6ba..c294e5c3222 100644 --- a/src/intel/compiler/brw_compiler.h +++ b/src/intel/compiler/brw_compiler.h @@ -38,6 +38,15 @@ struct ra_regs; struct nir_shader; struct brw_program; +struct brw_simd32_heuristics_control { + bool grouped_sends_check; + int max_grouped_sends; + bool inst_count_check; + float inst_count_ratio; + bool mrt_check; + int max_mrts; +}; + struct brw_compiler { const struct gen_device_info *devinfo; @@ -118,6 +127,8 @@ struct brw_compiler { * whether nir_opt_large_constants will be run. */ bool supports_shader_constants; + + struct brw_simd32_heuristics_control simd32_heuristics_control; }; /** diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 8481fde50b1..5b29292d6a0 100644 --- a/src/intel/compiler/brw_fs.cpp +++ b/src/intel/compiler/brw_fs.cpp @@ -7603,6 +7603,8 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data, char **error_str) { const struct gen_device_info *devinfo = compiler->devinfo; + bool simd16_failed = false; + bool simd16_spilled = false; shader = brw_nir_apply_sampler_key(shader, compiler, &key->tex, true); brw_nir_lower_fs_inputs(shader, devinfo, key); @@ -7669,10 +7671,12 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data, shader_time_index16); v16.import_uniforms(&v8); if (!v16.run_fs(allow_spilling, use_rep_send)) { + simd16_failed = true; compiler->shader_perf_log(log_data, "SIMD16 shader failed to compile: %s", v16.fail_msg); } else { + simd16_spilled = v16.spilled_any_registers; simd16_cfg = v16.cfg; prog_data->dispatch_grf_start_reg_16 = v16.payload.num_regs; prog_data->reg_blocks_16 = brw_register_blocks(v16.grf_used); @@ -7680,9 +7684,17 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data, } /* Currently, the compiler only supports SIMD32 on SNB+ */ + const brw_simd32_heuristics_control *ctrl = &compiler->simd32_heuristics_control; + uint64_t mrts = shader->info.outputs_written << FRAG_RESULT_DATA0; + if (v8.max_dispatch_width >= 32 && !use_rep_send && compiler->devinfo->gen >= 6 && - unlikely(INTEL_DEBUG & DEBUG_DO32)) { + (unlikely(INTEL_DEBUG & DEBUG_DO32) || + (unlikely(INTEL_DEBUG & DEBUG_HEUR32) && + !simd16_failed && !simd16_spilled && + (!ctrl->mrt_check || + (ctrl->mrt_check && + u_count_bits64(&mrts) <= ctrl->max_mrts))))) { /* Try a SIMD32 compile */ fs_visitor v32(compiler, log_data, mem_ctx, key, &prog_data->base, prog, shader, 32, @@ -7693,9 +7705,12 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data, "SIMD32 shader failed to compile: %s", v32.fail_msg); } else { - simd32_cfg = v32.cfg; - prog_data->dispatch_grf_start_reg_32 = v32.payload.num_regs; - prog_data->reg_blocks_32 = brw_register_blocks(v32.grf_used); + if (likely(!(INTEL_DEBUG & DEBUG_HEUR32)) || + v32.run_heuristic(ctrl)) { + simd32_cfg = v32.cfg; + prog_data->dispatch_grf_start_reg_32 = v32.payload.num_regs; + prog_data->reg_blocks_32 = brw_register_blocks(v32.grf_used); + } } } @@ -7774,13 +7789,49 @@ brw_compile_fs(const struct brw_compiler *compiler, void *log_data, } if (simd32_cfg) { - prog_data->dispatch_32 = true; - prog_data->prog_offset_32 = g.generate_code(simd32_cfg, 32); + uint32_t offset = g.generate_code(simd32_cfg, 32); + + if (unlikely(INTEL_DEBUG & DEBUG_DO32) || + (unlikely(INTEL_DEBUG & DEBUG_HEUR32) && + (!simd16_cfg || + (simd16_cfg && + (!ctrl->inst_count_check || + (ctrl->inst_count_check && + (float)g.get_inst_count(32) / (float)g.get_inst_count(16) <= ctrl->inst_count_ratio)))))) { + prog_data->dispatch_32 = true; + prog_data->prog_offset_32 = offset; + } } return g.get_assembly(); } +bool +fs_visitor::run_heuristic(const struct brw_simd32_heuristics_control *ctrl) { + int grouped_sends = 0; + int max_grouped_sends = 0; + bool pass = true; + + foreach_block_and_inst(block, fs_inst, inst, cfg) { + if (inst->opcode >= SHADER_OPCODE_TEX && inst->opcode <= SHADER_OPCODE_SAMPLEINFO_LOGICAL) { + ++grouped_sends; + } else if (grouped_sends > 0) { + if (grouped_sends > max_grouped_sends) { + max_grouped_sends = grouped_sends; + } + grouped_sends = 0; + } + } + + if (ctrl->grouped_sends_check) { + if (max_grouped_sends > ctrl->max_grouped_sends) { + pass = false; + } + } + + return pass; +} + fs_reg * fs_visitor::emit_cs_work_group_id_setup() { diff --git a/src/intel/compiler/brw_fs.h b/src/intel/compiler/brw_fs.h index 5361b768003..72acf85581e 100644 --- a/src/intel/compiler/brw_fs.h +++ b/src/intel/compiler/brw_fs.h @@ -289,6 +289,8 @@ class fs_visitor : public backend_shader void dump_instruction(backend_instruction *inst); void dump_instruction(backend_instruction *inst, FILE *file); + bool run_heuristic(const struct brw_simd32_heuristics_control *ctrl); + const void *const key; const struct brw_sampler_prog_key_data *key_tex; @@ -400,6 +402,7 @@ class fs_generator void enable_debug(const char *shader_name); int generate_code(const cfg_t *cfg, int dispatch_width); + int get_inst_count(int dispatch_width); const unsigned *get_assembly(); private: @@ -495,6 +498,7 @@ class fs_generator struct brw_stage_prog_data * const prog_data; unsigned dispatch_width; /**< 8, 16 or 32 */ + int inst_count[3]; /* for 8, 16 and 32 */ exec_list discard_halt_patches; unsigned promoted_constants; diff --git a/src/intel/compiler/brw_fs_generator.cpp b/src/intel/compiler/brw_fs_generator.cpp index 09382775f3e..82c2713a77f 100644 --- a/src/intel/compiler/brw_fs_generator.cpp +++ b/src/intel/compiler/brw_fs_generator.cpp @@ -2297,6 +2297,8 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width) fill_count, promoted_constants, before_size, after_size); + inst_count[ffs(dispatch_width) - 4] = before_size / 16; + return start_offset; } @@ -2305,3 +2307,13 @@ fs_generator::get_assembly() { return brw_get_program(p, &prog_data->program_size); } + +int +fs_generator::get_inst_count(int dispatch_width) +{ + if (dispatch_width == 8 || dispatch_width == 16 || dispatch_width == 32) { + return inst_count[ffs(dispatch_width) - 4]; + } else { + return 0; + } +} \ No newline at end of file diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index 505da9896b3..e4bc5fe99f0 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++ b/src/mesa/drivers/dri/i965/brw_context.c @@ -893,6 +893,19 @@ brw_process_driconf_options(struct brw_context *brw) ctx->Const.dri_config_options_sha1 = ralloc_array(brw, unsigned char, 20); driComputeOptionsSha1(&brw->screen->optionCache, ctx->Const.dri_config_options_sha1); + + brw->screen->compiler->simd32_heuristics_control.grouped_sends_check = + driQueryOptionb(&brw->optionCache, "simd32_heuristic_grouped_check"); + brw->screen->compiler->simd32_heuristics_control.max_grouped_sends = + driQueryOptioni(&brw->optionCache, "simd32_heuristic_grouped_sends"); + brw->screen->compiler->simd32_heuristics_control.inst_count_check = + driQueryOptionb(&brw->optionCache, "simd32_heuristic_inst_check"); + brw->screen->compiler->simd32_heuristics_control.inst_count_ratio = + driQueryOptionf(&brw->optionCache, "simd32_heuristic_inst_ratio"); + brw->screen->compiler->simd32_heuristics_control.mrt_check = + driQueryOptionb(&brw->optionCache, "simd32_heuristic_mrt_check"); + brw->screen->compiler->simd32_heuristics_control.max_mrts = + driQueryOptioni(&brw->optionCache, "simd32_heuristic_max_mrts"); } GLboolean diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index 34c8f22abc3..2436f48a065 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++ b/src/mesa/drivers/dri/i965/intel_screen.c @@ -61,6 +61,33 @@ DRI_CONF_BEGIN DRI_CONF_ENUM(1, "Enable reuse of all sizes of buffer objects") DRI_CONF_DESC_END DRI_CONF_OPT_END + + DRI_CONF_OPT_BEGIN_B(simd32_heuristic_grouped_check, "true") + DRI_CONF_DESC(en, "Enable/disable grouped texture fetch " + "check in the SIMD32 selection heuristic.") + DRI_CONF_OPT_END + DRI_CONF_OPT_BEGIN_V(simd32_heuristic_grouped_sends, int, 6, "1:999") + DRI_CONF_DESC(en, "How many grouped texture fetches should " + "the SIMD32 selection heuristic allow.") + DRI_CONF_OPT_END + DRI_CONF_OPT_BEGIN_B(simd32_heuristic_inst_check, "true") + DRI_CONF_DESC(en, "Enable/disable SIMD32/SIMD16 instruction " + "count ratio check in the SIMD32 selection " + "heuristic.") + DRI_CONF_OPT_END + DRI_CONF_OPT_BEGIN_V(simd32_heuristic_inst_ratio, float, 2.3, "1:999") + DRI_CONF_DESC(en, "SIMD32/SIMD16 instruction count ratio " + "the SIMD32 selection heuristic should allow.") + DRI_CONF_OPT_END + DRI_CONF_OPT_BEGIN_B(simd32_heuristic_mrt_check, "true") + DRI_CONF_DESC(en, "Enable/disable MRT write check in the " + "SIMD32 selection heuristic.") + DRI_CONF_OPT_END + DRI_CONF_OPT_BEGIN_V(simd32_heuristic_max_mrts, int, 1, "1:8") + DRI_CONF_DESC(en, "How many MRT writes should the SIMD32 " + "selection heuristic allow.") + DRI_CONF_OPT_END + DRI_CONF_MESA_NO_ERROR("false") DRI_CONF_SECTION_END diff --git a/src/util/bitscan.h b/src/util/bitscan.h index dc89ac93f28..cdfecafaf01 100644 --- a/src/util/bitscan.h +++ b/src/util/bitscan.h @@ -112,6 +112,31 @@ u_bit_scan64(uint64_t *mask) return i; } +/* Count bits set in mask */ +static inline int +u_count_bits(unsigned *mask) +{ + unsigned v = *mask; + int c; + v = v - ((v >> 1) & 0x55555555); + v = (v & 0x33333333) + ((v >> 2) & 0x33333333); + v = (v + (v >> 4)) & 0xF0F0F0F; + c = (int)((v * 0x1010101) >> 24); + return c; +} + +static inline int +u_count_bits64(uint64_t *mask) +{ + uint64_t v = *mask; + int c; + v = v - ((v >> 1) & 0x5555555555555555ull); + v = (v & 0x3333333333333333ull) + ((v >> 2) & 0x3333333333333333ull); + v = (v + (v >> 4)) & 0xF0F0F0F0F0F0F0Full; + c = (int)((v * 0x101010101010101ull) >> 56); + return c; +} + /* Determine if an unsigned value is a power of two. * * \note From d16da8dadb5c39d2985e9915282a1112aedd6a42 Mon Sep 17 00:00:00 2001 From: Andrii Simiklit Date: Tue, 5 Mar 2019 17:58:53 +0200 Subject: [PATCH 20/27] FROMLIST: glsl: fix a binding points assignment for ssbo/ubo arrays This is needed to be in agreement with spec requirements: https://github.com/KhronosGroup/OpenGL-API/issues/46 Piers Daniell: "We discussed this in the OpenGL/ES working group meeting and agreed that eliminating unused elements from the interface block array is not desirable. There is no statement in the spec that this takes place and it would be highly implementation dependent if it happens. If the application has an "interface" in the shader they need to match up with the API it would be quite confusing to have the binding point get compacted. So the answer is no, the binding points aren't affected by unused elements in the interface block array." Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109532 Reported-By: Ilia Mirkin Signed-off-by: Andrii Simiklit TEST=[CTS 9.0r6} dEQP-GLES31.functional.ssbo.layout.random.all_per_block_buffers#18 (am from https://gitlab.freedesktop.org/mesa/mesa/merge_requests/332) Signed-off-by: Kevin Strasser --- .../glsl/link_uniform_block_active_visitor.cpp | 1 + .../glsl/link_uniform_block_active_visitor.h | 1 + src/compiler/glsl/link_uniform_blocks.cpp | 12 +++++++----- 3 files changed, 9 insertions(+), 5 deletions(-) diff --git a/src/compiler/glsl/link_uniform_block_active_visitor.cpp b/src/compiler/glsl/link_uniform_block_active_visitor.cpp index 368981852c0..0af3b312071 100644 --- a/src/compiler/glsl/link_uniform_block_active_visitor.cpp +++ b/src/compiler/glsl/link_uniform_block_active_visitor.cpp @@ -103,6 +103,7 @@ process_arrays(void *mem_ctx, ir_dereference_array *ir, if (*ub_array_ptr == NULL) { *ub_array_ptr = rzalloc(mem_ctx, struct uniform_block_array_elements); (*ub_array_ptr)->ir = ir; + (*ub_array_ptr)->original_dim_size = block->type->length; } struct uniform_block_array_elements *ub_array = *ub_array_ptr; diff --git a/src/compiler/glsl/link_uniform_block_active_visitor.h b/src/compiler/glsl/link_uniform_block_active_visitor.h index fbac65d5b67..a8ea3f52b6d 100644 --- a/src/compiler/glsl/link_uniform_block_active_visitor.h +++ b/src/compiler/glsl/link_uniform_block_active_visitor.h @@ -32,6 +32,7 @@ struct uniform_block_array_elements { unsigned num_array_elements; ir_dereference_array *ir; + unsigned original_dim_size; struct uniform_block_array_elements *array; }; diff --git a/src/compiler/glsl/link_uniform_blocks.cpp b/src/compiler/glsl/link_uniform_blocks.cpp index 0b890586298..e180d2bc379 100644 --- a/src/compiler/glsl/link_uniform_blocks.cpp +++ b/src/compiler/glsl/link_uniform_blocks.cpp @@ -244,18 +244,21 @@ process_block_array(struct uniform_block_array_elements *ub_array, char **name, for (unsigned j = 0; j < ub_array->num_array_elements; j++) { size_t new_length = name_length; + unsigned int element_idx = ub_array->array_elements[j]; /* Append the subscript to the current variable name */ - ralloc_asprintf_rewrite_tail(name, &new_length, "[%u]", - ub_array->array_elements[j]); + ralloc_asprintf_rewrite_tail(name, &new_length, "[%u]", element_idx); if (ub_array->array) { + unsigned boffset = (*binding_offset) + (element_idx * + ub_array->original_dim_size); process_block_array(ub_array->array, name, new_length, blocks, parcel, variables, b, block_index, - binding_offset, ctx, prog, first_index); + &boffset, ctx, prog, first_index); } else { + unsigned boffset = (*binding_offset) + element_idx; process_block_array_leaf(*name, blocks, parcel, variables, b, block_index, - binding_offset, *block_index - first_index, + &boffset, *block_index - first_index, ctx, prog); } } @@ -307,7 +310,6 @@ process_block_array_leaf(const char *name, (unsigned)(ptrdiff_t)(&variables[parcel->index] - blocks[i].Uniforms); *block_index = *block_index + 1; - *binding_offset = *binding_offset + 1; } /* This function resizes the array types of the block so that later we can use From 73918cdb58c838bbe7f78596c9dbf4bf10f8381a Mon Sep 17 00:00:00 2001 From: Andrii Simiklit Date: Tue, 5 Mar 2019 17:38:20 +0200 Subject: [PATCH 21/27] FROMLIST: glsl: fix an incorrect max_array_access after optimization of ssbo/ubo This is needed to fix these tests: piglit.spec.arb_shader_storage_buffer_object.compiler.unused-array-element_frag piglit.spec.arb_shader_storage_buffer_object.compiler.unused-array-element_comp Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109532 Reported-By: Ilia Mirkin Signed-off-by: Andrii Simiklit TEST=[CTS 9.0r6} dEQP-GLES31.functional.ssbo.layout.random.all_per_block_buffers#18 (am from https://gitlab.freedesktop.org/mesa/mesa/merge_requests/332) Signed-off-by: Kevin Strasser --- src/compiler/glsl/link_uniform_blocks.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/src/compiler/glsl/link_uniform_blocks.cpp b/src/compiler/glsl/link_uniform_blocks.cpp index e180d2bc379..1665fc3f8cb 100644 --- a/src/compiler/glsl/link_uniform_blocks.cpp +++ b/src/compiler/glsl/link_uniform_blocks.cpp @@ -442,6 +442,7 @@ link_uniform_blocks(void *mem_ctx, GLSL_INTERFACE_PACKING_PACKED)) { b->type = resize_block_array(b->type, b->array); b->var->type = b->type; + b->var->data.max_array_access = b->type->length - 1; } block_size.num_active_uniforms = 0; From 31938ce2697603248d7d021a166ec69d08b97631 Mon Sep 17 00:00:00 2001 From: Chenglei Ren Date: Thu, 23 May 2019 11:22:00 +0800 Subject: [PATCH 22/27] UPSTREAM: anv/android: fix missing dependencies issue during parallel build MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The libmesa_anv_gen* modules require anv_extensions.h, patch makes sure it gets generated as a dependency before building them. Signed-off-by: Chenglei Ren Reviewed-by: Tapani Pälli Cc: (cherry picked from commit 13b38ca1e4341f5f16ae3ee9856552db12fda4cf) --- src/intel/Android.vulkan.mk | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/src/intel/Android.vulkan.mk b/src/intel/Android.vulkan.mk index 279a673de73..73586803552 100644 --- a/src/intel/Android.vulkan.mk +++ b/src/intel/Android.vulkan.mk @@ -72,6 +72,7 @@ LOCAL_C_INCLUDES := \ LOCAL_GENERATED_SOURCES += $(intermediates)/vulkan/anv_entrypoints.h LOCAL_GENERATED_SOURCES += $(intermediates)/vulkan/dummy.c +LOCAL_GENERATED_SOURCES += $(intermediates)/vulkan/anv_extensions.h $(intermediates)/vulkan/dummy.c: @mkdir -p $(dir $@) @@ -86,6 +87,14 @@ $(intermediates)/vulkan/anv_entrypoints.h: $(intermediates)/vulkan/dummy.c \ --outdir $(dir $@) \ --xml $(VULKAN_API_XML) +$(intermediates)/vulkan/anv_extensions.h: $(ANV_ENTRYPOINTS_GEN_SCRIPT) \ + $(ANV_EXTENSIONS_SCRIPT) \ + $(VULKAN_API_XML) + @mkdir -p $(dir $@) + $(MESA_PYTHON2) $(ANV_EXTENSIONS_GEN_SCRIPT) \ + --xml $(VULKAN_API_XML) \ + --out-h $@ + LOCAL_EXPORT_C_INCLUDE_DIRS := \ $(intermediates) @@ -262,7 +271,6 @@ LOCAL_WHOLE_STATIC_LIBRARIES := \ LOCAL_GENERATED_SOURCES += $(intermediates)/vulkan/anv_entrypoints.c LOCAL_GENERATED_SOURCES += $(intermediates)/vulkan/anv_extensions.c -LOCAL_GENERATED_SOURCES += $(intermediates)/vulkan/anv_extensions.h $(intermediates)/vulkan/anv_entrypoints.c: $(ANV_ENTRYPOINTS_GEN_SCRIPT) \ $(ANV_EXTENSIONS_SCRIPT) \ @@ -280,14 +288,6 @@ $(intermediates)/vulkan/anv_extensions.c: $(ANV_EXTENSIONS_GEN_SCRIPT) \ --xml $(VULKAN_API_XML) \ --out-c $@ -$(intermediates)/vulkan/anv_extensions.h: $(ANV_EXTENSIONS_GEN_SCRIPT) \ - $(ANV_EXTENSIONS_SCRIPT) \ - $(VULKAN_API_XML) - @mkdir -p $(dir $@) - $(MESA_PYTHON2) $(ANV_EXTENSIONS_GEN_SCRIPT) \ - --xml $(VULKAN_API_XML) \ - --out-h $@ - LOCAL_SHARED_LIBRARIES := $(ANV_SHARED_LIBRARIES) LOCAL_HEADER_LIBRARIES += $(VULKAN_COMMON_HEADER_LIBRARIES) From bdf98e2554043278ae66d26baa2f0a389a76c7ef Mon Sep 17 00:00:00 2001 From: renchenglei Date: Thu, 30 May 2019 23:38:08 +0800 Subject: [PATCH 23/27] Add prebuilt-intermediates for xmlpool The AOSP master build system has started to police the use of non-hermetic tools from the system PATH. The Mesa project was using xgettext and other tools which are not part of the standard Android host build tools, and are therefore not allowed. This ban is now being enforced. To work around this problem, introduce prebuilt-intermediates for xmlpool based on the current source tree. Bug: 116125577 Change-Id: Ica53192b4c5495550ce5d6b49510b5984cedd4be Signed-off-by: Alistair Strachan --- prebuilt-intermediates/xmlpool/options.h | 632 +++++++++++++++++++++++ src/util/Android.mk | 55 +- 2 files changed, 638 insertions(+), 49 deletions(-) create mode 100644 prebuilt-intermediates/xmlpool/options.h diff --git a/prebuilt-intermediates/xmlpool/options.h b/prebuilt-intermediates/xmlpool/options.h new file mode 100644 index 00000000000..d1201383f20 --- /dev/null +++ b/prebuilt-intermediates/xmlpool/options.h @@ -0,0 +1,632 @@ +/* This is file is generated automatically. Don't edit! */ +/* + * XML DRI client-side driver configuration + * Copyright (C) 2003 Felix Kuehling + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * FELIX KUEHLING, OR ANY OTHER CONTRIBUTORS BE LIABLE FOR ANY CLAIM, + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE + * OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + */ +/** + * \file t_options.h + * \brief Templates of common options + * \author Felix Kuehling + * + * This file defines macros for common options that can be used to + * construct driConfigOptions in the drivers. This file is only a + * template containing English descriptions for options wrapped in + * gettext(). xgettext can be used to extract translatable + * strings. These strings can then be translated by anyone familiar + * with GNU gettext. gen_xmlpool.py takes this template and fills in + * all the translations. The result (options.h) is included by + * xmlpool.h which in turn can be included by drivers. + * + * The macros used to describe otions in this file are defined in + * ../xmlpool.h. + */ + +/* This is needed for xgettext to extract translatable strings. + * gen_xmlpool.py will discard this line. */ +/* #include + * commented out by gen_xmlpool.py */ + +/* + * predefined option sections and options with multi-lingual descriptions + */ + + +/** + * \brief Debugging options + */ +#define DRI_CONF_SECTION_DEBUG \ +DRI_CONF_SECTION_BEGIN \ + DRI_CONF_DESC(en,"Debugging") \ + DRI_CONF_DESC(de,"Fehlersuche") \ + DRI_CONF_DESC(es,"Depuración") \ + DRI_CONF_DESC(nl,"Debuggen") \ + DRI_CONF_DESC(fr,"Debogage") \ + DRI_CONF_DESC(sv,"Felsökning") + +#define DRI_CONF_ALWAYS_FLUSH_BATCH(def) \ +DRI_CONF_OPT_BEGIN_B(always_flush_batch, def) \ + DRI_CONF_DESC(en,"Enable flushing batchbuffer after each draw call") \ + DRI_CONF_DESC(de,"Aktiviere sofortige Leerung des Stapelpuffers nach jedem Zeichenaufruf") \ + DRI_CONF_DESC(es,"Habilitar vaciado del batchbuffer después de cada llamada de dibujo") \ + DRI_CONF_DESC(nl,"Enable flushing batchbuffer after each draw call") \ + DRI_CONF_DESC(fr,"Enable flushing batchbuffer after each draw call") \ + DRI_CONF_DESC(sv,"Enable flushing batchbuffer after each draw call") \ +DRI_CONF_OPT_END + +#define DRI_CONF_ALWAYS_FLUSH_CACHE(def) \ +DRI_CONF_OPT_BEGIN_B(always_flush_cache, def) \ + DRI_CONF_DESC(en,"Enable flushing GPU caches with each draw call") \ + DRI_CONF_DESC(de,"Aktiviere sofortige Leerung der GPU-Zwischenspeicher mit jedem Zeichenaufruf") \ + DRI_CONF_DESC(es,"Habilitar vaciado de los cachés GPU con cada llamada de dibujo") \ + DRI_CONF_DESC(nl,"Enable flushing GPU caches with each draw call") \ + DRI_CONF_DESC(fr,"Enable flushing GPU caches with each draw call") \ + DRI_CONF_DESC(sv,"Enable flushing GPU caches with each draw call") \ +DRI_CONF_OPT_END + +#define DRI_CONF_DISABLE_THROTTLING(def) \ +DRI_CONF_OPT_BEGIN_B(disable_throttling, def) \ + DRI_CONF_DESC(en,"Disable throttling on first batch after flush") \ + DRI_CONF_DESC(de,"Disable throttling on first batch after flush") \ + DRI_CONF_DESC(es,"Deshabilitar regulación del primer lote después de vaciar") \ + DRI_CONF_DESC(nl,"Disable throttling on first batch after flush") \ + DRI_CONF_DESC(fr,"Disable throttling on first batch after flush") \ + DRI_CONF_DESC(sv,"Disable throttling on first batch after flush") \ +DRI_CONF_OPT_END + +#define DRI_CONF_FORCE_GLSL_EXTENSIONS_WARN(def) \ +DRI_CONF_OPT_BEGIN_B(force_glsl_extensions_warn, def) \ + DRI_CONF_DESC(en,"Force GLSL extension default behavior to 'warn'") \ + DRI_CONF_DESC(de,"Force GLSL extension default behavior to 'warn'") \ + DRI_CONF_DESC(es,"Forzar que el comportamiento por defecto de las extensiones GLSL sea 'warn'") \ + DRI_CONF_DESC(nl,"Force GLSL extension default behavior to 'warn'") \ + DRI_CONF_DESC(fr,"Force GLSL extension default behavior to 'warn'") \ + DRI_CONF_DESC(sv,"Force GLSL extension default behavior to 'warn'") \ +DRI_CONF_OPT_END + +#define DRI_CONF_DISABLE_BLEND_FUNC_EXTENDED(def) \ +DRI_CONF_OPT_BEGIN_B(disable_blend_func_extended, def) \ + DRI_CONF_DESC(en,"Disable dual source blending") \ + DRI_CONF_DESC(de,"Disable dual source blending") \ + DRI_CONF_DESC(es,"Deshabilitar mezcla de fuente dual") \ + DRI_CONF_DESC(nl,"Disable dual source blending") \ + DRI_CONF_DESC(fr,"Disable dual source blending") \ + DRI_CONF_DESC(sv,"Disable dual source blending") \ +DRI_CONF_OPT_END + +#define DRI_CONF_DUAL_COLOR_BLEND_BY_LOCATION(def) \ +DRI_CONF_OPT_BEGIN_B(dual_color_blend_by_location, def) \ + DRI_CONF_DESC(en,"Identify dual color blending sources by location rather than index") \ + DRI_CONF_DESC(de,"Identify dual color blending sources by location rather than index") \ + DRI_CONF_DESC(es,"Identify dual color blending sources by location rather than index") \ + DRI_CONF_DESC(nl,"Identify dual color blending sources by location rather than index") \ + DRI_CONF_DESC(fr,"Identify dual color blending sources by location rather than index") \ + DRI_CONF_DESC(sv,"Identify dual color blending sources by location rather than index") \ +DRI_CONF_OPT_END + +#define DRI_CONF_DISABLE_GLSL_LINE_CONTINUATIONS(def) \ +DRI_CONF_OPT_BEGIN_B(disable_glsl_line_continuations, def) \ + DRI_CONF_DESC(en,"Disable backslash-based line continuations in GLSL source") \ + DRI_CONF_DESC(de,"Disable backslash-based line continuations in GLSL source") \ + DRI_CONF_DESC(es,"Deshabilitar continuaciones de línea basadas en barra inversa en el código GLSL") \ + DRI_CONF_DESC(nl,"Disable backslash-based line continuations in GLSL source") \ + DRI_CONF_DESC(fr,"Disable backslash-based line continuations in GLSL source") \ + DRI_CONF_DESC(sv,"Disable backslash-based line continuations in GLSL source") \ +DRI_CONF_OPT_END + +#define DRI_CONF_FORCE_GLSL_VERSION(def) \ +DRI_CONF_OPT_BEGIN_V(force_glsl_version, int, def, "0:999") \ + DRI_CONF_DESC(en,"Force a default GLSL version for shaders that lack an explicit #version line") \ + DRI_CONF_DESC(de,"Force a default GLSL version for shaders that lack an explicit #version line") \ + DRI_CONF_DESC(es,"Forzar una versión de GLSL por defecto en los shaders a los cuales les falta una línea #version explícita") \ + DRI_CONF_DESC(nl,"Force a default GLSL version for shaders that lack an explicit #version line") \ + DRI_CONF_DESC(fr,"Force a default GLSL version for shaders that lack an explicit #version line") \ + DRI_CONF_DESC(sv,"Force a default GLSL version for shaders that lack an explicit #version line") \ +DRI_CONF_OPT_END + +#define DRI_CONF_ALLOW_GLSL_EXTENSION_DIRECTIVE_MIDSHADER(def) \ +DRI_CONF_OPT_BEGIN_B(allow_glsl_extension_directive_midshader, def) \ + DRI_CONF_DESC(en,"Allow GLSL #extension directives in the middle of shaders") \ + DRI_CONF_DESC(de,"Allow GLSL #extension directives in the middle of shaders") \ + DRI_CONF_DESC(es,"Permite directivas #extension GLSL en medio de los shaders") \ + DRI_CONF_DESC(nl,"Allow GLSL #extension directives in the middle of shaders") \ + DRI_CONF_DESC(fr,"Allow GLSL #extension directives in the middle of shaders") \ + DRI_CONF_DESC(sv,"Allow GLSL #extension directives in the middle of shaders") \ +DRI_CONF_OPT_END + +#define DRI_CONF_ALLOW_GLSL_BUILTIN_CONST_EXPRESSION(def) \ +DRI_CONF_OPT_BEGIN_B(allow_glsl_builtin_const_expression, def) \ + DRI_CONF_DESC(en,"Allow builtins as part of constant expressions") \ + DRI_CONF_DESC(de,"Allow builtins as part of constant expressions") \ + DRI_CONF_DESC(es,"Allow builtins as part of constant expressions") \ + DRI_CONF_DESC(nl,"Allow builtins as part of constant expressions") \ + DRI_CONF_DESC(fr,"Allow builtins as part of constant expressions") \ + DRI_CONF_DESC(sv,"Allow builtins as part of constant expressions") \ +DRI_CONF_OPT_END + +#define DRI_CONF_ALLOW_GLSL_RELAXED_ES(def) \ +DRI_CONF_OPT_BEGIN_B(allow_glsl_relaxed_es, def) \ + DRI_CONF_DESC(en,"Allow some relaxation of GLSL ES shader restrictions") \ + DRI_CONF_DESC(de,"Allow some relaxation of GLSL ES shader restrictions") \ + DRI_CONF_DESC(es,"Allow some relaxation of GLSL ES shader restrictions") \ + DRI_CONF_DESC(nl,"Allow some relaxation of GLSL ES shader restrictions") \ + DRI_CONF_DESC(fr,"Allow some relaxation of GLSL ES shader restrictions") \ + DRI_CONF_DESC(sv,"Allow some relaxation of GLSL ES shader restrictions") \ +DRI_CONF_OPT_END + +#define DRI_CONF_ALLOW_GLSL_BUILTIN_VARIABLE_REDECLARATION(def) \ +DRI_CONF_OPT_BEGIN_B(allow_glsl_builtin_variable_redeclaration, def) \ + DRI_CONF_DESC(en,"Allow GLSL built-in variables to be redeclared verbatim") \ + DRI_CONF_DESC(de,"Allow GLSL built-in variables to be redeclared verbatim") \ + DRI_CONF_DESC(es,"Allow GLSL built-in variables to be redeclared verbatim") \ + DRI_CONF_DESC(nl,"Allow GLSL built-in variables to be redeclared verbatim") \ + DRI_CONF_DESC(fr,"Allow GLSL built-in variables to be redeclared verbatim") \ + DRI_CONF_DESC(sv,"Allow GLSL built-in variables to be redeclared verbatim") \ +DRI_CONF_OPT_END + +#define DRI_CONF_ALLOW_HIGHER_COMPAT_VERSION(def) \ +DRI_CONF_OPT_BEGIN_B(allow_higher_compat_version, def) \ + DRI_CONF_DESC(en,"Allow a higher compat profile (version 3.1+) for apps that request it") \ + DRI_CONF_DESC(de,"Allow a higher compat profile (version 3.1+) for apps that request it") \ + DRI_CONF_DESC(es,"Allow a higher compat profile (version 3.1+) for apps that request it") \ + DRI_CONF_DESC(nl,"Allow a higher compat profile (version 3.1+) for apps that request it") \ + DRI_CONF_DESC(fr,"Allow a higher compat profile (version 3.1+) for apps that request it") \ + DRI_CONF_DESC(sv,"Allow a higher compat profile (version 3.1+) for apps that request it") \ +DRI_CONF_OPT_END + +#define DRI_CONF_FORCE_GLSL_ABS_SQRT(def) \ +DRI_CONF_OPT_BEGIN_B(force_glsl_abs_sqrt, def) \ + DRI_CONF_DESC(en,"Force computing the absolute value for sqrt() and inversesqrt()") \ + DRI_CONF_DESC(de,"Force computing the absolute value for sqrt() and inversesqrt()") \ + DRI_CONF_DESC(es,"Force computing the absolute value for sqrt() and inversesqrt()") \ + DRI_CONF_DESC(nl,"Force computing the absolute value for sqrt() and inversesqrt()") \ + DRI_CONF_DESC(fr,"Force computing the absolute value for sqrt() and inversesqrt()") \ + DRI_CONF_DESC(sv,"Force computing the absolute value for sqrt() and inversesqrt()") \ +DRI_CONF_OPT_END + +#define DRI_CONF_GLSL_CORRECT_DERIVATIVES_AFTER_DISCARD(def) \ +DRI_CONF_OPT_BEGIN_B(glsl_correct_derivatives_after_discard, def) \ + DRI_CONF_DESC(en,"Implicit and explicit derivatives after a discard behave as if the discard didn't happen") \ + DRI_CONF_DESC(de,"Implicit and explicit derivatives after a discard behave as if the discard didn't happen") \ + DRI_CONF_DESC(es,"Implicit and explicit derivatives after a discard behave as if the discard didn't happen") \ + DRI_CONF_DESC(nl,"Implicit and explicit derivatives after a discard behave as if the discard didn't happen") \ + DRI_CONF_DESC(fr,"Implicit and explicit derivatives after a discard behave as if the discard didn't happen") \ + DRI_CONF_DESC(sv,"Implicit and explicit derivatives after a discard behave as if the discard didn't happen") \ +DRI_CONF_OPT_END + +#define DRI_CONF_ALLOW_GLSL_CROSS_STAGE_INTERPOLATION_MISMATCH(def) \ +DRI_CONF_OPT_BEGIN_B(allow_glsl_cross_stage_interpolation_mismatch, def) \ + DRI_CONF_DESC(en,"Allow interpolation qualifier mismatch across shader stages") \ + DRI_CONF_DESC(de,"Allow interpolation qualifier mismatch across shader stages") \ + DRI_CONF_DESC(es,"Allow interpolation qualifier mismatch across shader stages") \ + DRI_CONF_DESC(nl,"Allow interpolation qualifier mismatch across shader stages") \ + DRI_CONF_DESC(fr,"Allow interpolation qualifier mismatch across shader stages") \ + DRI_CONF_DESC(sv,"Allow interpolation qualifier mismatch across shader stages") \ +DRI_CONF_OPT_END + +#define DRI_CONF_ALLOW_GLSL_LAYOUT_QUALIFIER_ON_FUNCTION_PARAMETERS(def) \ +DRI_CONF_OPT_BEGIN_B(allow_glsl_layout_qualifier_on_function_parameters, def) \ + DRI_CONF_DESC(en,"Allow layout qualifiers on function parameters.") \ + DRI_CONF_DESC(de,"Allow layout qualifiers on function parameters.") \ + DRI_CONF_DESC(es,"Allow layout qualifiers on function parameters.") \ + DRI_CONF_DESC(nl,"Allow layout qualifiers on function parameters.") \ + DRI_CONF_DESC(fr,"Allow layout qualifiers on function parameters.") \ + DRI_CONF_DESC(sv,"Allow layout qualifiers on function parameters.") \ +DRI_CONF_OPT_END + +#define DRI_CONF_FORCE_COMPAT_PROFILE(def) \ +DRI_CONF_OPT_BEGIN_B(force_compat_profile, def) \ + DRI_CONF_DESC(en,"Force an OpenGL compatibility context") \ + DRI_CONF_DESC(de,"Force an OpenGL compatibility context") \ + DRI_CONF_DESC(es,"Force an OpenGL compatibility context") \ + DRI_CONF_DESC(nl,"Force an OpenGL compatibility context") \ + DRI_CONF_DESC(fr,"Force an OpenGL compatibility context") \ + DRI_CONF_DESC(sv,"Force an OpenGL compatibility context") \ +DRI_CONF_OPT_END + +/** + * \brief Image quality-related options + */ +#define DRI_CONF_SECTION_QUALITY \ +DRI_CONF_SECTION_BEGIN \ + DRI_CONF_DESC(en,"Image Quality") \ + DRI_CONF_DESC(de,"Bildqualität") \ + DRI_CONF_DESC(es,"Calidad de imagen") \ + DRI_CONF_DESC(nl,"Beeldkwaliteit") \ + DRI_CONF_DESC(fr,"Qualité d'image") \ + DRI_CONF_DESC(sv,"Bildkvalitet") + +#define DRI_CONF_PRECISE_TRIG(def) \ +DRI_CONF_OPT_BEGIN_B(precise_trig, def) \ + DRI_CONF_DESC(en,"Prefer accuracy over performance in trig functions") \ + DRI_CONF_DESC(de,"Prefer accuracy over performance in trig functions") \ + DRI_CONF_DESC(es,"Prefer accuracy over performance in trig functions") \ + DRI_CONF_DESC(nl,"Prefer accuracy over performance in trig functions") \ + DRI_CONF_DESC(fr,"Prefer accuracy over performance in trig functions") \ + DRI_CONF_DESC(sv,"Prefer accuracy over performance in trig functions") \ +DRI_CONF_OPT_END + +#define DRI_CONF_PP_CELSHADE(def) \ +DRI_CONF_OPT_BEGIN_V(pp_celshade,enum,def,"0:1") \ + DRI_CONF_DESC(en,"A post-processing filter to cel-shade the output") \ + DRI_CONF_DESC(de,"Nachbearbeitungsfilter für Cell Shading") \ + DRI_CONF_DESC(es,"Un filtro de postprocesamiento para aplicar cel shading a la salida") \ + DRI_CONF_DESC(nl,"A post-processing filter to cel-shade the output") \ + DRI_CONF_DESC(fr,"A post-processing filter to cel-shade the output") \ + DRI_CONF_DESC(sv,"A post-processing filter to cel-shade the output") \ +DRI_CONF_OPT_END + +#define DRI_CONF_PP_NORED(def) \ +DRI_CONF_OPT_BEGIN_V(pp_nored,enum,def,"0:1") \ + DRI_CONF_DESC(en,"A post-processing filter to remove the red channel") \ + DRI_CONF_DESC(de,"Nachbearbeitungsfilter zum Entfernen des Rotkanals") \ + DRI_CONF_DESC(es,"Un filtro de postprocesamiento para eliminar el canal rojo") \ + DRI_CONF_DESC(nl,"A post-processing filter to remove the red channel") \ + DRI_CONF_DESC(fr,"A post-processing filter to remove the red channel") \ + DRI_CONF_DESC(sv,"A post-processing filter to remove the red channel") \ +DRI_CONF_OPT_END + +#define DRI_CONF_PP_NOGREEN(def) \ +DRI_CONF_OPT_BEGIN_V(pp_nogreen,enum,def,"0:1") \ + DRI_CONF_DESC(en,"A post-processing filter to remove the green channel") \ + DRI_CONF_DESC(de,"Nachbearbeitungsfilter zum Entfernen des Grünkanals") \ + DRI_CONF_DESC(es,"Un filtro de postprocesamiento para eliminar el canal verde") \ + DRI_CONF_DESC(nl,"A post-processing filter to remove the green channel") \ + DRI_CONF_DESC(fr,"A post-processing filter to remove the green channel") \ + DRI_CONF_DESC(sv,"A post-processing filter to remove the green channel") \ +DRI_CONF_OPT_END + +#define DRI_CONF_PP_NOBLUE(def) \ +DRI_CONF_OPT_BEGIN_V(pp_noblue,enum,def,"0:1") \ + DRI_CONF_DESC(en,"A post-processing filter to remove the blue channel") \ + DRI_CONF_DESC(de,"Nachbearbeitungsfilter zum Entfernen des Blaukanals") \ + DRI_CONF_DESC(es,"Un filtro de postprocesamiento para eliminar el canal azul") \ + DRI_CONF_DESC(nl,"A post-processing filter to remove the blue channel") \ + DRI_CONF_DESC(fr,"A post-processing filter to remove the blue channel") \ + DRI_CONF_DESC(sv,"A post-processing filter to remove the blue channel") \ +DRI_CONF_OPT_END + +#define DRI_CONF_PP_JIMENEZMLAA(def,min,max) \ +DRI_CONF_OPT_BEGIN_V(pp_jimenezmlaa,int,def, # min ":" # max ) \ + DRI_CONF_DESC(en,"Morphological anti-aliasing based on Jimenez\' MLAA. 0 to disable, 8 for default quality") \ + DRI_CONF_DESC(de,"Morphologische Kantenglättung (Anti-Aliasing) basierend auf Jimenez' MLAA. 0 für deaktiviert, 8 für Standardqualität") \ + DRI_CONF_DESC(es,"Antialiasing morfológico basado en el MLAA de Jimenez. 0 para deshabilitar, 8 para calidad por defecto") \ + DRI_CONF_DESC(nl,"Morphological anti-aliasing based on Jimenez\' MLAA. 0 to disable, 8 for default quality") \ + DRI_CONF_DESC(fr,"Morphological anti-aliasing based on Jimenez\' MLAA. 0 to disable, 8 for default quality") \ + DRI_CONF_DESC(sv,"Morphological anti-aliasing based on Jimenez\' MLAA. 0 to disable, 8 for default quality") \ +DRI_CONF_OPT_END + +#define DRI_CONF_PP_JIMENEZMLAA_COLOR(def,min,max) \ +DRI_CONF_OPT_BEGIN_V(pp_jimenezmlaa_color,int,def, # min ":" # max ) \ + DRI_CONF_DESC(en,"Morphological anti-aliasing based on Jimenez\' MLAA. 0 to disable, 8 for default quality. Color version, usable with 2d GL apps") \ + DRI_CONF_DESC(de,"Morphologische Kantenglättung (Anti-Aliasing) basierend auf Jimenez' MLAA. 0 für deaktiviert, 8 für Standardqualität. Farbversion, für 2D-Anwendungen") \ + DRI_CONF_DESC(es,"Antialiasing morfológico basado en el MLAA de Jimenez. 0 para deshabilitar, 8 para calidad por defecto. Versión en color, usable con aplicaciones GL 2D") \ + DRI_CONF_DESC(nl,"Morphological anti-aliasing based on Jimenez\' MLAA. 0 to disable, 8 for default quality. Color version, usable with 2d GL apps") \ + DRI_CONF_DESC(fr,"Morphological anti-aliasing based on Jimenez\' MLAA. 0 to disable, 8 for default quality. Color version, usable with 2d GL apps") \ + DRI_CONF_DESC(sv,"Morphological anti-aliasing based on Jimenez\' MLAA. 0 to disable, 8 for default quality. Color version, usable with 2d GL apps") \ +DRI_CONF_OPT_END + + + +/** + * \brief Performance-related options + */ +#define DRI_CONF_SECTION_PERFORMANCE \ +DRI_CONF_SECTION_BEGIN \ + DRI_CONF_DESC(en,"Performance") \ + DRI_CONF_DESC(de,"Leistung") \ + DRI_CONF_DESC(es,"Rendimiento") \ + DRI_CONF_DESC(nl,"Prestatie") \ + DRI_CONF_DESC(fr,"Performance") \ + DRI_CONF_DESC(sv,"Prestanda") + +#define DRI_CONF_VBLANK_NEVER 0 +#define DRI_CONF_VBLANK_DEF_INTERVAL_0 1 +#define DRI_CONF_VBLANK_DEF_INTERVAL_1 2 +#define DRI_CONF_VBLANK_ALWAYS_SYNC 3 +#define DRI_CONF_VBLANK_MODE(def) \ +DRI_CONF_OPT_BEGIN_V(vblank_mode,enum,def,"0:3") \ + DRI_CONF_DESC_BEGIN(en,"Synchronization with vertical refresh (swap intervals)") \ + DRI_CONF_ENUM(0,"Never synchronize with vertical refresh, ignore application's choice") \ + DRI_CONF_ENUM(1,"Initial swap interval 0, obey application's choice") \ + DRI_CONF_ENUM(2,"Initial swap interval 1, obey application's choice") \ + DRI_CONF_ENUM(3,"Always synchronize with vertical refresh, application chooses the minimum swap interval") \ + DRI_CONF_DESC_END \ + DRI_CONF_DESC_BEGIN(de,"Synchronisation mit der vertikalen Bildwiederholung") \ + DRI_CONF_ENUM(0,"Niemals mit der Bildwiederholung synchronisieren, Anweisungen der Anwendung ignorieren") \ + DRI_CONF_ENUM(1,"Initiales Bildinterval 0, Anweisungen der Anwendung gehorchen") \ + DRI_CONF_ENUM(2,"Initiales Bildinterval 1, Anweisungen der Anwendung gehorchen") \ + DRI_CONF_ENUM(3,"Immer mit der Bildwiederholung synchronisieren, Anwendung wählt das minimale Bildintervall") \ + DRI_CONF_DESC_END \ + DRI_CONF_DESC_BEGIN(es,"Sincronización con el refresco vertical (intervalos de intercambio)") \ + DRI_CONF_ENUM(0,"No sincronizar nunca con el refresco vertical, ignorar la elección de la aplicación") \ + DRI_CONF_ENUM(1,"Intervalo de intercambio inicial 0, obedecer la elección de la aplicación") \ + DRI_CONF_ENUM(2,"Intervalo de intercambio inicial 1, obedecer la elección de la aplicación") \ + DRI_CONF_ENUM(3,"Sincronizar siempre con el refresco vertical, la aplicación elige el intervalo de intercambio mínimo") \ + DRI_CONF_DESC_END \ + DRI_CONF_DESC_BEGIN(nl,"Synchronisatie met verticale verversing (interval omwisselen)") \ + DRI_CONF_ENUM(0,"Nooit synchroniseren met verticale verversing, negeer de keuze van de applicatie") \ + DRI_CONF_ENUM(1,"Initïeel omwisselingsinterval 0, honoreer de keuze van de applicatie") \ + DRI_CONF_ENUM(2,"Initïeel omwisselingsinterval 1, honoreer de keuze van de applicatie") \ + DRI_CONF_ENUM(3,"Synchroniseer altijd met verticale verversing, de applicatie kiest het minimum omwisselingsinterval") \ + DRI_CONF_DESC_END \ + DRI_CONF_DESC_BEGIN(fr,"Synchronisation de l'affichage avec le balayage vertical") \ + DRI_CONF_ENUM(0,"Ne jamais synchroniser avec le balayage vertical, ignorer le choix de l'application") \ + DRI_CONF_ENUM(1,"Ne pas synchroniser avec le balayage vertical par défaut, mais obéir au choix de l'application") \ + DRI_CONF_ENUM(2,"Synchroniser avec le balayage vertical par défaut, mais obéir au choix de l'application") \ + DRI_CONF_ENUM(3,"Toujours synchroniser avec le balayage vertical, l'application choisit l'intervalle minimal") \ + DRI_CONF_DESC_END \ + DRI_CONF_DESC_BEGIN(sv,"Synkronisering med vertikal uppdatering (växlingsintervall)") \ + DRI_CONF_ENUM(0,"Synkronisera aldrig med vertikal uppdatering, ignorera programmets val") \ + DRI_CONF_ENUM(1,"Initialt växlingsintervall 0, följ programmets val") \ + DRI_CONF_ENUM(2,"Initialt växlingsintervall 1, följ programmets val") \ + DRI_CONF_ENUM(3,"Synkronisera alltid med vertikal uppdatering, programmet väljer den minsta växlingsintervallen") \ + DRI_CONF_DESC_END \ +DRI_CONF_OPT_END + +#define DRI_CONF_ADAPTIVE_SYNC(def) \ +DRI_CONF_OPT_BEGIN_B(adaptive_sync,def) \ + DRI_CONF_DESC(en,"Adapt the monitor sync to the application performance (when possible)") \ + DRI_CONF_DESC(de,"Adapt the monitor sync to the application performance (when possible)") \ + DRI_CONF_DESC(es,"Adapt the monitor sync to the application performance (when possible)") \ + DRI_CONF_DESC(nl,"Adapt the monitor sync to the application performance (when possible)") \ + DRI_CONF_DESC(fr,"Adapt the monitor sync to the application performance (when possible)") \ + DRI_CONF_DESC(sv,"Adapt the monitor sync to the application performance (when possible)") \ +DRI_CONF_OPT_END + +#define DRI_CONF_MESA_GLTHREAD(def) \ +DRI_CONF_OPT_BEGIN_B(mesa_glthread, def) \ + DRI_CONF_DESC(en,"Enable offloading GL driver work to a separate thread") \ + DRI_CONF_DESC(de,"Enable offloading GL driver work to a separate thread") \ + DRI_CONF_DESC(es,"Enable offloading GL driver work to a separate thread") \ + DRI_CONF_DESC(nl,"Enable offloading GL driver work to a separate thread") \ + DRI_CONF_DESC(fr,"Enable offloading GL driver work to a separate thread") \ + DRI_CONF_DESC(sv,"Enable offloading GL driver work to a separate thread") \ +DRI_CONF_OPT_END + +#define DRI_CONF_MESA_NO_ERROR(def) \ +DRI_CONF_OPT_BEGIN_B(mesa_no_error, def) \ + DRI_CONF_DESC(en,"Disable GL driver error checking") \ + DRI_CONF_DESC(de,"Disable GL driver error checking") \ + DRI_CONF_DESC(es,"Disable GL driver error checking") \ + DRI_CONF_DESC(nl,"Disable GL driver error checking") \ + DRI_CONF_DESC(fr,"Disable GL driver error checking") \ + DRI_CONF_DESC(sv,"Disable GL driver error checking") \ +DRI_CONF_OPT_END + +#define DRI_CONF_DISABLE_EXT_BUFFER_AGE(def) \ +DRI_CONF_OPT_BEGIN_B(glx_disable_ext_buffer_age, def) \ + DRI_CONF_DESC(en, "Disable the GLX_EXT_buffer_age extension") \ + DRI_CONF_DESC(de, "Disable the GLX_EXT_buffer_age extension") \ + DRI_CONF_DESC(es, "Disable the GLX_EXT_buffer_age extension") \ + DRI_CONF_DESC(nl, "Disable the GLX_EXT_buffer_age extension") \ + DRI_CONF_DESC(fr, "Disable the GLX_EXT_buffer_age extension") \ + DRI_CONF_DESC(sv, "Disable the GLX_EXT_buffer_age extension") \ +DRI_CONF_OPT_END + +#define DRI_CONF_DISABLE_OML_SYNC_CONTROL(def) \ +DRI_CONF_OPT_BEGIN_B(glx_disable_oml_sync_control, def) \ + DRI_CONF_DESC(en, "Disable the GLX_OML_sync_control extension") \ + DRI_CONF_DESC(de, "Disable the GLX_OML_sync_control extension") \ + DRI_CONF_DESC(es, "Disable the GLX_OML_sync_control extension") \ + DRI_CONF_DESC(nl, "Disable the GLX_OML_sync_control extension") \ + DRI_CONF_DESC(fr, "Disable the GLX_OML_sync_control extension") \ + DRI_CONF_DESC(sv, "Disable the GLX_OML_sync_control extension") \ +DRI_CONF_OPT_END + +#define DRI_CONF_DISABLE_SGI_VIDEO_SYNC(def) \ +DRI_CONF_OPT_BEGIN_B(glx_disable_sgi_video_sync, def) \ + DRI_CONF_DESC(en, "Disable the GLX_SGI_video_sync extension") \ + DRI_CONF_DESC(de, "Disable the GLX_SGI_video_sync extension") \ + DRI_CONF_DESC(es, "Disable the GLX_SGI_video_sync extension") \ + DRI_CONF_DESC(nl, "Disable the GLX_SGI_video_sync extension") \ + DRI_CONF_DESC(fr, "Disable the GLX_SGI_video_sync extension") \ + DRI_CONF_DESC(sv, "Disable the GLX_SGI_video_sync extension") \ +DRI_CONF_OPT_END + + + +/** + * \brief Miscellaneous configuration options + */ +#define DRI_CONF_SECTION_MISCELLANEOUS \ +DRI_CONF_SECTION_BEGIN \ + DRI_CONF_DESC(en,"Miscellaneous") \ + DRI_CONF_DESC(de,"Miscellaneous") \ + DRI_CONF_DESC(es,"Misceláneos") \ + DRI_CONF_DESC(nl,"Miscellaneous") \ + DRI_CONF_DESC(fr,"Miscellaneous") \ + DRI_CONF_DESC(sv,"Miscellaneous") + +#define DRI_CONF_ALWAYS_HAVE_DEPTH_BUFFER(def) \ +DRI_CONF_OPT_BEGIN_B(always_have_depth_buffer, def) \ + DRI_CONF_DESC(en,"Create all visuals with a depth buffer") \ + DRI_CONF_DESC(de,"Create all visuals with a depth buffer") \ + DRI_CONF_DESC(es,"Crear todos los visuales con búfer de profundidad") \ + DRI_CONF_DESC(nl,"Create all visuals with a depth buffer") \ + DRI_CONF_DESC(fr,"Create all visuals with a depth buffer") \ + DRI_CONF_DESC(sv,"Create all visuals with a depth buffer") \ +DRI_CONF_OPT_END + +#define DRI_CONF_GLSL_ZERO_INIT(def) \ +DRI_CONF_OPT_BEGIN_B(glsl_zero_init, def) \ + DRI_CONF_DESC(en,"Force uninitialized variables to default to zero") \ + DRI_CONF_DESC(de,"Force uninitialized variables to default to zero") \ + DRI_CONF_DESC(es,"Force uninitialized variables to default to zero") \ + DRI_CONF_DESC(nl,"Force uninitialized variables to default to zero") \ + DRI_CONF_DESC(fr,"Force uninitialized variables to default to zero") \ + DRI_CONF_DESC(sv,"Force uninitialized variables to default to zero") \ +DRI_CONF_OPT_END + +#define DRI_CONF_ALLOW_RGB10_CONFIGS(def) \ +DRI_CONF_OPT_BEGIN_B(allow_rgb10_configs, def) \ +DRI_CONF_DESC(en,"Allow exposure of visuals and fbconfigs with rgb10a2 formats") \ +DRI_CONF_DESC(de,"Allow exposure of visuals and fbconfigs with rgb10a2 formats") \ +DRI_CONF_DESC(es,"Allow exposure of visuals and fbconfigs with rgb10a2 formats") \ +DRI_CONF_DESC(nl,"Allow exposure of visuals and fbconfigs with rgb10a2 formats") \ +DRI_CONF_DESC(fr,"Allow exposure of visuals and fbconfigs with rgb10a2 formats") \ +DRI_CONF_DESC(sv,"Allow exposure of visuals and fbconfigs with rgb10a2 formats") \ +DRI_CONF_OPT_END + +/** + * \brief Initialization configuration options + */ +#define DRI_CONF_SECTION_INITIALIZATION \ +DRI_CONF_SECTION_BEGIN \ + DRI_CONF_DESC(en,"Initialization") \ + DRI_CONF_DESC(de,"Initialization") \ + DRI_CONF_DESC(es,"Inicialización") \ + DRI_CONF_DESC(nl,"Initialization") \ + DRI_CONF_DESC(fr,"Initialization") \ + DRI_CONF_DESC(sv,"Initialization") + +#define DRI_CONF_DEVICE_ID_PATH_TAG(def) \ +DRI_CONF_OPT_BEGIN(device_id, string, def) \ + DRI_CONF_DESC(en,"Define the graphic device to use if possible") \ + DRI_CONF_DESC(de,"Define the graphic device to use if possible") \ + DRI_CONF_DESC(es,"Define el dispositivo de gráficos que usar si es posible") \ + DRI_CONF_DESC(nl,"Define the graphic device to use if possible") \ + DRI_CONF_DESC(fr,"Define the graphic device to use if possible") \ + DRI_CONF_DESC(sv,"Define the graphic device to use if possible") \ +DRI_CONF_OPT_END + +#define DRI_CONF_DRI_DRIVER(def) \ +DRI_CONF_OPT_BEGIN(dri_driver, string, def) \ + DRI_CONF_DESC(en,"Override the DRI driver to load") \ + DRI_CONF_DESC(de,"Override the DRI driver to load") \ + DRI_CONF_DESC(es,"Override the DRI driver to load") \ + DRI_CONF_DESC(nl,"Override the DRI driver to load") \ + DRI_CONF_DESC(fr,"Override the DRI driver to load") \ + DRI_CONF_DESC(sv,"Override the DRI driver to load") \ +DRI_CONF_OPT_END + +/** + * \brief Gallium-Nine specific configuration options + */ + +#define DRI_CONF_SECTION_NINE \ +DRI_CONF_SECTION_BEGIN \ + DRI_CONF_DESC(en,"Gallium Nine") \ + DRI_CONF_DESC(de,"Gallium Nine") \ + DRI_CONF_DESC(es,"Gallium Nine") \ + DRI_CONF_DESC(nl,"Gallium Nine") \ + DRI_CONF_DESC(fr,"Gallium Nine") \ + DRI_CONF_DESC(sv,"Gallium Nine") + +#define DRI_CONF_NINE_THROTTLE(def) \ +DRI_CONF_OPT_BEGIN(throttle_value, int, def) \ + DRI_CONF_DESC(en,"Define the throttling value. -1 for no throttling, -2 for default (usually 2), 0 for glfinish behaviour") \ + DRI_CONF_DESC(de,"Define the throttling value. -1 for no throttling, -2 for default (usually 2), 0 for glfinish behaviour") \ + DRI_CONF_DESC(es,"Define el valor de regulación. -1 para no regular, -2 para el por defecto (generalmente 2), 0 para el comportamiento de glfinish") \ + DRI_CONF_DESC(nl,"Define the throttling value. -1 for no throttling, -2 for default (usually 2), 0 for glfinish behaviour") \ + DRI_CONF_DESC(fr,"Define the throttling value. -1 for no throttling, -2 for default (usually 2), 0 for glfinish behaviour") \ + DRI_CONF_DESC(sv,"Define the throttling value. -1 for no throttling, -2 for default (usually 2), 0 for glfinish behaviour") \ +DRI_CONF_OPT_END + +#define DRI_CONF_NINE_THREADSUBMIT(def) \ +DRI_CONF_OPT_BEGIN_B(thread_submit, def) \ + DRI_CONF_DESC(en,"Use an additional thread to submit buffers.") \ + DRI_CONF_DESC(de,"Use an additional thread to submit buffers.") \ + DRI_CONF_DESC(es,"Usar un hilo adicional para entregar los búfer.") \ + DRI_CONF_DESC(nl,"Use an additional thread to submit buffers.") \ + DRI_CONF_DESC(fr,"Use an additional thread to submit buffers.") \ + DRI_CONF_DESC(sv,"Use an additional thread to submit buffers.") \ +DRI_CONF_OPT_END + +#define DRI_CONF_NINE_OVERRIDEVENDOR(def) \ +DRI_CONF_OPT_BEGIN(override_vendorid, int, def) \ + DRI_CONF_DESC(en,"Define the vendor_id to report. This allows faking another hardware vendor.") \ + DRI_CONF_DESC(de,"Define the vendor_id to report. This allows faking another hardware vendor.") \ + DRI_CONF_DESC(es,"Define the vendor_id to report. This allows faking another hardware vendor.") \ + DRI_CONF_DESC(nl,"Define the vendor_id to report. This allows faking another hardware vendor.") \ + DRI_CONF_DESC(fr,"Define the vendor_id to report. This allows faking another hardware vendor.") \ + DRI_CONF_DESC(sv,"Define the vendor_id to report. This allows faking another hardware vendor.") \ +DRI_CONF_OPT_END + +#define DRI_CONF_NINE_ALLOWDISCARDDELAYEDRELEASE(def) \ +DRI_CONF_OPT_BEGIN_B(discard_delayed_release, def) \ + DRI_CONF_DESC(en,"Whether to allow the display server to release buffers with a delay when using d3d's presentation mode DISCARD. Default to true. Set to false if suffering from lag (thread_submit=true can also help in this situation).") \ + DRI_CONF_DESC(de,"Whether to allow the display server to release buffers with a delay when using d3d's presentation mode DISCARD. Default to true. Set to false if suffering from lag (thread_submit=true can also help in this situation).") \ + DRI_CONF_DESC(es,"Whether to allow the display server to release buffers with a delay when using d3d's presentation mode DISCARD. Default to true. Set to false if suffering from lag (thread_submit=true can also help in this situation).") \ + DRI_CONF_DESC(nl,"Whether to allow the display server to release buffers with a delay when using d3d's presentation mode DISCARD. Default to true. Set to false if suffering from lag (thread_submit=true can also help in this situation).") \ + DRI_CONF_DESC(fr,"Whether to allow the display server to release buffers with a delay when using d3d's presentation mode DISCARD. Default to true. Set to false if suffering from lag (thread_submit=true can also help in this situation).") \ + DRI_CONF_DESC(sv,"Whether to allow the display server to release buffers with a delay when using d3d's presentation mode DISCARD. Default to true. Set to false if suffering from lag (thread_submit=true can also help in this situation).") \ +DRI_CONF_OPT_END + +#define DRI_CONF_NINE_TEARFREEDISCARD(def) \ +DRI_CONF_OPT_BEGIN_B(tearfree_discard, def) \ + DRI_CONF_DESC(en,"Whether to make d3d's presentation mode DISCARD (games usually use that mode) Tear Free. If rendering above screen refresh, some frames will get skipped. false by default.") \ + DRI_CONF_DESC(de,"Whether to make d3d's presentation mode DISCARD (games usually use that mode) Tear Free. If rendering above screen refresh, some frames will get skipped. false by default.") \ + DRI_CONF_DESC(es,"Whether to make d3d's presentation mode DISCARD (games usually use that mode) Tear Free. If rendering above screen refresh, some frames will get skipped. false by default.") \ + DRI_CONF_DESC(nl,"Whether to make d3d's presentation mode DISCARD (games usually use that mode) Tear Free. If rendering above screen refresh, some frames will get skipped. false by default.") \ + DRI_CONF_DESC(fr,"Whether to make d3d's presentation mode DISCARD (games usually use that mode) Tear Free. If rendering above screen refresh, some frames will get skipped. false by default.") \ + DRI_CONF_DESC(sv,"Whether to make d3d's presentation mode DISCARD (games usually use that mode) Tear Free. If rendering above screen refresh, some frames will get skipped. false by default.") \ +DRI_CONF_OPT_END + +#define DRI_CONF_NINE_CSMT(def) \ +DRI_CONF_OPT_BEGIN(csmt_force, int, def) \ + DRI_CONF_DESC(en,"If set to 1, force gallium nine CSMT. If set to 0, disable it. By default (-1) CSMT is enabled on known thread-safe drivers.") \ + DRI_CONF_DESC(de,"If set to 1, force gallium nine CSMT. If set to 0, disable it. By default (-1) CSMT is enabled on known thread-safe drivers.") \ + DRI_CONF_DESC(es,"If set to 1, force gallium nine CSMT. If set to 0, disable it. By default (-1) CSMT is enabled on known thread-safe drivers.") \ + DRI_CONF_DESC(nl,"If set to 1, force gallium nine CSMT. If set to 0, disable it. By default (-1) CSMT is enabled on known thread-safe drivers.") \ + DRI_CONF_DESC(fr,"If set to 1, force gallium nine CSMT. If set to 0, disable it. By default (-1) CSMT is enabled on known thread-safe drivers.") \ + DRI_CONF_DESC(sv,"If set to 1, force gallium nine CSMT. If set to 0, disable it. By default (-1) CSMT is enabled on known thread-safe drivers.") \ +DRI_CONF_OPT_END + +/** + * \brief radeonsi specific configuration options + */ + +#define DRI_CONF_RADEONSI_ENABLE_SISCHED(def) \ +DRI_CONF_OPT_BEGIN_B(radeonsi_enable_sisched, def) \ + DRI_CONF_DESC(en,"Use the LLVM sisched option for shader compiles") \ + DRI_CONF_DESC(de,"Use the LLVM sisched option for shader compiles") \ + DRI_CONF_DESC(es,"Use the LLVM sisched option for shader compiles") \ + DRI_CONF_DESC(nl,"Use the LLVM sisched option for shader compiles") \ + DRI_CONF_DESC(fr,"Use the LLVM sisched option for shader compiles") \ + DRI_CONF_DESC(sv,"Use the LLVM sisched option for shader compiles") \ +DRI_CONF_OPT_END + +#define DRI_CONF_RADEONSI_ASSUME_NO_Z_FIGHTS(def) \ +DRI_CONF_OPT_BEGIN_B(radeonsi_assume_no_z_fights, def) \ + DRI_CONF_DESC(en,"Assume no Z fights (enables aggressive out-of-order rasterization to improve performance; may cause rendering errors)") \ + DRI_CONF_DESC(de,"Assume no Z fights (enables aggressive out-of-order rasterization to improve performance; may cause rendering errors)") \ + DRI_CONF_DESC(es,"Assume no Z fights (enables aggressive out-of-order rasterization to improve performance; may cause rendering errors)") \ + DRI_CONF_DESC(nl,"Assume no Z fights (enables aggressive out-of-order rasterization to improve performance; may cause rendering errors)") \ + DRI_CONF_DESC(fr,"Assume no Z fights (enables aggressive out-of-order rasterization to improve performance; may cause rendering errors)") \ + DRI_CONF_DESC(sv,"Assume no Z fights (enables aggressive out-of-order rasterization to improve performance; may cause rendering errors)") \ +DRI_CONF_OPT_END + +#define DRI_CONF_RADEONSI_COMMUTATIVE_BLEND_ADD(def) \ +DRI_CONF_OPT_BEGIN_B(radeonsi_commutative_blend_add, def) \ + DRI_CONF_DESC(en,"Commutative additive blending optimizations (may cause rendering errors)") \ + DRI_CONF_DESC(de,"Commutative additive blending optimizations (may cause rendering errors)") \ + DRI_CONF_DESC(es,"Commutative additive blending optimizations (may cause rendering errors)") \ + DRI_CONF_DESC(nl,"Commutative additive blending optimizations (may cause rendering errors)") \ + DRI_CONF_DESC(fr,"Commutative additive blending optimizations (may cause rendering errors)") \ + DRI_CONF_DESC(sv,"Commutative additive blending optimizations (may cause rendering errors)") \ +DRI_CONF_OPT_END + +#define DRI_CONF_RADEONSI_ZERO_ALL_VRAM_ALLOCS(def) \ +DRI_CONF_OPT_BEGIN_B(radeonsi_zerovram, def) \ + DRI_CONF_DESC(en,"Zero all vram allocations") \ +DRI_CONF_OPT_END + diff --git a/src/util/Android.mk b/src/util/Android.mk index 6d770ca9575..fe26cf035e3 100644 --- a/src/util/Android.mk +++ b/src/util/Android.mk @@ -56,6 +56,8 @@ LOCAL_MODULE := libmesa_util LOCAL_MODULE_CLASS := STATIC_LIBRARIES +prebuilt_intermediates := $(MESA_TOP)/prebuilt-intermediates + intermediates := $(call local-generated-sources-dir) LOCAL_EXPORT_C_INCLUDE_DIRS := $(intermediates) @@ -63,57 +65,12 @@ LOCAL_EXPORT_C_INCLUDE_DIRS := $(intermediates) UTIL_GENERATED_SOURCES := $(addprefix $(intermediates)/,$(MESA_UTIL_GENERATED_FILES)) LOCAL_GENERATED_SOURCES := $(UTIL_GENERATED_SOURCES) +$(intermediates)/xmlpool/options.h: $(prebuilt_intermediates)/xmlpool/options.h + @mkdir -p $(dir $@) + @cp -f $< $@ + MESA_DRI_OPTIONS_H := $(intermediates)/xmlpool/options.h LOCAL_GENERATED_SOURCES += $(MESA_DRI_OPTIONS_H) -# -# Generate options.h from gettext translations. -# - -MESA_DRI_OPTIONS_LANGS := de es nl fr sv -POT := $(intermediates)/xmlpool.pot - -$(POT): $(LOCAL_PATH)/xmlpool/t_options.h - @mkdir -p $(dir $@) - xgettext -L C --from-code utf-8 -o $@ $< - -$(MESA_DRI_OPTIONS_LANGS:%=$(intermediates)/xmlpool/%.po): $(intermediates)/xmlpool/%.po: $(LOCAL_PATH)/xmlpool/%.po $(POT) - lang=$(basename $(notdir $@)); \ - mkdir -p $(dir $@); \ - if [ -f $< ]; then \ - msgmerge -o $@ $^; \ - else \ - msginit -i $(POT) \ - -o $@ \ - --locale=$$lang \ - --no-translator; \ - sed -i -e 's/charset=.*\\n/charset=UTF-8\\n/' $@; \ - fi - -PRIVATE_SCRIPT := $(LOCAL_PATH)/xmlpool/gen_xmlpool.py -PRIVATE_LOCALEDIR := $(intermediates)/xmlpool -PRIVATE_TEMPLATE_HEADER := $(LOCAL_PATH)/xmlpool/t_options.h -PRIVATE_MO_FILES := $(MESA_DRI_OPTIONS_LANGS:%=$(intermediates)/xmlpool/%.gmo) - -LOCAL_GENERATED_SOURCES += $(PRIVATE_MO_FILES) - -$(LOCAL_GENERATED_SOURCES): PRIVATE_PYTHON := $(MESA_PYTHON2) - -$(PRIVATE_MO_FILES): $(intermediates)/xmlpool/%.gmo: $(intermediates)/xmlpool/%.po - mkdir -p $(dir $@) - msgfmt -o $@ $< - -$(UTIL_GENERATED_SOURCES): PRIVATE_CUSTOM_TOOL = $(PRIVATE_PYTHON) $^ > $@ -$(UTIL_GENERATED_SOURCES): $(intermediates)/%.c: $(LOCAL_PATH)/%.py - $(transform-generated-source) - -$(MESA_DRI_OPTIONS_H): PRIVATE_CUSTOM_TOOL = $(PRIVATE_PYTHON) $< \ - --template $(PRIVATE_TEMPLATE_HEADER) \ - --output $@ \ - --localedir $(PRIVATE_LOCALEDIR) \ - --languages $(MESA_DRI_OPTIONS_LANGS) -$(MESA_DRI_OPTIONS_H): $(PRIVATE_SCRIPT) $(PRIVATE_TEMPLATE_HEADER) $(PRIVATE_MO_FILES) - $(transform-generated-source) - include $(MESA_COMMON_MK) include $(BUILD_STATIC_LIBRARY) From 9077a85d5309108ec198e261a1fee80292da4c88 Mon Sep 17 00:00:00 2001 From: renchenglei Date: Fri, 31 May 2019 01:07:31 +0800 Subject: [PATCH 24/27] Add generated file for i965_dri library --- .../compiler/brw_nir_trig_workarounds.c | 196 + prebuilt-intermediates/genxml/genX_bits.h | 239810 +++++++++++++++ prebuilt-intermediates/genxml/genX_xml.h | 14476 + .../glsl/ir_expression_operation.h | 172 + .../glsl/ir_expression_operation_constant.h | 1871 + .../glsl/ir_expression_operation_strings.h | 308 + .../i965_dri_intermediates/brw_oa_metrics.c | 150862 +++++++++ .../i965_dri_intermediates/brw_oa_metrics.h | 41 + .../isl/isl_format_layout.c | 5677 + prebuilt-intermediates/main/format_fallback.c | 352 + prebuilt-intermediates/main/format_pack.c | 11288 + prebuilt-intermediates/main/format_unpack.c | 7654 + .../nir/nir_builder_opcodes.h | 1655 + .../nir/nir_constant_expressions.c | 20610 ++ prebuilt-intermediates/nir/nir_intrinsics.c | 2998 + prebuilt-intermediates/nir/nir_intrinsics.h | 269 + prebuilt-intermediates/nir/nir_opcodes.c | 3862 + prebuilt-intermediates/nir/nir_opcodes.h | 292 + .../nir/nir_opt_algebraic.c | 39316 +++ prebuilt-intermediates/spirv/spirv_info.c | 678 + .../spirv/vtn_gather_types.c | 368 + src/compiler/Android.glsl.gen.mk | 23 +- src/compiler/Android.nir.gen.mk | 72 +- src/intel/Android.compiler.mk | 10 +- src/intel/Android.genxml.mk | 27 +- src/intel/Android.isl.mk | 13 +- src/mesa/Android.gen.mk | 36 +- src/mesa/drivers/dri/i965/Android.mk | 27 +- 28 files changed, 502896 insertions(+), 67 deletions(-) create mode 100644 prebuilt-intermediates/compiler/brw_nir_trig_workarounds.c create mode 100644 prebuilt-intermediates/genxml/genX_bits.h create mode 100644 prebuilt-intermediates/genxml/genX_xml.h create mode 100644 prebuilt-intermediates/glsl/ir_expression_operation.h create mode 100644 prebuilt-intermediates/glsl/ir_expression_operation_constant.h create mode 100644 prebuilt-intermediates/glsl/ir_expression_operation_strings.h create mode 100644 prebuilt-intermediates/i965_dri_intermediates/brw_oa_metrics.c create mode 100644 prebuilt-intermediates/i965_dri_intermediates/brw_oa_metrics.h create mode 100644 prebuilt-intermediates/isl/isl_format_layout.c create mode 100644 prebuilt-intermediates/main/format_fallback.c create mode 100644 prebuilt-intermediates/main/format_pack.c create mode 100644 prebuilt-intermediates/main/format_unpack.c create mode 100644 prebuilt-intermediates/nir/nir_builder_opcodes.h create mode 100644 prebuilt-intermediates/nir/nir_constant_expressions.c create mode 100644 prebuilt-intermediates/nir/nir_intrinsics.c create mode 100644 prebuilt-intermediates/nir/nir_intrinsics.h create mode 100644 prebuilt-intermediates/nir/nir_opcodes.c create mode 100644 prebuilt-intermediates/nir/nir_opcodes.h create mode 100644 prebuilt-intermediates/nir/nir_opt_algebraic.c create mode 100644 prebuilt-intermediates/spirv/spirv_info.c create mode 100644 prebuilt-intermediates/spirv/vtn_gather_types.c diff --git a/prebuilt-intermediates/compiler/brw_nir_trig_workarounds.c b/prebuilt-intermediates/compiler/brw_nir_trig_workarounds.c new file mode 100644 index 00000000000..db90e448dd8 --- /dev/null +++ b/prebuilt-intermediates/compiler/brw_nir_trig_workarounds.c @@ -0,0 +1,196 @@ +#include "brw_nir.h" + +#include "nir.h" +#include "nir_builder.h" +#include "nir_search.h" +#include "nir_search_helpers.h" + +#ifndef NIR_OPT_ALGEBRAIC_STRUCT_DEFS +#define NIR_OPT_ALGEBRAIC_STRUCT_DEFS + +struct transform { + const nir_search_expression *search; + const nir_search_value *replace; + unsigned condition_offset; +}; + +#endif + + +static const nir_search_variable search0_0 = { + { nir_search_value_variable, -1 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fsin, + { &search0_0.value }, + NULL, +}; + +static const nir_search_variable replace0_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace0_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fsin, + { &replace0_0_0.value }, + NULL, +}; + +static const nir_search_constant replace0_1 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x3fefffc115df6556 /* 0.99997 */ }, +}; +static const nir_search_expression replace0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmul, + { &replace0_0.value, &replace0_1.value }, + NULL, +}; + +static const nir_search_variable search1_0 = { + { nir_search_value_variable, -1 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fcos, + { &search1_0.value }, + NULL, +}; + +static const nir_search_variable replace1_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace1_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fcos, + { &replace1_0_0.value }, + NULL, +}; + +static const nir_search_constant replace1_1 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x3fefffc115df6556 /* 0.99997 */ }, +}; +static const nir_search_expression replace1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmul, + { &replace1_0.value, &replace1_1.value }, + NULL, +}; + +static const struct transform brw_nir_apply_trig_workarounds_fcos_xforms[] = { + { &search1, &replace1.value, 0 }, +}; +static const struct transform brw_nir_apply_trig_workarounds_fsin_xforms[] = { + { &search0, &replace0.value, 0 }, +}; + +static bool +brw_nir_apply_trig_workarounds_block(nir_builder *build, nir_block *block, + const bool *condition_flags) +{ + bool progress = false; + + nir_foreach_instr_reverse_safe(instr, block) { + if (instr->type != nir_instr_type_alu) + continue; + + nir_alu_instr *alu = nir_instr_as_alu(instr); + if (!alu->dest.dest.is_ssa) + continue; + + switch (alu->op) { + case nir_op_fcos: + for (unsigned i = 0; i < ARRAY_SIZE(brw_nir_apply_trig_workarounds_fcos_xforms); i++) { + const struct transform *xform = &brw_nir_apply_trig_workarounds_fcos_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_fsin: + for (unsigned i = 0; i < ARRAY_SIZE(brw_nir_apply_trig_workarounds_fsin_xforms); i++) { + const struct transform *xform = &brw_nir_apply_trig_workarounds_fsin_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + default: + break; + } + } + + return progress; +} + +static bool +brw_nir_apply_trig_workarounds_impl(nir_function_impl *impl, const bool *condition_flags) +{ + bool progress = false; + + nir_builder build; + nir_builder_init(&build, impl); + + nir_foreach_block_reverse(block, impl) { + progress |= brw_nir_apply_trig_workarounds_block(&build, block, condition_flags); + } + + if (progress) { + nir_metadata_preserve(impl, nir_metadata_block_index | + nir_metadata_dominance); + } else { +#ifndef NDEBUG + impl->valid_metadata &= ~nir_metadata_not_properly_reset; +#endif + } + + return progress; +} + + +bool +brw_nir_apply_trig_workarounds(nir_shader *shader) +{ + bool progress = false; + bool condition_flags[1]; + const nir_shader_compiler_options *options = shader->options; + (void) options; + + condition_flags[0] = true; + + nir_foreach_function(function, shader) { + if (function->impl) + progress |= brw_nir_apply_trig_workarounds_impl(function->impl, condition_flags); + } + + return progress; +} + diff --git a/prebuilt-intermediates/genxml/genX_bits.h b/prebuilt-intermediates/genxml/genX_bits.h new file mode 100644 index 00000000000..dd3d19e22c3 --- /dev/null +++ b/prebuilt-intermediates/genxml/genX_bits.h @@ -0,0 +1,239810 @@ +/* + * Copyright © 2017 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +/* THIS FILE HAS BEEN GENERATED, DO NOT HAND EDIT. + * + * Sizes of bitfields in genxml instructions, structures, and registers. + */ + +#ifndef GENX_BITS_H +#define GENX_BITS_H + +#include + +#include "dev/gen_device_info.h" +#include "util/macros.h" + + + +#ifdef __cplusplus +extern "C" { +#endif + +/* 3DPRIMITIVE */ + + +#define GEN11_3DPRIMITIVE_length 7 +#define GEN10_3DPRIMITIVE_length 7 +#define GEN9_3DPRIMITIVE_length 7 +#define GEN8_3DPRIMITIVE_length 7 +#define GEN75_3DPRIMITIVE_length 7 +#define GEN7_3DPRIMITIVE_length 7 +#define GEN6_3DPRIMITIVE_length 6 +#define GEN5_3DPRIMITIVE_length 6 +#define GEN45_3DPRIMITIVE_length 6 +#define GEN4_3DPRIMITIVE_length 6 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 7; + } else { + return 7; + } + case 6: return 6; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DPRIMITIVE::3D Command Opcode */ + + +#define GEN11_3DPRIMITIVE_3DCommandOpcode_bits 3 +#define GEN10_3DPRIMITIVE_3DCommandOpcode_bits 3 +#define GEN9_3DPRIMITIVE_3DCommandOpcode_bits 3 +#define GEN8_3DPRIMITIVE_3DCommandOpcode_bits 3 +#define GEN75_3DPRIMITIVE_3DCommandOpcode_bits 3 +#define GEN7_3DPRIMITIVE_3DCommandOpcode_bits 3 +#define GEN6_3DPRIMITIVE_3DCommandOpcode_bits 3 +#define GEN5_3DPRIMITIVE_3DCommandOpcode_bits 3 +#define GEN45_3DPRIMITIVE_3DCommandOpcode_bits 3 +#define GEN4_3DPRIMITIVE_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DPRIMITIVE_3DCommandOpcode_start 24 +#define GEN10_3DPRIMITIVE_3DCommandOpcode_start 24 +#define GEN9_3DPRIMITIVE_3DCommandOpcode_start 24 +#define GEN8_3DPRIMITIVE_3DCommandOpcode_start 24 +#define GEN75_3DPRIMITIVE_3DCommandOpcode_start 24 +#define GEN7_3DPRIMITIVE_3DCommandOpcode_start 24 +#define GEN6_3DPRIMITIVE_3DCommandOpcode_start 24 +#define GEN5_3DPRIMITIVE_3DCommandOpcode_start 24 +#define GEN45_3DPRIMITIVE_3DCommandOpcode_start 24 +#define GEN4_3DPRIMITIVE_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 24; + case 4: + if (devinfo->is_g4x) { + return 24; + } else { + return 24; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DPRIMITIVE::3D Command Sub Opcode */ + + +#define GEN11_3DPRIMITIVE_3DCommandSubOpcode_bits 8 +#define GEN10_3DPRIMITIVE_3DCommandSubOpcode_bits 8 +#define GEN9_3DPRIMITIVE_3DCommandSubOpcode_bits 8 +#define GEN8_3DPRIMITIVE_3DCommandSubOpcode_bits 8 +#define GEN75_3DPRIMITIVE_3DCommandSubOpcode_bits 8 +#define GEN7_3DPRIMITIVE_3DCommandSubOpcode_bits 8 +#define GEN6_3DPRIMITIVE_3DCommandSubOpcode_bits 8 +#define GEN5_3DPRIMITIVE_3DCommandSubOpcode_bits 8 +#define GEN45_3DPRIMITIVE_3DCommandSubOpcode_bits 8 +#define GEN4_3DPRIMITIVE_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DPRIMITIVE_3DCommandSubOpcode_start 16 +#define GEN10_3DPRIMITIVE_3DCommandSubOpcode_start 16 +#define GEN9_3DPRIMITIVE_3DCommandSubOpcode_start 16 +#define GEN8_3DPRIMITIVE_3DCommandSubOpcode_start 16 +#define GEN75_3DPRIMITIVE_3DCommandSubOpcode_start 16 +#define GEN7_3DPRIMITIVE_3DCommandSubOpcode_start 16 +#define GEN6_3DPRIMITIVE_3DCommandSubOpcode_start 16 +#define GEN5_3DPRIMITIVE_3DCommandSubOpcode_start 16 +#define GEN45_3DPRIMITIVE_3DCommandSubOpcode_start 16 +#define GEN4_3DPRIMITIVE_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DPRIMITIVE::Base Vertex Location */ + + +#define GEN11_3DPRIMITIVE_BaseVertexLocation_bits 32 +#define GEN10_3DPRIMITIVE_BaseVertexLocation_bits 32 +#define GEN9_3DPRIMITIVE_BaseVertexLocation_bits 32 +#define GEN8_3DPRIMITIVE_BaseVertexLocation_bits 32 +#define GEN75_3DPRIMITIVE_BaseVertexLocation_bits 32 +#define GEN7_3DPRIMITIVE_BaseVertexLocation_bits 32 +#define GEN6_3DPRIMITIVE_BaseVertexLocation_bits 32 +#define GEN5_3DPRIMITIVE_BaseVertexLocation_bits 32 +#define GEN45_3DPRIMITIVE_BaseVertexLocation_bits 32 +#define GEN4_3DPRIMITIVE_BaseVertexLocation_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_BaseVertexLocation_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DPRIMITIVE_BaseVertexLocation_start 192 +#define GEN10_3DPRIMITIVE_BaseVertexLocation_start 192 +#define GEN9_3DPRIMITIVE_BaseVertexLocation_start 192 +#define GEN8_3DPRIMITIVE_BaseVertexLocation_start 192 +#define GEN75_3DPRIMITIVE_BaseVertexLocation_start 192 +#define GEN7_3DPRIMITIVE_BaseVertexLocation_start 192 +#define GEN6_3DPRIMITIVE_BaseVertexLocation_start 160 +#define GEN5_3DPRIMITIVE_BaseVertexLocation_start 160 +#define GEN45_3DPRIMITIVE_BaseVertexLocation_start 160 +#define GEN4_3DPRIMITIVE_BaseVertexLocation_start 160 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_BaseVertexLocation_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 192; + case 10: return 192; + case 9: return 192; + case 8: return 192; + case 7: + if (devinfo->is_haswell) { + return 192; + } else { + return 192; + } + case 6: return 160; + case 5: return 160; + case 4: + if (devinfo->is_g4x) { + return 160; + } else { + return 160; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DPRIMITIVE::Command SubType */ + + +#define GEN11_3DPRIMITIVE_CommandSubType_bits 2 +#define GEN10_3DPRIMITIVE_CommandSubType_bits 2 +#define GEN9_3DPRIMITIVE_CommandSubType_bits 2 +#define GEN8_3DPRIMITIVE_CommandSubType_bits 2 +#define GEN75_3DPRIMITIVE_CommandSubType_bits 2 +#define GEN7_3DPRIMITIVE_CommandSubType_bits 2 +#define GEN6_3DPRIMITIVE_CommandSubType_bits 2 +#define GEN5_3DPRIMITIVE_CommandSubType_bits 2 +#define GEN45_3DPRIMITIVE_CommandSubType_bits 2 +#define GEN4_3DPRIMITIVE_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DPRIMITIVE_CommandSubType_start 27 +#define GEN10_3DPRIMITIVE_CommandSubType_start 27 +#define GEN9_3DPRIMITIVE_CommandSubType_start 27 +#define GEN8_3DPRIMITIVE_CommandSubType_start 27 +#define GEN75_3DPRIMITIVE_CommandSubType_start 27 +#define GEN7_3DPRIMITIVE_CommandSubType_start 27 +#define GEN6_3DPRIMITIVE_CommandSubType_start 27 +#define GEN5_3DPRIMITIVE_CommandSubType_start 27 +#define GEN45_3DPRIMITIVE_CommandSubType_start 27 +#define GEN4_3DPRIMITIVE_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DPRIMITIVE::Command Type */ + + +#define GEN11_3DPRIMITIVE_CommandType_bits 3 +#define GEN10_3DPRIMITIVE_CommandType_bits 3 +#define GEN9_3DPRIMITIVE_CommandType_bits 3 +#define GEN8_3DPRIMITIVE_CommandType_bits 3 +#define GEN75_3DPRIMITIVE_CommandType_bits 3 +#define GEN7_3DPRIMITIVE_CommandType_bits 3 +#define GEN6_3DPRIMITIVE_CommandType_bits 3 +#define GEN5_3DPRIMITIVE_CommandType_bits 3 +#define GEN45_3DPRIMITIVE_CommandType_bits 3 +#define GEN4_3DPRIMITIVE_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DPRIMITIVE_CommandType_start 29 +#define GEN10_3DPRIMITIVE_CommandType_start 29 +#define GEN9_3DPRIMITIVE_CommandType_start 29 +#define GEN8_3DPRIMITIVE_CommandType_start 29 +#define GEN75_3DPRIMITIVE_CommandType_start 29 +#define GEN7_3DPRIMITIVE_CommandType_start 29 +#define GEN6_3DPRIMITIVE_CommandType_start 29 +#define GEN5_3DPRIMITIVE_CommandType_start 29 +#define GEN45_3DPRIMITIVE_CommandType_start 29 +#define GEN4_3DPRIMITIVE_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 29; + case 4: + if (devinfo->is_g4x) { + return 29; + } else { + return 29; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DPRIMITIVE::DWord Length */ + + +#define GEN11_3DPRIMITIVE_DWordLength_bits 8 +#define GEN10_3DPRIMITIVE_DWordLength_bits 8 +#define GEN9_3DPRIMITIVE_DWordLength_bits 8 +#define GEN8_3DPRIMITIVE_DWordLength_bits 8 +#define GEN75_3DPRIMITIVE_DWordLength_bits 8 +#define GEN7_3DPRIMITIVE_DWordLength_bits 8 +#define GEN6_3DPRIMITIVE_DWordLength_bits 8 +#define GEN5_3DPRIMITIVE_DWordLength_bits 8 +#define GEN45_3DPRIMITIVE_DWordLength_bits 8 +#define GEN4_3DPRIMITIVE_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DPRIMITIVE_DWordLength_start 0 +#define GEN10_3DPRIMITIVE_DWordLength_start 0 +#define GEN9_3DPRIMITIVE_DWordLength_start 0 +#define GEN8_3DPRIMITIVE_DWordLength_start 0 +#define GEN75_3DPRIMITIVE_DWordLength_start 0 +#define GEN7_3DPRIMITIVE_DWordLength_start 0 +#define GEN6_3DPRIMITIVE_DWordLength_start 0 +#define GEN5_3DPRIMITIVE_DWordLength_start 0 +#define GEN45_3DPRIMITIVE_DWordLength_start 0 +#define GEN4_3DPRIMITIVE_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DPRIMITIVE::End Offset Enable */ + + +#define GEN11_3DPRIMITIVE_EndOffsetEnable_bits 1 +#define GEN10_3DPRIMITIVE_EndOffsetEnable_bits 1 +#define GEN9_3DPRIMITIVE_EndOffsetEnable_bits 1 +#define GEN8_3DPRIMITIVE_EndOffsetEnable_bits 1 +#define GEN75_3DPRIMITIVE_EndOffsetEnable_bits 1 +#define GEN7_3DPRIMITIVE_EndOffsetEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_EndOffsetEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DPRIMITIVE_EndOffsetEnable_start 41 +#define GEN10_3DPRIMITIVE_EndOffsetEnable_start 41 +#define GEN9_3DPRIMITIVE_EndOffsetEnable_start 41 +#define GEN8_3DPRIMITIVE_EndOffsetEnable_start 41 +#define GEN75_3DPRIMITIVE_EndOffsetEnable_start 41 +#define GEN7_3DPRIMITIVE_EndOffsetEnable_start 41 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_EndOffsetEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 41; + case 10: return 41; + case 9: return 41; + case 8: return 41; + case 7: + if (devinfo->is_haswell) { + return 41; + } else { + return 41; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DPRIMITIVE::Extended Parameter 0 */ + + +#define GEN11_3DPRIMITIVE_ExtendedParameter0_bits 32 +#define GEN10_3DPRIMITIVE_ExtendedParameter0_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_ExtendedParameter0_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DPRIMITIVE_ExtendedParameter0_start 224 +#define GEN10_3DPRIMITIVE_ExtendedParameter0_start 224 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_ExtendedParameter0_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 224; + case 10: return 224; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DPRIMITIVE::Extended Parameter 1 */ + + +#define GEN11_3DPRIMITIVE_ExtendedParameter1_bits 32 +#define GEN10_3DPRIMITIVE_ExtendedParameter1_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_ExtendedParameter1_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DPRIMITIVE_ExtendedParameter1_start 256 +#define GEN10_3DPRIMITIVE_ExtendedParameter1_start 256 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_ExtendedParameter1_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 256; + case 10: return 256; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DPRIMITIVE::Extended Parameter 2 */ + + +#define GEN11_3DPRIMITIVE_ExtendedParameter2_bits 32 +#define GEN10_3DPRIMITIVE_ExtendedParameter2_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_ExtendedParameter2_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DPRIMITIVE_ExtendedParameter2_start 288 +#define GEN10_3DPRIMITIVE_ExtendedParameter2_start 288 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_ExtendedParameter2_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 288; + case 10: return 288; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DPRIMITIVE::Extended Parameters Present */ + + +#define GEN11_3DPRIMITIVE_ExtendedParametersPresent_bits 1 +#define GEN10_3DPRIMITIVE_ExtendedParametersPresent_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_ExtendedParametersPresent_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DPRIMITIVE_ExtendedParametersPresent_start 11 +#define GEN10_3DPRIMITIVE_ExtendedParametersPresent_start 11 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_ExtendedParametersPresent_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DPRIMITIVE::Indirect Parameter Enable */ + + +#define GEN11_3DPRIMITIVE_IndirectParameterEnable_bits 1 +#define GEN10_3DPRIMITIVE_IndirectParameterEnable_bits 1 +#define GEN9_3DPRIMITIVE_IndirectParameterEnable_bits 1 +#define GEN8_3DPRIMITIVE_IndirectParameterEnable_bits 1 +#define GEN75_3DPRIMITIVE_IndirectParameterEnable_bits 1 +#define GEN7_3DPRIMITIVE_IndirectParameterEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_IndirectParameterEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DPRIMITIVE_IndirectParameterEnable_start 10 +#define GEN10_3DPRIMITIVE_IndirectParameterEnable_start 10 +#define GEN9_3DPRIMITIVE_IndirectParameterEnable_start 10 +#define GEN8_3DPRIMITIVE_IndirectParameterEnable_start 10 +#define GEN75_3DPRIMITIVE_IndirectParameterEnable_start 10 +#define GEN7_3DPRIMITIVE_IndirectParameterEnable_start 10 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_IndirectParameterEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 10; + case 10: return 10; + case 9: return 10; + case 8: return 10; + case 7: + if (devinfo->is_haswell) { + return 10; + } else { + return 10; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DPRIMITIVE::Indirect Vertex Count */ + + +#define GEN5_3DPRIMITIVE_IndirectVertexCount_bits 1 +#define GEN45_3DPRIMITIVE_IndirectVertexCount_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_IndirectVertexCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_3DPRIMITIVE_IndirectVertexCount_start 9 +#define GEN45_3DPRIMITIVE_IndirectVertexCount_start 9 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_IndirectVertexCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 9; + case 4: + if (devinfo->is_g4x) { + return 9; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DPRIMITIVE::Instance Count */ + + +#define GEN11_3DPRIMITIVE_InstanceCount_bits 32 +#define GEN10_3DPRIMITIVE_InstanceCount_bits 32 +#define GEN9_3DPRIMITIVE_InstanceCount_bits 32 +#define GEN8_3DPRIMITIVE_InstanceCount_bits 32 +#define GEN75_3DPRIMITIVE_InstanceCount_bits 32 +#define GEN7_3DPRIMITIVE_InstanceCount_bits 32 +#define GEN6_3DPRIMITIVE_InstanceCount_bits 32 +#define GEN5_3DPRIMITIVE_InstanceCount_bits 32 +#define GEN45_3DPRIMITIVE_InstanceCount_bits 32 +#define GEN4_3DPRIMITIVE_InstanceCount_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_InstanceCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DPRIMITIVE_InstanceCount_start 128 +#define GEN10_3DPRIMITIVE_InstanceCount_start 128 +#define GEN9_3DPRIMITIVE_InstanceCount_start 128 +#define GEN8_3DPRIMITIVE_InstanceCount_start 128 +#define GEN75_3DPRIMITIVE_InstanceCount_start 128 +#define GEN7_3DPRIMITIVE_InstanceCount_start 128 +#define GEN6_3DPRIMITIVE_InstanceCount_start 96 +#define GEN5_3DPRIMITIVE_InstanceCount_start 96 +#define GEN45_3DPRIMITIVE_InstanceCount_start 96 +#define GEN4_3DPRIMITIVE_InstanceCount_start 96 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_InstanceCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 128; + case 10: return 128; + case 9: return 128; + case 8: return 128; + case 7: + if (devinfo->is_haswell) { + return 128; + } else { + return 128; + } + case 6: return 96; + case 5: return 96; + case 4: + if (devinfo->is_g4x) { + return 96; + } else { + return 96; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DPRIMITIVE::Internal Vertex Count */ + + +#define GEN6_3DPRIMITIVE_InternalVertexCount_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_InternalVertexCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DPRIMITIVE_InternalVertexCount_start 9 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_InternalVertexCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 9; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DPRIMITIVE::Predicate Enable */ + + +#define GEN11_3DPRIMITIVE_PredicateEnable_bits 1 +#define GEN10_3DPRIMITIVE_PredicateEnable_bits 1 +#define GEN9_3DPRIMITIVE_PredicateEnable_bits 1 +#define GEN8_3DPRIMITIVE_PredicateEnable_bits 1 +#define GEN75_3DPRIMITIVE_PredicateEnable_bits 1 +#define GEN7_3DPRIMITIVE_PredicateEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_PredicateEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DPRIMITIVE_PredicateEnable_start 8 +#define GEN10_3DPRIMITIVE_PredicateEnable_start 8 +#define GEN9_3DPRIMITIVE_PredicateEnable_start 8 +#define GEN8_3DPRIMITIVE_PredicateEnable_start 8 +#define GEN75_3DPRIMITIVE_PredicateEnable_start 8 +#define GEN7_3DPRIMITIVE_PredicateEnable_start 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_PredicateEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DPRIMITIVE::Primitive Topology Type */ + + +#define GEN11_3DPRIMITIVE_PrimitiveTopologyType_bits 6 +#define GEN10_3DPRIMITIVE_PrimitiveTopologyType_bits 6 +#define GEN9_3DPRIMITIVE_PrimitiveTopologyType_bits 6 +#define GEN8_3DPRIMITIVE_PrimitiveTopologyType_bits 6 +#define GEN75_3DPRIMITIVE_PrimitiveTopologyType_bits 6 +#define GEN7_3DPRIMITIVE_PrimitiveTopologyType_bits 6 +#define GEN6_3DPRIMITIVE_PrimitiveTopologyType_bits 5 +#define GEN5_3DPRIMITIVE_PrimitiveTopologyType_bits 5 +#define GEN45_3DPRIMITIVE_PrimitiveTopologyType_bits 5 +#define GEN4_3DPRIMITIVE_PrimitiveTopologyType_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_PrimitiveTopologyType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 5; + case 5: return 5; + case 4: + if (devinfo->is_g4x) { + return 5; + } else { + return 5; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DPRIMITIVE_PrimitiveTopologyType_start 32 +#define GEN10_3DPRIMITIVE_PrimitiveTopologyType_start 32 +#define GEN9_3DPRIMITIVE_PrimitiveTopologyType_start 32 +#define GEN8_3DPRIMITIVE_PrimitiveTopologyType_start 32 +#define GEN75_3DPRIMITIVE_PrimitiveTopologyType_start 32 +#define GEN7_3DPRIMITIVE_PrimitiveTopologyType_start 32 +#define GEN6_3DPRIMITIVE_PrimitiveTopologyType_start 10 +#define GEN5_3DPRIMITIVE_PrimitiveTopologyType_start 10 +#define GEN45_3DPRIMITIVE_PrimitiveTopologyType_start 10 +#define GEN4_3DPRIMITIVE_PrimitiveTopologyType_start 10 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_PrimitiveTopologyType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 10; + case 5: return 10; + case 4: + if (devinfo->is_g4x) { + return 10; + } else { + return 10; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DPRIMITIVE::Start Instance Location */ + + +#define GEN11_3DPRIMITIVE_StartInstanceLocation_bits 32 +#define GEN10_3DPRIMITIVE_StartInstanceLocation_bits 32 +#define GEN9_3DPRIMITIVE_StartInstanceLocation_bits 32 +#define GEN8_3DPRIMITIVE_StartInstanceLocation_bits 32 +#define GEN75_3DPRIMITIVE_StartInstanceLocation_bits 32 +#define GEN7_3DPRIMITIVE_StartInstanceLocation_bits 32 +#define GEN6_3DPRIMITIVE_StartInstanceLocation_bits 32 +#define GEN5_3DPRIMITIVE_StartInstanceLocation_bits 32 +#define GEN45_3DPRIMITIVE_StartInstanceLocation_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_StartInstanceLocation_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DPRIMITIVE_StartInstanceLocation_start 160 +#define GEN10_3DPRIMITIVE_StartInstanceLocation_start 160 +#define GEN9_3DPRIMITIVE_StartInstanceLocation_start 160 +#define GEN8_3DPRIMITIVE_StartInstanceLocation_start 160 +#define GEN75_3DPRIMITIVE_StartInstanceLocation_start 160 +#define GEN7_3DPRIMITIVE_StartInstanceLocation_start 160 +#define GEN6_3DPRIMITIVE_StartInstanceLocation_start 128 +#define GEN5_3DPRIMITIVE_StartInstanceLocation_start 128 +#define GEN45_3DPRIMITIVE_StartInstanceLocation_start 128 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_StartInstanceLocation_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 160; + case 10: return 160; + case 9: return 160; + case 8: return 160; + case 7: + if (devinfo->is_haswell) { + return 160; + } else { + return 160; + } + case 6: return 128; + case 5: return 128; + case 4: + if (devinfo->is_g4x) { + return 128; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DPRIMITIVE::Start Vertex Location */ + + +#define GEN11_3DPRIMITIVE_StartVertexLocation_bits 32 +#define GEN10_3DPRIMITIVE_StartVertexLocation_bits 32 +#define GEN9_3DPRIMITIVE_StartVertexLocation_bits 32 +#define GEN8_3DPRIMITIVE_StartVertexLocation_bits 32 +#define GEN75_3DPRIMITIVE_StartVertexLocation_bits 32 +#define GEN7_3DPRIMITIVE_StartVertexLocation_bits 32 +#define GEN6_3DPRIMITIVE_StartVertexLocation_bits 32 +#define GEN5_3DPRIMITIVE_StartVertexLocation_bits 32 +#define GEN45_3DPRIMITIVE_StartVertexLocation_bits 32 +#define GEN4_3DPRIMITIVE_StartVertexLocation_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_StartVertexLocation_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DPRIMITIVE_StartVertexLocation_start 96 +#define GEN10_3DPRIMITIVE_StartVertexLocation_start 96 +#define GEN9_3DPRIMITIVE_StartVertexLocation_start 96 +#define GEN8_3DPRIMITIVE_StartVertexLocation_start 96 +#define GEN75_3DPRIMITIVE_StartVertexLocation_start 96 +#define GEN7_3DPRIMITIVE_StartVertexLocation_start 96 +#define GEN6_3DPRIMITIVE_StartVertexLocation_start 64 +#define GEN5_3DPRIMITIVE_StartVertexLocation_start 64 +#define GEN45_3DPRIMITIVE_StartVertexLocation_start 64 +#define GEN4_3DPRIMITIVE_StartVertexLocation_start 64 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_StartVertexLocation_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 96; + case 10: return 96; + case 9: return 96; + case 8: return 96; + case 7: + if (devinfo->is_haswell) { + return 96; + } else { + return 96; + } + case 6: return 64; + case 5: return 64; + case 4: + if (devinfo->is_g4x) { + return 64; + } else { + return 64; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DPRIMITIVE::UAV Coherency Required */ + + +#define GEN11_3DPRIMITIVE_UAVCoherencyRequired_bits 1 +#define GEN10_3DPRIMITIVE_UAVCoherencyRequired_bits 1 +#define GEN9_3DPRIMITIVE_UAVCoherencyRequired_bits 1 +#define GEN8_3DPRIMITIVE_UAVCoherencyRequired_bits 1 +#define GEN75_3DPRIMITIVE_UAVCoherencyRequired_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_UAVCoherencyRequired_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DPRIMITIVE_UAVCoherencyRequired_start 9 +#define GEN10_3DPRIMITIVE_UAVCoherencyRequired_start 9 +#define GEN9_3DPRIMITIVE_UAVCoherencyRequired_start 9 +#define GEN8_3DPRIMITIVE_UAVCoherencyRequired_start 9 +#define GEN75_3DPRIMITIVE_UAVCoherencyRequired_start 9 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_UAVCoherencyRequired_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 9; + case 10: return 9; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DPRIMITIVE::Vertex Access Type */ + + +#define GEN11_3DPRIMITIVE_VertexAccessType_bits 1 +#define GEN10_3DPRIMITIVE_VertexAccessType_bits 1 +#define GEN9_3DPRIMITIVE_VertexAccessType_bits 1 +#define GEN8_3DPRIMITIVE_VertexAccessType_bits 1 +#define GEN75_3DPRIMITIVE_VertexAccessType_bits 1 +#define GEN7_3DPRIMITIVE_VertexAccessType_bits 1 +#define GEN6_3DPRIMITIVE_VertexAccessType_bits 1 +#define GEN5_3DPRIMITIVE_VertexAccessType_bits 1 +#define GEN45_3DPRIMITIVE_VertexAccessType_bits 1 +#define GEN4_3DPRIMITIVE_VertexAccessType_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_VertexAccessType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DPRIMITIVE_VertexAccessType_start 40 +#define GEN10_3DPRIMITIVE_VertexAccessType_start 40 +#define GEN9_3DPRIMITIVE_VertexAccessType_start 40 +#define GEN8_3DPRIMITIVE_VertexAccessType_start 40 +#define GEN75_3DPRIMITIVE_VertexAccessType_start 40 +#define GEN7_3DPRIMITIVE_VertexAccessType_start 40 +#define GEN6_3DPRIMITIVE_VertexAccessType_start 15 +#define GEN5_3DPRIMITIVE_VertexAccessType_start 15 +#define GEN45_3DPRIMITIVE_VertexAccessType_start 15 +#define GEN4_3DPRIMITIVE_VertexAccessType_start 15 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_VertexAccessType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 40; + case 10: return 40; + case 9: return 40; + case 8: return 40; + case 7: + if (devinfo->is_haswell) { + return 40; + } else { + return 40; + } + case 6: return 15; + case 5: return 15; + case 4: + if (devinfo->is_g4x) { + return 15; + } else { + return 15; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DPRIMITIVE::Vertex Count Per Instance */ + + +#define GEN11_3DPRIMITIVE_VertexCountPerInstance_bits 32 +#define GEN10_3DPRIMITIVE_VertexCountPerInstance_bits 32 +#define GEN9_3DPRIMITIVE_VertexCountPerInstance_bits 32 +#define GEN8_3DPRIMITIVE_VertexCountPerInstance_bits 32 +#define GEN75_3DPRIMITIVE_VertexCountPerInstance_bits 32 +#define GEN7_3DPRIMITIVE_VertexCountPerInstance_bits 32 +#define GEN6_3DPRIMITIVE_VertexCountPerInstance_bits 32 +#define GEN5_3DPRIMITIVE_VertexCountPerInstance_bits 32 +#define GEN45_3DPRIMITIVE_VertexCountPerInstance_bits 32 +#define GEN4_3DPRIMITIVE_VertexCountPerInstance_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_VertexCountPerInstance_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DPRIMITIVE_VertexCountPerInstance_start 64 +#define GEN10_3DPRIMITIVE_VertexCountPerInstance_start 64 +#define GEN9_3DPRIMITIVE_VertexCountPerInstance_start 64 +#define GEN8_3DPRIMITIVE_VertexCountPerInstance_start 64 +#define GEN75_3DPRIMITIVE_VertexCountPerInstance_start 64 +#define GEN7_3DPRIMITIVE_VertexCountPerInstance_start 64 +#define GEN6_3DPRIMITIVE_VertexCountPerInstance_start 32 +#define GEN5_3DPRIMITIVE_VertexCountPerInstance_start 32 +#define GEN45_3DPRIMITIVE_VertexCountPerInstance_start 32 +#define GEN4_3DPRIMITIVE_VertexCountPerInstance_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DPRIMITIVE_VertexCountPerInstance_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_3D_MODE */ + + +#define GEN11_3DSTATE_3D_MODE_length 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_3D_MODE_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_3D_MODE::3D Command Opcode */ + + +#define GEN11_3DSTATE_3D_MODE_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_3D_MODE_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_3D_MODE_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_3D_MODE_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_3D_MODE::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_3D_MODE_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_3D_MODE_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_3D_MODE_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_3D_MODE_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_3D_MODE::Command SubType */ + + +#define GEN11_3DSTATE_3D_MODE_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_3D_MODE_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_3D_MODE_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_3D_MODE_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_3D_MODE::Command Type */ + + +#define GEN11_3DSTATE_3D_MODE_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_3D_MODE_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_3D_MODE_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_3D_MODE_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_3D_MODE::DWord Length */ + + +#define GEN11_3DSTATE_3D_MODE_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_3D_MODE_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_3D_MODE_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_3D_MODE_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_3D_MODE::Mask Bits */ + + +#define GEN11_3DSTATE_3D_MODE_MaskBits_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_3D_MODE_MaskBits_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_3D_MODE_MaskBits_start 48 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_3D_MODE_MaskBits_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_AA_LINE_PARAMETERS */ + + +#define GEN11_3DSTATE_AA_LINE_PARAMETERS_length 3 +#define GEN10_3DSTATE_AA_LINE_PARAMETERS_length 3 +#define GEN9_3DSTATE_AA_LINE_PARAMETERS_length 3 +#define GEN8_3DSTATE_AA_LINE_PARAMETERS_length 3 +#define GEN75_3DSTATE_AA_LINE_PARAMETERS_length 3 +#define GEN7_3DSTATE_AA_LINE_PARAMETERS_length 3 +#define GEN6_3DSTATE_AA_LINE_PARAMETERS_length 3 +#define GEN5_3DSTATE_AA_LINE_PARAMETERS_length 3 +#define GEN45_3DSTATE_AA_LINE_PARAMETERS_length 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_AA_LINE_PARAMETERS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_AA_LINE_PARAMETERS::3D Command Opcode */ + + +#define GEN11_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits 3 +#define GEN6_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits 3 +#define GEN5_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits 3 +#define GEN45_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start 24 +#define GEN6_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start 24 +#define GEN5_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start 24 +#define GEN45_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_AA_LINE_PARAMETERS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 24; + case 4: + if (devinfo->is_g4x) { + return 24; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_AA_LINE_PARAMETERS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits 8 +#define GEN6_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits 8 +#define GEN5_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits 8 +#define GEN45_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start 16 +#define GEN6_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start 16 +#define GEN5_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start 16 +#define GEN45_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_AA_LINE_PARAMETERS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_AA_LINE_PARAMETERS::AA Coverage Bias */ + + +#define GEN11_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits 8 +#define GEN10_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits 8 +#define GEN9_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits 8 +#define GEN8_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits 8 +#define GEN75_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits 8 +#define GEN7_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits 8 +#define GEN6_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits 8 +#define GEN5_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits 8 +#define GEN45_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start 48 +#define GEN10_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start 48 +#define GEN9_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start 48 +#define GEN8_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start 48 +#define GEN75_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start 48 +#define GEN7_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start 48 +#define GEN6_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start 48 +#define GEN5_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start 48 +#define GEN45_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start 48 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_AA_LINE_PARAMETERS_AACoverageBias_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 48; + case 7: + if (devinfo->is_haswell) { + return 48; + } else { + return 48; + } + case 6: return 48; + case 5: return 48; + case 4: + if (devinfo->is_g4x) { + return 48; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_AA_LINE_PARAMETERS::AA Coverage EndCap Bias */ + + +#define GEN11_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits 8 +#define GEN10_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits 8 +#define GEN9_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits 8 +#define GEN8_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits 8 +#define GEN75_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits 8 +#define GEN7_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits 8 +#define GEN6_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits 8 +#define GEN5_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits 8 +#define GEN45_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start 80 +#define GEN10_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start 80 +#define GEN9_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start 80 +#define GEN8_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start 80 +#define GEN75_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start 80 +#define GEN7_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start 80 +#define GEN6_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start 80 +#define GEN5_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start 80 +#define GEN45_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start 80 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapBias_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 80; + case 10: return 80; + case 9: return 80; + case 8: return 80; + case 7: + if (devinfo->is_haswell) { + return 80; + } else { + return 80; + } + case 6: return 80; + case 5: return 80; + case 4: + if (devinfo->is_g4x) { + return 80; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_AA_LINE_PARAMETERS::AA Coverage EndCap Slope */ + + +#define GEN11_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits 8 +#define GEN10_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits 8 +#define GEN9_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits 8 +#define GEN8_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits 8 +#define GEN75_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits 8 +#define GEN7_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits 8 +#define GEN6_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits 8 +#define GEN5_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits 8 +#define GEN45_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start 64 +#define GEN10_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start 64 +#define GEN9_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start 64 +#define GEN8_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start 64 +#define GEN75_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start 64 +#define GEN7_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start 64 +#define GEN6_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start 64 +#define GEN5_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start 64 +#define GEN45_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start 64 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_AA_LINE_PARAMETERS_AACoverageEndCapSlope_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 64; + case 5: return 64; + case 4: + if (devinfo->is_g4x) { + return 64; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_AA_LINE_PARAMETERS::AA Coverage Slope */ + + +#define GEN11_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits 8 +#define GEN10_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits 8 +#define GEN9_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits 8 +#define GEN8_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits 8 +#define GEN75_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits 8 +#define GEN7_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits 8 +#define GEN6_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits 8 +#define GEN5_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits 8 +#define GEN45_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start 32 +#define GEN10_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start 32 +#define GEN9_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start 32 +#define GEN8_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start 32 +#define GEN75_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start 32 +#define GEN7_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start 32 +#define GEN6_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start 32 +#define GEN5_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start 32 +#define GEN45_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_AA_LINE_PARAMETERS_AACoverageSlope_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_AA_LINE_PARAMETERS::AA Point Coverage Bias */ + + +#define GEN11_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageBias_bits 8 +#define GEN10_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageBias_bits 8 +#define GEN9_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageBias_bits 8 +#define GEN8_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageBias_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageBias_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageBias_start 56 +#define GEN10_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageBias_start 56 +#define GEN9_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageBias_start 56 +#define GEN8_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageBias_start 56 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageBias_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 56; + case 10: return 56; + case 9: return 56; + case 8: return 56; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_AA_LINE_PARAMETERS::AA Point Coverage EndCap Bias */ + + +#define GEN11_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapBias_bits 8 +#define GEN10_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapBias_bits 8 +#define GEN9_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapBias_bits 8 +#define GEN8_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapBias_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapBias_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapBias_start 88 +#define GEN10_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapBias_start 88 +#define GEN9_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapBias_start 88 +#define GEN8_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapBias_start 88 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapBias_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 88; + case 10: return 88; + case 9: return 88; + case 8: return 88; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_AA_LINE_PARAMETERS::AA Point Coverage EndCap Slope */ + + +#define GEN11_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapSlope_bits 8 +#define GEN10_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapSlope_bits 8 +#define GEN9_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapSlope_bits 8 +#define GEN8_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapSlope_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapSlope_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapSlope_start 72 +#define GEN10_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapSlope_start 72 +#define GEN9_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapSlope_start 72 +#define GEN8_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapSlope_start 72 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageEndCapSlope_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 72; + case 10: return 72; + case 9: return 72; + case 8: return 72; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_AA_LINE_PARAMETERS::AA Point Coverage Slope */ + + +#define GEN11_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageSlope_bits 8 +#define GEN10_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageSlope_bits 8 +#define GEN9_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageSlope_bits 8 +#define GEN8_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageSlope_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageSlope_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageSlope_start 40 +#define GEN10_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageSlope_start 40 +#define GEN9_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageSlope_start 40 +#define GEN8_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageSlope_start 40 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_AA_LINE_PARAMETERS_AAPointCoverageSlope_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 40; + case 10: return 40; + case 9: return 40; + case 8: return 40; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_AA_LINE_PARAMETERS::Command SubType */ + + +#define GEN11_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits 2 +#define GEN10_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits 2 +#define GEN9_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits 2 +#define GEN8_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits 2 +#define GEN75_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits 2 +#define GEN7_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits 2 +#define GEN6_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits 2 +#define GEN5_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits 2 +#define GEN45_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start 27 +#define GEN10_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start 27 +#define GEN9_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start 27 +#define GEN8_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start 27 +#define GEN75_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start 27 +#define GEN7_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start 27 +#define GEN6_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start 27 +#define GEN5_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start 27 +#define GEN45_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_AA_LINE_PARAMETERS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_AA_LINE_PARAMETERS::Command Type */ + + +#define GEN11_3DSTATE_AA_LINE_PARAMETERS_CommandType_bits 3 +#define GEN10_3DSTATE_AA_LINE_PARAMETERS_CommandType_bits 3 +#define GEN9_3DSTATE_AA_LINE_PARAMETERS_CommandType_bits 3 +#define GEN8_3DSTATE_AA_LINE_PARAMETERS_CommandType_bits 3 +#define GEN75_3DSTATE_AA_LINE_PARAMETERS_CommandType_bits 3 +#define GEN7_3DSTATE_AA_LINE_PARAMETERS_CommandType_bits 3 +#define GEN6_3DSTATE_AA_LINE_PARAMETERS_CommandType_bits 3 +#define GEN5_3DSTATE_AA_LINE_PARAMETERS_CommandType_bits 3 +#define GEN45_3DSTATE_AA_LINE_PARAMETERS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_AA_LINE_PARAMETERS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_AA_LINE_PARAMETERS_CommandType_start 29 +#define GEN10_3DSTATE_AA_LINE_PARAMETERS_CommandType_start 29 +#define GEN9_3DSTATE_AA_LINE_PARAMETERS_CommandType_start 29 +#define GEN8_3DSTATE_AA_LINE_PARAMETERS_CommandType_start 29 +#define GEN75_3DSTATE_AA_LINE_PARAMETERS_CommandType_start 29 +#define GEN7_3DSTATE_AA_LINE_PARAMETERS_CommandType_start 29 +#define GEN6_3DSTATE_AA_LINE_PARAMETERS_CommandType_start 29 +#define GEN5_3DSTATE_AA_LINE_PARAMETERS_CommandType_start 29 +#define GEN45_3DSTATE_AA_LINE_PARAMETERS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_AA_LINE_PARAMETERS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 29; + case 4: + if (devinfo->is_g4x) { + return 29; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_AA_LINE_PARAMETERS::DWord Length */ + + +#define GEN11_3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits 8 +#define GEN10_3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits 8 +#define GEN9_3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits 8 +#define GEN8_3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits 8 +#define GEN75_3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits 8 +#define GEN7_3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits 8 +#define GEN6_3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits 8 +#define GEN5_3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits 8 +#define GEN45_3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_AA_LINE_PARAMETERS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_AA_LINE_PARAMETERS_DWordLength_start 0 +#define GEN10_3DSTATE_AA_LINE_PARAMETERS_DWordLength_start 0 +#define GEN9_3DSTATE_AA_LINE_PARAMETERS_DWordLength_start 0 +#define GEN8_3DSTATE_AA_LINE_PARAMETERS_DWordLength_start 0 +#define GEN75_3DSTATE_AA_LINE_PARAMETERS_DWordLength_start 0 +#define GEN7_3DSTATE_AA_LINE_PARAMETERS_DWordLength_start 0 +#define GEN6_3DSTATE_AA_LINE_PARAMETERS_DWordLength_start 0 +#define GEN5_3DSTATE_AA_LINE_PARAMETERS_DWordLength_start 0 +#define GEN45_3DSTATE_AA_LINE_PARAMETERS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_AA_LINE_PARAMETERS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_DS */ + + + + + +/* 3DSTATE_BINDING_TABLE_EDIT_DS::3D Command Opcode */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_DS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_DS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_DS::Binding Table Block Clear */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_bits 16 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_bits 16 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_bits 16 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_bits 16 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_start 48 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_start 48 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_start 48 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_start 48 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_start 48 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableBlockClear_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 48; + case 7: + if (devinfo->is_haswell) { + return 48; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_DS::Binding Table Edit Target */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_bits 2 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_bits 2 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_bits 2 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_bits 2 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_start 32 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_start 32 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_start 32 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_start 32 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_DS_BindingTableEditTarget_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_DS::Command SubType */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_bits 2 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_bits 2 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_bits 2 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_bits 2 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_start 27 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_start 27 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_start 27 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_start 27 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_DS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_DS::Command Type */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_bits 3 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_bits 3 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_bits 3 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_bits 3 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_start 29 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_start 29 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_start 29 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_start 29 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_DS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_DS::DWord Length */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_bits 9 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_bits 9 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_bits 9 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_bits 9 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 9; + case 10: return 9; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_start 0 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_start 0 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_start 0 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_start 0 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_DS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_DS::Entry [n] */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_DS_Entryn_bits 32 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_Entryn_bits 32 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_Entryn_bits 32 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_Entryn_bits 32 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_Entryn_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_DS_Entryn_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_DS_Entryn_start 0 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_DS_Entryn_start 0 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_DS_Entryn_start 0 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_DS_Entryn_start 0 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_DS_Entryn_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_DS_Entryn_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_GS */ + + + + + +/* 3DSTATE_BINDING_TABLE_EDIT_GS::3D Command Opcode */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_GS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_GS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_GS::Binding Table Block Clear */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_bits 16 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_bits 16 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_bits 16 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_bits 16 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_start 48 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_start 48 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_start 48 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_start 48 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_start 48 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableBlockClear_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 48; + case 7: + if (devinfo->is_haswell) { + return 48; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_GS::Binding Table Edit Target */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_bits 2 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_bits 2 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_bits 2 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_bits 2 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_start 32 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_start 32 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_start 32 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_start 32 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_GS_BindingTableEditTarget_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_GS::Command SubType */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_bits 2 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_bits 2 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_bits 2 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_bits 2 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_start 27 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_start 27 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_start 27 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_start 27 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_GS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_GS::Command Type */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_bits 3 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_bits 3 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_bits 3 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_bits 3 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_start 29 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_start 29 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_start 29 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_start 29 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_GS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_GS::DWord Length */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_bits 9 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_bits 9 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_bits 9 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_bits 9 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 9; + case 10: return 9; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_start 0 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_start 0 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_start 0 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_start 0 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_GS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_GS::Entry [n] */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_GS_Entryn_bits 32 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_Entryn_bits 32 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_Entryn_bits 32 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_Entryn_bits 32 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_Entryn_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_GS_Entryn_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_GS_Entryn_start 0 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_GS_Entryn_start 0 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_GS_Entryn_start 0 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_GS_Entryn_start 0 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_GS_Entryn_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_GS_Entryn_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_HS */ + + + + + +/* 3DSTATE_BINDING_TABLE_EDIT_HS::3D Command Opcode */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_HS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_HS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_HS::Binding Table Block Clear */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_bits 16 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_bits 16 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_bits 16 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_bits 16 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_start 48 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_start 48 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_start 48 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_start 48 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_start 48 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableBlockClear_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 48; + case 7: + if (devinfo->is_haswell) { + return 48; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_HS::Binding Table Edit Target */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_bits 2 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_bits 2 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_bits 2 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_bits 2 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_start 32 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_start 32 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_start 32 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_start 32 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_HS_BindingTableEditTarget_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_HS::Command SubType */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_bits 2 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_bits 2 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_bits 2 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_bits 2 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_start 27 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_start 27 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_start 27 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_start 27 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_HS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_HS::Command Type */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_bits 3 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_bits 3 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_bits 3 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_bits 3 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_start 29 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_start 29 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_start 29 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_start 29 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_HS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_HS::DWord Length */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_bits 9 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_bits 9 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_bits 9 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_bits 9 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 9; + case 10: return 9; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_start 0 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_start 0 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_start 0 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_start 0 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_HS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_HS::Entry [n] */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_HS_Entryn_bits 32 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_Entryn_bits 32 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_Entryn_bits 32 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_Entryn_bits 32 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_Entryn_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_HS_Entryn_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_HS_Entryn_start 0 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_HS_Entryn_start 0 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_HS_Entryn_start 0 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_HS_Entryn_start 0 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_HS_Entryn_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_HS_Entryn_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_PS */ + + + + + +/* 3DSTATE_BINDING_TABLE_EDIT_PS::3D Command Opcode */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_PS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_PS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_PS::Binding Table Block Clear */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_bits 16 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_bits 16 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_bits 16 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_bits 16 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_start 48 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_start 48 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_start 48 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_start 48 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_start 48 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableBlockClear_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 48; + case 7: + if (devinfo->is_haswell) { + return 48; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_PS::Binding Table Edit Target */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_bits 2 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_bits 2 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_bits 2 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_bits 2 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_start 32 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_start 32 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_start 32 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_start 32 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_PS_BindingTableEditTarget_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_PS::Command SubType */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_bits 2 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_bits 2 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_bits 2 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_bits 2 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_start 27 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_start 27 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_start 27 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_start 27 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_PS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_PS::Command Type */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_bits 3 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_bits 3 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_bits 3 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_bits 3 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_start 29 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_start 29 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_start 29 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_start 29 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_PS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_PS::DWord Length */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_bits 9 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_bits 9 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_bits 9 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_bits 9 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 9; + case 10: return 9; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_start 0 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_start 0 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_start 0 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_start 0 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_PS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_PS::Entry [n] */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_PS_Entryn_bits 32 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_Entryn_bits 32 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_Entryn_bits 32 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_Entryn_bits 32 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_Entryn_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_PS_Entryn_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_PS_Entryn_start 0 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_PS_Entryn_start 0 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_PS_Entryn_start 0 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_PS_Entryn_start 0 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_PS_Entryn_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_PS_Entryn_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_VS */ + + + + + +/* 3DSTATE_BINDING_TABLE_EDIT_VS::3D Command Opcode */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_VS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_VS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_VS::Binding Table Block Clear */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_bits 16 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_bits 16 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_bits 16 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_bits 16 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_start 48 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_start 48 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_start 48 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_start 48 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_start 48 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableBlockClear_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 48; + case 7: + if (devinfo->is_haswell) { + return 48; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_VS::Binding Table Edit Target */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_bits 2 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_bits 2 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_bits 2 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_bits 2 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_start 32 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_start 32 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_start 32 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_start 32 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_VS_BindingTableEditTarget_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_VS::Command SubType */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_bits 2 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_bits 2 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_bits 2 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_bits 2 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_start 27 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_start 27 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_start 27 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_start 27 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_VS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_VS::Command Type */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_bits 3 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_bits 3 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_bits 3 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_bits 3 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_start 29 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_start 29 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_start 29 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_start 29 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_VS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_VS::DWord Length */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_bits 9 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_bits 9 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_bits 9 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_bits 9 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 9; + case 10: return 9; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_start 0 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_start 0 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_start 0 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_start 0 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_VS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_EDIT_VS::Entry [n] */ + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_VS_Entryn_bits 32 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_Entryn_bits 32 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_Entryn_bits 32 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_Entryn_bits 32 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_Entryn_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_VS_Entryn_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_EDIT_VS_Entryn_start 0 +#define GEN10_3DSTATE_BINDING_TABLE_EDIT_VS_Entryn_start 0 +#define GEN9_3DSTATE_BINDING_TABLE_EDIT_VS_Entryn_start 0 +#define GEN8_3DSTATE_BINDING_TABLE_EDIT_VS_Entryn_start 0 +#define GEN75_3DSTATE_BINDING_TABLE_EDIT_VS_Entryn_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_EDIT_VS_Entryn_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS */ + + +#define GEN6_3DSTATE_BINDING_TABLE_POINTERS_length 4 +#define GEN5_3DSTATE_BINDING_TABLE_POINTERS_length 6 +#define GEN45_3DSTATE_BINDING_TABLE_POINTERS_length 6 +#define GEN4_3DSTATE_BINDING_TABLE_POINTERS_length 6 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 4; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS::3D Command Opcode */ + + +#define GEN6_3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_bits 3 +#define GEN5_3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_bits 3 +#define GEN45_3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_bits 3 +#define GEN4_3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_start 24 +#define GEN5_3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_start 24 +#define GEN45_3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_start 24 +#define GEN4_3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 24; + case 5: return 24; + case 4: + if (devinfo->is_g4x) { + return 24; + } else { + return 24; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS::3D Command Sub Opcode */ + + +#define GEN6_3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_bits 8 +#define GEN5_3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_bits 8 +#define GEN45_3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_bits 8 +#define GEN4_3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_start 16 +#define GEN5_3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_start 16 +#define GEN45_3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_start 16 +#define GEN4_3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS::Command SubType */ + + +#define GEN6_3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_bits 2 +#define GEN5_3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_bits 2 +#define GEN45_3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_bits 2 +#define GEN4_3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 2; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_start 27 +#define GEN5_3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_start 27 +#define GEN45_3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_start 27 +#define GEN4_3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 27; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS::Command Type */ + + +#define GEN6_3DSTATE_BINDING_TABLE_POINTERS_CommandType_bits 3 +#define GEN5_3DSTATE_BINDING_TABLE_POINTERS_CommandType_bits 3 +#define GEN45_3DSTATE_BINDING_TABLE_POINTERS_CommandType_bits 3 +#define GEN4_3DSTATE_BINDING_TABLE_POINTERS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_BINDING_TABLE_POINTERS_CommandType_start 29 +#define GEN5_3DSTATE_BINDING_TABLE_POINTERS_CommandType_start 29 +#define GEN45_3DSTATE_BINDING_TABLE_POINTERS_CommandType_start 29 +#define GEN4_3DSTATE_BINDING_TABLE_POINTERS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 29; + case 5: return 29; + case 4: + if (devinfo->is_g4x) { + return 29; + } else { + return 29; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS::DWord Length */ + + +#define GEN6_3DSTATE_BINDING_TABLE_POINTERS_DWordLength_bits 8 +#define GEN5_3DSTATE_BINDING_TABLE_POINTERS_DWordLength_bits 8 +#define GEN45_3DSTATE_BINDING_TABLE_POINTERS_DWordLength_bits 8 +#define GEN4_3DSTATE_BINDING_TABLE_POINTERS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_BINDING_TABLE_POINTERS_DWordLength_start 0 +#define GEN5_3DSTATE_BINDING_TABLE_POINTERS_DWordLength_start 0 +#define GEN45_3DSTATE_BINDING_TABLE_POINTERS_DWordLength_start 0 +#define GEN4_3DSTATE_BINDING_TABLE_POINTERS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS::GS Binding Table Change */ + + +#define GEN6_3DSTATE_BINDING_TABLE_POINTERS_GSBindingTableChange_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_GSBindingTableChange_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_BINDING_TABLE_POINTERS_GSBindingTableChange_start 9 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_GSBindingTableChange_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 9; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS::PS Binding Table Change */ + + +#define GEN6_3DSTATE_BINDING_TABLE_POINTERS_PSBindingTableChange_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_PSBindingTableChange_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_BINDING_TABLE_POINTERS_PSBindingTableChange_start 12 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_PSBindingTableChange_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 12; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS::Pointer to CLIP Binding Table */ + + +#define GEN5_3DSTATE_BINDING_TABLE_POINTERS_PointertoCLIPBindingTable_bits 27 +#define GEN45_3DSTATE_BINDING_TABLE_POINTERS_PointertoCLIPBindingTable_bits 27 +#define GEN4_3DSTATE_BINDING_TABLE_POINTERS_PointertoCLIPBindingTable_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_PointertoCLIPBindingTable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_3DSTATE_BINDING_TABLE_POINTERS_PointertoCLIPBindingTable_start 101 +#define GEN45_3DSTATE_BINDING_TABLE_POINTERS_PointertoCLIPBindingTable_start 101 +#define GEN4_3DSTATE_BINDING_TABLE_POINTERS_PointertoCLIPBindingTable_start 101 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_PointertoCLIPBindingTable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 101; + case 4: + if (devinfo->is_g4x) { + return 101; + } else { + return 101; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS::Pointer to GS Binding Table */ + + +#define GEN6_3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_bits 27 +#define GEN5_3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_bits 27 +#define GEN45_3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_bits 27 +#define GEN4_3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 27; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_start 69 +#define GEN5_3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_start 69 +#define GEN45_3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_start 69 +#define GEN4_3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_start 69 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_PointertoGSBindingTable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 69; + case 5: return 69; + case 4: + if (devinfo->is_g4x) { + return 69; + } else { + return 69; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS::Pointer to PS Binding Table */ + + +#define GEN6_3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_bits 27 +#define GEN5_3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_bits 27 +#define GEN45_3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_bits 27 +#define GEN4_3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 27; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_start 101 +#define GEN5_3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_start 165 +#define GEN45_3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_start 165 +#define GEN4_3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_start 165 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_PointertoPSBindingTable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 101; + case 5: return 165; + case 4: + if (devinfo->is_g4x) { + return 165; + } else { + return 165; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS::Pointer to SF Binding Table */ + + +#define GEN5_3DSTATE_BINDING_TABLE_POINTERS_PointertoSFBindingTable_bits 27 +#define GEN45_3DSTATE_BINDING_TABLE_POINTERS_PointertoSFBindingTable_bits 27 +#define GEN4_3DSTATE_BINDING_TABLE_POINTERS_PointertoSFBindingTable_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_PointertoSFBindingTable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_3DSTATE_BINDING_TABLE_POINTERS_PointertoSFBindingTable_start 133 +#define GEN45_3DSTATE_BINDING_TABLE_POINTERS_PointertoSFBindingTable_start 133 +#define GEN4_3DSTATE_BINDING_TABLE_POINTERS_PointertoSFBindingTable_start 133 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_PointertoSFBindingTable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 133; + case 4: + if (devinfo->is_g4x) { + return 133; + } else { + return 133; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS::Pointer to VS Binding Table */ + + +#define GEN6_3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_bits 27 +#define GEN5_3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_bits 27 +#define GEN45_3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_bits 27 +#define GEN4_3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 27; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_start 37 +#define GEN5_3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_start 37 +#define GEN45_3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_start 37 +#define GEN4_3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_start 37 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_PointertoVSBindingTable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 37; + case 5: return 37; + case 4: + if (devinfo->is_g4x) { + return 37; + } else { + return 37; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS::VS Binding Table Change */ + + +#define GEN6_3DSTATE_BINDING_TABLE_POINTERS_VSBindingTableChange_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_VSBindingTableChange_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_BINDING_TABLE_POINTERS_VSBindingTableChange_start 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_VSBindingTableChange_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS_DS */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_DS_length 2 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_length 2 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_length 2 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_length 2 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_length 2 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_length 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_DS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS_DS::3D Command Opcode */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS_DS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_DS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS_DS::Command SubType */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_bits 2 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_bits 2 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_bits 2 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_bits 2 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_bits 2 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_start 27 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_start 27 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_start 27 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_start 27 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_start 27 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS_DS::Command Type */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_bits 3 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_bits 3 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_bits 3 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_bits 3 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_bits 3 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_start 29 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_start 29 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_start 29 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_start 29 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_start 29 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_DS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS_DS::DWord Length */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_bits 8 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_bits 8 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_bits 8 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_bits 8 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_bits 8 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_start 0 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_start 0 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_start 0 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_start 0 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_start 0 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_DS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS_DS::Pointer to DS Binding Table */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_bits 11 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_bits 11 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_bits 11 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_bits 11 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_bits 11 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_bits 11 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 11; + } else { + return 11; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_start 37 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_start 37 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_start 37 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_start 37 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_start 37 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_start 37 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_DS_PointertoDSBindingTable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 37; + case 10: return 37; + case 9: return 37; + case 8: return 37; + case 7: + if (devinfo->is_haswell) { + return 37; + } else { + return 37; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS_GS */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_GS_length 2 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_length 2 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_length 2 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_length 2 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_length 2 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_length 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_GS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS_GS::3D Command Opcode */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS_GS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_GS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS_GS::Command SubType */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_bits 2 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_bits 2 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_bits 2 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_bits 2 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_bits 2 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_start 27 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_start 27 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_start 27 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_start 27 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_start 27 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS_GS::Command Type */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_bits 3 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_bits 3 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_bits 3 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_bits 3 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_bits 3 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_start 29 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_start 29 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_start 29 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_start 29 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_start 29 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_GS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS_GS::DWord Length */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_bits 8 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_bits 8 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_bits 8 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_bits 8 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_bits 8 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_start 0 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_start 0 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_start 0 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_start 0 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_start 0 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_GS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS_GS::Pointer to GS Binding Table */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_bits 11 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_bits 11 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_bits 11 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_bits 11 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_bits 11 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_bits 11 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 11; + } else { + return 11; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_start 37 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_start 37 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_start 37 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_start 37 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_start 37 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_start 37 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_GS_PointertoGSBindingTable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 37; + case 10: return 37; + case 9: return 37; + case 8: return 37; + case 7: + if (devinfo->is_haswell) { + return 37; + } else { + return 37; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS_HS */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_HS_length 2 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_length 2 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_length 2 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_length 2 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_length 2 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_length 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_HS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS_HS::3D Command Opcode */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS_HS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_HS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS_HS::Command SubType */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_bits 2 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_bits 2 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_bits 2 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_bits 2 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_bits 2 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_start 27 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_start 27 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_start 27 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_start 27 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_start 27 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS_HS::Command Type */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_bits 3 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_bits 3 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_bits 3 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_bits 3 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_bits 3 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_start 29 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_start 29 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_start 29 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_start 29 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_start 29 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_HS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS_HS::DWord Length */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_bits 8 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_bits 8 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_bits 8 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_bits 8 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_bits 8 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_start 0 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_start 0 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_start 0 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_start 0 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_start 0 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_HS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS_HS::Pointer to HS Binding Table */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_bits 11 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_bits 11 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_bits 11 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_bits 11 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_bits 11 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_bits 11 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 11; + } else { + return 11; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_start 37 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_start 37 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_start 37 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_start 37 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_start 37 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_start 37 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_HS_PointertoHSBindingTable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 37; + case 10: return 37; + case 9: return 37; + case 8: return 37; + case 7: + if (devinfo->is_haswell) { + return 37; + } else { + return 37; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS_PS */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_PS_length 2 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_length 2 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_length 2 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_length 2 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_length 2 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_length 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_PS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS_PS::3D Command Opcode */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS_PS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_PS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS_PS::Command SubType */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_bits 2 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_bits 2 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_bits 2 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_bits 2 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_bits 2 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_start 27 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_start 27 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_start 27 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_start 27 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_start 27 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS_PS::Command Type */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_bits 3 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_bits 3 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_bits 3 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_bits 3 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_bits 3 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_start 29 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_start 29 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_start 29 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_start 29 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_start 29 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_PS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS_PS::DWord Length */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_bits 8 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_bits 8 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_bits 8 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_bits 8 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_bits 8 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_start 0 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_start 0 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_start 0 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_start 0 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_start 0 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_PS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS_PS::Pointer to PS Binding Table */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_bits 11 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_bits 11 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_bits 11 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_bits 11 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_bits 11 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_bits 11 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 11; + } else { + return 11; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_start 37 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_start 37 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_start 37 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_start 37 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_start 37 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_start 37 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_PS_PointertoPSBindingTable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 37; + case 10: return 37; + case 9: return 37; + case 8: return 37; + case 7: + if (devinfo->is_haswell) { + return 37; + } else { + return 37; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS_VS */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_VS_length 2 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_length 2 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_length 2 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_length 2 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_length 2 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_length 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_VS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS_VS::3D Command Opcode */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS_VS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_VS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS_VS::Command SubType */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_bits 2 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_bits 2 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_bits 2 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_bits 2 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_bits 2 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_start 27 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_start 27 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_start 27 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_start 27 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_start 27 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS_VS::Command Type */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_bits 3 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_bits 3 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_bits 3 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_bits 3 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_bits 3 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_start 29 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_start 29 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_start 29 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_start 29 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_start 29 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_VS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS_VS::DWord Length */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_bits 8 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_bits 8 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_bits 8 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_bits 8 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_bits 8 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_start 0 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_start 0 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_start 0 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_start 0 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_start 0 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_VS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POINTERS_VS::Pointer to VS Binding Table */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_bits 11 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_bits 11 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_bits 11 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_bits 11 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_bits 11 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_bits 11 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 11; + } else { + return 11; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_start 37 +#define GEN10_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_start 37 +#define GEN9_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_start 37 +#define GEN8_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_start 37 +#define GEN75_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_start 37 +#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_start 37 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POINTERS_VS_PointertoVSBindingTable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 37; + case 10: return 37; + case 9: return 37; + case 8: return 37; + case 7: + if (devinfo->is_haswell) { + return 37; + } else { + return 37; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POOL_ALLOC */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POOL_ALLOC_length 4 +#define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_length 4 +#define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_length 4 +#define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_length 4 +#define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_length 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POOL_ALLOC_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POOL_ALLOC::3D Command Opcode */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POOL_ALLOC::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POOL_ALLOC_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POOL_ALLOC::Binding Table Pool Base Address */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_bits 52 +#define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_bits 52 +#define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_bits 52 +#define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_bits 52 +#define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_bits 20 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 52; + case 10: return 52; + case 9: return 52; + case 8: return 52; + case 7: + if (devinfo->is_haswell) { + return 20; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_start 44 +#define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_start 44 +#define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_start 44 +#define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_start 44 +#define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_start 44 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBaseAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 44; + case 10: return 44; + case 9: return 44; + case 8: return 44; + case 7: + if (devinfo->is_haswell) { + return 44; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POOL_ALLOC::Binding Table Pool Buffer Size */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBufferSize_bits 20 +#define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBufferSize_bits 20 +#define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBufferSize_bits 20 +#define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBufferSize_bits 20 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBufferSize_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 20; + case 10: return 20; + case 9: return 20; + case 8: return 20; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBufferSize_start 108 +#define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBufferSize_start 108 +#define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBufferSize_start 108 +#define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBufferSize_start 108 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolBufferSize_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 108; + case 10: return 108; + case 9: return 108; + case 8: return 108; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POOL_ALLOC::Binding Table Pool Enable */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_bits 1 +#define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_bits 1 +#define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_bits 1 +#define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_bits 1 +#define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_start 43 +#define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_start 43 +#define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_start 43 +#define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_start 43 +#define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_start 43 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 43; + case 10: return 43; + case 9: return 43; + case 8: return 43; + case 7: + if (devinfo->is_haswell) { + return 43; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POOL_ALLOC::Binding Table Pool Upper Bound */ + + +#define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolUpperBound_bits 20 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolUpperBound_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 20; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolUpperBound_start 76 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POOL_ALLOC_BindingTablePoolUpperBound_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 76; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POOL_ALLOC::Command SubType */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_bits 2 +#define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_bits 2 +#define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_bits 2 +#define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_bits 2 +#define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_start 27 +#define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_start 27 +#define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_start 27 +#define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_start 27 +#define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POOL_ALLOC::Command Type */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_bits 3 +#define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_bits 3 +#define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_bits 3 +#define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_bits 3 +#define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_start 29 +#define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_start 29 +#define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_start 29 +#define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_start 29 +#define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POOL_ALLOC_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POOL_ALLOC::DWord Length */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_bits 8 +#define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_bits 8 +#define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_bits 8 +#define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_bits 8 +#define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_start 0 +#define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_start 0 +#define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_start 0 +#define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_start 0 +#define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POOL_ALLOC_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BINDING_TABLE_POOL_ALLOC::MOCS */ + + +#define GEN11_3DSTATE_BINDING_TABLE_POOL_ALLOC_MOCS_bits 7 +#define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_MOCS_bits 7 +#define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_MOCS_bits 7 +#define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_MOCS_bits 7 +#define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_MOCS_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POOL_ALLOC_MOCS_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BINDING_TABLE_POOL_ALLOC_MOCS_start 32 +#define GEN10_3DSTATE_BINDING_TABLE_POOL_ALLOC_MOCS_start 32 +#define GEN9_3DSTATE_BINDING_TABLE_POOL_ALLOC_MOCS_start 32 +#define GEN8_3DSTATE_BINDING_TABLE_POOL_ALLOC_MOCS_start 32 +#define GEN75_3DSTATE_BINDING_TABLE_POOL_ALLOC_MOCS_start 39 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BINDING_TABLE_POOL_ALLOC_MOCS_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 39; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BLEND_STATE_POINTERS */ + + +#define GEN11_3DSTATE_BLEND_STATE_POINTERS_length 2 +#define GEN10_3DSTATE_BLEND_STATE_POINTERS_length 2 +#define GEN9_3DSTATE_BLEND_STATE_POINTERS_length 2 +#define GEN8_3DSTATE_BLEND_STATE_POINTERS_length 2 +#define GEN75_3DSTATE_BLEND_STATE_POINTERS_length 2 +#define GEN7_3DSTATE_BLEND_STATE_POINTERS_length 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BLEND_STATE_POINTERS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BLEND_STATE_POINTERS::3D Command Opcode */ + + +#define GEN11_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BLEND_STATE_POINTERS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BLEND_STATE_POINTERS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BLEND_STATE_POINTERS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BLEND_STATE_POINTERS::Blend State Pointer */ + + +#define GEN11_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_bits 26 +#define GEN10_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_bits 26 +#define GEN9_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_bits 26 +#define GEN8_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_bits 26 +#define GEN75_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_bits 26 +#define GEN7_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_bits 26 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 26; + case 10: return 26; + case 9: return 26; + case 8: return 26; + case 7: + if (devinfo->is_haswell) { + return 26; + } else { + return 26; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_start 38 +#define GEN10_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_start 38 +#define GEN9_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_start 38 +#define GEN8_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_start 38 +#define GEN75_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_start 38 +#define GEN7_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_start 38 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 38; + case 10: return 38; + case 9: return 38; + case 8: return 38; + case 7: + if (devinfo->is_haswell) { + return 38; + } else { + return 38; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BLEND_STATE_POINTERS::Blend State Pointer Valid */ + + +#define GEN11_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointerValid_bits 1 +#define GEN10_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointerValid_bits 1 +#define GEN9_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointerValid_bits 1 +#define GEN8_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointerValid_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointerValid_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointerValid_start 32 +#define GEN10_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointerValid_start 32 +#define GEN9_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointerValid_start 32 +#define GEN8_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointerValid_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BLEND_STATE_POINTERS_BlendStatePointerValid_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BLEND_STATE_POINTERS::Command SubType */ + + +#define GEN11_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_bits 2 +#define GEN10_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_bits 2 +#define GEN9_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_bits 2 +#define GEN8_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_bits 2 +#define GEN75_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_bits 2 +#define GEN7_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_start 27 +#define GEN10_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_start 27 +#define GEN9_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_start 27 +#define GEN8_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_start 27 +#define GEN75_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_start 27 +#define GEN7_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BLEND_STATE_POINTERS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BLEND_STATE_POINTERS::Command Type */ + + +#define GEN11_3DSTATE_BLEND_STATE_POINTERS_CommandType_bits 3 +#define GEN10_3DSTATE_BLEND_STATE_POINTERS_CommandType_bits 3 +#define GEN9_3DSTATE_BLEND_STATE_POINTERS_CommandType_bits 3 +#define GEN8_3DSTATE_BLEND_STATE_POINTERS_CommandType_bits 3 +#define GEN75_3DSTATE_BLEND_STATE_POINTERS_CommandType_bits 3 +#define GEN7_3DSTATE_BLEND_STATE_POINTERS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BLEND_STATE_POINTERS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BLEND_STATE_POINTERS_CommandType_start 29 +#define GEN10_3DSTATE_BLEND_STATE_POINTERS_CommandType_start 29 +#define GEN9_3DSTATE_BLEND_STATE_POINTERS_CommandType_start 29 +#define GEN8_3DSTATE_BLEND_STATE_POINTERS_CommandType_start 29 +#define GEN75_3DSTATE_BLEND_STATE_POINTERS_CommandType_start 29 +#define GEN7_3DSTATE_BLEND_STATE_POINTERS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BLEND_STATE_POINTERS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_BLEND_STATE_POINTERS::DWord Length */ + + +#define GEN11_3DSTATE_BLEND_STATE_POINTERS_DWordLength_bits 8 +#define GEN10_3DSTATE_BLEND_STATE_POINTERS_DWordLength_bits 8 +#define GEN9_3DSTATE_BLEND_STATE_POINTERS_DWordLength_bits 8 +#define GEN8_3DSTATE_BLEND_STATE_POINTERS_DWordLength_bits 8 +#define GEN75_3DSTATE_BLEND_STATE_POINTERS_DWordLength_bits 8 +#define GEN7_3DSTATE_BLEND_STATE_POINTERS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BLEND_STATE_POINTERS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_BLEND_STATE_POINTERS_DWordLength_start 0 +#define GEN10_3DSTATE_BLEND_STATE_POINTERS_DWordLength_start 0 +#define GEN9_3DSTATE_BLEND_STATE_POINTERS_DWordLength_start 0 +#define GEN8_3DSTATE_BLEND_STATE_POINTERS_DWordLength_start 0 +#define GEN75_3DSTATE_BLEND_STATE_POINTERS_DWordLength_start 0 +#define GEN7_3DSTATE_BLEND_STATE_POINTERS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_BLEND_STATE_POINTERS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CC_STATE_POINTERS */ + + +#define GEN11_3DSTATE_CC_STATE_POINTERS_length 2 +#define GEN10_3DSTATE_CC_STATE_POINTERS_length 2 +#define GEN9_3DSTATE_CC_STATE_POINTERS_length 2 +#define GEN8_3DSTATE_CC_STATE_POINTERS_length 2 +#define GEN75_3DSTATE_CC_STATE_POINTERS_length 2 +#define GEN7_3DSTATE_CC_STATE_POINTERS_length 2 +#define GEN6_3DSTATE_CC_STATE_POINTERS_length 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CC_STATE_POINTERS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CC_STATE_POINTERS::3D Command Opcode */ + + +#define GEN11_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_bits 3 +#define GEN6_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_start 24 +#define GEN6_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CC_STATE_POINTERS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CC_STATE_POINTERS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_bits 8 +#define GEN6_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_start 16 +#define GEN6_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CC_STATE_POINTERS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CC_STATE_POINTERS::BLEND_STATE Change */ + + +#define GEN6_3DSTATE_CC_STATE_POINTERS_BLEND_STATEChange_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CC_STATE_POINTERS_BLEND_STATEChange_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_CC_STATE_POINTERS_BLEND_STATEChange_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CC_STATE_POINTERS_BLEND_STATEChange_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CC_STATE_POINTERS::Color Calc State Pointer */ + + +#define GEN11_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_bits 26 +#define GEN10_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_bits 26 +#define GEN9_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_bits 26 +#define GEN8_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_bits 26 +#define GEN75_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_bits 26 +#define GEN7_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_bits 26 +#define GEN6_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_bits 26 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 26; + case 10: return 26; + case 9: return 26; + case 8: return 26; + case 7: + if (devinfo->is_haswell) { + return 26; + } else { + return 26; + } + case 6: return 26; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_start 38 +#define GEN10_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_start 38 +#define GEN9_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_start 38 +#define GEN8_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_start 38 +#define GEN75_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_start 38 +#define GEN7_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_start 38 +#define GEN6_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_start 102 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 38; + case 10: return 38; + case 9: return 38; + case 8: return 38; + case 7: + if (devinfo->is_haswell) { + return 38; + } else { + return 38; + } + case 6: return 102; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CC_STATE_POINTERS::Color Calc State Pointer Valid */ + + +#define GEN11_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_bits 1 +#define GEN10_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_bits 1 +#define GEN9_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_bits 1 +#define GEN8_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_bits 1 +#define GEN6_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_start 32 +#define GEN10_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_start 32 +#define GEN9_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_start 32 +#define GEN8_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_start 32 +#define GEN6_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_start 96 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CC_STATE_POINTERS_ColorCalcStatePointerValid_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 96; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CC_STATE_POINTERS::Command SubType */ + + +#define GEN11_3DSTATE_CC_STATE_POINTERS_CommandSubType_bits 2 +#define GEN10_3DSTATE_CC_STATE_POINTERS_CommandSubType_bits 2 +#define GEN9_3DSTATE_CC_STATE_POINTERS_CommandSubType_bits 2 +#define GEN8_3DSTATE_CC_STATE_POINTERS_CommandSubType_bits 2 +#define GEN75_3DSTATE_CC_STATE_POINTERS_CommandSubType_bits 2 +#define GEN7_3DSTATE_CC_STATE_POINTERS_CommandSubType_bits 2 +#define GEN6_3DSTATE_CC_STATE_POINTERS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CC_STATE_POINTERS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CC_STATE_POINTERS_CommandSubType_start 27 +#define GEN10_3DSTATE_CC_STATE_POINTERS_CommandSubType_start 27 +#define GEN9_3DSTATE_CC_STATE_POINTERS_CommandSubType_start 27 +#define GEN8_3DSTATE_CC_STATE_POINTERS_CommandSubType_start 27 +#define GEN75_3DSTATE_CC_STATE_POINTERS_CommandSubType_start 27 +#define GEN7_3DSTATE_CC_STATE_POINTERS_CommandSubType_start 27 +#define GEN6_3DSTATE_CC_STATE_POINTERS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CC_STATE_POINTERS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CC_STATE_POINTERS::Command Type */ + + +#define GEN11_3DSTATE_CC_STATE_POINTERS_CommandType_bits 3 +#define GEN10_3DSTATE_CC_STATE_POINTERS_CommandType_bits 3 +#define GEN9_3DSTATE_CC_STATE_POINTERS_CommandType_bits 3 +#define GEN8_3DSTATE_CC_STATE_POINTERS_CommandType_bits 3 +#define GEN75_3DSTATE_CC_STATE_POINTERS_CommandType_bits 3 +#define GEN7_3DSTATE_CC_STATE_POINTERS_CommandType_bits 3 +#define GEN6_3DSTATE_CC_STATE_POINTERS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CC_STATE_POINTERS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CC_STATE_POINTERS_CommandType_start 29 +#define GEN10_3DSTATE_CC_STATE_POINTERS_CommandType_start 29 +#define GEN9_3DSTATE_CC_STATE_POINTERS_CommandType_start 29 +#define GEN8_3DSTATE_CC_STATE_POINTERS_CommandType_start 29 +#define GEN75_3DSTATE_CC_STATE_POINTERS_CommandType_start 29 +#define GEN7_3DSTATE_CC_STATE_POINTERS_CommandType_start 29 +#define GEN6_3DSTATE_CC_STATE_POINTERS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CC_STATE_POINTERS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CC_STATE_POINTERS::DEPTH_STENCIL_STATE Change */ + + +#define GEN6_3DSTATE_CC_STATE_POINTERS_DEPTH_STENCIL_STATEChange_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CC_STATE_POINTERS_DEPTH_STENCIL_STATEChange_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_CC_STATE_POINTERS_DEPTH_STENCIL_STATEChange_start 64 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CC_STATE_POINTERS_DEPTH_STENCIL_STATEChange_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 64; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CC_STATE_POINTERS::DWord Length */ + + +#define GEN11_3DSTATE_CC_STATE_POINTERS_DWordLength_bits 8 +#define GEN10_3DSTATE_CC_STATE_POINTERS_DWordLength_bits 8 +#define GEN9_3DSTATE_CC_STATE_POINTERS_DWordLength_bits 8 +#define GEN8_3DSTATE_CC_STATE_POINTERS_DWordLength_bits 8 +#define GEN75_3DSTATE_CC_STATE_POINTERS_DWordLength_bits 8 +#define GEN7_3DSTATE_CC_STATE_POINTERS_DWordLength_bits 8 +#define GEN6_3DSTATE_CC_STATE_POINTERS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CC_STATE_POINTERS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CC_STATE_POINTERS_DWordLength_start 0 +#define GEN10_3DSTATE_CC_STATE_POINTERS_DWordLength_start 0 +#define GEN9_3DSTATE_CC_STATE_POINTERS_DWordLength_start 0 +#define GEN8_3DSTATE_CC_STATE_POINTERS_DWordLength_start 0 +#define GEN75_3DSTATE_CC_STATE_POINTERS_DWordLength_start 0 +#define GEN7_3DSTATE_CC_STATE_POINTERS_DWordLength_start 0 +#define GEN6_3DSTATE_CC_STATE_POINTERS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CC_STATE_POINTERS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CC_STATE_POINTERS::Pointer to BLEND_STATE */ + + +#define GEN6_3DSTATE_CC_STATE_POINTERS_PointertoBLEND_STATE_bits 26 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CC_STATE_POINTERS_PointertoBLEND_STATE_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 26; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_CC_STATE_POINTERS_PointertoBLEND_STATE_start 38 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CC_STATE_POINTERS_PointertoBLEND_STATE_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 38; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CC_STATE_POINTERS::Pointer to DEPTH_STENCIL_STATE */ + + +#define GEN6_3DSTATE_CC_STATE_POINTERS_PointertoDEPTH_STENCIL_STATE_bits 26 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CC_STATE_POINTERS_PointertoDEPTH_STENCIL_STATE_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 26; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_CC_STATE_POINTERS_PointertoDEPTH_STENCIL_STATE_start 70 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CC_STATE_POINTERS_PointertoDEPTH_STENCIL_STATE_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 70; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CHROMA_KEY */ + + +#define GEN11_3DSTATE_CHROMA_KEY_length 4 +#define GEN10_3DSTATE_CHROMA_KEY_length 4 +#define GEN9_3DSTATE_CHROMA_KEY_length 4 +#define GEN8_3DSTATE_CHROMA_KEY_length 4 +#define GEN75_3DSTATE_CHROMA_KEY_length 4 +#define GEN7_3DSTATE_CHROMA_KEY_length 4 +#define GEN6_3DSTATE_CHROMA_KEY_length 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CHROMA_KEY_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CHROMA_KEY::3D Command Opcode */ + + +#define GEN11_3DSTATE_CHROMA_KEY_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_CHROMA_KEY_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_CHROMA_KEY_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_CHROMA_KEY_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_CHROMA_KEY_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_CHROMA_KEY_3DCommandOpcode_bits 3 +#define GEN6_3DSTATE_CHROMA_KEY_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CHROMA_KEY_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CHROMA_KEY_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_CHROMA_KEY_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_CHROMA_KEY_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_CHROMA_KEY_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_CHROMA_KEY_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_CHROMA_KEY_3DCommandOpcode_start 24 +#define GEN6_3DSTATE_CHROMA_KEY_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CHROMA_KEY_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CHROMA_KEY::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_bits 8 +#define GEN6_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_start 16 +#define GEN6_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CHROMA_KEY_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CHROMA_KEY::ChromaKey High Value */ + + +#define GEN11_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_bits 32 +#define GEN10_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_bits 32 +#define GEN9_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_bits 32 +#define GEN8_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_bits 32 +#define GEN75_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_bits 32 +#define GEN7_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_bits 32 +#define GEN6_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_start 96 +#define GEN10_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_start 96 +#define GEN9_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_start 96 +#define GEN8_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_start 96 +#define GEN75_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_start 96 +#define GEN7_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_start 96 +#define GEN6_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_start 96 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CHROMA_KEY_ChromaKeyHighValue_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 96; + case 10: return 96; + case 9: return 96; + case 8: return 96; + case 7: + if (devinfo->is_haswell) { + return 96; + } else { + return 96; + } + case 6: return 96; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CHROMA_KEY::ChromaKey Low Value */ + + +#define GEN11_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_bits 32 +#define GEN10_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_bits 32 +#define GEN9_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_bits 32 +#define GEN8_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_bits 32 +#define GEN75_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_bits 32 +#define GEN7_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_bits 32 +#define GEN6_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_start 64 +#define GEN10_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_start 64 +#define GEN9_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_start 64 +#define GEN8_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_start 64 +#define GEN75_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_start 64 +#define GEN7_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_start 64 +#define GEN6_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_start 64 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CHROMA_KEY_ChromaKeyLowValue_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 64; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CHROMA_KEY::ChromaKey Table Index */ + + +#define GEN11_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_bits 2 +#define GEN10_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_bits 2 +#define GEN9_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_bits 2 +#define GEN8_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_bits 2 +#define GEN75_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_bits 2 +#define GEN7_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_bits 2 +#define GEN6_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_start 62 +#define GEN10_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_start 62 +#define GEN9_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_start 62 +#define GEN8_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_start 62 +#define GEN75_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_start 62 +#define GEN7_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_start 62 +#define GEN6_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_start 62 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CHROMA_KEY_ChromaKeyTableIndex_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 62; + case 10: return 62; + case 9: return 62; + case 8: return 62; + case 7: + if (devinfo->is_haswell) { + return 62; + } else { + return 62; + } + case 6: return 62; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CHROMA_KEY::Command SubType */ + + +#define GEN11_3DSTATE_CHROMA_KEY_CommandSubType_bits 2 +#define GEN10_3DSTATE_CHROMA_KEY_CommandSubType_bits 2 +#define GEN9_3DSTATE_CHROMA_KEY_CommandSubType_bits 2 +#define GEN8_3DSTATE_CHROMA_KEY_CommandSubType_bits 2 +#define GEN75_3DSTATE_CHROMA_KEY_CommandSubType_bits 2 +#define GEN7_3DSTATE_CHROMA_KEY_CommandSubType_bits 2 +#define GEN6_3DSTATE_CHROMA_KEY_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CHROMA_KEY_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CHROMA_KEY_CommandSubType_start 27 +#define GEN10_3DSTATE_CHROMA_KEY_CommandSubType_start 27 +#define GEN9_3DSTATE_CHROMA_KEY_CommandSubType_start 27 +#define GEN8_3DSTATE_CHROMA_KEY_CommandSubType_start 27 +#define GEN75_3DSTATE_CHROMA_KEY_CommandSubType_start 27 +#define GEN7_3DSTATE_CHROMA_KEY_CommandSubType_start 27 +#define GEN6_3DSTATE_CHROMA_KEY_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CHROMA_KEY_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CHROMA_KEY::Command Type */ + + +#define GEN11_3DSTATE_CHROMA_KEY_CommandType_bits 3 +#define GEN10_3DSTATE_CHROMA_KEY_CommandType_bits 3 +#define GEN9_3DSTATE_CHROMA_KEY_CommandType_bits 3 +#define GEN8_3DSTATE_CHROMA_KEY_CommandType_bits 3 +#define GEN75_3DSTATE_CHROMA_KEY_CommandType_bits 3 +#define GEN7_3DSTATE_CHROMA_KEY_CommandType_bits 3 +#define GEN6_3DSTATE_CHROMA_KEY_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CHROMA_KEY_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CHROMA_KEY_CommandType_start 29 +#define GEN10_3DSTATE_CHROMA_KEY_CommandType_start 29 +#define GEN9_3DSTATE_CHROMA_KEY_CommandType_start 29 +#define GEN8_3DSTATE_CHROMA_KEY_CommandType_start 29 +#define GEN75_3DSTATE_CHROMA_KEY_CommandType_start 29 +#define GEN7_3DSTATE_CHROMA_KEY_CommandType_start 29 +#define GEN6_3DSTATE_CHROMA_KEY_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CHROMA_KEY_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CHROMA_KEY::DWord Length */ + + +#define GEN11_3DSTATE_CHROMA_KEY_DWordLength_bits 8 +#define GEN10_3DSTATE_CHROMA_KEY_DWordLength_bits 8 +#define GEN9_3DSTATE_CHROMA_KEY_DWordLength_bits 8 +#define GEN8_3DSTATE_CHROMA_KEY_DWordLength_bits 8 +#define GEN75_3DSTATE_CHROMA_KEY_DWordLength_bits 8 +#define GEN7_3DSTATE_CHROMA_KEY_DWordLength_bits 8 +#define GEN6_3DSTATE_CHROMA_KEY_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CHROMA_KEY_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CHROMA_KEY_DWordLength_start 0 +#define GEN10_3DSTATE_CHROMA_KEY_DWordLength_start 0 +#define GEN9_3DSTATE_CHROMA_KEY_DWordLength_start 0 +#define GEN8_3DSTATE_CHROMA_KEY_DWordLength_start 0 +#define GEN75_3DSTATE_CHROMA_KEY_DWordLength_start 0 +#define GEN7_3DSTATE_CHROMA_KEY_DWordLength_start 0 +#define GEN6_3DSTATE_CHROMA_KEY_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CHROMA_KEY_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLEAR_PARAMS */ + + +#define GEN11_3DSTATE_CLEAR_PARAMS_length 3 +#define GEN10_3DSTATE_CLEAR_PARAMS_length 3 +#define GEN9_3DSTATE_CLEAR_PARAMS_length 3 +#define GEN8_3DSTATE_CLEAR_PARAMS_length 3 +#define GEN75_3DSTATE_CLEAR_PARAMS_length 3 +#define GEN7_3DSTATE_CLEAR_PARAMS_length 3 +#define GEN6_3DSTATE_CLEAR_PARAMS_length 2 +#define GEN5_3DSTATE_CLEAR_PARAMS_length 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLEAR_PARAMS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 2; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLEAR_PARAMS::3D Command Opcode */ + + +#define GEN11_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_bits 3 +#define GEN6_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_bits 3 +#define GEN5_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_start 24 +#define GEN6_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_start 24 +#define GEN5_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLEAR_PARAMS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 24; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLEAR_PARAMS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_bits 8 +#define GEN6_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_bits 8 +#define GEN5_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_start 16 +#define GEN6_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_start 16 +#define GEN5_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLEAR_PARAMS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLEAR_PARAMS::Command SubType */ + + +#define GEN11_3DSTATE_CLEAR_PARAMS_CommandSubType_bits 2 +#define GEN10_3DSTATE_CLEAR_PARAMS_CommandSubType_bits 2 +#define GEN9_3DSTATE_CLEAR_PARAMS_CommandSubType_bits 2 +#define GEN8_3DSTATE_CLEAR_PARAMS_CommandSubType_bits 2 +#define GEN75_3DSTATE_CLEAR_PARAMS_CommandSubType_bits 2 +#define GEN7_3DSTATE_CLEAR_PARAMS_CommandSubType_bits 2 +#define GEN6_3DSTATE_CLEAR_PARAMS_CommandSubType_bits 2 +#define GEN5_3DSTATE_CLEAR_PARAMS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLEAR_PARAMS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CLEAR_PARAMS_CommandSubType_start 27 +#define GEN10_3DSTATE_CLEAR_PARAMS_CommandSubType_start 27 +#define GEN9_3DSTATE_CLEAR_PARAMS_CommandSubType_start 27 +#define GEN8_3DSTATE_CLEAR_PARAMS_CommandSubType_start 27 +#define GEN75_3DSTATE_CLEAR_PARAMS_CommandSubType_start 27 +#define GEN7_3DSTATE_CLEAR_PARAMS_CommandSubType_start 27 +#define GEN6_3DSTATE_CLEAR_PARAMS_CommandSubType_start 27 +#define GEN5_3DSTATE_CLEAR_PARAMS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLEAR_PARAMS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLEAR_PARAMS::Command Type */ + + +#define GEN11_3DSTATE_CLEAR_PARAMS_CommandType_bits 3 +#define GEN10_3DSTATE_CLEAR_PARAMS_CommandType_bits 3 +#define GEN9_3DSTATE_CLEAR_PARAMS_CommandType_bits 3 +#define GEN8_3DSTATE_CLEAR_PARAMS_CommandType_bits 3 +#define GEN75_3DSTATE_CLEAR_PARAMS_CommandType_bits 3 +#define GEN7_3DSTATE_CLEAR_PARAMS_CommandType_bits 3 +#define GEN6_3DSTATE_CLEAR_PARAMS_CommandType_bits 3 +#define GEN5_3DSTATE_CLEAR_PARAMS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLEAR_PARAMS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CLEAR_PARAMS_CommandType_start 29 +#define GEN10_3DSTATE_CLEAR_PARAMS_CommandType_start 29 +#define GEN9_3DSTATE_CLEAR_PARAMS_CommandType_start 29 +#define GEN8_3DSTATE_CLEAR_PARAMS_CommandType_start 29 +#define GEN75_3DSTATE_CLEAR_PARAMS_CommandType_start 29 +#define GEN7_3DSTATE_CLEAR_PARAMS_CommandType_start 29 +#define GEN6_3DSTATE_CLEAR_PARAMS_CommandType_start 29 +#define GEN5_3DSTATE_CLEAR_PARAMS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLEAR_PARAMS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 29; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLEAR_PARAMS::DWord Length */ + + +#define GEN11_3DSTATE_CLEAR_PARAMS_DWordLength_bits 8 +#define GEN10_3DSTATE_CLEAR_PARAMS_DWordLength_bits 8 +#define GEN9_3DSTATE_CLEAR_PARAMS_DWordLength_bits 8 +#define GEN8_3DSTATE_CLEAR_PARAMS_DWordLength_bits 8 +#define GEN75_3DSTATE_CLEAR_PARAMS_DWordLength_bits 8 +#define GEN7_3DSTATE_CLEAR_PARAMS_DWordLength_bits 8 +#define GEN6_3DSTATE_CLEAR_PARAMS_DWordLength_bits 8 +#define GEN5_3DSTATE_CLEAR_PARAMS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLEAR_PARAMS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CLEAR_PARAMS_DWordLength_start 0 +#define GEN10_3DSTATE_CLEAR_PARAMS_DWordLength_start 0 +#define GEN9_3DSTATE_CLEAR_PARAMS_DWordLength_start 0 +#define GEN8_3DSTATE_CLEAR_PARAMS_DWordLength_start 0 +#define GEN75_3DSTATE_CLEAR_PARAMS_DWordLength_start 0 +#define GEN7_3DSTATE_CLEAR_PARAMS_DWordLength_start 0 +#define GEN6_3DSTATE_CLEAR_PARAMS_DWordLength_start 0 +#define GEN5_3DSTATE_CLEAR_PARAMS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLEAR_PARAMS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLEAR_PARAMS::Depth Clear Value */ + + +#define GEN11_3DSTATE_CLEAR_PARAMS_DepthClearValue_bits 32 +#define GEN10_3DSTATE_CLEAR_PARAMS_DepthClearValue_bits 32 +#define GEN9_3DSTATE_CLEAR_PARAMS_DepthClearValue_bits 32 +#define GEN8_3DSTATE_CLEAR_PARAMS_DepthClearValue_bits 32 +#define GEN75_3DSTATE_CLEAR_PARAMS_DepthClearValue_bits 32 +#define GEN7_3DSTATE_CLEAR_PARAMS_DepthClearValue_bits 32 +#define GEN6_3DSTATE_CLEAR_PARAMS_DepthClearValue_bits 32 +#define GEN5_3DSTATE_CLEAR_PARAMS_DepthClearValue_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLEAR_PARAMS_DepthClearValue_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CLEAR_PARAMS_DepthClearValue_start 32 +#define GEN10_3DSTATE_CLEAR_PARAMS_DepthClearValue_start 32 +#define GEN9_3DSTATE_CLEAR_PARAMS_DepthClearValue_start 32 +#define GEN8_3DSTATE_CLEAR_PARAMS_DepthClearValue_start 32 +#define GEN75_3DSTATE_CLEAR_PARAMS_DepthClearValue_start 32 +#define GEN7_3DSTATE_CLEAR_PARAMS_DepthClearValue_start 32 +#define GEN6_3DSTATE_CLEAR_PARAMS_DepthClearValue_start 32 +#define GEN5_3DSTATE_CLEAR_PARAMS_DepthClearValue_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLEAR_PARAMS_DepthClearValue_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLEAR_PARAMS::Depth Clear Value Valid */ + + +#define GEN11_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_bits 1 +#define GEN10_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_bits 1 +#define GEN9_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_bits 1 +#define GEN8_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_bits 1 +#define GEN75_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_bits 1 +#define GEN7_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_bits 1 +#define GEN6_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_bits 1 +#define GEN5_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_start 64 +#define GEN10_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_start 64 +#define GEN9_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_start 64 +#define GEN8_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_start 64 +#define GEN75_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_start 64 +#define GEN7_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_start 64 +#define GEN6_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_start 15 +#define GEN5_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_start 15 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLEAR_PARAMS_DepthClearValueValid_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 15; + case 5: return 15; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLIP */ + + +#define GEN11_3DSTATE_CLIP_length 4 +#define GEN10_3DSTATE_CLIP_length 4 +#define GEN9_3DSTATE_CLIP_length 4 +#define GEN8_3DSTATE_CLIP_length 4 +#define GEN75_3DSTATE_CLIP_length 4 +#define GEN7_3DSTATE_CLIP_length 4 +#define GEN6_3DSTATE_CLIP_length 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLIP::3D Command Opcode */ + + +#define GEN11_3DSTATE_CLIP_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_CLIP_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_CLIP_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_CLIP_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_CLIP_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_CLIP_3DCommandOpcode_bits 3 +#define GEN6_3DSTATE_CLIP_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CLIP_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_CLIP_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_CLIP_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_CLIP_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_CLIP_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_CLIP_3DCommandOpcode_start 24 +#define GEN6_3DSTATE_CLIP_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLIP::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_CLIP_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_CLIP_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_CLIP_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_CLIP_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_CLIP_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_CLIP_3DCommandSubOpcode_bits 8 +#define GEN6_3DSTATE_CLIP_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CLIP_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_CLIP_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_CLIP_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_CLIP_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_CLIP_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_CLIP_3DCommandSubOpcode_start 16 +#define GEN6_3DSTATE_CLIP_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLIP::API Mode */ + + +#define GEN11_3DSTATE_CLIP_APIMode_bits 1 +#define GEN10_3DSTATE_CLIP_APIMode_bits 1 +#define GEN9_3DSTATE_CLIP_APIMode_bits 1 +#define GEN8_3DSTATE_CLIP_APIMode_bits 1 +#define GEN75_3DSTATE_CLIP_APIMode_bits 1 +#define GEN7_3DSTATE_CLIP_APIMode_bits 1 +#define GEN6_3DSTATE_CLIP_APIMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_APIMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CLIP_APIMode_start 94 +#define GEN10_3DSTATE_CLIP_APIMode_start 94 +#define GEN9_3DSTATE_CLIP_APIMode_start 94 +#define GEN8_3DSTATE_CLIP_APIMode_start 94 +#define GEN75_3DSTATE_CLIP_APIMode_start 94 +#define GEN7_3DSTATE_CLIP_APIMode_start 94 +#define GEN6_3DSTATE_CLIP_APIMode_start 94 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_APIMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 94; + case 10: return 94; + case 9: return 94; + case 8: return 94; + case 7: + if (devinfo->is_haswell) { + return 94; + } else { + return 94; + } + case 6: return 94; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLIP::Clip Enable */ + + +#define GEN11_3DSTATE_CLIP_ClipEnable_bits 1 +#define GEN10_3DSTATE_CLIP_ClipEnable_bits 1 +#define GEN9_3DSTATE_CLIP_ClipEnable_bits 1 +#define GEN8_3DSTATE_CLIP_ClipEnable_bits 1 +#define GEN75_3DSTATE_CLIP_ClipEnable_bits 1 +#define GEN7_3DSTATE_CLIP_ClipEnable_bits 1 +#define GEN6_3DSTATE_CLIP_ClipEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_ClipEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CLIP_ClipEnable_start 95 +#define GEN10_3DSTATE_CLIP_ClipEnable_start 95 +#define GEN9_3DSTATE_CLIP_ClipEnable_start 95 +#define GEN8_3DSTATE_CLIP_ClipEnable_start 95 +#define GEN75_3DSTATE_CLIP_ClipEnable_start 95 +#define GEN7_3DSTATE_CLIP_ClipEnable_start 95 +#define GEN6_3DSTATE_CLIP_ClipEnable_start 95 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_ClipEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 95; + case 10: return 95; + case 9: return 95; + case 8: return 95; + case 7: + if (devinfo->is_haswell) { + return 95; + } else { + return 95; + } + case 6: return 95; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLIP::Clip Mode */ + + +#define GEN11_3DSTATE_CLIP_ClipMode_bits 3 +#define GEN10_3DSTATE_CLIP_ClipMode_bits 3 +#define GEN9_3DSTATE_CLIP_ClipMode_bits 3 +#define GEN8_3DSTATE_CLIP_ClipMode_bits 3 +#define GEN75_3DSTATE_CLIP_ClipMode_bits 3 +#define GEN7_3DSTATE_CLIP_ClipMode_bits 3 +#define GEN6_3DSTATE_CLIP_ClipMode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_ClipMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CLIP_ClipMode_start 77 +#define GEN10_3DSTATE_CLIP_ClipMode_start 77 +#define GEN9_3DSTATE_CLIP_ClipMode_start 77 +#define GEN8_3DSTATE_CLIP_ClipMode_start 77 +#define GEN75_3DSTATE_CLIP_ClipMode_start 77 +#define GEN7_3DSTATE_CLIP_ClipMode_start 77 +#define GEN6_3DSTATE_CLIP_ClipMode_start 77 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_ClipMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 77; + case 10: return 77; + case 9: return 77; + case 8: return 77; + case 7: + if (devinfo->is_haswell) { + return 77; + } else { + return 77; + } + case 6: return 77; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLIP::Command SubType */ + + +#define GEN11_3DSTATE_CLIP_CommandSubType_bits 2 +#define GEN10_3DSTATE_CLIP_CommandSubType_bits 2 +#define GEN9_3DSTATE_CLIP_CommandSubType_bits 2 +#define GEN8_3DSTATE_CLIP_CommandSubType_bits 2 +#define GEN75_3DSTATE_CLIP_CommandSubType_bits 2 +#define GEN7_3DSTATE_CLIP_CommandSubType_bits 2 +#define GEN6_3DSTATE_CLIP_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CLIP_CommandSubType_start 27 +#define GEN10_3DSTATE_CLIP_CommandSubType_start 27 +#define GEN9_3DSTATE_CLIP_CommandSubType_start 27 +#define GEN8_3DSTATE_CLIP_CommandSubType_start 27 +#define GEN75_3DSTATE_CLIP_CommandSubType_start 27 +#define GEN7_3DSTATE_CLIP_CommandSubType_start 27 +#define GEN6_3DSTATE_CLIP_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLIP::Command Type */ + + +#define GEN11_3DSTATE_CLIP_CommandType_bits 3 +#define GEN10_3DSTATE_CLIP_CommandType_bits 3 +#define GEN9_3DSTATE_CLIP_CommandType_bits 3 +#define GEN8_3DSTATE_CLIP_CommandType_bits 3 +#define GEN75_3DSTATE_CLIP_CommandType_bits 3 +#define GEN7_3DSTATE_CLIP_CommandType_bits 3 +#define GEN6_3DSTATE_CLIP_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CLIP_CommandType_start 29 +#define GEN10_3DSTATE_CLIP_CommandType_start 29 +#define GEN9_3DSTATE_CLIP_CommandType_start 29 +#define GEN8_3DSTATE_CLIP_CommandType_start 29 +#define GEN75_3DSTATE_CLIP_CommandType_start 29 +#define GEN7_3DSTATE_CLIP_CommandType_start 29 +#define GEN6_3DSTATE_CLIP_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLIP::Cull Mode */ + + +#define GEN75_3DSTATE_CLIP_CullMode_bits 2 +#define GEN7_3DSTATE_CLIP_CullMode_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_CullMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_CLIP_CullMode_start 48 +#define GEN7_3DSTATE_CLIP_CullMode_start 48 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_CullMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 48; + } else { + return 48; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLIP::DWord Length */ + + +#define GEN11_3DSTATE_CLIP_DWordLength_bits 8 +#define GEN10_3DSTATE_CLIP_DWordLength_bits 8 +#define GEN9_3DSTATE_CLIP_DWordLength_bits 8 +#define GEN8_3DSTATE_CLIP_DWordLength_bits 8 +#define GEN75_3DSTATE_CLIP_DWordLength_bits 8 +#define GEN7_3DSTATE_CLIP_DWordLength_bits 8 +#define GEN6_3DSTATE_CLIP_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CLIP_DWordLength_start 0 +#define GEN10_3DSTATE_CLIP_DWordLength_start 0 +#define GEN9_3DSTATE_CLIP_DWordLength_start 0 +#define GEN8_3DSTATE_CLIP_DWordLength_start 0 +#define GEN75_3DSTATE_CLIP_DWordLength_start 0 +#define GEN7_3DSTATE_CLIP_DWordLength_start 0 +#define GEN6_3DSTATE_CLIP_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLIP::Early Cull Enable */ + + +#define GEN11_3DSTATE_CLIP_EarlyCullEnable_bits 1 +#define GEN10_3DSTATE_CLIP_EarlyCullEnable_bits 1 +#define GEN9_3DSTATE_CLIP_EarlyCullEnable_bits 1 +#define GEN8_3DSTATE_CLIP_EarlyCullEnable_bits 1 +#define GEN75_3DSTATE_CLIP_EarlyCullEnable_bits 1 +#define GEN7_3DSTATE_CLIP_EarlyCullEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_EarlyCullEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CLIP_EarlyCullEnable_start 50 +#define GEN10_3DSTATE_CLIP_EarlyCullEnable_start 50 +#define GEN9_3DSTATE_CLIP_EarlyCullEnable_start 50 +#define GEN8_3DSTATE_CLIP_EarlyCullEnable_start 50 +#define GEN75_3DSTATE_CLIP_EarlyCullEnable_start 50 +#define GEN7_3DSTATE_CLIP_EarlyCullEnable_start 50 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_EarlyCullEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 50; + case 10: return 50; + case 9: return 50; + case 8: return 50; + case 7: + if (devinfo->is_haswell) { + return 50; + } else { + return 50; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLIP::Force Clip Mode */ + + +#define GEN11_3DSTATE_CLIP_ForceClipMode_bits 1 +#define GEN10_3DSTATE_CLIP_ForceClipMode_bits 1 +#define GEN9_3DSTATE_CLIP_ForceClipMode_bits 1 +#define GEN8_3DSTATE_CLIP_ForceClipMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_ForceClipMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CLIP_ForceClipMode_start 48 +#define GEN10_3DSTATE_CLIP_ForceClipMode_start 48 +#define GEN9_3DSTATE_CLIP_ForceClipMode_start 48 +#define GEN8_3DSTATE_CLIP_ForceClipMode_start 48 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_ForceClipMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 48; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLIP::Force User Clip Distance Clip Test Enable Bitmask */ + + +#define GEN11_3DSTATE_CLIP_ForceUserClipDistanceClipTestEnableBitmask_bits 1 +#define GEN10_3DSTATE_CLIP_ForceUserClipDistanceClipTestEnableBitmask_bits 1 +#define GEN9_3DSTATE_CLIP_ForceUserClipDistanceClipTestEnableBitmask_bits 1 +#define GEN8_3DSTATE_CLIP_ForceUserClipDistanceClipTestEnableBitmask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_ForceUserClipDistanceClipTestEnableBitmask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CLIP_ForceUserClipDistanceClipTestEnableBitmask_start 49 +#define GEN10_3DSTATE_CLIP_ForceUserClipDistanceClipTestEnableBitmask_start 49 +#define GEN9_3DSTATE_CLIP_ForceUserClipDistanceClipTestEnableBitmask_start 49 +#define GEN8_3DSTATE_CLIP_ForceUserClipDistanceClipTestEnableBitmask_start 49 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_ForceUserClipDistanceClipTestEnableBitmask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 49; + case 10: return 49; + case 9: return 49; + case 8: return 49; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLIP::Force User Clip Distance Cull Test Enable Bitmask */ + + +#define GEN11_3DSTATE_CLIP_ForceUserClipDistanceCullTestEnableBitmask_bits 1 +#define GEN10_3DSTATE_CLIP_ForceUserClipDistanceCullTestEnableBitmask_bits 1 +#define GEN9_3DSTATE_CLIP_ForceUserClipDistanceCullTestEnableBitmask_bits 1 +#define GEN8_3DSTATE_CLIP_ForceUserClipDistanceCullTestEnableBitmask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_ForceUserClipDistanceCullTestEnableBitmask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CLIP_ForceUserClipDistanceCullTestEnableBitmask_start 52 +#define GEN10_3DSTATE_CLIP_ForceUserClipDistanceCullTestEnableBitmask_start 52 +#define GEN9_3DSTATE_CLIP_ForceUserClipDistanceCullTestEnableBitmask_start 52 +#define GEN8_3DSTATE_CLIP_ForceUserClipDistanceCullTestEnableBitmask_start 52 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_ForceUserClipDistanceCullTestEnableBitmask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 52; + case 10: return 52; + case 9: return 52; + case 8: return 52; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLIP::Force Zero RTA Index Enable */ + + +#define GEN11_3DSTATE_CLIP_ForceZeroRTAIndexEnable_bits 1 +#define GEN10_3DSTATE_CLIP_ForceZeroRTAIndexEnable_bits 1 +#define GEN9_3DSTATE_CLIP_ForceZeroRTAIndexEnable_bits 1 +#define GEN8_3DSTATE_CLIP_ForceZeroRTAIndexEnable_bits 1 +#define GEN75_3DSTATE_CLIP_ForceZeroRTAIndexEnable_bits 1 +#define GEN7_3DSTATE_CLIP_ForceZeroRTAIndexEnable_bits 1 +#define GEN6_3DSTATE_CLIP_ForceZeroRTAIndexEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_ForceZeroRTAIndexEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CLIP_ForceZeroRTAIndexEnable_start 101 +#define GEN10_3DSTATE_CLIP_ForceZeroRTAIndexEnable_start 101 +#define GEN9_3DSTATE_CLIP_ForceZeroRTAIndexEnable_start 101 +#define GEN8_3DSTATE_CLIP_ForceZeroRTAIndexEnable_start 101 +#define GEN75_3DSTATE_CLIP_ForceZeroRTAIndexEnable_start 101 +#define GEN7_3DSTATE_CLIP_ForceZeroRTAIndexEnable_start 101 +#define GEN6_3DSTATE_CLIP_ForceZeroRTAIndexEnable_start 101 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_ForceZeroRTAIndexEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 101; + case 10: return 101; + case 9: return 101; + case 8: return 101; + case 7: + if (devinfo->is_haswell) { + return 101; + } else { + return 101; + } + case 6: return 101; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLIP::Front Winding */ + + +#define GEN75_3DSTATE_CLIP_FrontWinding_bits 1 +#define GEN7_3DSTATE_CLIP_FrontWinding_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_FrontWinding_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_CLIP_FrontWinding_start 52 +#define GEN7_3DSTATE_CLIP_FrontWinding_start 52 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_FrontWinding_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 52; + } else { + return 52; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLIP::Guardband Clip Test Enable */ + + +#define GEN11_3DSTATE_CLIP_GuardbandClipTestEnable_bits 1 +#define GEN10_3DSTATE_CLIP_GuardbandClipTestEnable_bits 1 +#define GEN9_3DSTATE_CLIP_GuardbandClipTestEnable_bits 1 +#define GEN8_3DSTATE_CLIP_GuardbandClipTestEnable_bits 1 +#define GEN75_3DSTATE_CLIP_GuardbandClipTestEnable_bits 1 +#define GEN7_3DSTATE_CLIP_GuardbandClipTestEnable_bits 1 +#define GEN6_3DSTATE_CLIP_GuardbandClipTestEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_GuardbandClipTestEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CLIP_GuardbandClipTestEnable_start 90 +#define GEN10_3DSTATE_CLIP_GuardbandClipTestEnable_start 90 +#define GEN9_3DSTATE_CLIP_GuardbandClipTestEnable_start 90 +#define GEN8_3DSTATE_CLIP_GuardbandClipTestEnable_start 90 +#define GEN75_3DSTATE_CLIP_GuardbandClipTestEnable_start 90 +#define GEN7_3DSTATE_CLIP_GuardbandClipTestEnable_start 90 +#define GEN6_3DSTATE_CLIP_GuardbandClipTestEnable_start 90 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_GuardbandClipTestEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 90; + case 10: return 90; + case 9: return 90; + case 8: return 90; + case 7: + if (devinfo->is_haswell) { + return 90; + } else { + return 90; + } + case 6: return 90; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLIP::Line Strip/List Provoking Vertex Select */ + + +#define GEN11_3DSTATE_CLIP_LineStripListProvokingVertexSelect_bits 2 +#define GEN10_3DSTATE_CLIP_LineStripListProvokingVertexSelect_bits 2 +#define GEN9_3DSTATE_CLIP_LineStripListProvokingVertexSelect_bits 2 +#define GEN8_3DSTATE_CLIP_LineStripListProvokingVertexSelect_bits 2 +#define GEN75_3DSTATE_CLIP_LineStripListProvokingVertexSelect_bits 2 +#define GEN7_3DSTATE_CLIP_LineStripListProvokingVertexSelect_bits 2 +#define GEN6_3DSTATE_CLIP_LineStripListProvokingVertexSelect_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_LineStripListProvokingVertexSelect_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CLIP_LineStripListProvokingVertexSelect_start 66 +#define GEN10_3DSTATE_CLIP_LineStripListProvokingVertexSelect_start 66 +#define GEN9_3DSTATE_CLIP_LineStripListProvokingVertexSelect_start 66 +#define GEN8_3DSTATE_CLIP_LineStripListProvokingVertexSelect_start 66 +#define GEN75_3DSTATE_CLIP_LineStripListProvokingVertexSelect_start 66 +#define GEN7_3DSTATE_CLIP_LineStripListProvokingVertexSelect_start 66 +#define GEN6_3DSTATE_CLIP_LineStripListProvokingVertexSelect_start 66 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_LineStripListProvokingVertexSelect_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 66; + case 10: return 66; + case 9: return 66; + case 8: return 66; + case 7: + if (devinfo->is_haswell) { + return 66; + } else { + return 66; + } + case 6: return 66; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLIP::Maximum Point Width */ + + +#define GEN11_3DSTATE_CLIP_MaximumPointWidth_bits 11 +#define GEN10_3DSTATE_CLIP_MaximumPointWidth_bits 11 +#define GEN9_3DSTATE_CLIP_MaximumPointWidth_bits 11 +#define GEN8_3DSTATE_CLIP_MaximumPointWidth_bits 11 +#define GEN75_3DSTATE_CLIP_MaximumPointWidth_bits 11 +#define GEN7_3DSTATE_CLIP_MaximumPointWidth_bits 11 +#define GEN6_3DSTATE_CLIP_MaximumPointWidth_bits 11 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_MaximumPointWidth_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 11; + } else { + return 11; + } + case 6: return 11; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CLIP_MaximumPointWidth_start 102 +#define GEN10_3DSTATE_CLIP_MaximumPointWidth_start 102 +#define GEN9_3DSTATE_CLIP_MaximumPointWidth_start 102 +#define GEN8_3DSTATE_CLIP_MaximumPointWidth_start 102 +#define GEN75_3DSTATE_CLIP_MaximumPointWidth_start 102 +#define GEN7_3DSTATE_CLIP_MaximumPointWidth_start 102 +#define GEN6_3DSTATE_CLIP_MaximumPointWidth_start 102 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_MaximumPointWidth_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 102; + case 10: return 102; + case 9: return 102; + case 8: return 102; + case 7: + if (devinfo->is_haswell) { + return 102; + } else { + return 102; + } + case 6: return 102; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLIP::Maximum VP Index */ + + +#define GEN11_3DSTATE_CLIP_MaximumVPIndex_bits 4 +#define GEN10_3DSTATE_CLIP_MaximumVPIndex_bits 4 +#define GEN9_3DSTATE_CLIP_MaximumVPIndex_bits 4 +#define GEN8_3DSTATE_CLIP_MaximumVPIndex_bits 4 +#define GEN75_3DSTATE_CLIP_MaximumVPIndex_bits 4 +#define GEN7_3DSTATE_CLIP_MaximumVPIndex_bits 4 +#define GEN6_3DSTATE_CLIP_MaximumVPIndex_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_MaximumVPIndex_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CLIP_MaximumVPIndex_start 96 +#define GEN10_3DSTATE_CLIP_MaximumVPIndex_start 96 +#define GEN9_3DSTATE_CLIP_MaximumVPIndex_start 96 +#define GEN8_3DSTATE_CLIP_MaximumVPIndex_start 96 +#define GEN75_3DSTATE_CLIP_MaximumVPIndex_start 96 +#define GEN7_3DSTATE_CLIP_MaximumVPIndex_start 96 +#define GEN6_3DSTATE_CLIP_MaximumVPIndex_start 96 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_MaximumVPIndex_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 96; + case 10: return 96; + case 9: return 96; + case 8: return 96; + case 7: + if (devinfo->is_haswell) { + return 96; + } else { + return 96; + } + case 6: return 96; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLIP::Minimum Point Width */ + + +#define GEN11_3DSTATE_CLIP_MinimumPointWidth_bits 11 +#define GEN10_3DSTATE_CLIP_MinimumPointWidth_bits 11 +#define GEN9_3DSTATE_CLIP_MinimumPointWidth_bits 11 +#define GEN8_3DSTATE_CLIP_MinimumPointWidth_bits 11 +#define GEN75_3DSTATE_CLIP_MinimumPointWidth_bits 11 +#define GEN7_3DSTATE_CLIP_MinimumPointWidth_bits 11 +#define GEN6_3DSTATE_CLIP_MinimumPointWidth_bits 11 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_MinimumPointWidth_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 11; + } else { + return 11; + } + case 6: return 11; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CLIP_MinimumPointWidth_start 113 +#define GEN10_3DSTATE_CLIP_MinimumPointWidth_start 113 +#define GEN9_3DSTATE_CLIP_MinimumPointWidth_start 113 +#define GEN8_3DSTATE_CLIP_MinimumPointWidth_start 113 +#define GEN75_3DSTATE_CLIP_MinimumPointWidth_start 113 +#define GEN7_3DSTATE_CLIP_MinimumPointWidth_start 113 +#define GEN6_3DSTATE_CLIP_MinimumPointWidth_start 113 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_MinimumPointWidth_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 113; + case 10: return 113; + case 9: return 113; + case 8: return 113; + case 7: + if (devinfo->is_haswell) { + return 113; + } else { + return 113; + } + case 6: return 113; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLIP::Non-Perspective Barycentric Enable */ + + +#define GEN11_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_bits 1 +#define GEN10_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_bits 1 +#define GEN9_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_bits 1 +#define GEN8_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_bits 1 +#define GEN75_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_bits 1 +#define GEN7_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_bits 1 +#define GEN6_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_start 72 +#define GEN10_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_start 72 +#define GEN9_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_start 72 +#define GEN8_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_start 72 +#define GEN75_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_start 72 +#define GEN7_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_start 72 +#define GEN6_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_start 72 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_NonPerspectiveBarycentricEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 72; + case 10: return 72; + case 9: return 72; + case 8: return 72; + case 7: + if (devinfo->is_haswell) { + return 72; + } else { + return 72; + } + case 6: return 72; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLIP::Perspective Divide Disable */ + + +#define GEN11_3DSTATE_CLIP_PerspectiveDivideDisable_bits 1 +#define GEN10_3DSTATE_CLIP_PerspectiveDivideDisable_bits 1 +#define GEN9_3DSTATE_CLIP_PerspectiveDivideDisable_bits 1 +#define GEN8_3DSTATE_CLIP_PerspectiveDivideDisable_bits 1 +#define GEN75_3DSTATE_CLIP_PerspectiveDivideDisable_bits 1 +#define GEN7_3DSTATE_CLIP_PerspectiveDivideDisable_bits 1 +#define GEN6_3DSTATE_CLIP_PerspectiveDivideDisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_PerspectiveDivideDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CLIP_PerspectiveDivideDisable_start 73 +#define GEN10_3DSTATE_CLIP_PerspectiveDivideDisable_start 73 +#define GEN9_3DSTATE_CLIP_PerspectiveDivideDisable_start 73 +#define GEN8_3DSTATE_CLIP_PerspectiveDivideDisable_start 73 +#define GEN75_3DSTATE_CLIP_PerspectiveDivideDisable_start 73 +#define GEN7_3DSTATE_CLIP_PerspectiveDivideDisable_start 73 +#define GEN6_3DSTATE_CLIP_PerspectiveDivideDisable_start 73 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_PerspectiveDivideDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 73; + case 10: return 73; + case 9: return 73; + case 8: return 73; + case 7: + if (devinfo->is_haswell) { + return 73; + } else { + return 73; + } + case 6: return 73; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLIP::Statistics Enable */ + + +#define GEN11_3DSTATE_CLIP_StatisticsEnable_bits 1 +#define GEN10_3DSTATE_CLIP_StatisticsEnable_bits 1 +#define GEN9_3DSTATE_CLIP_StatisticsEnable_bits 1 +#define GEN8_3DSTATE_CLIP_StatisticsEnable_bits 1 +#define GEN75_3DSTATE_CLIP_StatisticsEnable_bits 1 +#define GEN7_3DSTATE_CLIP_StatisticsEnable_bits 1 +#define GEN6_3DSTATE_CLIP_StatisticsEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_StatisticsEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CLIP_StatisticsEnable_start 42 +#define GEN10_3DSTATE_CLIP_StatisticsEnable_start 42 +#define GEN9_3DSTATE_CLIP_StatisticsEnable_start 42 +#define GEN8_3DSTATE_CLIP_StatisticsEnable_start 42 +#define GEN75_3DSTATE_CLIP_StatisticsEnable_start 42 +#define GEN7_3DSTATE_CLIP_StatisticsEnable_start 42 +#define GEN6_3DSTATE_CLIP_StatisticsEnable_start 42 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_StatisticsEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 42; + case 10: return 42; + case 9: return 42; + case 8: return 42; + case 7: + if (devinfo->is_haswell) { + return 42; + } else { + return 42; + } + case 6: return 42; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLIP::Triangle Fan Provoking Vertex Select */ + + +#define GEN11_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_bits 2 +#define GEN10_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_bits 2 +#define GEN9_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_bits 2 +#define GEN8_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_bits 2 +#define GEN75_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_bits 2 +#define GEN7_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_bits 2 +#define GEN6_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_start 64 +#define GEN10_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_start 64 +#define GEN9_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_start 64 +#define GEN8_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_start 64 +#define GEN75_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_start 64 +#define GEN7_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_start 64 +#define GEN6_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_start 64 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_TriangleFanProvokingVertexSelect_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 64; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLIP::Triangle Strip/List Provoking Vertex Select */ + + +#define GEN11_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_bits 2 +#define GEN10_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_bits 2 +#define GEN9_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_bits 2 +#define GEN8_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_bits 2 +#define GEN75_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_bits 2 +#define GEN7_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_bits 2 +#define GEN6_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_start 68 +#define GEN10_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_start 68 +#define GEN9_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_start 68 +#define GEN8_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_start 68 +#define GEN75_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_start 68 +#define GEN7_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_start 68 +#define GEN6_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_start 68 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_TriangleStripListProvokingVertexSelect_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 68; + case 10: return 68; + case 9: return 68; + case 8: return 68; + case 7: + if (devinfo->is_haswell) { + return 68; + } else { + return 68; + } + case 6: return 68; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLIP::User Clip Distance Clip Test Enable Bitmask */ + + +#define GEN11_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_bits 8 +#define GEN10_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_bits 8 +#define GEN9_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_bits 8 +#define GEN8_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_bits 8 +#define GEN75_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_bits 8 +#define GEN7_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_bits 8 +#define GEN6_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_start 80 +#define GEN10_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_start 80 +#define GEN9_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_start 80 +#define GEN8_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_start 80 +#define GEN75_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_start 80 +#define GEN7_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_start 80 +#define GEN6_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_start 80 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_UserClipDistanceClipTestEnableBitmask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 80; + case 10: return 80; + case 9: return 80; + case 8: return 80; + case 7: + if (devinfo->is_haswell) { + return 80; + } else { + return 80; + } + case 6: return 80; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLIP::User Clip Distance Cull Test Enable Bitmask */ + + +#define GEN11_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_bits 8 +#define GEN10_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_bits 8 +#define GEN9_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_bits 8 +#define GEN8_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_bits 8 +#define GEN75_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_bits 8 +#define GEN7_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_bits 8 +#define GEN6_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_start 32 +#define GEN10_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_start 32 +#define GEN9_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_start 32 +#define GEN8_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_start 32 +#define GEN75_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_start 32 +#define GEN7_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_start 32 +#define GEN6_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_UserClipDistanceCullTestEnableBitmask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLIP::Vertex Sub Pixel Precision Select */ + + +#define GEN11_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_bits 1 +#define GEN10_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_bits 1 +#define GEN9_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_bits 1 +#define GEN8_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_bits 1 +#define GEN75_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_bits 1 +#define GEN7_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_start 51 +#define GEN10_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_start 51 +#define GEN9_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_start 51 +#define GEN8_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_start 51 +#define GEN75_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_start 51 +#define GEN7_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_start 51 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_VertexSubPixelPrecisionSelect_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 51; + case 10: return 51; + case 9: return 51; + case 8: return 51; + case 7: + if (devinfo->is_haswell) { + return 51; + } else { + return 51; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLIP::Viewport XY Clip Test Enable */ + + +#define GEN11_3DSTATE_CLIP_ViewportXYClipTestEnable_bits 1 +#define GEN10_3DSTATE_CLIP_ViewportXYClipTestEnable_bits 1 +#define GEN9_3DSTATE_CLIP_ViewportXYClipTestEnable_bits 1 +#define GEN8_3DSTATE_CLIP_ViewportXYClipTestEnable_bits 1 +#define GEN75_3DSTATE_CLIP_ViewportXYClipTestEnable_bits 1 +#define GEN7_3DSTATE_CLIP_ViewportXYClipTestEnable_bits 1 +#define GEN6_3DSTATE_CLIP_ViewportXYClipTestEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_ViewportXYClipTestEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CLIP_ViewportXYClipTestEnable_start 92 +#define GEN10_3DSTATE_CLIP_ViewportXYClipTestEnable_start 92 +#define GEN9_3DSTATE_CLIP_ViewportXYClipTestEnable_start 92 +#define GEN8_3DSTATE_CLIP_ViewportXYClipTestEnable_start 92 +#define GEN75_3DSTATE_CLIP_ViewportXYClipTestEnable_start 92 +#define GEN7_3DSTATE_CLIP_ViewportXYClipTestEnable_start 92 +#define GEN6_3DSTATE_CLIP_ViewportXYClipTestEnable_start 92 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_ViewportXYClipTestEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 92; + case 10: return 92; + case 9: return 92; + case 8: return 92; + case 7: + if (devinfo->is_haswell) { + return 92; + } else { + return 92; + } + case 6: return 92; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CLIP::Viewport Z Clip Test Enable */ + + +#define GEN75_3DSTATE_CLIP_ViewportZClipTestEnable_bits 1 +#define GEN7_3DSTATE_CLIP_ViewportZClipTestEnable_bits 1 +#define GEN6_3DSTATE_CLIP_ViewportZClipTestEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_ViewportZClipTestEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_CLIP_ViewportZClipTestEnable_start 91 +#define GEN7_3DSTATE_CLIP_ViewportZClipTestEnable_start 91 +#define GEN6_3DSTATE_CLIP_ViewportZClipTestEnable_start 91 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CLIP_ViewportZClipTestEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 91; + } else { + return 91; + } + case 6: return 91; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_BODY */ + + +#define GEN11_3DSTATE_CONSTANT_BODY_length 10 +#define GEN10_3DSTATE_CONSTANT_BODY_length 10 +#define GEN9_3DSTATE_CONSTANT_BODY_length 10 +#define GEN8_3DSTATE_CONSTANT_BODY_length 10 +#define GEN75_3DSTATE_CONSTANT_BODY_length 6 +#define GEN7_3DSTATE_CONSTANT_BODY_length 6 +#define GEN6_3DSTATE_CONSTANT_BODY_length 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_BODY_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 10; + case 10: return 10; + case 9: return 10; + case 8: return 10; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_BODY::Buffer */ + + +#define GEN11_3DSTATE_CONSTANT_BODY_Buffer_bits 59 +#define GEN10_3DSTATE_CONSTANT_BODY_Buffer_bits 59 +#define GEN9_3DSTATE_CONSTANT_BODY_Buffer_bits 59 +#define GEN8_3DSTATE_CONSTANT_BODY_Buffer_bits 59 +#define GEN75_3DSTATE_CONSTANT_BODY_Buffer_bits 27 +#define GEN7_3DSTATE_CONSTANT_BODY_Buffer_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_BODY_Buffer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 59; + case 10: return 59; + case 9: return 59; + case 8: return 59; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CONSTANT_BODY_Buffer_start 5 +#define GEN10_3DSTATE_CONSTANT_BODY_Buffer_start 5 +#define GEN9_3DSTATE_CONSTANT_BODY_Buffer_start 5 +#define GEN8_3DSTATE_CONSTANT_BODY_Buffer_start 5 +#define GEN75_3DSTATE_CONSTANT_BODY_Buffer_start 5 +#define GEN7_3DSTATE_CONSTANT_BODY_Buffer_start 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_BODY_Buffer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 5; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_BODY::Constant Buffer 0 Read Length */ + + +#define GEN6_3DSTATE_CONSTANT_BODY_ConstantBuffer0ReadLength_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_BODY_ConstantBuffer0ReadLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 5; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_CONSTANT_BODY_ConstantBuffer0ReadLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_BODY_ConstantBuffer0ReadLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_BODY::Constant Buffer 1 Read Length */ + + +#define GEN6_3DSTATE_CONSTANT_BODY_ConstantBuffer1ReadLength_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_BODY_ConstantBuffer1ReadLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 5; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_CONSTANT_BODY_ConstantBuffer1ReadLength_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_BODY_ConstantBuffer1ReadLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_BODY::Constant Buffer 2 Read Length */ + + +#define GEN6_3DSTATE_CONSTANT_BODY_ConstantBuffer2ReadLength_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_BODY_ConstantBuffer2ReadLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 5; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_CONSTANT_BODY_ConstantBuffer2ReadLength_start 64 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_BODY_ConstantBuffer2ReadLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 64; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_BODY::Constant Buffer 3 Read Length */ + + +#define GEN6_3DSTATE_CONSTANT_BODY_ConstantBuffer3ReadLength_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_BODY_ConstantBuffer3ReadLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 5; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_CONSTANT_BODY_ConstantBuffer3ReadLength_start 96 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_BODY_ConstantBuffer3ReadLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 96; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_BODY::MOCS */ + + +#define GEN75_3DSTATE_CONSTANT_BODY_MOCS_bits 5 +#define GEN7_3DSTATE_CONSTANT_BODY_MOCS_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_BODY_MOCS_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 5; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_CONSTANT_BODY_MOCS_start 64 +#define GEN7_3DSTATE_CONSTANT_BODY_MOCS_start 64 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_BODY_MOCS_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_BODY::Pointer to Constant Buffer 0 */ + + +#define GEN6_3DSTATE_CONSTANT_BODY_PointertoConstantBuffer0_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_BODY_PointertoConstantBuffer0_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_CONSTANT_BODY_PointertoConstantBuffer0_start 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_BODY_PointertoConstantBuffer0_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 5; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_BODY::Pointer to Constant Buffer 1 */ + + +#define GEN6_3DSTATE_CONSTANT_BODY_PointertoConstantBuffer1_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_BODY_PointertoConstantBuffer1_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_CONSTANT_BODY_PointertoConstantBuffer1_start 37 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_BODY_PointertoConstantBuffer1_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 37; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_BODY::Pointer to Constant Buffer 2 */ + + +#define GEN6_3DSTATE_CONSTANT_BODY_PointertoConstantBuffer2_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_BODY_PointertoConstantBuffer2_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_CONSTANT_BODY_PointertoConstantBuffer2_start 69 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_BODY_PointertoConstantBuffer2_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 69; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_BODY::Pointer to Constant Buffer 3 */ + + +#define GEN6_3DSTATE_CONSTANT_BODY_PointertoConstantBuffer3_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_BODY_PointertoConstantBuffer3_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_CONSTANT_BODY_PointertoConstantBuffer3_start 101 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_BODY_PointertoConstantBuffer3_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 101; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_BODY::Read Length */ + + +#define GEN11_3DSTATE_CONSTANT_BODY_ReadLength_bits 16 +#define GEN10_3DSTATE_CONSTANT_BODY_ReadLength_bits 16 +#define GEN9_3DSTATE_CONSTANT_BODY_ReadLength_bits 16 +#define GEN8_3DSTATE_CONSTANT_BODY_ReadLength_bits 16 +#define GEN75_3DSTATE_CONSTANT_BODY_ReadLength_bits 16 +#define GEN7_3DSTATE_CONSTANT_BODY_ReadLength_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_BODY_ReadLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CONSTANT_BODY_ReadLength_start 0 +#define GEN10_3DSTATE_CONSTANT_BODY_ReadLength_start 0 +#define GEN9_3DSTATE_CONSTANT_BODY_ReadLength_start 0 +#define GEN8_3DSTATE_CONSTANT_BODY_ReadLength_start 0 +#define GEN75_3DSTATE_CONSTANT_BODY_ReadLength_start 0 +#define GEN7_3DSTATE_CONSTANT_BODY_ReadLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_BODY_ReadLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_COLOR */ + + +#define GEN5_3DSTATE_CONSTANT_COLOR_length 5 +#define GEN45_3DSTATE_CONSTANT_COLOR_length 5 +#define GEN4_3DSTATE_CONSTANT_COLOR_length 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_COLOR_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 5; + case 4: + if (devinfo->is_g4x) { + return 5; + } else { + return 5; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_COLOR::3D Command Opcode */ + + +#define GEN5_3DSTATE_CONSTANT_COLOR_3DCommandOpcode_bits 3 +#define GEN45_3DSTATE_CONSTANT_COLOR_3DCommandOpcode_bits 3 +#define GEN4_3DSTATE_CONSTANT_COLOR_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_COLOR_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_3DSTATE_CONSTANT_COLOR_3DCommandOpcode_start 24 +#define GEN45_3DSTATE_CONSTANT_COLOR_3DCommandOpcode_start 24 +#define GEN4_3DSTATE_CONSTANT_COLOR_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_COLOR_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 24; + case 4: + if (devinfo->is_g4x) { + return 24; + } else { + return 24; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_COLOR::3D Command Sub Opcode */ + + +#define GEN5_3DSTATE_CONSTANT_COLOR_3DCommandSubOpcode_bits 8 +#define GEN45_3DSTATE_CONSTANT_COLOR_3DCommandSubOpcode_bits 8 +#define GEN4_3DSTATE_CONSTANT_COLOR_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_COLOR_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_3DSTATE_CONSTANT_COLOR_3DCommandSubOpcode_start 16 +#define GEN45_3DSTATE_CONSTANT_COLOR_3DCommandSubOpcode_start 16 +#define GEN4_3DSTATE_CONSTANT_COLOR_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_COLOR_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_COLOR::Blend Constant Color Alpha */ + + +#define GEN5_3DSTATE_CONSTANT_COLOR_BlendConstantColorAlpha_bits 32 +#define GEN45_3DSTATE_CONSTANT_COLOR_BlendConstantColorAlpha_bits 32 +#define GEN4_3DSTATE_CONSTANT_COLOR_BlendConstantColorAlpha_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_COLOR_BlendConstantColorAlpha_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_3DSTATE_CONSTANT_COLOR_BlendConstantColorAlpha_start 128 +#define GEN45_3DSTATE_CONSTANT_COLOR_BlendConstantColorAlpha_start 128 +#define GEN4_3DSTATE_CONSTANT_COLOR_BlendConstantColorAlpha_start 128 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_COLOR_BlendConstantColorAlpha_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 128; + case 4: + if (devinfo->is_g4x) { + return 128; + } else { + return 128; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_COLOR::Blend Constant Color Blue */ + + +#define GEN5_3DSTATE_CONSTANT_COLOR_BlendConstantColorBlue_bits 32 +#define GEN45_3DSTATE_CONSTANT_COLOR_BlendConstantColorBlue_bits 32 +#define GEN4_3DSTATE_CONSTANT_COLOR_BlendConstantColorBlue_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_COLOR_BlendConstantColorBlue_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_3DSTATE_CONSTANT_COLOR_BlendConstantColorBlue_start 96 +#define GEN45_3DSTATE_CONSTANT_COLOR_BlendConstantColorBlue_start 96 +#define GEN4_3DSTATE_CONSTANT_COLOR_BlendConstantColorBlue_start 96 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_COLOR_BlendConstantColorBlue_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 96; + case 4: + if (devinfo->is_g4x) { + return 96; + } else { + return 96; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_COLOR::Blend Constant Color Green */ + + +#define GEN5_3DSTATE_CONSTANT_COLOR_BlendConstantColorGreen_bits 32 +#define GEN45_3DSTATE_CONSTANT_COLOR_BlendConstantColorGreen_bits 32 +#define GEN4_3DSTATE_CONSTANT_COLOR_BlendConstantColorGreen_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_COLOR_BlendConstantColorGreen_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_3DSTATE_CONSTANT_COLOR_BlendConstantColorGreen_start 64 +#define GEN45_3DSTATE_CONSTANT_COLOR_BlendConstantColorGreen_start 64 +#define GEN4_3DSTATE_CONSTANT_COLOR_BlendConstantColorGreen_start 64 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_COLOR_BlendConstantColorGreen_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 64; + case 4: + if (devinfo->is_g4x) { + return 64; + } else { + return 64; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_COLOR::Blend Constant Color Red */ + + +#define GEN5_3DSTATE_CONSTANT_COLOR_BlendConstantColorRed_bits 32 +#define GEN45_3DSTATE_CONSTANT_COLOR_BlendConstantColorRed_bits 32 +#define GEN4_3DSTATE_CONSTANT_COLOR_BlendConstantColorRed_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_COLOR_BlendConstantColorRed_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_3DSTATE_CONSTANT_COLOR_BlendConstantColorRed_start 32 +#define GEN45_3DSTATE_CONSTANT_COLOR_BlendConstantColorRed_start 32 +#define GEN4_3DSTATE_CONSTANT_COLOR_BlendConstantColorRed_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_COLOR_BlendConstantColorRed_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_COLOR::Command SubType */ + + +#define GEN5_3DSTATE_CONSTANT_COLOR_CommandSubType_bits 2 +#define GEN45_3DSTATE_CONSTANT_COLOR_CommandSubType_bits 2 +#define GEN4_3DSTATE_CONSTANT_COLOR_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_COLOR_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_3DSTATE_CONSTANT_COLOR_CommandSubType_start 27 +#define GEN45_3DSTATE_CONSTANT_COLOR_CommandSubType_start 27 +#define GEN4_3DSTATE_CONSTANT_COLOR_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_COLOR_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_COLOR::Command Type */ + + +#define GEN5_3DSTATE_CONSTANT_COLOR_CommandType_bits 3 +#define GEN45_3DSTATE_CONSTANT_COLOR_CommandType_bits 3 +#define GEN4_3DSTATE_CONSTANT_COLOR_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_COLOR_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_3DSTATE_CONSTANT_COLOR_CommandType_start 29 +#define GEN45_3DSTATE_CONSTANT_COLOR_CommandType_start 29 +#define GEN4_3DSTATE_CONSTANT_COLOR_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_COLOR_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 29; + case 4: + if (devinfo->is_g4x) { + return 29; + } else { + return 29; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_COLOR::DWord Length */ + + +#define GEN5_3DSTATE_CONSTANT_COLOR_DWordLength_bits 8 +#define GEN45_3DSTATE_CONSTANT_COLOR_DWordLength_bits 8 +#define GEN4_3DSTATE_CONSTANT_COLOR_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_COLOR_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_3DSTATE_CONSTANT_COLOR_DWordLength_start 0 +#define GEN45_3DSTATE_CONSTANT_COLOR_DWordLength_start 0 +#define GEN4_3DSTATE_CONSTANT_COLOR_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_COLOR_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_DS */ + + +#define GEN11_3DSTATE_CONSTANT_DS_length 11 +#define GEN10_3DSTATE_CONSTANT_DS_length 11 +#define GEN9_3DSTATE_CONSTANT_DS_length 11 +#define GEN8_3DSTATE_CONSTANT_DS_length 11 +#define GEN75_3DSTATE_CONSTANT_DS_length 7 +#define GEN7_3DSTATE_CONSTANT_DS_length 7 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_DS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 7; + } else { + return 7; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_DS::3D Command Opcode */ + + +#define GEN11_3DSTATE_CONSTANT_DS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_CONSTANT_DS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_CONSTANT_DS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_CONSTANT_DS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_CONSTANT_DS_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_CONSTANT_DS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_DS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CONSTANT_DS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_CONSTANT_DS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_CONSTANT_DS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_CONSTANT_DS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_CONSTANT_DS_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_CONSTANT_DS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_DS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_DS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_DS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_DS::Command SubType */ + + +#define GEN11_3DSTATE_CONSTANT_DS_CommandSubType_bits 2 +#define GEN10_3DSTATE_CONSTANT_DS_CommandSubType_bits 2 +#define GEN9_3DSTATE_CONSTANT_DS_CommandSubType_bits 2 +#define GEN8_3DSTATE_CONSTANT_DS_CommandSubType_bits 2 +#define GEN75_3DSTATE_CONSTANT_DS_CommandSubType_bits 2 +#define GEN7_3DSTATE_CONSTANT_DS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_DS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CONSTANT_DS_CommandSubType_start 27 +#define GEN10_3DSTATE_CONSTANT_DS_CommandSubType_start 27 +#define GEN9_3DSTATE_CONSTANT_DS_CommandSubType_start 27 +#define GEN8_3DSTATE_CONSTANT_DS_CommandSubType_start 27 +#define GEN75_3DSTATE_CONSTANT_DS_CommandSubType_start 27 +#define GEN7_3DSTATE_CONSTANT_DS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_DS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_DS::Command Type */ + + +#define GEN11_3DSTATE_CONSTANT_DS_CommandType_bits 3 +#define GEN10_3DSTATE_CONSTANT_DS_CommandType_bits 3 +#define GEN9_3DSTATE_CONSTANT_DS_CommandType_bits 3 +#define GEN8_3DSTATE_CONSTANT_DS_CommandType_bits 3 +#define GEN75_3DSTATE_CONSTANT_DS_CommandType_bits 3 +#define GEN7_3DSTATE_CONSTANT_DS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_DS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CONSTANT_DS_CommandType_start 29 +#define GEN10_3DSTATE_CONSTANT_DS_CommandType_start 29 +#define GEN9_3DSTATE_CONSTANT_DS_CommandType_start 29 +#define GEN8_3DSTATE_CONSTANT_DS_CommandType_start 29 +#define GEN75_3DSTATE_CONSTANT_DS_CommandType_start 29 +#define GEN7_3DSTATE_CONSTANT_DS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_DS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_DS::Constant Body */ + + +#define GEN11_3DSTATE_CONSTANT_DS_ConstantBody_bits 320 +#define GEN10_3DSTATE_CONSTANT_DS_ConstantBody_bits 320 +#define GEN9_3DSTATE_CONSTANT_DS_ConstantBody_bits 320 +#define GEN8_3DSTATE_CONSTANT_DS_ConstantBody_bits 320 +#define GEN75_3DSTATE_CONSTANT_DS_ConstantBody_bits 192 +#define GEN7_3DSTATE_CONSTANT_DS_ConstantBody_bits 192 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_DS_ConstantBody_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 320; + case 10: return 320; + case 9: return 320; + case 8: return 320; + case 7: + if (devinfo->is_haswell) { + return 192; + } else { + return 192; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CONSTANT_DS_ConstantBody_start 32 +#define GEN10_3DSTATE_CONSTANT_DS_ConstantBody_start 32 +#define GEN9_3DSTATE_CONSTANT_DS_ConstantBody_start 32 +#define GEN8_3DSTATE_CONSTANT_DS_ConstantBody_start 32 +#define GEN75_3DSTATE_CONSTANT_DS_ConstantBody_start 32 +#define GEN7_3DSTATE_CONSTANT_DS_ConstantBody_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_DS_ConstantBody_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_DS::DWord Length */ + + +#define GEN11_3DSTATE_CONSTANT_DS_DWordLength_bits 8 +#define GEN10_3DSTATE_CONSTANT_DS_DWordLength_bits 8 +#define GEN9_3DSTATE_CONSTANT_DS_DWordLength_bits 8 +#define GEN8_3DSTATE_CONSTANT_DS_DWordLength_bits 8 +#define GEN75_3DSTATE_CONSTANT_DS_DWordLength_bits 8 +#define GEN7_3DSTATE_CONSTANT_DS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_DS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CONSTANT_DS_DWordLength_start 0 +#define GEN10_3DSTATE_CONSTANT_DS_DWordLength_start 0 +#define GEN9_3DSTATE_CONSTANT_DS_DWordLength_start 0 +#define GEN8_3DSTATE_CONSTANT_DS_DWordLength_start 0 +#define GEN75_3DSTATE_CONSTANT_DS_DWordLength_start 0 +#define GEN7_3DSTATE_CONSTANT_DS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_DS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_DS::MOCS */ + + +#define GEN11_3DSTATE_CONSTANT_DS_MOCS_bits 7 +#define GEN10_3DSTATE_CONSTANT_DS_MOCS_bits 7 +#define GEN9_3DSTATE_CONSTANT_DS_MOCS_bits 7 +#define GEN8_3DSTATE_CONSTANT_DS_MOCS_bits 7 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_DS_MOCS_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CONSTANT_DS_MOCS_start 8 +#define GEN10_3DSTATE_CONSTANT_DS_MOCS_start 8 +#define GEN9_3DSTATE_CONSTANT_DS_MOCS_start 8 +#define GEN8_3DSTATE_CONSTANT_DS_MOCS_start 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_DS_MOCS_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_GS */ + + +#define GEN11_3DSTATE_CONSTANT_GS_length 11 +#define GEN10_3DSTATE_CONSTANT_GS_length 11 +#define GEN9_3DSTATE_CONSTANT_GS_length 11 +#define GEN8_3DSTATE_CONSTANT_GS_length 11 +#define GEN75_3DSTATE_CONSTANT_GS_length 7 +#define GEN7_3DSTATE_CONSTANT_GS_length 7 +#define GEN6_3DSTATE_CONSTANT_GS_length 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_GS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 7; + } else { + return 7; + } + case 6: return 5; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_GS::3D Command Opcode */ + + +#define GEN11_3DSTATE_CONSTANT_GS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_CONSTANT_GS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_CONSTANT_GS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_CONSTANT_GS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_CONSTANT_GS_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_CONSTANT_GS_3DCommandOpcode_bits 3 +#define GEN6_3DSTATE_CONSTANT_GS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_GS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CONSTANT_GS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_CONSTANT_GS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_CONSTANT_GS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_CONSTANT_GS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_CONSTANT_GS_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_CONSTANT_GS_3DCommandOpcode_start 24 +#define GEN6_3DSTATE_CONSTANT_GS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_GS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_GS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_bits 8 +#define GEN6_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_start 16 +#define GEN6_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_GS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_GS::Buffer 0 Valid */ + + +#define GEN6_3DSTATE_CONSTANT_GS_Buffer0Valid_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_GS_Buffer0Valid_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_CONSTANT_GS_Buffer0Valid_start 12 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_GS_Buffer0Valid_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 12; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_GS::Buffer 1 Valid */ + + +#define GEN6_3DSTATE_CONSTANT_GS_Buffer1Valid_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_GS_Buffer1Valid_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_CONSTANT_GS_Buffer1Valid_start 13 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_GS_Buffer1Valid_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 13; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_GS::Buffer 2 Valid */ + + +#define GEN6_3DSTATE_CONSTANT_GS_Buffer2Valid_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_GS_Buffer2Valid_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_CONSTANT_GS_Buffer2Valid_start 14 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_GS_Buffer2Valid_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 14; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_GS::Buffer 3 Valid */ + + +#define GEN6_3DSTATE_CONSTANT_GS_Buffer3Valid_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_GS_Buffer3Valid_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_CONSTANT_GS_Buffer3Valid_start 15 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_GS_Buffer3Valid_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 15; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_GS::Command SubType */ + + +#define GEN11_3DSTATE_CONSTANT_GS_CommandSubType_bits 2 +#define GEN10_3DSTATE_CONSTANT_GS_CommandSubType_bits 2 +#define GEN9_3DSTATE_CONSTANT_GS_CommandSubType_bits 2 +#define GEN8_3DSTATE_CONSTANT_GS_CommandSubType_bits 2 +#define GEN75_3DSTATE_CONSTANT_GS_CommandSubType_bits 2 +#define GEN7_3DSTATE_CONSTANT_GS_CommandSubType_bits 2 +#define GEN6_3DSTATE_CONSTANT_GS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_GS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CONSTANT_GS_CommandSubType_start 27 +#define GEN10_3DSTATE_CONSTANT_GS_CommandSubType_start 27 +#define GEN9_3DSTATE_CONSTANT_GS_CommandSubType_start 27 +#define GEN8_3DSTATE_CONSTANT_GS_CommandSubType_start 27 +#define GEN75_3DSTATE_CONSTANT_GS_CommandSubType_start 27 +#define GEN7_3DSTATE_CONSTANT_GS_CommandSubType_start 27 +#define GEN6_3DSTATE_CONSTANT_GS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_GS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_GS::Command Type */ + + +#define GEN11_3DSTATE_CONSTANT_GS_CommandType_bits 3 +#define GEN10_3DSTATE_CONSTANT_GS_CommandType_bits 3 +#define GEN9_3DSTATE_CONSTANT_GS_CommandType_bits 3 +#define GEN8_3DSTATE_CONSTANT_GS_CommandType_bits 3 +#define GEN75_3DSTATE_CONSTANT_GS_CommandType_bits 3 +#define GEN7_3DSTATE_CONSTANT_GS_CommandType_bits 3 +#define GEN6_3DSTATE_CONSTANT_GS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_GS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CONSTANT_GS_CommandType_start 29 +#define GEN10_3DSTATE_CONSTANT_GS_CommandType_start 29 +#define GEN9_3DSTATE_CONSTANT_GS_CommandType_start 29 +#define GEN8_3DSTATE_CONSTANT_GS_CommandType_start 29 +#define GEN75_3DSTATE_CONSTANT_GS_CommandType_start 29 +#define GEN7_3DSTATE_CONSTANT_GS_CommandType_start 29 +#define GEN6_3DSTATE_CONSTANT_GS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_GS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_GS::Constant Body */ + + +#define GEN11_3DSTATE_CONSTANT_GS_ConstantBody_bits 320 +#define GEN10_3DSTATE_CONSTANT_GS_ConstantBody_bits 320 +#define GEN9_3DSTATE_CONSTANT_GS_ConstantBody_bits 320 +#define GEN8_3DSTATE_CONSTANT_GS_ConstantBody_bits 320 +#define GEN75_3DSTATE_CONSTANT_GS_ConstantBody_bits 192 +#define GEN7_3DSTATE_CONSTANT_GS_ConstantBody_bits 192 +#define GEN6_3DSTATE_CONSTANT_GS_ConstantBody_bits 128 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_GS_ConstantBody_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 320; + case 10: return 320; + case 9: return 320; + case 8: return 320; + case 7: + if (devinfo->is_haswell) { + return 192; + } else { + return 192; + } + case 6: return 128; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CONSTANT_GS_ConstantBody_start 32 +#define GEN10_3DSTATE_CONSTANT_GS_ConstantBody_start 32 +#define GEN9_3DSTATE_CONSTANT_GS_ConstantBody_start 32 +#define GEN8_3DSTATE_CONSTANT_GS_ConstantBody_start 32 +#define GEN75_3DSTATE_CONSTANT_GS_ConstantBody_start 32 +#define GEN7_3DSTATE_CONSTANT_GS_ConstantBody_start 32 +#define GEN6_3DSTATE_CONSTANT_GS_ConstantBody_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_GS_ConstantBody_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_GS::DWord Length */ + + +#define GEN11_3DSTATE_CONSTANT_GS_DWordLength_bits 8 +#define GEN10_3DSTATE_CONSTANT_GS_DWordLength_bits 8 +#define GEN9_3DSTATE_CONSTANT_GS_DWordLength_bits 8 +#define GEN8_3DSTATE_CONSTANT_GS_DWordLength_bits 8 +#define GEN75_3DSTATE_CONSTANT_GS_DWordLength_bits 8 +#define GEN7_3DSTATE_CONSTANT_GS_DWordLength_bits 8 +#define GEN6_3DSTATE_CONSTANT_GS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_GS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CONSTANT_GS_DWordLength_start 0 +#define GEN10_3DSTATE_CONSTANT_GS_DWordLength_start 0 +#define GEN9_3DSTATE_CONSTANT_GS_DWordLength_start 0 +#define GEN8_3DSTATE_CONSTANT_GS_DWordLength_start 0 +#define GEN75_3DSTATE_CONSTANT_GS_DWordLength_start 0 +#define GEN7_3DSTATE_CONSTANT_GS_DWordLength_start 0 +#define GEN6_3DSTATE_CONSTANT_GS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_GS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_GS::MOCS */ + + +#define GEN11_3DSTATE_CONSTANT_GS_MOCS_bits 7 +#define GEN10_3DSTATE_CONSTANT_GS_MOCS_bits 7 +#define GEN9_3DSTATE_CONSTANT_GS_MOCS_bits 7 +#define GEN8_3DSTATE_CONSTANT_GS_MOCS_bits 7 +#define GEN6_3DSTATE_CONSTANT_GS_MOCS_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_GS_MOCS_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CONSTANT_GS_MOCS_start 8 +#define GEN10_3DSTATE_CONSTANT_GS_MOCS_start 8 +#define GEN9_3DSTATE_CONSTANT_GS_MOCS_start 8 +#define GEN8_3DSTATE_CONSTANT_GS_MOCS_start 8 +#define GEN6_3DSTATE_CONSTANT_GS_MOCS_start 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_GS_MOCS_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_HS */ + + +#define GEN11_3DSTATE_CONSTANT_HS_length 11 +#define GEN10_3DSTATE_CONSTANT_HS_length 11 +#define GEN9_3DSTATE_CONSTANT_HS_length 11 +#define GEN8_3DSTATE_CONSTANT_HS_length 11 +#define GEN75_3DSTATE_CONSTANT_HS_length 7 +#define GEN7_3DSTATE_CONSTANT_HS_length 7 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_HS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 7; + } else { + return 7; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_HS::3D Command Opcode */ + + +#define GEN11_3DSTATE_CONSTANT_HS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_CONSTANT_HS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_CONSTANT_HS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_CONSTANT_HS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_CONSTANT_HS_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_CONSTANT_HS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_HS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CONSTANT_HS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_CONSTANT_HS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_CONSTANT_HS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_CONSTANT_HS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_CONSTANT_HS_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_CONSTANT_HS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_HS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_HS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_HS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_HS::Command SubType */ + + +#define GEN11_3DSTATE_CONSTANT_HS_CommandSubType_bits 2 +#define GEN10_3DSTATE_CONSTANT_HS_CommandSubType_bits 2 +#define GEN9_3DSTATE_CONSTANT_HS_CommandSubType_bits 2 +#define GEN8_3DSTATE_CONSTANT_HS_CommandSubType_bits 2 +#define GEN75_3DSTATE_CONSTANT_HS_CommandSubType_bits 2 +#define GEN7_3DSTATE_CONSTANT_HS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_HS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CONSTANT_HS_CommandSubType_start 27 +#define GEN10_3DSTATE_CONSTANT_HS_CommandSubType_start 27 +#define GEN9_3DSTATE_CONSTANT_HS_CommandSubType_start 27 +#define GEN8_3DSTATE_CONSTANT_HS_CommandSubType_start 27 +#define GEN75_3DSTATE_CONSTANT_HS_CommandSubType_start 27 +#define GEN7_3DSTATE_CONSTANT_HS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_HS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_HS::Command Type */ + + +#define GEN11_3DSTATE_CONSTANT_HS_CommandType_bits 3 +#define GEN10_3DSTATE_CONSTANT_HS_CommandType_bits 3 +#define GEN9_3DSTATE_CONSTANT_HS_CommandType_bits 3 +#define GEN8_3DSTATE_CONSTANT_HS_CommandType_bits 3 +#define GEN75_3DSTATE_CONSTANT_HS_CommandType_bits 3 +#define GEN7_3DSTATE_CONSTANT_HS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_HS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CONSTANT_HS_CommandType_start 29 +#define GEN10_3DSTATE_CONSTANT_HS_CommandType_start 29 +#define GEN9_3DSTATE_CONSTANT_HS_CommandType_start 29 +#define GEN8_3DSTATE_CONSTANT_HS_CommandType_start 29 +#define GEN75_3DSTATE_CONSTANT_HS_CommandType_start 29 +#define GEN7_3DSTATE_CONSTANT_HS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_HS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_HS::Constant Body */ + + +#define GEN11_3DSTATE_CONSTANT_HS_ConstantBody_bits 320 +#define GEN10_3DSTATE_CONSTANT_HS_ConstantBody_bits 320 +#define GEN9_3DSTATE_CONSTANT_HS_ConstantBody_bits 320 +#define GEN8_3DSTATE_CONSTANT_HS_ConstantBody_bits 320 +#define GEN75_3DSTATE_CONSTANT_HS_ConstantBody_bits 192 +#define GEN7_3DSTATE_CONSTANT_HS_ConstantBody_bits 192 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_HS_ConstantBody_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 320; + case 10: return 320; + case 9: return 320; + case 8: return 320; + case 7: + if (devinfo->is_haswell) { + return 192; + } else { + return 192; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CONSTANT_HS_ConstantBody_start 32 +#define GEN10_3DSTATE_CONSTANT_HS_ConstantBody_start 32 +#define GEN9_3DSTATE_CONSTANT_HS_ConstantBody_start 32 +#define GEN8_3DSTATE_CONSTANT_HS_ConstantBody_start 32 +#define GEN75_3DSTATE_CONSTANT_HS_ConstantBody_start 32 +#define GEN7_3DSTATE_CONSTANT_HS_ConstantBody_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_HS_ConstantBody_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_HS::DWord Length */ + + +#define GEN11_3DSTATE_CONSTANT_HS_DWordLength_bits 8 +#define GEN10_3DSTATE_CONSTANT_HS_DWordLength_bits 8 +#define GEN9_3DSTATE_CONSTANT_HS_DWordLength_bits 8 +#define GEN8_3DSTATE_CONSTANT_HS_DWordLength_bits 8 +#define GEN75_3DSTATE_CONSTANT_HS_DWordLength_bits 8 +#define GEN7_3DSTATE_CONSTANT_HS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_HS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CONSTANT_HS_DWordLength_start 0 +#define GEN10_3DSTATE_CONSTANT_HS_DWordLength_start 0 +#define GEN9_3DSTATE_CONSTANT_HS_DWordLength_start 0 +#define GEN8_3DSTATE_CONSTANT_HS_DWordLength_start 0 +#define GEN75_3DSTATE_CONSTANT_HS_DWordLength_start 0 +#define GEN7_3DSTATE_CONSTANT_HS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_HS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_HS::MOCS */ + + +#define GEN11_3DSTATE_CONSTANT_HS_MOCS_bits 7 +#define GEN10_3DSTATE_CONSTANT_HS_MOCS_bits 7 +#define GEN9_3DSTATE_CONSTANT_HS_MOCS_bits 7 +#define GEN8_3DSTATE_CONSTANT_HS_MOCS_bits 7 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_HS_MOCS_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CONSTANT_HS_MOCS_start 8 +#define GEN10_3DSTATE_CONSTANT_HS_MOCS_start 8 +#define GEN9_3DSTATE_CONSTANT_HS_MOCS_start 8 +#define GEN8_3DSTATE_CONSTANT_HS_MOCS_start 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_HS_MOCS_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_PS */ + + +#define GEN11_3DSTATE_CONSTANT_PS_length 11 +#define GEN10_3DSTATE_CONSTANT_PS_length 11 +#define GEN9_3DSTATE_CONSTANT_PS_length 11 +#define GEN8_3DSTATE_CONSTANT_PS_length 11 +#define GEN75_3DSTATE_CONSTANT_PS_length 7 +#define GEN7_3DSTATE_CONSTANT_PS_length 7 +#define GEN6_3DSTATE_CONSTANT_PS_length 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_PS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 7; + } else { + return 7; + } + case 6: return 5; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_PS::3D Command Opcode */ + + +#define GEN11_3DSTATE_CONSTANT_PS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_CONSTANT_PS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_CONSTANT_PS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_CONSTANT_PS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_CONSTANT_PS_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_CONSTANT_PS_3DCommandOpcode_bits 3 +#define GEN6_3DSTATE_CONSTANT_PS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_PS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CONSTANT_PS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_CONSTANT_PS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_CONSTANT_PS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_CONSTANT_PS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_CONSTANT_PS_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_CONSTANT_PS_3DCommandOpcode_start 24 +#define GEN6_3DSTATE_CONSTANT_PS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_PS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_PS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_bits 8 +#define GEN6_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_start 16 +#define GEN6_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_PS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_PS::Buffer 0 Valid */ + + +#define GEN6_3DSTATE_CONSTANT_PS_Buffer0Valid_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_PS_Buffer0Valid_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_CONSTANT_PS_Buffer0Valid_start 12 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_PS_Buffer0Valid_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 12; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_PS::Buffer 1 Valid */ + + +#define GEN6_3DSTATE_CONSTANT_PS_Buffer1Valid_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_PS_Buffer1Valid_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_CONSTANT_PS_Buffer1Valid_start 13 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_PS_Buffer1Valid_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 13; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_PS::Buffer 2 Valid */ + + +#define GEN6_3DSTATE_CONSTANT_PS_Buffer2Valid_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_PS_Buffer2Valid_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_CONSTANT_PS_Buffer2Valid_start 14 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_PS_Buffer2Valid_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 14; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_PS::Buffer 3 Valid */ + + +#define GEN6_3DSTATE_CONSTANT_PS_Buffer3Valid_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_PS_Buffer3Valid_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_CONSTANT_PS_Buffer3Valid_start 15 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_PS_Buffer3Valid_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 15; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_PS::Command SubType */ + + +#define GEN11_3DSTATE_CONSTANT_PS_CommandSubType_bits 2 +#define GEN10_3DSTATE_CONSTANT_PS_CommandSubType_bits 2 +#define GEN9_3DSTATE_CONSTANT_PS_CommandSubType_bits 2 +#define GEN8_3DSTATE_CONSTANT_PS_CommandSubType_bits 2 +#define GEN75_3DSTATE_CONSTANT_PS_CommandSubType_bits 2 +#define GEN7_3DSTATE_CONSTANT_PS_CommandSubType_bits 2 +#define GEN6_3DSTATE_CONSTANT_PS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_PS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CONSTANT_PS_CommandSubType_start 27 +#define GEN10_3DSTATE_CONSTANT_PS_CommandSubType_start 27 +#define GEN9_3DSTATE_CONSTANT_PS_CommandSubType_start 27 +#define GEN8_3DSTATE_CONSTANT_PS_CommandSubType_start 27 +#define GEN75_3DSTATE_CONSTANT_PS_CommandSubType_start 27 +#define GEN7_3DSTATE_CONSTANT_PS_CommandSubType_start 27 +#define GEN6_3DSTATE_CONSTANT_PS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_PS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_PS::Command Type */ + + +#define GEN11_3DSTATE_CONSTANT_PS_CommandType_bits 3 +#define GEN10_3DSTATE_CONSTANT_PS_CommandType_bits 3 +#define GEN9_3DSTATE_CONSTANT_PS_CommandType_bits 3 +#define GEN8_3DSTATE_CONSTANT_PS_CommandType_bits 3 +#define GEN75_3DSTATE_CONSTANT_PS_CommandType_bits 3 +#define GEN7_3DSTATE_CONSTANT_PS_CommandType_bits 3 +#define GEN6_3DSTATE_CONSTANT_PS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_PS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CONSTANT_PS_CommandType_start 29 +#define GEN10_3DSTATE_CONSTANT_PS_CommandType_start 29 +#define GEN9_3DSTATE_CONSTANT_PS_CommandType_start 29 +#define GEN8_3DSTATE_CONSTANT_PS_CommandType_start 29 +#define GEN75_3DSTATE_CONSTANT_PS_CommandType_start 29 +#define GEN7_3DSTATE_CONSTANT_PS_CommandType_start 29 +#define GEN6_3DSTATE_CONSTANT_PS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_PS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_PS::Constant Body */ + + +#define GEN11_3DSTATE_CONSTANT_PS_ConstantBody_bits 320 +#define GEN10_3DSTATE_CONSTANT_PS_ConstantBody_bits 320 +#define GEN9_3DSTATE_CONSTANT_PS_ConstantBody_bits 320 +#define GEN8_3DSTATE_CONSTANT_PS_ConstantBody_bits 320 +#define GEN75_3DSTATE_CONSTANT_PS_ConstantBody_bits 192 +#define GEN7_3DSTATE_CONSTANT_PS_ConstantBody_bits 192 +#define GEN6_3DSTATE_CONSTANT_PS_ConstantBody_bits 128 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_PS_ConstantBody_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 320; + case 10: return 320; + case 9: return 320; + case 8: return 320; + case 7: + if (devinfo->is_haswell) { + return 192; + } else { + return 192; + } + case 6: return 128; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CONSTANT_PS_ConstantBody_start 32 +#define GEN10_3DSTATE_CONSTANT_PS_ConstantBody_start 32 +#define GEN9_3DSTATE_CONSTANT_PS_ConstantBody_start 32 +#define GEN8_3DSTATE_CONSTANT_PS_ConstantBody_start 32 +#define GEN75_3DSTATE_CONSTANT_PS_ConstantBody_start 32 +#define GEN7_3DSTATE_CONSTANT_PS_ConstantBody_start 32 +#define GEN6_3DSTATE_CONSTANT_PS_ConstantBody_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_PS_ConstantBody_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_PS::DWord Length */ + + +#define GEN11_3DSTATE_CONSTANT_PS_DWordLength_bits 8 +#define GEN10_3DSTATE_CONSTANT_PS_DWordLength_bits 8 +#define GEN9_3DSTATE_CONSTANT_PS_DWordLength_bits 8 +#define GEN8_3DSTATE_CONSTANT_PS_DWordLength_bits 8 +#define GEN75_3DSTATE_CONSTANT_PS_DWordLength_bits 8 +#define GEN7_3DSTATE_CONSTANT_PS_DWordLength_bits 8 +#define GEN6_3DSTATE_CONSTANT_PS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_PS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CONSTANT_PS_DWordLength_start 0 +#define GEN10_3DSTATE_CONSTANT_PS_DWordLength_start 0 +#define GEN9_3DSTATE_CONSTANT_PS_DWordLength_start 0 +#define GEN8_3DSTATE_CONSTANT_PS_DWordLength_start 0 +#define GEN75_3DSTATE_CONSTANT_PS_DWordLength_start 0 +#define GEN7_3DSTATE_CONSTANT_PS_DWordLength_start 0 +#define GEN6_3DSTATE_CONSTANT_PS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_PS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_PS::Disable Gather at Set Shader Hint */ + + +#define GEN11_3DSTATE_CONSTANT_PS_DisableGatheratSetShaderHint_bits 1 +#define GEN10_3DSTATE_CONSTANT_PS_DisableGatheratSetShaderHint_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_PS_DisableGatheratSetShaderHint_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CONSTANT_PS_DisableGatheratSetShaderHint_start 15 +#define GEN10_3DSTATE_CONSTANT_PS_DisableGatheratSetShaderHint_start 15 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_PS_DisableGatheratSetShaderHint_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 15; + case 10: return 15; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_PS::MOCS */ + + +#define GEN11_3DSTATE_CONSTANT_PS_MOCS_bits 7 +#define GEN10_3DSTATE_CONSTANT_PS_MOCS_bits 7 +#define GEN9_3DSTATE_CONSTANT_PS_MOCS_bits 7 +#define GEN8_3DSTATE_CONSTANT_PS_MOCS_bits 7 +#define GEN6_3DSTATE_CONSTANT_PS_MOCS_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_PS_MOCS_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CONSTANT_PS_MOCS_start 8 +#define GEN10_3DSTATE_CONSTANT_PS_MOCS_start 8 +#define GEN9_3DSTATE_CONSTANT_PS_MOCS_start 8 +#define GEN8_3DSTATE_CONSTANT_PS_MOCS_start 8 +#define GEN6_3DSTATE_CONSTANT_PS_MOCS_start 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_PS_MOCS_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_VS */ + + +#define GEN11_3DSTATE_CONSTANT_VS_length 11 +#define GEN10_3DSTATE_CONSTANT_VS_length 11 +#define GEN9_3DSTATE_CONSTANT_VS_length 11 +#define GEN8_3DSTATE_CONSTANT_VS_length 11 +#define GEN75_3DSTATE_CONSTANT_VS_length 7 +#define GEN7_3DSTATE_CONSTANT_VS_length 7 +#define GEN6_3DSTATE_CONSTANT_VS_length 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_VS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 7; + } else { + return 7; + } + case 6: return 5; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_VS::3D Command Opcode */ + + +#define GEN11_3DSTATE_CONSTANT_VS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_CONSTANT_VS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_CONSTANT_VS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_CONSTANT_VS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_CONSTANT_VS_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_CONSTANT_VS_3DCommandOpcode_bits 3 +#define GEN6_3DSTATE_CONSTANT_VS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_VS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CONSTANT_VS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_CONSTANT_VS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_CONSTANT_VS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_CONSTANT_VS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_CONSTANT_VS_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_CONSTANT_VS_3DCommandOpcode_start 24 +#define GEN6_3DSTATE_CONSTANT_VS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_VS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_VS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_bits 8 +#define GEN6_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_start 16 +#define GEN6_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_VS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_VS::Buffer 0 Valid */ + + +#define GEN6_3DSTATE_CONSTANT_VS_Buffer0Valid_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_VS_Buffer0Valid_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_CONSTANT_VS_Buffer0Valid_start 12 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_VS_Buffer0Valid_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 12; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_VS::Buffer 1 Valid */ + + +#define GEN6_3DSTATE_CONSTANT_VS_Buffer1Valid_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_VS_Buffer1Valid_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_CONSTANT_VS_Buffer1Valid_start 13 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_VS_Buffer1Valid_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 13; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_VS::Buffer 2 Valid */ + + +#define GEN6_3DSTATE_CONSTANT_VS_Buffer2Valid_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_VS_Buffer2Valid_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_CONSTANT_VS_Buffer2Valid_start 14 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_VS_Buffer2Valid_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 14; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_VS::Buffer 3 Valid */ + + +#define GEN6_3DSTATE_CONSTANT_VS_Buffer3Valid_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_VS_Buffer3Valid_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_CONSTANT_VS_Buffer3Valid_start 15 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_VS_Buffer3Valid_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 15; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_VS::Command SubType */ + + +#define GEN11_3DSTATE_CONSTANT_VS_CommandSubType_bits 2 +#define GEN10_3DSTATE_CONSTANT_VS_CommandSubType_bits 2 +#define GEN9_3DSTATE_CONSTANT_VS_CommandSubType_bits 2 +#define GEN8_3DSTATE_CONSTANT_VS_CommandSubType_bits 2 +#define GEN75_3DSTATE_CONSTANT_VS_CommandSubType_bits 2 +#define GEN7_3DSTATE_CONSTANT_VS_CommandSubType_bits 2 +#define GEN6_3DSTATE_CONSTANT_VS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_VS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CONSTANT_VS_CommandSubType_start 27 +#define GEN10_3DSTATE_CONSTANT_VS_CommandSubType_start 27 +#define GEN9_3DSTATE_CONSTANT_VS_CommandSubType_start 27 +#define GEN8_3DSTATE_CONSTANT_VS_CommandSubType_start 27 +#define GEN75_3DSTATE_CONSTANT_VS_CommandSubType_start 27 +#define GEN7_3DSTATE_CONSTANT_VS_CommandSubType_start 27 +#define GEN6_3DSTATE_CONSTANT_VS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_VS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_VS::Command Type */ + + +#define GEN11_3DSTATE_CONSTANT_VS_CommandType_bits 3 +#define GEN10_3DSTATE_CONSTANT_VS_CommandType_bits 3 +#define GEN9_3DSTATE_CONSTANT_VS_CommandType_bits 3 +#define GEN8_3DSTATE_CONSTANT_VS_CommandType_bits 3 +#define GEN75_3DSTATE_CONSTANT_VS_CommandType_bits 3 +#define GEN7_3DSTATE_CONSTANT_VS_CommandType_bits 3 +#define GEN6_3DSTATE_CONSTANT_VS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_VS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CONSTANT_VS_CommandType_start 29 +#define GEN10_3DSTATE_CONSTANT_VS_CommandType_start 29 +#define GEN9_3DSTATE_CONSTANT_VS_CommandType_start 29 +#define GEN8_3DSTATE_CONSTANT_VS_CommandType_start 29 +#define GEN75_3DSTATE_CONSTANT_VS_CommandType_start 29 +#define GEN7_3DSTATE_CONSTANT_VS_CommandType_start 29 +#define GEN6_3DSTATE_CONSTANT_VS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_VS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_VS::Constant Body */ + + +#define GEN11_3DSTATE_CONSTANT_VS_ConstantBody_bits 320 +#define GEN10_3DSTATE_CONSTANT_VS_ConstantBody_bits 320 +#define GEN9_3DSTATE_CONSTANT_VS_ConstantBody_bits 320 +#define GEN8_3DSTATE_CONSTANT_VS_ConstantBody_bits 320 +#define GEN75_3DSTATE_CONSTANT_VS_ConstantBody_bits 192 +#define GEN7_3DSTATE_CONSTANT_VS_ConstantBody_bits 192 +#define GEN6_3DSTATE_CONSTANT_VS_ConstantBody_bits 128 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_VS_ConstantBody_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 320; + case 10: return 320; + case 9: return 320; + case 8: return 320; + case 7: + if (devinfo->is_haswell) { + return 192; + } else { + return 192; + } + case 6: return 128; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CONSTANT_VS_ConstantBody_start 32 +#define GEN10_3DSTATE_CONSTANT_VS_ConstantBody_start 32 +#define GEN9_3DSTATE_CONSTANT_VS_ConstantBody_start 32 +#define GEN8_3DSTATE_CONSTANT_VS_ConstantBody_start 32 +#define GEN75_3DSTATE_CONSTANT_VS_ConstantBody_start 32 +#define GEN7_3DSTATE_CONSTANT_VS_ConstantBody_start 32 +#define GEN6_3DSTATE_CONSTANT_VS_ConstantBody_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_VS_ConstantBody_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_VS::DWord Length */ + + +#define GEN11_3DSTATE_CONSTANT_VS_DWordLength_bits 8 +#define GEN10_3DSTATE_CONSTANT_VS_DWordLength_bits 8 +#define GEN9_3DSTATE_CONSTANT_VS_DWordLength_bits 8 +#define GEN8_3DSTATE_CONSTANT_VS_DWordLength_bits 8 +#define GEN75_3DSTATE_CONSTANT_VS_DWordLength_bits 8 +#define GEN7_3DSTATE_CONSTANT_VS_DWordLength_bits 8 +#define GEN6_3DSTATE_CONSTANT_VS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_VS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CONSTANT_VS_DWordLength_start 0 +#define GEN10_3DSTATE_CONSTANT_VS_DWordLength_start 0 +#define GEN9_3DSTATE_CONSTANT_VS_DWordLength_start 0 +#define GEN8_3DSTATE_CONSTANT_VS_DWordLength_start 0 +#define GEN75_3DSTATE_CONSTANT_VS_DWordLength_start 0 +#define GEN7_3DSTATE_CONSTANT_VS_DWordLength_start 0 +#define GEN6_3DSTATE_CONSTANT_VS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_VS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_CONSTANT_VS::MOCS */ + + +#define GEN11_3DSTATE_CONSTANT_VS_MOCS_bits 7 +#define GEN10_3DSTATE_CONSTANT_VS_MOCS_bits 7 +#define GEN9_3DSTATE_CONSTANT_VS_MOCS_bits 7 +#define GEN8_3DSTATE_CONSTANT_VS_MOCS_bits 7 +#define GEN6_3DSTATE_CONSTANT_VS_MOCS_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_VS_MOCS_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_CONSTANT_VS_MOCS_start 8 +#define GEN10_3DSTATE_CONSTANT_VS_MOCS_start 8 +#define GEN9_3DSTATE_CONSTANT_VS_MOCS_start 8 +#define GEN8_3DSTATE_CONSTANT_VS_MOCS_start 8 +#define GEN6_3DSTATE_CONSTANT_VS_MOCS_start 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_CONSTANT_VS_MOCS_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DEPTH_BUFFER */ + + +#define GEN11_3DSTATE_DEPTH_BUFFER_length 8 +#define GEN10_3DSTATE_DEPTH_BUFFER_length 8 +#define GEN9_3DSTATE_DEPTH_BUFFER_length 8 +#define GEN8_3DSTATE_DEPTH_BUFFER_length 8 +#define GEN75_3DSTATE_DEPTH_BUFFER_length 7 +#define GEN7_3DSTATE_DEPTH_BUFFER_length 7 +#define GEN6_3DSTATE_DEPTH_BUFFER_length 7 +#define GEN5_3DSTATE_DEPTH_BUFFER_length 6 +#define GEN45_3DSTATE_DEPTH_BUFFER_length 6 +#define GEN4_3DSTATE_DEPTH_BUFFER_length 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 7; + } else { + return 7; + } + case 6: return 7; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 5; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DEPTH_BUFFER::3D Command Opcode */ + + +#define GEN11_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_bits 3 +#define GEN6_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_bits 3 +#define GEN5_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_bits 3 +#define GEN45_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_bits 3 +#define GEN4_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_start 24 +#define GEN6_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_start 24 +#define GEN5_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_start 24 +#define GEN45_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_start 24 +#define GEN4_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 24; + case 4: + if (devinfo->is_g4x) { + return 24; + } else { + return 24; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DEPTH_BUFFER::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN6_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN5_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN45_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN4_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_start 16 +#define GEN6_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_start 16 +#define GEN5_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_start 16 +#define GEN45_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_start 16 +#define GEN4_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DEPTH_BUFFER::Command SubType */ + + +#define GEN11_3DSTATE_DEPTH_BUFFER_CommandSubType_bits 2 +#define GEN10_3DSTATE_DEPTH_BUFFER_CommandSubType_bits 2 +#define GEN9_3DSTATE_DEPTH_BUFFER_CommandSubType_bits 2 +#define GEN8_3DSTATE_DEPTH_BUFFER_CommandSubType_bits 2 +#define GEN75_3DSTATE_DEPTH_BUFFER_CommandSubType_bits 2 +#define GEN7_3DSTATE_DEPTH_BUFFER_CommandSubType_bits 2 +#define GEN6_3DSTATE_DEPTH_BUFFER_CommandSubType_bits 2 +#define GEN5_3DSTATE_DEPTH_BUFFER_CommandSubType_bits 2 +#define GEN45_3DSTATE_DEPTH_BUFFER_CommandSubType_bits 2 +#define GEN4_3DSTATE_DEPTH_BUFFER_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DEPTH_BUFFER_CommandSubType_start 27 +#define GEN10_3DSTATE_DEPTH_BUFFER_CommandSubType_start 27 +#define GEN9_3DSTATE_DEPTH_BUFFER_CommandSubType_start 27 +#define GEN8_3DSTATE_DEPTH_BUFFER_CommandSubType_start 27 +#define GEN75_3DSTATE_DEPTH_BUFFER_CommandSubType_start 27 +#define GEN7_3DSTATE_DEPTH_BUFFER_CommandSubType_start 27 +#define GEN6_3DSTATE_DEPTH_BUFFER_CommandSubType_start 27 +#define GEN5_3DSTATE_DEPTH_BUFFER_CommandSubType_start 27 +#define GEN45_3DSTATE_DEPTH_BUFFER_CommandSubType_start 27 +#define GEN4_3DSTATE_DEPTH_BUFFER_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DEPTH_BUFFER::Command Type */ + + +#define GEN11_3DSTATE_DEPTH_BUFFER_CommandType_bits 3 +#define GEN10_3DSTATE_DEPTH_BUFFER_CommandType_bits 3 +#define GEN9_3DSTATE_DEPTH_BUFFER_CommandType_bits 3 +#define GEN8_3DSTATE_DEPTH_BUFFER_CommandType_bits 3 +#define GEN75_3DSTATE_DEPTH_BUFFER_CommandType_bits 3 +#define GEN7_3DSTATE_DEPTH_BUFFER_CommandType_bits 3 +#define GEN6_3DSTATE_DEPTH_BUFFER_CommandType_bits 3 +#define GEN5_3DSTATE_DEPTH_BUFFER_CommandType_bits 3 +#define GEN45_3DSTATE_DEPTH_BUFFER_CommandType_bits 3 +#define GEN4_3DSTATE_DEPTH_BUFFER_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DEPTH_BUFFER_CommandType_start 29 +#define GEN10_3DSTATE_DEPTH_BUFFER_CommandType_start 29 +#define GEN9_3DSTATE_DEPTH_BUFFER_CommandType_start 29 +#define GEN8_3DSTATE_DEPTH_BUFFER_CommandType_start 29 +#define GEN75_3DSTATE_DEPTH_BUFFER_CommandType_start 29 +#define GEN7_3DSTATE_DEPTH_BUFFER_CommandType_start 29 +#define GEN6_3DSTATE_DEPTH_BUFFER_CommandType_start 29 +#define GEN5_3DSTATE_DEPTH_BUFFER_CommandType_start 29 +#define GEN45_3DSTATE_DEPTH_BUFFER_CommandType_start 29 +#define GEN4_3DSTATE_DEPTH_BUFFER_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 29; + case 4: + if (devinfo->is_g4x) { + return 29; + } else { + return 29; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DEPTH_BUFFER::DWord Length */ + + +#define GEN11_3DSTATE_DEPTH_BUFFER_DWordLength_bits 8 +#define GEN10_3DSTATE_DEPTH_BUFFER_DWordLength_bits 8 +#define GEN9_3DSTATE_DEPTH_BUFFER_DWordLength_bits 8 +#define GEN8_3DSTATE_DEPTH_BUFFER_DWordLength_bits 8 +#define GEN75_3DSTATE_DEPTH_BUFFER_DWordLength_bits 8 +#define GEN7_3DSTATE_DEPTH_BUFFER_DWordLength_bits 8 +#define GEN6_3DSTATE_DEPTH_BUFFER_DWordLength_bits 8 +#define GEN5_3DSTATE_DEPTH_BUFFER_DWordLength_bits 8 +#define GEN45_3DSTATE_DEPTH_BUFFER_DWordLength_bits 8 +#define GEN4_3DSTATE_DEPTH_BUFFER_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DEPTH_BUFFER_DWordLength_start 0 +#define GEN10_3DSTATE_DEPTH_BUFFER_DWordLength_start 0 +#define GEN9_3DSTATE_DEPTH_BUFFER_DWordLength_start 0 +#define GEN8_3DSTATE_DEPTH_BUFFER_DWordLength_start 0 +#define GEN75_3DSTATE_DEPTH_BUFFER_DWordLength_start 0 +#define GEN7_3DSTATE_DEPTH_BUFFER_DWordLength_start 0 +#define GEN6_3DSTATE_DEPTH_BUFFER_DWordLength_start 0 +#define GEN5_3DSTATE_DEPTH_BUFFER_DWordLength_start 0 +#define GEN45_3DSTATE_DEPTH_BUFFER_DWordLength_start 0 +#define GEN4_3DSTATE_DEPTH_BUFFER_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DEPTH_BUFFER::Depth */ + + +#define GEN11_3DSTATE_DEPTH_BUFFER_Depth_bits 11 +#define GEN10_3DSTATE_DEPTH_BUFFER_Depth_bits 11 +#define GEN9_3DSTATE_DEPTH_BUFFER_Depth_bits 11 +#define GEN8_3DSTATE_DEPTH_BUFFER_Depth_bits 11 +#define GEN75_3DSTATE_DEPTH_BUFFER_Depth_bits 11 +#define GEN7_3DSTATE_DEPTH_BUFFER_Depth_bits 11 +#define GEN6_3DSTATE_DEPTH_BUFFER_Depth_bits 11 +#define GEN5_3DSTATE_DEPTH_BUFFER_Depth_bits 11 +#define GEN45_3DSTATE_DEPTH_BUFFER_Depth_bits 11 +#define GEN4_3DSTATE_DEPTH_BUFFER_Depth_bits 11 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_Depth_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 11; + } else { + return 11; + } + case 6: return 11; + case 5: return 11; + case 4: + if (devinfo->is_g4x) { + return 11; + } else { + return 11; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DEPTH_BUFFER_Depth_start 181 +#define GEN10_3DSTATE_DEPTH_BUFFER_Depth_start 181 +#define GEN9_3DSTATE_DEPTH_BUFFER_Depth_start 181 +#define GEN8_3DSTATE_DEPTH_BUFFER_Depth_start 181 +#define GEN75_3DSTATE_DEPTH_BUFFER_Depth_start 149 +#define GEN7_3DSTATE_DEPTH_BUFFER_Depth_start 149 +#define GEN6_3DSTATE_DEPTH_BUFFER_Depth_start 149 +#define GEN5_3DSTATE_DEPTH_BUFFER_Depth_start 149 +#define GEN45_3DSTATE_DEPTH_BUFFER_Depth_start 149 +#define GEN4_3DSTATE_DEPTH_BUFFER_Depth_start 149 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_Depth_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 181; + case 10: return 181; + case 9: return 181; + case 8: return 181; + case 7: + if (devinfo->is_haswell) { + return 149; + } else { + return 149; + } + case 6: return 149; + case 5: return 149; + case 4: + if (devinfo->is_g4x) { + return 149; + } else { + return 149; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DEPTH_BUFFER::Depth Buffer Coordinate Offset Disable */ + + +#define GEN45_3DSTATE_DEPTH_BUFFER_DepthBufferCoordinateOffsetDisable_bits 1 +#define GEN4_3DSTATE_DEPTH_BUFFER_DepthBufferCoordinateOffsetDisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_DepthBufferCoordinateOffsetDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN45_3DSTATE_DEPTH_BUFFER_DepthBufferCoordinateOffsetDisable_start 57 +#define GEN4_3DSTATE_DEPTH_BUFFER_DepthBufferCoordinateOffsetDisable_start 57 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_DepthBufferCoordinateOffsetDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 57; + } else { + return 57; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DEPTH_BUFFER::Depth Coordinate Offset X */ + + +#define GEN75_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetX_bits 16 +#define GEN7_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetX_bits 16 +#define GEN6_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetX_bits 16 +#define GEN5_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetX_bits 16 +#define GEN45_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetX_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetX_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetX_start 160 +#define GEN7_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetX_start 160 +#define GEN6_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetX_start 160 +#define GEN5_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetX_start 160 +#define GEN45_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetX_start 160 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetX_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 160; + } else { + return 160; + } + case 6: return 160; + case 5: return 160; + case 4: + if (devinfo->is_g4x) { + return 160; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DEPTH_BUFFER::Depth Coordinate Offset Y */ + + +#define GEN75_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetY_bits 16 +#define GEN7_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetY_bits 16 +#define GEN6_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetY_bits 16 +#define GEN5_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetY_bits 16 +#define GEN45_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetY_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetY_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetY_start 176 +#define GEN7_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetY_start 176 +#define GEN6_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetY_start 176 +#define GEN5_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetY_start 176 +#define GEN45_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetY_start 176 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_DepthCoordinateOffsetY_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 176; + } else { + return 176; + } + case 6: return 176; + case 5: return 176; + case 4: + if (devinfo->is_g4x) { + return 176; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DEPTH_BUFFER::Depth Write Enable */ + + +#define GEN11_3DSTATE_DEPTH_BUFFER_DepthWriteEnable_bits 1 +#define GEN10_3DSTATE_DEPTH_BUFFER_DepthWriteEnable_bits 1 +#define GEN9_3DSTATE_DEPTH_BUFFER_DepthWriteEnable_bits 1 +#define GEN8_3DSTATE_DEPTH_BUFFER_DepthWriteEnable_bits 1 +#define GEN75_3DSTATE_DEPTH_BUFFER_DepthWriteEnable_bits 1 +#define GEN7_3DSTATE_DEPTH_BUFFER_DepthWriteEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_DepthWriteEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DEPTH_BUFFER_DepthWriteEnable_start 60 +#define GEN10_3DSTATE_DEPTH_BUFFER_DepthWriteEnable_start 60 +#define GEN9_3DSTATE_DEPTH_BUFFER_DepthWriteEnable_start 60 +#define GEN8_3DSTATE_DEPTH_BUFFER_DepthWriteEnable_start 60 +#define GEN75_3DSTATE_DEPTH_BUFFER_DepthWriteEnable_start 60 +#define GEN7_3DSTATE_DEPTH_BUFFER_DepthWriteEnable_start 60 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_DepthWriteEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 60; + case 10: return 60; + case 9: return 60; + case 8: return 60; + case 7: + if (devinfo->is_haswell) { + return 60; + } else { + return 60; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DEPTH_BUFFER::Height */ + + +#define GEN11_3DSTATE_DEPTH_BUFFER_Height_bits 14 +#define GEN10_3DSTATE_DEPTH_BUFFER_Height_bits 14 +#define GEN9_3DSTATE_DEPTH_BUFFER_Height_bits 14 +#define GEN8_3DSTATE_DEPTH_BUFFER_Height_bits 14 +#define GEN75_3DSTATE_DEPTH_BUFFER_Height_bits 14 +#define GEN7_3DSTATE_DEPTH_BUFFER_Height_bits 14 +#define GEN6_3DSTATE_DEPTH_BUFFER_Height_bits 13 +#define GEN5_3DSTATE_DEPTH_BUFFER_Height_bits 13 +#define GEN45_3DSTATE_DEPTH_BUFFER_Height_bits 13 +#define GEN4_3DSTATE_DEPTH_BUFFER_Height_bits 13 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_Height_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 14; + case 10: return 14; + case 9: return 14; + case 8: return 14; + case 7: + if (devinfo->is_haswell) { + return 14; + } else { + return 14; + } + case 6: return 13; + case 5: return 13; + case 4: + if (devinfo->is_g4x) { + return 13; + } else { + return 13; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DEPTH_BUFFER_Height_start 146 +#define GEN10_3DSTATE_DEPTH_BUFFER_Height_start 146 +#define GEN9_3DSTATE_DEPTH_BUFFER_Height_start 146 +#define GEN8_3DSTATE_DEPTH_BUFFER_Height_start 146 +#define GEN75_3DSTATE_DEPTH_BUFFER_Height_start 114 +#define GEN7_3DSTATE_DEPTH_BUFFER_Height_start 114 +#define GEN6_3DSTATE_DEPTH_BUFFER_Height_start 115 +#define GEN5_3DSTATE_DEPTH_BUFFER_Height_start 115 +#define GEN45_3DSTATE_DEPTH_BUFFER_Height_start 115 +#define GEN4_3DSTATE_DEPTH_BUFFER_Height_start 115 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_Height_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 146; + case 10: return 146; + case 9: return 146; + case 8: return 146; + case 7: + if (devinfo->is_haswell) { + return 114; + } else { + return 114; + } + case 6: return 115; + case 5: return 115; + case 4: + if (devinfo->is_g4x) { + return 115; + } else { + return 115; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DEPTH_BUFFER::Hierarchical Depth Buffer Enable */ + + +#define GEN11_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_bits 1 +#define GEN10_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_bits 1 +#define GEN9_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_bits 1 +#define GEN8_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_bits 1 +#define GEN75_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_bits 1 +#define GEN7_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_bits 1 +#define GEN6_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_bits 1 +#define GEN5_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_start 54 +#define GEN10_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_start 54 +#define GEN9_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_start 54 +#define GEN8_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_start 54 +#define GEN75_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_start 54 +#define GEN7_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_start 54 +#define GEN6_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_start 54 +#define GEN5_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_start 54 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_HierarchicalDepthBufferEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 54; + case 10: return 54; + case 9: return 54; + case 8: return 54; + case 7: + if (devinfo->is_haswell) { + return 54; + } else { + return 54; + } + case 6: return 54; + case 5: return 54; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DEPTH_BUFFER::LOD */ + + +#define GEN11_3DSTATE_DEPTH_BUFFER_LOD_bits 4 +#define GEN10_3DSTATE_DEPTH_BUFFER_LOD_bits 4 +#define GEN9_3DSTATE_DEPTH_BUFFER_LOD_bits 4 +#define GEN8_3DSTATE_DEPTH_BUFFER_LOD_bits 4 +#define GEN75_3DSTATE_DEPTH_BUFFER_LOD_bits 4 +#define GEN7_3DSTATE_DEPTH_BUFFER_LOD_bits 4 +#define GEN6_3DSTATE_DEPTH_BUFFER_LOD_bits 4 +#define GEN5_3DSTATE_DEPTH_BUFFER_LOD_bits 4 +#define GEN45_3DSTATE_DEPTH_BUFFER_LOD_bits 4 +#define GEN4_3DSTATE_DEPTH_BUFFER_LOD_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_LOD_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 4; + case 4: + if (devinfo->is_g4x) { + return 4; + } else { + return 4; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DEPTH_BUFFER_LOD_start 128 +#define GEN10_3DSTATE_DEPTH_BUFFER_LOD_start 128 +#define GEN9_3DSTATE_DEPTH_BUFFER_LOD_start 128 +#define GEN8_3DSTATE_DEPTH_BUFFER_LOD_start 128 +#define GEN75_3DSTATE_DEPTH_BUFFER_LOD_start 96 +#define GEN7_3DSTATE_DEPTH_BUFFER_LOD_start 96 +#define GEN6_3DSTATE_DEPTH_BUFFER_LOD_start 98 +#define GEN5_3DSTATE_DEPTH_BUFFER_LOD_start 98 +#define GEN45_3DSTATE_DEPTH_BUFFER_LOD_start 98 +#define GEN4_3DSTATE_DEPTH_BUFFER_LOD_start 98 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_LOD_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 128; + case 10: return 128; + case 9: return 128; + case 8: return 128; + case 7: + if (devinfo->is_haswell) { + return 96; + } else { + return 96; + } + case 6: return 98; + case 5: return 98; + case 4: + if (devinfo->is_g4x) { + return 98; + } else { + return 98; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DEPTH_BUFFER::MIP Map Layout Mode */ + + +#define GEN6_3DSTATE_DEPTH_BUFFER_MIPMapLayoutMode_bits 1 +#define GEN5_3DSTATE_DEPTH_BUFFER_MIPMapLayoutMode_bits 1 +#define GEN45_3DSTATE_DEPTH_BUFFER_MIPMapLayoutMode_bits 1 +#define GEN4_3DSTATE_DEPTH_BUFFER_MIPMapLayoutMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_MIPMapLayoutMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_DEPTH_BUFFER_MIPMapLayoutMode_start 97 +#define GEN5_3DSTATE_DEPTH_BUFFER_MIPMapLayoutMode_start 97 +#define GEN45_3DSTATE_DEPTH_BUFFER_MIPMapLayoutMode_start 97 +#define GEN4_3DSTATE_DEPTH_BUFFER_MIPMapLayoutMode_start 97 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_MIPMapLayoutMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 97; + case 5: return 97; + case 4: + if (devinfo->is_g4x) { + return 97; + } else { + return 97; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DEPTH_BUFFER::MOCS */ + + +#define GEN11_3DSTATE_DEPTH_BUFFER_MOCS_bits 7 +#define GEN10_3DSTATE_DEPTH_BUFFER_MOCS_bits 7 +#define GEN9_3DSTATE_DEPTH_BUFFER_MOCS_bits 7 +#define GEN8_3DSTATE_DEPTH_BUFFER_MOCS_bits 7 +#define GEN75_3DSTATE_DEPTH_BUFFER_MOCS_bits 4 +#define GEN7_3DSTATE_DEPTH_BUFFER_MOCS_bits 4 +#define GEN6_3DSTATE_DEPTH_BUFFER_MOCS_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_MOCS_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 5; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DEPTH_BUFFER_MOCS_start 160 +#define GEN10_3DSTATE_DEPTH_BUFFER_MOCS_start 160 +#define GEN9_3DSTATE_DEPTH_BUFFER_MOCS_start 160 +#define GEN8_3DSTATE_DEPTH_BUFFER_MOCS_start 160 +#define GEN75_3DSTATE_DEPTH_BUFFER_MOCS_start 128 +#define GEN7_3DSTATE_DEPTH_BUFFER_MOCS_start 128 +#define GEN6_3DSTATE_DEPTH_BUFFER_MOCS_start 219 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_MOCS_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 160; + case 10: return 160; + case 9: return 160; + case 8: return 160; + case 7: + if (devinfo->is_haswell) { + return 128; + } else { + return 128; + } + case 6: return 219; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DEPTH_BUFFER::Minimum Array Element */ + + +#define GEN11_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_bits 11 +#define GEN10_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_bits 11 +#define GEN9_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_bits 11 +#define GEN8_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_bits 11 +#define GEN75_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_bits 11 +#define GEN7_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_bits 11 +#define GEN6_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_bits 11 +#define GEN5_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_bits 11 +#define GEN45_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_bits 11 +#define GEN4_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_bits 11 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 11; + } else { + return 11; + } + case 6: return 11; + case 5: return 11; + case 4: + if (devinfo->is_g4x) { + return 11; + } else { + return 11; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_start 170 +#define GEN10_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_start 170 +#define GEN9_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_start 170 +#define GEN8_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_start 170 +#define GEN75_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_start 138 +#define GEN7_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_start 138 +#define GEN6_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_start 138 +#define GEN5_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_start 138 +#define GEN45_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_start 138 +#define GEN4_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_start 138 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_MinimumArrayElement_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 170; + case 10: return 170; + case 9: return 170; + case 8: return 170; + case 7: + if (devinfo->is_haswell) { + return 138; + } else { + return 138; + } + case 6: return 138; + case 5: return 138; + case 4: + if (devinfo->is_g4x) { + return 138; + } else { + return 138; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DEPTH_BUFFER::Mip Tail Start LOD */ + + +#define GEN11_3DSTATE_DEPTH_BUFFER_MipTailStartLOD_bits 4 +#define GEN10_3DSTATE_DEPTH_BUFFER_MipTailStartLOD_bits 4 +#define GEN9_3DSTATE_DEPTH_BUFFER_MipTailStartLOD_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_MipTailStartLOD_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DEPTH_BUFFER_MipTailStartLOD_start 218 +#define GEN10_3DSTATE_DEPTH_BUFFER_MipTailStartLOD_start 218 +#define GEN9_3DSTATE_DEPTH_BUFFER_MipTailStartLOD_start 218 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_MipTailStartLOD_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 218; + case 10: return 218; + case 9: return 218; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DEPTH_BUFFER::Render Target View Extent */ + + +#define GEN11_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_bits 11 +#define GEN10_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_bits 11 +#define GEN9_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_bits 11 +#define GEN8_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_bits 11 +#define GEN75_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_bits 11 +#define GEN7_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_bits 11 +#define GEN6_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_bits 9 +#define GEN5_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_bits 9 +#define GEN45_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_bits 9 +#define GEN4_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 11; + } else { + return 11; + } + case 6: return 9; + case 5: return 9; + case 4: + if (devinfo->is_g4x) { + return 9; + } else { + return 9; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_start 245 +#define GEN10_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_start 245 +#define GEN9_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_start 245 +#define GEN8_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_start 245 +#define GEN75_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_start 213 +#define GEN7_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_start 213 +#define GEN6_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_start 129 +#define GEN5_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_start 129 +#define GEN45_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_start 129 +#define GEN4_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_start 129 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_RenderTargetViewExtent_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 245; + case 10: return 245; + case 9: return 245; + case 8: return 245; + case 7: + if (devinfo->is_haswell) { + return 213; + } else { + return 213; + } + case 6: return 129; + case 5: return 129; + case 4: + if (devinfo->is_g4x) { + return 129; + } else { + return 129; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DEPTH_BUFFER::Separate Stencil Buffer Enable */ + + +#define GEN6_3DSTATE_DEPTH_BUFFER_SeparateStencilBufferEnable_bits 1 +#define GEN5_3DSTATE_DEPTH_BUFFER_SeparateStencilBufferEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_SeparateStencilBufferEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_DEPTH_BUFFER_SeparateStencilBufferEnable_start 53 +#define GEN5_3DSTATE_DEPTH_BUFFER_SeparateStencilBufferEnable_start 53 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_SeparateStencilBufferEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 53; + case 5: return 53; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DEPTH_BUFFER::Software Tiled Rendering Mode */ + + +#define GEN6_3DSTATE_DEPTH_BUFFER_SoftwareTiledRenderingMode_bits 2 +#define GEN5_3DSTATE_DEPTH_BUFFER_SoftwareTiledRenderingMode_bits 2 +#define GEN45_3DSTATE_DEPTH_BUFFER_SoftwareTiledRenderingMode_bits 2 +#define GEN4_3DSTATE_DEPTH_BUFFER_SoftwareTiledRenderingMode_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_SoftwareTiledRenderingMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 2; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_DEPTH_BUFFER_SoftwareTiledRenderingMode_start 55 +#define GEN5_3DSTATE_DEPTH_BUFFER_SoftwareTiledRenderingMode_start 55 +#define GEN45_3DSTATE_DEPTH_BUFFER_SoftwareTiledRenderingMode_start 55 +#define GEN4_3DSTATE_DEPTH_BUFFER_SoftwareTiledRenderingMode_start 55 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_SoftwareTiledRenderingMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 55; + case 5: return 55; + case 4: + if (devinfo->is_g4x) { + return 55; + } else { + return 55; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DEPTH_BUFFER::Stencil Write Enable */ + + +#define GEN11_3DSTATE_DEPTH_BUFFER_StencilWriteEnable_bits 1 +#define GEN10_3DSTATE_DEPTH_BUFFER_StencilWriteEnable_bits 1 +#define GEN9_3DSTATE_DEPTH_BUFFER_StencilWriteEnable_bits 1 +#define GEN8_3DSTATE_DEPTH_BUFFER_StencilWriteEnable_bits 1 +#define GEN75_3DSTATE_DEPTH_BUFFER_StencilWriteEnable_bits 1 +#define GEN7_3DSTATE_DEPTH_BUFFER_StencilWriteEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_StencilWriteEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DEPTH_BUFFER_StencilWriteEnable_start 59 +#define GEN10_3DSTATE_DEPTH_BUFFER_StencilWriteEnable_start 59 +#define GEN9_3DSTATE_DEPTH_BUFFER_StencilWriteEnable_start 59 +#define GEN8_3DSTATE_DEPTH_BUFFER_StencilWriteEnable_start 59 +#define GEN75_3DSTATE_DEPTH_BUFFER_StencilWriteEnable_start 59 +#define GEN7_3DSTATE_DEPTH_BUFFER_StencilWriteEnable_start 59 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_StencilWriteEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 59; + case 10: return 59; + case 9: return 59; + case 8: return 59; + case 7: + if (devinfo->is_haswell) { + return 59; + } else { + return 59; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DEPTH_BUFFER::Surface Base Address */ + + +#define GEN11_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_bits 64 +#define GEN10_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_bits 64 +#define GEN9_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_bits 64 +#define GEN8_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_bits 64 +#define GEN75_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_bits 32 +#define GEN7_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_bits 32 +#define GEN6_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_bits 32 +#define GEN5_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_bits 32 +#define GEN45_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_bits 32 +#define GEN4_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start 64 +#define GEN10_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start 64 +#define GEN9_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start 64 +#define GEN8_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start 64 +#define GEN75_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start 64 +#define GEN7_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start 64 +#define GEN6_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start 64 +#define GEN5_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start 64 +#define GEN45_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start 64 +#define GEN4_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start 64 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_SurfaceBaseAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 64; + case 5: return 64; + case 4: + if (devinfo->is_g4x) { + return 64; + } else { + return 64; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DEPTH_BUFFER::Surface Format */ + + +#define GEN11_3DSTATE_DEPTH_BUFFER_SurfaceFormat_bits 3 +#define GEN10_3DSTATE_DEPTH_BUFFER_SurfaceFormat_bits 3 +#define GEN9_3DSTATE_DEPTH_BUFFER_SurfaceFormat_bits 3 +#define GEN8_3DSTATE_DEPTH_BUFFER_SurfaceFormat_bits 3 +#define GEN75_3DSTATE_DEPTH_BUFFER_SurfaceFormat_bits 3 +#define GEN7_3DSTATE_DEPTH_BUFFER_SurfaceFormat_bits 3 +#define GEN6_3DSTATE_DEPTH_BUFFER_SurfaceFormat_bits 3 +#define GEN5_3DSTATE_DEPTH_BUFFER_SurfaceFormat_bits 3 +#define GEN45_3DSTATE_DEPTH_BUFFER_SurfaceFormat_bits 3 +#define GEN4_3DSTATE_DEPTH_BUFFER_SurfaceFormat_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_SurfaceFormat_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DEPTH_BUFFER_SurfaceFormat_start 50 +#define GEN10_3DSTATE_DEPTH_BUFFER_SurfaceFormat_start 50 +#define GEN9_3DSTATE_DEPTH_BUFFER_SurfaceFormat_start 50 +#define GEN8_3DSTATE_DEPTH_BUFFER_SurfaceFormat_start 50 +#define GEN75_3DSTATE_DEPTH_BUFFER_SurfaceFormat_start 50 +#define GEN7_3DSTATE_DEPTH_BUFFER_SurfaceFormat_start 50 +#define GEN6_3DSTATE_DEPTH_BUFFER_SurfaceFormat_start 50 +#define GEN5_3DSTATE_DEPTH_BUFFER_SurfaceFormat_start 50 +#define GEN45_3DSTATE_DEPTH_BUFFER_SurfaceFormat_start 50 +#define GEN4_3DSTATE_DEPTH_BUFFER_SurfaceFormat_start 50 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_SurfaceFormat_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 50; + case 10: return 50; + case 9: return 50; + case 8: return 50; + case 7: + if (devinfo->is_haswell) { + return 50; + } else { + return 50; + } + case 6: return 50; + case 5: return 50; + case 4: + if (devinfo->is_g4x) { + return 50; + } else { + return 50; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DEPTH_BUFFER::Surface Pitch */ + + +#define GEN11_3DSTATE_DEPTH_BUFFER_SurfacePitch_bits 18 +#define GEN10_3DSTATE_DEPTH_BUFFER_SurfacePitch_bits 18 +#define GEN9_3DSTATE_DEPTH_BUFFER_SurfacePitch_bits 18 +#define GEN8_3DSTATE_DEPTH_BUFFER_SurfacePitch_bits 18 +#define GEN75_3DSTATE_DEPTH_BUFFER_SurfacePitch_bits 18 +#define GEN7_3DSTATE_DEPTH_BUFFER_SurfacePitch_bits 18 +#define GEN6_3DSTATE_DEPTH_BUFFER_SurfacePitch_bits 17 +#define GEN5_3DSTATE_DEPTH_BUFFER_SurfacePitch_bits 17 +#define GEN45_3DSTATE_DEPTH_BUFFER_SurfacePitch_bits 17 +#define GEN4_3DSTATE_DEPTH_BUFFER_SurfacePitch_bits 17 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_SurfacePitch_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 18; + case 10: return 18; + case 9: return 18; + case 8: return 18; + case 7: + if (devinfo->is_haswell) { + return 18; + } else { + return 18; + } + case 6: return 17; + case 5: return 17; + case 4: + if (devinfo->is_g4x) { + return 17; + } else { + return 17; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DEPTH_BUFFER_SurfacePitch_start 32 +#define GEN10_3DSTATE_DEPTH_BUFFER_SurfacePitch_start 32 +#define GEN9_3DSTATE_DEPTH_BUFFER_SurfacePitch_start 32 +#define GEN8_3DSTATE_DEPTH_BUFFER_SurfacePitch_start 32 +#define GEN75_3DSTATE_DEPTH_BUFFER_SurfacePitch_start 32 +#define GEN7_3DSTATE_DEPTH_BUFFER_SurfacePitch_start 32 +#define GEN6_3DSTATE_DEPTH_BUFFER_SurfacePitch_start 32 +#define GEN5_3DSTATE_DEPTH_BUFFER_SurfacePitch_start 32 +#define GEN45_3DSTATE_DEPTH_BUFFER_SurfacePitch_start 32 +#define GEN4_3DSTATE_DEPTH_BUFFER_SurfacePitch_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_SurfacePitch_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DEPTH_BUFFER::Surface QPitch */ + + +#define GEN11_3DSTATE_DEPTH_BUFFER_SurfaceQPitch_bits 15 +#define GEN10_3DSTATE_DEPTH_BUFFER_SurfaceQPitch_bits 15 +#define GEN9_3DSTATE_DEPTH_BUFFER_SurfaceQPitch_bits 15 +#define GEN8_3DSTATE_DEPTH_BUFFER_SurfaceQPitch_bits 15 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_SurfaceQPitch_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 15; + case 10: return 15; + case 9: return 15; + case 8: return 15; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DEPTH_BUFFER_SurfaceQPitch_start 224 +#define GEN10_3DSTATE_DEPTH_BUFFER_SurfaceQPitch_start 224 +#define GEN9_3DSTATE_DEPTH_BUFFER_SurfaceQPitch_start 224 +#define GEN8_3DSTATE_DEPTH_BUFFER_SurfaceQPitch_start 224 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_SurfaceQPitch_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 224; + case 10: return 224; + case 9: return 224; + case 8: return 224; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DEPTH_BUFFER::Surface Type */ + + +#define GEN11_3DSTATE_DEPTH_BUFFER_SurfaceType_bits 3 +#define GEN10_3DSTATE_DEPTH_BUFFER_SurfaceType_bits 3 +#define GEN9_3DSTATE_DEPTH_BUFFER_SurfaceType_bits 3 +#define GEN8_3DSTATE_DEPTH_BUFFER_SurfaceType_bits 3 +#define GEN75_3DSTATE_DEPTH_BUFFER_SurfaceType_bits 3 +#define GEN7_3DSTATE_DEPTH_BUFFER_SurfaceType_bits 3 +#define GEN6_3DSTATE_DEPTH_BUFFER_SurfaceType_bits 3 +#define GEN5_3DSTATE_DEPTH_BUFFER_SurfaceType_bits 3 +#define GEN45_3DSTATE_DEPTH_BUFFER_SurfaceType_bits 3 +#define GEN4_3DSTATE_DEPTH_BUFFER_SurfaceType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_SurfaceType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DEPTH_BUFFER_SurfaceType_start 61 +#define GEN10_3DSTATE_DEPTH_BUFFER_SurfaceType_start 61 +#define GEN9_3DSTATE_DEPTH_BUFFER_SurfaceType_start 61 +#define GEN8_3DSTATE_DEPTH_BUFFER_SurfaceType_start 61 +#define GEN75_3DSTATE_DEPTH_BUFFER_SurfaceType_start 61 +#define GEN7_3DSTATE_DEPTH_BUFFER_SurfaceType_start 61 +#define GEN6_3DSTATE_DEPTH_BUFFER_SurfaceType_start 61 +#define GEN5_3DSTATE_DEPTH_BUFFER_SurfaceType_start 61 +#define GEN45_3DSTATE_DEPTH_BUFFER_SurfaceType_start 61 +#define GEN4_3DSTATE_DEPTH_BUFFER_SurfaceType_start 61 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_SurfaceType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 61; + case 10: return 61; + case 9: return 61; + case 8: return 61; + case 7: + if (devinfo->is_haswell) { + return 61; + } else { + return 61; + } + case 6: return 61; + case 5: return 61; + case 4: + if (devinfo->is_g4x) { + return 61; + } else { + return 61; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DEPTH_BUFFER::Tile Walk */ + + +#define GEN6_3DSTATE_DEPTH_BUFFER_TileWalk_bits 1 +#define GEN5_3DSTATE_DEPTH_BUFFER_TileWalk_bits 1 +#define GEN45_3DSTATE_DEPTH_BUFFER_TileWalk_bits 1 +#define GEN4_3DSTATE_DEPTH_BUFFER_TileWalk_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_TileWalk_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_DEPTH_BUFFER_TileWalk_start 58 +#define GEN5_3DSTATE_DEPTH_BUFFER_TileWalk_start 58 +#define GEN45_3DSTATE_DEPTH_BUFFER_TileWalk_start 58 +#define GEN4_3DSTATE_DEPTH_BUFFER_TileWalk_start 58 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_TileWalk_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 58; + case 5: return 58; + case 4: + if (devinfo->is_g4x) { + return 58; + } else { + return 58; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DEPTH_BUFFER::Tiled Resource Mode */ + + +#define GEN11_3DSTATE_DEPTH_BUFFER_TiledResourceMode_bits 2 +#define GEN10_3DSTATE_DEPTH_BUFFER_TiledResourceMode_bits 2 +#define GEN9_3DSTATE_DEPTH_BUFFER_TiledResourceMode_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_TiledResourceMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DEPTH_BUFFER_TiledResourceMode_start 222 +#define GEN10_3DSTATE_DEPTH_BUFFER_TiledResourceMode_start 222 +#define GEN9_3DSTATE_DEPTH_BUFFER_TiledResourceMode_start 222 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_TiledResourceMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 222; + case 10: return 222; + case 9: return 222; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DEPTH_BUFFER::Tiled Surface */ + + +#define GEN6_3DSTATE_DEPTH_BUFFER_TiledSurface_bits 1 +#define GEN5_3DSTATE_DEPTH_BUFFER_TiledSurface_bits 1 +#define GEN45_3DSTATE_DEPTH_BUFFER_TiledSurface_bits 1 +#define GEN4_3DSTATE_DEPTH_BUFFER_TiledSurface_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_TiledSurface_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_DEPTH_BUFFER_TiledSurface_start 59 +#define GEN5_3DSTATE_DEPTH_BUFFER_TiledSurface_start 59 +#define GEN45_3DSTATE_DEPTH_BUFFER_TiledSurface_start 59 +#define GEN4_3DSTATE_DEPTH_BUFFER_TiledSurface_start 59 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_TiledSurface_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 59; + case 5: return 59; + case 4: + if (devinfo->is_g4x) { + return 59; + } else { + return 59; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DEPTH_BUFFER::Width */ + + +#define GEN11_3DSTATE_DEPTH_BUFFER_Width_bits 14 +#define GEN10_3DSTATE_DEPTH_BUFFER_Width_bits 14 +#define GEN9_3DSTATE_DEPTH_BUFFER_Width_bits 14 +#define GEN8_3DSTATE_DEPTH_BUFFER_Width_bits 14 +#define GEN75_3DSTATE_DEPTH_BUFFER_Width_bits 14 +#define GEN7_3DSTATE_DEPTH_BUFFER_Width_bits 14 +#define GEN6_3DSTATE_DEPTH_BUFFER_Width_bits 13 +#define GEN5_3DSTATE_DEPTH_BUFFER_Width_bits 13 +#define GEN45_3DSTATE_DEPTH_BUFFER_Width_bits 13 +#define GEN4_3DSTATE_DEPTH_BUFFER_Width_bits 13 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_Width_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 14; + case 10: return 14; + case 9: return 14; + case 8: return 14; + case 7: + if (devinfo->is_haswell) { + return 14; + } else { + return 14; + } + case 6: return 13; + case 5: return 13; + case 4: + if (devinfo->is_g4x) { + return 13; + } else { + return 13; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DEPTH_BUFFER_Width_start 132 +#define GEN10_3DSTATE_DEPTH_BUFFER_Width_start 132 +#define GEN9_3DSTATE_DEPTH_BUFFER_Width_start 132 +#define GEN8_3DSTATE_DEPTH_BUFFER_Width_start 132 +#define GEN75_3DSTATE_DEPTH_BUFFER_Width_start 100 +#define GEN7_3DSTATE_DEPTH_BUFFER_Width_start 100 +#define GEN6_3DSTATE_DEPTH_BUFFER_Width_start 102 +#define GEN5_3DSTATE_DEPTH_BUFFER_Width_start 102 +#define GEN45_3DSTATE_DEPTH_BUFFER_Width_start 102 +#define GEN4_3DSTATE_DEPTH_BUFFER_Width_start 102 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_BUFFER_Width_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 132; + case 10: return 132; + case 9: return 132; + case 8: return 132; + case 7: + if (devinfo->is_haswell) { + return 100; + } else { + return 100; + } + case 6: return 102; + case 5: return 102; + case 4: + if (devinfo->is_g4x) { + return 102; + } else { + return 102; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS */ + + +#define GEN75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_length 2 +#define GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_length 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS::3D Command Opcode */ + + +#define GEN75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS::3D Command Sub Opcode */ + + +#define GEN75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS::Command SubType */ + + +#define GEN75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_CommandSubType_bits 2 +#define GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_CommandSubType_start 27 +#define GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS::Command Type */ + + +#define GEN75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_CommandType_bits 3 +#define GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_CommandType_start 29 +#define GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS::DWord Length */ + + +#define GEN75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_DWordLength_bits 8 +#define GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_DWordLength_start 0 +#define GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DEPTH_STENCIL_STATE_POINTERS::Pointer to DEPTH_STENCIL_STATE */ + + +#define GEN75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_PointertoDEPTH_STENCIL_STATE_bits 26 +#define GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_PointertoDEPTH_STENCIL_STATE_bits 26 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_PointertoDEPTH_STENCIL_STATE_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 26; + } else { + return 26; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_PointertoDEPTH_STENCIL_STATE_start 38 +#define GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_PointertoDEPTH_STENCIL_STATE_start 38 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DEPTH_STENCIL_STATE_POINTERS_PointertoDEPTH_STENCIL_STATE_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 38; + } else { + return 38; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DRAWING_RECTANGLE */ + + +#define GEN11_3DSTATE_DRAWING_RECTANGLE_length 4 +#define GEN10_3DSTATE_DRAWING_RECTANGLE_length 4 +#define GEN9_3DSTATE_DRAWING_RECTANGLE_length 4 +#define GEN8_3DSTATE_DRAWING_RECTANGLE_length 4 +#define GEN75_3DSTATE_DRAWING_RECTANGLE_length 4 +#define GEN7_3DSTATE_DRAWING_RECTANGLE_length 4 +#define GEN6_3DSTATE_DRAWING_RECTANGLE_length 4 +#define GEN5_3DSTATE_DRAWING_RECTANGLE_length 4 +#define GEN45_3DSTATE_DRAWING_RECTANGLE_length 4 +#define GEN4_3DSTATE_DRAWING_RECTANGLE_length 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DRAWING_RECTANGLE_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 4; + case 4: + if (devinfo->is_g4x) { + return 4; + } else { + return 4; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DRAWING_RECTANGLE::3D Command Opcode */ + + +#define GEN11_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_bits 3 +#define GEN6_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_bits 3 +#define GEN5_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_bits 3 +#define GEN45_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_bits 3 +#define GEN4_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_start 24 +#define GEN6_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_start 24 +#define GEN5_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_start 24 +#define GEN45_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_start 24 +#define GEN4_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DRAWING_RECTANGLE_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 24; + case 4: + if (devinfo->is_g4x) { + return 24; + } else { + return 24; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DRAWING_RECTANGLE::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_bits 8 +#define GEN6_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_bits 8 +#define GEN5_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_bits 8 +#define GEN45_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_bits 8 +#define GEN4_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_start 16 +#define GEN6_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_start 16 +#define GEN5_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_start 16 +#define GEN45_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_start 16 +#define GEN4_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DRAWING_RECTANGLE_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DRAWING_RECTANGLE::Clipped Drawing Rectangle X Max */ + + +#define GEN11_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_bits 16 +#define GEN10_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_bits 16 +#define GEN9_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_bits 16 +#define GEN8_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_bits 16 +#define GEN75_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_bits 16 +#define GEN7_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_bits 16 +#define GEN6_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_bits 16 +#define GEN5_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_bits 16 +#define GEN45_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_bits 16 +#define GEN4_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_start 64 +#define GEN10_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_start 64 +#define GEN9_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_start 64 +#define GEN8_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_start 64 +#define GEN75_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_start 64 +#define GEN7_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_start 64 +#define GEN6_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_start 64 +#define GEN5_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_start 64 +#define GEN45_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_start 64 +#define GEN4_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_start 64 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMax_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 64; + case 5: return 64; + case 4: + if (devinfo->is_g4x) { + return 64; + } else { + return 64; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DRAWING_RECTANGLE::Clipped Drawing Rectangle X Min */ + + +#define GEN11_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_bits 16 +#define GEN10_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_bits 16 +#define GEN9_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_bits 16 +#define GEN8_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_bits 16 +#define GEN75_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_bits 16 +#define GEN7_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_bits 16 +#define GEN6_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_bits 16 +#define GEN5_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_bits 16 +#define GEN45_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_bits 16 +#define GEN4_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_start 32 +#define GEN10_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_start 32 +#define GEN9_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_start 32 +#define GEN8_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_start 32 +#define GEN75_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_start 32 +#define GEN7_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_start 32 +#define GEN6_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_start 32 +#define GEN5_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_start 32 +#define GEN45_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_start 32 +#define GEN4_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleXMin_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DRAWING_RECTANGLE::Clipped Drawing Rectangle Y Max */ + + +#define GEN11_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_bits 16 +#define GEN10_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_bits 16 +#define GEN9_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_bits 16 +#define GEN8_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_bits 16 +#define GEN75_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_bits 16 +#define GEN7_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_bits 16 +#define GEN6_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_bits 16 +#define GEN5_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_bits 16 +#define GEN45_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_bits 16 +#define GEN4_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_start 80 +#define GEN10_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_start 80 +#define GEN9_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_start 80 +#define GEN8_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_start 80 +#define GEN75_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_start 80 +#define GEN7_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_start 80 +#define GEN6_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_start 80 +#define GEN5_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_start 80 +#define GEN45_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_start 80 +#define GEN4_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_start 80 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMax_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 80; + case 10: return 80; + case 9: return 80; + case 8: return 80; + case 7: + if (devinfo->is_haswell) { + return 80; + } else { + return 80; + } + case 6: return 80; + case 5: return 80; + case 4: + if (devinfo->is_g4x) { + return 80; + } else { + return 80; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DRAWING_RECTANGLE::Clipped Drawing Rectangle Y Min */ + + +#define GEN11_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_bits 16 +#define GEN10_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_bits 16 +#define GEN9_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_bits 16 +#define GEN8_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_bits 16 +#define GEN75_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_bits 16 +#define GEN7_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_bits 16 +#define GEN6_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_bits 16 +#define GEN5_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_bits 16 +#define GEN45_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_bits 16 +#define GEN4_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_start 48 +#define GEN10_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_start 48 +#define GEN9_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_start 48 +#define GEN8_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_start 48 +#define GEN75_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_start 48 +#define GEN7_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_start 48 +#define GEN6_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_start 48 +#define GEN5_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_start 48 +#define GEN45_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_start 48 +#define GEN4_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_start 48 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DRAWING_RECTANGLE_ClippedDrawingRectangleYMin_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 48; + case 7: + if (devinfo->is_haswell) { + return 48; + } else { + return 48; + } + case 6: return 48; + case 5: return 48; + case 4: + if (devinfo->is_g4x) { + return 48; + } else { + return 48; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DRAWING_RECTANGLE::Command SubType */ + + +#define GEN11_3DSTATE_DRAWING_RECTANGLE_CommandSubType_bits 2 +#define GEN10_3DSTATE_DRAWING_RECTANGLE_CommandSubType_bits 2 +#define GEN9_3DSTATE_DRAWING_RECTANGLE_CommandSubType_bits 2 +#define GEN8_3DSTATE_DRAWING_RECTANGLE_CommandSubType_bits 2 +#define GEN75_3DSTATE_DRAWING_RECTANGLE_CommandSubType_bits 2 +#define GEN7_3DSTATE_DRAWING_RECTANGLE_CommandSubType_bits 2 +#define GEN6_3DSTATE_DRAWING_RECTANGLE_CommandSubType_bits 2 +#define GEN5_3DSTATE_DRAWING_RECTANGLE_CommandSubType_bits 2 +#define GEN45_3DSTATE_DRAWING_RECTANGLE_CommandSubType_bits 2 +#define GEN4_3DSTATE_DRAWING_RECTANGLE_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DRAWING_RECTANGLE_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DRAWING_RECTANGLE_CommandSubType_start 27 +#define GEN10_3DSTATE_DRAWING_RECTANGLE_CommandSubType_start 27 +#define GEN9_3DSTATE_DRAWING_RECTANGLE_CommandSubType_start 27 +#define GEN8_3DSTATE_DRAWING_RECTANGLE_CommandSubType_start 27 +#define GEN75_3DSTATE_DRAWING_RECTANGLE_CommandSubType_start 27 +#define GEN7_3DSTATE_DRAWING_RECTANGLE_CommandSubType_start 27 +#define GEN6_3DSTATE_DRAWING_RECTANGLE_CommandSubType_start 27 +#define GEN5_3DSTATE_DRAWING_RECTANGLE_CommandSubType_start 27 +#define GEN45_3DSTATE_DRAWING_RECTANGLE_CommandSubType_start 27 +#define GEN4_3DSTATE_DRAWING_RECTANGLE_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DRAWING_RECTANGLE_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DRAWING_RECTANGLE::Command Type */ + + +#define GEN11_3DSTATE_DRAWING_RECTANGLE_CommandType_bits 3 +#define GEN10_3DSTATE_DRAWING_RECTANGLE_CommandType_bits 3 +#define GEN9_3DSTATE_DRAWING_RECTANGLE_CommandType_bits 3 +#define GEN8_3DSTATE_DRAWING_RECTANGLE_CommandType_bits 3 +#define GEN75_3DSTATE_DRAWING_RECTANGLE_CommandType_bits 3 +#define GEN7_3DSTATE_DRAWING_RECTANGLE_CommandType_bits 3 +#define GEN6_3DSTATE_DRAWING_RECTANGLE_CommandType_bits 3 +#define GEN5_3DSTATE_DRAWING_RECTANGLE_CommandType_bits 3 +#define GEN45_3DSTATE_DRAWING_RECTANGLE_CommandType_bits 3 +#define GEN4_3DSTATE_DRAWING_RECTANGLE_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DRAWING_RECTANGLE_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DRAWING_RECTANGLE_CommandType_start 29 +#define GEN10_3DSTATE_DRAWING_RECTANGLE_CommandType_start 29 +#define GEN9_3DSTATE_DRAWING_RECTANGLE_CommandType_start 29 +#define GEN8_3DSTATE_DRAWING_RECTANGLE_CommandType_start 29 +#define GEN75_3DSTATE_DRAWING_RECTANGLE_CommandType_start 29 +#define GEN7_3DSTATE_DRAWING_RECTANGLE_CommandType_start 29 +#define GEN6_3DSTATE_DRAWING_RECTANGLE_CommandType_start 29 +#define GEN5_3DSTATE_DRAWING_RECTANGLE_CommandType_start 29 +#define GEN45_3DSTATE_DRAWING_RECTANGLE_CommandType_start 29 +#define GEN4_3DSTATE_DRAWING_RECTANGLE_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DRAWING_RECTANGLE_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 29; + case 4: + if (devinfo->is_g4x) { + return 29; + } else { + return 29; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DRAWING_RECTANGLE::Core Mode Select */ + + +#define GEN11_3DSTATE_DRAWING_RECTANGLE_CoreModeSelect_bits 2 +#define GEN10_3DSTATE_DRAWING_RECTANGLE_CoreModeSelect_bits 2 +#define GEN9_3DSTATE_DRAWING_RECTANGLE_CoreModeSelect_bits 2 +#define GEN8_3DSTATE_DRAWING_RECTANGLE_CoreModeSelect_bits 2 +#define GEN75_3DSTATE_DRAWING_RECTANGLE_CoreModeSelect_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DRAWING_RECTANGLE_CoreModeSelect_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DRAWING_RECTANGLE_CoreModeSelect_start 14 +#define GEN10_3DSTATE_DRAWING_RECTANGLE_CoreModeSelect_start 14 +#define GEN9_3DSTATE_DRAWING_RECTANGLE_CoreModeSelect_start 14 +#define GEN8_3DSTATE_DRAWING_RECTANGLE_CoreModeSelect_start 14 +#define GEN75_3DSTATE_DRAWING_RECTANGLE_CoreModeSelect_start 14 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DRAWING_RECTANGLE_CoreModeSelect_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 14; + case 10: return 14; + case 9: return 14; + case 8: return 14; + case 7: + if (devinfo->is_haswell) { + return 14; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DRAWING_RECTANGLE::DWord Length */ + + +#define GEN11_3DSTATE_DRAWING_RECTANGLE_DWordLength_bits 8 +#define GEN10_3DSTATE_DRAWING_RECTANGLE_DWordLength_bits 8 +#define GEN9_3DSTATE_DRAWING_RECTANGLE_DWordLength_bits 8 +#define GEN8_3DSTATE_DRAWING_RECTANGLE_DWordLength_bits 8 +#define GEN75_3DSTATE_DRAWING_RECTANGLE_DWordLength_bits 8 +#define GEN7_3DSTATE_DRAWING_RECTANGLE_DWordLength_bits 8 +#define GEN6_3DSTATE_DRAWING_RECTANGLE_DWordLength_bits 8 +#define GEN5_3DSTATE_DRAWING_RECTANGLE_DWordLength_bits 8 +#define GEN45_3DSTATE_DRAWING_RECTANGLE_DWordLength_bits 8 +#define GEN4_3DSTATE_DRAWING_RECTANGLE_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DRAWING_RECTANGLE_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DRAWING_RECTANGLE_DWordLength_start 0 +#define GEN10_3DSTATE_DRAWING_RECTANGLE_DWordLength_start 0 +#define GEN9_3DSTATE_DRAWING_RECTANGLE_DWordLength_start 0 +#define GEN8_3DSTATE_DRAWING_RECTANGLE_DWordLength_start 0 +#define GEN75_3DSTATE_DRAWING_RECTANGLE_DWordLength_start 0 +#define GEN7_3DSTATE_DRAWING_RECTANGLE_DWordLength_start 0 +#define GEN6_3DSTATE_DRAWING_RECTANGLE_DWordLength_start 0 +#define GEN5_3DSTATE_DRAWING_RECTANGLE_DWordLength_start 0 +#define GEN45_3DSTATE_DRAWING_RECTANGLE_DWordLength_start 0 +#define GEN4_3DSTATE_DRAWING_RECTANGLE_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DRAWING_RECTANGLE_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DRAWING_RECTANGLE::Drawing Rectangle Origin X */ + + +#define GEN11_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_bits 16 +#define GEN10_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_bits 16 +#define GEN9_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_bits 16 +#define GEN8_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_bits 16 +#define GEN75_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_bits 16 +#define GEN7_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_bits 16 +#define GEN6_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_bits 16 +#define GEN5_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_bits 16 +#define GEN45_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_bits 16 +#define GEN4_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_start 96 +#define GEN10_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_start 96 +#define GEN9_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_start 96 +#define GEN8_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_start 96 +#define GEN75_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_start 96 +#define GEN7_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_start 96 +#define GEN6_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_start 96 +#define GEN5_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_start 96 +#define GEN45_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_start 96 +#define GEN4_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_start 96 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginX_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 96; + case 10: return 96; + case 9: return 96; + case 8: return 96; + case 7: + if (devinfo->is_haswell) { + return 96; + } else { + return 96; + } + case 6: return 96; + case 5: return 96; + case 4: + if (devinfo->is_g4x) { + return 96; + } else { + return 96; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DRAWING_RECTANGLE::Drawing Rectangle Origin Y */ + + +#define GEN11_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_bits 16 +#define GEN10_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_bits 16 +#define GEN9_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_bits 16 +#define GEN8_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_bits 16 +#define GEN75_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_bits 16 +#define GEN7_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_bits 16 +#define GEN6_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_bits 16 +#define GEN5_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_bits 16 +#define GEN45_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_bits 16 +#define GEN4_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_start 112 +#define GEN10_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_start 112 +#define GEN9_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_start 112 +#define GEN8_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_start 112 +#define GEN75_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_start 112 +#define GEN7_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_start 112 +#define GEN6_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_start 112 +#define GEN5_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_start 112 +#define GEN45_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_start 112 +#define GEN4_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_start 112 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DRAWING_RECTANGLE_DrawingRectangleOriginY_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 112; + case 10: return 112; + case 9: return 112; + case 8: return 112; + case 7: + if (devinfo->is_haswell) { + return 112; + } else { + return 112; + } + case 6: return 112; + case 5: return 112; + case 4: + if (devinfo->is_g4x) { + return 112; + } else { + return 112; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DS */ + + +#define GEN11_3DSTATE_DS_length 11 +#define GEN10_3DSTATE_DS_length 11 +#define GEN9_3DSTATE_DS_length 11 +#define GEN8_3DSTATE_DS_length 9 +#define GEN75_3DSTATE_DS_length 6 +#define GEN7_3DSTATE_DS_length 6 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DS::3D Command Opcode */ + + +#define GEN11_3DSTATE_DS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_DS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_DS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_DS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_DS_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_DS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_DS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_DS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_DS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_DS_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_DS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_DS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_DS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_DS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_DS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_DS_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_DS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_DS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_DS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_DS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_DS_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_DS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DS::Accesses UAV */ + + +#define GEN11_3DSTATE_DS_AccessesUAV_bits 1 +#define GEN10_3DSTATE_DS_AccessesUAV_bits 1 +#define GEN9_3DSTATE_DS_AccessesUAV_bits 1 +#define GEN8_3DSTATE_DS_AccessesUAV_bits 1 +#define GEN75_3DSTATE_DS_AccessesUAV_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_AccessesUAV_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DS_AccessesUAV_start 110 +#define GEN10_3DSTATE_DS_AccessesUAV_start 110 +#define GEN9_3DSTATE_DS_AccessesUAV_start 110 +#define GEN8_3DSTATE_DS_AccessesUAV_start 110 +#define GEN75_3DSTATE_DS_AccessesUAV_start 78 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_AccessesUAV_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 110; + case 10: return 110; + case 9: return 110; + case 8: return 110; + case 7: + if (devinfo->is_haswell) { + return 78; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DS::Binding Table Entry Count */ + + +#define GEN11_3DSTATE_DS_BindingTableEntryCount_bits 8 +#define GEN10_3DSTATE_DS_BindingTableEntryCount_bits 8 +#define GEN9_3DSTATE_DS_BindingTableEntryCount_bits 8 +#define GEN8_3DSTATE_DS_BindingTableEntryCount_bits 8 +#define GEN75_3DSTATE_DS_BindingTableEntryCount_bits 8 +#define GEN7_3DSTATE_DS_BindingTableEntryCount_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_BindingTableEntryCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DS_BindingTableEntryCount_start 114 +#define GEN10_3DSTATE_DS_BindingTableEntryCount_start 114 +#define GEN9_3DSTATE_DS_BindingTableEntryCount_start 114 +#define GEN8_3DSTATE_DS_BindingTableEntryCount_start 114 +#define GEN75_3DSTATE_DS_BindingTableEntryCount_start 82 +#define GEN7_3DSTATE_DS_BindingTableEntryCount_start 82 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_BindingTableEntryCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 114; + case 10: return 114; + case 9: return 114; + case 8: return 114; + case 7: + if (devinfo->is_haswell) { + return 82; + } else { + return 82; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DS::Cache Disable */ + + +#define GEN11_3DSTATE_DS_CacheDisable_bits 1 +#define GEN10_3DSTATE_DS_CacheDisable_bits 1 +#define GEN9_3DSTATE_DS_CacheDisable_bits 1 +#define GEN8_3DSTATE_DS_CacheDisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_CacheDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DS_CacheDisable_start 225 +#define GEN10_3DSTATE_DS_CacheDisable_start 225 +#define GEN9_3DSTATE_DS_CacheDisable_start 225 +#define GEN8_3DSTATE_DS_CacheDisable_start 225 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_CacheDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 225; + case 10: return 225; + case 9: return 225; + case 8: return 225; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DS::Command SubType */ + + +#define GEN11_3DSTATE_DS_CommandSubType_bits 2 +#define GEN10_3DSTATE_DS_CommandSubType_bits 2 +#define GEN9_3DSTATE_DS_CommandSubType_bits 2 +#define GEN8_3DSTATE_DS_CommandSubType_bits 2 +#define GEN75_3DSTATE_DS_CommandSubType_bits 2 +#define GEN7_3DSTATE_DS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DS_CommandSubType_start 27 +#define GEN10_3DSTATE_DS_CommandSubType_start 27 +#define GEN9_3DSTATE_DS_CommandSubType_start 27 +#define GEN8_3DSTATE_DS_CommandSubType_start 27 +#define GEN75_3DSTATE_DS_CommandSubType_start 27 +#define GEN7_3DSTATE_DS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DS::Command Type */ + + +#define GEN11_3DSTATE_DS_CommandType_bits 3 +#define GEN10_3DSTATE_DS_CommandType_bits 3 +#define GEN9_3DSTATE_DS_CommandType_bits 3 +#define GEN8_3DSTATE_DS_CommandType_bits 3 +#define GEN75_3DSTATE_DS_CommandType_bits 3 +#define GEN7_3DSTATE_DS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DS_CommandType_start 29 +#define GEN10_3DSTATE_DS_CommandType_start 29 +#define GEN9_3DSTATE_DS_CommandType_start 29 +#define GEN8_3DSTATE_DS_CommandType_start 29 +#define GEN75_3DSTATE_DS_CommandType_start 29 +#define GEN7_3DSTATE_DS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DS::Compute W Coordinate Enable */ + + +#define GEN11_3DSTATE_DS_ComputeWCoordinateEnable_bits 1 +#define GEN10_3DSTATE_DS_ComputeWCoordinateEnable_bits 1 +#define GEN9_3DSTATE_DS_ComputeWCoordinateEnable_bits 1 +#define GEN8_3DSTATE_DS_ComputeWCoordinateEnable_bits 1 +#define GEN75_3DSTATE_DS_ComputeWCoordinateEnable_bits 1 +#define GEN7_3DSTATE_DS_ComputeWCoordinateEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_ComputeWCoordinateEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DS_ComputeWCoordinateEnable_start 226 +#define GEN10_3DSTATE_DS_ComputeWCoordinateEnable_start 226 +#define GEN9_3DSTATE_DS_ComputeWCoordinateEnable_start 226 +#define GEN8_3DSTATE_DS_ComputeWCoordinateEnable_start 226 +#define GEN75_3DSTATE_DS_ComputeWCoordinateEnable_start 162 +#define GEN7_3DSTATE_DS_ComputeWCoordinateEnable_start 162 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_ComputeWCoordinateEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 226; + case 10: return 226; + case 9: return 226; + case 8: return 226; + case 7: + if (devinfo->is_haswell) { + return 162; + } else { + return 162; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DS::DS Cache Disable */ + + +#define GEN75_3DSTATE_DS_DSCacheDisable_bits 1 +#define GEN7_3DSTATE_DS_DSCacheDisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_DSCacheDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_DS_DSCacheDisable_start 161 +#define GEN7_3DSTATE_DS_DSCacheDisable_start 161 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_DSCacheDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 161; + } else { + return 161; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DS::DUAL_PATCH Kernel Start Pointer */ + + +#define GEN11_3DSTATE_DS_DUAL_PATCHKernelStartPointer_bits 58 +#define GEN10_3DSTATE_DS_DUAL_PATCHKernelStartPointer_bits 58 +#define GEN9_3DSTATE_DS_DUAL_PATCHKernelStartPointer_bits 58 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_DUAL_PATCHKernelStartPointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 58; + case 10: return 58; + case 9: return 58; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DS_DUAL_PATCHKernelStartPointer_start 294 +#define GEN10_3DSTATE_DS_DUAL_PATCHKernelStartPointer_start 294 +#define GEN9_3DSTATE_DS_DUAL_PATCHKernelStartPointer_start 294 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_DUAL_PATCHKernelStartPointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 294; + case 10: return 294; + case 9: return 294; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DS::DWord Length */ + + +#define GEN11_3DSTATE_DS_DWordLength_bits 8 +#define GEN10_3DSTATE_DS_DWordLength_bits 8 +#define GEN9_3DSTATE_DS_DWordLength_bits 8 +#define GEN8_3DSTATE_DS_DWordLength_bits 8 +#define GEN75_3DSTATE_DS_DWordLength_bits 8 +#define GEN7_3DSTATE_DS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DS_DWordLength_start 0 +#define GEN10_3DSTATE_DS_DWordLength_start 0 +#define GEN9_3DSTATE_DS_DWordLength_start 0 +#define GEN8_3DSTATE_DS_DWordLength_start 0 +#define GEN75_3DSTATE_DS_DWordLength_start 0 +#define GEN7_3DSTATE_DS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DS::Dispatch GRF Start Register For URB Data */ + + +#define GEN11_3DSTATE_DS_DispatchGRFStartRegisterForURBData_bits 5 +#define GEN10_3DSTATE_DS_DispatchGRFStartRegisterForURBData_bits 5 +#define GEN9_3DSTATE_DS_DispatchGRFStartRegisterForURBData_bits 5 +#define GEN8_3DSTATE_DS_DispatchGRFStartRegisterForURBData_bits 5 +#define GEN75_3DSTATE_DS_DispatchGRFStartRegisterForURBData_bits 5 +#define GEN7_3DSTATE_DS_DispatchGRFStartRegisterForURBData_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_DispatchGRFStartRegisterForURBData_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 5; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DS_DispatchGRFStartRegisterForURBData_start 212 +#define GEN10_3DSTATE_DS_DispatchGRFStartRegisterForURBData_start 212 +#define GEN9_3DSTATE_DS_DispatchGRFStartRegisterForURBData_start 212 +#define GEN8_3DSTATE_DS_DispatchGRFStartRegisterForURBData_start 212 +#define GEN75_3DSTATE_DS_DispatchGRFStartRegisterForURBData_start 148 +#define GEN7_3DSTATE_DS_DispatchGRFStartRegisterForURBData_start 148 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_DispatchGRFStartRegisterForURBData_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 212; + case 10: return 212; + case 9: return 212; + case 8: return 212; + case 7: + if (devinfo->is_haswell) { + return 148; + } else { + return 148; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DS::Dispatch Mode */ + + +#define GEN11_3DSTATE_DS_DispatchMode_bits 2 +#define GEN10_3DSTATE_DS_DispatchMode_bits 2 +#define GEN9_3DSTATE_DS_DispatchMode_bits 2 +#define GEN8_3DSTATE_DS_DispatchMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_DispatchMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DS_DispatchMode_start 227 +#define GEN10_3DSTATE_DS_DispatchMode_start 227 +#define GEN9_3DSTATE_DS_DispatchMode_start 227 +#define GEN8_3DSTATE_DS_DispatchMode_start 227 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_DispatchMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 227; + case 10: return 227; + case 9: return 227; + case 8: return 227; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DS::Enable */ + + +#define GEN11_3DSTATE_DS_Enable_bits 1 +#define GEN10_3DSTATE_DS_Enable_bits 1 +#define GEN9_3DSTATE_DS_Enable_bits 1 +#define GEN8_3DSTATE_DS_Enable_bits 1 +#define GEN75_3DSTATE_DS_Enable_bits 1 +#define GEN7_3DSTATE_DS_Enable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_Enable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DS_Enable_start 224 +#define GEN10_3DSTATE_DS_Enable_start 224 +#define GEN9_3DSTATE_DS_Enable_start 224 +#define GEN8_3DSTATE_DS_Enable_start 224 +#define GEN75_3DSTATE_DS_Enable_start 160 +#define GEN7_3DSTATE_DS_Enable_start 160 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_Enable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 224; + case 10: return 224; + case 9: return 224; + case 8: return 224; + case 7: + if (devinfo->is_haswell) { + return 160; + } else { + return 160; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DS::Floating Point Mode */ + + +#define GEN11_3DSTATE_DS_FloatingPointMode_bits 1 +#define GEN10_3DSTATE_DS_FloatingPointMode_bits 1 +#define GEN9_3DSTATE_DS_FloatingPointMode_bits 1 +#define GEN8_3DSTATE_DS_FloatingPointMode_bits 1 +#define GEN75_3DSTATE_DS_FloatingPointMode_bits 1 +#define GEN7_3DSTATE_DS_FloatingPointMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_FloatingPointMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DS_FloatingPointMode_start 112 +#define GEN10_3DSTATE_DS_FloatingPointMode_start 112 +#define GEN9_3DSTATE_DS_FloatingPointMode_start 112 +#define GEN8_3DSTATE_DS_FloatingPointMode_start 112 +#define GEN75_3DSTATE_DS_FloatingPointMode_start 80 +#define GEN7_3DSTATE_DS_FloatingPointMode_start 80 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_FloatingPointMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 112; + case 10: return 112; + case 9: return 112; + case 8: return 112; + case 7: + if (devinfo->is_haswell) { + return 80; + } else { + return 80; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DS::Illegal Opcode Exception Enable */ + + +#define GEN11_3DSTATE_DS_IllegalOpcodeExceptionEnable_bits 1 +#define GEN10_3DSTATE_DS_IllegalOpcodeExceptionEnable_bits 1 +#define GEN9_3DSTATE_DS_IllegalOpcodeExceptionEnable_bits 1 +#define GEN8_3DSTATE_DS_IllegalOpcodeExceptionEnable_bits 1 +#define GEN75_3DSTATE_DS_IllegalOpcodeExceptionEnable_bits 1 +#define GEN7_3DSTATE_DS_IllegalOpcodeExceptionEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_IllegalOpcodeExceptionEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DS_IllegalOpcodeExceptionEnable_start 109 +#define GEN10_3DSTATE_DS_IllegalOpcodeExceptionEnable_start 109 +#define GEN9_3DSTATE_DS_IllegalOpcodeExceptionEnable_start 109 +#define GEN8_3DSTATE_DS_IllegalOpcodeExceptionEnable_start 109 +#define GEN75_3DSTATE_DS_IllegalOpcodeExceptionEnable_start 77 +#define GEN7_3DSTATE_DS_IllegalOpcodeExceptionEnable_start 77 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_IllegalOpcodeExceptionEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 109; + case 10: return 109; + case 9: return 109; + case 8: return 109; + case 7: + if (devinfo->is_haswell) { + return 77; + } else { + return 77; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DS::Kernel Start Pointer */ + + +#define GEN11_3DSTATE_DS_KernelStartPointer_bits 58 +#define GEN10_3DSTATE_DS_KernelStartPointer_bits 58 +#define GEN9_3DSTATE_DS_KernelStartPointer_bits 58 +#define GEN8_3DSTATE_DS_KernelStartPointer_bits 58 +#define GEN75_3DSTATE_DS_KernelStartPointer_bits 26 +#define GEN7_3DSTATE_DS_KernelStartPointer_bits 26 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_KernelStartPointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 58; + case 10: return 58; + case 9: return 58; + case 8: return 58; + case 7: + if (devinfo->is_haswell) { + return 26; + } else { + return 26; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DS_KernelStartPointer_start 38 +#define GEN10_3DSTATE_DS_KernelStartPointer_start 38 +#define GEN9_3DSTATE_DS_KernelStartPointer_start 38 +#define GEN8_3DSTATE_DS_KernelStartPointer_start 38 +#define GEN75_3DSTATE_DS_KernelStartPointer_start 38 +#define GEN7_3DSTATE_DS_KernelStartPointer_start 38 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_KernelStartPointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 38; + case 10: return 38; + case 9: return 38; + case 8: return 38; + case 7: + if (devinfo->is_haswell) { + return 38; + } else { + return 38; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DS::Maximum Number of Threads */ + + +#define GEN11_3DSTATE_DS_MaximumNumberofThreads_bits 10 +#define GEN10_3DSTATE_DS_MaximumNumberofThreads_bits 10 +#define GEN9_3DSTATE_DS_MaximumNumberofThreads_bits 9 +#define GEN8_3DSTATE_DS_MaximumNumberofThreads_bits 9 +#define GEN75_3DSTATE_DS_MaximumNumberofThreads_bits 9 +#define GEN7_3DSTATE_DS_MaximumNumberofThreads_bits 7 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_MaximumNumberofThreads_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 10; + case 10: return 10; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 7; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DS_MaximumNumberofThreads_start 245 +#define GEN10_3DSTATE_DS_MaximumNumberofThreads_start 245 +#define GEN9_3DSTATE_DS_MaximumNumberofThreads_start 245 +#define GEN8_3DSTATE_DS_MaximumNumberofThreads_start 245 +#define GEN75_3DSTATE_DS_MaximumNumberofThreads_start 181 +#define GEN7_3DSTATE_DS_MaximumNumberofThreads_start 185 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_MaximumNumberofThreads_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 245; + case 10: return 245; + case 9: return 245; + case 8: return 245; + case 7: + if (devinfo->is_haswell) { + return 181; + } else { + return 185; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DS::Patch URB Entry Read Length */ + + +#define GEN11_3DSTATE_DS_PatchURBEntryReadLength_bits 7 +#define GEN10_3DSTATE_DS_PatchURBEntryReadLength_bits 7 +#define GEN9_3DSTATE_DS_PatchURBEntryReadLength_bits 7 +#define GEN8_3DSTATE_DS_PatchURBEntryReadLength_bits 7 +#define GEN75_3DSTATE_DS_PatchURBEntryReadLength_bits 7 +#define GEN7_3DSTATE_DS_PatchURBEntryReadLength_bits 7 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_PatchURBEntryReadLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 7; + } else { + return 7; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DS_PatchURBEntryReadLength_start 203 +#define GEN10_3DSTATE_DS_PatchURBEntryReadLength_start 203 +#define GEN9_3DSTATE_DS_PatchURBEntryReadLength_start 203 +#define GEN8_3DSTATE_DS_PatchURBEntryReadLength_start 203 +#define GEN75_3DSTATE_DS_PatchURBEntryReadLength_start 139 +#define GEN7_3DSTATE_DS_PatchURBEntryReadLength_start 139 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_PatchURBEntryReadLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 203; + case 10: return 203; + case 9: return 203; + case 8: return 203; + case 7: + if (devinfo->is_haswell) { + return 139; + } else { + return 139; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DS::Patch URB Entry Read Offset */ + + +#define GEN11_3DSTATE_DS_PatchURBEntryReadOffset_bits 6 +#define GEN10_3DSTATE_DS_PatchURBEntryReadOffset_bits 6 +#define GEN9_3DSTATE_DS_PatchURBEntryReadOffset_bits 6 +#define GEN8_3DSTATE_DS_PatchURBEntryReadOffset_bits 6 +#define GEN75_3DSTATE_DS_PatchURBEntryReadOffset_bits 6 +#define GEN7_3DSTATE_DS_PatchURBEntryReadOffset_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_PatchURBEntryReadOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DS_PatchURBEntryReadOffset_start 196 +#define GEN10_3DSTATE_DS_PatchURBEntryReadOffset_start 196 +#define GEN9_3DSTATE_DS_PatchURBEntryReadOffset_start 196 +#define GEN8_3DSTATE_DS_PatchURBEntryReadOffset_start 196 +#define GEN75_3DSTATE_DS_PatchURBEntryReadOffset_start 132 +#define GEN7_3DSTATE_DS_PatchURBEntryReadOffset_start 132 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_PatchURBEntryReadOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 196; + case 10: return 196; + case 9: return 196; + case 8: return 196; + case 7: + if (devinfo->is_haswell) { + return 132; + } else { + return 132; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DS::Per-Thread Scratch Space */ + + +#define GEN11_3DSTATE_DS_PerThreadScratchSpace_bits 4 +#define GEN10_3DSTATE_DS_PerThreadScratchSpace_bits 4 +#define GEN9_3DSTATE_DS_PerThreadScratchSpace_bits 4 +#define GEN8_3DSTATE_DS_PerThreadScratchSpace_bits 4 +#define GEN75_3DSTATE_DS_PerThreadScratchSpace_bits 4 +#define GEN7_3DSTATE_DS_PerThreadScratchSpace_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_PerThreadScratchSpace_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DS_PerThreadScratchSpace_start 128 +#define GEN10_3DSTATE_DS_PerThreadScratchSpace_start 128 +#define GEN9_3DSTATE_DS_PerThreadScratchSpace_start 128 +#define GEN8_3DSTATE_DS_PerThreadScratchSpace_start 128 +#define GEN75_3DSTATE_DS_PerThreadScratchSpace_start 96 +#define GEN7_3DSTATE_DS_PerThreadScratchSpace_start 96 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_PerThreadScratchSpace_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 128; + case 10: return 128; + case 9: return 128; + case 8: return 128; + case 7: + if (devinfo->is_haswell) { + return 96; + } else { + return 96; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DS::Sampler Count */ + + +#define GEN11_3DSTATE_DS_SamplerCount_bits 3 +#define GEN10_3DSTATE_DS_SamplerCount_bits 3 +#define GEN9_3DSTATE_DS_SamplerCount_bits 3 +#define GEN8_3DSTATE_DS_SamplerCount_bits 3 +#define GEN75_3DSTATE_DS_SamplerCount_bits 3 +#define GEN7_3DSTATE_DS_SamplerCount_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_SamplerCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DS_SamplerCount_start 123 +#define GEN10_3DSTATE_DS_SamplerCount_start 123 +#define GEN9_3DSTATE_DS_SamplerCount_start 123 +#define GEN8_3DSTATE_DS_SamplerCount_start 123 +#define GEN75_3DSTATE_DS_SamplerCount_start 91 +#define GEN7_3DSTATE_DS_SamplerCount_start 91 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_SamplerCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 123; + case 10: return 123; + case 9: return 123; + case 8: return 123; + case 7: + if (devinfo->is_haswell) { + return 91; + } else { + return 91; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DS::Scratch Space Base Pointer */ + + +#define GEN11_3DSTATE_DS_ScratchSpaceBasePointer_bits 54 +#define GEN10_3DSTATE_DS_ScratchSpaceBasePointer_bits 54 +#define GEN9_3DSTATE_DS_ScratchSpaceBasePointer_bits 54 +#define GEN8_3DSTATE_DS_ScratchSpaceBasePointer_bits 54 +#define GEN75_3DSTATE_DS_ScratchSpaceBasePointer_bits 22 +#define GEN7_3DSTATE_DS_ScratchSpaceBasePointer_bits 22 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_ScratchSpaceBasePointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 54; + case 10: return 54; + case 9: return 54; + case 8: return 54; + case 7: + if (devinfo->is_haswell) { + return 22; + } else { + return 22; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DS_ScratchSpaceBasePointer_start 138 +#define GEN10_3DSTATE_DS_ScratchSpaceBasePointer_start 138 +#define GEN9_3DSTATE_DS_ScratchSpaceBasePointer_start 138 +#define GEN8_3DSTATE_DS_ScratchSpaceBasePointer_start 138 +#define GEN75_3DSTATE_DS_ScratchSpaceBasePointer_start 106 +#define GEN7_3DSTATE_DS_ScratchSpaceBasePointer_start 106 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_ScratchSpaceBasePointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 138; + case 10: return 138; + case 9: return 138; + case 8: return 138; + case 7: + if (devinfo->is_haswell) { + return 106; + } else { + return 106; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DS::Single Domain Point Dispatch */ + + +#define GEN8_3DSTATE_DS_SingleDomainPointDispatch_bits 1 +#define GEN75_3DSTATE_DS_SingleDomainPointDispatch_bits 1 +#define GEN7_3DSTATE_DS_SingleDomainPointDispatch_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_SingleDomainPointDispatch_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_3DSTATE_DS_SingleDomainPointDispatch_start 127 +#define GEN75_3DSTATE_DS_SingleDomainPointDispatch_start 95 +#define GEN7_3DSTATE_DS_SingleDomainPointDispatch_start 95 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_SingleDomainPointDispatch_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 127; + case 7: + if (devinfo->is_haswell) { + return 95; + } else { + return 95; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DS::Software Exception Enable */ + + +#define GEN11_3DSTATE_DS_SoftwareExceptionEnable_bits 1 +#define GEN10_3DSTATE_DS_SoftwareExceptionEnable_bits 1 +#define GEN9_3DSTATE_DS_SoftwareExceptionEnable_bits 1 +#define GEN8_3DSTATE_DS_SoftwareExceptionEnable_bits 1 +#define GEN75_3DSTATE_DS_SoftwareExceptionEnable_bits 1 +#define GEN7_3DSTATE_DS_SoftwareExceptionEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_SoftwareExceptionEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DS_SoftwareExceptionEnable_start 103 +#define GEN10_3DSTATE_DS_SoftwareExceptionEnable_start 103 +#define GEN9_3DSTATE_DS_SoftwareExceptionEnable_start 103 +#define GEN8_3DSTATE_DS_SoftwareExceptionEnable_start 103 +#define GEN75_3DSTATE_DS_SoftwareExceptionEnable_start 71 +#define GEN7_3DSTATE_DS_SoftwareExceptionEnable_start 71 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_SoftwareExceptionEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 103; + case 10: return 103; + case 9: return 103; + case 8: return 103; + case 7: + if (devinfo->is_haswell) { + return 71; + } else { + return 71; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DS::Statistics Enable */ + + +#define GEN11_3DSTATE_DS_StatisticsEnable_bits 1 +#define GEN10_3DSTATE_DS_StatisticsEnable_bits 1 +#define GEN9_3DSTATE_DS_StatisticsEnable_bits 1 +#define GEN8_3DSTATE_DS_StatisticsEnable_bits 1 +#define GEN75_3DSTATE_DS_StatisticsEnable_bits 1 +#define GEN7_3DSTATE_DS_StatisticsEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_StatisticsEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DS_StatisticsEnable_start 234 +#define GEN10_3DSTATE_DS_StatisticsEnable_start 234 +#define GEN9_3DSTATE_DS_StatisticsEnable_start 234 +#define GEN8_3DSTATE_DS_StatisticsEnable_start 234 +#define GEN75_3DSTATE_DS_StatisticsEnable_start 170 +#define GEN7_3DSTATE_DS_StatisticsEnable_start 170 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_StatisticsEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 234; + case 10: return 234; + case 9: return 234; + case 8: return 234; + case 7: + if (devinfo->is_haswell) { + return 170; + } else { + return 170; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DS::Thread Dispatch Priority */ + + +#define GEN11_3DSTATE_DS_ThreadDispatchPriority_bits 1 +#define GEN10_3DSTATE_DS_ThreadDispatchPriority_bits 1 +#define GEN9_3DSTATE_DS_ThreadDispatchPriority_bits 1 +#define GEN8_3DSTATE_DS_ThreadDispatchPriority_bits 1 +#define GEN75_3DSTATE_DS_ThreadDispatchPriority_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_ThreadDispatchPriority_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DS_ThreadDispatchPriority_start 113 +#define GEN10_3DSTATE_DS_ThreadDispatchPriority_start 113 +#define GEN9_3DSTATE_DS_ThreadDispatchPriority_start 113 +#define GEN8_3DSTATE_DS_ThreadDispatchPriority_start 113 +#define GEN75_3DSTATE_DS_ThreadDispatchPriority_start 81 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_ThreadDispatchPriority_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 113; + case 10: return 113; + case 9: return 113; + case 8: return 113; + case 7: + if (devinfo->is_haswell) { + return 81; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DS::User Clip Distance Clip Test Enable Bitmask */ + + +#define GEN11_3DSTATE_DS_UserClipDistanceClipTestEnableBitmask_bits 8 +#define GEN10_3DSTATE_DS_UserClipDistanceClipTestEnableBitmask_bits 8 +#define GEN9_3DSTATE_DS_UserClipDistanceClipTestEnableBitmask_bits 8 +#define GEN8_3DSTATE_DS_UserClipDistanceClipTestEnableBitmask_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_UserClipDistanceClipTestEnableBitmask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DS_UserClipDistanceClipTestEnableBitmask_start 264 +#define GEN10_3DSTATE_DS_UserClipDistanceClipTestEnableBitmask_start 264 +#define GEN9_3DSTATE_DS_UserClipDistanceClipTestEnableBitmask_start 264 +#define GEN8_3DSTATE_DS_UserClipDistanceClipTestEnableBitmask_start 264 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_UserClipDistanceClipTestEnableBitmask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 264; + case 10: return 264; + case 9: return 264; + case 8: return 264; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DS::User Clip Distance Cull Test Enable Bitmask */ + + +#define GEN11_3DSTATE_DS_UserClipDistanceCullTestEnableBitmask_bits 8 +#define GEN10_3DSTATE_DS_UserClipDistanceCullTestEnableBitmask_bits 8 +#define GEN9_3DSTATE_DS_UserClipDistanceCullTestEnableBitmask_bits 8 +#define GEN8_3DSTATE_DS_UserClipDistanceCullTestEnableBitmask_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_UserClipDistanceCullTestEnableBitmask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DS_UserClipDistanceCullTestEnableBitmask_start 256 +#define GEN10_3DSTATE_DS_UserClipDistanceCullTestEnableBitmask_start 256 +#define GEN9_3DSTATE_DS_UserClipDistanceCullTestEnableBitmask_start 256 +#define GEN8_3DSTATE_DS_UserClipDistanceCullTestEnableBitmask_start 256 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_UserClipDistanceCullTestEnableBitmask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 256; + case 10: return 256; + case 9: return 256; + case 8: return 256; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DS::Vector Mask Enable */ + + +#define GEN11_3DSTATE_DS_VectorMaskEnable_bits 1 +#define GEN10_3DSTATE_DS_VectorMaskEnable_bits 1 +#define GEN9_3DSTATE_DS_VectorMaskEnable_bits 1 +#define GEN8_3DSTATE_DS_VectorMaskEnable_bits 1 +#define GEN75_3DSTATE_DS_VectorMaskEnable_bits 1 +#define GEN7_3DSTATE_DS_VectorMaskEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_VectorMaskEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DS_VectorMaskEnable_start 126 +#define GEN10_3DSTATE_DS_VectorMaskEnable_start 126 +#define GEN9_3DSTATE_DS_VectorMaskEnable_start 126 +#define GEN8_3DSTATE_DS_VectorMaskEnable_start 126 +#define GEN75_3DSTATE_DS_VectorMaskEnable_start 94 +#define GEN7_3DSTATE_DS_VectorMaskEnable_start 94 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_VectorMaskEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 126; + case 10: return 126; + case 9: return 126; + case 8: return 126; + case 7: + if (devinfo->is_haswell) { + return 94; + } else { + return 94; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DS::Vertex URB Entry Output Length */ + + +#define GEN11_3DSTATE_DS_VertexURBEntryOutputLength_bits 5 +#define GEN10_3DSTATE_DS_VertexURBEntryOutputLength_bits 5 +#define GEN9_3DSTATE_DS_VertexURBEntryOutputLength_bits 5 +#define GEN8_3DSTATE_DS_VertexURBEntryOutputLength_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_VertexURBEntryOutputLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DS_VertexURBEntryOutputLength_start 272 +#define GEN10_3DSTATE_DS_VertexURBEntryOutputLength_start 272 +#define GEN9_3DSTATE_DS_VertexURBEntryOutputLength_start 272 +#define GEN8_3DSTATE_DS_VertexURBEntryOutputLength_start 272 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_VertexURBEntryOutputLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 272; + case 10: return 272; + case 9: return 272; + case 8: return 272; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_DS::Vertex URB Entry Output Read Offset */ + + +#define GEN11_3DSTATE_DS_VertexURBEntryOutputReadOffset_bits 6 +#define GEN10_3DSTATE_DS_VertexURBEntryOutputReadOffset_bits 6 +#define GEN9_3DSTATE_DS_VertexURBEntryOutputReadOffset_bits 6 +#define GEN8_3DSTATE_DS_VertexURBEntryOutputReadOffset_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_VertexURBEntryOutputReadOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_DS_VertexURBEntryOutputReadOffset_start 277 +#define GEN10_3DSTATE_DS_VertexURBEntryOutputReadOffset_start 277 +#define GEN9_3DSTATE_DS_VertexURBEntryOutputReadOffset_start 277 +#define GEN8_3DSTATE_DS_VertexURBEntryOutputReadOffset_start 277 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_DS_VertexURBEntryOutputReadOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 277; + case 10: return 277; + case 9: return 277; + case 8: return 277; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_DS */ + + + + + +/* 3DSTATE_GATHER_CONSTANT_DS::3D Command Opcode */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_DS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_GATHER_CONSTANT_DS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_GATHER_CONSTANT_DS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_GATHER_CONSTANT_DS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_GATHER_CONSTANT_DS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_DS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_DS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_GATHER_CONSTANT_DS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_GATHER_CONSTANT_DS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_GATHER_CONSTANT_DS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_GATHER_CONSTANT_DS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_DS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_DS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_DS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_GATHER_CONSTANT_DS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_GATHER_CONSTANT_DS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_GATHER_CONSTANT_DS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_GATHER_CONSTANT_DS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_DS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_DS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_GATHER_CONSTANT_DS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_GATHER_CONSTANT_DS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_GATHER_CONSTANT_DS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_GATHER_CONSTANT_DS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_DS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_DS::Command SubType */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_DS_CommandSubType_bits 2 +#define GEN10_3DSTATE_GATHER_CONSTANT_DS_CommandSubType_bits 2 +#define GEN9_3DSTATE_GATHER_CONSTANT_DS_CommandSubType_bits 2 +#define GEN8_3DSTATE_GATHER_CONSTANT_DS_CommandSubType_bits 2 +#define GEN75_3DSTATE_GATHER_CONSTANT_DS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_DS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_DS_CommandSubType_start 27 +#define GEN10_3DSTATE_GATHER_CONSTANT_DS_CommandSubType_start 27 +#define GEN9_3DSTATE_GATHER_CONSTANT_DS_CommandSubType_start 27 +#define GEN8_3DSTATE_GATHER_CONSTANT_DS_CommandSubType_start 27 +#define GEN75_3DSTATE_GATHER_CONSTANT_DS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_DS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_DS::Command Type */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_DS_CommandType_bits 3 +#define GEN10_3DSTATE_GATHER_CONSTANT_DS_CommandType_bits 3 +#define GEN9_3DSTATE_GATHER_CONSTANT_DS_CommandType_bits 3 +#define GEN8_3DSTATE_GATHER_CONSTANT_DS_CommandType_bits 3 +#define GEN75_3DSTATE_GATHER_CONSTANT_DS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_DS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_DS_CommandType_start 29 +#define GEN10_3DSTATE_GATHER_CONSTANT_DS_CommandType_start 29 +#define GEN9_3DSTATE_GATHER_CONSTANT_DS_CommandType_start 29 +#define GEN8_3DSTATE_GATHER_CONSTANT_DS_CommandType_start 29 +#define GEN75_3DSTATE_GATHER_CONSTANT_DS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_DS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_DS::Constant Buffer Binding Table Block */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferBindingTableBlock_bits 4 +#define GEN10_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferBindingTableBlock_bits 4 +#define GEN9_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferBindingTableBlock_bits 4 +#define GEN8_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferBindingTableBlock_bits 4 +#define GEN75_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferBindingTableBlock_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferBindingTableBlock_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferBindingTableBlock_start 44 +#define GEN10_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferBindingTableBlock_start 44 +#define GEN9_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferBindingTableBlock_start 44 +#define GEN8_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferBindingTableBlock_start 44 +#define GEN75_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferBindingTableBlock_start 44 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferBindingTableBlock_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 44; + case 10: return 44; + case 9: return 44; + case 8: return 44; + case 7: + if (devinfo->is_haswell) { + return 44; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_DS::Constant Buffer Dx9 Generate Stall */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferDx9GenerateStall_bits 1 +#define GEN10_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferDx9GenerateStall_bits 1 +#define GEN9_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferDx9GenerateStall_bits 1 +#define GEN8_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferDx9GenerateStall_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferDx9GenerateStall_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferDx9GenerateStall_start 69 +#define GEN10_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferDx9GenerateStall_start 69 +#define GEN9_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferDx9GenerateStall_start 69 +#define GEN8_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferDx9GenerateStall_start 69 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferDx9GenerateStall_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 69; + case 10: return 69; + case 9: return 69; + case 8: return 69; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_DS::Constant Buffer Valid */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferValid_bits 16 +#define GEN10_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferValid_bits 16 +#define GEN9_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferValid_bits 16 +#define GEN8_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferValid_bits 16 +#define GEN75_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferValid_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferValid_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferValid_start 48 +#define GEN10_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferValid_start 48 +#define GEN9_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferValid_start 48 +#define GEN8_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferValid_start 48 +#define GEN75_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferValid_start 48 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_DS_ConstantBufferValid_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 48; + case 7: + if (devinfo->is_haswell) { + return 48; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_DS::DWord Length */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_DS_DWordLength_bits 8 +#define GEN10_3DSTATE_GATHER_CONSTANT_DS_DWordLength_bits 8 +#define GEN9_3DSTATE_GATHER_CONSTANT_DS_DWordLength_bits 8 +#define GEN8_3DSTATE_GATHER_CONSTANT_DS_DWordLength_bits 8 +#define GEN75_3DSTATE_GATHER_CONSTANT_DS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_DS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_DS_DWordLength_start 0 +#define GEN10_3DSTATE_GATHER_CONSTANT_DS_DWordLength_start 0 +#define GEN9_3DSTATE_GATHER_CONSTANT_DS_DWordLength_start 0 +#define GEN8_3DSTATE_GATHER_CONSTANT_DS_DWordLength_start 0 +#define GEN75_3DSTATE_GATHER_CONSTANT_DS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_DS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_DS::Entry_0 */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_DS_Entry_0_bits 16 +#define GEN10_3DSTATE_GATHER_CONSTANT_DS_Entry_0_bits 16 +#define GEN9_3DSTATE_GATHER_CONSTANT_DS_Entry_0_bits 16 +#define GEN8_3DSTATE_GATHER_CONSTANT_DS_Entry_0_bits 16 +#define GEN75_3DSTATE_GATHER_CONSTANT_DS_Entry_0_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_DS_Entry_0_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_DS_Entry_0_start 0 +#define GEN10_3DSTATE_GATHER_CONSTANT_DS_Entry_0_start 0 +#define GEN9_3DSTATE_GATHER_CONSTANT_DS_Entry_0_start 0 +#define GEN8_3DSTATE_GATHER_CONSTANT_DS_Entry_0_start 0 +#define GEN75_3DSTATE_GATHER_CONSTANT_DS_Entry_0_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_DS_Entry_0_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_DS::Entry_1 */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_DS_Entry_1_bits 16 +#define GEN10_3DSTATE_GATHER_CONSTANT_DS_Entry_1_bits 16 +#define GEN9_3DSTATE_GATHER_CONSTANT_DS_Entry_1_bits 16 +#define GEN8_3DSTATE_GATHER_CONSTANT_DS_Entry_1_bits 16 +#define GEN75_3DSTATE_GATHER_CONSTANT_DS_Entry_1_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_DS_Entry_1_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_DS_Entry_1_start 16 +#define GEN10_3DSTATE_GATHER_CONSTANT_DS_Entry_1_start 16 +#define GEN9_3DSTATE_GATHER_CONSTANT_DS_Entry_1_start 16 +#define GEN8_3DSTATE_GATHER_CONSTANT_DS_Entry_1_start 16 +#define GEN75_3DSTATE_GATHER_CONSTANT_DS_Entry_1_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_DS_Entry_1_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_DS::Gather Buffer Offset */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_DS_GatherBufferOffset_bits 17 +#define GEN10_3DSTATE_GATHER_CONSTANT_DS_GatherBufferOffset_bits 17 +#define GEN9_3DSTATE_GATHER_CONSTANT_DS_GatherBufferOffset_bits 17 +#define GEN8_3DSTATE_GATHER_CONSTANT_DS_GatherBufferOffset_bits 17 +#define GEN75_3DSTATE_GATHER_CONSTANT_DS_GatherBufferOffset_bits 17 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_DS_GatherBufferOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 17; + case 10: return 17; + case 9: return 17; + case 8: return 17; + case 7: + if (devinfo->is_haswell) { + return 17; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_DS_GatherBufferOffset_start 70 +#define GEN10_3DSTATE_GATHER_CONSTANT_DS_GatherBufferOffset_start 70 +#define GEN9_3DSTATE_GATHER_CONSTANT_DS_GatherBufferOffset_start 70 +#define GEN8_3DSTATE_GATHER_CONSTANT_DS_GatherBufferOffset_start 70 +#define GEN75_3DSTATE_GATHER_CONSTANT_DS_GatherBufferOffset_start 70 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_DS_GatherBufferOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 70; + case 10: return 70; + case 9: return 70; + case 8: return 70; + case 7: + if (devinfo->is_haswell) { + return 70; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_DS::On-Die Table */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_DS_OnDieTable_bits 1 +#define GEN10_3DSTATE_GATHER_CONSTANT_DS_OnDieTable_bits 1 +#define GEN9_3DSTATE_GATHER_CONSTANT_DS_OnDieTable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_DS_OnDieTable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_DS_OnDieTable_start 67 +#define GEN10_3DSTATE_GATHER_CONSTANT_DS_OnDieTable_start 67 +#define GEN9_3DSTATE_GATHER_CONSTANT_DS_OnDieTable_start 67 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_DS_OnDieTable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 67; + case 10: return 67; + case 9: return 67; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_DS::Update Gather Table Only */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_DS_UpdateGatherTableOnly_bits 1 +#define GEN10_3DSTATE_GATHER_CONSTANT_DS_UpdateGatherTableOnly_bits 1 +#define GEN9_3DSTATE_GATHER_CONSTANT_DS_UpdateGatherTableOnly_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_DS_UpdateGatherTableOnly_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_DS_UpdateGatherTableOnly_start 33 +#define GEN10_3DSTATE_GATHER_CONSTANT_DS_UpdateGatherTableOnly_start 33 +#define GEN9_3DSTATE_GATHER_CONSTANT_DS_UpdateGatherTableOnly_start 33 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_DS_UpdateGatherTableOnly_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 33; + case 10: return 33; + case 9: return 33; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_GS */ + + + + + +/* 3DSTATE_GATHER_CONSTANT_GS::3D Command Opcode */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_GS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_GATHER_CONSTANT_GS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_GATHER_CONSTANT_GS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_GATHER_CONSTANT_GS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_GATHER_CONSTANT_GS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_GS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_GS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_GATHER_CONSTANT_GS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_GATHER_CONSTANT_GS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_GATHER_CONSTANT_GS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_GATHER_CONSTANT_GS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_GS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_GS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_GS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_GATHER_CONSTANT_GS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_GATHER_CONSTANT_GS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_GATHER_CONSTANT_GS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_GATHER_CONSTANT_GS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_GS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_GS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_GATHER_CONSTANT_GS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_GATHER_CONSTANT_GS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_GATHER_CONSTANT_GS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_GATHER_CONSTANT_GS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_GS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_GS::Command SubType */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_GS_CommandSubType_bits 2 +#define GEN10_3DSTATE_GATHER_CONSTANT_GS_CommandSubType_bits 2 +#define GEN9_3DSTATE_GATHER_CONSTANT_GS_CommandSubType_bits 2 +#define GEN8_3DSTATE_GATHER_CONSTANT_GS_CommandSubType_bits 2 +#define GEN75_3DSTATE_GATHER_CONSTANT_GS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_GS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_GS_CommandSubType_start 27 +#define GEN10_3DSTATE_GATHER_CONSTANT_GS_CommandSubType_start 27 +#define GEN9_3DSTATE_GATHER_CONSTANT_GS_CommandSubType_start 27 +#define GEN8_3DSTATE_GATHER_CONSTANT_GS_CommandSubType_start 27 +#define GEN75_3DSTATE_GATHER_CONSTANT_GS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_GS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_GS::Command Type */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_GS_CommandType_bits 3 +#define GEN10_3DSTATE_GATHER_CONSTANT_GS_CommandType_bits 3 +#define GEN9_3DSTATE_GATHER_CONSTANT_GS_CommandType_bits 3 +#define GEN8_3DSTATE_GATHER_CONSTANT_GS_CommandType_bits 3 +#define GEN75_3DSTATE_GATHER_CONSTANT_GS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_GS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_GS_CommandType_start 29 +#define GEN10_3DSTATE_GATHER_CONSTANT_GS_CommandType_start 29 +#define GEN9_3DSTATE_GATHER_CONSTANT_GS_CommandType_start 29 +#define GEN8_3DSTATE_GATHER_CONSTANT_GS_CommandType_start 29 +#define GEN75_3DSTATE_GATHER_CONSTANT_GS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_GS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_GS::Constant Buffer Binding Table Block */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferBindingTableBlock_bits 4 +#define GEN10_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferBindingTableBlock_bits 4 +#define GEN9_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferBindingTableBlock_bits 4 +#define GEN8_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferBindingTableBlock_bits 4 +#define GEN75_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferBindingTableBlock_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferBindingTableBlock_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferBindingTableBlock_start 44 +#define GEN10_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferBindingTableBlock_start 44 +#define GEN9_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferBindingTableBlock_start 44 +#define GEN8_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferBindingTableBlock_start 44 +#define GEN75_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferBindingTableBlock_start 44 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferBindingTableBlock_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 44; + case 10: return 44; + case 9: return 44; + case 8: return 44; + case 7: + if (devinfo->is_haswell) { + return 44; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_GS::Constant Buffer Dx9 Generate Stall */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferDx9GenerateStall_bits 1 +#define GEN10_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferDx9GenerateStall_bits 1 +#define GEN9_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferDx9GenerateStall_bits 1 +#define GEN8_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferDx9GenerateStall_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferDx9GenerateStall_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferDx9GenerateStall_start 69 +#define GEN10_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferDx9GenerateStall_start 69 +#define GEN9_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferDx9GenerateStall_start 69 +#define GEN8_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferDx9GenerateStall_start 69 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferDx9GenerateStall_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 69; + case 10: return 69; + case 9: return 69; + case 8: return 69; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_GS::Constant Buffer Valid */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferValid_bits 16 +#define GEN10_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferValid_bits 16 +#define GEN9_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferValid_bits 16 +#define GEN8_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferValid_bits 16 +#define GEN75_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferValid_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferValid_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferValid_start 48 +#define GEN10_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferValid_start 48 +#define GEN9_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferValid_start 48 +#define GEN8_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferValid_start 48 +#define GEN75_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferValid_start 48 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_GS_ConstantBufferValid_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 48; + case 7: + if (devinfo->is_haswell) { + return 48; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_GS::DWord Length */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_GS_DWordLength_bits 8 +#define GEN10_3DSTATE_GATHER_CONSTANT_GS_DWordLength_bits 8 +#define GEN9_3DSTATE_GATHER_CONSTANT_GS_DWordLength_bits 8 +#define GEN8_3DSTATE_GATHER_CONSTANT_GS_DWordLength_bits 8 +#define GEN75_3DSTATE_GATHER_CONSTANT_GS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_GS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_GS_DWordLength_start 0 +#define GEN10_3DSTATE_GATHER_CONSTANT_GS_DWordLength_start 0 +#define GEN9_3DSTATE_GATHER_CONSTANT_GS_DWordLength_start 0 +#define GEN8_3DSTATE_GATHER_CONSTANT_GS_DWordLength_start 0 +#define GEN75_3DSTATE_GATHER_CONSTANT_GS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_GS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_GS::Entry_0 */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_GS_Entry_0_bits 16 +#define GEN10_3DSTATE_GATHER_CONSTANT_GS_Entry_0_bits 16 +#define GEN9_3DSTATE_GATHER_CONSTANT_GS_Entry_0_bits 16 +#define GEN8_3DSTATE_GATHER_CONSTANT_GS_Entry_0_bits 16 +#define GEN75_3DSTATE_GATHER_CONSTANT_GS_Entry_0_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_GS_Entry_0_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_GS_Entry_0_start 0 +#define GEN10_3DSTATE_GATHER_CONSTANT_GS_Entry_0_start 0 +#define GEN9_3DSTATE_GATHER_CONSTANT_GS_Entry_0_start 0 +#define GEN8_3DSTATE_GATHER_CONSTANT_GS_Entry_0_start 0 +#define GEN75_3DSTATE_GATHER_CONSTANT_GS_Entry_0_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_GS_Entry_0_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_GS::Entry_1 */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_GS_Entry_1_bits 16 +#define GEN10_3DSTATE_GATHER_CONSTANT_GS_Entry_1_bits 16 +#define GEN9_3DSTATE_GATHER_CONSTANT_GS_Entry_1_bits 16 +#define GEN8_3DSTATE_GATHER_CONSTANT_GS_Entry_1_bits 16 +#define GEN75_3DSTATE_GATHER_CONSTANT_GS_Entry_1_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_GS_Entry_1_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_GS_Entry_1_start 16 +#define GEN10_3DSTATE_GATHER_CONSTANT_GS_Entry_1_start 16 +#define GEN9_3DSTATE_GATHER_CONSTANT_GS_Entry_1_start 16 +#define GEN8_3DSTATE_GATHER_CONSTANT_GS_Entry_1_start 16 +#define GEN75_3DSTATE_GATHER_CONSTANT_GS_Entry_1_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_GS_Entry_1_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_GS::Gather Buffer Offset */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_GS_GatherBufferOffset_bits 17 +#define GEN10_3DSTATE_GATHER_CONSTANT_GS_GatherBufferOffset_bits 17 +#define GEN9_3DSTATE_GATHER_CONSTANT_GS_GatherBufferOffset_bits 17 +#define GEN8_3DSTATE_GATHER_CONSTANT_GS_GatherBufferOffset_bits 17 +#define GEN75_3DSTATE_GATHER_CONSTANT_GS_GatherBufferOffset_bits 17 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_GS_GatherBufferOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 17; + case 10: return 17; + case 9: return 17; + case 8: return 17; + case 7: + if (devinfo->is_haswell) { + return 17; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_GS_GatherBufferOffset_start 70 +#define GEN10_3DSTATE_GATHER_CONSTANT_GS_GatherBufferOffset_start 70 +#define GEN9_3DSTATE_GATHER_CONSTANT_GS_GatherBufferOffset_start 70 +#define GEN8_3DSTATE_GATHER_CONSTANT_GS_GatherBufferOffset_start 70 +#define GEN75_3DSTATE_GATHER_CONSTANT_GS_GatherBufferOffset_start 70 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_GS_GatherBufferOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 70; + case 10: return 70; + case 9: return 70; + case 8: return 70; + case 7: + if (devinfo->is_haswell) { + return 70; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_GS::On-Die Table */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_GS_OnDieTable_bits 1 +#define GEN10_3DSTATE_GATHER_CONSTANT_GS_OnDieTable_bits 1 +#define GEN9_3DSTATE_GATHER_CONSTANT_GS_OnDieTable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_GS_OnDieTable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_GS_OnDieTable_start 67 +#define GEN10_3DSTATE_GATHER_CONSTANT_GS_OnDieTable_start 67 +#define GEN9_3DSTATE_GATHER_CONSTANT_GS_OnDieTable_start 67 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_GS_OnDieTable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 67; + case 10: return 67; + case 9: return 67; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_GS::Update Gather Table Only */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_GS_UpdateGatherTableOnly_bits 1 +#define GEN10_3DSTATE_GATHER_CONSTANT_GS_UpdateGatherTableOnly_bits 1 +#define GEN9_3DSTATE_GATHER_CONSTANT_GS_UpdateGatherTableOnly_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_GS_UpdateGatherTableOnly_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_GS_UpdateGatherTableOnly_start 33 +#define GEN10_3DSTATE_GATHER_CONSTANT_GS_UpdateGatherTableOnly_start 33 +#define GEN9_3DSTATE_GATHER_CONSTANT_GS_UpdateGatherTableOnly_start 33 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_GS_UpdateGatherTableOnly_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 33; + case 10: return 33; + case 9: return 33; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_HS */ + + + + + +/* 3DSTATE_GATHER_CONSTANT_HS::3D Command Opcode */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_HS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_GATHER_CONSTANT_HS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_GATHER_CONSTANT_HS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_GATHER_CONSTANT_HS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_GATHER_CONSTANT_HS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_HS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_HS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_GATHER_CONSTANT_HS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_GATHER_CONSTANT_HS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_GATHER_CONSTANT_HS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_GATHER_CONSTANT_HS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_HS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_HS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_HS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_GATHER_CONSTANT_HS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_GATHER_CONSTANT_HS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_GATHER_CONSTANT_HS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_GATHER_CONSTANT_HS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_HS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_HS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_GATHER_CONSTANT_HS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_GATHER_CONSTANT_HS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_GATHER_CONSTANT_HS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_GATHER_CONSTANT_HS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_HS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_HS::Command SubType */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_HS_CommandSubType_bits 2 +#define GEN10_3DSTATE_GATHER_CONSTANT_HS_CommandSubType_bits 2 +#define GEN9_3DSTATE_GATHER_CONSTANT_HS_CommandSubType_bits 2 +#define GEN8_3DSTATE_GATHER_CONSTANT_HS_CommandSubType_bits 2 +#define GEN75_3DSTATE_GATHER_CONSTANT_HS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_HS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_HS_CommandSubType_start 27 +#define GEN10_3DSTATE_GATHER_CONSTANT_HS_CommandSubType_start 27 +#define GEN9_3DSTATE_GATHER_CONSTANT_HS_CommandSubType_start 27 +#define GEN8_3DSTATE_GATHER_CONSTANT_HS_CommandSubType_start 27 +#define GEN75_3DSTATE_GATHER_CONSTANT_HS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_HS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_HS::Command Type */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_HS_CommandType_bits 3 +#define GEN10_3DSTATE_GATHER_CONSTANT_HS_CommandType_bits 3 +#define GEN9_3DSTATE_GATHER_CONSTANT_HS_CommandType_bits 3 +#define GEN8_3DSTATE_GATHER_CONSTANT_HS_CommandType_bits 3 +#define GEN75_3DSTATE_GATHER_CONSTANT_HS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_HS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_HS_CommandType_start 29 +#define GEN10_3DSTATE_GATHER_CONSTANT_HS_CommandType_start 29 +#define GEN9_3DSTATE_GATHER_CONSTANT_HS_CommandType_start 29 +#define GEN8_3DSTATE_GATHER_CONSTANT_HS_CommandType_start 29 +#define GEN75_3DSTATE_GATHER_CONSTANT_HS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_HS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_HS::Constant Buffer Binding Table Block */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferBindingTableBlock_bits 4 +#define GEN10_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferBindingTableBlock_bits 4 +#define GEN9_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferBindingTableBlock_bits 4 +#define GEN8_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferBindingTableBlock_bits 4 +#define GEN75_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferBindingTableBlock_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferBindingTableBlock_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferBindingTableBlock_start 44 +#define GEN10_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferBindingTableBlock_start 44 +#define GEN9_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferBindingTableBlock_start 44 +#define GEN8_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferBindingTableBlock_start 44 +#define GEN75_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferBindingTableBlock_start 44 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferBindingTableBlock_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 44; + case 10: return 44; + case 9: return 44; + case 8: return 44; + case 7: + if (devinfo->is_haswell) { + return 44; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_HS::Constant Buffer Dx9 Generate Stall */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferDx9GenerateStall_bits 1 +#define GEN10_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferDx9GenerateStall_bits 1 +#define GEN9_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferDx9GenerateStall_bits 1 +#define GEN8_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferDx9GenerateStall_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferDx9GenerateStall_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferDx9GenerateStall_start 69 +#define GEN10_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferDx9GenerateStall_start 69 +#define GEN9_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferDx9GenerateStall_start 69 +#define GEN8_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferDx9GenerateStall_start 69 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferDx9GenerateStall_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 69; + case 10: return 69; + case 9: return 69; + case 8: return 69; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_HS::Constant Buffer Valid */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferValid_bits 16 +#define GEN10_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferValid_bits 16 +#define GEN9_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferValid_bits 16 +#define GEN8_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferValid_bits 16 +#define GEN75_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferValid_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferValid_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferValid_start 48 +#define GEN10_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferValid_start 48 +#define GEN9_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferValid_start 48 +#define GEN8_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferValid_start 48 +#define GEN75_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferValid_start 48 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_HS_ConstantBufferValid_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 48; + case 7: + if (devinfo->is_haswell) { + return 48; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_HS::DWord Length */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_HS_DWordLength_bits 8 +#define GEN10_3DSTATE_GATHER_CONSTANT_HS_DWordLength_bits 8 +#define GEN9_3DSTATE_GATHER_CONSTANT_HS_DWordLength_bits 8 +#define GEN8_3DSTATE_GATHER_CONSTANT_HS_DWordLength_bits 8 +#define GEN75_3DSTATE_GATHER_CONSTANT_HS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_HS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_HS_DWordLength_start 0 +#define GEN10_3DSTATE_GATHER_CONSTANT_HS_DWordLength_start 0 +#define GEN9_3DSTATE_GATHER_CONSTANT_HS_DWordLength_start 0 +#define GEN8_3DSTATE_GATHER_CONSTANT_HS_DWordLength_start 0 +#define GEN75_3DSTATE_GATHER_CONSTANT_HS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_HS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_HS::Entry_0 */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_HS_Entry_0_bits 16 +#define GEN10_3DSTATE_GATHER_CONSTANT_HS_Entry_0_bits 16 +#define GEN9_3DSTATE_GATHER_CONSTANT_HS_Entry_0_bits 16 +#define GEN8_3DSTATE_GATHER_CONSTANT_HS_Entry_0_bits 16 +#define GEN75_3DSTATE_GATHER_CONSTANT_HS_Entry_0_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_HS_Entry_0_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_HS_Entry_0_start 0 +#define GEN10_3DSTATE_GATHER_CONSTANT_HS_Entry_0_start 0 +#define GEN9_3DSTATE_GATHER_CONSTANT_HS_Entry_0_start 0 +#define GEN8_3DSTATE_GATHER_CONSTANT_HS_Entry_0_start 0 +#define GEN75_3DSTATE_GATHER_CONSTANT_HS_Entry_0_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_HS_Entry_0_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_HS::Entry_1 */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_HS_Entry_1_bits 16 +#define GEN10_3DSTATE_GATHER_CONSTANT_HS_Entry_1_bits 16 +#define GEN9_3DSTATE_GATHER_CONSTANT_HS_Entry_1_bits 16 +#define GEN8_3DSTATE_GATHER_CONSTANT_HS_Entry_1_bits 16 +#define GEN75_3DSTATE_GATHER_CONSTANT_HS_Entry_1_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_HS_Entry_1_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_HS_Entry_1_start 16 +#define GEN10_3DSTATE_GATHER_CONSTANT_HS_Entry_1_start 16 +#define GEN9_3DSTATE_GATHER_CONSTANT_HS_Entry_1_start 16 +#define GEN8_3DSTATE_GATHER_CONSTANT_HS_Entry_1_start 16 +#define GEN75_3DSTATE_GATHER_CONSTANT_HS_Entry_1_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_HS_Entry_1_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_HS::Gather Buffer Offset */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_HS_GatherBufferOffset_bits 17 +#define GEN10_3DSTATE_GATHER_CONSTANT_HS_GatherBufferOffset_bits 17 +#define GEN9_3DSTATE_GATHER_CONSTANT_HS_GatherBufferOffset_bits 17 +#define GEN8_3DSTATE_GATHER_CONSTANT_HS_GatherBufferOffset_bits 17 +#define GEN75_3DSTATE_GATHER_CONSTANT_HS_GatherBufferOffset_bits 17 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_HS_GatherBufferOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 17; + case 10: return 17; + case 9: return 17; + case 8: return 17; + case 7: + if (devinfo->is_haswell) { + return 17; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_HS_GatherBufferOffset_start 70 +#define GEN10_3DSTATE_GATHER_CONSTANT_HS_GatherBufferOffset_start 70 +#define GEN9_3DSTATE_GATHER_CONSTANT_HS_GatherBufferOffset_start 70 +#define GEN8_3DSTATE_GATHER_CONSTANT_HS_GatherBufferOffset_start 70 +#define GEN75_3DSTATE_GATHER_CONSTANT_HS_GatherBufferOffset_start 70 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_HS_GatherBufferOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 70; + case 10: return 70; + case 9: return 70; + case 8: return 70; + case 7: + if (devinfo->is_haswell) { + return 70; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_HS::On-Die Table */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_HS_OnDieTable_bits 1 +#define GEN10_3DSTATE_GATHER_CONSTANT_HS_OnDieTable_bits 1 +#define GEN9_3DSTATE_GATHER_CONSTANT_HS_OnDieTable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_HS_OnDieTable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_HS_OnDieTable_start 67 +#define GEN10_3DSTATE_GATHER_CONSTANT_HS_OnDieTable_start 67 +#define GEN9_3DSTATE_GATHER_CONSTANT_HS_OnDieTable_start 67 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_HS_OnDieTable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 67; + case 10: return 67; + case 9: return 67; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_HS::Update Gather Table Only */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_HS_UpdateGatherTableOnly_bits 1 +#define GEN10_3DSTATE_GATHER_CONSTANT_HS_UpdateGatherTableOnly_bits 1 +#define GEN9_3DSTATE_GATHER_CONSTANT_HS_UpdateGatherTableOnly_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_HS_UpdateGatherTableOnly_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_HS_UpdateGatherTableOnly_start 33 +#define GEN10_3DSTATE_GATHER_CONSTANT_HS_UpdateGatherTableOnly_start 33 +#define GEN9_3DSTATE_GATHER_CONSTANT_HS_UpdateGatherTableOnly_start 33 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_HS_UpdateGatherTableOnly_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 33; + case 10: return 33; + case 9: return 33; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_PS */ + + + + + +/* 3DSTATE_GATHER_CONSTANT_PS::3D Command Opcode */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_PS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_GATHER_CONSTANT_PS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_GATHER_CONSTANT_PS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_GATHER_CONSTANT_PS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_GATHER_CONSTANT_PS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_PS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_PS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_GATHER_CONSTANT_PS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_GATHER_CONSTANT_PS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_GATHER_CONSTANT_PS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_GATHER_CONSTANT_PS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_PS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_PS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_PS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_GATHER_CONSTANT_PS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_GATHER_CONSTANT_PS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_GATHER_CONSTANT_PS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_GATHER_CONSTANT_PS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_PS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_PS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_GATHER_CONSTANT_PS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_GATHER_CONSTANT_PS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_GATHER_CONSTANT_PS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_GATHER_CONSTANT_PS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_PS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_PS::Command SubType */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_PS_CommandSubType_bits 2 +#define GEN10_3DSTATE_GATHER_CONSTANT_PS_CommandSubType_bits 2 +#define GEN9_3DSTATE_GATHER_CONSTANT_PS_CommandSubType_bits 2 +#define GEN8_3DSTATE_GATHER_CONSTANT_PS_CommandSubType_bits 2 +#define GEN75_3DSTATE_GATHER_CONSTANT_PS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_PS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_PS_CommandSubType_start 27 +#define GEN10_3DSTATE_GATHER_CONSTANT_PS_CommandSubType_start 27 +#define GEN9_3DSTATE_GATHER_CONSTANT_PS_CommandSubType_start 27 +#define GEN8_3DSTATE_GATHER_CONSTANT_PS_CommandSubType_start 27 +#define GEN75_3DSTATE_GATHER_CONSTANT_PS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_PS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_PS::Command Type */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_PS_CommandType_bits 3 +#define GEN10_3DSTATE_GATHER_CONSTANT_PS_CommandType_bits 3 +#define GEN9_3DSTATE_GATHER_CONSTANT_PS_CommandType_bits 3 +#define GEN8_3DSTATE_GATHER_CONSTANT_PS_CommandType_bits 3 +#define GEN75_3DSTATE_GATHER_CONSTANT_PS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_PS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_PS_CommandType_start 29 +#define GEN10_3DSTATE_GATHER_CONSTANT_PS_CommandType_start 29 +#define GEN9_3DSTATE_GATHER_CONSTANT_PS_CommandType_start 29 +#define GEN8_3DSTATE_GATHER_CONSTANT_PS_CommandType_start 29 +#define GEN75_3DSTATE_GATHER_CONSTANT_PS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_PS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_PS::Constant Buffer Binding Table Block */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferBindingTableBlock_bits 4 +#define GEN10_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferBindingTableBlock_bits 4 +#define GEN9_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferBindingTableBlock_bits 4 +#define GEN8_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferBindingTableBlock_bits 4 +#define GEN75_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferBindingTableBlock_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferBindingTableBlock_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferBindingTableBlock_start 44 +#define GEN10_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferBindingTableBlock_start 44 +#define GEN9_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferBindingTableBlock_start 44 +#define GEN8_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferBindingTableBlock_start 44 +#define GEN75_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferBindingTableBlock_start 44 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferBindingTableBlock_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 44; + case 10: return 44; + case 9: return 44; + case 8: return 44; + case 7: + if (devinfo->is_haswell) { + return 44; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_PS::Constant Buffer Dx9 Enable */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9Enable_bits 1 +#define GEN10_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9Enable_bits 1 +#define GEN9_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9Enable_bits 1 +#define GEN8_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9Enable_bits 1 +#define GEN75_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9Enable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9Enable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9Enable_start 68 +#define GEN10_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9Enable_start 68 +#define GEN9_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9Enable_start 68 +#define GEN8_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9Enable_start 68 +#define GEN75_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9Enable_start 68 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9Enable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 68; + case 10: return 68; + case 9: return 68; + case 8: return 68; + case 7: + if (devinfo->is_haswell) { + return 68; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_PS::Constant Buffer Dx9 Generate Stall */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9GenerateStall_bits 1 +#define GEN10_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9GenerateStall_bits 1 +#define GEN9_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9GenerateStall_bits 1 +#define GEN8_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9GenerateStall_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9GenerateStall_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9GenerateStall_start 69 +#define GEN10_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9GenerateStall_start 69 +#define GEN9_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9GenerateStall_start 69 +#define GEN8_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9GenerateStall_start 69 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferDx9GenerateStall_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 69; + case 10: return 69; + case 9: return 69; + case 8: return 69; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_PS::Constant Buffer Valid */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferValid_bits 16 +#define GEN10_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferValid_bits 16 +#define GEN9_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferValid_bits 16 +#define GEN8_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferValid_bits 16 +#define GEN75_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferValid_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferValid_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferValid_start 48 +#define GEN10_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferValid_start 48 +#define GEN9_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferValid_start 48 +#define GEN8_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferValid_start 48 +#define GEN75_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferValid_start 48 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_PS_ConstantBufferValid_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 48; + case 7: + if (devinfo->is_haswell) { + return 48; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_PS::DWord Length */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_PS_DWordLength_bits 8 +#define GEN10_3DSTATE_GATHER_CONSTANT_PS_DWordLength_bits 8 +#define GEN9_3DSTATE_GATHER_CONSTANT_PS_DWordLength_bits 8 +#define GEN8_3DSTATE_GATHER_CONSTANT_PS_DWordLength_bits 8 +#define GEN75_3DSTATE_GATHER_CONSTANT_PS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_PS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_PS_DWordLength_start 0 +#define GEN10_3DSTATE_GATHER_CONSTANT_PS_DWordLength_start 0 +#define GEN9_3DSTATE_GATHER_CONSTANT_PS_DWordLength_start 0 +#define GEN8_3DSTATE_GATHER_CONSTANT_PS_DWordLength_start 0 +#define GEN75_3DSTATE_GATHER_CONSTANT_PS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_PS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_PS::DX9 On-Die Register Read Enable */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_PS_DX9OnDieRegisterReadEnable_bits 1 +#define GEN10_3DSTATE_GATHER_CONSTANT_PS_DX9OnDieRegisterReadEnable_bits 1 +#define GEN9_3DSTATE_GATHER_CONSTANT_PS_DX9OnDieRegisterReadEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_PS_DX9OnDieRegisterReadEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_PS_DX9OnDieRegisterReadEnable_start 32 +#define GEN10_3DSTATE_GATHER_CONSTANT_PS_DX9OnDieRegisterReadEnable_start 32 +#define GEN9_3DSTATE_GATHER_CONSTANT_PS_DX9OnDieRegisterReadEnable_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_PS_DX9OnDieRegisterReadEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_PS::Entry_0 */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_PS_Entry_0_bits 16 +#define GEN10_3DSTATE_GATHER_CONSTANT_PS_Entry_0_bits 16 +#define GEN9_3DSTATE_GATHER_CONSTANT_PS_Entry_0_bits 16 +#define GEN8_3DSTATE_GATHER_CONSTANT_PS_Entry_0_bits 16 +#define GEN75_3DSTATE_GATHER_CONSTANT_PS_Entry_0_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_PS_Entry_0_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_PS_Entry_0_start 0 +#define GEN10_3DSTATE_GATHER_CONSTANT_PS_Entry_0_start 0 +#define GEN9_3DSTATE_GATHER_CONSTANT_PS_Entry_0_start 0 +#define GEN8_3DSTATE_GATHER_CONSTANT_PS_Entry_0_start 0 +#define GEN75_3DSTATE_GATHER_CONSTANT_PS_Entry_0_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_PS_Entry_0_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_PS::Entry_1 */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_PS_Entry_1_bits 16 +#define GEN10_3DSTATE_GATHER_CONSTANT_PS_Entry_1_bits 16 +#define GEN9_3DSTATE_GATHER_CONSTANT_PS_Entry_1_bits 16 +#define GEN8_3DSTATE_GATHER_CONSTANT_PS_Entry_1_bits 16 +#define GEN75_3DSTATE_GATHER_CONSTANT_PS_Entry_1_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_PS_Entry_1_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_PS_Entry_1_start 16 +#define GEN10_3DSTATE_GATHER_CONSTANT_PS_Entry_1_start 16 +#define GEN9_3DSTATE_GATHER_CONSTANT_PS_Entry_1_start 16 +#define GEN8_3DSTATE_GATHER_CONSTANT_PS_Entry_1_start 16 +#define GEN75_3DSTATE_GATHER_CONSTANT_PS_Entry_1_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_PS_Entry_1_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_PS::Gather Buffer Offset */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_PS_GatherBufferOffset_bits 17 +#define GEN10_3DSTATE_GATHER_CONSTANT_PS_GatherBufferOffset_bits 17 +#define GEN9_3DSTATE_GATHER_CONSTANT_PS_GatherBufferOffset_bits 17 +#define GEN8_3DSTATE_GATHER_CONSTANT_PS_GatherBufferOffset_bits 17 +#define GEN75_3DSTATE_GATHER_CONSTANT_PS_GatherBufferOffset_bits 17 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_PS_GatherBufferOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 17; + case 10: return 17; + case 9: return 17; + case 8: return 17; + case 7: + if (devinfo->is_haswell) { + return 17; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_PS_GatherBufferOffset_start 70 +#define GEN10_3DSTATE_GATHER_CONSTANT_PS_GatherBufferOffset_start 70 +#define GEN9_3DSTATE_GATHER_CONSTANT_PS_GatherBufferOffset_start 70 +#define GEN8_3DSTATE_GATHER_CONSTANT_PS_GatherBufferOffset_start 70 +#define GEN75_3DSTATE_GATHER_CONSTANT_PS_GatherBufferOffset_start 70 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_PS_GatherBufferOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 70; + case 10: return 70; + case 9: return 70; + case 8: return 70; + case 7: + if (devinfo->is_haswell) { + return 70; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_PS::On-Die Table */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_PS_OnDieTable_bits 1 +#define GEN10_3DSTATE_GATHER_CONSTANT_PS_OnDieTable_bits 1 +#define GEN9_3DSTATE_GATHER_CONSTANT_PS_OnDieTable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_PS_OnDieTable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_PS_OnDieTable_start 67 +#define GEN10_3DSTATE_GATHER_CONSTANT_PS_OnDieTable_start 67 +#define GEN9_3DSTATE_GATHER_CONSTANT_PS_OnDieTable_start 67 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_PS_OnDieTable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 67; + case 10: return 67; + case 9: return 67; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_PS::Update Gather Table Only */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_PS_UpdateGatherTableOnly_bits 1 +#define GEN10_3DSTATE_GATHER_CONSTANT_PS_UpdateGatherTableOnly_bits 1 +#define GEN9_3DSTATE_GATHER_CONSTANT_PS_UpdateGatherTableOnly_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_PS_UpdateGatherTableOnly_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_PS_UpdateGatherTableOnly_start 33 +#define GEN10_3DSTATE_GATHER_CONSTANT_PS_UpdateGatherTableOnly_start 33 +#define GEN9_3DSTATE_GATHER_CONSTANT_PS_UpdateGatherTableOnly_start 33 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_PS_UpdateGatherTableOnly_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 33; + case 10: return 33; + case 9: return 33; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_VS */ + + + + + +/* 3DSTATE_GATHER_CONSTANT_VS::3D Command Opcode */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_VS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_GATHER_CONSTANT_VS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_GATHER_CONSTANT_VS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_GATHER_CONSTANT_VS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_GATHER_CONSTANT_VS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_VS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_VS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_GATHER_CONSTANT_VS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_GATHER_CONSTANT_VS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_GATHER_CONSTANT_VS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_GATHER_CONSTANT_VS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_VS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_VS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_VS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_GATHER_CONSTANT_VS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_GATHER_CONSTANT_VS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_GATHER_CONSTANT_VS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_GATHER_CONSTANT_VS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_VS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_VS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_GATHER_CONSTANT_VS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_GATHER_CONSTANT_VS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_GATHER_CONSTANT_VS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_GATHER_CONSTANT_VS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_VS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_VS::Command SubType */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_VS_CommandSubType_bits 2 +#define GEN10_3DSTATE_GATHER_CONSTANT_VS_CommandSubType_bits 2 +#define GEN9_3DSTATE_GATHER_CONSTANT_VS_CommandSubType_bits 2 +#define GEN8_3DSTATE_GATHER_CONSTANT_VS_CommandSubType_bits 2 +#define GEN75_3DSTATE_GATHER_CONSTANT_VS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_VS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_VS_CommandSubType_start 27 +#define GEN10_3DSTATE_GATHER_CONSTANT_VS_CommandSubType_start 27 +#define GEN9_3DSTATE_GATHER_CONSTANT_VS_CommandSubType_start 27 +#define GEN8_3DSTATE_GATHER_CONSTANT_VS_CommandSubType_start 27 +#define GEN75_3DSTATE_GATHER_CONSTANT_VS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_VS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_VS::Command Type */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_VS_CommandType_bits 3 +#define GEN10_3DSTATE_GATHER_CONSTANT_VS_CommandType_bits 3 +#define GEN9_3DSTATE_GATHER_CONSTANT_VS_CommandType_bits 3 +#define GEN8_3DSTATE_GATHER_CONSTANT_VS_CommandType_bits 3 +#define GEN75_3DSTATE_GATHER_CONSTANT_VS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_VS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_VS_CommandType_start 29 +#define GEN10_3DSTATE_GATHER_CONSTANT_VS_CommandType_start 29 +#define GEN9_3DSTATE_GATHER_CONSTANT_VS_CommandType_start 29 +#define GEN8_3DSTATE_GATHER_CONSTANT_VS_CommandType_start 29 +#define GEN75_3DSTATE_GATHER_CONSTANT_VS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_VS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_VS::Constant Buffer Binding Table Block */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferBindingTableBlock_bits 4 +#define GEN10_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferBindingTableBlock_bits 4 +#define GEN9_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferBindingTableBlock_bits 4 +#define GEN8_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferBindingTableBlock_bits 4 +#define GEN75_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferBindingTableBlock_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferBindingTableBlock_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferBindingTableBlock_start 44 +#define GEN10_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferBindingTableBlock_start 44 +#define GEN9_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferBindingTableBlock_start 44 +#define GEN8_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferBindingTableBlock_start 44 +#define GEN75_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferBindingTableBlock_start 44 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferBindingTableBlock_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 44; + case 10: return 44; + case 9: return 44; + case 8: return 44; + case 7: + if (devinfo->is_haswell) { + return 44; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_VS::Constant Buffer Dx9 Enable */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9Enable_bits 1 +#define GEN10_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9Enable_bits 1 +#define GEN9_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9Enable_bits 1 +#define GEN8_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9Enable_bits 1 +#define GEN75_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9Enable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9Enable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9Enable_start 68 +#define GEN10_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9Enable_start 68 +#define GEN9_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9Enable_start 68 +#define GEN8_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9Enable_start 68 +#define GEN75_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9Enable_start 68 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9Enable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 68; + case 10: return 68; + case 9: return 68; + case 8: return 68; + case 7: + if (devinfo->is_haswell) { + return 68; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_VS::Constant Buffer Dx9 Generate Stall */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9GenerateStall_bits 1 +#define GEN10_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9GenerateStall_bits 1 +#define GEN9_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9GenerateStall_bits 1 +#define GEN8_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9GenerateStall_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9GenerateStall_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9GenerateStall_start 69 +#define GEN10_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9GenerateStall_start 69 +#define GEN9_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9GenerateStall_start 69 +#define GEN8_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9GenerateStall_start 69 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferDx9GenerateStall_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 69; + case 10: return 69; + case 9: return 69; + case 8: return 69; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_VS::Constant Buffer Valid */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferValid_bits 16 +#define GEN10_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferValid_bits 16 +#define GEN9_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferValid_bits 16 +#define GEN8_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferValid_bits 16 +#define GEN75_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferValid_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferValid_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferValid_start 48 +#define GEN10_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferValid_start 48 +#define GEN9_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferValid_start 48 +#define GEN8_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferValid_start 48 +#define GEN75_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferValid_start 48 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_VS_ConstantBufferValid_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 48; + case 7: + if (devinfo->is_haswell) { + return 48; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_VS::DWord Length */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_VS_DWordLength_bits 8 +#define GEN10_3DSTATE_GATHER_CONSTANT_VS_DWordLength_bits 8 +#define GEN9_3DSTATE_GATHER_CONSTANT_VS_DWordLength_bits 8 +#define GEN8_3DSTATE_GATHER_CONSTANT_VS_DWordLength_bits 8 +#define GEN75_3DSTATE_GATHER_CONSTANT_VS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_VS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_VS_DWordLength_start 0 +#define GEN10_3DSTATE_GATHER_CONSTANT_VS_DWordLength_start 0 +#define GEN9_3DSTATE_GATHER_CONSTANT_VS_DWordLength_start 0 +#define GEN8_3DSTATE_GATHER_CONSTANT_VS_DWordLength_start 0 +#define GEN75_3DSTATE_GATHER_CONSTANT_VS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_VS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_VS::DX9 On-Die Register Read Enable */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_VS_DX9OnDieRegisterReadEnable_bits 1 +#define GEN10_3DSTATE_GATHER_CONSTANT_VS_DX9OnDieRegisterReadEnable_bits 1 +#define GEN9_3DSTATE_GATHER_CONSTANT_VS_DX9OnDieRegisterReadEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_VS_DX9OnDieRegisterReadEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_VS_DX9OnDieRegisterReadEnable_start 32 +#define GEN10_3DSTATE_GATHER_CONSTANT_VS_DX9OnDieRegisterReadEnable_start 32 +#define GEN9_3DSTATE_GATHER_CONSTANT_VS_DX9OnDieRegisterReadEnable_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_VS_DX9OnDieRegisterReadEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_VS::Entry_0 */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_VS_Entry_0_bits 16 +#define GEN10_3DSTATE_GATHER_CONSTANT_VS_Entry_0_bits 16 +#define GEN9_3DSTATE_GATHER_CONSTANT_VS_Entry_0_bits 16 +#define GEN8_3DSTATE_GATHER_CONSTANT_VS_Entry_0_bits 16 +#define GEN75_3DSTATE_GATHER_CONSTANT_VS_Entry_0_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_VS_Entry_0_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_VS_Entry_0_start 0 +#define GEN10_3DSTATE_GATHER_CONSTANT_VS_Entry_0_start 0 +#define GEN9_3DSTATE_GATHER_CONSTANT_VS_Entry_0_start 0 +#define GEN8_3DSTATE_GATHER_CONSTANT_VS_Entry_0_start 0 +#define GEN75_3DSTATE_GATHER_CONSTANT_VS_Entry_0_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_VS_Entry_0_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_VS::Entry_1 */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_VS_Entry_1_bits 16 +#define GEN10_3DSTATE_GATHER_CONSTANT_VS_Entry_1_bits 16 +#define GEN9_3DSTATE_GATHER_CONSTANT_VS_Entry_1_bits 16 +#define GEN8_3DSTATE_GATHER_CONSTANT_VS_Entry_1_bits 16 +#define GEN75_3DSTATE_GATHER_CONSTANT_VS_Entry_1_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_VS_Entry_1_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_VS_Entry_1_start 16 +#define GEN10_3DSTATE_GATHER_CONSTANT_VS_Entry_1_start 16 +#define GEN9_3DSTATE_GATHER_CONSTANT_VS_Entry_1_start 16 +#define GEN8_3DSTATE_GATHER_CONSTANT_VS_Entry_1_start 16 +#define GEN75_3DSTATE_GATHER_CONSTANT_VS_Entry_1_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_VS_Entry_1_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_VS::Gather Buffer Offset */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_VS_GatherBufferOffset_bits 17 +#define GEN10_3DSTATE_GATHER_CONSTANT_VS_GatherBufferOffset_bits 17 +#define GEN9_3DSTATE_GATHER_CONSTANT_VS_GatherBufferOffset_bits 17 +#define GEN8_3DSTATE_GATHER_CONSTANT_VS_GatherBufferOffset_bits 17 +#define GEN75_3DSTATE_GATHER_CONSTANT_VS_GatherBufferOffset_bits 17 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_VS_GatherBufferOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 17; + case 10: return 17; + case 9: return 17; + case 8: return 17; + case 7: + if (devinfo->is_haswell) { + return 17; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_VS_GatherBufferOffset_start 70 +#define GEN10_3DSTATE_GATHER_CONSTANT_VS_GatherBufferOffset_start 70 +#define GEN9_3DSTATE_GATHER_CONSTANT_VS_GatherBufferOffset_start 70 +#define GEN8_3DSTATE_GATHER_CONSTANT_VS_GatherBufferOffset_start 70 +#define GEN75_3DSTATE_GATHER_CONSTANT_VS_GatherBufferOffset_start 70 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_VS_GatherBufferOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 70; + case 10: return 70; + case 9: return 70; + case 8: return 70; + case 7: + if (devinfo->is_haswell) { + return 70; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_VS::On-Die Table */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_VS_OnDieTable_bits 1 +#define GEN10_3DSTATE_GATHER_CONSTANT_VS_OnDieTable_bits 1 +#define GEN9_3DSTATE_GATHER_CONSTANT_VS_OnDieTable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_VS_OnDieTable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_VS_OnDieTable_start 67 +#define GEN10_3DSTATE_GATHER_CONSTANT_VS_OnDieTable_start 67 +#define GEN9_3DSTATE_GATHER_CONSTANT_VS_OnDieTable_start 67 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_VS_OnDieTable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 67; + case 10: return 67; + case 9: return 67; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_CONSTANT_VS::Update Gather Table Only */ + + +#define GEN11_3DSTATE_GATHER_CONSTANT_VS_UpdateGatherTableOnly_bits 1 +#define GEN10_3DSTATE_GATHER_CONSTANT_VS_UpdateGatherTableOnly_bits 1 +#define GEN9_3DSTATE_GATHER_CONSTANT_VS_UpdateGatherTableOnly_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_VS_UpdateGatherTableOnly_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_CONSTANT_VS_UpdateGatherTableOnly_start 33 +#define GEN10_3DSTATE_GATHER_CONSTANT_VS_UpdateGatherTableOnly_start 33 +#define GEN9_3DSTATE_GATHER_CONSTANT_VS_UpdateGatherTableOnly_start 33 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_CONSTANT_VS_UpdateGatherTableOnly_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 33; + case 10: return 33; + case 9: return 33; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_POOL_ALLOC */ + + +#define GEN11_3DSTATE_GATHER_POOL_ALLOC_length 4 +#define GEN10_3DSTATE_GATHER_POOL_ALLOC_length 4 +#define GEN9_3DSTATE_GATHER_POOL_ALLOC_length 4 +#define GEN8_3DSTATE_GATHER_POOL_ALLOC_length 4 +#define GEN75_3DSTATE_GATHER_POOL_ALLOC_length 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_POOL_ALLOC_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_POOL_ALLOC::3D Command Opcode */ + + +#define GEN11_3DSTATE_GATHER_POOL_ALLOC_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_GATHER_POOL_ALLOC_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_GATHER_POOL_ALLOC_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_GATHER_POOL_ALLOC_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_GATHER_POOL_ALLOC_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_POOL_ALLOC_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_POOL_ALLOC_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_GATHER_POOL_ALLOC_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_GATHER_POOL_ALLOC_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_GATHER_POOL_ALLOC_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_GATHER_POOL_ALLOC_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_POOL_ALLOC_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_POOL_ALLOC::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_GATHER_POOL_ALLOC_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_GATHER_POOL_ALLOC_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_GATHER_POOL_ALLOC_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_GATHER_POOL_ALLOC_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_GATHER_POOL_ALLOC_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_POOL_ALLOC_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_POOL_ALLOC_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_GATHER_POOL_ALLOC_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_GATHER_POOL_ALLOC_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_GATHER_POOL_ALLOC_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_GATHER_POOL_ALLOC_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_POOL_ALLOC_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_POOL_ALLOC::Command SubType */ + + +#define GEN11_3DSTATE_GATHER_POOL_ALLOC_CommandSubType_bits 2 +#define GEN10_3DSTATE_GATHER_POOL_ALLOC_CommandSubType_bits 2 +#define GEN9_3DSTATE_GATHER_POOL_ALLOC_CommandSubType_bits 2 +#define GEN8_3DSTATE_GATHER_POOL_ALLOC_CommandSubType_bits 2 +#define GEN75_3DSTATE_GATHER_POOL_ALLOC_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_POOL_ALLOC_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_POOL_ALLOC_CommandSubType_start 27 +#define GEN10_3DSTATE_GATHER_POOL_ALLOC_CommandSubType_start 27 +#define GEN9_3DSTATE_GATHER_POOL_ALLOC_CommandSubType_start 27 +#define GEN8_3DSTATE_GATHER_POOL_ALLOC_CommandSubType_start 27 +#define GEN75_3DSTATE_GATHER_POOL_ALLOC_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_POOL_ALLOC_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_POOL_ALLOC::Command Type */ + + +#define GEN11_3DSTATE_GATHER_POOL_ALLOC_CommandType_bits 3 +#define GEN10_3DSTATE_GATHER_POOL_ALLOC_CommandType_bits 3 +#define GEN9_3DSTATE_GATHER_POOL_ALLOC_CommandType_bits 3 +#define GEN8_3DSTATE_GATHER_POOL_ALLOC_CommandType_bits 3 +#define GEN75_3DSTATE_GATHER_POOL_ALLOC_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_POOL_ALLOC_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_POOL_ALLOC_CommandType_start 29 +#define GEN10_3DSTATE_GATHER_POOL_ALLOC_CommandType_start 29 +#define GEN9_3DSTATE_GATHER_POOL_ALLOC_CommandType_start 29 +#define GEN8_3DSTATE_GATHER_POOL_ALLOC_CommandType_start 29 +#define GEN75_3DSTATE_GATHER_POOL_ALLOC_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_POOL_ALLOC_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_POOL_ALLOC::DWord Length */ + + +#define GEN11_3DSTATE_GATHER_POOL_ALLOC_DWordLength_bits 8 +#define GEN10_3DSTATE_GATHER_POOL_ALLOC_DWordLength_bits 8 +#define GEN9_3DSTATE_GATHER_POOL_ALLOC_DWordLength_bits 8 +#define GEN8_3DSTATE_GATHER_POOL_ALLOC_DWordLength_bits 8 +#define GEN75_3DSTATE_GATHER_POOL_ALLOC_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_POOL_ALLOC_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_POOL_ALLOC_DWordLength_start 0 +#define GEN10_3DSTATE_GATHER_POOL_ALLOC_DWordLength_start 0 +#define GEN9_3DSTATE_GATHER_POOL_ALLOC_DWordLength_start 0 +#define GEN8_3DSTATE_GATHER_POOL_ALLOC_DWordLength_start 0 +#define GEN75_3DSTATE_GATHER_POOL_ALLOC_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_POOL_ALLOC_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_POOL_ALLOC::Gather Pool Base Address */ + + +#define GEN11_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBaseAddress_bits 52 +#define GEN10_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBaseAddress_bits 52 +#define GEN9_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBaseAddress_bits 52 +#define GEN8_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBaseAddress_bits 52 +#define GEN75_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBaseAddress_bits 20 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBaseAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 52; + case 10: return 52; + case 9: return 52; + case 8: return 52; + case 7: + if (devinfo->is_haswell) { + return 20; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBaseAddress_start 44 +#define GEN10_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBaseAddress_start 44 +#define GEN9_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBaseAddress_start 44 +#define GEN8_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBaseAddress_start 44 +#define GEN75_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBaseAddress_start 44 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBaseAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 44; + case 10: return 44; + case 9: return 44; + case 8: return 44; + case 7: + if (devinfo->is_haswell) { + return 44; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_POOL_ALLOC::Gather Pool Buffer Size */ + + +#define GEN11_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBufferSize_bits 20 +#define GEN10_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBufferSize_bits 20 +#define GEN9_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBufferSize_bits 20 +#define GEN8_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBufferSize_bits 20 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBufferSize_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 20; + case 10: return 20; + case 9: return 20; + case 8: return 20; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBufferSize_start 108 +#define GEN10_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBufferSize_start 108 +#define GEN9_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBufferSize_start 108 +#define GEN8_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBufferSize_start 108 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_POOL_ALLOC_GatherPoolBufferSize_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 108; + case 10: return 108; + case 9: return 108; + case 8: return 108; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_POOL_ALLOC::Gather Pool Enable */ + + +#define GEN11_3DSTATE_GATHER_POOL_ALLOC_GatherPoolEnable_bits 1 +#define GEN10_3DSTATE_GATHER_POOL_ALLOC_GatherPoolEnable_bits 1 +#define GEN9_3DSTATE_GATHER_POOL_ALLOC_GatherPoolEnable_bits 1 +#define GEN8_3DSTATE_GATHER_POOL_ALLOC_GatherPoolEnable_bits 1 +#define GEN75_3DSTATE_GATHER_POOL_ALLOC_GatherPoolEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_POOL_ALLOC_GatherPoolEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_POOL_ALLOC_GatherPoolEnable_start 43 +#define GEN10_3DSTATE_GATHER_POOL_ALLOC_GatherPoolEnable_start 43 +#define GEN9_3DSTATE_GATHER_POOL_ALLOC_GatherPoolEnable_start 43 +#define GEN8_3DSTATE_GATHER_POOL_ALLOC_GatherPoolEnable_start 43 +#define GEN75_3DSTATE_GATHER_POOL_ALLOC_GatherPoolEnable_start 43 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_POOL_ALLOC_GatherPoolEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 43; + case 10: return 43; + case 9: return 43; + case 8: return 43; + case 7: + if (devinfo->is_haswell) { + return 43; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_POOL_ALLOC::Gather Pool Upper Bound */ + + +#define GEN75_3DSTATE_GATHER_POOL_ALLOC_GatherPoolUpperBound_bits 20 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_POOL_ALLOC_GatherPoolUpperBound_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 20; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_GATHER_POOL_ALLOC_GatherPoolUpperBound_start 76 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_POOL_ALLOC_GatherPoolUpperBound_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 76; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GATHER_POOL_ALLOC::MOCS */ + + +#define GEN11_3DSTATE_GATHER_POOL_ALLOC_MOCS_bits 7 +#define GEN10_3DSTATE_GATHER_POOL_ALLOC_MOCS_bits 7 +#define GEN9_3DSTATE_GATHER_POOL_ALLOC_MOCS_bits 7 +#define GEN8_3DSTATE_GATHER_POOL_ALLOC_MOCS_bits 7 +#define GEN75_3DSTATE_GATHER_POOL_ALLOC_MOCS_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_POOL_ALLOC_MOCS_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GATHER_POOL_ALLOC_MOCS_start 32 +#define GEN10_3DSTATE_GATHER_POOL_ALLOC_MOCS_start 32 +#define GEN9_3DSTATE_GATHER_POOL_ALLOC_MOCS_start 32 +#define GEN8_3DSTATE_GATHER_POOL_ALLOC_MOCS_start 32 +#define GEN75_3DSTATE_GATHER_POOL_ALLOC_MOCS_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GATHER_POOL_ALLOC_MOCS_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP */ + + +#define GEN5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_length 2 +#define GEN45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_length 2 +#define GEN4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_length 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP::3D Command Opcode */ + + +#define GEN5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandOpcode_bits 3 +#define GEN45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandOpcode_bits 3 +#define GEN4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandOpcode_start 24 +#define GEN45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandOpcode_start 24 +#define GEN4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 24; + case 4: + if (devinfo->is_g4x) { + return 24; + } else { + return 24; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP::3D Command Sub Opcode */ + + +#define GEN5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandSubOpcode_bits 8 +#define GEN45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandSubOpcode_bits 8 +#define GEN4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandSubOpcode_start 16 +#define GEN45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandSubOpcode_start 16 +#define GEN4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP::Command SubType */ + + +#define GEN5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandSubType_bits 2 +#define GEN45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandSubType_bits 2 +#define GEN4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandSubType_start 27 +#define GEN45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandSubType_start 27 +#define GEN4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP::Command Type */ + + +#define GEN5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandType_bits 3 +#define GEN45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandType_bits 3 +#define GEN4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandType_start 29 +#define GEN45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandType_start 29 +#define GEN4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 29; + case 4: + if (devinfo->is_g4x) { + return 29; + } else { + return 29; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP::DWord Length */ + + +#define GEN5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_DWordLength_bits 8 +#define GEN45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_DWordLength_bits 8 +#define GEN4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_DWordLength_start 0 +#define GEN45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_DWordLength_start 0 +#define GEN4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP::Global Depth Offset Clamp */ + + +#define GEN5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_GlobalDepthOffsetClamp_bits 32 +#define GEN45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_GlobalDepthOffsetClamp_bits 32 +#define GEN4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_GlobalDepthOffsetClamp_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_GlobalDepthOffsetClamp_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_GlobalDepthOffsetClamp_start 32 +#define GEN45_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_GlobalDepthOffsetClamp_start 32 +#define GEN4_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_GlobalDepthOffsetClamp_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP_GlobalDepthOffsetClamp_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS */ + + +#define GEN11_3DSTATE_GS_length 10 +#define GEN10_3DSTATE_GS_length 10 +#define GEN9_3DSTATE_GS_length 10 +#define GEN8_3DSTATE_GS_length 10 +#define GEN75_3DSTATE_GS_length 7 +#define GEN7_3DSTATE_GS_length 7 +#define GEN6_3DSTATE_GS_length 7 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 10; + case 10: return 10; + case 9: return 10; + case 8: return 10; + case 7: + if (devinfo->is_haswell) { + return 7; + } else { + return 7; + } + case 6: return 7; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::3D Command Opcode */ + + +#define GEN11_3DSTATE_GS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_GS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_GS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_GS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_GS_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_GS_3DCommandOpcode_bits 3 +#define GEN6_3DSTATE_GS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_GS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_GS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_GS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_GS_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_GS_3DCommandOpcode_start 24 +#define GEN6_3DSTATE_GS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_GS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_GS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_GS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_GS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_GS_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_GS_3DCommandSubOpcode_bits 8 +#define GEN6_3DSTATE_GS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_GS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_GS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_GS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_GS_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_GS_3DCommandSubOpcode_start 16 +#define GEN6_3DSTATE_GS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Accesses UAV */ + + +#define GEN11_3DSTATE_GS_AccessesUAV_bits 1 +#define GEN10_3DSTATE_GS_AccessesUAV_bits 1 +#define GEN9_3DSTATE_GS_AccessesUAV_bits 1 +#define GEN8_3DSTATE_GS_AccessesUAV_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_AccessesUAV_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_AccessesUAV_start 108 +#define GEN10_3DSTATE_GS_AccessesUAV_start 108 +#define GEN9_3DSTATE_GS_AccessesUAV_start 108 +#define GEN8_3DSTATE_GS_AccessesUAV_start 108 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_AccessesUAV_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 108; + case 10: return 108; + case 9: return 108; + case 8: return 108; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Binding Table Entry Count */ + + +#define GEN11_3DSTATE_GS_BindingTableEntryCount_bits 8 +#define GEN10_3DSTATE_GS_BindingTableEntryCount_bits 8 +#define GEN9_3DSTATE_GS_BindingTableEntryCount_bits 8 +#define GEN8_3DSTATE_GS_BindingTableEntryCount_bits 8 +#define GEN75_3DSTATE_GS_BindingTableEntryCount_bits 8 +#define GEN7_3DSTATE_GS_BindingTableEntryCount_bits 8 +#define GEN6_3DSTATE_GS_BindingTableEntryCount_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_BindingTableEntryCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_BindingTableEntryCount_start 114 +#define GEN10_3DSTATE_GS_BindingTableEntryCount_start 114 +#define GEN9_3DSTATE_GS_BindingTableEntryCount_start 114 +#define GEN8_3DSTATE_GS_BindingTableEntryCount_start 114 +#define GEN75_3DSTATE_GS_BindingTableEntryCount_start 82 +#define GEN7_3DSTATE_GS_BindingTableEntryCount_start 82 +#define GEN6_3DSTATE_GS_BindingTableEntryCount_start 82 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_BindingTableEntryCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 114; + case 10: return 114; + case 9: return 114; + case 8: return 114; + case 7: + if (devinfo->is_haswell) { + return 82; + } else { + return 82; + } + case 6: return 82; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Command SubType */ + + +#define GEN11_3DSTATE_GS_CommandSubType_bits 2 +#define GEN10_3DSTATE_GS_CommandSubType_bits 2 +#define GEN9_3DSTATE_GS_CommandSubType_bits 2 +#define GEN8_3DSTATE_GS_CommandSubType_bits 2 +#define GEN75_3DSTATE_GS_CommandSubType_bits 2 +#define GEN7_3DSTATE_GS_CommandSubType_bits 2 +#define GEN6_3DSTATE_GS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_CommandSubType_start 27 +#define GEN10_3DSTATE_GS_CommandSubType_start 27 +#define GEN9_3DSTATE_GS_CommandSubType_start 27 +#define GEN8_3DSTATE_GS_CommandSubType_start 27 +#define GEN75_3DSTATE_GS_CommandSubType_start 27 +#define GEN7_3DSTATE_GS_CommandSubType_start 27 +#define GEN6_3DSTATE_GS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Command Type */ + + +#define GEN11_3DSTATE_GS_CommandType_bits 3 +#define GEN10_3DSTATE_GS_CommandType_bits 3 +#define GEN9_3DSTATE_GS_CommandType_bits 3 +#define GEN8_3DSTATE_GS_CommandType_bits 3 +#define GEN75_3DSTATE_GS_CommandType_bits 3 +#define GEN7_3DSTATE_GS_CommandType_bits 3 +#define GEN6_3DSTATE_GS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_CommandType_start 29 +#define GEN10_3DSTATE_GS_CommandType_start 29 +#define GEN9_3DSTATE_GS_CommandType_start 29 +#define GEN8_3DSTATE_GS_CommandType_start 29 +#define GEN75_3DSTATE_GS_CommandType_start 29 +#define GEN7_3DSTATE_GS_CommandType_start 29 +#define GEN6_3DSTATE_GS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Control Data Format */ + + +#define GEN11_3DSTATE_GS_ControlDataFormat_bits 1 +#define GEN10_3DSTATE_GS_ControlDataFormat_bits 1 +#define GEN9_3DSTATE_GS_ControlDataFormat_bits 1 +#define GEN8_3DSTATE_GS_ControlDataFormat_bits 1 +#define GEN75_3DSTATE_GS_ControlDataFormat_bits 1 +#define GEN7_3DSTATE_GS_ControlDataFormat_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_ControlDataFormat_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_ControlDataFormat_start 287 +#define GEN10_3DSTATE_GS_ControlDataFormat_start 287 +#define GEN9_3DSTATE_GS_ControlDataFormat_start 287 +#define GEN8_3DSTATE_GS_ControlDataFormat_start 287 +#define GEN75_3DSTATE_GS_ControlDataFormat_start 223 +#define GEN7_3DSTATE_GS_ControlDataFormat_start 184 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_ControlDataFormat_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 287; + case 10: return 287; + case 9: return 287; + case 8: return 287; + case 7: + if (devinfo->is_haswell) { + return 223; + } else { + return 184; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Control Data Header Size */ + + +#define GEN11_3DSTATE_GS_ControlDataHeaderSize_bits 4 +#define GEN10_3DSTATE_GS_ControlDataHeaderSize_bits 4 +#define GEN9_3DSTATE_GS_ControlDataHeaderSize_bits 4 +#define GEN8_3DSTATE_GS_ControlDataHeaderSize_bits 4 +#define GEN75_3DSTATE_GS_ControlDataHeaderSize_bits 4 +#define GEN7_3DSTATE_GS_ControlDataHeaderSize_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_ControlDataHeaderSize_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_ControlDataHeaderSize_start 244 +#define GEN10_3DSTATE_GS_ControlDataHeaderSize_start 244 +#define GEN9_3DSTATE_GS_ControlDataHeaderSize_start 244 +#define GEN8_3DSTATE_GS_ControlDataHeaderSize_start 244 +#define GEN75_3DSTATE_GS_ControlDataHeaderSize_start 180 +#define GEN7_3DSTATE_GS_ControlDataHeaderSize_start 180 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_ControlDataHeaderSize_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 244; + case 10: return 244; + case 9: return 244; + case 8: return 244; + case 7: + if (devinfo->is_haswell) { + return 180; + } else { + return 180; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::DWord Length */ + + +#define GEN11_3DSTATE_GS_DWordLength_bits 8 +#define GEN10_3DSTATE_GS_DWordLength_bits 8 +#define GEN9_3DSTATE_GS_DWordLength_bits 8 +#define GEN8_3DSTATE_GS_DWordLength_bits 8 +#define GEN75_3DSTATE_GS_DWordLength_bits 8 +#define GEN7_3DSTATE_GS_DWordLength_bits 8 +#define GEN6_3DSTATE_GS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_DWordLength_start 0 +#define GEN10_3DSTATE_GS_DWordLength_start 0 +#define GEN9_3DSTATE_GS_DWordLength_start 0 +#define GEN8_3DSTATE_GS_DWordLength_start 0 +#define GEN75_3DSTATE_GS_DWordLength_start 0 +#define GEN7_3DSTATE_GS_DWordLength_start 0 +#define GEN6_3DSTATE_GS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Default Stream Id */ + + +#define GEN11_3DSTATE_GS_DefaultStreamId_bits 2 +#define GEN10_3DSTATE_GS_DefaultStreamId_bits 2 +#define GEN9_3DSTATE_GS_DefaultStreamId_bits 2 +#define GEN8_3DSTATE_GS_DefaultStreamId_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_DefaultStreamId_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_DefaultStreamId_start 237 +#define GEN10_3DSTATE_GS_DefaultStreamId_start 237 +#define GEN9_3DSTATE_GS_DefaultStreamId_start 237 +#define GEN8_3DSTATE_GS_DefaultStreamId_start 237 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_DefaultStreamId_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 237; + case 10: return 237; + case 9: return 237; + case 8: return 237; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Default StreamID */ + + +#define GEN75_3DSTATE_GS_DefaultStreamID_bits 2 +#define GEN7_3DSTATE_GS_DefaultStreamID_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_DefaultStreamID_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_GS_DefaultStreamID_start 173 +#define GEN7_3DSTATE_GS_DefaultStreamID_start 173 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_DefaultStreamID_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 173; + } else { + return 173; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Discard Adjacency */ + + +#define GEN11_3DSTATE_GS_DiscardAdjacency_bits 1 +#define GEN10_3DSTATE_GS_DiscardAdjacency_bits 1 +#define GEN9_3DSTATE_GS_DiscardAdjacency_bits 1 +#define GEN8_3DSTATE_GS_DiscardAdjacency_bits 1 +#define GEN75_3DSTATE_GS_DiscardAdjacency_bits 1 +#define GEN7_3DSTATE_GS_DiscardAdjacency_bits 1 +#define GEN6_3DSTATE_GS_DiscardAdjacency_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_DiscardAdjacency_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_DiscardAdjacency_start 225 +#define GEN10_3DSTATE_GS_DiscardAdjacency_start 225 +#define GEN9_3DSTATE_GS_DiscardAdjacency_start 225 +#define GEN8_3DSTATE_GS_DiscardAdjacency_start 225 +#define GEN75_3DSTATE_GS_DiscardAdjacency_start 161 +#define GEN7_3DSTATE_GS_DiscardAdjacency_start 161 +#define GEN6_3DSTATE_GS_DiscardAdjacency_start 221 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_DiscardAdjacency_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 225; + case 10: return 225; + case 9: return 225; + case 8: return 225; + case 7: + if (devinfo->is_haswell) { + return 161; + } else { + return 161; + } + case 6: return 221; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Dispatch GRF Start Register For URB Data */ + + +#define GEN11_3DSTATE_GS_DispatchGRFStartRegisterForURBData_bits 4 +#define GEN10_3DSTATE_GS_DispatchGRFStartRegisterForURBData_bits 4 +#define GEN9_3DSTATE_GS_DispatchGRFStartRegisterForURBData_bits 4 +#define GEN8_3DSTATE_GS_DispatchGRFStartRegisterForURBData_bits 4 +#define GEN75_3DSTATE_GS_DispatchGRFStartRegisterForURBData_bits 4 +#define GEN7_3DSTATE_GS_DispatchGRFStartRegisterForURBData_bits 4 +#define GEN6_3DSTATE_GS_DispatchGRFStartRegisterForURBData_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_DispatchGRFStartRegisterForURBData_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_DispatchGRFStartRegisterForURBData_start 192 +#define GEN10_3DSTATE_GS_DispatchGRFStartRegisterForURBData_start 192 +#define GEN9_3DSTATE_GS_DispatchGRFStartRegisterForURBData_start 192 +#define GEN8_3DSTATE_GS_DispatchGRFStartRegisterForURBData_start 192 +#define GEN75_3DSTATE_GS_DispatchGRFStartRegisterForURBData_start 128 +#define GEN7_3DSTATE_GS_DispatchGRFStartRegisterForURBData_start 128 +#define GEN6_3DSTATE_GS_DispatchGRFStartRegisterForURBData_start 128 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_DispatchGRFStartRegisterForURBData_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 192; + case 10: return 192; + case 9: return 192; + case 8: return 192; + case 7: + if (devinfo->is_haswell) { + return 128; + } else { + return 128; + } + case 6: return 128; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Dispatch GRF Start Register For URB Data [5:4] */ + + +#define GEN11_3DSTATE_GS_DispatchGRFStartRegisterForURBData54_bits 2 +#define GEN10_3DSTATE_GS_DispatchGRFStartRegisterForURBData54_bits 2 +#define GEN9_3DSTATE_GS_DispatchGRFStartRegisterForURBData54_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_DispatchGRFStartRegisterForURBData54_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_DispatchGRFStartRegisterForURBData54_start 221 +#define GEN10_3DSTATE_GS_DispatchGRFStartRegisterForURBData54_start 221 +#define GEN9_3DSTATE_GS_DispatchGRFStartRegisterForURBData54_start 221 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_DispatchGRFStartRegisterForURBData54_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 221; + case 10: return 221; + case 9: return 221; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Dispatch Mode */ + + +#define GEN11_3DSTATE_GS_DispatchMode_bits 2 +#define GEN10_3DSTATE_GS_DispatchMode_bits 2 +#define GEN9_3DSTATE_GS_DispatchMode_bits 2 +#define GEN8_3DSTATE_GS_DispatchMode_bits 2 +#define GEN75_3DSTATE_GS_DispatchMode_bits 2 +#define GEN7_3DSTATE_GS_DispatchMode_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_DispatchMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_DispatchMode_start 235 +#define GEN10_3DSTATE_GS_DispatchMode_start 235 +#define GEN9_3DSTATE_GS_DispatchMode_start 235 +#define GEN8_3DSTATE_GS_DispatchMode_start 235 +#define GEN75_3DSTATE_GS_DispatchMode_start 171 +#define GEN7_3DSTATE_GS_DispatchMode_start 171 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_DispatchMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 235; + case 10: return 235; + case 9: return 235; + case 8: return 235; + case 7: + if (devinfo->is_haswell) { + return 171; + } else { + return 171; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Enable */ + + +#define GEN11_3DSTATE_GS_Enable_bits 1 +#define GEN10_3DSTATE_GS_Enable_bits 1 +#define GEN9_3DSTATE_GS_Enable_bits 1 +#define GEN8_3DSTATE_GS_Enable_bits 1 +#define GEN75_3DSTATE_GS_Enable_bits 1 +#define GEN7_3DSTATE_GS_Enable_bits 1 +#define GEN6_3DSTATE_GS_Enable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_Enable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_Enable_start 224 +#define GEN10_3DSTATE_GS_Enable_start 224 +#define GEN9_3DSTATE_GS_Enable_start 224 +#define GEN8_3DSTATE_GS_Enable_start 224 +#define GEN75_3DSTATE_GS_Enable_start 160 +#define GEN7_3DSTATE_GS_Enable_start 160 +#define GEN6_3DSTATE_GS_Enable_start 207 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_Enable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 224; + case 10: return 224; + case 9: return 224; + case 8: return 224; + case 7: + if (devinfo->is_haswell) { + return 160; + } else { + return 160; + } + case 6: return 207; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Expected Vertex Count */ + + +#define GEN11_3DSTATE_GS_ExpectedVertexCount_bits 6 +#define GEN10_3DSTATE_GS_ExpectedVertexCount_bits 6 +#define GEN9_3DSTATE_GS_ExpectedVertexCount_bits 6 +#define GEN8_3DSTATE_GS_ExpectedVertexCount_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_ExpectedVertexCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_ExpectedVertexCount_start 96 +#define GEN10_3DSTATE_GS_ExpectedVertexCount_start 96 +#define GEN9_3DSTATE_GS_ExpectedVertexCount_start 96 +#define GEN8_3DSTATE_GS_ExpectedVertexCount_start 96 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_ExpectedVertexCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 96; + case 10: return 96; + case 9: return 96; + case 8: return 96; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Floating Point Mode */ + + +#define GEN11_3DSTATE_GS_FloatingPointMode_bits 1 +#define GEN10_3DSTATE_GS_FloatingPointMode_bits 1 +#define GEN9_3DSTATE_GS_FloatingPointMode_bits 1 +#define GEN8_3DSTATE_GS_FloatingPointMode_bits 1 +#define GEN75_3DSTATE_GS_FloatingPointMode_bits 1 +#define GEN7_3DSTATE_GS_FloatingPointMode_bits 1 +#define GEN6_3DSTATE_GS_FloatingPointMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_FloatingPointMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_FloatingPointMode_start 112 +#define GEN10_3DSTATE_GS_FloatingPointMode_start 112 +#define GEN9_3DSTATE_GS_FloatingPointMode_start 112 +#define GEN8_3DSTATE_GS_FloatingPointMode_start 112 +#define GEN75_3DSTATE_GS_FloatingPointMode_start 80 +#define GEN7_3DSTATE_GS_FloatingPointMode_start 80 +#define GEN6_3DSTATE_GS_FloatingPointMode_start 80 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_FloatingPointMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 112; + case 10: return 112; + case 9: return 112; + case 8: return 112; + case 7: + if (devinfo->is_haswell) { + return 80; + } else { + return 80; + } + case 6: return 80; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::GS Invocations Increment Value */ + + +#define GEN75_3DSTATE_GS_GSInvocationsIncrementValue_bits 5 +#define GEN7_3DSTATE_GS_GSInvocationsIncrementValue_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_GSInvocationsIncrementValue_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 5; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_GS_GSInvocationsIncrementValue_start 165 +#define GEN7_3DSTATE_GS_GSInvocationsIncrementValue_start 165 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_GSInvocationsIncrementValue_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 165; + } else { + return 165; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::GS accesses UAV */ + + +#define GEN75_3DSTATE_GS_GSaccessesUAV_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_GSaccessesUAV_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_GS_GSaccessesUAV_start 76 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_GSaccessesUAV_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 76; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Hint */ + + +#define GEN11_3DSTATE_GS_Hint_bits 1 +#define GEN10_3DSTATE_GS_Hint_bits 1 +#define GEN9_3DSTATE_GS_Hint_bits 1 +#define GEN8_3DSTATE_GS_Hint_bits 1 +#define GEN75_3DSTATE_GS_Hint_bits 1 +#define GEN7_3DSTATE_GS_Hint_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_Hint_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_Hint_start 227 +#define GEN10_3DSTATE_GS_Hint_start 227 +#define GEN9_3DSTATE_GS_Hint_start 227 +#define GEN8_3DSTATE_GS_Hint_start 227 +#define GEN75_3DSTATE_GS_Hint_start 163 +#define GEN7_3DSTATE_GS_Hint_start 163 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_Hint_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 227; + case 10: return 227; + case 9: return 227; + case 8: return 227; + case 7: + if (devinfo->is_haswell) { + return 163; + } else { + return 163; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Illegal Opcode Exception Enable */ + + +#define GEN11_3DSTATE_GS_IllegalOpcodeExceptionEnable_bits 1 +#define GEN10_3DSTATE_GS_IllegalOpcodeExceptionEnable_bits 1 +#define GEN9_3DSTATE_GS_IllegalOpcodeExceptionEnable_bits 1 +#define GEN8_3DSTATE_GS_IllegalOpcodeExceptionEnable_bits 1 +#define GEN75_3DSTATE_GS_IllegalOpcodeExceptionEnable_bits 1 +#define GEN7_3DSTATE_GS_IllegalOpcodeExceptionEnable_bits 1 +#define GEN6_3DSTATE_GS_IllegalOpcodeExceptionEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_IllegalOpcodeExceptionEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_IllegalOpcodeExceptionEnable_start 109 +#define GEN10_3DSTATE_GS_IllegalOpcodeExceptionEnable_start 109 +#define GEN9_3DSTATE_GS_IllegalOpcodeExceptionEnable_start 109 +#define GEN8_3DSTATE_GS_IllegalOpcodeExceptionEnable_start 109 +#define GEN75_3DSTATE_GS_IllegalOpcodeExceptionEnable_start 77 +#define GEN7_3DSTATE_GS_IllegalOpcodeExceptionEnable_start 77 +#define GEN6_3DSTATE_GS_IllegalOpcodeExceptionEnable_start 77 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_IllegalOpcodeExceptionEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 109; + case 10: return 109; + case 9: return 109; + case 8: return 109; + case 7: + if (devinfo->is_haswell) { + return 77; + } else { + return 77; + } + case 6: return 77; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Include Primitive ID */ + + +#define GEN11_3DSTATE_GS_IncludePrimitiveID_bits 1 +#define GEN10_3DSTATE_GS_IncludePrimitiveID_bits 1 +#define GEN9_3DSTATE_GS_IncludePrimitiveID_bits 1 +#define GEN8_3DSTATE_GS_IncludePrimitiveID_bits 1 +#define GEN75_3DSTATE_GS_IncludePrimitiveID_bits 1 +#define GEN7_3DSTATE_GS_IncludePrimitiveID_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_IncludePrimitiveID_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_IncludePrimitiveID_start 228 +#define GEN10_3DSTATE_GS_IncludePrimitiveID_start 228 +#define GEN9_3DSTATE_GS_IncludePrimitiveID_start 228 +#define GEN8_3DSTATE_GS_IncludePrimitiveID_start 228 +#define GEN75_3DSTATE_GS_IncludePrimitiveID_start 164 +#define GEN7_3DSTATE_GS_IncludePrimitiveID_start 164 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_IncludePrimitiveID_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 228; + case 10: return 228; + case 9: return 228; + case 8: return 228; + case 7: + if (devinfo->is_haswell) { + return 164; + } else { + return 164; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Include Vertex Handles */ + + +#define GEN11_3DSTATE_GS_IncludeVertexHandles_bits 1 +#define GEN10_3DSTATE_GS_IncludeVertexHandles_bits 1 +#define GEN9_3DSTATE_GS_IncludeVertexHandles_bits 1 +#define GEN8_3DSTATE_GS_IncludeVertexHandles_bits 1 +#define GEN75_3DSTATE_GS_IncludeVertexHandles_bits 1 +#define GEN7_3DSTATE_GS_IncludeVertexHandles_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_IncludeVertexHandles_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_IncludeVertexHandles_start 202 +#define GEN10_3DSTATE_GS_IncludeVertexHandles_start 202 +#define GEN9_3DSTATE_GS_IncludeVertexHandles_start 202 +#define GEN8_3DSTATE_GS_IncludeVertexHandles_start 202 +#define GEN75_3DSTATE_GS_IncludeVertexHandles_start 138 +#define GEN7_3DSTATE_GS_IncludeVertexHandles_start 138 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_IncludeVertexHandles_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 202; + case 10: return 202; + case 9: return 202; + case 8: return 202; + case 7: + if (devinfo->is_haswell) { + return 138; + } else { + return 138; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Instance Control */ + + +#define GEN11_3DSTATE_GS_InstanceControl_bits 5 +#define GEN10_3DSTATE_GS_InstanceControl_bits 5 +#define GEN9_3DSTATE_GS_InstanceControl_bits 5 +#define GEN8_3DSTATE_GS_InstanceControl_bits 5 +#define GEN75_3DSTATE_GS_InstanceControl_bits 5 +#define GEN7_3DSTATE_GS_InstanceControl_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_InstanceControl_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 5; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_InstanceControl_start 239 +#define GEN10_3DSTATE_GS_InstanceControl_start 239 +#define GEN9_3DSTATE_GS_InstanceControl_start 239 +#define GEN8_3DSTATE_GS_InstanceControl_start 239 +#define GEN75_3DSTATE_GS_InstanceControl_start 175 +#define GEN7_3DSTATE_GS_InstanceControl_start 175 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_InstanceControl_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 239; + case 10: return 239; + case 9: return 239; + case 8: return 239; + case 7: + if (devinfo->is_haswell) { + return 175; + } else { + return 175; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Invocations Increment Value */ + + +#define GEN11_3DSTATE_GS_InvocationsIncrementValue_bits 5 +#define GEN10_3DSTATE_GS_InvocationsIncrementValue_bits 5 +#define GEN9_3DSTATE_GS_InvocationsIncrementValue_bits 5 +#define GEN8_3DSTATE_GS_InvocationsIncrementValue_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_InvocationsIncrementValue_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_InvocationsIncrementValue_start 229 +#define GEN10_3DSTATE_GS_InvocationsIncrementValue_start 229 +#define GEN9_3DSTATE_GS_InvocationsIncrementValue_start 229 +#define GEN8_3DSTATE_GS_InvocationsIncrementValue_start 229 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_InvocationsIncrementValue_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 229; + case 10: return 229; + case 9: return 229; + case 8: return 229; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Kernel Start Pointer */ + + +#define GEN11_3DSTATE_GS_KernelStartPointer_bits 58 +#define GEN10_3DSTATE_GS_KernelStartPointer_bits 58 +#define GEN9_3DSTATE_GS_KernelStartPointer_bits 58 +#define GEN8_3DSTATE_GS_KernelStartPointer_bits 58 +#define GEN75_3DSTATE_GS_KernelStartPointer_bits 26 +#define GEN7_3DSTATE_GS_KernelStartPointer_bits 26 +#define GEN6_3DSTATE_GS_KernelStartPointer_bits 26 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_KernelStartPointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 58; + case 10: return 58; + case 9: return 58; + case 8: return 58; + case 7: + if (devinfo->is_haswell) { + return 26; + } else { + return 26; + } + case 6: return 26; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_KernelStartPointer_start 38 +#define GEN10_3DSTATE_GS_KernelStartPointer_start 38 +#define GEN9_3DSTATE_GS_KernelStartPointer_start 38 +#define GEN8_3DSTATE_GS_KernelStartPointer_start 38 +#define GEN75_3DSTATE_GS_KernelStartPointer_start 38 +#define GEN7_3DSTATE_GS_KernelStartPointer_start 38 +#define GEN6_3DSTATE_GS_KernelStartPointer_start 38 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_KernelStartPointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 38; + case 10: return 38; + case 9: return 38; + case 8: return 38; + case 7: + if (devinfo->is_haswell) { + return 38; + } else { + return 38; + } + case 6: return 38; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Mask Stack Exception Enable */ + + +#define GEN11_3DSTATE_GS_MaskStackExceptionEnable_bits 1 +#define GEN10_3DSTATE_GS_MaskStackExceptionEnable_bits 1 +#define GEN9_3DSTATE_GS_MaskStackExceptionEnable_bits 1 +#define GEN8_3DSTATE_GS_MaskStackExceptionEnable_bits 1 +#define GEN75_3DSTATE_GS_MaskStackExceptionEnable_bits 1 +#define GEN7_3DSTATE_GS_MaskStackExceptionEnable_bits 1 +#define GEN6_3DSTATE_GS_MaskStackExceptionEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_MaskStackExceptionEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_MaskStackExceptionEnable_start 107 +#define GEN10_3DSTATE_GS_MaskStackExceptionEnable_start 107 +#define GEN9_3DSTATE_GS_MaskStackExceptionEnable_start 107 +#define GEN8_3DSTATE_GS_MaskStackExceptionEnable_start 107 +#define GEN75_3DSTATE_GS_MaskStackExceptionEnable_start 75 +#define GEN7_3DSTATE_GS_MaskStackExceptionEnable_start 75 +#define GEN6_3DSTATE_GS_MaskStackExceptionEnable_start 75 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_MaskStackExceptionEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 107; + case 10: return 107; + case 9: return 107; + case 8: return 107; + case 7: + if (devinfo->is_haswell) { + return 75; + } else { + return 75; + } + case 6: return 75; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Maximum Number of Threads */ + + +#define GEN11_3DSTATE_GS_MaximumNumberofThreads_bits 9 +#define GEN10_3DSTATE_GS_MaximumNumberofThreads_bits 9 +#define GEN9_3DSTATE_GS_MaximumNumberofThreads_bits 9 +#define GEN8_3DSTATE_GS_MaximumNumberofThreads_bits 8 +#define GEN75_3DSTATE_GS_MaximumNumberofThreads_bits 8 +#define GEN7_3DSTATE_GS_MaximumNumberofThreads_bits 7 +#define GEN6_3DSTATE_GS_MaximumNumberofThreads_bits 7 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_MaximumNumberofThreads_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 9; + case 10: return 9; + case 9: return 9; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 7; + } + case 6: return 7; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_MaximumNumberofThreads_start 256 +#define GEN10_3DSTATE_GS_MaximumNumberofThreads_start 256 +#define GEN9_3DSTATE_GS_MaximumNumberofThreads_start 256 +#define GEN8_3DSTATE_GS_MaximumNumberofThreads_start 248 +#define GEN75_3DSTATE_GS_MaximumNumberofThreads_start 184 +#define GEN7_3DSTATE_GS_MaximumNumberofThreads_start 185 +#define GEN6_3DSTATE_GS_MaximumNumberofThreads_start 185 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_MaximumNumberofThreads_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 256; + case 10: return 256; + case 9: return 256; + case 8: return 248; + case 7: + if (devinfo->is_haswell) { + return 184; + } else { + return 185; + } + case 6: return 185; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Output Topology */ + + +#define GEN11_3DSTATE_GS_OutputTopology_bits 6 +#define GEN10_3DSTATE_GS_OutputTopology_bits 6 +#define GEN9_3DSTATE_GS_OutputTopology_bits 6 +#define GEN8_3DSTATE_GS_OutputTopology_bits 6 +#define GEN75_3DSTATE_GS_OutputTopology_bits 6 +#define GEN7_3DSTATE_GS_OutputTopology_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_OutputTopology_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_OutputTopology_start 209 +#define GEN10_3DSTATE_GS_OutputTopology_start 209 +#define GEN9_3DSTATE_GS_OutputTopology_start 209 +#define GEN8_3DSTATE_GS_OutputTopology_start 209 +#define GEN75_3DSTATE_GS_OutputTopology_start 145 +#define GEN7_3DSTATE_GS_OutputTopology_start 145 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_OutputTopology_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 209; + case 10: return 209; + case 9: return 209; + case 8: return 209; + case 7: + if (devinfo->is_haswell) { + return 145; + } else { + return 145; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Output Vertex Size */ + + +#define GEN11_3DSTATE_GS_OutputVertexSize_bits 6 +#define GEN10_3DSTATE_GS_OutputVertexSize_bits 6 +#define GEN9_3DSTATE_GS_OutputVertexSize_bits 6 +#define GEN8_3DSTATE_GS_OutputVertexSize_bits 6 +#define GEN75_3DSTATE_GS_OutputVertexSize_bits 6 +#define GEN7_3DSTATE_GS_OutputVertexSize_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_OutputVertexSize_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_OutputVertexSize_start 215 +#define GEN10_3DSTATE_GS_OutputVertexSize_start 215 +#define GEN9_3DSTATE_GS_OutputVertexSize_start 215 +#define GEN8_3DSTATE_GS_OutputVertexSize_start 215 +#define GEN75_3DSTATE_GS_OutputVertexSize_start 151 +#define GEN7_3DSTATE_GS_OutputVertexSize_start 151 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_OutputVertexSize_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 215; + case 10: return 215; + case 9: return 215; + case 8: return 215; + case 7: + if (devinfo->is_haswell) { + return 151; + } else { + return 151; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Per-Thread Scratch Space */ + + +#define GEN11_3DSTATE_GS_PerThreadScratchSpace_bits 4 +#define GEN10_3DSTATE_GS_PerThreadScratchSpace_bits 4 +#define GEN9_3DSTATE_GS_PerThreadScratchSpace_bits 4 +#define GEN8_3DSTATE_GS_PerThreadScratchSpace_bits 4 +#define GEN75_3DSTATE_GS_PerThreadScratchSpace_bits 4 +#define GEN7_3DSTATE_GS_PerThreadScratchSpace_bits 4 +#define GEN6_3DSTATE_GS_PerThreadScratchSpace_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_PerThreadScratchSpace_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_PerThreadScratchSpace_start 128 +#define GEN10_3DSTATE_GS_PerThreadScratchSpace_start 128 +#define GEN9_3DSTATE_GS_PerThreadScratchSpace_start 128 +#define GEN8_3DSTATE_GS_PerThreadScratchSpace_start 128 +#define GEN75_3DSTATE_GS_PerThreadScratchSpace_start 96 +#define GEN7_3DSTATE_GS_PerThreadScratchSpace_start 96 +#define GEN6_3DSTATE_GS_PerThreadScratchSpace_start 96 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_PerThreadScratchSpace_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 128; + case 10: return 128; + case 9: return 128; + case 8: return 128; + case 7: + if (devinfo->is_haswell) { + return 96; + } else { + return 96; + } + case 6: return 96; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Rendering Enabled */ + + +#define GEN6_3DSTATE_GS_RenderingEnabled_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_RenderingEnabled_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_GS_RenderingEnabled_start 168 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_RenderingEnabled_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 168; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Reorder Mode */ + + +#define GEN11_3DSTATE_GS_ReorderMode_bits 1 +#define GEN10_3DSTATE_GS_ReorderMode_bits 1 +#define GEN9_3DSTATE_GS_ReorderMode_bits 1 +#define GEN8_3DSTATE_GS_ReorderMode_bits 1 +#define GEN75_3DSTATE_GS_ReorderMode_bits 1 +#define GEN7_3DSTATE_GS_ReorderMode_bits 1 +#define GEN6_3DSTATE_GS_ReorderMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_ReorderMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_ReorderMode_start 226 +#define GEN10_3DSTATE_GS_ReorderMode_start 226 +#define GEN9_3DSTATE_GS_ReorderMode_start 226 +#define GEN8_3DSTATE_GS_ReorderMode_start 226 +#define GEN75_3DSTATE_GS_ReorderMode_start 162 +#define GEN7_3DSTATE_GS_ReorderMode_start 162 +#define GEN6_3DSTATE_GS_ReorderMode_start 222 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_ReorderMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 226; + case 10: return 226; + case 9: return 226; + case 8: return 226; + case 7: + if (devinfo->is_haswell) { + return 162; + } else { + return 162; + } + case 6: return 222; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::SO Statistics Enable */ + + +#define GEN6_3DSTATE_GS_SOStatisticsEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_SOStatisticsEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_GS_SOStatisticsEnable_start 169 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_SOStatisticsEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 169; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::SVBI Payload Enable */ + + +#define GEN6_3DSTATE_GS_SVBIPayloadEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_SVBIPayloadEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_GS_SVBIPayloadEnable_start 220 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_SVBIPayloadEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 220; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::SVBI Post-Increment Enable */ + + +#define GEN6_3DSTATE_GS_SVBIPostIncrementEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_SVBIPostIncrementEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_GS_SVBIPostIncrementEnable_start 219 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_SVBIPostIncrementEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 219; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::SVBI Post-Increment Value */ + + +#define GEN6_3DSTATE_GS_SVBIPostIncrementValue_bits 10 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_SVBIPostIncrementValue_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 10; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_GS_SVBIPostIncrementValue_start 208 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_SVBIPostIncrementValue_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 208; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Sampler Count */ + + +#define GEN11_3DSTATE_GS_SamplerCount_bits 3 +#define GEN10_3DSTATE_GS_SamplerCount_bits 3 +#define GEN9_3DSTATE_GS_SamplerCount_bits 3 +#define GEN8_3DSTATE_GS_SamplerCount_bits 3 +#define GEN75_3DSTATE_GS_SamplerCount_bits 3 +#define GEN7_3DSTATE_GS_SamplerCount_bits 3 +#define GEN6_3DSTATE_GS_SamplerCount_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_SamplerCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_SamplerCount_start 123 +#define GEN10_3DSTATE_GS_SamplerCount_start 123 +#define GEN9_3DSTATE_GS_SamplerCount_start 123 +#define GEN8_3DSTATE_GS_SamplerCount_start 123 +#define GEN75_3DSTATE_GS_SamplerCount_start 91 +#define GEN7_3DSTATE_GS_SamplerCount_start 91 +#define GEN6_3DSTATE_GS_SamplerCount_start 91 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_SamplerCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 123; + case 10: return 123; + case 9: return 123; + case 8: return 123; + case 7: + if (devinfo->is_haswell) { + return 91; + } else { + return 91; + } + case 6: return 91; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Scratch Space Base Pointer */ + + +#define GEN11_3DSTATE_GS_ScratchSpaceBasePointer_bits 54 +#define GEN10_3DSTATE_GS_ScratchSpaceBasePointer_bits 54 +#define GEN9_3DSTATE_GS_ScratchSpaceBasePointer_bits 54 +#define GEN8_3DSTATE_GS_ScratchSpaceBasePointer_bits 54 +#define GEN75_3DSTATE_GS_ScratchSpaceBasePointer_bits 22 +#define GEN7_3DSTATE_GS_ScratchSpaceBasePointer_bits 22 +#define GEN6_3DSTATE_GS_ScratchSpaceBasePointer_bits 22 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_ScratchSpaceBasePointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 54; + case 10: return 54; + case 9: return 54; + case 8: return 54; + case 7: + if (devinfo->is_haswell) { + return 22; + } else { + return 22; + } + case 6: return 22; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_ScratchSpaceBasePointer_start 138 +#define GEN10_3DSTATE_GS_ScratchSpaceBasePointer_start 138 +#define GEN9_3DSTATE_GS_ScratchSpaceBasePointer_start 138 +#define GEN8_3DSTATE_GS_ScratchSpaceBasePointer_start 138 +#define GEN75_3DSTATE_GS_ScratchSpaceBasePointer_start 106 +#define GEN7_3DSTATE_GS_ScratchSpaceBasePointer_start 106 +#define GEN6_3DSTATE_GS_ScratchSpaceBasePointer_start 106 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_ScratchSpaceBasePointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 138; + case 10: return 138; + case 9: return 138; + case 8: return 138; + case 7: + if (devinfo->is_haswell) { + return 106; + } else { + return 106; + } + case 6: return 106; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Semaphore Handle */ + + +#define GEN75_3DSTATE_GS_SemaphoreHandle_bits 13 +#define GEN7_3DSTATE_GS_SemaphoreHandle_bits 12 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_SemaphoreHandle_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 13; + } else { + return 12; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_GS_SemaphoreHandle_start 192 +#define GEN7_3DSTATE_GS_SemaphoreHandle_start 192 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_SemaphoreHandle_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 192; + } else { + return 192; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Single Program Flow */ + + +#define GEN11_3DSTATE_GS_SingleProgramFlow_bits 1 +#define GEN10_3DSTATE_GS_SingleProgramFlow_bits 1 +#define GEN9_3DSTATE_GS_SingleProgramFlow_bits 1 +#define GEN8_3DSTATE_GS_SingleProgramFlow_bits 1 +#define GEN75_3DSTATE_GS_SingleProgramFlow_bits 1 +#define GEN7_3DSTATE_GS_SingleProgramFlow_bits 1 +#define GEN6_3DSTATE_GS_SingleProgramFlow_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_SingleProgramFlow_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_SingleProgramFlow_start 127 +#define GEN10_3DSTATE_GS_SingleProgramFlow_start 127 +#define GEN9_3DSTATE_GS_SingleProgramFlow_start 127 +#define GEN8_3DSTATE_GS_SingleProgramFlow_start 127 +#define GEN75_3DSTATE_GS_SingleProgramFlow_start 95 +#define GEN7_3DSTATE_GS_SingleProgramFlow_start 95 +#define GEN6_3DSTATE_GS_SingleProgramFlow_start 95 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_SingleProgramFlow_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 127; + case 10: return 127; + case 9: return 127; + case 8: return 127; + case 7: + if (devinfo->is_haswell) { + return 95; + } else { + return 95; + } + case 6: return 95; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Software Exception Enable */ + + +#define GEN11_3DSTATE_GS_SoftwareExceptionEnable_bits 1 +#define GEN10_3DSTATE_GS_SoftwareExceptionEnable_bits 1 +#define GEN9_3DSTATE_GS_SoftwareExceptionEnable_bits 1 +#define GEN8_3DSTATE_GS_SoftwareExceptionEnable_bits 1 +#define GEN75_3DSTATE_GS_SoftwareExceptionEnable_bits 1 +#define GEN7_3DSTATE_GS_SoftwareExceptionEnable_bits 1 +#define GEN6_3DSTATE_GS_SoftwareExceptionEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_SoftwareExceptionEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_SoftwareExceptionEnable_start 103 +#define GEN10_3DSTATE_GS_SoftwareExceptionEnable_start 103 +#define GEN9_3DSTATE_GS_SoftwareExceptionEnable_start 103 +#define GEN8_3DSTATE_GS_SoftwareExceptionEnable_start 103 +#define GEN75_3DSTATE_GS_SoftwareExceptionEnable_start 71 +#define GEN7_3DSTATE_GS_SoftwareExceptionEnable_start 71 +#define GEN6_3DSTATE_GS_SoftwareExceptionEnable_start 71 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_SoftwareExceptionEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 103; + case 10: return 103; + case 9: return 103; + case 8: return 103; + case 7: + if (devinfo->is_haswell) { + return 71; + } else { + return 71; + } + case 6: return 71; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Static Output */ + + +#define GEN11_3DSTATE_GS_StaticOutput_bits 1 +#define GEN10_3DSTATE_GS_StaticOutput_bits 1 +#define GEN9_3DSTATE_GS_StaticOutput_bits 1 +#define GEN8_3DSTATE_GS_StaticOutput_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_StaticOutput_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_StaticOutput_start 286 +#define GEN10_3DSTATE_GS_StaticOutput_start 286 +#define GEN9_3DSTATE_GS_StaticOutput_start 286 +#define GEN8_3DSTATE_GS_StaticOutput_start 286 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_StaticOutput_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 286; + case 10: return 286; + case 9: return 286; + case 8: return 286; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Static Output Vertex Count */ + + +#define GEN11_3DSTATE_GS_StaticOutputVertexCount_bits 11 +#define GEN10_3DSTATE_GS_StaticOutputVertexCount_bits 11 +#define GEN9_3DSTATE_GS_StaticOutputVertexCount_bits 11 +#define GEN8_3DSTATE_GS_StaticOutputVertexCount_bits 11 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_StaticOutputVertexCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_StaticOutputVertexCount_start 272 +#define GEN10_3DSTATE_GS_StaticOutputVertexCount_start 272 +#define GEN9_3DSTATE_GS_StaticOutputVertexCount_start 272 +#define GEN8_3DSTATE_GS_StaticOutputVertexCount_start 272 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_StaticOutputVertexCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 272; + case 10: return 272; + case 9: return 272; + case 8: return 272; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Statistics Enable */ + + +#define GEN11_3DSTATE_GS_StatisticsEnable_bits 1 +#define GEN10_3DSTATE_GS_StatisticsEnable_bits 1 +#define GEN9_3DSTATE_GS_StatisticsEnable_bits 1 +#define GEN8_3DSTATE_GS_StatisticsEnable_bits 1 +#define GEN75_3DSTATE_GS_StatisticsEnable_bits 1 +#define GEN7_3DSTATE_GS_StatisticsEnable_bits 1 +#define GEN6_3DSTATE_GS_StatisticsEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_StatisticsEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_StatisticsEnable_start 234 +#define GEN10_3DSTATE_GS_StatisticsEnable_start 234 +#define GEN9_3DSTATE_GS_StatisticsEnable_start 234 +#define GEN8_3DSTATE_GS_StatisticsEnable_start 234 +#define GEN75_3DSTATE_GS_StatisticsEnable_start 170 +#define GEN7_3DSTATE_GS_StatisticsEnable_start 170 +#define GEN6_3DSTATE_GS_StatisticsEnable_start 170 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_StatisticsEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 234; + case 10: return 234; + case 9: return 234; + case 8: return 234; + case 7: + if (devinfo->is_haswell) { + return 170; + } else { + return 170; + } + case 6: return 170; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Thread Dispatch Priority */ + + +#define GEN11_3DSTATE_GS_ThreadDispatchPriority_bits 1 +#define GEN10_3DSTATE_GS_ThreadDispatchPriority_bits 1 +#define GEN9_3DSTATE_GS_ThreadDispatchPriority_bits 1 +#define GEN8_3DSTATE_GS_ThreadDispatchPriority_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_ThreadDispatchPriority_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_ThreadDispatchPriority_start 113 +#define GEN10_3DSTATE_GS_ThreadDispatchPriority_start 113 +#define GEN9_3DSTATE_GS_ThreadDispatchPriority_start 113 +#define GEN8_3DSTATE_GS_ThreadDispatchPriority_start 113 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_ThreadDispatchPriority_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 113; + case 10: return 113; + case 9: return 113; + case 8: return 113; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Thread Priority */ + + +#define GEN75_3DSTATE_GS_ThreadPriority_bits 1 +#define GEN7_3DSTATE_GS_ThreadPriority_bits 1 +#define GEN6_3DSTATE_GS_ThreadPriority_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_ThreadPriority_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_GS_ThreadPriority_start 81 +#define GEN7_3DSTATE_GS_ThreadPriority_start 81 +#define GEN6_3DSTATE_GS_ThreadPriority_start 81 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_ThreadPriority_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 81; + } else { + return 81; + } + case 6: return 81; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::User Clip Distance Clip Test Enable Bitmask */ + + +#define GEN11_3DSTATE_GS_UserClipDistanceClipTestEnableBitmask_bits 8 +#define GEN10_3DSTATE_GS_UserClipDistanceClipTestEnableBitmask_bits 8 +#define GEN9_3DSTATE_GS_UserClipDistanceClipTestEnableBitmask_bits 8 +#define GEN8_3DSTATE_GS_UserClipDistanceClipTestEnableBitmask_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_UserClipDistanceClipTestEnableBitmask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_UserClipDistanceClipTestEnableBitmask_start 296 +#define GEN10_3DSTATE_GS_UserClipDistanceClipTestEnableBitmask_start 296 +#define GEN9_3DSTATE_GS_UserClipDistanceClipTestEnableBitmask_start 296 +#define GEN8_3DSTATE_GS_UserClipDistanceClipTestEnableBitmask_start 296 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_UserClipDistanceClipTestEnableBitmask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 296; + case 10: return 296; + case 9: return 296; + case 8: return 296; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::User Clip Distance Cull Test Enable Bitmask */ + + +#define GEN11_3DSTATE_GS_UserClipDistanceCullTestEnableBitmask_bits 8 +#define GEN10_3DSTATE_GS_UserClipDistanceCullTestEnableBitmask_bits 8 +#define GEN9_3DSTATE_GS_UserClipDistanceCullTestEnableBitmask_bits 8 +#define GEN8_3DSTATE_GS_UserClipDistanceCullTestEnableBitmask_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_UserClipDistanceCullTestEnableBitmask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_UserClipDistanceCullTestEnableBitmask_start 288 +#define GEN10_3DSTATE_GS_UserClipDistanceCullTestEnableBitmask_start 288 +#define GEN9_3DSTATE_GS_UserClipDistanceCullTestEnableBitmask_start 288 +#define GEN8_3DSTATE_GS_UserClipDistanceCullTestEnableBitmask_start 288 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_UserClipDistanceCullTestEnableBitmask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 288; + case 10: return 288; + case 9: return 288; + case 8: return 288; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Vector Mask Enable */ + + +#define GEN11_3DSTATE_GS_VectorMaskEnable_bits 1 +#define GEN10_3DSTATE_GS_VectorMaskEnable_bits 1 +#define GEN9_3DSTATE_GS_VectorMaskEnable_bits 1 +#define GEN8_3DSTATE_GS_VectorMaskEnable_bits 1 +#define GEN75_3DSTATE_GS_VectorMaskEnable_bits 1 +#define GEN7_3DSTATE_GS_VectorMaskEnable_bits 1 +#define GEN6_3DSTATE_GS_VectorMaskEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_VectorMaskEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_VectorMaskEnable_start 126 +#define GEN10_3DSTATE_GS_VectorMaskEnable_start 126 +#define GEN9_3DSTATE_GS_VectorMaskEnable_start 126 +#define GEN8_3DSTATE_GS_VectorMaskEnable_start 126 +#define GEN75_3DSTATE_GS_VectorMaskEnable_start 94 +#define GEN7_3DSTATE_GS_VectorMaskEnable_start 94 +#define GEN6_3DSTATE_GS_VectorMaskEnable_start 94 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_VectorMaskEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 126; + case 10: return 126; + case 9: return 126; + case 8: return 126; + case 7: + if (devinfo->is_haswell) { + return 94; + } else { + return 94; + } + case 6: return 94; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Vertex URB Entry Output Length */ + + +#define GEN11_3DSTATE_GS_VertexURBEntryOutputLength_bits 5 +#define GEN10_3DSTATE_GS_VertexURBEntryOutputLength_bits 5 +#define GEN9_3DSTATE_GS_VertexURBEntryOutputLength_bits 5 +#define GEN8_3DSTATE_GS_VertexURBEntryOutputLength_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_VertexURBEntryOutputLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_VertexURBEntryOutputLength_start 304 +#define GEN10_3DSTATE_GS_VertexURBEntryOutputLength_start 304 +#define GEN9_3DSTATE_GS_VertexURBEntryOutputLength_start 304 +#define GEN8_3DSTATE_GS_VertexURBEntryOutputLength_start 304 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_VertexURBEntryOutputLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 304; + case 10: return 304; + case 9: return 304; + case 8: return 304; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Vertex URB Entry Output Read Offset */ + + +#define GEN11_3DSTATE_GS_VertexURBEntryOutputReadOffset_bits 6 +#define GEN10_3DSTATE_GS_VertexURBEntryOutputReadOffset_bits 6 +#define GEN9_3DSTATE_GS_VertexURBEntryOutputReadOffset_bits 6 +#define GEN8_3DSTATE_GS_VertexURBEntryOutputReadOffset_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_VertexURBEntryOutputReadOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_VertexURBEntryOutputReadOffset_start 309 +#define GEN10_3DSTATE_GS_VertexURBEntryOutputReadOffset_start 309 +#define GEN9_3DSTATE_GS_VertexURBEntryOutputReadOffset_start 309 +#define GEN8_3DSTATE_GS_VertexURBEntryOutputReadOffset_start 309 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_VertexURBEntryOutputReadOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 309; + case 10: return 309; + case 9: return 309; + case 8: return 309; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Vertex URB Entry Read Length */ + + +#define GEN11_3DSTATE_GS_VertexURBEntryReadLength_bits 6 +#define GEN10_3DSTATE_GS_VertexURBEntryReadLength_bits 6 +#define GEN9_3DSTATE_GS_VertexURBEntryReadLength_bits 6 +#define GEN8_3DSTATE_GS_VertexURBEntryReadLength_bits 6 +#define GEN75_3DSTATE_GS_VertexURBEntryReadLength_bits 6 +#define GEN7_3DSTATE_GS_VertexURBEntryReadLength_bits 6 +#define GEN6_3DSTATE_GS_VertexURBEntryReadLength_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_VertexURBEntryReadLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 6; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_VertexURBEntryReadLength_start 203 +#define GEN10_3DSTATE_GS_VertexURBEntryReadLength_start 203 +#define GEN9_3DSTATE_GS_VertexURBEntryReadLength_start 203 +#define GEN8_3DSTATE_GS_VertexURBEntryReadLength_start 203 +#define GEN75_3DSTATE_GS_VertexURBEntryReadLength_start 139 +#define GEN7_3DSTATE_GS_VertexURBEntryReadLength_start 139 +#define GEN6_3DSTATE_GS_VertexURBEntryReadLength_start 139 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_VertexURBEntryReadLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 203; + case 10: return 203; + case 9: return 203; + case 8: return 203; + case 7: + if (devinfo->is_haswell) { + return 139; + } else { + return 139; + } + case 6: return 139; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS::Vertex URB Entry Read Offset */ + + +#define GEN11_3DSTATE_GS_VertexURBEntryReadOffset_bits 6 +#define GEN10_3DSTATE_GS_VertexURBEntryReadOffset_bits 6 +#define GEN9_3DSTATE_GS_VertexURBEntryReadOffset_bits 6 +#define GEN8_3DSTATE_GS_VertexURBEntryReadOffset_bits 6 +#define GEN75_3DSTATE_GS_VertexURBEntryReadOffset_bits 6 +#define GEN7_3DSTATE_GS_VertexURBEntryReadOffset_bits 6 +#define GEN6_3DSTATE_GS_VertexURBEntryReadOffset_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_VertexURBEntryReadOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 6; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_GS_VertexURBEntryReadOffset_start 196 +#define GEN10_3DSTATE_GS_VertexURBEntryReadOffset_start 196 +#define GEN9_3DSTATE_GS_VertexURBEntryReadOffset_start 196 +#define GEN8_3DSTATE_GS_VertexURBEntryReadOffset_start 196 +#define GEN75_3DSTATE_GS_VertexURBEntryReadOffset_start 132 +#define GEN7_3DSTATE_GS_VertexURBEntryReadOffset_start 132 +#define GEN6_3DSTATE_GS_VertexURBEntryReadOffset_start 132 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_VertexURBEntryReadOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 196; + case 10: return 196; + case 9: return 196; + case 8: return 196; + case 7: + if (devinfo->is_haswell) { + return 132; + } else { + return 132; + } + case 6: return 132; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS_SVB_INDEX */ + + +#define GEN6_3DSTATE_GS_SVB_INDEX_length 7 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_SVB_INDEX_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 7; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS_SVB_INDEX::3D Command Opcode */ + + +#define GEN6_3DSTATE_GS_SVB_INDEX_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_SVB_INDEX_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_GS_SVB_INDEX_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_SVB_INDEX_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 24; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS_SVB_INDEX::3D Command Sub Opcode */ + + +#define GEN6_3DSTATE_GS_SVB_INDEX_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_SVB_INDEX_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_GS_SVB_INDEX_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_SVB_INDEX_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS_SVB_INDEX::Command SubType */ + + +#define GEN6_3DSTATE_GS_SVB_INDEX_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_SVB_INDEX_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_GS_SVB_INDEX_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_SVB_INDEX_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS_SVB_INDEX::Command Type */ + + +#define GEN6_3DSTATE_GS_SVB_INDEX_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_SVB_INDEX_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_GS_SVB_INDEX_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_SVB_INDEX_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS_SVB_INDEX::DWord Length */ + + +#define GEN6_3DSTATE_GS_SVB_INDEX_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_SVB_INDEX_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_GS_SVB_INDEX_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_SVB_INDEX_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS_SVB_INDEX::Index Number */ + + +#define GEN6_3DSTATE_GS_SVB_INDEX_IndexNumber_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_SVB_INDEX_IndexNumber_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_GS_SVB_INDEX_IndexNumber_start 61 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_SVB_INDEX_IndexNumber_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 61; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS_SVB_INDEX::Load Internal Vertex Count */ + + +#define GEN6_3DSTATE_GS_SVB_INDEX_LoadInternalVertexCount_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_SVB_INDEX_LoadInternalVertexCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_GS_SVB_INDEX_LoadInternalVertexCount_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_SVB_INDEX_LoadInternalVertexCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS_SVB_INDEX::Maximum Index */ + + +#define GEN6_3DSTATE_GS_SVB_INDEX_MaximumIndex_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_SVB_INDEX_MaximumIndex_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_GS_SVB_INDEX_MaximumIndex_start 96 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_SVB_INDEX_MaximumIndex_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 96; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_GS_SVB_INDEX::Streamed Vertex Buffer Index */ + + +#define GEN6_3DSTATE_GS_SVB_INDEX_StreamedVertexBufferIndex_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_SVB_INDEX_StreamedVertexBufferIndex_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_GS_SVB_INDEX_StreamedVertexBufferIndex_start 64 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_GS_SVB_INDEX_StreamedVertexBufferIndex_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 64; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HIER_DEPTH_BUFFER */ + + +#define GEN11_3DSTATE_HIER_DEPTH_BUFFER_length 5 +#define GEN10_3DSTATE_HIER_DEPTH_BUFFER_length 5 +#define GEN9_3DSTATE_HIER_DEPTH_BUFFER_length 5 +#define GEN8_3DSTATE_HIER_DEPTH_BUFFER_length 5 +#define GEN75_3DSTATE_HIER_DEPTH_BUFFER_length 3 +#define GEN7_3DSTATE_HIER_DEPTH_BUFFER_length 3 +#define GEN6_3DSTATE_HIER_DEPTH_BUFFER_length 3 +#define GEN5_3DSTATE_HIER_DEPTH_BUFFER_length 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HIER_DEPTH_BUFFER_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HIER_DEPTH_BUFFER::3D Command Opcode */ + + +#define GEN11_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_bits 3 +#define GEN6_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_bits 3 +#define GEN5_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_start 24 +#define GEN6_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_start 24 +#define GEN5_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HIER_DEPTH_BUFFER_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 24; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HIER_DEPTH_BUFFER::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN6_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN5_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_start 16 +#define GEN6_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_start 16 +#define GEN5_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HIER_DEPTH_BUFFER_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HIER_DEPTH_BUFFER::Command SubType */ + + +#define GEN11_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_bits 2 +#define GEN10_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_bits 2 +#define GEN9_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_bits 2 +#define GEN8_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_bits 2 +#define GEN75_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_bits 2 +#define GEN7_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_bits 2 +#define GEN6_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_bits 2 +#define GEN5_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_start 27 +#define GEN10_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_start 27 +#define GEN9_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_start 27 +#define GEN8_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_start 27 +#define GEN75_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_start 27 +#define GEN7_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_start 27 +#define GEN6_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_start 27 +#define GEN5_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HIER_DEPTH_BUFFER_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HIER_DEPTH_BUFFER::Command Type */ + + +#define GEN11_3DSTATE_HIER_DEPTH_BUFFER_CommandType_bits 3 +#define GEN10_3DSTATE_HIER_DEPTH_BUFFER_CommandType_bits 3 +#define GEN9_3DSTATE_HIER_DEPTH_BUFFER_CommandType_bits 3 +#define GEN8_3DSTATE_HIER_DEPTH_BUFFER_CommandType_bits 3 +#define GEN75_3DSTATE_HIER_DEPTH_BUFFER_CommandType_bits 3 +#define GEN7_3DSTATE_HIER_DEPTH_BUFFER_CommandType_bits 3 +#define GEN6_3DSTATE_HIER_DEPTH_BUFFER_CommandType_bits 3 +#define GEN5_3DSTATE_HIER_DEPTH_BUFFER_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HIER_DEPTH_BUFFER_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_HIER_DEPTH_BUFFER_CommandType_start 29 +#define GEN10_3DSTATE_HIER_DEPTH_BUFFER_CommandType_start 29 +#define GEN9_3DSTATE_HIER_DEPTH_BUFFER_CommandType_start 29 +#define GEN8_3DSTATE_HIER_DEPTH_BUFFER_CommandType_start 29 +#define GEN75_3DSTATE_HIER_DEPTH_BUFFER_CommandType_start 29 +#define GEN7_3DSTATE_HIER_DEPTH_BUFFER_CommandType_start 29 +#define GEN6_3DSTATE_HIER_DEPTH_BUFFER_CommandType_start 29 +#define GEN5_3DSTATE_HIER_DEPTH_BUFFER_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HIER_DEPTH_BUFFER_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 29; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HIER_DEPTH_BUFFER::DWord Length */ + + +#define GEN11_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_bits 8 +#define GEN10_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_bits 8 +#define GEN9_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_bits 8 +#define GEN8_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_bits 8 +#define GEN75_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_bits 8 +#define GEN7_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_bits 8 +#define GEN6_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_bits 8 +#define GEN5_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_start 0 +#define GEN10_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_start 0 +#define GEN9_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_start 0 +#define GEN8_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_start 0 +#define GEN75_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_start 0 +#define GEN7_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_start 0 +#define GEN6_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_start 0 +#define GEN5_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HIER_DEPTH_BUFFER_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HIER_DEPTH_BUFFER::MOCS */ + + +#define GEN11_3DSTATE_HIER_DEPTH_BUFFER_MOCS_bits 7 +#define GEN10_3DSTATE_HIER_DEPTH_BUFFER_MOCS_bits 7 +#define GEN9_3DSTATE_HIER_DEPTH_BUFFER_MOCS_bits 7 +#define GEN8_3DSTATE_HIER_DEPTH_BUFFER_MOCS_bits 7 +#define GEN75_3DSTATE_HIER_DEPTH_BUFFER_MOCS_bits 4 +#define GEN7_3DSTATE_HIER_DEPTH_BUFFER_MOCS_bits 4 +#define GEN6_3DSTATE_HIER_DEPTH_BUFFER_MOCS_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HIER_DEPTH_BUFFER_MOCS_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_HIER_DEPTH_BUFFER_MOCS_start 57 +#define GEN10_3DSTATE_HIER_DEPTH_BUFFER_MOCS_start 57 +#define GEN9_3DSTATE_HIER_DEPTH_BUFFER_MOCS_start 57 +#define GEN8_3DSTATE_HIER_DEPTH_BUFFER_MOCS_start 57 +#define GEN75_3DSTATE_HIER_DEPTH_BUFFER_MOCS_start 57 +#define GEN7_3DSTATE_HIER_DEPTH_BUFFER_MOCS_start 57 +#define GEN6_3DSTATE_HIER_DEPTH_BUFFER_MOCS_start 57 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HIER_DEPTH_BUFFER_MOCS_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 57; + case 10: return 57; + case 9: return 57; + case 8: return 57; + case 7: + if (devinfo->is_haswell) { + return 57; + } else { + return 57; + } + case 6: return 57; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HIER_DEPTH_BUFFER::Surface Base Address */ + + +#define GEN11_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_bits 64 +#define GEN10_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_bits 64 +#define GEN9_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_bits 64 +#define GEN8_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_bits 64 +#define GEN75_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_bits 32 +#define GEN7_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_bits 32 +#define GEN6_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_bits 32 +#define GEN5_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start 64 +#define GEN10_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start 64 +#define GEN9_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start 64 +#define GEN8_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start 64 +#define GEN75_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start 64 +#define GEN7_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start 64 +#define GEN6_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start 64 +#define GEN5_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start 64 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HIER_DEPTH_BUFFER_SurfaceBaseAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 64; + case 5: return 64; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HIER_DEPTH_BUFFER::Surface Pitch */ + + +#define GEN11_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits 17 +#define GEN10_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits 17 +#define GEN9_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits 17 +#define GEN8_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits 17 +#define GEN75_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits 17 +#define GEN7_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits 17 +#define GEN6_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits 17 +#define GEN5_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits 17 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 17; + case 10: return 17; + case 9: return 17; + case 8: return 17; + case 7: + if (devinfo->is_haswell) { + return 17; + } else { + return 17; + } + case 6: return 17; + case 5: return 17; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_start 32 +#define GEN10_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_start 32 +#define GEN9_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_start 32 +#define GEN8_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_start 32 +#define GEN75_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_start 32 +#define GEN7_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_start 32 +#define GEN6_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_start 32 +#define GEN5_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HIER_DEPTH_BUFFER_SurfacePitch_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HIER_DEPTH_BUFFER::Surface QPitch */ + + +#define GEN11_3DSTATE_HIER_DEPTH_BUFFER_SurfaceQPitch_bits 15 +#define GEN10_3DSTATE_HIER_DEPTH_BUFFER_SurfaceQPitch_bits 15 +#define GEN9_3DSTATE_HIER_DEPTH_BUFFER_SurfaceQPitch_bits 15 +#define GEN8_3DSTATE_HIER_DEPTH_BUFFER_SurfaceQPitch_bits 15 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HIER_DEPTH_BUFFER_SurfaceQPitch_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 15; + case 10: return 15; + case 9: return 15; + case 8: return 15; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_HIER_DEPTH_BUFFER_SurfaceQPitch_start 128 +#define GEN10_3DSTATE_HIER_DEPTH_BUFFER_SurfaceQPitch_start 128 +#define GEN9_3DSTATE_HIER_DEPTH_BUFFER_SurfaceQPitch_start 128 +#define GEN8_3DSTATE_HIER_DEPTH_BUFFER_SurfaceQPitch_start 128 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HIER_DEPTH_BUFFER_SurfaceQPitch_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 128; + case 10: return 128; + case 9: return 128; + case 8: return 128; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HIER_DEPTH_BUFFER::Tiled Resource Mode */ + + +#define GEN11_3DSTATE_HIER_DEPTH_BUFFER_TiledResourceMode_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HIER_DEPTH_BUFFER_TiledResourceMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_HIER_DEPTH_BUFFER_TiledResourceMode_start 55 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HIER_DEPTH_BUFFER_TiledResourceMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 55; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HS */ + + +#define GEN11_3DSTATE_HS_length 9 +#define GEN10_3DSTATE_HS_length 9 +#define GEN9_3DSTATE_HS_length 9 +#define GEN8_3DSTATE_HS_length 9 +#define GEN75_3DSTATE_HS_length 7 +#define GEN7_3DSTATE_HS_length 7 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 9; + case 10: return 9; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 7; + } else { + return 7; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HS::3D Command Opcode */ + + +#define GEN11_3DSTATE_HS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_HS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_HS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_HS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_HS_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_HS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_HS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_HS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_HS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_HS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_HS_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_HS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_HS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_HS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_HS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_HS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_HS_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_HS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_HS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_HS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_HS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_HS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_HS_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_HS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HS::Accesses UAV */ + + +#define GEN11_3DSTATE_HS_AccessesUAV_bits 1 +#define GEN10_3DSTATE_HS_AccessesUAV_bits 1 +#define GEN9_3DSTATE_HS_AccessesUAV_bits 1 +#define GEN8_3DSTATE_HS_AccessesUAV_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_AccessesUAV_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_HS_AccessesUAV_start 249 +#define GEN10_3DSTATE_HS_AccessesUAV_start 249 +#define GEN9_3DSTATE_HS_AccessesUAV_start 249 +#define GEN8_3DSTATE_HS_AccessesUAV_start 249 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_AccessesUAV_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 249; + case 10: return 249; + case 9: return 249; + case 8: return 249; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HS::Binding Table Entry Count */ + + +#define GEN11_3DSTATE_HS_BindingTableEntryCount_bits 8 +#define GEN10_3DSTATE_HS_BindingTableEntryCount_bits 8 +#define GEN9_3DSTATE_HS_BindingTableEntryCount_bits 8 +#define GEN8_3DSTATE_HS_BindingTableEntryCount_bits 8 +#define GEN75_3DSTATE_HS_BindingTableEntryCount_bits 8 +#define GEN7_3DSTATE_HS_BindingTableEntryCount_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_BindingTableEntryCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_HS_BindingTableEntryCount_start 50 +#define GEN10_3DSTATE_HS_BindingTableEntryCount_start 50 +#define GEN9_3DSTATE_HS_BindingTableEntryCount_start 50 +#define GEN8_3DSTATE_HS_BindingTableEntryCount_start 50 +#define GEN75_3DSTATE_HS_BindingTableEntryCount_start 50 +#define GEN7_3DSTATE_HS_BindingTableEntryCount_start 50 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_BindingTableEntryCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 50; + case 10: return 50; + case 9: return 50; + case 8: return 50; + case 7: + if (devinfo->is_haswell) { + return 50; + } else { + return 50; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HS::Command SubType */ + + +#define GEN11_3DSTATE_HS_CommandSubType_bits 2 +#define GEN10_3DSTATE_HS_CommandSubType_bits 2 +#define GEN9_3DSTATE_HS_CommandSubType_bits 2 +#define GEN8_3DSTATE_HS_CommandSubType_bits 2 +#define GEN75_3DSTATE_HS_CommandSubType_bits 2 +#define GEN7_3DSTATE_HS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_HS_CommandSubType_start 27 +#define GEN10_3DSTATE_HS_CommandSubType_start 27 +#define GEN9_3DSTATE_HS_CommandSubType_start 27 +#define GEN8_3DSTATE_HS_CommandSubType_start 27 +#define GEN75_3DSTATE_HS_CommandSubType_start 27 +#define GEN7_3DSTATE_HS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HS::Command Type */ + + +#define GEN11_3DSTATE_HS_CommandType_bits 3 +#define GEN10_3DSTATE_HS_CommandType_bits 3 +#define GEN9_3DSTATE_HS_CommandType_bits 3 +#define GEN8_3DSTATE_HS_CommandType_bits 3 +#define GEN75_3DSTATE_HS_CommandType_bits 3 +#define GEN7_3DSTATE_HS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_HS_CommandType_start 29 +#define GEN10_3DSTATE_HS_CommandType_start 29 +#define GEN9_3DSTATE_HS_CommandType_start 29 +#define GEN8_3DSTATE_HS_CommandType_start 29 +#define GEN75_3DSTATE_HS_CommandType_start 29 +#define GEN7_3DSTATE_HS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HS::DWord Length */ + + +#define GEN11_3DSTATE_HS_DWordLength_bits 8 +#define GEN10_3DSTATE_HS_DWordLength_bits 8 +#define GEN9_3DSTATE_HS_DWordLength_bits 8 +#define GEN8_3DSTATE_HS_DWordLength_bits 8 +#define GEN75_3DSTATE_HS_DWordLength_bits 8 +#define GEN7_3DSTATE_HS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_HS_DWordLength_start 0 +#define GEN10_3DSTATE_HS_DWordLength_start 0 +#define GEN9_3DSTATE_HS_DWordLength_start 0 +#define GEN8_3DSTATE_HS_DWordLength_start 0 +#define GEN75_3DSTATE_HS_DWordLength_start 0 +#define GEN7_3DSTATE_HS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HS::Dispatch GRF Start Register For URB Data */ + + +#define GEN11_3DSTATE_HS_DispatchGRFStartRegisterForURBData_bits 5 +#define GEN10_3DSTATE_HS_DispatchGRFStartRegisterForURBData_bits 5 +#define GEN9_3DSTATE_HS_DispatchGRFStartRegisterForURBData_bits 5 +#define GEN8_3DSTATE_HS_DispatchGRFStartRegisterForURBData_bits 5 +#define GEN75_3DSTATE_HS_DispatchGRFStartRegisterForURBData_bits 5 +#define GEN7_3DSTATE_HS_DispatchGRFStartRegisterForURBData_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_DispatchGRFStartRegisterForURBData_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 5; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_HS_DispatchGRFStartRegisterForURBData_start 243 +#define GEN10_3DSTATE_HS_DispatchGRFStartRegisterForURBData_start 243 +#define GEN9_3DSTATE_HS_DispatchGRFStartRegisterForURBData_start 243 +#define GEN8_3DSTATE_HS_DispatchGRFStartRegisterForURBData_start 243 +#define GEN75_3DSTATE_HS_DispatchGRFStartRegisterForURBData_start 179 +#define GEN7_3DSTATE_HS_DispatchGRFStartRegisterForURBData_start 179 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_DispatchGRFStartRegisterForURBData_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 243; + case 10: return 243; + case 9: return 243; + case 8: return 243; + case 7: + if (devinfo->is_haswell) { + return 179; + } else { + return 179; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HS::Dispatch GRF Start Register For URB Data [5] */ + + +#define GEN11_3DSTATE_HS_DispatchGRFStartRegisterForURBData5_bits 1 +#define GEN10_3DSTATE_HS_DispatchGRFStartRegisterForURBData5_bits 1 +#define GEN9_3DSTATE_HS_DispatchGRFStartRegisterForURBData5_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_DispatchGRFStartRegisterForURBData5_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_HS_DispatchGRFStartRegisterForURBData5_start 252 +#define GEN10_3DSTATE_HS_DispatchGRFStartRegisterForURBData5_start 252 +#define GEN9_3DSTATE_HS_DispatchGRFStartRegisterForURBData5_start 252 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_DispatchGRFStartRegisterForURBData5_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 252; + case 10: return 252; + case 9: return 252; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HS::Dispatch Mode */ + + +#define GEN11_3DSTATE_HS_DispatchMode_bits 2 +#define GEN10_3DSTATE_HS_DispatchMode_bits 2 +#define GEN9_3DSTATE_HS_DispatchMode_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_DispatchMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_HS_DispatchMode_start 241 +#define GEN10_3DSTATE_HS_DispatchMode_start 241 +#define GEN9_3DSTATE_HS_DispatchMode_start 241 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_DispatchMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 241; + case 10: return 241; + case 9: return 241; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HS::Enable */ + + +#define GEN11_3DSTATE_HS_Enable_bits 1 +#define GEN10_3DSTATE_HS_Enable_bits 1 +#define GEN9_3DSTATE_HS_Enable_bits 1 +#define GEN8_3DSTATE_HS_Enable_bits 1 +#define GEN75_3DSTATE_HS_Enable_bits 1 +#define GEN7_3DSTATE_HS_Enable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_Enable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_HS_Enable_start 95 +#define GEN10_3DSTATE_HS_Enable_start 95 +#define GEN9_3DSTATE_HS_Enable_start 95 +#define GEN8_3DSTATE_HS_Enable_start 95 +#define GEN75_3DSTATE_HS_Enable_start 95 +#define GEN7_3DSTATE_HS_Enable_start 95 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_Enable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 95; + case 10: return 95; + case 9: return 95; + case 8: return 95; + case 7: + if (devinfo->is_haswell) { + return 95; + } else { + return 95; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HS::Floating Point Mode */ + + +#define GEN11_3DSTATE_HS_FloatingPointMode_bits 1 +#define GEN10_3DSTATE_HS_FloatingPointMode_bits 1 +#define GEN9_3DSTATE_HS_FloatingPointMode_bits 1 +#define GEN8_3DSTATE_HS_FloatingPointMode_bits 1 +#define GEN75_3DSTATE_HS_FloatingPointMode_bits 1 +#define GEN7_3DSTATE_HS_FloatingPointMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_FloatingPointMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_HS_FloatingPointMode_start 48 +#define GEN10_3DSTATE_HS_FloatingPointMode_start 48 +#define GEN9_3DSTATE_HS_FloatingPointMode_start 48 +#define GEN8_3DSTATE_HS_FloatingPointMode_start 48 +#define GEN75_3DSTATE_HS_FloatingPointMode_start 48 +#define GEN7_3DSTATE_HS_FloatingPointMode_start 48 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_FloatingPointMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 48; + case 7: + if (devinfo->is_haswell) { + return 48; + } else { + return 48; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HS::HS accesses UAV */ + + +#define GEN75_3DSTATE_HS_HSaccessesUAV_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_HSaccessesUAV_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_HS_HSaccessesUAV_start 185 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_HSaccessesUAV_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 185; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HS::Illegal Opcode Exception Enable */ + + +#define GEN11_3DSTATE_HS_IllegalOpcodeExceptionEnable_bits 1 +#define GEN10_3DSTATE_HS_IllegalOpcodeExceptionEnable_bits 1 +#define GEN9_3DSTATE_HS_IllegalOpcodeExceptionEnable_bits 1 +#define GEN8_3DSTATE_HS_IllegalOpcodeExceptionEnable_bits 1 +#define GEN75_3DSTATE_HS_IllegalOpcodeExceptionEnable_bits 1 +#define GEN7_3DSTATE_HS_IllegalOpcodeExceptionEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_IllegalOpcodeExceptionEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_HS_IllegalOpcodeExceptionEnable_start 45 +#define GEN10_3DSTATE_HS_IllegalOpcodeExceptionEnable_start 45 +#define GEN9_3DSTATE_HS_IllegalOpcodeExceptionEnable_start 45 +#define GEN8_3DSTATE_HS_IllegalOpcodeExceptionEnable_start 45 +#define GEN75_3DSTATE_HS_IllegalOpcodeExceptionEnable_start 45 +#define GEN7_3DSTATE_HS_IllegalOpcodeExceptionEnable_start 45 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_IllegalOpcodeExceptionEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 45; + case 10: return 45; + case 9: return 45; + case 8: return 45; + case 7: + if (devinfo->is_haswell) { + return 45; + } else { + return 45; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HS::Include Primitive ID */ + + +#define GEN11_3DSTATE_HS_IncludePrimitiveID_bits 1 +#define GEN10_3DSTATE_HS_IncludePrimitiveID_bits 1 +#define GEN9_3DSTATE_HS_IncludePrimitiveID_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_IncludePrimitiveID_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_HS_IncludePrimitiveID_start 224 +#define GEN10_3DSTATE_HS_IncludePrimitiveID_start 224 +#define GEN9_3DSTATE_HS_IncludePrimitiveID_start 224 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_IncludePrimitiveID_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 224; + case 10: return 224; + case 9: return 224; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HS::Include Vertex Handles */ + + +#define GEN11_3DSTATE_HS_IncludeVertexHandles_bits 1 +#define GEN10_3DSTATE_HS_IncludeVertexHandles_bits 1 +#define GEN9_3DSTATE_HS_IncludeVertexHandles_bits 1 +#define GEN8_3DSTATE_HS_IncludeVertexHandles_bits 1 +#define GEN75_3DSTATE_HS_IncludeVertexHandles_bits 1 +#define GEN7_3DSTATE_HS_IncludeVertexHandles_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_IncludeVertexHandles_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_HS_IncludeVertexHandles_start 248 +#define GEN10_3DSTATE_HS_IncludeVertexHandles_start 248 +#define GEN9_3DSTATE_HS_IncludeVertexHandles_start 248 +#define GEN8_3DSTATE_HS_IncludeVertexHandles_start 248 +#define GEN75_3DSTATE_HS_IncludeVertexHandles_start 184 +#define GEN7_3DSTATE_HS_IncludeVertexHandles_start 184 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_IncludeVertexHandles_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 248; + case 10: return 248; + case 9: return 248; + case 8: return 248; + case 7: + if (devinfo->is_haswell) { + return 184; + } else { + return 184; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HS::Instance Count */ + + +#define GEN11_3DSTATE_HS_InstanceCount_bits 4 +#define GEN10_3DSTATE_HS_InstanceCount_bits 4 +#define GEN9_3DSTATE_HS_InstanceCount_bits 4 +#define GEN8_3DSTATE_HS_InstanceCount_bits 4 +#define GEN75_3DSTATE_HS_InstanceCount_bits 4 +#define GEN7_3DSTATE_HS_InstanceCount_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_InstanceCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_HS_InstanceCount_start 64 +#define GEN10_3DSTATE_HS_InstanceCount_start 64 +#define GEN9_3DSTATE_HS_InstanceCount_start 64 +#define GEN8_3DSTATE_HS_InstanceCount_start 64 +#define GEN75_3DSTATE_HS_InstanceCount_start 64 +#define GEN7_3DSTATE_HS_InstanceCount_start 64 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_InstanceCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HS::Kernel Start Pointer */ + + +#define GEN11_3DSTATE_HS_KernelStartPointer_bits 58 +#define GEN10_3DSTATE_HS_KernelStartPointer_bits 58 +#define GEN9_3DSTATE_HS_KernelStartPointer_bits 58 +#define GEN8_3DSTATE_HS_KernelStartPointer_bits 58 +#define GEN75_3DSTATE_HS_KernelStartPointer_bits 26 +#define GEN7_3DSTATE_HS_KernelStartPointer_bits 26 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_KernelStartPointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 58; + case 10: return 58; + case 9: return 58; + case 8: return 58; + case 7: + if (devinfo->is_haswell) { + return 26; + } else { + return 26; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_HS_KernelStartPointer_start 102 +#define GEN10_3DSTATE_HS_KernelStartPointer_start 102 +#define GEN9_3DSTATE_HS_KernelStartPointer_start 102 +#define GEN8_3DSTATE_HS_KernelStartPointer_start 102 +#define GEN75_3DSTATE_HS_KernelStartPointer_start 102 +#define GEN7_3DSTATE_HS_KernelStartPointer_start 102 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_KernelStartPointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 102; + case 10: return 102; + case 9: return 102; + case 8: return 102; + case 7: + if (devinfo->is_haswell) { + return 102; + } else { + return 102; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HS::Maximum Number of Threads */ + + +#define GEN11_3DSTATE_HS_MaximumNumberofThreads_bits 9 +#define GEN10_3DSTATE_HS_MaximumNumberofThreads_bits 9 +#define GEN9_3DSTATE_HS_MaximumNumberofThreads_bits 9 +#define GEN8_3DSTATE_HS_MaximumNumberofThreads_bits 9 +#define GEN75_3DSTATE_HS_MaximumNumberofThreads_bits 8 +#define GEN7_3DSTATE_HS_MaximumNumberofThreads_bits 7 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_MaximumNumberofThreads_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 9; + case 10: return 9; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 7; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_HS_MaximumNumberofThreads_start 72 +#define GEN10_3DSTATE_HS_MaximumNumberofThreads_start 72 +#define GEN9_3DSTATE_HS_MaximumNumberofThreads_start 72 +#define GEN8_3DSTATE_HS_MaximumNumberofThreads_start 72 +#define GEN75_3DSTATE_HS_MaximumNumberofThreads_start 32 +#define GEN7_3DSTATE_HS_MaximumNumberofThreads_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_MaximumNumberofThreads_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 72; + case 10: return 72; + case 9: return 72; + case 8: return 72; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HS::Per-Thread Scratch Space */ + + +#define GEN11_3DSTATE_HS_PerThreadScratchSpace_bits 4 +#define GEN10_3DSTATE_HS_PerThreadScratchSpace_bits 4 +#define GEN9_3DSTATE_HS_PerThreadScratchSpace_bits 4 +#define GEN8_3DSTATE_HS_PerThreadScratchSpace_bits 4 +#define GEN75_3DSTATE_HS_PerThreadScratchSpace_bits 4 +#define GEN7_3DSTATE_HS_PerThreadScratchSpace_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_PerThreadScratchSpace_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_HS_PerThreadScratchSpace_start 160 +#define GEN10_3DSTATE_HS_PerThreadScratchSpace_start 160 +#define GEN9_3DSTATE_HS_PerThreadScratchSpace_start 160 +#define GEN8_3DSTATE_HS_PerThreadScratchSpace_start 160 +#define GEN75_3DSTATE_HS_PerThreadScratchSpace_start 128 +#define GEN7_3DSTATE_HS_PerThreadScratchSpace_start 128 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_PerThreadScratchSpace_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 160; + case 10: return 160; + case 9: return 160; + case 8: return 160; + case 7: + if (devinfo->is_haswell) { + return 128; + } else { + return 128; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HS::Sampler Count */ + + +#define GEN11_3DSTATE_HS_SamplerCount_bits 3 +#define GEN10_3DSTATE_HS_SamplerCount_bits 3 +#define GEN9_3DSTATE_HS_SamplerCount_bits 3 +#define GEN8_3DSTATE_HS_SamplerCount_bits 3 +#define GEN75_3DSTATE_HS_SamplerCount_bits 3 +#define GEN7_3DSTATE_HS_SamplerCount_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_SamplerCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_HS_SamplerCount_start 59 +#define GEN10_3DSTATE_HS_SamplerCount_start 59 +#define GEN9_3DSTATE_HS_SamplerCount_start 59 +#define GEN8_3DSTATE_HS_SamplerCount_start 59 +#define GEN75_3DSTATE_HS_SamplerCount_start 59 +#define GEN7_3DSTATE_HS_SamplerCount_start 59 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_SamplerCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 59; + case 10: return 59; + case 9: return 59; + case 8: return 59; + case 7: + if (devinfo->is_haswell) { + return 59; + } else { + return 59; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HS::Scratch Space Base Pointer */ + + +#define GEN11_3DSTATE_HS_ScratchSpaceBasePointer_bits 54 +#define GEN10_3DSTATE_HS_ScratchSpaceBasePointer_bits 54 +#define GEN9_3DSTATE_HS_ScratchSpaceBasePointer_bits 54 +#define GEN8_3DSTATE_HS_ScratchSpaceBasePointer_bits 54 +#define GEN75_3DSTATE_HS_ScratchSpaceBasePointer_bits 22 +#define GEN7_3DSTATE_HS_ScratchSpaceBasePointer_bits 22 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_ScratchSpaceBasePointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 54; + case 10: return 54; + case 9: return 54; + case 8: return 54; + case 7: + if (devinfo->is_haswell) { + return 22; + } else { + return 22; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_HS_ScratchSpaceBasePointer_start 170 +#define GEN10_3DSTATE_HS_ScratchSpaceBasePointer_start 170 +#define GEN9_3DSTATE_HS_ScratchSpaceBasePointer_start 170 +#define GEN8_3DSTATE_HS_ScratchSpaceBasePointer_start 170 +#define GEN75_3DSTATE_HS_ScratchSpaceBasePointer_start 138 +#define GEN7_3DSTATE_HS_ScratchSpaceBasePointer_start 138 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_ScratchSpaceBasePointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 170; + case 10: return 170; + case 9: return 170; + case 8: return 170; + case 7: + if (devinfo->is_haswell) { + return 138; + } else { + return 138; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HS::Semaphore Handle */ + + +#define GEN75_3DSTATE_HS_SemaphoreHandle_bits 13 +#define GEN7_3DSTATE_HS_SemaphoreHandle_bits 12 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_SemaphoreHandle_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 13; + } else { + return 12; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_HS_SemaphoreHandle_start 192 +#define GEN7_3DSTATE_HS_SemaphoreHandle_start 192 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_SemaphoreHandle_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 192; + } else { + return 192; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HS::Single Program Flow */ + + +#define GEN11_3DSTATE_HS_SingleProgramFlow_bits 1 +#define GEN10_3DSTATE_HS_SingleProgramFlow_bits 1 +#define GEN9_3DSTATE_HS_SingleProgramFlow_bits 1 +#define GEN8_3DSTATE_HS_SingleProgramFlow_bits 1 +#define GEN75_3DSTATE_HS_SingleProgramFlow_bits 1 +#define GEN7_3DSTATE_HS_SingleProgramFlow_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_SingleProgramFlow_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_HS_SingleProgramFlow_start 251 +#define GEN10_3DSTATE_HS_SingleProgramFlow_start 251 +#define GEN9_3DSTATE_HS_SingleProgramFlow_start 251 +#define GEN8_3DSTATE_HS_SingleProgramFlow_start 251 +#define GEN75_3DSTATE_HS_SingleProgramFlow_start 187 +#define GEN7_3DSTATE_HS_SingleProgramFlow_start 187 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_SingleProgramFlow_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 251; + case 10: return 251; + case 9: return 251; + case 8: return 251; + case 7: + if (devinfo->is_haswell) { + return 187; + } else { + return 187; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HS::Software Exception Enable */ + + +#define GEN11_3DSTATE_HS_SoftwareExceptionEnable_bits 1 +#define GEN10_3DSTATE_HS_SoftwareExceptionEnable_bits 1 +#define GEN9_3DSTATE_HS_SoftwareExceptionEnable_bits 1 +#define GEN8_3DSTATE_HS_SoftwareExceptionEnable_bits 1 +#define GEN75_3DSTATE_HS_SoftwareExceptionEnable_bits 1 +#define GEN7_3DSTATE_HS_SoftwareExceptionEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_SoftwareExceptionEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_HS_SoftwareExceptionEnable_start 44 +#define GEN10_3DSTATE_HS_SoftwareExceptionEnable_start 44 +#define GEN9_3DSTATE_HS_SoftwareExceptionEnable_start 44 +#define GEN8_3DSTATE_HS_SoftwareExceptionEnable_start 44 +#define GEN75_3DSTATE_HS_SoftwareExceptionEnable_start 44 +#define GEN7_3DSTATE_HS_SoftwareExceptionEnable_start 39 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_SoftwareExceptionEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 44; + case 10: return 44; + case 9: return 44; + case 8: return 44; + case 7: + if (devinfo->is_haswell) { + return 44; + } else { + return 39; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HS::Statistics Enable */ + + +#define GEN11_3DSTATE_HS_StatisticsEnable_bits 1 +#define GEN10_3DSTATE_HS_StatisticsEnable_bits 1 +#define GEN9_3DSTATE_HS_StatisticsEnable_bits 1 +#define GEN8_3DSTATE_HS_StatisticsEnable_bits 1 +#define GEN75_3DSTATE_HS_StatisticsEnable_bits 1 +#define GEN7_3DSTATE_HS_StatisticsEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_StatisticsEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_HS_StatisticsEnable_start 93 +#define GEN10_3DSTATE_HS_StatisticsEnable_start 93 +#define GEN9_3DSTATE_HS_StatisticsEnable_start 93 +#define GEN8_3DSTATE_HS_StatisticsEnable_start 93 +#define GEN75_3DSTATE_HS_StatisticsEnable_start 93 +#define GEN7_3DSTATE_HS_StatisticsEnable_start 93 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_StatisticsEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 93; + case 10: return 93; + case 9: return 93; + case 8: return 93; + case 7: + if (devinfo->is_haswell) { + return 93; + } else { + return 93; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HS::Thread Dispatch Priority */ + + +#define GEN11_3DSTATE_HS_ThreadDispatchPriority_bits 1 +#define GEN10_3DSTATE_HS_ThreadDispatchPriority_bits 1 +#define GEN9_3DSTATE_HS_ThreadDispatchPriority_bits 1 +#define GEN8_3DSTATE_HS_ThreadDispatchPriority_bits 1 +#define GEN75_3DSTATE_HS_ThreadDispatchPriority_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_ThreadDispatchPriority_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_HS_ThreadDispatchPriority_start 49 +#define GEN10_3DSTATE_HS_ThreadDispatchPriority_start 49 +#define GEN9_3DSTATE_HS_ThreadDispatchPriority_start 49 +#define GEN8_3DSTATE_HS_ThreadDispatchPriority_start 49 +#define GEN75_3DSTATE_HS_ThreadDispatchPriority_start 49 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_ThreadDispatchPriority_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 49; + case 10: return 49; + case 9: return 49; + case 8: return 49; + case 7: + if (devinfo->is_haswell) { + return 49; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HS::Vector Mask Enable */ + + +#define GEN11_3DSTATE_HS_VectorMaskEnable_bits 1 +#define GEN10_3DSTATE_HS_VectorMaskEnable_bits 1 +#define GEN9_3DSTATE_HS_VectorMaskEnable_bits 1 +#define GEN8_3DSTATE_HS_VectorMaskEnable_bits 1 +#define GEN75_3DSTATE_HS_VectorMaskEnable_bits 1 +#define GEN7_3DSTATE_HS_VectorMaskEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_VectorMaskEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_HS_VectorMaskEnable_start 250 +#define GEN10_3DSTATE_HS_VectorMaskEnable_start 250 +#define GEN9_3DSTATE_HS_VectorMaskEnable_start 250 +#define GEN8_3DSTATE_HS_VectorMaskEnable_start 250 +#define GEN75_3DSTATE_HS_VectorMaskEnable_start 186 +#define GEN7_3DSTATE_HS_VectorMaskEnable_start 186 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_VectorMaskEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 250; + case 10: return 250; + case 9: return 250; + case 8: return 250; + case 7: + if (devinfo->is_haswell) { + return 186; + } else { + return 186; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HS::Vertex URB Entry Read Length */ + + +#define GEN11_3DSTATE_HS_VertexURBEntryReadLength_bits 6 +#define GEN10_3DSTATE_HS_VertexURBEntryReadLength_bits 6 +#define GEN9_3DSTATE_HS_VertexURBEntryReadLength_bits 6 +#define GEN8_3DSTATE_HS_VertexURBEntryReadLength_bits 6 +#define GEN75_3DSTATE_HS_VertexURBEntryReadLength_bits 6 +#define GEN7_3DSTATE_HS_VertexURBEntryReadLength_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_VertexURBEntryReadLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_HS_VertexURBEntryReadLength_start 235 +#define GEN10_3DSTATE_HS_VertexURBEntryReadLength_start 235 +#define GEN9_3DSTATE_HS_VertexURBEntryReadLength_start 235 +#define GEN8_3DSTATE_HS_VertexURBEntryReadLength_start 235 +#define GEN75_3DSTATE_HS_VertexURBEntryReadLength_start 171 +#define GEN7_3DSTATE_HS_VertexURBEntryReadLength_start 171 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_VertexURBEntryReadLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 235; + case 10: return 235; + case 9: return 235; + case 8: return 235; + case 7: + if (devinfo->is_haswell) { + return 171; + } else { + return 171; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_HS::Vertex URB Entry Read Offset */ + + +#define GEN11_3DSTATE_HS_VertexURBEntryReadOffset_bits 6 +#define GEN10_3DSTATE_HS_VertexURBEntryReadOffset_bits 6 +#define GEN9_3DSTATE_HS_VertexURBEntryReadOffset_bits 6 +#define GEN8_3DSTATE_HS_VertexURBEntryReadOffset_bits 6 +#define GEN75_3DSTATE_HS_VertexURBEntryReadOffset_bits 6 +#define GEN7_3DSTATE_HS_VertexURBEntryReadOffset_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_VertexURBEntryReadOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_HS_VertexURBEntryReadOffset_start 228 +#define GEN10_3DSTATE_HS_VertexURBEntryReadOffset_start 228 +#define GEN9_3DSTATE_HS_VertexURBEntryReadOffset_start 228 +#define GEN8_3DSTATE_HS_VertexURBEntryReadOffset_start 228 +#define GEN75_3DSTATE_HS_VertexURBEntryReadOffset_start 164 +#define GEN7_3DSTATE_HS_VertexURBEntryReadOffset_start 164 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_HS_VertexURBEntryReadOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 228; + case 10: return 228; + case 9: return 228; + case 8: return 228; + case 7: + if (devinfo->is_haswell) { + return 164; + } else { + return 164; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_INDEX_BUFFER */ + + +#define GEN11_3DSTATE_INDEX_BUFFER_length 5 +#define GEN10_3DSTATE_INDEX_BUFFER_length 5 +#define GEN9_3DSTATE_INDEX_BUFFER_length 5 +#define GEN8_3DSTATE_INDEX_BUFFER_length 5 +#define GEN75_3DSTATE_INDEX_BUFFER_length 3 +#define GEN7_3DSTATE_INDEX_BUFFER_length 3 +#define GEN6_3DSTATE_INDEX_BUFFER_length 3 +#define GEN5_3DSTATE_INDEX_BUFFER_length 3 +#define GEN45_3DSTATE_INDEX_BUFFER_length 3 +#define GEN4_3DSTATE_INDEX_BUFFER_length 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_INDEX_BUFFER_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_INDEX_BUFFER::3D Command Opcode */ + + +#define GEN11_3DSTATE_INDEX_BUFFER_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_INDEX_BUFFER_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_INDEX_BUFFER_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_INDEX_BUFFER_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_INDEX_BUFFER_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_INDEX_BUFFER_3DCommandOpcode_bits 3 +#define GEN6_3DSTATE_INDEX_BUFFER_3DCommandOpcode_bits 3 +#define GEN5_3DSTATE_INDEX_BUFFER_3DCommandOpcode_bits 3 +#define GEN45_3DSTATE_INDEX_BUFFER_3DCommandOpcode_bits 3 +#define GEN4_3DSTATE_INDEX_BUFFER_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_INDEX_BUFFER_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_INDEX_BUFFER_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_INDEX_BUFFER_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_INDEX_BUFFER_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_INDEX_BUFFER_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_INDEX_BUFFER_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_INDEX_BUFFER_3DCommandOpcode_start 24 +#define GEN6_3DSTATE_INDEX_BUFFER_3DCommandOpcode_start 24 +#define GEN5_3DSTATE_INDEX_BUFFER_3DCommandOpcode_start 24 +#define GEN45_3DSTATE_INDEX_BUFFER_3DCommandOpcode_start 24 +#define GEN4_3DSTATE_INDEX_BUFFER_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_INDEX_BUFFER_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 24; + case 4: + if (devinfo->is_g4x) { + return 24; + } else { + return 24; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_INDEX_BUFFER::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN6_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN5_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN45_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN4_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_start 16 +#define GEN6_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_start 16 +#define GEN5_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_start 16 +#define GEN45_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_start 16 +#define GEN4_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_INDEX_BUFFER_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_INDEX_BUFFER::Buffer Ending Address */ + + +#define GEN75_3DSTATE_INDEX_BUFFER_BufferEndingAddress_bits 32 +#define GEN7_3DSTATE_INDEX_BUFFER_BufferEndingAddress_bits 32 +#define GEN6_3DSTATE_INDEX_BUFFER_BufferEndingAddress_bits 32 +#define GEN5_3DSTATE_INDEX_BUFFER_BufferEndingAddress_bits 32 +#define GEN45_3DSTATE_INDEX_BUFFER_BufferEndingAddress_bits 32 +#define GEN4_3DSTATE_INDEX_BUFFER_BufferEndingAddress_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_INDEX_BUFFER_BufferEndingAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_INDEX_BUFFER_BufferEndingAddress_start 64 +#define GEN7_3DSTATE_INDEX_BUFFER_BufferEndingAddress_start 64 +#define GEN6_3DSTATE_INDEX_BUFFER_BufferEndingAddress_start 64 +#define GEN5_3DSTATE_INDEX_BUFFER_BufferEndingAddress_start 64 +#define GEN45_3DSTATE_INDEX_BUFFER_BufferEndingAddress_start 64 +#define GEN4_3DSTATE_INDEX_BUFFER_BufferEndingAddress_start 64 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_INDEX_BUFFER_BufferEndingAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 64; + case 5: return 64; + case 4: + if (devinfo->is_g4x) { + return 64; + } else { + return 64; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_INDEX_BUFFER::Buffer Size */ + + +#define GEN11_3DSTATE_INDEX_BUFFER_BufferSize_bits 32 +#define GEN10_3DSTATE_INDEX_BUFFER_BufferSize_bits 32 +#define GEN9_3DSTATE_INDEX_BUFFER_BufferSize_bits 32 +#define GEN8_3DSTATE_INDEX_BUFFER_BufferSize_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_INDEX_BUFFER_BufferSize_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_INDEX_BUFFER_BufferSize_start 128 +#define GEN10_3DSTATE_INDEX_BUFFER_BufferSize_start 128 +#define GEN9_3DSTATE_INDEX_BUFFER_BufferSize_start 128 +#define GEN8_3DSTATE_INDEX_BUFFER_BufferSize_start 128 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_INDEX_BUFFER_BufferSize_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 128; + case 10: return 128; + case 9: return 128; + case 8: return 128; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_INDEX_BUFFER::Buffer Starting Address */ + + +#define GEN11_3DSTATE_INDEX_BUFFER_BufferStartingAddress_bits 64 +#define GEN10_3DSTATE_INDEX_BUFFER_BufferStartingAddress_bits 64 +#define GEN9_3DSTATE_INDEX_BUFFER_BufferStartingAddress_bits 64 +#define GEN8_3DSTATE_INDEX_BUFFER_BufferStartingAddress_bits 64 +#define GEN75_3DSTATE_INDEX_BUFFER_BufferStartingAddress_bits 32 +#define GEN7_3DSTATE_INDEX_BUFFER_BufferStartingAddress_bits 32 +#define GEN6_3DSTATE_INDEX_BUFFER_BufferStartingAddress_bits 32 +#define GEN5_3DSTATE_INDEX_BUFFER_BufferStartingAddress_bits 32 +#define GEN45_3DSTATE_INDEX_BUFFER_BufferStartingAddress_bits 32 +#define GEN4_3DSTATE_INDEX_BUFFER_BufferStartingAddress_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_INDEX_BUFFER_BufferStartingAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_INDEX_BUFFER_BufferStartingAddress_start 64 +#define GEN10_3DSTATE_INDEX_BUFFER_BufferStartingAddress_start 64 +#define GEN9_3DSTATE_INDEX_BUFFER_BufferStartingAddress_start 64 +#define GEN8_3DSTATE_INDEX_BUFFER_BufferStartingAddress_start 64 +#define GEN75_3DSTATE_INDEX_BUFFER_BufferStartingAddress_start 32 +#define GEN7_3DSTATE_INDEX_BUFFER_BufferStartingAddress_start 32 +#define GEN6_3DSTATE_INDEX_BUFFER_BufferStartingAddress_start 32 +#define GEN5_3DSTATE_INDEX_BUFFER_BufferStartingAddress_start 32 +#define GEN45_3DSTATE_INDEX_BUFFER_BufferStartingAddress_start 32 +#define GEN4_3DSTATE_INDEX_BUFFER_BufferStartingAddress_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_INDEX_BUFFER_BufferStartingAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_INDEX_BUFFER::Command SubType */ + + +#define GEN11_3DSTATE_INDEX_BUFFER_CommandSubType_bits 2 +#define GEN10_3DSTATE_INDEX_BUFFER_CommandSubType_bits 2 +#define GEN9_3DSTATE_INDEX_BUFFER_CommandSubType_bits 2 +#define GEN8_3DSTATE_INDEX_BUFFER_CommandSubType_bits 2 +#define GEN75_3DSTATE_INDEX_BUFFER_CommandSubType_bits 2 +#define GEN7_3DSTATE_INDEX_BUFFER_CommandSubType_bits 2 +#define GEN6_3DSTATE_INDEX_BUFFER_CommandSubType_bits 2 +#define GEN5_3DSTATE_INDEX_BUFFER_CommandSubType_bits 2 +#define GEN45_3DSTATE_INDEX_BUFFER_CommandSubType_bits 2 +#define GEN4_3DSTATE_INDEX_BUFFER_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_INDEX_BUFFER_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_INDEX_BUFFER_CommandSubType_start 27 +#define GEN10_3DSTATE_INDEX_BUFFER_CommandSubType_start 27 +#define GEN9_3DSTATE_INDEX_BUFFER_CommandSubType_start 27 +#define GEN8_3DSTATE_INDEX_BUFFER_CommandSubType_start 27 +#define GEN75_3DSTATE_INDEX_BUFFER_CommandSubType_start 27 +#define GEN7_3DSTATE_INDEX_BUFFER_CommandSubType_start 27 +#define GEN6_3DSTATE_INDEX_BUFFER_CommandSubType_start 27 +#define GEN5_3DSTATE_INDEX_BUFFER_CommandSubType_start 27 +#define GEN45_3DSTATE_INDEX_BUFFER_CommandSubType_start 27 +#define GEN4_3DSTATE_INDEX_BUFFER_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_INDEX_BUFFER_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_INDEX_BUFFER::Command Type */ + + +#define GEN11_3DSTATE_INDEX_BUFFER_CommandType_bits 3 +#define GEN10_3DSTATE_INDEX_BUFFER_CommandType_bits 3 +#define GEN9_3DSTATE_INDEX_BUFFER_CommandType_bits 3 +#define GEN8_3DSTATE_INDEX_BUFFER_CommandType_bits 3 +#define GEN75_3DSTATE_INDEX_BUFFER_CommandType_bits 3 +#define GEN7_3DSTATE_INDEX_BUFFER_CommandType_bits 3 +#define GEN6_3DSTATE_INDEX_BUFFER_CommandType_bits 3 +#define GEN5_3DSTATE_INDEX_BUFFER_CommandType_bits 3 +#define GEN45_3DSTATE_INDEX_BUFFER_CommandType_bits 3 +#define GEN4_3DSTATE_INDEX_BUFFER_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_INDEX_BUFFER_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_INDEX_BUFFER_CommandType_start 29 +#define GEN10_3DSTATE_INDEX_BUFFER_CommandType_start 29 +#define GEN9_3DSTATE_INDEX_BUFFER_CommandType_start 29 +#define GEN8_3DSTATE_INDEX_BUFFER_CommandType_start 29 +#define GEN75_3DSTATE_INDEX_BUFFER_CommandType_start 29 +#define GEN7_3DSTATE_INDEX_BUFFER_CommandType_start 29 +#define GEN6_3DSTATE_INDEX_BUFFER_CommandType_start 29 +#define GEN5_3DSTATE_INDEX_BUFFER_CommandType_start 29 +#define GEN45_3DSTATE_INDEX_BUFFER_CommandType_start 29 +#define GEN4_3DSTATE_INDEX_BUFFER_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_INDEX_BUFFER_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 29; + case 4: + if (devinfo->is_g4x) { + return 29; + } else { + return 29; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_INDEX_BUFFER::Cut Index Enable */ + + +#define GEN7_3DSTATE_INDEX_BUFFER_CutIndexEnable_bits 1 +#define GEN6_3DSTATE_INDEX_BUFFER_CutIndexEnable_bits 1 +#define GEN5_3DSTATE_INDEX_BUFFER_CutIndexEnable_bits 1 +#define GEN45_3DSTATE_INDEX_BUFFER_CutIndexEnable_bits 1 +#define GEN4_3DSTATE_INDEX_BUFFER_CutIndexEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_INDEX_BUFFER_CutIndexEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN7_3DSTATE_INDEX_BUFFER_CutIndexEnable_start 10 +#define GEN6_3DSTATE_INDEX_BUFFER_CutIndexEnable_start 10 +#define GEN5_3DSTATE_INDEX_BUFFER_CutIndexEnable_start 10 +#define GEN45_3DSTATE_INDEX_BUFFER_CutIndexEnable_start 10 +#define GEN4_3DSTATE_INDEX_BUFFER_CutIndexEnable_start 10 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_INDEX_BUFFER_CutIndexEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 10; + } + case 6: return 10; + case 5: return 10; + case 4: + if (devinfo->is_g4x) { + return 10; + } else { + return 10; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_INDEX_BUFFER::DWord Length */ + + +#define GEN11_3DSTATE_INDEX_BUFFER_DWordLength_bits 8 +#define GEN10_3DSTATE_INDEX_BUFFER_DWordLength_bits 8 +#define GEN9_3DSTATE_INDEX_BUFFER_DWordLength_bits 8 +#define GEN8_3DSTATE_INDEX_BUFFER_DWordLength_bits 8 +#define GEN75_3DSTATE_INDEX_BUFFER_DWordLength_bits 8 +#define GEN7_3DSTATE_INDEX_BUFFER_DWordLength_bits 8 +#define GEN6_3DSTATE_INDEX_BUFFER_DWordLength_bits 8 +#define GEN5_3DSTATE_INDEX_BUFFER_DWordLength_bits 8 +#define GEN45_3DSTATE_INDEX_BUFFER_DWordLength_bits 8 +#define GEN4_3DSTATE_INDEX_BUFFER_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_INDEX_BUFFER_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_INDEX_BUFFER_DWordLength_start 0 +#define GEN10_3DSTATE_INDEX_BUFFER_DWordLength_start 0 +#define GEN9_3DSTATE_INDEX_BUFFER_DWordLength_start 0 +#define GEN8_3DSTATE_INDEX_BUFFER_DWordLength_start 0 +#define GEN75_3DSTATE_INDEX_BUFFER_DWordLength_start 0 +#define GEN7_3DSTATE_INDEX_BUFFER_DWordLength_start 0 +#define GEN6_3DSTATE_INDEX_BUFFER_DWordLength_start 0 +#define GEN5_3DSTATE_INDEX_BUFFER_DWordLength_start 0 +#define GEN45_3DSTATE_INDEX_BUFFER_DWordLength_start 0 +#define GEN4_3DSTATE_INDEX_BUFFER_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_INDEX_BUFFER_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_INDEX_BUFFER::Index Format */ + + +#define GEN11_3DSTATE_INDEX_BUFFER_IndexFormat_bits 2 +#define GEN10_3DSTATE_INDEX_BUFFER_IndexFormat_bits 2 +#define GEN9_3DSTATE_INDEX_BUFFER_IndexFormat_bits 2 +#define GEN8_3DSTATE_INDEX_BUFFER_IndexFormat_bits 2 +#define GEN75_3DSTATE_INDEX_BUFFER_IndexFormat_bits 2 +#define GEN7_3DSTATE_INDEX_BUFFER_IndexFormat_bits 2 +#define GEN6_3DSTATE_INDEX_BUFFER_IndexFormat_bits 2 +#define GEN5_3DSTATE_INDEX_BUFFER_IndexFormat_bits 2 +#define GEN45_3DSTATE_INDEX_BUFFER_IndexFormat_bits 2 +#define GEN4_3DSTATE_INDEX_BUFFER_IndexFormat_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_INDEX_BUFFER_IndexFormat_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_INDEX_BUFFER_IndexFormat_start 40 +#define GEN10_3DSTATE_INDEX_BUFFER_IndexFormat_start 40 +#define GEN9_3DSTATE_INDEX_BUFFER_IndexFormat_start 40 +#define GEN8_3DSTATE_INDEX_BUFFER_IndexFormat_start 40 +#define GEN75_3DSTATE_INDEX_BUFFER_IndexFormat_start 8 +#define GEN7_3DSTATE_INDEX_BUFFER_IndexFormat_start 8 +#define GEN6_3DSTATE_INDEX_BUFFER_IndexFormat_start 8 +#define GEN5_3DSTATE_INDEX_BUFFER_IndexFormat_start 8 +#define GEN45_3DSTATE_INDEX_BUFFER_IndexFormat_start 8 +#define GEN4_3DSTATE_INDEX_BUFFER_IndexFormat_start 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_INDEX_BUFFER_IndexFormat_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 40; + case 10: return 40; + case 9: return 40; + case 8: return 40; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_INDEX_BUFFER::MOCS */ + + +#define GEN11_3DSTATE_INDEX_BUFFER_MOCS_bits 7 +#define GEN10_3DSTATE_INDEX_BUFFER_MOCS_bits 7 +#define GEN9_3DSTATE_INDEX_BUFFER_MOCS_bits 7 +#define GEN8_3DSTATE_INDEX_BUFFER_MOCS_bits 7 +#define GEN75_3DSTATE_INDEX_BUFFER_MOCS_bits 4 +#define GEN7_3DSTATE_INDEX_BUFFER_MOCS_bits 4 +#define GEN6_3DSTATE_INDEX_BUFFER_MOCS_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_INDEX_BUFFER_MOCS_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_INDEX_BUFFER_MOCS_start 32 +#define GEN10_3DSTATE_INDEX_BUFFER_MOCS_start 32 +#define GEN9_3DSTATE_INDEX_BUFFER_MOCS_start 32 +#define GEN8_3DSTATE_INDEX_BUFFER_MOCS_start 32 +#define GEN75_3DSTATE_INDEX_BUFFER_MOCS_start 12 +#define GEN7_3DSTATE_INDEX_BUFFER_MOCS_start 12 +#define GEN6_3DSTATE_INDEX_BUFFER_MOCS_start 12 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_INDEX_BUFFER_MOCS_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 12; + } else { + return 12; + } + case 6: return 12; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_LINE_STIPPLE */ + + +#define GEN11_3DSTATE_LINE_STIPPLE_length 3 +#define GEN10_3DSTATE_LINE_STIPPLE_length 3 +#define GEN9_3DSTATE_LINE_STIPPLE_length 3 +#define GEN8_3DSTATE_LINE_STIPPLE_length 3 +#define GEN75_3DSTATE_LINE_STIPPLE_length 3 +#define GEN7_3DSTATE_LINE_STIPPLE_length 3 +#define GEN6_3DSTATE_LINE_STIPPLE_length 3 +#define GEN5_3DSTATE_LINE_STIPPLE_length 3 +#define GEN45_3DSTATE_LINE_STIPPLE_length 3 +#define GEN4_3DSTATE_LINE_STIPPLE_length 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_LINE_STIPPLE_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_LINE_STIPPLE::3D Command Opcode */ + + +#define GEN11_3DSTATE_LINE_STIPPLE_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_LINE_STIPPLE_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_LINE_STIPPLE_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_LINE_STIPPLE_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_LINE_STIPPLE_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_LINE_STIPPLE_3DCommandOpcode_bits 3 +#define GEN6_3DSTATE_LINE_STIPPLE_3DCommandOpcode_bits 3 +#define GEN5_3DSTATE_LINE_STIPPLE_3DCommandOpcode_bits 3 +#define GEN45_3DSTATE_LINE_STIPPLE_3DCommandOpcode_bits 3 +#define GEN4_3DSTATE_LINE_STIPPLE_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_LINE_STIPPLE_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_LINE_STIPPLE_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_LINE_STIPPLE_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_LINE_STIPPLE_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_LINE_STIPPLE_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_LINE_STIPPLE_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_LINE_STIPPLE_3DCommandOpcode_start 24 +#define GEN6_3DSTATE_LINE_STIPPLE_3DCommandOpcode_start 24 +#define GEN5_3DSTATE_LINE_STIPPLE_3DCommandOpcode_start 24 +#define GEN45_3DSTATE_LINE_STIPPLE_3DCommandOpcode_start 24 +#define GEN4_3DSTATE_LINE_STIPPLE_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_LINE_STIPPLE_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 24; + case 4: + if (devinfo->is_g4x) { + return 24; + } else { + return 24; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_LINE_STIPPLE::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_bits 8 +#define GEN6_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_bits 8 +#define GEN5_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_bits 8 +#define GEN45_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_bits 8 +#define GEN4_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_start 16 +#define GEN6_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_start 16 +#define GEN5_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_start 16 +#define GEN45_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_start 16 +#define GEN4_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_LINE_STIPPLE_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_LINE_STIPPLE::Command SubType */ + + +#define GEN11_3DSTATE_LINE_STIPPLE_CommandSubType_bits 2 +#define GEN10_3DSTATE_LINE_STIPPLE_CommandSubType_bits 2 +#define GEN9_3DSTATE_LINE_STIPPLE_CommandSubType_bits 2 +#define GEN8_3DSTATE_LINE_STIPPLE_CommandSubType_bits 2 +#define GEN75_3DSTATE_LINE_STIPPLE_CommandSubType_bits 2 +#define GEN7_3DSTATE_LINE_STIPPLE_CommandSubType_bits 2 +#define GEN6_3DSTATE_LINE_STIPPLE_CommandSubType_bits 2 +#define GEN5_3DSTATE_LINE_STIPPLE_CommandSubType_bits 2 +#define GEN45_3DSTATE_LINE_STIPPLE_CommandSubType_bits 2 +#define GEN4_3DSTATE_LINE_STIPPLE_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_LINE_STIPPLE_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_LINE_STIPPLE_CommandSubType_start 27 +#define GEN10_3DSTATE_LINE_STIPPLE_CommandSubType_start 27 +#define GEN9_3DSTATE_LINE_STIPPLE_CommandSubType_start 27 +#define GEN8_3DSTATE_LINE_STIPPLE_CommandSubType_start 27 +#define GEN75_3DSTATE_LINE_STIPPLE_CommandSubType_start 27 +#define GEN7_3DSTATE_LINE_STIPPLE_CommandSubType_start 27 +#define GEN6_3DSTATE_LINE_STIPPLE_CommandSubType_start 27 +#define GEN5_3DSTATE_LINE_STIPPLE_CommandSubType_start 27 +#define GEN45_3DSTATE_LINE_STIPPLE_CommandSubType_start 27 +#define GEN4_3DSTATE_LINE_STIPPLE_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_LINE_STIPPLE_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_LINE_STIPPLE::Command Type */ + + +#define GEN11_3DSTATE_LINE_STIPPLE_CommandType_bits 3 +#define GEN10_3DSTATE_LINE_STIPPLE_CommandType_bits 3 +#define GEN9_3DSTATE_LINE_STIPPLE_CommandType_bits 3 +#define GEN8_3DSTATE_LINE_STIPPLE_CommandType_bits 3 +#define GEN75_3DSTATE_LINE_STIPPLE_CommandType_bits 3 +#define GEN7_3DSTATE_LINE_STIPPLE_CommandType_bits 3 +#define GEN6_3DSTATE_LINE_STIPPLE_CommandType_bits 3 +#define GEN5_3DSTATE_LINE_STIPPLE_CommandType_bits 3 +#define GEN45_3DSTATE_LINE_STIPPLE_CommandType_bits 3 +#define GEN4_3DSTATE_LINE_STIPPLE_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_LINE_STIPPLE_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_LINE_STIPPLE_CommandType_start 29 +#define GEN10_3DSTATE_LINE_STIPPLE_CommandType_start 29 +#define GEN9_3DSTATE_LINE_STIPPLE_CommandType_start 29 +#define GEN8_3DSTATE_LINE_STIPPLE_CommandType_start 29 +#define GEN75_3DSTATE_LINE_STIPPLE_CommandType_start 29 +#define GEN7_3DSTATE_LINE_STIPPLE_CommandType_start 29 +#define GEN6_3DSTATE_LINE_STIPPLE_CommandType_start 29 +#define GEN5_3DSTATE_LINE_STIPPLE_CommandType_start 29 +#define GEN45_3DSTATE_LINE_STIPPLE_CommandType_start 29 +#define GEN4_3DSTATE_LINE_STIPPLE_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_LINE_STIPPLE_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 29; + case 4: + if (devinfo->is_g4x) { + return 29; + } else { + return 29; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_LINE_STIPPLE::Current Repeat Counter */ + + +#define GEN11_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_bits 9 +#define GEN10_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_bits 9 +#define GEN9_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_bits 9 +#define GEN8_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_bits 9 +#define GEN75_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_bits 9 +#define GEN7_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_bits 9 +#define GEN6_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_bits 9 +#define GEN5_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_bits 9 +#define GEN45_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_bits 9 +#define GEN4_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 9; + case 10: return 9; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 9; + } + case 6: return 9; + case 5: return 9; + case 4: + if (devinfo->is_g4x) { + return 9; + } else { + return 9; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_start 53 +#define GEN10_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_start 53 +#define GEN9_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_start 53 +#define GEN8_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_start 53 +#define GEN75_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_start 53 +#define GEN7_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_start 53 +#define GEN6_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_start 53 +#define GEN5_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_start 53 +#define GEN45_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_start 53 +#define GEN4_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_start 53 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_LINE_STIPPLE_CurrentRepeatCounter_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 53; + case 10: return 53; + case 9: return 53; + case 8: return 53; + case 7: + if (devinfo->is_haswell) { + return 53; + } else { + return 53; + } + case 6: return 53; + case 5: return 53; + case 4: + if (devinfo->is_g4x) { + return 53; + } else { + return 53; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_LINE_STIPPLE::Current Stipple Index */ + + +#define GEN11_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_bits 4 +#define GEN10_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_bits 4 +#define GEN9_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_bits 4 +#define GEN8_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_bits 4 +#define GEN75_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_bits 4 +#define GEN7_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_bits 4 +#define GEN6_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_bits 4 +#define GEN5_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_bits 4 +#define GEN45_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_bits 4 +#define GEN4_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 4; + case 4: + if (devinfo->is_g4x) { + return 4; + } else { + return 4; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_start 48 +#define GEN10_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_start 48 +#define GEN9_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_start 48 +#define GEN8_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_start 48 +#define GEN75_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_start 48 +#define GEN7_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_start 48 +#define GEN6_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_start 48 +#define GEN5_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_start 48 +#define GEN45_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_start 48 +#define GEN4_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_start 48 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_LINE_STIPPLE_CurrentStippleIndex_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 48; + case 7: + if (devinfo->is_haswell) { + return 48; + } else { + return 48; + } + case 6: return 48; + case 5: return 48; + case 4: + if (devinfo->is_g4x) { + return 48; + } else { + return 48; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_LINE_STIPPLE::DWord Length */ + + +#define GEN11_3DSTATE_LINE_STIPPLE_DWordLength_bits 8 +#define GEN10_3DSTATE_LINE_STIPPLE_DWordLength_bits 8 +#define GEN9_3DSTATE_LINE_STIPPLE_DWordLength_bits 8 +#define GEN8_3DSTATE_LINE_STIPPLE_DWordLength_bits 8 +#define GEN75_3DSTATE_LINE_STIPPLE_DWordLength_bits 8 +#define GEN7_3DSTATE_LINE_STIPPLE_DWordLength_bits 8 +#define GEN6_3DSTATE_LINE_STIPPLE_DWordLength_bits 8 +#define GEN5_3DSTATE_LINE_STIPPLE_DWordLength_bits 8 +#define GEN45_3DSTATE_LINE_STIPPLE_DWordLength_bits 8 +#define GEN4_3DSTATE_LINE_STIPPLE_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_LINE_STIPPLE_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_LINE_STIPPLE_DWordLength_start 0 +#define GEN10_3DSTATE_LINE_STIPPLE_DWordLength_start 0 +#define GEN9_3DSTATE_LINE_STIPPLE_DWordLength_start 0 +#define GEN8_3DSTATE_LINE_STIPPLE_DWordLength_start 0 +#define GEN75_3DSTATE_LINE_STIPPLE_DWordLength_start 0 +#define GEN7_3DSTATE_LINE_STIPPLE_DWordLength_start 0 +#define GEN6_3DSTATE_LINE_STIPPLE_DWordLength_start 0 +#define GEN5_3DSTATE_LINE_STIPPLE_DWordLength_start 0 +#define GEN45_3DSTATE_LINE_STIPPLE_DWordLength_start 0 +#define GEN4_3DSTATE_LINE_STIPPLE_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_LINE_STIPPLE_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_LINE_STIPPLE::Line Stipple Inverse Repeat Count */ + + +#define GEN11_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_bits 17 +#define GEN10_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_bits 17 +#define GEN9_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_bits 17 +#define GEN8_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_bits 17 +#define GEN75_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_bits 17 +#define GEN7_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_bits 17 +#define GEN6_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_bits 16 +#define GEN5_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_bits 16 +#define GEN45_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_bits 16 +#define GEN4_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 17; + case 10: return 17; + case 9: return 17; + case 8: return 17; + case 7: + if (devinfo->is_haswell) { + return 17; + } else { + return 17; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_start 79 +#define GEN10_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_start 79 +#define GEN9_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_start 79 +#define GEN8_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_start 79 +#define GEN75_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_start 79 +#define GEN7_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_start 79 +#define GEN6_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_start 80 +#define GEN5_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_start 80 +#define GEN45_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_start 80 +#define GEN4_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_start 80 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_LINE_STIPPLE_LineStippleInverseRepeatCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 79; + case 10: return 79; + case 9: return 79; + case 8: return 79; + case 7: + if (devinfo->is_haswell) { + return 79; + } else { + return 79; + } + case 6: return 80; + case 5: return 80; + case 4: + if (devinfo->is_g4x) { + return 80; + } else { + return 80; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_LINE_STIPPLE::Line Stipple Pattern */ + + +#define GEN11_3DSTATE_LINE_STIPPLE_LineStipplePattern_bits 16 +#define GEN10_3DSTATE_LINE_STIPPLE_LineStipplePattern_bits 16 +#define GEN9_3DSTATE_LINE_STIPPLE_LineStipplePattern_bits 16 +#define GEN8_3DSTATE_LINE_STIPPLE_LineStipplePattern_bits 16 +#define GEN75_3DSTATE_LINE_STIPPLE_LineStipplePattern_bits 16 +#define GEN7_3DSTATE_LINE_STIPPLE_LineStipplePattern_bits 16 +#define GEN6_3DSTATE_LINE_STIPPLE_LineStipplePattern_bits 16 +#define GEN5_3DSTATE_LINE_STIPPLE_LineStipplePattern_bits 16 +#define GEN45_3DSTATE_LINE_STIPPLE_LineStipplePattern_bits 16 +#define GEN4_3DSTATE_LINE_STIPPLE_LineStipplePattern_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_LINE_STIPPLE_LineStipplePattern_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_LINE_STIPPLE_LineStipplePattern_start 32 +#define GEN10_3DSTATE_LINE_STIPPLE_LineStipplePattern_start 32 +#define GEN9_3DSTATE_LINE_STIPPLE_LineStipplePattern_start 32 +#define GEN8_3DSTATE_LINE_STIPPLE_LineStipplePattern_start 32 +#define GEN75_3DSTATE_LINE_STIPPLE_LineStipplePattern_start 32 +#define GEN7_3DSTATE_LINE_STIPPLE_LineStipplePattern_start 32 +#define GEN6_3DSTATE_LINE_STIPPLE_LineStipplePattern_start 32 +#define GEN5_3DSTATE_LINE_STIPPLE_LineStipplePattern_start 32 +#define GEN45_3DSTATE_LINE_STIPPLE_LineStipplePattern_start 32 +#define GEN4_3DSTATE_LINE_STIPPLE_LineStipplePattern_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_LINE_STIPPLE_LineStipplePattern_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_LINE_STIPPLE::Line Stipple Repeat Count */ + + +#define GEN11_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_bits 9 +#define GEN10_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_bits 9 +#define GEN9_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_bits 9 +#define GEN8_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_bits 9 +#define GEN75_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_bits 9 +#define GEN7_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_bits 9 +#define GEN6_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_bits 9 +#define GEN5_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_bits 9 +#define GEN45_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_bits 9 +#define GEN4_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 9; + case 10: return 9; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 9; + } + case 6: return 9; + case 5: return 9; + case 4: + if (devinfo->is_g4x) { + return 9; + } else { + return 9; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_start 64 +#define GEN10_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_start 64 +#define GEN9_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_start 64 +#define GEN8_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_start 64 +#define GEN75_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_start 64 +#define GEN7_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_start 64 +#define GEN6_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_start 64 +#define GEN5_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_start 64 +#define GEN45_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_start 64 +#define GEN4_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_start 64 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_LINE_STIPPLE_LineStippleRepeatCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 64; + case 5: return 64; + case 4: + if (devinfo->is_g4x) { + return 64; + } else { + return 64; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_LINE_STIPPLE::Modify Enable */ + + +#define GEN5_3DSTATE_LINE_STIPPLE_ModifyEnable_bits 1 +#define GEN4_3DSTATE_LINE_STIPPLE_ModifyEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_LINE_STIPPLE_ModifyEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_3DSTATE_LINE_STIPPLE_ModifyEnable_start 63 +#define GEN4_3DSTATE_LINE_STIPPLE_ModifyEnable_start 63 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_LINE_STIPPLE_ModifyEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 63; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 63; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_LINE_STIPPLE::Modify Enable (Current Repeat Counter, Current Stipple Index) */ + + +#define GEN11_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_bits 1 +#define GEN10_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_bits 1 +#define GEN9_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_bits 1 +#define GEN8_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_bits 1 +#define GEN75_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_bits 1 +#define GEN7_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_bits 1 +#define GEN6_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_bits 1 +#define GEN45_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_start 63 +#define GEN10_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_start 63 +#define GEN9_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_start 63 +#define GEN8_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_start 63 +#define GEN75_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_start 63 +#define GEN7_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_start 63 +#define GEN6_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_start 63 +#define GEN45_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_start 63 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_LINE_STIPPLE_ModifyEnableCurrentRepeatCounterCurrentStippleIndex_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 63; + case 10: return 63; + case 9: return 63; + case 8: return 63; + case 7: + if (devinfo->is_haswell) { + return 63; + } else { + return 63; + } + case 6: return 63; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 63; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_MONOFILTER_SIZE */ + + +#define GEN11_3DSTATE_MONOFILTER_SIZE_length 2 +#define GEN10_3DSTATE_MONOFILTER_SIZE_length 2 +#define GEN9_3DSTATE_MONOFILTER_SIZE_length 2 +#define GEN8_3DSTATE_MONOFILTER_SIZE_length 2 +#define GEN75_3DSTATE_MONOFILTER_SIZE_length 2 +#define GEN7_3DSTATE_MONOFILTER_SIZE_length 2 +#define GEN6_3DSTATE_MONOFILTER_SIZE_length 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MONOFILTER_SIZE_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_MONOFILTER_SIZE::3D Command Opcode */ + + +#define GEN11_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_bits 3 +#define GEN6_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_start 24 +#define GEN6_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MONOFILTER_SIZE_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_MONOFILTER_SIZE::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_bits 8 +#define GEN6_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_start 16 +#define GEN6_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MONOFILTER_SIZE_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_MONOFILTER_SIZE::Command SubType */ + + +#define GEN11_3DSTATE_MONOFILTER_SIZE_CommandSubType_bits 2 +#define GEN10_3DSTATE_MONOFILTER_SIZE_CommandSubType_bits 2 +#define GEN9_3DSTATE_MONOFILTER_SIZE_CommandSubType_bits 2 +#define GEN8_3DSTATE_MONOFILTER_SIZE_CommandSubType_bits 2 +#define GEN75_3DSTATE_MONOFILTER_SIZE_CommandSubType_bits 2 +#define GEN7_3DSTATE_MONOFILTER_SIZE_CommandSubType_bits 2 +#define GEN6_3DSTATE_MONOFILTER_SIZE_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MONOFILTER_SIZE_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_MONOFILTER_SIZE_CommandSubType_start 27 +#define GEN10_3DSTATE_MONOFILTER_SIZE_CommandSubType_start 27 +#define GEN9_3DSTATE_MONOFILTER_SIZE_CommandSubType_start 27 +#define GEN8_3DSTATE_MONOFILTER_SIZE_CommandSubType_start 27 +#define GEN75_3DSTATE_MONOFILTER_SIZE_CommandSubType_start 27 +#define GEN7_3DSTATE_MONOFILTER_SIZE_CommandSubType_start 27 +#define GEN6_3DSTATE_MONOFILTER_SIZE_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MONOFILTER_SIZE_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_MONOFILTER_SIZE::Command Type */ + + +#define GEN11_3DSTATE_MONOFILTER_SIZE_CommandType_bits 3 +#define GEN10_3DSTATE_MONOFILTER_SIZE_CommandType_bits 3 +#define GEN9_3DSTATE_MONOFILTER_SIZE_CommandType_bits 3 +#define GEN8_3DSTATE_MONOFILTER_SIZE_CommandType_bits 3 +#define GEN75_3DSTATE_MONOFILTER_SIZE_CommandType_bits 3 +#define GEN7_3DSTATE_MONOFILTER_SIZE_CommandType_bits 3 +#define GEN6_3DSTATE_MONOFILTER_SIZE_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MONOFILTER_SIZE_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_MONOFILTER_SIZE_CommandType_start 29 +#define GEN10_3DSTATE_MONOFILTER_SIZE_CommandType_start 29 +#define GEN9_3DSTATE_MONOFILTER_SIZE_CommandType_start 29 +#define GEN8_3DSTATE_MONOFILTER_SIZE_CommandType_start 29 +#define GEN75_3DSTATE_MONOFILTER_SIZE_CommandType_start 29 +#define GEN7_3DSTATE_MONOFILTER_SIZE_CommandType_start 29 +#define GEN6_3DSTATE_MONOFILTER_SIZE_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MONOFILTER_SIZE_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_MONOFILTER_SIZE::DWord Length */ + + +#define GEN11_3DSTATE_MONOFILTER_SIZE_DWordLength_bits 8 +#define GEN10_3DSTATE_MONOFILTER_SIZE_DWordLength_bits 8 +#define GEN9_3DSTATE_MONOFILTER_SIZE_DWordLength_bits 8 +#define GEN8_3DSTATE_MONOFILTER_SIZE_DWordLength_bits 8 +#define GEN75_3DSTATE_MONOFILTER_SIZE_DWordLength_bits 8 +#define GEN7_3DSTATE_MONOFILTER_SIZE_DWordLength_bits 8 +#define GEN6_3DSTATE_MONOFILTER_SIZE_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MONOFILTER_SIZE_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_MONOFILTER_SIZE_DWordLength_start 0 +#define GEN10_3DSTATE_MONOFILTER_SIZE_DWordLength_start 0 +#define GEN9_3DSTATE_MONOFILTER_SIZE_DWordLength_start 0 +#define GEN8_3DSTATE_MONOFILTER_SIZE_DWordLength_start 0 +#define GEN75_3DSTATE_MONOFILTER_SIZE_DWordLength_start 0 +#define GEN7_3DSTATE_MONOFILTER_SIZE_DWordLength_start 0 +#define GEN6_3DSTATE_MONOFILTER_SIZE_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MONOFILTER_SIZE_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_MONOFILTER_SIZE::Monochrome Filter Height */ + + +#define GEN11_3DSTATE_MONOFILTER_SIZE_MonochromeFilterHeight_bits 3 +#define GEN10_3DSTATE_MONOFILTER_SIZE_MonochromeFilterHeight_bits 3 +#define GEN9_3DSTATE_MONOFILTER_SIZE_MonochromeFilterHeight_bits 3 +#define GEN8_3DSTATE_MONOFILTER_SIZE_MonochromeFilterHeight_bits 3 +#define GEN75_3DSTATE_MONOFILTER_SIZE_MonochromeFilterHeight_bits 3 +#define GEN7_3DSTATE_MONOFILTER_SIZE_MonochromeFilterHeight_bits 3 +#define GEN6_3DSTATE_MONOFILTER_SIZE_MonochromeFilterHeight_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MONOFILTER_SIZE_MonochromeFilterHeight_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_MONOFILTER_SIZE_MonochromeFilterHeight_start 32 +#define GEN10_3DSTATE_MONOFILTER_SIZE_MonochromeFilterHeight_start 32 +#define GEN9_3DSTATE_MONOFILTER_SIZE_MonochromeFilterHeight_start 32 +#define GEN8_3DSTATE_MONOFILTER_SIZE_MonochromeFilterHeight_start 32 +#define GEN75_3DSTATE_MONOFILTER_SIZE_MonochromeFilterHeight_start 32 +#define GEN7_3DSTATE_MONOFILTER_SIZE_MonochromeFilterHeight_start 32 +#define GEN6_3DSTATE_MONOFILTER_SIZE_MonochromeFilterHeight_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MONOFILTER_SIZE_MonochromeFilterHeight_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_MONOFILTER_SIZE::Monochrome Filter Width */ + + +#define GEN11_3DSTATE_MONOFILTER_SIZE_MonochromeFilterWidth_bits 3 +#define GEN10_3DSTATE_MONOFILTER_SIZE_MonochromeFilterWidth_bits 3 +#define GEN9_3DSTATE_MONOFILTER_SIZE_MonochromeFilterWidth_bits 3 +#define GEN8_3DSTATE_MONOFILTER_SIZE_MonochromeFilterWidth_bits 3 +#define GEN75_3DSTATE_MONOFILTER_SIZE_MonochromeFilterWidth_bits 3 +#define GEN7_3DSTATE_MONOFILTER_SIZE_MonochromeFilterWidth_bits 3 +#define GEN6_3DSTATE_MONOFILTER_SIZE_MonochromeFilterWidth_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MONOFILTER_SIZE_MonochromeFilterWidth_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_MONOFILTER_SIZE_MonochromeFilterWidth_start 35 +#define GEN10_3DSTATE_MONOFILTER_SIZE_MonochromeFilterWidth_start 35 +#define GEN9_3DSTATE_MONOFILTER_SIZE_MonochromeFilterWidth_start 35 +#define GEN8_3DSTATE_MONOFILTER_SIZE_MonochromeFilterWidth_start 35 +#define GEN75_3DSTATE_MONOFILTER_SIZE_MonochromeFilterWidth_start 35 +#define GEN7_3DSTATE_MONOFILTER_SIZE_MonochromeFilterWidth_start 35 +#define GEN6_3DSTATE_MONOFILTER_SIZE_MonochromeFilterWidth_start 35 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MONOFILTER_SIZE_MonochromeFilterWidth_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 35; + case 10: return 35; + case 9: return 35; + case 8: return 35; + case 7: + if (devinfo->is_haswell) { + return 35; + } else { + return 35; + } + case 6: return 35; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_MULTISAMPLE */ + + +#define GEN11_3DSTATE_MULTISAMPLE_length 2 +#define GEN10_3DSTATE_MULTISAMPLE_length 2 +#define GEN9_3DSTATE_MULTISAMPLE_length 2 +#define GEN8_3DSTATE_MULTISAMPLE_length 2 +#define GEN75_3DSTATE_MULTISAMPLE_length 4 +#define GEN7_3DSTATE_MULTISAMPLE_length 4 +#define GEN6_3DSTATE_MULTISAMPLE_length 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_MULTISAMPLE::3D Command Opcode */ + + +#define GEN11_3DSTATE_MULTISAMPLE_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_MULTISAMPLE_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_MULTISAMPLE_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_MULTISAMPLE_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_MULTISAMPLE_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_MULTISAMPLE_3DCommandOpcode_bits 3 +#define GEN6_3DSTATE_MULTISAMPLE_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_MULTISAMPLE_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_MULTISAMPLE_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_MULTISAMPLE_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_MULTISAMPLE_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_MULTISAMPLE_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_MULTISAMPLE_3DCommandOpcode_start 24 +#define GEN6_3DSTATE_MULTISAMPLE_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_MULTISAMPLE::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_MULTISAMPLE_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_MULTISAMPLE_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_MULTISAMPLE_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_MULTISAMPLE_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_MULTISAMPLE_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_MULTISAMPLE_3DCommandSubOpcode_bits 8 +#define GEN6_3DSTATE_MULTISAMPLE_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_MULTISAMPLE_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_MULTISAMPLE_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_MULTISAMPLE_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_MULTISAMPLE_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_MULTISAMPLE_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_MULTISAMPLE_3DCommandSubOpcode_start 16 +#define GEN6_3DSTATE_MULTISAMPLE_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_MULTISAMPLE::Command SubType */ + + +#define GEN11_3DSTATE_MULTISAMPLE_CommandSubType_bits 2 +#define GEN10_3DSTATE_MULTISAMPLE_CommandSubType_bits 2 +#define GEN9_3DSTATE_MULTISAMPLE_CommandSubType_bits 2 +#define GEN8_3DSTATE_MULTISAMPLE_CommandSubType_bits 2 +#define GEN75_3DSTATE_MULTISAMPLE_CommandSubType_bits 2 +#define GEN7_3DSTATE_MULTISAMPLE_CommandSubType_bits 2 +#define GEN6_3DSTATE_MULTISAMPLE_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_MULTISAMPLE_CommandSubType_start 27 +#define GEN10_3DSTATE_MULTISAMPLE_CommandSubType_start 27 +#define GEN9_3DSTATE_MULTISAMPLE_CommandSubType_start 27 +#define GEN8_3DSTATE_MULTISAMPLE_CommandSubType_start 27 +#define GEN75_3DSTATE_MULTISAMPLE_CommandSubType_start 27 +#define GEN7_3DSTATE_MULTISAMPLE_CommandSubType_start 27 +#define GEN6_3DSTATE_MULTISAMPLE_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_MULTISAMPLE::Command Type */ + + +#define GEN11_3DSTATE_MULTISAMPLE_CommandType_bits 3 +#define GEN10_3DSTATE_MULTISAMPLE_CommandType_bits 3 +#define GEN9_3DSTATE_MULTISAMPLE_CommandType_bits 3 +#define GEN8_3DSTATE_MULTISAMPLE_CommandType_bits 3 +#define GEN75_3DSTATE_MULTISAMPLE_CommandType_bits 3 +#define GEN7_3DSTATE_MULTISAMPLE_CommandType_bits 3 +#define GEN6_3DSTATE_MULTISAMPLE_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_MULTISAMPLE_CommandType_start 29 +#define GEN10_3DSTATE_MULTISAMPLE_CommandType_start 29 +#define GEN9_3DSTATE_MULTISAMPLE_CommandType_start 29 +#define GEN8_3DSTATE_MULTISAMPLE_CommandType_start 29 +#define GEN75_3DSTATE_MULTISAMPLE_CommandType_start 29 +#define GEN7_3DSTATE_MULTISAMPLE_CommandType_start 29 +#define GEN6_3DSTATE_MULTISAMPLE_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_MULTISAMPLE::DWord Length */ + + +#define GEN11_3DSTATE_MULTISAMPLE_DWordLength_bits 8 +#define GEN10_3DSTATE_MULTISAMPLE_DWordLength_bits 8 +#define GEN9_3DSTATE_MULTISAMPLE_DWordLength_bits 8 +#define GEN8_3DSTATE_MULTISAMPLE_DWordLength_bits 8 +#define GEN75_3DSTATE_MULTISAMPLE_DWordLength_bits 8 +#define GEN7_3DSTATE_MULTISAMPLE_DWordLength_bits 8 +#define GEN6_3DSTATE_MULTISAMPLE_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_MULTISAMPLE_DWordLength_start 0 +#define GEN10_3DSTATE_MULTISAMPLE_DWordLength_start 0 +#define GEN9_3DSTATE_MULTISAMPLE_DWordLength_start 0 +#define GEN8_3DSTATE_MULTISAMPLE_DWordLength_start 0 +#define GEN75_3DSTATE_MULTISAMPLE_DWordLength_start 0 +#define GEN7_3DSTATE_MULTISAMPLE_DWordLength_start 0 +#define GEN6_3DSTATE_MULTISAMPLE_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_MULTISAMPLE::Multi Sample Enable */ + + +#define GEN75_3DSTATE_MULTISAMPLE_MultiSampleEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_MultiSampleEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_MULTISAMPLE_MultiSampleEnable_start 37 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_MultiSampleEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 37; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_MULTISAMPLE::Number of Multisamples */ + + +#define GEN11_3DSTATE_MULTISAMPLE_NumberofMultisamples_bits 3 +#define GEN10_3DSTATE_MULTISAMPLE_NumberofMultisamples_bits 3 +#define GEN9_3DSTATE_MULTISAMPLE_NumberofMultisamples_bits 3 +#define GEN8_3DSTATE_MULTISAMPLE_NumberofMultisamples_bits 3 +#define GEN75_3DSTATE_MULTISAMPLE_NumberofMultisamples_bits 3 +#define GEN7_3DSTATE_MULTISAMPLE_NumberofMultisamples_bits 3 +#define GEN6_3DSTATE_MULTISAMPLE_NumberofMultisamples_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_NumberofMultisamples_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_MULTISAMPLE_NumberofMultisamples_start 33 +#define GEN10_3DSTATE_MULTISAMPLE_NumberofMultisamples_start 33 +#define GEN9_3DSTATE_MULTISAMPLE_NumberofMultisamples_start 33 +#define GEN8_3DSTATE_MULTISAMPLE_NumberofMultisamples_start 33 +#define GEN75_3DSTATE_MULTISAMPLE_NumberofMultisamples_start 33 +#define GEN7_3DSTATE_MULTISAMPLE_NumberofMultisamples_start 33 +#define GEN6_3DSTATE_MULTISAMPLE_NumberofMultisamples_start 33 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_NumberofMultisamples_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 33; + case 10: return 33; + case 9: return 33; + case 8: return 33; + case 7: + if (devinfo->is_haswell) { + return 33; + } else { + return 33; + } + case 6: return 33; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_MULTISAMPLE::Pixel Location */ + + +#define GEN11_3DSTATE_MULTISAMPLE_PixelLocation_bits 1 +#define GEN10_3DSTATE_MULTISAMPLE_PixelLocation_bits 1 +#define GEN9_3DSTATE_MULTISAMPLE_PixelLocation_bits 1 +#define GEN8_3DSTATE_MULTISAMPLE_PixelLocation_bits 1 +#define GEN75_3DSTATE_MULTISAMPLE_PixelLocation_bits 1 +#define GEN7_3DSTATE_MULTISAMPLE_PixelLocation_bits 1 +#define GEN6_3DSTATE_MULTISAMPLE_PixelLocation_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_PixelLocation_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_MULTISAMPLE_PixelLocation_start 36 +#define GEN10_3DSTATE_MULTISAMPLE_PixelLocation_start 36 +#define GEN9_3DSTATE_MULTISAMPLE_PixelLocation_start 36 +#define GEN8_3DSTATE_MULTISAMPLE_PixelLocation_start 36 +#define GEN75_3DSTATE_MULTISAMPLE_PixelLocation_start 36 +#define GEN7_3DSTATE_MULTISAMPLE_PixelLocation_start 36 +#define GEN6_3DSTATE_MULTISAMPLE_PixelLocation_start 36 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_PixelLocation_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 36; + case 10: return 36; + case 9: return 36; + case 8: return 36; + case 7: + if (devinfo->is_haswell) { + return 36; + } else { + return 36; + } + case 6: return 36; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_MULTISAMPLE::Pixel Position Offset Enable */ + + +#define GEN11_3DSTATE_MULTISAMPLE_PixelPositionOffsetEnable_bits 1 +#define GEN10_3DSTATE_MULTISAMPLE_PixelPositionOffsetEnable_bits 1 +#define GEN9_3DSTATE_MULTISAMPLE_PixelPositionOffsetEnable_bits 1 +#define GEN8_3DSTATE_MULTISAMPLE_PixelPositionOffsetEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_PixelPositionOffsetEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_MULTISAMPLE_PixelPositionOffsetEnable_start 37 +#define GEN10_3DSTATE_MULTISAMPLE_PixelPositionOffsetEnable_start 37 +#define GEN9_3DSTATE_MULTISAMPLE_PixelPositionOffsetEnable_start 37 +#define GEN8_3DSTATE_MULTISAMPLE_PixelPositionOffsetEnable_start 37 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_PixelPositionOffsetEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 37; + case 10: return 37; + case 9: return 37; + case 8: return 37; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_MULTISAMPLE::Sample0 X Offset */ + + +#define GEN75_3DSTATE_MULTISAMPLE_Sample0XOffset_bits 4 +#define GEN7_3DSTATE_MULTISAMPLE_Sample0XOffset_bits 4 +#define GEN6_3DSTATE_MULTISAMPLE_Sample0XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_Sample0XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_MULTISAMPLE_Sample0XOffset_start 68 +#define GEN7_3DSTATE_MULTISAMPLE_Sample0XOffset_start 68 +#define GEN6_3DSTATE_MULTISAMPLE_Sample0XOffset_start 68 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_Sample0XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 68; + } else { + return 68; + } + case 6: return 68; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_MULTISAMPLE::Sample0 Y Offset */ + + +#define GEN75_3DSTATE_MULTISAMPLE_Sample0YOffset_bits 4 +#define GEN7_3DSTATE_MULTISAMPLE_Sample0YOffset_bits 4 +#define GEN6_3DSTATE_MULTISAMPLE_Sample0YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_Sample0YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_MULTISAMPLE_Sample0YOffset_start 64 +#define GEN7_3DSTATE_MULTISAMPLE_Sample0YOffset_start 64 +#define GEN6_3DSTATE_MULTISAMPLE_Sample0YOffset_start 64 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_Sample0YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 64; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_MULTISAMPLE::Sample1 X Offset */ + + +#define GEN75_3DSTATE_MULTISAMPLE_Sample1XOffset_bits 4 +#define GEN7_3DSTATE_MULTISAMPLE_Sample1XOffset_bits 4 +#define GEN6_3DSTATE_MULTISAMPLE_Sample1XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_Sample1XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_MULTISAMPLE_Sample1XOffset_start 76 +#define GEN7_3DSTATE_MULTISAMPLE_Sample1XOffset_start 76 +#define GEN6_3DSTATE_MULTISAMPLE_Sample1XOffset_start 76 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_Sample1XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 76; + } else { + return 76; + } + case 6: return 76; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_MULTISAMPLE::Sample1 Y Offset */ + + +#define GEN75_3DSTATE_MULTISAMPLE_Sample1YOffset_bits 4 +#define GEN7_3DSTATE_MULTISAMPLE_Sample1YOffset_bits 4 +#define GEN6_3DSTATE_MULTISAMPLE_Sample1YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_Sample1YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_MULTISAMPLE_Sample1YOffset_start 72 +#define GEN7_3DSTATE_MULTISAMPLE_Sample1YOffset_start 72 +#define GEN6_3DSTATE_MULTISAMPLE_Sample1YOffset_start 72 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_Sample1YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 72; + } else { + return 72; + } + case 6: return 72; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_MULTISAMPLE::Sample2 X Offset */ + + +#define GEN75_3DSTATE_MULTISAMPLE_Sample2XOffset_bits 4 +#define GEN7_3DSTATE_MULTISAMPLE_Sample2XOffset_bits 4 +#define GEN6_3DSTATE_MULTISAMPLE_Sample2XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_Sample2XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_MULTISAMPLE_Sample2XOffset_start 84 +#define GEN7_3DSTATE_MULTISAMPLE_Sample2XOffset_start 84 +#define GEN6_3DSTATE_MULTISAMPLE_Sample2XOffset_start 84 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_Sample2XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 84; + } else { + return 84; + } + case 6: return 84; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_MULTISAMPLE::Sample2 Y Offset */ + + +#define GEN75_3DSTATE_MULTISAMPLE_Sample2YOffset_bits 4 +#define GEN7_3DSTATE_MULTISAMPLE_Sample2YOffset_bits 4 +#define GEN6_3DSTATE_MULTISAMPLE_Sample2YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_Sample2YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_MULTISAMPLE_Sample2YOffset_start 80 +#define GEN7_3DSTATE_MULTISAMPLE_Sample2YOffset_start 80 +#define GEN6_3DSTATE_MULTISAMPLE_Sample2YOffset_start 80 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_Sample2YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 80; + } else { + return 80; + } + case 6: return 80; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_MULTISAMPLE::Sample3 X Offset */ + + +#define GEN75_3DSTATE_MULTISAMPLE_Sample3XOffset_bits 4 +#define GEN7_3DSTATE_MULTISAMPLE_Sample3XOffset_bits 4 +#define GEN6_3DSTATE_MULTISAMPLE_Sample3XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_Sample3XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_MULTISAMPLE_Sample3XOffset_start 92 +#define GEN7_3DSTATE_MULTISAMPLE_Sample3XOffset_start 92 +#define GEN6_3DSTATE_MULTISAMPLE_Sample3XOffset_start 92 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_Sample3XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 92; + } else { + return 92; + } + case 6: return 92; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_MULTISAMPLE::Sample3 Y Offset */ + + +#define GEN75_3DSTATE_MULTISAMPLE_Sample3YOffset_bits 4 +#define GEN7_3DSTATE_MULTISAMPLE_Sample3YOffset_bits 4 +#define GEN6_3DSTATE_MULTISAMPLE_Sample3YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_Sample3YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_MULTISAMPLE_Sample3YOffset_start 88 +#define GEN7_3DSTATE_MULTISAMPLE_Sample3YOffset_start 88 +#define GEN6_3DSTATE_MULTISAMPLE_Sample3YOffset_start 88 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_Sample3YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 88; + } else { + return 88; + } + case 6: return 88; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_MULTISAMPLE::Sample4 X Offset */ + + +#define GEN75_3DSTATE_MULTISAMPLE_Sample4XOffset_bits 4 +#define GEN7_3DSTATE_MULTISAMPLE_Sample4XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_Sample4XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_MULTISAMPLE_Sample4XOffset_start 100 +#define GEN7_3DSTATE_MULTISAMPLE_Sample4XOffset_start 100 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_Sample4XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 100; + } else { + return 100; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_MULTISAMPLE::Sample4 Y Offset */ + + +#define GEN75_3DSTATE_MULTISAMPLE_Sample4YOffset_bits 4 +#define GEN7_3DSTATE_MULTISAMPLE_Sample4YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_Sample4YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_MULTISAMPLE_Sample4YOffset_start 96 +#define GEN7_3DSTATE_MULTISAMPLE_Sample4YOffset_start 96 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_Sample4YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 96; + } else { + return 96; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_MULTISAMPLE::Sample5 X Offset */ + + +#define GEN75_3DSTATE_MULTISAMPLE_Sample5XOffset_bits 4 +#define GEN7_3DSTATE_MULTISAMPLE_Sample5XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_Sample5XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_MULTISAMPLE_Sample5XOffset_start 108 +#define GEN7_3DSTATE_MULTISAMPLE_Sample5XOffset_start 108 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_Sample5XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 108; + } else { + return 108; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_MULTISAMPLE::Sample5 Y Offset */ + + +#define GEN75_3DSTATE_MULTISAMPLE_Sample5YOffset_bits 4 +#define GEN7_3DSTATE_MULTISAMPLE_Sample5YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_Sample5YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_MULTISAMPLE_Sample5YOffset_start 104 +#define GEN7_3DSTATE_MULTISAMPLE_Sample5YOffset_start 104 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_Sample5YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 104; + } else { + return 104; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_MULTISAMPLE::Sample6 X Offset */ + + +#define GEN75_3DSTATE_MULTISAMPLE_Sample6XOffset_bits 4 +#define GEN7_3DSTATE_MULTISAMPLE_Sample6XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_Sample6XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_MULTISAMPLE_Sample6XOffset_start 116 +#define GEN7_3DSTATE_MULTISAMPLE_Sample6XOffset_start 116 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_Sample6XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 116; + } else { + return 116; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_MULTISAMPLE::Sample6 Y Offset */ + + +#define GEN75_3DSTATE_MULTISAMPLE_Sample6YOffset_bits 4 +#define GEN7_3DSTATE_MULTISAMPLE_Sample6YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_Sample6YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_MULTISAMPLE_Sample6YOffset_start 112 +#define GEN7_3DSTATE_MULTISAMPLE_Sample6YOffset_start 112 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_Sample6YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 112; + } else { + return 112; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_MULTISAMPLE::Sample7 X Offset */ + + +#define GEN75_3DSTATE_MULTISAMPLE_Sample7XOffset_bits 4 +#define GEN7_3DSTATE_MULTISAMPLE_Sample7XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_Sample7XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_MULTISAMPLE_Sample7XOffset_start 124 +#define GEN7_3DSTATE_MULTISAMPLE_Sample7XOffset_start 124 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_Sample7XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 124; + } else { + return 124; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_MULTISAMPLE::Sample7 Y Offset */ + + +#define GEN75_3DSTATE_MULTISAMPLE_Sample7YOffset_bits 4 +#define GEN7_3DSTATE_MULTISAMPLE_Sample7YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_Sample7YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_MULTISAMPLE_Sample7YOffset_start 120 +#define GEN7_3DSTATE_MULTISAMPLE_Sample7YOffset_start 120 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_MULTISAMPLE_Sample7YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 120; + } else { + return 120; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PIPELINED_POINTERS */ + + +#define GEN5_3DSTATE_PIPELINED_POINTERS_length 7 +#define GEN45_3DSTATE_PIPELINED_POINTERS_length 7 +#define GEN4_3DSTATE_PIPELINED_POINTERS_length 7 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PIPELINED_POINTERS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 7; + case 4: + if (devinfo->is_g4x) { + return 7; + } else { + return 7; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PIPELINED_POINTERS::3D Command Opcode */ + + +#define GEN5_3DSTATE_PIPELINED_POINTERS_3DCommandOpcode_bits 3 +#define GEN45_3DSTATE_PIPELINED_POINTERS_3DCommandOpcode_bits 3 +#define GEN4_3DSTATE_PIPELINED_POINTERS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PIPELINED_POINTERS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_3DSTATE_PIPELINED_POINTERS_3DCommandOpcode_start 24 +#define GEN45_3DSTATE_PIPELINED_POINTERS_3DCommandOpcode_start 24 +#define GEN4_3DSTATE_PIPELINED_POINTERS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PIPELINED_POINTERS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 24; + case 4: + if (devinfo->is_g4x) { + return 24; + } else { + return 24; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PIPELINED_POINTERS::3D Command Sub Opcode */ + + +#define GEN5_3DSTATE_PIPELINED_POINTERS_3DCommandSubOpcode_bits 8 +#define GEN45_3DSTATE_PIPELINED_POINTERS_3DCommandSubOpcode_bits 8 +#define GEN4_3DSTATE_PIPELINED_POINTERS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PIPELINED_POINTERS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_3DSTATE_PIPELINED_POINTERS_3DCommandSubOpcode_start 16 +#define GEN45_3DSTATE_PIPELINED_POINTERS_3DCommandSubOpcode_start 16 +#define GEN4_3DSTATE_PIPELINED_POINTERS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PIPELINED_POINTERS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PIPELINED_POINTERS::Clip Enable */ + + +#define GEN5_3DSTATE_PIPELINED_POINTERS_ClipEnable_bits 1 +#define GEN45_3DSTATE_PIPELINED_POINTERS_ClipEnable_bits 1 +#define GEN4_3DSTATE_PIPELINED_POINTERS_ClipEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PIPELINED_POINTERS_ClipEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_3DSTATE_PIPELINED_POINTERS_ClipEnable_start 96 +#define GEN45_3DSTATE_PIPELINED_POINTERS_ClipEnable_start 96 +#define GEN4_3DSTATE_PIPELINED_POINTERS_ClipEnable_start 96 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PIPELINED_POINTERS_ClipEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 96; + case 4: + if (devinfo->is_g4x) { + return 96; + } else { + return 96; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PIPELINED_POINTERS::Command SubType */ + + +#define GEN5_3DSTATE_PIPELINED_POINTERS_CommandSubType_bits 2 +#define GEN45_3DSTATE_PIPELINED_POINTERS_CommandSubType_bits 2 +#define GEN4_3DSTATE_PIPELINED_POINTERS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PIPELINED_POINTERS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_3DSTATE_PIPELINED_POINTERS_CommandSubType_start 27 +#define GEN45_3DSTATE_PIPELINED_POINTERS_CommandSubType_start 27 +#define GEN4_3DSTATE_PIPELINED_POINTERS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PIPELINED_POINTERS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PIPELINED_POINTERS::Command Type */ + + +#define GEN5_3DSTATE_PIPELINED_POINTERS_CommandType_bits 3 +#define GEN45_3DSTATE_PIPELINED_POINTERS_CommandType_bits 3 +#define GEN4_3DSTATE_PIPELINED_POINTERS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PIPELINED_POINTERS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_3DSTATE_PIPELINED_POINTERS_CommandType_start 29 +#define GEN45_3DSTATE_PIPELINED_POINTERS_CommandType_start 29 +#define GEN4_3DSTATE_PIPELINED_POINTERS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PIPELINED_POINTERS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 29; + case 4: + if (devinfo->is_g4x) { + return 29; + } else { + return 29; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PIPELINED_POINTERS::DWord Length */ + + +#define GEN5_3DSTATE_PIPELINED_POINTERS_DWordLength_bits 8 +#define GEN45_3DSTATE_PIPELINED_POINTERS_DWordLength_bits 8 +#define GEN4_3DSTATE_PIPELINED_POINTERS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PIPELINED_POINTERS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_3DSTATE_PIPELINED_POINTERS_DWordLength_start 0 +#define GEN45_3DSTATE_PIPELINED_POINTERS_DWordLength_start 0 +#define GEN4_3DSTATE_PIPELINED_POINTERS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PIPELINED_POINTERS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PIPELINED_POINTERS::GS Enable */ + + +#define GEN5_3DSTATE_PIPELINED_POINTERS_GSEnable_bits 1 +#define GEN45_3DSTATE_PIPELINED_POINTERS_GSEnable_bits 1 +#define GEN4_3DSTATE_PIPELINED_POINTERS_GSEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PIPELINED_POINTERS_GSEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_3DSTATE_PIPELINED_POINTERS_GSEnable_start 64 +#define GEN45_3DSTATE_PIPELINED_POINTERS_GSEnable_start 64 +#define GEN4_3DSTATE_PIPELINED_POINTERS_GSEnable_start 64 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PIPELINED_POINTERS_GSEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 64; + case 4: + if (devinfo->is_g4x) { + return 64; + } else { + return 64; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PIPELINED_POINTERS::Pointer to CLIP State */ + + +#define GEN5_3DSTATE_PIPELINED_POINTERS_PointertoCLIPState_bits 27 +#define GEN45_3DSTATE_PIPELINED_POINTERS_PointertoCLIPState_bits 27 +#define GEN4_3DSTATE_PIPELINED_POINTERS_PointertoCLIPState_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PIPELINED_POINTERS_PointertoCLIPState_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_3DSTATE_PIPELINED_POINTERS_PointertoCLIPState_start 101 +#define GEN45_3DSTATE_PIPELINED_POINTERS_PointertoCLIPState_start 101 +#define GEN4_3DSTATE_PIPELINED_POINTERS_PointertoCLIPState_start 101 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PIPELINED_POINTERS_PointertoCLIPState_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 101; + case 4: + if (devinfo->is_g4x) { + return 101; + } else { + return 101; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PIPELINED_POINTERS::Pointer to Color Calc State */ + + +#define GEN5_3DSTATE_PIPELINED_POINTERS_PointertoColorCalcState_bits 27 +#define GEN45_3DSTATE_PIPELINED_POINTERS_PointertoColorCalcState_bits 27 +#define GEN4_3DSTATE_PIPELINED_POINTERS_PointertoColorCalcState_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PIPELINED_POINTERS_PointertoColorCalcState_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_3DSTATE_PIPELINED_POINTERS_PointertoColorCalcState_start 197 +#define GEN45_3DSTATE_PIPELINED_POINTERS_PointertoColorCalcState_start 197 +#define GEN4_3DSTATE_PIPELINED_POINTERS_PointertoColorCalcState_start 197 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PIPELINED_POINTERS_PointertoColorCalcState_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 197; + case 4: + if (devinfo->is_g4x) { + return 197; + } else { + return 197; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PIPELINED_POINTERS::Pointer to GS State */ + + +#define GEN5_3DSTATE_PIPELINED_POINTERS_PointertoGSState_bits 27 +#define GEN45_3DSTATE_PIPELINED_POINTERS_PointertoGSState_bits 27 +#define GEN4_3DSTATE_PIPELINED_POINTERS_PointertoGSState_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PIPELINED_POINTERS_PointertoGSState_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_3DSTATE_PIPELINED_POINTERS_PointertoGSState_start 69 +#define GEN45_3DSTATE_PIPELINED_POINTERS_PointertoGSState_start 69 +#define GEN4_3DSTATE_PIPELINED_POINTERS_PointertoGSState_start 69 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PIPELINED_POINTERS_PointertoGSState_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 69; + case 4: + if (devinfo->is_g4x) { + return 69; + } else { + return 69; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PIPELINED_POINTERS::Pointer to SF State */ + + +#define GEN5_3DSTATE_PIPELINED_POINTERS_PointertoSFState_bits 27 +#define GEN45_3DSTATE_PIPELINED_POINTERS_PointertoSFState_bits 27 +#define GEN4_3DSTATE_PIPELINED_POINTERS_PointertoSFState_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PIPELINED_POINTERS_PointertoSFState_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_3DSTATE_PIPELINED_POINTERS_PointertoSFState_start 133 +#define GEN45_3DSTATE_PIPELINED_POINTERS_PointertoSFState_start 133 +#define GEN4_3DSTATE_PIPELINED_POINTERS_PointertoSFState_start 133 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PIPELINED_POINTERS_PointertoSFState_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 133; + case 4: + if (devinfo->is_g4x) { + return 133; + } else { + return 133; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PIPELINED_POINTERS::Pointer to VS State */ + + +#define GEN5_3DSTATE_PIPELINED_POINTERS_PointertoVSState_bits 27 +#define GEN45_3DSTATE_PIPELINED_POINTERS_PointertoVSState_bits 27 +#define GEN4_3DSTATE_PIPELINED_POINTERS_PointertoVSState_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PIPELINED_POINTERS_PointertoVSState_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_3DSTATE_PIPELINED_POINTERS_PointertoVSState_start 37 +#define GEN45_3DSTATE_PIPELINED_POINTERS_PointertoVSState_start 37 +#define GEN4_3DSTATE_PIPELINED_POINTERS_PointertoVSState_start 37 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PIPELINED_POINTERS_PointertoVSState_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 37; + case 4: + if (devinfo->is_g4x) { + return 37; + } else { + return 37; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PIPELINED_POINTERS::Pointer to WM State */ + + +#define GEN5_3DSTATE_PIPELINED_POINTERS_PointertoWMState_bits 27 +#define GEN45_3DSTATE_PIPELINED_POINTERS_PointertoWMState_bits 27 +#define GEN4_3DSTATE_PIPELINED_POINTERS_PointertoWMState_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PIPELINED_POINTERS_PointertoWMState_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_3DSTATE_PIPELINED_POINTERS_PointertoWMState_start 165 +#define GEN45_3DSTATE_PIPELINED_POINTERS_PointertoWMState_start 165 +#define GEN4_3DSTATE_PIPELINED_POINTERS_PointertoWMState_start 165 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PIPELINED_POINTERS_PointertoWMState_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 165; + case 4: + if (devinfo->is_g4x) { + return 165; + } else { + return 165; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_POLY_STIPPLE_OFFSET */ + + +#define GEN11_3DSTATE_POLY_STIPPLE_OFFSET_length 2 +#define GEN10_3DSTATE_POLY_STIPPLE_OFFSET_length 2 +#define GEN9_3DSTATE_POLY_STIPPLE_OFFSET_length 2 +#define GEN8_3DSTATE_POLY_STIPPLE_OFFSET_length 2 +#define GEN75_3DSTATE_POLY_STIPPLE_OFFSET_length 2 +#define GEN7_3DSTATE_POLY_STIPPLE_OFFSET_length 2 +#define GEN6_3DSTATE_POLY_STIPPLE_OFFSET_length 2 +#define GEN5_3DSTATE_POLY_STIPPLE_OFFSET_length 2 +#define GEN45_3DSTATE_POLY_STIPPLE_OFFSET_length 2 +#define GEN4_3DSTATE_POLY_STIPPLE_OFFSET_length 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_POLY_STIPPLE_OFFSET_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_POLY_STIPPLE_OFFSET::3D Command Opcode */ + + +#define GEN11_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_bits 3 +#define GEN6_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_bits 3 +#define GEN5_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_bits 3 +#define GEN45_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_bits 3 +#define GEN4_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_start 24 +#define GEN6_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_start 24 +#define GEN5_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_start 24 +#define GEN45_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_start 24 +#define GEN4_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 24; + case 4: + if (devinfo->is_g4x) { + return 24; + } else { + return 24; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_POLY_STIPPLE_OFFSET::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_bits 8 +#define GEN6_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_bits 8 +#define GEN5_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_bits 8 +#define GEN45_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_bits 8 +#define GEN4_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_start 16 +#define GEN6_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_start 16 +#define GEN5_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_start 16 +#define GEN45_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_start 16 +#define GEN4_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_POLY_STIPPLE_OFFSET_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_POLY_STIPPLE_OFFSET::Command SubType */ + + +#define GEN11_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_bits 2 +#define GEN10_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_bits 2 +#define GEN9_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_bits 2 +#define GEN8_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_bits 2 +#define GEN75_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_bits 2 +#define GEN7_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_bits 2 +#define GEN6_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_bits 2 +#define GEN5_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_bits 2 +#define GEN45_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_bits 2 +#define GEN4_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_start 27 +#define GEN10_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_start 27 +#define GEN9_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_start 27 +#define GEN8_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_start 27 +#define GEN75_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_start 27 +#define GEN7_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_start 27 +#define GEN6_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_start 27 +#define GEN5_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_start 27 +#define GEN45_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_start 27 +#define GEN4_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_POLY_STIPPLE_OFFSET_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_POLY_STIPPLE_OFFSET::Command Type */ + + +#define GEN11_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_bits 3 +#define GEN10_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_bits 3 +#define GEN9_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_bits 3 +#define GEN8_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_bits 3 +#define GEN75_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_bits 3 +#define GEN7_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_bits 3 +#define GEN6_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_bits 3 +#define GEN5_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_bits 3 +#define GEN45_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_bits 3 +#define GEN4_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_start 29 +#define GEN10_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_start 29 +#define GEN9_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_start 29 +#define GEN8_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_start 29 +#define GEN75_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_start 29 +#define GEN7_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_start 29 +#define GEN6_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_start 29 +#define GEN5_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_start 29 +#define GEN45_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_start 29 +#define GEN4_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_POLY_STIPPLE_OFFSET_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 29; + case 4: + if (devinfo->is_g4x) { + return 29; + } else { + return 29; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_POLY_STIPPLE_OFFSET::DWord Length */ + + +#define GEN11_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_bits 8 +#define GEN10_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_bits 8 +#define GEN9_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_bits 8 +#define GEN8_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_bits 8 +#define GEN75_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_bits 8 +#define GEN7_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_bits 8 +#define GEN6_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_bits 8 +#define GEN5_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_bits 8 +#define GEN45_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_bits 8 +#define GEN4_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_start 0 +#define GEN10_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_start 0 +#define GEN9_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_start 0 +#define GEN8_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_start 0 +#define GEN75_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_start 0 +#define GEN7_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_start 0 +#define GEN6_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_start 0 +#define GEN5_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_start 0 +#define GEN45_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_start 0 +#define GEN4_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_POLY_STIPPLE_OFFSET_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_POLY_STIPPLE_OFFSET::Polygon Stipple X Offset */ + + +#define GEN11_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_bits 5 +#define GEN10_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_bits 5 +#define GEN9_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_bits 5 +#define GEN8_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_bits 5 +#define GEN75_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_bits 5 +#define GEN7_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_bits 5 +#define GEN6_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_bits 5 +#define GEN5_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_bits 5 +#define GEN45_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_bits 5 +#define GEN4_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 5; + } + case 6: return 5; + case 5: return 5; + case 4: + if (devinfo->is_g4x) { + return 5; + } else { + return 5; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_start 40 +#define GEN10_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_start 40 +#define GEN9_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_start 40 +#define GEN8_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_start 40 +#define GEN75_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_start 40 +#define GEN7_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_start 40 +#define GEN6_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_start 40 +#define GEN5_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_start 40 +#define GEN45_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_start 40 +#define GEN4_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_start 40 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleXOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 40; + case 10: return 40; + case 9: return 40; + case 8: return 40; + case 7: + if (devinfo->is_haswell) { + return 40; + } else { + return 40; + } + case 6: return 40; + case 5: return 40; + case 4: + if (devinfo->is_g4x) { + return 40; + } else { + return 40; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_POLY_STIPPLE_OFFSET::Polygon Stipple Y Offset */ + + +#define GEN11_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_bits 5 +#define GEN10_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_bits 5 +#define GEN9_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_bits 5 +#define GEN8_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_bits 5 +#define GEN75_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_bits 5 +#define GEN7_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_bits 5 +#define GEN6_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_bits 5 +#define GEN5_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_bits 5 +#define GEN45_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_bits 5 +#define GEN4_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 5; + } + case 6: return 5; + case 5: return 5; + case 4: + if (devinfo->is_g4x) { + return 5; + } else { + return 5; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_start 32 +#define GEN10_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_start 32 +#define GEN9_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_start 32 +#define GEN8_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_start 32 +#define GEN75_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_start 32 +#define GEN7_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_start 32 +#define GEN6_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_start 32 +#define GEN5_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_start 32 +#define GEN45_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_start 32 +#define GEN4_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_POLY_STIPPLE_OFFSET_PolygonStippleYOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_POLY_STIPPLE_PATTERN */ + + +#define GEN11_3DSTATE_POLY_STIPPLE_PATTERN_length 33 +#define GEN10_3DSTATE_POLY_STIPPLE_PATTERN_length 33 +#define GEN9_3DSTATE_POLY_STIPPLE_PATTERN_length 33 +#define GEN8_3DSTATE_POLY_STIPPLE_PATTERN_length 33 +#define GEN75_3DSTATE_POLY_STIPPLE_PATTERN_length 33 +#define GEN7_3DSTATE_POLY_STIPPLE_PATTERN_length 33 +#define GEN6_3DSTATE_POLY_STIPPLE_PATTERN_length 33 +#define GEN5_3DSTATE_POLY_STIPPLE_PATTERN_length 33 +#define GEN45_3DSTATE_POLY_STIPPLE_PATTERN_length 33 +#define GEN4_3DSTATE_POLY_STIPPLE_PATTERN_length 33 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_POLY_STIPPLE_PATTERN_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 33; + case 10: return 33; + case 9: return 33; + case 8: return 33; + case 7: + if (devinfo->is_haswell) { + return 33; + } else { + return 33; + } + case 6: return 33; + case 5: return 33; + case 4: + if (devinfo->is_g4x) { + return 33; + } else { + return 33; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_POLY_STIPPLE_PATTERN::3D Command Opcode */ + + +#define GEN11_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_bits 3 +#define GEN6_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_bits 3 +#define GEN5_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_bits 3 +#define GEN45_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_bits 3 +#define GEN4_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_start 24 +#define GEN6_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_start 24 +#define GEN5_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_start 24 +#define GEN45_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_start 24 +#define GEN4_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 24; + case 4: + if (devinfo->is_g4x) { + return 24; + } else { + return 24; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_POLY_STIPPLE_PATTERN::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_bits 8 +#define GEN6_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_bits 8 +#define GEN5_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_bits 8 +#define GEN45_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_bits 8 +#define GEN4_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_start 16 +#define GEN6_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_start 16 +#define GEN5_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_start 16 +#define GEN45_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_start 16 +#define GEN4_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_POLY_STIPPLE_PATTERN_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_POLY_STIPPLE_PATTERN::Command SubType */ + + +#define GEN11_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_bits 2 +#define GEN10_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_bits 2 +#define GEN9_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_bits 2 +#define GEN8_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_bits 2 +#define GEN75_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_bits 2 +#define GEN7_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_bits 2 +#define GEN6_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_bits 2 +#define GEN5_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_bits 2 +#define GEN45_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_bits 2 +#define GEN4_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_start 27 +#define GEN10_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_start 27 +#define GEN9_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_start 27 +#define GEN8_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_start 27 +#define GEN75_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_start 27 +#define GEN7_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_start 27 +#define GEN6_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_start 27 +#define GEN5_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_start 27 +#define GEN45_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_start 27 +#define GEN4_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_POLY_STIPPLE_PATTERN_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_POLY_STIPPLE_PATTERN::Command Type */ + + +#define GEN11_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_bits 3 +#define GEN10_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_bits 3 +#define GEN9_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_bits 3 +#define GEN8_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_bits 3 +#define GEN75_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_bits 3 +#define GEN7_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_bits 3 +#define GEN6_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_bits 3 +#define GEN5_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_bits 3 +#define GEN45_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_bits 3 +#define GEN4_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_start 29 +#define GEN10_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_start 29 +#define GEN9_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_start 29 +#define GEN8_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_start 29 +#define GEN75_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_start 29 +#define GEN7_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_start 29 +#define GEN6_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_start 29 +#define GEN5_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_start 29 +#define GEN45_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_start 29 +#define GEN4_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_POLY_STIPPLE_PATTERN_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 29; + case 4: + if (devinfo->is_g4x) { + return 29; + } else { + return 29; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_POLY_STIPPLE_PATTERN::DWord Length */ + + +#define GEN11_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_bits 8 +#define GEN10_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_bits 8 +#define GEN9_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_bits 8 +#define GEN8_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_bits 8 +#define GEN75_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_bits 8 +#define GEN7_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_bits 8 +#define GEN6_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_bits 8 +#define GEN5_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_bits 8 +#define GEN45_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_bits 8 +#define GEN4_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_start 0 +#define GEN10_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_start 0 +#define GEN9_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_start 0 +#define GEN8_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_start 0 +#define GEN75_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_start 0 +#define GEN7_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_start 0 +#define GEN6_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_start 0 +#define GEN5_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_start 0 +#define GEN45_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_start 0 +#define GEN4_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_POLY_STIPPLE_PATTERN_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_POLY_STIPPLE_PATTERN::Pattern Row */ + + +#define GEN11_3DSTATE_POLY_STIPPLE_PATTERN_PatternRow_bits 32 +#define GEN10_3DSTATE_POLY_STIPPLE_PATTERN_PatternRow_bits 32 +#define GEN9_3DSTATE_POLY_STIPPLE_PATTERN_PatternRow_bits 32 +#define GEN8_3DSTATE_POLY_STIPPLE_PATTERN_PatternRow_bits 32 +#define GEN75_3DSTATE_POLY_STIPPLE_PATTERN_PatternRow_bits 32 +#define GEN7_3DSTATE_POLY_STIPPLE_PATTERN_PatternRow_bits 32 +#define GEN6_3DSTATE_POLY_STIPPLE_PATTERN_PatternRow_bits 32 +#define GEN5_3DSTATE_POLY_STIPPLE_PATTERN_PatternRow_bits 32 +#define GEN45_3DSTATE_POLY_STIPPLE_PATTERN_PatternRow_bits 32 +#define GEN4_3DSTATE_POLY_STIPPLE_PATTERN_PatternRow_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_POLY_STIPPLE_PATTERN_PatternRow_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_POLY_STIPPLE_PATTERN_PatternRow_start 0 +#define GEN10_3DSTATE_POLY_STIPPLE_PATTERN_PatternRow_start 0 +#define GEN9_3DSTATE_POLY_STIPPLE_PATTERN_PatternRow_start 0 +#define GEN8_3DSTATE_POLY_STIPPLE_PATTERN_PatternRow_start 0 +#define GEN75_3DSTATE_POLY_STIPPLE_PATTERN_PatternRow_start 0 +#define GEN7_3DSTATE_POLY_STIPPLE_PATTERN_PatternRow_start 0 +#define GEN6_3DSTATE_POLY_STIPPLE_PATTERN_PatternRow_start 0 +#define GEN5_3DSTATE_POLY_STIPPLE_PATTERN_PatternRow_start 0 +#define GEN45_3DSTATE_POLY_STIPPLE_PATTERN_PatternRow_start 0 +#define GEN4_3DSTATE_POLY_STIPPLE_PATTERN_PatternRow_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_POLY_STIPPLE_PATTERN_PatternRow_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS */ + + +#define GEN11_3DSTATE_PS_length 12 +#define GEN10_3DSTATE_PS_length 12 +#define GEN9_3DSTATE_PS_length 12 +#define GEN8_3DSTATE_PS_length 12 +#define GEN75_3DSTATE_PS_length 8 +#define GEN7_3DSTATE_PS_length 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 12; + case 10: return 12; + case 9: return 12; + case 8: return 12; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::16 Pixel Dispatch Enable */ + + +#define GEN11_3DSTATE_PS_16PixelDispatchEnable_bits 1 +#define GEN10_3DSTATE_PS_16PixelDispatchEnable_bits 1 +#define GEN9_3DSTATE_PS_16PixelDispatchEnable_bits 1 +#define GEN8_3DSTATE_PS_16PixelDispatchEnable_bits 1 +#define GEN75_3DSTATE_PS_16PixelDispatchEnable_bits 1 +#define GEN7_3DSTATE_PS_16PixelDispatchEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_16PixelDispatchEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_16PixelDispatchEnable_start 193 +#define GEN10_3DSTATE_PS_16PixelDispatchEnable_start 193 +#define GEN9_3DSTATE_PS_16PixelDispatchEnable_start 193 +#define GEN8_3DSTATE_PS_16PixelDispatchEnable_start 193 +#define GEN75_3DSTATE_PS_16PixelDispatchEnable_start 129 +#define GEN7_3DSTATE_PS_16PixelDispatchEnable_start 129 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_16PixelDispatchEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 193; + case 10: return 193; + case 9: return 193; + case 8: return 193; + case 7: + if (devinfo->is_haswell) { + return 129; + } else { + return 129; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::32 Pixel Dispatch Enable */ + + +#define GEN11_3DSTATE_PS_32PixelDispatchEnable_bits 1 +#define GEN10_3DSTATE_PS_32PixelDispatchEnable_bits 1 +#define GEN9_3DSTATE_PS_32PixelDispatchEnable_bits 1 +#define GEN8_3DSTATE_PS_32PixelDispatchEnable_bits 1 +#define GEN75_3DSTATE_PS_32PixelDispatchEnable_bits 1 +#define GEN7_3DSTATE_PS_32PixelDispatchEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_32PixelDispatchEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_32PixelDispatchEnable_start 194 +#define GEN10_3DSTATE_PS_32PixelDispatchEnable_start 194 +#define GEN9_3DSTATE_PS_32PixelDispatchEnable_start 194 +#define GEN8_3DSTATE_PS_32PixelDispatchEnable_start 194 +#define GEN75_3DSTATE_PS_32PixelDispatchEnable_start 130 +#define GEN7_3DSTATE_PS_32PixelDispatchEnable_start 130 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_32PixelDispatchEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 194; + case 10: return 194; + case 9: return 194; + case 8: return 194; + case 7: + if (devinfo->is_haswell) { + return 130; + } else { + return 130; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::3D Command Opcode */ + + +#define GEN11_3DSTATE_PS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_PS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_PS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_PS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_PS_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_PS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_PS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_PS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_PS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_PS_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_PS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_PS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_PS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_PS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_PS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_PS_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_PS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_PS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_PS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_PS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_PS_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_PS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::8 Pixel Dispatch Enable */ + + +#define GEN11_3DSTATE_PS_8PixelDispatchEnable_bits 1 +#define GEN10_3DSTATE_PS_8PixelDispatchEnable_bits 1 +#define GEN9_3DSTATE_PS_8PixelDispatchEnable_bits 1 +#define GEN8_3DSTATE_PS_8PixelDispatchEnable_bits 1 +#define GEN75_3DSTATE_PS_8PixelDispatchEnable_bits 1 +#define GEN7_3DSTATE_PS_8PixelDispatchEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_8PixelDispatchEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_8PixelDispatchEnable_start 192 +#define GEN10_3DSTATE_PS_8PixelDispatchEnable_start 192 +#define GEN9_3DSTATE_PS_8PixelDispatchEnable_start 192 +#define GEN8_3DSTATE_PS_8PixelDispatchEnable_start 192 +#define GEN75_3DSTATE_PS_8PixelDispatchEnable_start 128 +#define GEN7_3DSTATE_PS_8PixelDispatchEnable_start 128 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_8PixelDispatchEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 192; + case 10: return 192; + case 9: return 192; + case 8: return 192; + case 7: + if (devinfo->is_haswell) { + return 128; + } else { + return 128; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::Attribute Enable */ + + +#define GEN75_3DSTATE_PS_AttributeEnable_bits 1 +#define GEN7_3DSTATE_PS_AttributeEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_AttributeEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_PS_AttributeEnable_start 138 +#define GEN7_3DSTATE_PS_AttributeEnable_start 138 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_AttributeEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 138; + } else { + return 138; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::Binding Table Entry Count */ + + +#define GEN11_3DSTATE_PS_BindingTableEntryCount_bits 8 +#define GEN10_3DSTATE_PS_BindingTableEntryCount_bits 8 +#define GEN9_3DSTATE_PS_BindingTableEntryCount_bits 8 +#define GEN8_3DSTATE_PS_BindingTableEntryCount_bits 8 +#define GEN75_3DSTATE_PS_BindingTableEntryCount_bits 8 +#define GEN7_3DSTATE_PS_BindingTableEntryCount_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_BindingTableEntryCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_BindingTableEntryCount_start 114 +#define GEN10_3DSTATE_PS_BindingTableEntryCount_start 114 +#define GEN9_3DSTATE_PS_BindingTableEntryCount_start 114 +#define GEN8_3DSTATE_PS_BindingTableEntryCount_start 114 +#define GEN75_3DSTATE_PS_BindingTableEntryCount_start 82 +#define GEN7_3DSTATE_PS_BindingTableEntryCount_start 82 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_BindingTableEntryCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 114; + case 10: return 114; + case 9: return 114; + case 8: return 114; + case 7: + if (devinfo->is_haswell) { + return 82; + } else { + return 82; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::Command SubType */ + + +#define GEN11_3DSTATE_PS_CommandSubType_bits 2 +#define GEN10_3DSTATE_PS_CommandSubType_bits 2 +#define GEN9_3DSTATE_PS_CommandSubType_bits 2 +#define GEN8_3DSTATE_PS_CommandSubType_bits 2 +#define GEN75_3DSTATE_PS_CommandSubType_bits 2 +#define GEN7_3DSTATE_PS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_CommandSubType_start 27 +#define GEN10_3DSTATE_PS_CommandSubType_start 27 +#define GEN9_3DSTATE_PS_CommandSubType_start 27 +#define GEN8_3DSTATE_PS_CommandSubType_start 27 +#define GEN75_3DSTATE_PS_CommandSubType_start 27 +#define GEN7_3DSTATE_PS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::Command Type */ + + +#define GEN11_3DSTATE_PS_CommandType_bits 3 +#define GEN10_3DSTATE_PS_CommandType_bits 3 +#define GEN9_3DSTATE_PS_CommandType_bits 3 +#define GEN8_3DSTATE_PS_CommandType_bits 3 +#define GEN75_3DSTATE_PS_CommandType_bits 3 +#define GEN7_3DSTATE_PS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_CommandType_start 29 +#define GEN10_3DSTATE_PS_CommandType_start 29 +#define GEN9_3DSTATE_PS_CommandType_start 29 +#define GEN8_3DSTATE_PS_CommandType_start 29 +#define GEN75_3DSTATE_PS_CommandType_start 29 +#define GEN7_3DSTATE_PS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::DWord Length */ + + +#define GEN11_3DSTATE_PS_DWordLength_bits 8 +#define GEN10_3DSTATE_PS_DWordLength_bits 8 +#define GEN9_3DSTATE_PS_DWordLength_bits 8 +#define GEN8_3DSTATE_PS_DWordLength_bits 8 +#define GEN75_3DSTATE_PS_DWordLength_bits 8 +#define GEN7_3DSTATE_PS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_DWordLength_start 0 +#define GEN10_3DSTATE_PS_DWordLength_start 0 +#define GEN9_3DSTATE_PS_DWordLength_start 0 +#define GEN8_3DSTATE_PS_DWordLength_start 0 +#define GEN75_3DSTATE_PS_DWordLength_start 0 +#define GEN7_3DSTATE_PS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::Denormal Mode */ + + +#define GEN75_3DSTATE_PS_DenormalMode_bits 1 +#define GEN7_3DSTATE_PS_DenormalMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_DenormalMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_PS_DenormalMode_start 90 +#define GEN7_3DSTATE_PS_DenormalMode_start 90 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_DenormalMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 90; + } else { + return 90; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::Dispatch GRF Start Register For Constant/Setup Data 0 */ + + +#define GEN11_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData0_bits 7 +#define GEN10_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData0_bits 7 +#define GEN9_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData0_bits 7 +#define GEN8_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData0_bits 7 +#define GEN75_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData0_bits 7 +#define GEN7_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData0_bits 7 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData0_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 7; + } else { + return 7; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData0_start 240 +#define GEN10_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData0_start 240 +#define GEN9_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData0_start 240 +#define GEN8_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData0_start 240 +#define GEN75_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData0_start 176 +#define GEN7_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData0_start 176 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData0_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 240; + case 10: return 240; + case 9: return 240; + case 8: return 240; + case 7: + if (devinfo->is_haswell) { + return 176; + } else { + return 176; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::Dispatch GRF Start Register For Constant/Setup Data 1 */ + + +#define GEN11_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData1_bits 7 +#define GEN10_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData1_bits 7 +#define GEN9_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData1_bits 7 +#define GEN8_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData1_bits 7 +#define GEN75_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData1_bits 7 +#define GEN7_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData1_bits 7 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData1_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 7; + } else { + return 7; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData1_start 232 +#define GEN10_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData1_start 232 +#define GEN9_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData1_start 232 +#define GEN8_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData1_start 232 +#define GEN75_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData1_start 168 +#define GEN7_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData1_start 168 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData1_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 232; + case 10: return 232; + case 9: return 232; + case 8: return 232; + case 7: + if (devinfo->is_haswell) { + return 168; + } else { + return 168; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::Dispatch GRF Start Register For Constant/Setup Data 2 */ + + +#define GEN11_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData2_bits 7 +#define GEN10_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData2_bits 7 +#define GEN9_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData2_bits 7 +#define GEN8_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData2_bits 7 +#define GEN75_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData2_bits 7 +#define GEN7_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData2_bits 7 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData2_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 7; + } else { + return 7; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData2_start 224 +#define GEN10_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData2_start 224 +#define GEN9_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData2_start 224 +#define GEN8_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData2_start 224 +#define GEN75_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData2_start 160 +#define GEN7_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData2_start 160 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_DispatchGRFStartRegisterForConstantSetupData2_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 224; + case 10: return 224; + case 9: return 224; + case 8: return 224; + case 7: + if (devinfo->is_haswell) { + return 160; + } else { + return 160; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::Dual Source Blend Enable */ + + +#define GEN75_3DSTATE_PS_DualSourceBlendEnable_bits 1 +#define GEN7_3DSTATE_PS_DualSourceBlendEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_DualSourceBlendEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_PS_DualSourceBlendEnable_start 135 +#define GEN7_3DSTATE_PS_DualSourceBlendEnable_start 135 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_DualSourceBlendEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 135; + } else { + return 135; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::Floating Point Mode */ + + +#define GEN11_3DSTATE_PS_FloatingPointMode_bits 1 +#define GEN10_3DSTATE_PS_FloatingPointMode_bits 1 +#define GEN9_3DSTATE_PS_FloatingPointMode_bits 1 +#define GEN8_3DSTATE_PS_FloatingPointMode_bits 1 +#define GEN75_3DSTATE_PS_FloatingPointMode_bits 1 +#define GEN7_3DSTATE_PS_FloatingPointMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_FloatingPointMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_FloatingPointMode_start 112 +#define GEN10_3DSTATE_PS_FloatingPointMode_start 112 +#define GEN9_3DSTATE_PS_FloatingPointMode_start 112 +#define GEN8_3DSTATE_PS_FloatingPointMode_start 112 +#define GEN75_3DSTATE_PS_FloatingPointMode_start 80 +#define GEN7_3DSTATE_PS_FloatingPointMode_start 80 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_FloatingPointMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 112; + case 10: return 112; + case 9: return 112; + case 8: return 112; + case 7: + if (devinfo->is_haswell) { + return 80; + } else { + return 80; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::Illegal Opcode Exception Enable */ + + +#define GEN11_3DSTATE_PS_IllegalOpcodeExceptionEnable_bits 1 +#define GEN10_3DSTATE_PS_IllegalOpcodeExceptionEnable_bits 1 +#define GEN9_3DSTATE_PS_IllegalOpcodeExceptionEnable_bits 1 +#define GEN8_3DSTATE_PS_IllegalOpcodeExceptionEnable_bits 1 +#define GEN75_3DSTATE_PS_IllegalOpcodeExceptionEnable_bits 1 +#define GEN7_3DSTATE_PS_IllegalOpcodeExceptionEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_IllegalOpcodeExceptionEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_IllegalOpcodeExceptionEnable_start 109 +#define GEN10_3DSTATE_PS_IllegalOpcodeExceptionEnable_start 109 +#define GEN9_3DSTATE_PS_IllegalOpcodeExceptionEnable_start 109 +#define GEN8_3DSTATE_PS_IllegalOpcodeExceptionEnable_start 109 +#define GEN75_3DSTATE_PS_IllegalOpcodeExceptionEnable_start 77 +#define GEN7_3DSTATE_PS_IllegalOpcodeExceptionEnable_start 77 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_IllegalOpcodeExceptionEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 109; + case 10: return 109; + case 9: return 109; + case 8: return 109; + case 7: + if (devinfo->is_haswell) { + return 77; + } else { + return 77; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::Kernel Start Pointer 0 */ + + +#define GEN11_3DSTATE_PS_KernelStartPointer0_bits 58 +#define GEN10_3DSTATE_PS_KernelStartPointer0_bits 58 +#define GEN9_3DSTATE_PS_KernelStartPointer0_bits 58 +#define GEN8_3DSTATE_PS_KernelStartPointer0_bits 58 +#define GEN75_3DSTATE_PS_KernelStartPointer0_bits 26 +#define GEN7_3DSTATE_PS_KernelStartPointer0_bits 26 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_KernelStartPointer0_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 58; + case 10: return 58; + case 9: return 58; + case 8: return 58; + case 7: + if (devinfo->is_haswell) { + return 26; + } else { + return 26; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_KernelStartPointer0_start 38 +#define GEN10_3DSTATE_PS_KernelStartPointer0_start 38 +#define GEN9_3DSTATE_PS_KernelStartPointer0_start 38 +#define GEN8_3DSTATE_PS_KernelStartPointer0_start 38 +#define GEN75_3DSTATE_PS_KernelStartPointer0_start 38 +#define GEN7_3DSTATE_PS_KernelStartPointer0_start 38 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_KernelStartPointer0_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 38; + case 10: return 38; + case 9: return 38; + case 8: return 38; + case 7: + if (devinfo->is_haswell) { + return 38; + } else { + return 38; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::Kernel Start Pointer 1 */ + + +#define GEN11_3DSTATE_PS_KernelStartPointer1_bits 58 +#define GEN10_3DSTATE_PS_KernelStartPointer1_bits 58 +#define GEN9_3DSTATE_PS_KernelStartPointer1_bits 58 +#define GEN8_3DSTATE_PS_KernelStartPointer1_bits 58 +#define GEN75_3DSTATE_PS_KernelStartPointer1_bits 26 +#define GEN7_3DSTATE_PS_KernelStartPointer1_bits 26 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_KernelStartPointer1_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 58; + case 10: return 58; + case 9: return 58; + case 8: return 58; + case 7: + if (devinfo->is_haswell) { + return 26; + } else { + return 26; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_KernelStartPointer1_start 262 +#define GEN10_3DSTATE_PS_KernelStartPointer1_start 262 +#define GEN9_3DSTATE_PS_KernelStartPointer1_start 262 +#define GEN8_3DSTATE_PS_KernelStartPointer1_start 262 +#define GEN75_3DSTATE_PS_KernelStartPointer1_start 198 +#define GEN7_3DSTATE_PS_KernelStartPointer1_start 198 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_KernelStartPointer1_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 262; + case 10: return 262; + case 9: return 262; + case 8: return 262; + case 7: + if (devinfo->is_haswell) { + return 198; + } else { + return 198; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::Kernel Start Pointer 2 */ + + +#define GEN11_3DSTATE_PS_KernelStartPointer2_bits 58 +#define GEN10_3DSTATE_PS_KernelStartPointer2_bits 58 +#define GEN9_3DSTATE_PS_KernelStartPointer2_bits 58 +#define GEN8_3DSTATE_PS_KernelStartPointer2_bits 58 +#define GEN75_3DSTATE_PS_KernelStartPointer2_bits 26 +#define GEN7_3DSTATE_PS_KernelStartPointer2_bits 26 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_KernelStartPointer2_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 58; + case 10: return 58; + case 9: return 58; + case 8: return 58; + case 7: + if (devinfo->is_haswell) { + return 26; + } else { + return 26; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_KernelStartPointer2_start 326 +#define GEN10_3DSTATE_PS_KernelStartPointer2_start 326 +#define GEN9_3DSTATE_PS_KernelStartPointer2_start 326 +#define GEN8_3DSTATE_PS_KernelStartPointer2_start 326 +#define GEN75_3DSTATE_PS_KernelStartPointer2_start 230 +#define GEN7_3DSTATE_PS_KernelStartPointer2_start 230 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_KernelStartPointer2_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 326; + case 10: return 326; + case 9: return 326; + case 8: return 326; + case 7: + if (devinfo->is_haswell) { + return 230; + } else { + return 230; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::Mask Stack Exception Enable */ + + +#define GEN11_3DSTATE_PS_MaskStackExceptionEnable_bits 1 +#define GEN10_3DSTATE_PS_MaskStackExceptionEnable_bits 1 +#define GEN9_3DSTATE_PS_MaskStackExceptionEnable_bits 1 +#define GEN8_3DSTATE_PS_MaskStackExceptionEnable_bits 1 +#define GEN75_3DSTATE_PS_MaskStackExceptionEnable_bits 1 +#define GEN7_3DSTATE_PS_MaskStackExceptionEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_MaskStackExceptionEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_MaskStackExceptionEnable_start 107 +#define GEN10_3DSTATE_PS_MaskStackExceptionEnable_start 107 +#define GEN9_3DSTATE_PS_MaskStackExceptionEnable_start 107 +#define GEN8_3DSTATE_PS_MaskStackExceptionEnable_start 107 +#define GEN75_3DSTATE_PS_MaskStackExceptionEnable_start 75 +#define GEN7_3DSTATE_PS_MaskStackExceptionEnable_start 75 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_MaskStackExceptionEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 107; + case 10: return 107; + case 9: return 107; + case 8: return 107; + case 7: + if (devinfo->is_haswell) { + return 75; + } else { + return 75; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::Maximum Number of Threads */ + + +#define GEN75_3DSTATE_PS_MaximumNumberofThreads_bits 9 +#define GEN7_3DSTATE_PS_MaximumNumberofThreads_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_MaximumNumberofThreads_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_PS_MaximumNumberofThreads_start 151 +#define GEN7_3DSTATE_PS_MaximumNumberofThreads_start 152 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_MaximumNumberofThreads_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 151; + } else { + return 152; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::Maximum Number of Threads Per PSD */ + + +#define GEN11_3DSTATE_PS_MaximumNumberofThreadsPerPSD_bits 9 +#define GEN10_3DSTATE_PS_MaximumNumberofThreadsPerPSD_bits 9 +#define GEN9_3DSTATE_PS_MaximumNumberofThreadsPerPSD_bits 9 +#define GEN8_3DSTATE_PS_MaximumNumberofThreadsPerPSD_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_MaximumNumberofThreadsPerPSD_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 9; + case 10: return 9; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_MaximumNumberofThreadsPerPSD_start 215 +#define GEN10_3DSTATE_PS_MaximumNumberofThreadsPerPSD_start 215 +#define GEN9_3DSTATE_PS_MaximumNumberofThreadsPerPSD_start 215 +#define GEN8_3DSTATE_PS_MaximumNumberofThreadsPerPSD_start 215 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_MaximumNumberofThreadsPerPSD_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 215; + case 10: return 215; + case 9: return 215; + case 8: return 215; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::PS Accesses UAV */ + + +#define GEN75_3DSTATE_PS_PSAccessesUAV_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_PSAccessesUAV_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_PS_PSAccessesUAV_start 133 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_PSAccessesUAV_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 133; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::Per Thread Scratch Space */ + + +#define GEN11_3DSTATE_PS_PerThreadScratchSpace_bits 4 +#define GEN10_3DSTATE_PS_PerThreadScratchSpace_bits 4 +#define GEN9_3DSTATE_PS_PerThreadScratchSpace_bits 4 +#define GEN8_3DSTATE_PS_PerThreadScratchSpace_bits 4 +#define GEN75_3DSTATE_PS_PerThreadScratchSpace_bits 4 +#define GEN7_3DSTATE_PS_PerThreadScratchSpace_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_PerThreadScratchSpace_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_PerThreadScratchSpace_start 128 +#define GEN10_3DSTATE_PS_PerThreadScratchSpace_start 128 +#define GEN9_3DSTATE_PS_PerThreadScratchSpace_start 128 +#define GEN8_3DSTATE_PS_PerThreadScratchSpace_start 128 +#define GEN75_3DSTATE_PS_PerThreadScratchSpace_start 96 +#define GEN7_3DSTATE_PS_PerThreadScratchSpace_start 96 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_PerThreadScratchSpace_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 128; + case 10: return 128; + case 9: return 128; + case 8: return 128; + case 7: + if (devinfo->is_haswell) { + return 96; + } else { + return 96; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::Position XY Offset Select */ + + +#define GEN11_3DSTATE_PS_PositionXYOffsetSelect_bits 2 +#define GEN10_3DSTATE_PS_PositionXYOffsetSelect_bits 2 +#define GEN9_3DSTATE_PS_PositionXYOffsetSelect_bits 2 +#define GEN8_3DSTATE_PS_PositionXYOffsetSelect_bits 2 +#define GEN75_3DSTATE_PS_PositionXYOffsetSelect_bits 2 +#define GEN7_3DSTATE_PS_PositionXYOffsetSelect_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_PositionXYOffsetSelect_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_PositionXYOffsetSelect_start 195 +#define GEN10_3DSTATE_PS_PositionXYOffsetSelect_start 195 +#define GEN9_3DSTATE_PS_PositionXYOffsetSelect_start 195 +#define GEN8_3DSTATE_PS_PositionXYOffsetSelect_start 195 +#define GEN75_3DSTATE_PS_PositionXYOffsetSelect_start 131 +#define GEN7_3DSTATE_PS_PositionXYOffsetSelect_start 131 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_PositionXYOffsetSelect_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 195; + case 10: return 195; + case 9: return 195; + case 8: return 195; + case 7: + if (devinfo->is_haswell) { + return 131; + } else { + return 131; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::Push Constant Enable */ + + +#define GEN11_3DSTATE_PS_PushConstantEnable_bits 1 +#define GEN10_3DSTATE_PS_PushConstantEnable_bits 1 +#define GEN9_3DSTATE_PS_PushConstantEnable_bits 1 +#define GEN8_3DSTATE_PS_PushConstantEnable_bits 1 +#define GEN75_3DSTATE_PS_PushConstantEnable_bits 1 +#define GEN7_3DSTATE_PS_PushConstantEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_PushConstantEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_PushConstantEnable_start 203 +#define GEN10_3DSTATE_PS_PushConstantEnable_start 203 +#define GEN9_3DSTATE_PS_PushConstantEnable_start 203 +#define GEN8_3DSTATE_PS_PushConstantEnable_start 203 +#define GEN75_3DSTATE_PS_PushConstantEnable_start 139 +#define GEN7_3DSTATE_PS_PushConstantEnable_start 139 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_PushConstantEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 203; + case 10: return 203; + case 9: return 203; + case 8: return 203; + case 7: + if (devinfo->is_haswell) { + return 139; + } else { + return 139; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::Render Target Fast Clear Enable */ + + +#define GEN11_3DSTATE_PS_RenderTargetFastClearEnable_bits 1 +#define GEN10_3DSTATE_PS_RenderTargetFastClearEnable_bits 1 +#define GEN9_3DSTATE_PS_RenderTargetFastClearEnable_bits 1 +#define GEN8_3DSTATE_PS_RenderTargetFastClearEnable_bits 1 +#define GEN75_3DSTATE_PS_RenderTargetFastClearEnable_bits 1 +#define GEN7_3DSTATE_PS_RenderTargetFastClearEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_RenderTargetFastClearEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_RenderTargetFastClearEnable_start 200 +#define GEN10_3DSTATE_PS_RenderTargetFastClearEnable_start 200 +#define GEN9_3DSTATE_PS_RenderTargetFastClearEnable_start 200 +#define GEN8_3DSTATE_PS_RenderTargetFastClearEnable_start 200 +#define GEN75_3DSTATE_PS_RenderTargetFastClearEnable_start 136 +#define GEN7_3DSTATE_PS_RenderTargetFastClearEnable_start 136 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_RenderTargetFastClearEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 200; + case 10: return 200; + case 9: return 200; + case 8: return 200; + case 7: + if (devinfo->is_haswell) { + return 136; + } else { + return 136; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::Render Target Resolve Enable */ + + +#define GEN8_3DSTATE_PS_RenderTargetResolveEnable_bits 1 +#define GEN75_3DSTATE_PS_RenderTargetResolveEnable_bits 1 +#define GEN7_3DSTATE_PS_RenderTargetResolveEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_RenderTargetResolveEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_3DSTATE_PS_RenderTargetResolveEnable_start 198 +#define GEN75_3DSTATE_PS_RenderTargetResolveEnable_start 134 +#define GEN7_3DSTATE_PS_RenderTargetResolveEnable_start 134 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_RenderTargetResolveEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 198; + case 7: + if (devinfo->is_haswell) { + return 134; + } else { + return 134; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::Render Target Resolve Type */ + + +#define GEN11_3DSTATE_PS_RenderTargetResolveType_bits 2 +#define GEN10_3DSTATE_PS_RenderTargetResolveType_bits 2 +#define GEN9_3DSTATE_PS_RenderTargetResolveType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_RenderTargetResolveType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_RenderTargetResolveType_start 198 +#define GEN10_3DSTATE_PS_RenderTargetResolveType_start 198 +#define GEN9_3DSTATE_PS_RenderTargetResolveType_start 198 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_RenderTargetResolveType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 198; + case 10: return 198; + case 9: return 198; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::Rounding Mode */ + + +#define GEN11_3DSTATE_PS_RoundingMode_bits 2 +#define GEN10_3DSTATE_PS_RoundingMode_bits 2 +#define GEN9_3DSTATE_PS_RoundingMode_bits 2 +#define GEN8_3DSTATE_PS_RoundingMode_bits 2 +#define GEN75_3DSTATE_PS_RoundingMode_bits 2 +#define GEN7_3DSTATE_PS_RoundingMode_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_RoundingMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_RoundingMode_start 110 +#define GEN10_3DSTATE_PS_RoundingMode_start 110 +#define GEN9_3DSTATE_PS_RoundingMode_start 110 +#define GEN8_3DSTATE_PS_RoundingMode_start 110 +#define GEN75_3DSTATE_PS_RoundingMode_start 78 +#define GEN7_3DSTATE_PS_RoundingMode_start 78 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_RoundingMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 110; + case 10: return 110; + case 9: return 110; + case 8: return 110; + case 7: + if (devinfo->is_haswell) { + return 78; + } else { + return 78; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::Sample Mask */ + + +#define GEN75_3DSTATE_PS_SampleMask_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_SampleMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_PS_SampleMask_start 140 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_SampleMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 140; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::Sampler Count */ + + +#define GEN11_3DSTATE_PS_SamplerCount_bits 3 +#define GEN10_3DSTATE_PS_SamplerCount_bits 3 +#define GEN9_3DSTATE_PS_SamplerCount_bits 3 +#define GEN8_3DSTATE_PS_SamplerCount_bits 3 +#define GEN75_3DSTATE_PS_SamplerCount_bits 3 +#define GEN7_3DSTATE_PS_SamplerCount_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_SamplerCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_SamplerCount_start 123 +#define GEN10_3DSTATE_PS_SamplerCount_start 123 +#define GEN9_3DSTATE_PS_SamplerCount_start 123 +#define GEN8_3DSTATE_PS_SamplerCount_start 123 +#define GEN75_3DSTATE_PS_SamplerCount_start 91 +#define GEN7_3DSTATE_PS_SamplerCount_start 91 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_SamplerCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 123; + case 10: return 123; + case 9: return 123; + case 8: return 123; + case 7: + if (devinfo->is_haswell) { + return 91; + } else { + return 91; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::Scratch Space Base Pointer */ + + +#define GEN11_3DSTATE_PS_ScratchSpaceBasePointer_bits 54 +#define GEN10_3DSTATE_PS_ScratchSpaceBasePointer_bits 54 +#define GEN9_3DSTATE_PS_ScratchSpaceBasePointer_bits 54 +#define GEN8_3DSTATE_PS_ScratchSpaceBasePointer_bits 54 +#define GEN75_3DSTATE_PS_ScratchSpaceBasePointer_bits 22 +#define GEN7_3DSTATE_PS_ScratchSpaceBasePointer_bits 22 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_ScratchSpaceBasePointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 54; + case 10: return 54; + case 9: return 54; + case 8: return 54; + case 7: + if (devinfo->is_haswell) { + return 22; + } else { + return 22; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_ScratchSpaceBasePointer_start 138 +#define GEN10_3DSTATE_PS_ScratchSpaceBasePointer_start 138 +#define GEN9_3DSTATE_PS_ScratchSpaceBasePointer_start 138 +#define GEN8_3DSTATE_PS_ScratchSpaceBasePointer_start 138 +#define GEN75_3DSTATE_PS_ScratchSpaceBasePointer_start 106 +#define GEN7_3DSTATE_PS_ScratchSpaceBasePointer_start 106 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_ScratchSpaceBasePointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 138; + case 10: return 138; + case 9: return 138; + case 8: return 138; + case 7: + if (devinfo->is_haswell) { + return 106; + } else { + return 106; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::Single Precision Denormal Mode */ + + +#define GEN11_3DSTATE_PS_SinglePrecisionDenormalMode_bits 1 +#define GEN10_3DSTATE_PS_SinglePrecisionDenormalMode_bits 1 +#define GEN9_3DSTATE_PS_SinglePrecisionDenormalMode_bits 1 +#define GEN8_3DSTATE_PS_SinglePrecisionDenormalMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_SinglePrecisionDenormalMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_SinglePrecisionDenormalMode_start 122 +#define GEN10_3DSTATE_PS_SinglePrecisionDenormalMode_start 122 +#define GEN9_3DSTATE_PS_SinglePrecisionDenormalMode_start 122 +#define GEN8_3DSTATE_PS_SinglePrecisionDenormalMode_start 122 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_SinglePrecisionDenormalMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 122; + case 10: return 122; + case 9: return 122; + case 8: return 122; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::Single Program Flow */ + + +#define GEN11_3DSTATE_PS_SingleProgramFlow_bits 1 +#define GEN10_3DSTATE_PS_SingleProgramFlow_bits 1 +#define GEN9_3DSTATE_PS_SingleProgramFlow_bits 1 +#define GEN8_3DSTATE_PS_SingleProgramFlow_bits 1 +#define GEN75_3DSTATE_PS_SingleProgramFlow_bits 1 +#define GEN7_3DSTATE_PS_SingleProgramFlow_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_SingleProgramFlow_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_SingleProgramFlow_start 127 +#define GEN10_3DSTATE_PS_SingleProgramFlow_start 127 +#define GEN9_3DSTATE_PS_SingleProgramFlow_start 127 +#define GEN8_3DSTATE_PS_SingleProgramFlow_start 127 +#define GEN75_3DSTATE_PS_SingleProgramFlow_start 95 +#define GEN7_3DSTATE_PS_SingleProgramFlow_start 95 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_SingleProgramFlow_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 127; + case 10: return 127; + case 9: return 127; + case 8: return 127; + case 7: + if (devinfo->is_haswell) { + return 95; + } else { + return 95; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::Software Exception Enable */ + + +#define GEN11_3DSTATE_PS_SoftwareExceptionEnable_bits 1 +#define GEN10_3DSTATE_PS_SoftwareExceptionEnable_bits 1 +#define GEN9_3DSTATE_PS_SoftwareExceptionEnable_bits 1 +#define GEN8_3DSTATE_PS_SoftwareExceptionEnable_bits 1 +#define GEN75_3DSTATE_PS_SoftwareExceptionEnable_bits 1 +#define GEN7_3DSTATE_PS_SoftwareExceptionEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_SoftwareExceptionEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_SoftwareExceptionEnable_start 103 +#define GEN10_3DSTATE_PS_SoftwareExceptionEnable_start 103 +#define GEN9_3DSTATE_PS_SoftwareExceptionEnable_start 103 +#define GEN8_3DSTATE_PS_SoftwareExceptionEnable_start 103 +#define GEN75_3DSTATE_PS_SoftwareExceptionEnable_start 71 +#define GEN7_3DSTATE_PS_SoftwareExceptionEnable_start 71 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_SoftwareExceptionEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 103; + case 10: return 103; + case 9: return 103; + case 8: return 103; + case 7: + if (devinfo->is_haswell) { + return 71; + } else { + return 71; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::Thread Dispatch Priority */ + + +#define GEN11_3DSTATE_PS_ThreadDispatchPriority_bits 1 +#define GEN10_3DSTATE_PS_ThreadDispatchPriority_bits 1 +#define GEN9_3DSTATE_PS_ThreadDispatchPriority_bits 1 +#define GEN8_3DSTATE_PS_ThreadDispatchPriority_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_ThreadDispatchPriority_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_ThreadDispatchPriority_start 113 +#define GEN10_3DSTATE_PS_ThreadDispatchPriority_start 113 +#define GEN9_3DSTATE_PS_ThreadDispatchPriority_start 113 +#define GEN8_3DSTATE_PS_ThreadDispatchPriority_start 113 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_ThreadDispatchPriority_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 113; + case 10: return 113; + case 9: return 113; + case 8: return 113; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::Thread Priority */ + + +#define GEN75_3DSTATE_PS_ThreadPriority_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_ThreadPriority_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_PS_ThreadPriority_start 81 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_ThreadPriority_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 81; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::Vector Mask Enable */ + + +#define GEN11_3DSTATE_PS_VectorMaskEnable_bits 1 +#define GEN10_3DSTATE_PS_VectorMaskEnable_bits 1 +#define GEN9_3DSTATE_PS_VectorMaskEnable_bits 1 +#define GEN8_3DSTATE_PS_VectorMaskEnable_bits 1 +#define GEN75_3DSTATE_PS_VectorMaskEnable_bits 1 +#define GEN7_3DSTATE_PS_VectorMaskEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_VectorMaskEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_VectorMaskEnable_start 126 +#define GEN10_3DSTATE_PS_VectorMaskEnable_start 126 +#define GEN9_3DSTATE_PS_VectorMaskEnable_start 126 +#define GEN8_3DSTATE_PS_VectorMaskEnable_start 126 +#define GEN75_3DSTATE_PS_VectorMaskEnable_start 94 +#define GEN7_3DSTATE_PS_VectorMaskEnable_start 94 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_VectorMaskEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 126; + case 10: return 126; + case 9: return 126; + case 8: return 126; + case 7: + if (devinfo->is_haswell) { + return 94; + } else { + return 94; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS::oMask Present to RenderTarget */ + + +#define GEN75_3DSTATE_PS_oMaskPresenttoRenderTarget_bits 1 +#define GEN7_3DSTATE_PS_oMaskPresenttoRenderTarget_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_oMaskPresenttoRenderTarget_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_PS_oMaskPresenttoRenderTarget_start 137 +#define GEN7_3DSTATE_PS_oMaskPresenttoRenderTarget_start 137 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_oMaskPresenttoRenderTarget_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 137; + } else { + return 137; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_BLEND */ + + +#define GEN11_3DSTATE_PS_BLEND_length 2 +#define GEN10_3DSTATE_PS_BLEND_length 2 +#define GEN9_3DSTATE_PS_BLEND_length 2 +#define GEN8_3DSTATE_PS_BLEND_length 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_BLEND_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_BLEND::3D Command Opcode */ + + +#define GEN11_3DSTATE_PS_BLEND_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_PS_BLEND_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_PS_BLEND_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_PS_BLEND_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_BLEND_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_BLEND_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_PS_BLEND_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_PS_BLEND_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_PS_BLEND_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_BLEND_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_BLEND::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_PS_BLEND_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_PS_BLEND_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_PS_BLEND_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_PS_BLEND_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_BLEND_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_BLEND_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_PS_BLEND_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_PS_BLEND_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_PS_BLEND_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_BLEND_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_BLEND::Alpha Test Enable */ + + +#define GEN11_3DSTATE_PS_BLEND_AlphaTestEnable_bits 1 +#define GEN10_3DSTATE_PS_BLEND_AlphaTestEnable_bits 1 +#define GEN9_3DSTATE_PS_BLEND_AlphaTestEnable_bits 1 +#define GEN8_3DSTATE_PS_BLEND_AlphaTestEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_BLEND_AlphaTestEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_BLEND_AlphaTestEnable_start 40 +#define GEN10_3DSTATE_PS_BLEND_AlphaTestEnable_start 40 +#define GEN9_3DSTATE_PS_BLEND_AlphaTestEnable_start 40 +#define GEN8_3DSTATE_PS_BLEND_AlphaTestEnable_start 40 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_BLEND_AlphaTestEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 40; + case 10: return 40; + case 9: return 40; + case 8: return 40; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_BLEND::Alpha To Coverage Enable */ + + +#define GEN11_3DSTATE_PS_BLEND_AlphaToCoverageEnable_bits 1 +#define GEN10_3DSTATE_PS_BLEND_AlphaToCoverageEnable_bits 1 +#define GEN9_3DSTATE_PS_BLEND_AlphaToCoverageEnable_bits 1 +#define GEN8_3DSTATE_PS_BLEND_AlphaToCoverageEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_BLEND_AlphaToCoverageEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_BLEND_AlphaToCoverageEnable_start 63 +#define GEN10_3DSTATE_PS_BLEND_AlphaToCoverageEnable_start 63 +#define GEN9_3DSTATE_PS_BLEND_AlphaToCoverageEnable_start 63 +#define GEN8_3DSTATE_PS_BLEND_AlphaToCoverageEnable_start 63 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_BLEND_AlphaToCoverageEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 63; + case 10: return 63; + case 9: return 63; + case 8: return 63; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_BLEND::Color Buffer Blend Enable */ + + +#define GEN11_3DSTATE_PS_BLEND_ColorBufferBlendEnable_bits 1 +#define GEN10_3DSTATE_PS_BLEND_ColorBufferBlendEnable_bits 1 +#define GEN9_3DSTATE_PS_BLEND_ColorBufferBlendEnable_bits 1 +#define GEN8_3DSTATE_PS_BLEND_ColorBufferBlendEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_BLEND_ColorBufferBlendEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_BLEND_ColorBufferBlendEnable_start 61 +#define GEN10_3DSTATE_PS_BLEND_ColorBufferBlendEnable_start 61 +#define GEN9_3DSTATE_PS_BLEND_ColorBufferBlendEnable_start 61 +#define GEN8_3DSTATE_PS_BLEND_ColorBufferBlendEnable_start 61 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_BLEND_ColorBufferBlendEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 61; + case 10: return 61; + case 9: return 61; + case 8: return 61; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_BLEND::Command SubType */ + + +#define GEN11_3DSTATE_PS_BLEND_CommandSubType_bits 2 +#define GEN10_3DSTATE_PS_BLEND_CommandSubType_bits 2 +#define GEN9_3DSTATE_PS_BLEND_CommandSubType_bits 2 +#define GEN8_3DSTATE_PS_BLEND_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_BLEND_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_BLEND_CommandSubType_start 27 +#define GEN10_3DSTATE_PS_BLEND_CommandSubType_start 27 +#define GEN9_3DSTATE_PS_BLEND_CommandSubType_start 27 +#define GEN8_3DSTATE_PS_BLEND_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_BLEND_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_BLEND::Command Type */ + + +#define GEN11_3DSTATE_PS_BLEND_CommandType_bits 3 +#define GEN10_3DSTATE_PS_BLEND_CommandType_bits 3 +#define GEN9_3DSTATE_PS_BLEND_CommandType_bits 3 +#define GEN8_3DSTATE_PS_BLEND_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_BLEND_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_BLEND_CommandType_start 29 +#define GEN10_3DSTATE_PS_BLEND_CommandType_start 29 +#define GEN9_3DSTATE_PS_BLEND_CommandType_start 29 +#define GEN8_3DSTATE_PS_BLEND_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_BLEND_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_BLEND::DWord Length */ + + +#define GEN11_3DSTATE_PS_BLEND_DWordLength_bits 8 +#define GEN10_3DSTATE_PS_BLEND_DWordLength_bits 8 +#define GEN9_3DSTATE_PS_BLEND_DWordLength_bits 8 +#define GEN8_3DSTATE_PS_BLEND_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_BLEND_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_BLEND_DWordLength_start 0 +#define GEN10_3DSTATE_PS_BLEND_DWordLength_start 0 +#define GEN9_3DSTATE_PS_BLEND_DWordLength_start 0 +#define GEN8_3DSTATE_PS_BLEND_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_BLEND_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_BLEND::Destination Alpha Blend Factor */ + + +#define GEN11_3DSTATE_PS_BLEND_DestinationAlphaBlendFactor_bits 5 +#define GEN10_3DSTATE_PS_BLEND_DestinationAlphaBlendFactor_bits 5 +#define GEN9_3DSTATE_PS_BLEND_DestinationAlphaBlendFactor_bits 5 +#define GEN8_3DSTATE_PS_BLEND_DestinationAlphaBlendFactor_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_BLEND_DestinationAlphaBlendFactor_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_BLEND_DestinationAlphaBlendFactor_start 51 +#define GEN10_3DSTATE_PS_BLEND_DestinationAlphaBlendFactor_start 51 +#define GEN9_3DSTATE_PS_BLEND_DestinationAlphaBlendFactor_start 51 +#define GEN8_3DSTATE_PS_BLEND_DestinationAlphaBlendFactor_start 51 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_BLEND_DestinationAlphaBlendFactor_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 51; + case 10: return 51; + case 9: return 51; + case 8: return 51; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_BLEND::Destination Blend Factor */ + + +#define GEN11_3DSTATE_PS_BLEND_DestinationBlendFactor_bits 5 +#define GEN10_3DSTATE_PS_BLEND_DestinationBlendFactor_bits 5 +#define GEN9_3DSTATE_PS_BLEND_DestinationBlendFactor_bits 5 +#define GEN8_3DSTATE_PS_BLEND_DestinationBlendFactor_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_BLEND_DestinationBlendFactor_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_BLEND_DestinationBlendFactor_start 41 +#define GEN10_3DSTATE_PS_BLEND_DestinationBlendFactor_start 41 +#define GEN9_3DSTATE_PS_BLEND_DestinationBlendFactor_start 41 +#define GEN8_3DSTATE_PS_BLEND_DestinationBlendFactor_start 41 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_BLEND_DestinationBlendFactor_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 41; + case 10: return 41; + case 9: return 41; + case 8: return 41; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_BLEND::Has Writeable RT */ + + +#define GEN11_3DSTATE_PS_BLEND_HasWriteableRT_bits 1 +#define GEN10_3DSTATE_PS_BLEND_HasWriteableRT_bits 1 +#define GEN9_3DSTATE_PS_BLEND_HasWriteableRT_bits 1 +#define GEN8_3DSTATE_PS_BLEND_HasWriteableRT_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_BLEND_HasWriteableRT_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_BLEND_HasWriteableRT_start 62 +#define GEN10_3DSTATE_PS_BLEND_HasWriteableRT_start 62 +#define GEN9_3DSTATE_PS_BLEND_HasWriteableRT_start 62 +#define GEN8_3DSTATE_PS_BLEND_HasWriteableRT_start 62 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_BLEND_HasWriteableRT_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 62; + case 10: return 62; + case 9: return 62; + case 8: return 62; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_BLEND::Independent Alpha Blend Enable */ + + +#define GEN11_3DSTATE_PS_BLEND_IndependentAlphaBlendEnable_bits 1 +#define GEN10_3DSTATE_PS_BLEND_IndependentAlphaBlendEnable_bits 1 +#define GEN9_3DSTATE_PS_BLEND_IndependentAlphaBlendEnable_bits 1 +#define GEN8_3DSTATE_PS_BLEND_IndependentAlphaBlendEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_BLEND_IndependentAlphaBlendEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_BLEND_IndependentAlphaBlendEnable_start 39 +#define GEN10_3DSTATE_PS_BLEND_IndependentAlphaBlendEnable_start 39 +#define GEN9_3DSTATE_PS_BLEND_IndependentAlphaBlendEnable_start 39 +#define GEN8_3DSTATE_PS_BLEND_IndependentAlphaBlendEnable_start 39 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_BLEND_IndependentAlphaBlendEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 39; + case 10: return 39; + case 9: return 39; + case 8: return 39; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_BLEND::Source Alpha Blend Factor */ + + +#define GEN11_3DSTATE_PS_BLEND_SourceAlphaBlendFactor_bits 5 +#define GEN10_3DSTATE_PS_BLEND_SourceAlphaBlendFactor_bits 5 +#define GEN9_3DSTATE_PS_BLEND_SourceAlphaBlendFactor_bits 5 +#define GEN8_3DSTATE_PS_BLEND_SourceAlphaBlendFactor_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_BLEND_SourceAlphaBlendFactor_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_BLEND_SourceAlphaBlendFactor_start 56 +#define GEN10_3DSTATE_PS_BLEND_SourceAlphaBlendFactor_start 56 +#define GEN9_3DSTATE_PS_BLEND_SourceAlphaBlendFactor_start 56 +#define GEN8_3DSTATE_PS_BLEND_SourceAlphaBlendFactor_start 56 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_BLEND_SourceAlphaBlendFactor_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 56; + case 10: return 56; + case 9: return 56; + case 8: return 56; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_BLEND::Source Blend Factor */ + + +#define GEN11_3DSTATE_PS_BLEND_SourceBlendFactor_bits 5 +#define GEN10_3DSTATE_PS_BLEND_SourceBlendFactor_bits 5 +#define GEN9_3DSTATE_PS_BLEND_SourceBlendFactor_bits 5 +#define GEN8_3DSTATE_PS_BLEND_SourceBlendFactor_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_BLEND_SourceBlendFactor_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_BLEND_SourceBlendFactor_start 46 +#define GEN10_3DSTATE_PS_BLEND_SourceBlendFactor_start 46 +#define GEN9_3DSTATE_PS_BLEND_SourceBlendFactor_start 46 +#define GEN8_3DSTATE_PS_BLEND_SourceBlendFactor_start 46 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_BLEND_SourceBlendFactor_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 46; + case 10: return 46; + case 9: return 46; + case 8: return 46; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_EXTRA */ + + +#define GEN11_3DSTATE_PS_EXTRA_length 2 +#define GEN10_3DSTATE_PS_EXTRA_length 2 +#define GEN9_3DSTATE_PS_EXTRA_length 2 +#define GEN8_3DSTATE_PS_EXTRA_length 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_EXTRA::3D Command Opcode */ + + +#define GEN11_3DSTATE_PS_EXTRA_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_PS_EXTRA_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_PS_EXTRA_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_PS_EXTRA_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_EXTRA_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_PS_EXTRA_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_PS_EXTRA_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_PS_EXTRA_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_EXTRA::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_PS_EXTRA_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_PS_EXTRA_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_PS_EXTRA_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_PS_EXTRA_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_EXTRA_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_PS_EXTRA_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_PS_EXTRA_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_PS_EXTRA_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_EXTRA::Attribute Enable */ + + +#define GEN11_3DSTATE_PS_EXTRA_AttributeEnable_bits 1 +#define GEN10_3DSTATE_PS_EXTRA_AttributeEnable_bits 1 +#define GEN9_3DSTATE_PS_EXTRA_AttributeEnable_bits 1 +#define GEN8_3DSTATE_PS_EXTRA_AttributeEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_AttributeEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_EXTRA_AttributeEnable_start 40 +#define GEN10_3DSTATE_PS_EXTRA_AttributeEnable_start 40 +#define GEN9_3DSTATE_PS_EXTRA_AttributeEnable_start 40 +#define GEN8_3DSTATE_PS_EXTRA_AttributeEnable_start 40 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_AttributeEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 40; + case 10: return 40; + case 9: return 40; + case 8: return 40; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_EXTRA::Command SubType */ + + +#define GEN11_3DSTATE_PS_EXTRA_CommandSubType_bits 2 +#define GEN10_3DSTATE_PS_EXTRA_CommandSubType_bits 2 +#define GEN9_3DSTATE_PS_EXTRA_CommandSubType_bits 2 +#define GEN8_3DSTATE_PS_EXTRA_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_EXTRA_CommandSubType_start 27 +#define GEN10_3DSTATE_PS_EXTRA_CommandSubType_start 27 +#define GEN9_3DSTATE_PS_EXTRA_CommandSubType_start 27 +#define GEN8_3DSTATE_PS_EXTRA_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_EXTRA::Command Type */ + + +#define GEN11_3DSTATE_PS_EXTRA_CommandType_bits 3 +#define GEN10_3DSTATE_PS_EXTRA_CommandType_bits 3 +#define GEN9_3DSTATE_PS_EXTRA_CommandType_bits 3 +#define GEN8_3DSTATE_PS_EXTRA_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_EXTRA_CommandType_start 29 +#define GEN10_3DSTATE_PS_EXTRA_CommandType_start 29 +#define GEN9_3DSTATE_PS_EXTRA_CommandType_start 29 +#define GEN8_3DSTATE_PS_EXTRA_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_EXTRA::DWord Length */ + + +#define GEN11_3DSTATE_PS_EXTRA_DWordLength_bits 8 +#define GEN10_3DSTATE_PS_EXTRA_DWordLength_bits 8 +#define GEN9_3DSTATE_PS_EXTRA_DWordLength_bits 8 +#define GEN8_3DSTATE_PS_EXTRA_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_EXTRA_DWordLength_start 0 +#define GEN10_3DSTATE_PS_EXTRA_DWordLength_start 0 +#define GEN9_3DSTATE_PS_EXTRA_DWordLength_start 0 +#define GEN8_3DSTATE_PS_EXTRA_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_EXTRA::Force Computed Depth */ + + +#define GEN11_3DSTATE_PS_EXTRA_ForceComputedDepth_bits 1 +#define GEN10_3DSTATE_PS_EXTRA_ForceComputedDepth_bits 1 +#define GEN9_3DSTATE_PS_EXTRA_ForceComputedDepth_bits 1 +#define GEN8_3DSTATE_PS_EXTRA_ForceComputedDepth_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_ForceComputedDepth_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_EXTRA_ForceComputedDepth_start 57 +#define GEN10_3DSTATE_PS_EXTRA_ForceComputedDepth_start 57 +#define GEN9_3DSTATE_PS_EXTRA_ForceComputedDepth_start 57 +#define GEN8_3DSTATE_PS_EXTRA_ForceComputedDepth_start 57 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_ForceComputedDepth_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 57; + case 10: return 57; + case 9: return 57; + case 8: return 57; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_EXTRA::Input Coverage Mask State */ + + +#define GEN11_3DSTATE_PS_EXTRA_InputCoverageMaskState_bits 2 +#define GEN10_3DSTATE_PS_EXTRA_InputCoverageMaskState_bits 2 +#define GEN9_3DSTATE_PS_EXTRA_InputCoverageMaskState_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_InputCoverageMaskState_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_EXTRA_InputCoverageMaskState_start 32 +#define GEN10_3DSTATE_PS_EXTRA_InputCoverageMaskState_start 32 +#define GEN9_3DSTATE_PS_EXTRA_InputCoverageMaskState_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_InputCoverageMaskState_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_EXTRA::Pixel Shader Computed Depth Mode */ + + +#define GEN11_3DSTATE_PS_EXTRA_PixelShaderComputedDepthMode_bits 2 +#define GEN10_3DSTATE_PS_EXTRA_PixelShaderComputedDepthMode_bits 2 +#define GEN9_3DSTATE_PS_EXTRA_PixelShaderComputedDepthMode_bits 2 +#define GEN8_3DSTATE_PS_EXTRA_PixelShaderComputedDepthMode_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_PixelShaderComputedDepthMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_EXTRA_PixelShaderComputedDepthMode_start 58 +#define GEN10_3DSTATE_PS_EXTRA_PixelShaderComputedDepthMode_start 58 +#define GEN9_3DSTATE_PS_EXTRA_PixelShaderComputedDepthMode_start 58 +#define GEN8_3DSTATE_PS_EXTRA_PixelShaderComputedDepthMode_start 58 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_PixelShaderComputedDepthMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 58; + case 10: return 58; + case 9: return 58; + case 8: return 58; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_EXTRA::Pixel Shader Computes Stencil */ + + +#define GEN11_3DSTATE_PS_EXTRA_PixelShaderComputesStencil_bits 1 +#define GEN10_3DSTATE_PS_EXTRA_PixelShaderComputesStencil_bits 1 +#define GEN9_3DSTATE_PS_EXTRA_PixelShaderComputesStencil_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_PixelShaderComputesStencil_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_EXTRA_PixelShaderComputesStencil_start 37 +#define GEN10_3DSTATE_PS_EXTRA_PixelShaderComputesStencil_start 37 +#define GEN9_3DSTATE_PS_EXTRA_PixelShaderComputesStencil_start 37 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_PixelShaderComputesStencil_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 37; + case 10: return 37; + case 9: return 37; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_EXTRA::Pixel Shader Disables Alpha To Coverage */ + + +#define GEN11_3DSTATE_PS_EXTRA_PixelShaderDisablesAlphaToCoverage_bits 1 +#define GEN10_3DSTATE_PS_EXTRA_PixelShaderDisablesAlphaToCoverage_bits 1 +#define GEN9_3DSTATE_PS_EXTRA_PixelShaderDisablesAlphaToCoverage_bits 1 +#define GEN8_3DSTATE_PS_EXTRA_PixelShaderDisablesAlphaToCoverage_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_PixelShaderDisablesAlphaToCoverage_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_EXTRA_PixelShaderDisablesAlphaToCoverage_start 39 +#define GEN10_3DSTATE_PS_EXTRA_PixelShaderDisablesAlphaToCoverage_start 39 +#define GEN9_3DSTATE_PS_EXTRA_PixelShaderDisablesAlphaToCoverage_start 39 +#define GEN8_3DSTATE_PS_EXTRA_PixelShaderDisablesAlphaToCoverage_start 39 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_PixelShaderDisablesAlphaToCoverage_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 39; + case 10: return 39; + case 9: return 39; + case 8: return 39; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_EXTRA::Pixel Shader Does not write to RT */ + + +#define GEN11_3DSTATE_PS_EXTRA_PixelShaderDoesnotwritetoRT_bits 1 +#define GEN10_3DSTATE_PS_EXTRA_PixelShaderDoesnotwritetoRT_bits 1 +#define GEN9_3DSTATE_PS_EXTRA_PixelShaderDoesnotwritetoRT_bits 1 +#define GEN8_3DSTATE_PS_EXTRA_PixelShaderDoesnotwritetoRT_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_PixelShaderDoesnotwritetoRT_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_EXTRA_PixelShaderDoesnotwritetoRT_start 62 +#define GEN10_3DSTATE_PS_EXTRA_PixelShaderDoesnotwritetoRT_start 62 +#define GEN9_3DSTATE_PS_EXTRA_PixelShaderDoesnotwritetoRT_start 62 +#define GEN8_3DSTATE_PS_EXTRA_PixelShaderDoesnotwritetoRT_start 62 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_PixelShaderDoesnotwritetoRT_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 62; + case 10: return 62; + case 9: return 62; + case 8: return 62; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_EXTRA::Pixel Shader Has UAV */ + + +#define GEN11_3DSTATE_PS_EXTRA_PixelShaderHasUAV_bits 1 +#define GEN10_3DSTATE_PS_EXTRA_PixelShaderHasUAV_bits 1 +#define GEN9_3DSTATE_PS_EXTRA_PixelShaderHasUAV_bits 1 +#define GEN8_3DSTATE_PS_EXTRA_PixelShaderHasUAV_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_PixelShaderHasUAV_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_EXTRA_PixelShaderHasUAV_start 34 +#define GEN10_3DSTATE_PS_EXTRA_PixelShaderHasUAV_start 34 +#define GEN9_3DSTATE_PS_EXTRA_PixelShaderHasUAV_start 34 +#define GEN8_3DSTATE_PS_EXTRA_PixelShaderHasUAV_start 34 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_PixelShaderHasUAV_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 34; + case 10: return 34; + case 9: return 34; + case 8: return 34; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_EXTRA::Pixel Shader Is Per Sample */ + + +#define GEN11_3DSTATE_PS_EXTRA_PixelShaderIsPerSample_bits 1 +#define GEN10_3DSTATE_PS_EXTRA_PixelShaderIsPerSample_bits 1 +#define GEN9_3DSTATE_PS_EXTRA_PixelShaderIsPerSample_bits 1 +#define GEN8_3DSTATE_PS_EXTRA_PixelShaderIsPerSample_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_PixelShaderIsPerSample_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_EXTRA_PixelShaderIsPerSample_start 38 +#define GEN10_3DSTATE_PS_EXTRA_PixelShaderIsPerSample_start 38 +#define GEN9_3DSTATE_PS_EXTRA_PixelShaderIsPerSample_start 38 +#define GEN8_3DSTATE_PS_EXTRA_PixelShaderIsPerSample_start 38 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_PixelShaderIsPerSample_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 38; + case 10: return 38; + case 9: return 38; + case 8: return 38; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_EXTRA::Pixel Shader Kills Pixel */ + + +#define GEN11_3DSTATE_PS_EXTRA_PixelShaderKillsPixel_bits 1 +#define GEN10_3DSTATE_PS_EXTRA_PixelShaderKillsPixel_bits 1 +#define GEN9_3DSTATE_PS_EXTRA_PixelShaderKillsPixel_bits 1 +#define GEN8_3DSTATE_PS_EXTRA_PixelShaderKillsPixel_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_PixelShaderKillsPixel_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_EXTRA_PixelShaderKillsPixel_start 60 +#define GEN10_3DSTATE_PS_EXTRA_PixelShaderKillsPixel_start 60 +#define GEN9_3DSTATE_PS_EXTRA_PixelShaderKillsPixel_start 60 +#define GEN8_3DSTATE_PS_EXTRA_PixelShaderKillsPixel_start 60 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_PixelShaderKillsPixel_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 60; + case 10: return 60; + case 9: return 60; + case 8: return 60; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_EXTRA::Pixel Shader Pulls Bary */ + + +#define GEN11_3DSTATE_PS_EXTRA_PixelShaderPullsBary_bits 1 +#define GEN10_3DSTATE_PS_EXTRA_PixelShaderPullsBary_bits 1 +#define GEN9_3DSTATE_PS_EXTRA_PixelShaderPullsBary_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_PixelShaderPullsBary_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_EXTRA_PixelShaderPullsBary_start 35 +#define GEN10_3DSTATE_PS_EXTRA_PixelShaderPullsBary_start 35 +#define GEN9_3DSTATE_PS_EXTRA_PixelShaderPullsBary_start 35 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_PixelShaderPullsBary_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 35; + case 10: return 35; + case 9: return 35; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_EXTRA::Pixel Shader Requires Non-Perspective Bary Plane Coefficients */ + + +#define GEN11_3DSTATE_PS_EXTRA_PixelShaderRequiresNonPerspectiveBaryPlaneCoefficients_bits 1 +#define GEN10_3DSTATE_PS_EXTRA_PixelShaderRequiresNonPerspectiveBaryPlaneCoefficients_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_PixelShaderRequiresNonPerspectiveBaryPlaneCoefficients_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_EXTRA_PixelShaderRequiresNonPerspectiveBaryPlaneCoefficients_start 51 +#define GEN10_3DSTATE_PS_EXTRA_PixelShaderRequiresNonPerspectiveBaryPlaneCoefficients_start 51 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_PixelShaderRequiresNonPerspectiveBaryPlaneCoefficients_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 51; + case 10: return 51; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_EXTRA::Pixel Shader Requires Perspective Bary Plane Coefficients */ + + +#define GEN11_3DSTATE_PS_EXTRA_PixelShaderRequiresPerspectiveBaryPlaneCoefficients_bits 1 +#define GEN10_3DSTATE_PS_EXTRA_PixelShaderRequiresPerspectiveBaryPlaneCoefficients_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_PixelShaderRequiresPerspectiveBaryPlaneCoefficients_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_EXTRA_PixelShaderRequiresPerspectiveBaryPlaneCoefficients_start 52 +#define GEN10_3DSTATE_PS_EXTRA_PixelShaderRequiresPerspectiveBaryPlaneCoefficients_start 52 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_PixelShaderRequiresPerspectiveBaryPlaneCoefficients_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 52; + case 10: return 52; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_EXTRA::Pixel Shader Requires Source Depth and/or W Plane Coefficients */ + + +#define GEN11_3DSTATE_PS_EXTRA_PixelShaderRequiresSourceDepthandorWPlaneCoefficients_bits 1 +#define GEN10_3DSTATE_PS_EXTRA_PixelShaderRequiresSourceDepthandorWPlaneCoefficients_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_PixelShaderRequiresSourceDepthandorWPlaneCoefficients_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_EXTRA_PixelShaderRequiresSourceDepthandorWPlaneCoefficients_start 53 +#define GEN10_3DSTATE_PS_EXTRA_PixelShaderRequiresSourceDepthandorWPlaneCoefficients_start 53 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_PixelShaderRequiresSourceDepthandorWPlaneCoefficients_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 53; + case 10: return 53; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_EXTRA::Pixel Shader Requires Subpixel Sample Offsets */ + + +#define GEN11_3DSTATE_PS_EXTRA_PixelShaderRequiresSubpixelSampleOffsets_bits 1 +#define GEN10_3DSTATE_PS_EXTRA_PixelShaderRequiresSubpixelSampleOffsets_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_PixelShaderRequiresSubpixelSampleOffsets_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_EXTRA_PixelShaderRequiresSubpixelSampleOffsets_start 50 +#define GEN10_3DSTATE_PS_EXTRA_PixelShaderRequiresSubpixelSampleOffsets_start 50 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_PixelShaderRequiresSubpixelSampleOffsets_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 50; + case 10: return 50; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_EXTRA::Pixel Shader Uses Input Coverage Mask */ + + +#define GEN8_3DSTATE_PS_EXTRA_PixelShaderUsesInputCoverageMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_PixelShaderUsesInputCoverageMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_3DSTATE_PS_EXTRA_PixelShaderUsesInputCoverageMask_start 33 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_PixelShaderUsesInputCoverageMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 33; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_EXTRA::Pixel Shader Uses Source Depth */ + + +#define GEN11_3DSTATE_PS_EXTRA_PixelShaderUsesSourceDepth_bits 1 +#define GEN10_3DSTATE_PS_EXTRA_PixelShaderUsesSourceDepth_bits 1 +#define GEN9_3DSTATE_PS_EXTRA_PixelShaderUsesSourceDepth_bits 1 +#define GEN8_3DSTATE_PS_EXTRA_PixelShaderUsesSourceDepth_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_PixelShaderUsesSourceDepth_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_EXTRA_PixelShaderUsesSourceDepth_start 56 +#define GEN10_3DSTATE_PS_EXTRA_PixelShaderUsesSourceDepth_start 56 +#define GEN9_3DSTATE_PS_EXTRA_PixelShaderUsesSourceDepth_start 56 +#define GEN8_3DSTATE_PS_EXTRA_PixelShaderUsesSourceDepth_start 56 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_PixelShaderUsesSourceDepth_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 56; + case 10: return 56; + case 9: return 56; + case 8: return 56; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_EXTRA::Pixel Shader Uses Source W */ + + +#define GEN11_3DSTATE_PS_EXTRA_PixelShaderUsesSourceW_bits 1 +#define GEN10_3DSTATE_PS_EXTRA_PixelShaderUsesSourceW_bits 1 +#define GEN9_3DSTATE_PS_EXTRA_PixelShaderUsesSourceW_bits 1 +#define GEN8_3DSTATE_PS_EXTRA_PixelShaderUsesSourceW_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_PixelShaderUsesSourceW_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_EXTRA_PixelShaderUsesSourceW_start 55 +#define GEN10_3DSTATE_PS_EXTRA_PixelShaderUsesSourceW_start 55 +#define GEN9_3DSTATE_PS_EXTRA_PixelShaderUsesSourceW_start 55 +#define GEN8_3DSTATE_PS_EXTRA_PixelShaderUsesSourceW_start 55 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_PixelShaderUsesSourceW_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 55; + case 10: return 55; + case 9: return 55; + case 8: return 55; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_EXTRA::Pixel Shader Valid */ + + +#define GEN11_3DSTATE_PS_EXTRA_PixelShaderValid_bits 1 +#define GEN10_3DSTATE_PS_EXTRA_PixelShaderValid_bits 1 +#define GEN9_3DSTATE_PS_EXTRA_PixelShaderValid_bits 1 +#define GEN8_3DSTATE_PS_EXTRA_PixelShaderValid_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_PixelShaderValid_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_EXTRA_PixelShaderValid_start 63 +#define GEN10_3DSTATE_PS_EXTRA_PixelShaderValid_start 63 +#define GEN9_3DSTATE_PS_EXTRA_PixelShaderValid_start 63 +#define GEN8_3DSTATE_PS_EXTRA_PixelShaderValid_start 63 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_PixelShaderValid_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 63; + case 10: return 63; + case 9: return 63; + case 8: return 63; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_EXTRA::Simple PS Hint */ + + +#define GEN11_3DSTATE_PS_EXTRA_SimplePSHint_bits 1 +#define GEN10_3DSTATE_PS_EXTRA_SimplePSHint_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_SimplePSHint_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_EXTRA_SimplePSHint_start 41 +#define GEN10_3DSTATE_PS_EXTRA_SimplePSHint_start 41 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_SimplePSHint_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 41; + case 10: return 41; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PS_EXTRA::oMask Present to Render Target */ + + +#define GEN11_3DSTATE_PS_EXTRA_oMaskPresenttoRenderTarget_bits 1 +#define GEN10_3DSTATE_PS_EXTRA_oMaskPresenttoRenderTarget_bits 1 +#define GEN9_3DSTATE_PS_EXTRA_oMaskPresenttoRenderTarget_bits 1 +#define GEN8_3DSTATE_PS_EXTRA_oMaskPresenttoRenderTarget_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_oMaskPresenttoRenderTarget_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PS_EXTRA_oMaskPresenttoRenderTarget_start 61 +#define GEN10_3DSTATE_PS_EXTRA_oMaskPresenttoRenderTarget_start 61 +#define GEN9_3DSTATE_PS_EXTRA_oMaskPresenttoRenderTarget_start 61 +#define GEN8_3DSTATE_PS_EXTRA_oMaskPresenttoRenderTarget_start 61 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PS_EXTRA_oMaskPresenttoRenderTarget_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 61; + case 10: return 61; + case 9: return 61; + case 8: return 61; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_DS */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_DS_length 2 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_DS_length 2 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_DS_length 2 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_DS_length 2 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_DS_length 2 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS_length 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_DS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_DS::3D Command Opcode */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_DS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_DS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_DS::Command SubType */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandSubType_bits 2 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandSubType_bits 2 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandSubType_bits 2 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandSubType_bits 2 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandSubType_bits 2 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandSubType_start 27 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandSubType_start 27 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandSubType_start 27 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandSubType_start 27 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandSubType_start 27 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_DS::Command Type */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandType_bits 3 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandType_bits 3 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandType_bits 3 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandType_bits 3 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandType_bits 3 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandType_start 29 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandType_start 29 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandType_start 29 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandType_start 29 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandType_start 29 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_DS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_DS::Constant Buffer Offset */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferOffset_bits 5 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferOffset_bits 5 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferOffset_bits 5 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferOffset_bits 5 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferOffset_bits 5 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferOffset_start 48 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferOffset_start 48 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferOffset_start 48 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferOffset_start 48 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferOffset_start 48 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferOffset_start 48 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 48; + case 7: + if (devinfo->is_haswell) { + return 48; + } else { + return 48; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_DS::Constant Buffer Size */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferSize_bits 6 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferSize_bits 6 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferSize_bits 6 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferSize_bits 6 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferSize_bits 6 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferSize_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferSize_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 5; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferSize_start 32 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferSize_start 32 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferSize_start 32 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferSize_start 32 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferSize_start 32 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferSize_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_DS_ConstantBufferSize_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_DS::DWord Length */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_DS_DWordLength_bits 8 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_DS_DWordLength_bits 8 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_DS_DWordLength_bits 8 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_DS_DWordLength_bits 8 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_DS_DWordLength_bits 8 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_DS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_DS_DWordLength_start 0 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_DS_DWordLength_start 0 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_DS_DWordLength_start 0 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_DS_DWordLength_start 0 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_DS_DWordLength_start 0 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_DS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_DS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_GS */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_GS_length 2 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_GS_length 2 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_GS_length 2 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_GS_length 2 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_GS_length 2 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS_length 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_GS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_GS::3D Command Opcode */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_GS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_GS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_GS::Command SubType */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandSubType_bits 2 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandSubType_bits 2 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandSubType_bits 2 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandSubType_bits 2 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandSubType_bits 2 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandSubType_start 27 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandSubType_start 27 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandSubType_start 27 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandSubType_start 27 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandSubType_start 27 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_GS::Command Type */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandType_bits 3 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandType_bits 3 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandType_bits 3 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandType_bits 3 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandType_bits 3 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandType_start 29 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandType_start 29 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandType_start 29 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandType_start 29 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandType_start 29 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_GS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_GS::Constant Buffer Offset */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferOffset_bits 5 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferOffset_bits 5 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferOffset_bits 5 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferOffset_bits 5 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferOffset_bits 5 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferOffset_start 48 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferOffset_start 48 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferOffset_start 48 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferOffset_start 48 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferOffset_start 48 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferOffset_start 48 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 48; + case 7: + if (devinfo->is_haswell) { + return 48; + } else { + return 48; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_GS::Constant Buffer Size */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferSize_bits 6 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferSize_bits 6 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferSize_bits 6 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferSize_bits 6 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferSize_bits 6 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferSize_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferSize_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 5; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferSize_start 32 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferSize_start 32 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferSize_start 32 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferSize_start 32 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferSize_start 32 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferSize_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_GS_ConstantBufferSize_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_GS::DWord Length */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_GS_DWordLength_bits 8 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_GS_DWordLength_bits 8 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_GS_DWordLength_bits 8 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_GS_DWordLength_bits 8 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_GS_DWordLength_bits 8 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_GS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_GS_DWordLength_start 0 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_GS_DWordLength_start 0 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_GS_DWordLength_start 0 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_GS_DWordLength_start 0 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_GS_DWordLength_start 0 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_GS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_GS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_HS */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_HS_length 2 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_HS_length 2 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_HS_length 2 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_HS_length 2 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_HS_length 2 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS_length 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_HS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_HS::3D Command Opcode */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_HS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_HS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_HS::Command SubType */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandSubType_bits 2 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandSubType_bits 2 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandSubType_bits 2 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandSubType_bits 2 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandSubType_bits 2 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandSubType_start 27 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandSubType_start 27 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandSubType_start 27 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandSubType_start 27 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandSubType_start 27 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_HS::Command Type */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandType_bits 3 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandType_bits 3 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandType_bits 3 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandType_bits 3 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandType_bits 3 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandType_start 29 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandType_start 29 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandType_start 29 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandType_start 29 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandType_start 29 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_HS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_HS::Constant Buffer Offset */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferOffset_bits 5 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferOffset_bits 5 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferOffset_bits 5 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferOffset_bits 5 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferOffset_bits 5 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferOffset_start 48 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferOffset_start 48 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferOffset_start 48 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferOffset_start 48 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferOffset_start 48 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferOffset_start 48 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 48; + case 7: + if (devinfo->is_haswell) { + return 48; + } else { + return 48; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_HS::Constant Buffer Size */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferSize_bits 6 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferSize_bits 6 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferSize_bits 6 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferSize_bits 6 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferSize_bits 6 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferSize_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferSize_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 5; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferSize_start 32 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferSize_start 32 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferSize_start 32 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferSize_start 32 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferSize_start 32 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferSize_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_HS_ConstantBufferSize_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_HS::DWord Length */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_HS_DWordLength_bits 8 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_HS_DWordLength_bits 8 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_HS_DWordLength_bits 8 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_HS_DWordLength_bits 8 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_HS_DWordLength_bits 8 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_HS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_HS_DWordLength_start 0 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_HS_DWordLength_start 0 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_HS_DWordLength_start 0 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_HS_DWordLength_start 0 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_HS_DWordLength_start 0 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_HS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_HS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_PS */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_PS_length 2 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_PS_length 2 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_PS_length 2 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_PS_length 2 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_PS_length 2 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS_length 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_PS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_PS::3D Command Opcode */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_PS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_PS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_PS::Command SubType */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandSubType_bits 2 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandSubType_bits 2 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandSubType_bits 2 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandSubType_bits 2 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandSubType_bits 2 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandSubType_start 27 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandSubType_start 27 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandSubType_start 27 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandSubType_start 27 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandSubType_start 27 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_PS::Command Type */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandType_bits 3 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandType_bits 3 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandType_bits 3 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandType_bits 3 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandType_bits 3 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandType_start 29 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandType_start 29 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandType_start 29 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandType_start 29 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandType_start 29 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_PS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_PS::Constant Buffer Offset */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferOffset_bits 5 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferOffset_bits 5 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferOffset_bits 5 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferOffset_bits 5 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferOffset_bits 5 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferOffset_start 48 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferOffset_start 48 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferOffset_start 48 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferOffset_start 48 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferOffset_start 48 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferOffset_start 48 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 48; + case 7: + if (devinfo->is_haswell) { + return 48; + } else { + return 48; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_PS::Constant Buffer Size */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferSize_bits 6 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferSize_bits 6 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferSize_bits 6 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferSize_bits 6 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferSize_bits 6 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferSize_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferSize_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 5; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferSize_start 32 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferSize_start 32 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferSize_start 32 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferSize_start 32 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferSize_start 32 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferSize_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_PS_ConstantBufferSize_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_PS::DWord Length */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_PS_DWordLength_bits 8 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_PS_DWordLength_bits 8 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_PS_DWordLength_bits 8 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_PS_DWordLength_bits 8 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_PS_DWordLength_bits 8 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_PS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_PS_DWordLength_start 0 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_PS_DWordLength_start 0 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_PS_DWordLength_start 0 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_PS_DWordLength_start 0 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_PS_DWordLength_start 0 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_PS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_VS */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_VS_length 2 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_VS_length 2 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_VS_length 2 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_VS_length 2 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_VS_length 2 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS_length 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_VS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_VS::3D Command Opcode */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_VS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_VS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_VS::Command SubType */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandSubType_bits 2 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandSubType_bits 2 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandSubType_bits 2 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandSubType_bits 2 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandSubType_bits 2 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandSubType_start 27 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandSubType_start 27 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandSubType_start 27 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandSubType_start 27 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandSubType_start 27 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_VS::Command Type */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandType_bits 3 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandType_bits 3 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandType_bits 3 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandType_bits 3 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandType_bits 3 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandType_start 29 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandType_start 29 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandType_start 29 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandType_start 29 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandType_start 29 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_VS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_VS::Constant Buffer Offset */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferOffset_bits 5 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferOffset_bits 5 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferOffset_bits 5 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferOffset_bits 5 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferOffset_bits 5 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferOffset_start 48 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferOffset_start 48 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferOffset_start 48 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferOffset_start 48 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferOffset_start 48 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferOffset_start 48 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 48; + case 7: + if (devinfo->is_haswell) { + return 48; + } else { + return 48; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_VS::Constant Buffer Size */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferSize_bits 6 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferSize_bits 6 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferSize_bits 6 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferSize_bits 6 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferSize_bits 6 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferSize_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferSize_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 5; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferSize_start 32 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferSize_start 32 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferSize_start 32 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferSize_start 32 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferSize_start 32 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferSize_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_VS_ConstantBufferSize_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_PUSH_CONSTANT_ALLOC_VS::DWord Length */ + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_VS_DWordLength_bits 8 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_VS_DWordLength_bits 8 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_VS_DWordLength_bits 8 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_VS_DWordLength_bits 8 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_VS_DWordLength_bits 8 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_VS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_PUSH_CONSTANT_ALLOC_VS_DWordLength_start 0 +#define GEN10_3DSTATE_PUSH_CONSTANT_ALLOC_VS_DWordLength_start 0 +#define GEN9_3DSTATE_PUSH_CONSTANT_ALLOC_VS_DWordLength_start 0 +#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_VS_DWordLength_start 0 +#define GEN75_3DSTATE_PUSH_CONSTANT_ALLOC_VS_DWordLength_start 0 +#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_PUSH_CONSTANT_ALLOC_VS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RASTER */ + + +#define GEN11_3DSTATE_RASTER_length 5 +#define GEN10_3DSTATE_RASTER_length 5 +#define GEN9_3DSTATE_RASTER_length 5 +#define GEN8_3DSTATE_RASTER_length 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RASTER::3D Command Opcode */ + + +#define GEN11_3DSTATE_RASTER_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_RASTER_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_RASTER_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_RASTER_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_RASTER_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_RASTER_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_RASTER_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_RASTER_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RASTER::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_RASTER_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_RASTER_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_RASTER_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_RASTER_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_RASTER_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_RASTER_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_RASTER_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_RASTER_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RASTER::API Mode */ + + +#define GEN11_3DSTATE_RASTER_APIMode_bits 2 +#define GEN10_3DSTATE_RASTER_APIMode_bits 2 +#define GEN9_3DSTATE_RASTER_APIMode_bits 2 +#define GEN8_3DSTATE_RASTER_APIMode_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_APIMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_RASTER_APIMode_start 54 +#define GEN10_3DSTATE_RASTER_APIMode_start 54 +#define GEN9_3DSTATE_RASTER_APIMode_start 54 +#define GEN8_3DSTATE_RASTER_APIMode_start 54 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_APIMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 54; + case 10: return 54; + case 9: return 54; + case 8: return 54; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RASTER::Antialiasing Enable */ + + +#define GEN11_3DSTATE_RASTER_AntialiasingEnable_bits 1 +#define GEN10_3DSTATE_RASTER_AntialiasingEnable_bits 1 +#define GEN9_3DSTATE_RASTER_AntialiasingEnable_bits 1 +#define GEN8_3DSTATE_RASTER_AntialiasingEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_AntialiasingEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_RASTER_AntialiasingEnable_start 34 +#define GEN10_3DSTATE_RASTER_AntialiasingEnable_start 34 +#define GEN9_3DSTATE_RASTER_AntialiasingEnable_start 34 +#define GEN8_3DSTATE_RASTER_AntialiasingEnable_start 34 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_AntialiasingEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 34; + case 10: return 34; + case 9: return 34; + case 8: return 34; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RASTER::Back Face Fill Mode */ + + +#define GEN11_3DSTATE_RASTER_BackFaceFillMode_bits 2 +#define GEN10_3DSTATE_RASTER_BackFaceFillMode_bits 2 +#define GEN9_3DSTATE_RASTER_BackFaceFillMode_bits 2 +#define GEN8_3DSTATE_RASTER_BackFaceFillMode_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_BackFaceFillMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_RASTER_BackFaceFillMode_start 35 +#define GEN10_3DSTATE_RASTER_BackFaceFillMode_start 35 +#define GEN9_3DSTATE_RASTER_BackFaceFillMode_start 35 +#define GEN8_3DSTATE_RASTER_BackFaceFillMode_start 35 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_BackFaceFillMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 35; + case 10: return 35; + case 9: return 35; + case 8: return 35; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RASTER::Command SubType */ + + +#define GEN11_3DSTATE_RASTER_CommandSubType_bits 2 +#define GEN10_3DSTATE_RASTER_CommandSubType_bits 2 +#define GEN9_3DSTATE_RASTER_CommandSubType_bits 2 +#define GEN8_3DSTATE_RASTER_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_RASTER_CommandSubType_start 27 +#define GEN10_3DSTATE_RASTER_CommandSubType_start 27 +#define GEN9_3DSTATE_RASTER_CommandSubType_start 27 +#define GEN8_3DSTATE_RASTER_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RASTER::Command Type */ + + +#define GEN11_3DSTATE_RASTER_CommandType_bits 3 +#define GEN10_3DSTATE_RASTER_CommandType_bits 3 +#define GEN9_3DSTATE_RASTER_CommandType_bits 3 +#define GEN8_3DSTATE_RASTER_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_RASTER_CommandType_start 29 +#define GEN10_3DSTATE_RASTER_CommandType_start 29 +#define GEN9_3DSTATE_RASTER_CommandType_start 29 +#define GEN8_3DSTATE_RASTER_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RASTER::Conservative Rasterization Enable */ + + +#define GEN11_3DSTATE_RASTER_ConservativeRasterizationEnable_bits 1 +#define GEN10_3DSTATE_RASTER_ConservativeRasterizationEnable_bits 1 +#define GEN9_3DSTATE_RASTER_ConservativeRasterizationEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_ConservativeRasterizationEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_RASTER_ConservativeRasterizationEnable_start 56 +#define GEN10_3DSTATE_RASTER_ConservativeRasterizationEnable_start 56 +#define GEN9_3DSTATE_RASTER_ConservativeRasterizationEnable_start 56 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_ConservativeRasterizationEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 56; + case 10: return 56; + case 9: return 56; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RASTER::Cull Mode */ + + +#define GEN11_3DSTATE_RASTER_CullMode_bits 2 +#define GEN10_3DSTATE_RASTER_CullMode_bits 2 +#define GEN9_3DSTATE_RASTER_CullMode_bits 2 +#define GEN8_3DSTATE_RASTER_CullMode_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_CullMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_RASTER_CullMode_start 48 +#define GEN10_3DSTATE_RASTER_CullMode_start 48 +#define GEN9_3DSTATE_RASTER_CullMode_start 48 +#define GEN8_3DSTATE_RASTER_CullMode_start 48 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_CullMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 48; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RASTER::DWord Length */ + + +#define GEN11_3DSTATE_RASTER_DWordLength_bits 8 +#define GEN10_3DSTATE_RASTER_DWordLength_bits 8 +#define GEN9_3DSTATE_RASTER_DWordLength_bits 8 +#define GEN8_3DSTATE_RASTER_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_RASTER_DWordLength_start 0 +#define GEN10_3DSTATE_RASTER_DWordLength_start 0 +#define GEN9_3DSTATE_RASTER_DWordLength_start 0 +#define GEN8_3DSTATE_RASTER_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RASTER::DX Multisample Rasterization Enable */ + + +#define GEN11_3DSTATE_RASTER_DXMultisampleRasterizationEnable_bits 1 +#define GEN10_3DSTATE_RASTER_DXMultisampleRasterizationEnable_bits 1 +#define GEN9_3DSTATE_RASTER_DXMultisampleRasterizationEnable_bits 1 +#define GEN8_3DSTATE_RASTER_DXMultisampleRasterizationEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_DXMultisampleRasterizationEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_RASTER_DXMultisampleRasterizationEnable_start 44 +#define GEN10_3DSTATE_RASTER_DXMultisampleRasterizationEnable_start 44 +#define GEN9_3DSTATE_RASTER_DXMultisampleRasterizationEnable_start 44 +#define GEN8_3DSTATE_RASTER_DXMultisampleRasterizationEnable_start 44 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_DXMultisampleRasterizationEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 44; + case 10: return 44; + case 9: return 44; + case 8: return 44; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RASTER::DX Multisample Rasterization Mode */ + + +#define GEN11_3DSTATE_RASTER_DXMultisampleRasterizationMode_bits 2 +#define GEN10_3DSTATE_RASTER_DXMultisampleRasterizationMode_bits 2 +#define GEN9_3DSTATE_RASTER_DXMultisampleRasterizationMode_bits 2 +#define GEN8_3DSTATE_RASTER_DXMultisampleRasterizationMode_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_DXMultisampleRasterizationMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_RASTER_DXMultisampleRasterizationMode_start 42 +#define GEN10_3DSTATE_RASTER_DXMultisampleRasterizationMode_start 42 +#define GEN9_3DSTATE_RASTER_DXMultisampleRasterizationMode_start 42 +#define GEN8_3DSTATE_RASTER_DXMultisampleRasterizationMode_start 42 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_DXMultisampleRasterizationMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 42; + case 10: return 42; + case 9: return 42; + case 8: return 42; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RASTER::Force Multisampling */ + + +#define GEN11_3DSTATE_RASTER_ForceMultisampling_bits 1 +#define GEN10_3DSTATE_RASTER_ForceMultisampling_bits 1 +#define GEN9_3DSTATE_RASTER_ForceMultisampling_bits 1 +#define GEN8_3DSTATE_RASTER_ForceMultisampling_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_ForceMultisampling_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_RASTER_ForceMultisampling_start 46 +#define GEN10_3DSTATE_RASTER_ForceMultisampling_start 46 +#define GEN9_3DSTATE_RASTER_ForceMultisampling_start 46 +#define GEN8_3DSTATE_RASTER_ForceMultisampling_start 46 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_ForceMultisampling_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 46; + case 10: return 46; + case 9: return 46; + case 8: return 46; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RASTER::Forced Sample Count */ + + +#define GEN11_3DSTATE_RASTER_ForcedSampleCount_bits 3 +#define GEN10_3DSTATE_RASTER_ForcedSampleCount_bits 3 +#define GEN9_3DSTATE_RASTER_ForcedSampleCount_bits 3 +#define GEN8_3DSTATE_RASTER_ForcedSampleCount_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_ForcedSampleCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_RASTER_ForcedSampleCount_start 50 +#define GEN10_3DSTATE_RASTER_ForcedSampleCount_start 50 +#define GEN9_3DSTATE_RASTER_ForcedSampleCount_start 50 +#define GEN8_3DSTATE_RASTER_ForcedSampleCount_start 50 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_ForcedSampleCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 50; + case 10: return 50; + case 9: return 50; + case 8: return 50; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RASTER::Front Face Fill Mode */ + + +#define GEN11_3DSTATE_RASTER_FrontFaceFillMode_bits 2 +#define GEN10_3DSTATE_RASTER_FrontFaceFillMode_bits 2 +#define GEN9_3DSTATE_RASTER_FrontFaceFillMode_bits 2 +#define GEN8_3DSTATE_RASTER_FrontFaceFillMode_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_FrontFaceFillMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_RASTER_FrontFaceFillMode_start 37 +#define GEN10_3DSTATE_RASTER_FrontFaceFillMode_start 37 +#define GEN9_3DSTATE_RASTER_FrontFaceFillMode_start 37 +#define GEN8_3DSTATE_RASTER_FrontFaceFillMode_start 37 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_FrontFaceFillMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 37; + case 10: return 37; + case 9: return 37; + case 8: return 37; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RASTER::Front Winding */ + + +#define GEN11_3DSTATE_RASTER_FrontWinding_bits 1 +#define GEN10_3DSTATE_RASTER_FrontWinding_bits 1 +#define GEN9_3DSTATE_RASTER_FrontWinding_bits 1 +#define GEN8_3DSTATE_RASTER_FrontWinding_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_FrontWinding_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_RASTER_FrontWinding_start 53 +#define GEN10_3DSTATE_RASTER_FrontWinding_start 53 +#define GEN9_3DSTATE_RASTER_FrontWinding_start 53 +#define GEN8_3DSTATE_RASTER_FrontWinding_start 53 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_FrontWinding_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 53; + case 10: return 53; + case 9: return 53; + case 8: return 53; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RASTER::Global Depth Offset Clamp */ + + +#define GEN11_3DSTATE_RASTER_GlobalDepthOffsetClamp_bits 32 +#define GEN10_3DSTATE_RASTER_GlobalDepthOffsetClamp_bits 32 +#define GEN9_3DSTATE_RASTER_GlobalDepthOffsetClamp_bits 32 +#define GEN8_3DSTATE_RASTER_GlobalDepthOffsetClamp_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_GlobalDepthOffsetClamp_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_RASTER_GlobalDepthOffsetClamp_start 128 +#define GEN10_3DSTATE_RASTER_GlobalDepthOffsetClamp_start 128 +#define GEN9_3DSTATE_RASTER_GlobalDepthOffsetClamp_start 128 +#define GEN8_3DSTATE_RASTER_GlobalDepthOffsetClamp_start 128 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_GlobalDepthOffsetClamp_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 128; + case 10: return 128; + case 9: return 128; + case 8: return 128; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RASTER::Global Depth Offset Constant */ + + +#define GEN11_3DSTATE_RASTER_GlobalDepthOffsetConstant_bits 32 +#define GEN10_3DSTATE_RASTER_GlobalDepthOffsetConstant_bits 32 +#define GEN9_3DSTATE_RASTER_GlobalDepthOffsetConstant_bits 32 +#define GEN8_3DSTATE_RASTER_GlobalDepthOffsetConstant_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_GlobalDepthOffsetConstant_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_RASTER_GlobalDepthOffsetConstant_start 64 +#define GEN10_3DSTATE_RASTER_GlobalDepthOffsetConstant_start 64 +#define GEN9_3DSTATE_RASTER_GlobalDepthOffsetConstant_start 64 +#define GEN8_3DSTATE_RASTER_GlobalDepthOffsetConstant_start 64 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_GlobalDepthOffsetConstant_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RASTER::Global Depth Offset Enable Point */ + + +#define GEN11_3DSTATE_RASTER_GlobalDepthOffsetEnablePoint_bits 1 +#define GEN10_3DSTATE_RASTER_GlobalDepthOffsetEnablePoint_bits 1 +#define GEN9_3DSTATE_RASTER_GlobalDepthOffsetEnablePoint_bits 1 +#define GEN8_3DSTATE_RASTER_GlobalDepthOffsetEnablePoint_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_GlobalDepthOffsetEnablePoint_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_RASTER_GlobalDepthOffsetEnablePoint_start 39 +#define GEN10_3DSTATE_RASTER_GlobalDepthOffsetEnablePoint_start 39 +#define GEN9_3DSTATE_RASTER_GlobalDepthOffsetEnablePoint_start 39 +#define GEN8_3DSTATE_RASTER_GlobalDepthOffsetEnablePoint_start 39 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_GlobalDepthOffsetEnablePoint_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 39; + case 10: return 39; + case 9: return 39; + case 8: return 39; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RASTER::Global Depth Offset Enable Solid */ + + +#define GEN11_3DSTATE_RASTER_GlobalDepthOffsetEnableSolid_bits 1 +#define GEN10_3DSTATE_RASTER_GlobalDepthOffsetEnableSolid_bits 1 +#define GEN9_3DSTATE_RASTER_GlobalDepthOffsetEnableSolid_bits 1 +#define GEN8_3DSTATE_RASTER_GlobalDepthOffsetEnableSolid_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_GlobalDepthOffsetEnableSolid_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_RASTER_GlobalDepthOffsetEnableSolid_start 41 +#define GEN10_3DSTATE_RASTER_GlobalDepthOffsetEnableSolid_start 41 +#define GEN9_3DSTATE_RASTER_GlobalDepthOffsetEnableSolid_start 41 +#define GEN8_3DSTATE_RASTER_GlobalDepthOffsetEnableSolid_start 41 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_GlobalDepthOffsetEnableSolid_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 41; + case 10: return 41; + case 9: return 41; + case 8: return 41; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RASTER::Global Depth Offset Enable Wireframe */ + + +#define GEN11_3DSTATE_RASTER_GlobalDepthOffsetEnableWireframe_bits 1 +#define GEN10_3DSTATE_RASTER_GlobalDepthOffsetEnableWireframe_bits 1 +#define GEN9_3DSTATE_RASTER_GlobalDepthOffsetEnableWireframe_bits 1 +#define GEN8_3DSTATE_RASTER_GlobalDepthOffsetEnableWireframe_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_GlobalDepthOffsetEnableWireframe_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_RASTER_GlobalDepthOffsetEnableWireframe_start 40 +#define GEN10_3DSTATE_RASTER_GlobalDepthOffsetEnableWireframe_start 40 +#define GEN9_3DSTATE_RASTER_GlobalDepthOffsetEnableWireframe_start 40 +#define GEN8_3DSTATE_RASTER_GlobalDepthOffsetEnableWireframe_start 40 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_GlobalDepthOffsetEnableWireframe_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 40; + case 10: return 40; + case 9: return 40; + case 8: return 40; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RASTER::Global Depth Offset Scale */ + + +#define GEN11_3DSTATE_RASTER_GlobalDepthOffsetScale_bits 32 +#define GEN10_3DSTATE_RASTER_GlobalDepthOffsetScale_bits 32 +#define GEN9_3DSTATE_RASTER_GlobalDepthOffsetScale_bits 32 +#define GEN8_3DSTATE_RASTER_GlobalDepthOffsetScale_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_GlobalDepthOffsetScale_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_RASTER_GlobalDepthOffsetScale_start 96 +#define GEN10_3DSTATE_RASTER_GlobalDepthOffsetScale_start 96 +#define GEN9_3DSTATE_RASTER_GlobalDepthOffsetScale_start 96 +#define GEN8_3DSTATE_RASTER_GlobalDepthOffsetScale_start 96 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_GlobalDepthOffsetScale_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 96; + case 10: return 96; + case 9: return 96; + case 8: return 96; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RASTER::Scissor Rectangle Enable */ + + +#define GEN11_3DSTATE_RASTER_ScissorRectangleEnable_bits 1 +#define GEN10_3DSTATE_RASTER_ScissorRectangleEnable_bits 1 +#define GEN9_3DSTATE_RASTER_ScissorRectangleEnable_bits 1 +#define GEN8_3DSTATE_RASTER_ScissorRectangleEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_ScissorRectangleEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_RASTER_ScissorRectangleEnable_start 33 +#define GEN10_3DSTATE_RASTER_ScissorRectangleEnable_start 33 +#define GEN9_3DSTATE_RASTER_ScissorRectangleEnable_start 33 +#define GEN8_3DSTATE_RASTER_ScissorRectangleEnable_start 33 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_ScissorRectangleEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 33; + case 10: return 33; + case 9: return 33; + case 8: return 33; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RASTER::Smooth Point Enable */ + + +#define GEN11_3DSTATE_RASTER_SmoothPointEnable_bits 1 +#define GEN10_3DSTATE_RASTER_SmoothPointEnable_bits 1 +#define GEN9_3DSTATE_RASTER_SmoothPointEnable_bits 1 +#define GEN8_3DSTATE_RASTER_SmoothPointEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_SmoothPointEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_RASTER_SmoothPointEnable_start 45 +#define GEN10_3DSTATE_RASTER_SmoothPointEnable_start 45 +#define GEN9_3DSTATE_RASTER_SmoothPointEnable_start 45 +#define GEN8_3DSTATE_RASTER_SmoothPointEnable_start 45 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_SmoothPointEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 45; + case 10: return 45; + case 9: return 45; + case 8: return 45; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RASTER::Viewport Z Clip Test Enable */ + + +#define GEN8_3DSTATE_RASTER_ViewportZClipTestEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_ViewportZClipTestEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_3DSTATE_RASTER_ViewportZClipTestEnable_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_ViewportZClipTestEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RASTER::Viewport Z Far Clip Test Enable */ + + +#define GEN11_3DSTATE_RASTER_ViewportZFarClipTestEnable_bits 1 +#define GEN10_3DSTATE_RASTER_ViewportZFarClipTestEnable_bits 1 +#define GEN9_3DSTATE_RASTER_ViewportZFarClipTestEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_ViewportZFarClipTestEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_RASTER_ViewportZFarClipTestEnable_start 58 +#define GEN10_3DSTATE_RASTER_ViewportZFarClipTestEnable_start 58 +#define GEN9_3DSTATE_RASTER_ViewportZFarClipTestEnable_start 58 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_ViewportZFarClipTestEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 58; + case 10: return 58; + case 9: return 58; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RASTER::Viewport Z Near Clip Test Enable */ + + +#define GEN11_3DSTATE_RASTER_ViewportZNearClipTestEnable_bits 1 +#define GEN10_3DSTATE_RASTER_ViewportZNearClipTestEnable_bits 1 +#define GEN9_3DSTATE_RASTER_ViewportZNearClipTestEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_ViewportZNearClipTestEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_RASTER_ViewportZNearClipTestEnable_start 32 +#define GEN10_3DSTATE_RASTER_ViewportZNearClipTestEnable_start 32 +#define GEN9_3DSTATE_RASTER_ViewportZNearClipTestEnable_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RASTER_ViewportZNearClipTestEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_length 6 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE::3D Command Opcode */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE::3D Command Sub Opcode */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE::Command SubType */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE::Command Type */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE::DWord Length */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE::Number of Rasterization Multisamples */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_NumberofRasterizationMultisamples_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_NumberofRasterizationMultisamples_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_NumberofRasterizationMultisamples_start 33 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_NumberofRasterizationMultisamples_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 33; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE::Sample0 X Offset */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample0XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample0XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample0XOffset_start 68 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample0XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 68; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE::Sample0 Y Offset */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample0YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample0YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample0YOffset_start 64 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample0YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE::Sample1 X Offset */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample1XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample1XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample1XOffset_start 76 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample1XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 76; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE::Sample1 Y Offset */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample1YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample1YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample1YOffset_start 72 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample1YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 72; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE::Sample10 X Offset */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample10XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample10XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample10XOffset_start 148 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample10XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 148; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE::Sample10 Y Offset */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample10YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample10YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample10YOffset_start 144 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample10YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 144; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE::Sample11 X Offset */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample11XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample11XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample11XOffset_start 156 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample11XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 156; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE::Sample11 Y Offset */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample11YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample11YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample11YOffset_start 152 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample11YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 152; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE::Sample12 X Offset */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample12XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample12XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample12XOffset_start 164 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample12XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 164; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE::Sample12 Y Offset */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample12YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample12YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample12YOffset_start 160 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample12YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 160; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE::Sample13 X Offset */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample13XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample13XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample13XOffset_start 172 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample13XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 172; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE::Sample13 Y Offset */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample13YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample13YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample13YOffset_start 168 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample13YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 168; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE::Sample14 X Offset */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample14XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample14XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample14XOffset_start 180 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample14XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 180; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE::Sample14 Y Offset */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample14YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample14YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample14YOffset_start 176 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample14YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 176; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE::Sample15 X Offset */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample15XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample15XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample15XOffset_start 188 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample15XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 188; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE::Sample15 Y Offset */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample15YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample15YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample15YOffset_start 184 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample15YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 184; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE::Sample2 X Offset */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample2XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample2XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample2XOffset_start 84 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample2XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 84; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE::Sample2 Y Offset */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample2YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample2YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample2YOffset_start 80 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample2YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 80; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE::Sample3 X Offset */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample3XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample3XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample3XOffset_start 92 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample3XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 92; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE::Sample3 Y Offset */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample3YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample3YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample3YOffset_start 88 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample3YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 88; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE::Sample4 X Offset */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample4XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample4XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample4XOffset_start 100 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample4XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 100; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE::Sample4 Y Offset */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample4YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample4YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample4YOffset_start 96 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample4YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 96; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE::Sample5 X Offset */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample5XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample5XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample5XOffset_start 108 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample5XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 108; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE::Sample5 Y Offset */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample5YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample5YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample5YOffset_start 104 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample5YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 104; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE::Sample6 X Offset */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample6XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample6XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample6XOffset_start 116 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample6XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 116; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE::Sample6 Y Offset */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample6YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample6YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample6YOffset_start 112 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample6YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 112; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE::Sample7 X Offset */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample7XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample7XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample7XOffset_start 124 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample7XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 124; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE::Sample7 Y Offset */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample7YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample7YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample7YOffset_start 120 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample7YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 120; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE::Sample8 X Offset */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample8XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample8XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample8XOffset_start 132 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample8XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 132; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE::Sample8 Y Offset */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample8YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample8YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample8YOffset_start 128 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample8YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 128; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE::Sample9 X Offset */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample9XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample9XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample9XOffset_start 140 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample9XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 140; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RAST_MULTISAMPLE::Sample9 Y Offset */ + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample9YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample9YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_RAST_MULTISAMPLE_Sample9YOffset_start 136 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RAST_MULTISAMPLE_Sample9YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 136; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RS_CONSTANT_POINTER */ + + +#define GEN11_3DSTATE_RS_CONSTANT_POINTER_length 4 +#define GEN10_3DSTATE_RS_CONSTANT_POINTER_length 4 +#define GEN9_3DSTATE_RS_CONSTANT_POINTER_length 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RS_CONSTANT_POINTER_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RS_CONSTANT_POINTER::3D Command Opcode */ + + +#define GEN11_3DSTATE_RS_CONSTANT_POINTER_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_RS_CONSTANT_POINTER_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_RS_CONSTANT_POINTER_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RS_CONSTANT_POINTER_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_RS_CONSTANT_POINTER_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_RS_CONSTANT_POINTER_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_RS_CONSTANT_POINTER_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RS_CONSTANT_POINTER_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RS_CONSTANT_POINTER::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_RS_CONSTANT_POINTER_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_RS_CONSTANT_POINTER_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_RS_CONSTANT_POINTER_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RS_CONSTANT_POINTER_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_RS_CONSTANT_POINTER_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_RS_CONSTANT_POINTER_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_RS_CONSTANT_POINTER_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RS_CONSTANT_POINTER_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RS_CONSTANT_POINTER::Command SubType */ + + +#define GEN11_3DSTATE_RS_CONSTANT_POINTER_CommandSubType_bits 2 +#define GEN10_3DSTATE_RS_CONSTANT_POINTER_CommandSubType_bits 2 +#define GEN9_3DSTATE_RS_CONSTANT_POINTER_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RS_CONSTANT_POINTER_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_RS_CONSTANT_POINTER_CommandSubType_start 27 +#define GEN10_3DSTATE_RS_CONSTANT_POINTER_CommandSubType_start 27 +#define GEN9_3DSTATE_RS_CONSTANT_POINTER_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RS_CONSTANT_POINTER_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RS_CONSTANT_POINTER::Command Type */ + + +#define GEN11_3DSTATE_RS_CONSTANT_POINTER_CommandType_bits 3 +#define GEN10_3DSTATE_RS_CONSTANT_POINTER_CommandType_bits 3 +#define GEN9_3DSTATE_RS_CONSTANT_POINTER_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RS_CONSTANT_POINTER_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_RS_CONSTANT_POINTER_CommandType_start 29 +#define GEN10_3DSTATE_RS_CONSTANT_POINTER_CommandType_start 29 +#define GEN9_3DSTATE_RS_CONSTANT_POINTER_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RS_CONSTANT_POINTER_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RS_CONSTANT_POINTER::DWord Length */ + + +#define GEN11_3DSTATE_RS_CONSTANT_POINTER_DWordLength_bits 8 +#define GEN10_3DSTATE_RS_CONSTANT_POINTER_DWordLength_bits 8 +#define GEN9_3DSTATE_RS_CONSTANT_POINTER_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RS_CONSTANT_POINTER_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_RS_CONSTANT_POINTER_DWordLength_start 0 +#define GEN10_3DSTATE_RS_CONSTANT_POINTER_DWordLength_start 0 +#define GEN9_3DSTATE_RS_CONSTANT_POINTER_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RS_CONSTANT_POINTER_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RS_CONSTANT_POINTER::Global Constant Buffer Address */ + + +#define GEN11_3DSTATE_RS_CONSTANT_POINTER_GlobalConstantBufferAddress_bits 26 +#define GEN10_3DSTATE_RS_CONSTANT_POINTER_GlobalConstantBufferAddress_bits 26 +#define GEN9_3DSTATE_RS_CONSTANT_POINTER_GlobalConstantBufferAddress_bits 26 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RS_CONSTANT_POINTER_GlobalConstantBufferAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 26; + case 10: return 26; + case 9: return 26; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_RS_CONSTANT_POINTER_GlobalConstantBufferAddress_start 70 +#define GEN10_3DSTATE_RS_CONSTANT_POINTER_GlobalConstantBufferAddress_start 70 +#define GEN9_3DSTATE_RS_CONSTANT_POINTER_GlobalConstantBufferAddress_start 70 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RS_CONSTANT_POINTER_GlobalConstantBufferAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 70; + case 10: return 70; + case 9: return 70; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RS_CONSTANT_POINTER::Global Constant Buffer Address High */ + + +#define GEN11_3DSTATE_RS_CONSTANT_POINTER_GlobalConstantBufferAddressHigh_bits 32 +#define GEN10_3DSTATE_RS_CONSTANT_POINTER_GlobalConstantBufferAddressHigh_bits 32 +#define GEN9_3DSTATE_RS_CONSTANT_POINTER_GlobalConstantBufferAddressHigh_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RS_CONSTANT_POINTER_GlobalConstantBufferAddressHigh_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_RS_CONSTANT_POINTER_GlobalConstantBufferAddressHigh_start 96 +#define GEN10_3DSTATE_RS_CONSTANT_POINTER_GlobalConstantBufferAddressHigh_start 96 +#define GEN9_3DSTATE_RS_CONSTANT_POINTER_GlobalConstantBufferAddressHigh_start 96 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RS_CONSTANT_POINTER_GlobalConstantBufferAddressHigh_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 96; + case 10: return 96; + case 9: return 96; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RS_CONSTANT_POINTER::Operation Load or Store */ + + +#define GEN11_3DSTATE_RS_CONSTANT_POINTER_OperationLoadorStore_bits 1 +#define GEN10_3DSTATE_RS_CONSTANT_POINTER_OperationLoadorStore_bits 1 +#define GEN9_3DSTATE_RS_CONSTANT_POINTER_OperationLoadorStore_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RS_CONSTANT_POINTER_OperationLoadorStore_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_RS_CONSTANT_POINTER_OperationLoadorStore_start 44 +#define GEN10_3DSTATE_RS_CONSTANT_POINTER_OperationLoadorStore_start 44 +#define GEN9_3DSTATE_RS_CONSTANT_POINTER_OperationLoadorStore_start 44 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RS_CONSTANT_POINTER_OperationLoadorStore_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 44; + case 10: return 44; + case 9: return 44; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_RS_CONSTANT_POINTER::Shader Select */ + + +#define GEN11_3DSTATE_RS_CONSTANT_POINTER_ShaderSelect_bits 3 +#define GEN10_3DSTATE_RS_CONSTANT_POINTER_ShaderSelect_bits 3 +#define GEN9_3DSTATE_RS_CONSTANT_POINTER_ShaderSelect_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RS_CONSTANT_POINTER_ShaderSelect_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_RS_CONSTANT_POINTER_ShaderSelect_start 60 +#define GEN10_3DSTATE_RS_CONSTANT_POINTER_ShaderSelect_start 60 +#define GEN9_3DSTATE_RS_CONSTANT_POINTER_ShaderSelect_start 60 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_RS_CONSTANT_POINTER_ShaderSelect_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 60; + case 10: return 60; + case 9: return 60; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_PALETTE_LOAD0 */ + + + + + +/* 3DSTATE_SAMPLER_PALETTE_LOAD0::3D Command Opcode */ + + +#define GEN11_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandOpcode_bits 3 +#define GEN6_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandOpcode_start 24 +#define GEN6_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_PALETTE_LOAD0::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandSubOpcode_bits 8 +#define GEN6_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandSubOpcode_start 16 +#define GEN6_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_PALETTE_LOAD0_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_PALETTE_LOAD0::Command SubType */ + + +#define GEN11_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandSubType_bits 2 +#define GEN10_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandSubType_bits 2 +#define GEN9_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandSubType_bits 2 +#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandSubType_bits 2 +#define GEN75_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandSubType_bits 2 +#define GEN7_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandSubType_bits 2 +#define GEN6_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandSubType_start 27 +#define GEN10_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandSubType_start 27 +#define GEN9_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandSubType_start 27 +#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandSubType_start 27 +#define GEN75_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandSubType_start 27 +#define GEN7_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandSubType_start 27 +#define GEN6_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_PALETTE_LOAD0::Command Type */ + + +#define GEN11_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandType_bits 3 +#define GEN10_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandType_bits 3 +#define GEN9_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandType_bits 3 +#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandType_bits 3 +#define GEN75_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandType_bits 3 +#define GEN7_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandType_bits 3 +#define GEN6_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandType_start 29 +#define GEN10_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandType_start 29 +#define GEN9_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandType_start 29 +#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandType_start 29 +#define GEN75_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandType_start 29 +#define GEN7_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandType_start 29 +#define GEN6_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_PALETTE_LOAD0_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_PALETTE_LOAD0::DWord Length */ + + +#define GEN11_3DSTATE_SAMPLER_PALETTE_LOAD0_DWordLength_bits 8 +#define GEN10_3DSTATE_SAMPLER_PALETTE_LOAD0_DWordLength_bits 8 +#define GEN9_3DSTATE_SAMPLER_PALETTE_LOAD0_DWordLength_bits 8 +#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD0_DWordLength_bits 8 +#define GEN75_3DSTATE_SAMPLER_PALETTE_LOAD0_DWordLength_bits 8 +#define GEN7_3DSTATE_SAMPLER_PALETTE_LOAD0_DWordLength_bits 8 +#define GEN6_3DSTATE_SAMPLER_PALETTE_LOAD0_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_PALETTE_LOAD0_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_PALETTE_LOAD0_DWordLength_start 0 +#define GEN10_3DSTATE_SAMPLER_PALETTE_LOAD0_DWordLength_start 0 +#define GEN9_3DSTATE_SAMPLER_PALETTE_LOAD0_DWordLength_start 0 +#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD0_DWordLength_start 0 +#define GEN75_3DSTATE_SAMPLER_PALETTE_LOAD0_DWordLength_start 0 +#define GEN7_3DSTATE_SAMPLER_PALETTE_LOAD0_DWordLength_start 0 +#define GEN6_3DSTATE_SAMPLER_PALETTE_LOAD0_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_PALETTE_LOAD0_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_PALETTE_LOAD0::Entry */ + + +#define GEN11_3DSTATE_SAMPLER_PALETTE_LOAD0_Entry_bits 32 +#define GEN10_3DSTATE_SAMPLER_PALETTE_LOAD0_Entry_bits 32 +#define GEN9_3DSTATE_SAMPLER_PALETTE_LOAD0_Entry_bits 32 +#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD0_Entry_bits 32 +#define GEN75_3DSTATE_SAMPLER_PALETTE_LOAD0_Entry_bits 32 +#define GEN7_3DSTATE_SAMPLER_PALETTE_LOAD0_Entry_bits 32 +#define GEN6_3DSTATE_SAMPLER_PALETTE_LOAD0_Entry_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_PALETTE_LOAD0_Entry_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_PALETTE_LOAD0_Entry_start 0 +#define GEN10_3DSTATE_SAMPLER_PALETTE_LOAD0_Entry_start 0 +#define GEN9_3DSTATE_SAMPLER_PALETTE_LOAD0_Entry_start 0 +#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD0_Entry_start 0 +#define GEN75_3DSTATE_SAMPLER_PALETTE_LOAD0_Entry_start 0 +#define GEN7_3DSTATE_SAMPLER_PALETTE_LOAD0_Entry_start 0 +#define GEN6_3DSTATE_SAMPLER_PALETTE_LOAD0_Entry_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_PALETTE_LOAD0_Entry_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_PALETTE_LOAD1 */ + + + + + +/* 3DSTATE_SAMPLER_PALETTE_LOAD1::3D Command Opcode */ + + +#define GEN11_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandOpcode_bits 3 +#define GEN6_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandOpcode_start 24 +#define GEN6_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_PALETTE_LOAD1::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandSubOpcode_bits 8 +#define GEN6_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandSubOpcode_start 16 +#define GEN6_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_PALETTE_LOAD1_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_PALETTE_LOAD1::Command SubType */ + + +#define GEN11_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandSubType_bits 2 +#define GEN10_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandSubType_bits 2 +#define GEN9_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandSubType_bits 2 +#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandSubType_bits 2 +#define GEN75_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandSubType_bits 2 +#define GEN7_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandSubType_bits 2 +#define GEN6_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandSubType_start 27 +#define GEN10_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandSubType_start 27 +#define GEN9_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandSubType_start 27 +#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandSubType_start 27 +#define GEN75_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandSubType_start 27 +#define GEN7_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandSubType_start 27 +#define GEN6_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_PALETTE_LOAD1::Command Type */ + + +#define GEN11_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandType_bits 3 +#define GEN10_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandType_bits 3 +#define GEN9_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandType_bits 3 +#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandType_bits 3 +#define GEN75_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandType_bits 3 +#define GEN7_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandType_bits 3 +#define GEN6_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandType_start 29 +#define GEN10_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandType_start 29 +#define GEN9_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandType_start 29 +#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandType_start 29 +#define GEN75_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandType_start 29 +#define GEN7_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandType_start 29 +#define GEN6_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_PALETTE_LOAD1_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_PALETTE_LOAD1::DWord Length */ + + +#define GEN11_3DSTATE_SAMPLER_PALETTE_LOAD1_DWordLength_bits 8 +#define GEN10_3DSTATE_SAMPLER_PALETTE_LOAD1_DWordLength_bits 8 +#define GEN9_3DSTATE_SAMPLER_PALETTE_LOAD1_DWordLength_bits 8 +#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD1_DWordLength_bits 8 +#define GEN75_3DSTATE_SAMPLER_PALETTE_LOAD1_DWordLength_bits 8 +#define GEN7_3DSTATE_SAMPLER_PALETTE_LOAD1_DWordLength_bits 8 +#define GEN6_3DSTATE_SAMPLER_PALETTE_LOAD1_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_PALETTE_LOAD1_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_PALETTE_LOAD1_DWordLength_start 0 +#define GEN10_3DSTATE_SAMPLER_PALETTE_LOAD1_DWordLength_start 0 +#define GEN9_3DSTATE_SAMPLER_PALETTE_LOAD1_DWordLength_start 0 +#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD1_DWordLength_start 0 +#define GEN75_3DSTATE_SAMPLER_PALETTE_LOAD1_DWordLength_start 0 +#define GEN7_3DSTATE_SAMPLER_PALETTE_LOAD1_DWordLength_start 0 +#define GEN6_3DSTATE_SAMPLER_PALETTE_LOAD1_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_PALETTE_LOAD1_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_PALETTE_LOAD1::Palette Alpha[0:N-1] */ + + +#define GEN11_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteAlpha0N1_bits 8 +#define GEN10_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteAlpha0N1_bits 8 +#define GEN9_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteAlpha0N1_bits 8 +#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteAlpha0N1_bits 8 +#define GEN75_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteAlpha0N1_bits 8 +#define GEN7_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteAlpha0N1_bits 8 +#define GEN6_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteAlpha0N1_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteAlpha0N1_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteAlpha0N1_start 24 +#define GEN10_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteAlpha0N1_start 24 +#define GEN9_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteAlpha0N1_start 24 +#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteAlpha0N1_start 24 +#define GEN75_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteAlpha0N1_start 24 +#define GEN7_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteAlpha0N1_start 24 +#define GEN6_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteAlpha0N1_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteAlpha0N1_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_PALETTE_LOAD1::Palette Blue[0:N-1] */ + + +#define GEN11_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteBlue0N1_bits 8 +#define GEN10_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteBlue0N1_bits 8 +#define GEN9_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteBlue0N1_bits 8 +#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteBlue0N1_bits 8 +#define GEN75_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteBlue0N1_bits 8 +#define GEN7_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteBlue0N1_bits 8 +#define GEN6_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteBlue0N1_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteBlue0N1_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteBlue0N1_start 0 +#define GEN10_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteBlue0N1_start 0 +#define GEN9_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteBlue0N1_start 0 +#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteBlue0N1_start 0 +#define GEN75_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteBlue0N1_start 0 +#define GEN7_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteBlue0N1_start 0 +#define GEN6_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteBlue0N1_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteBlue0N1_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_PALETTE_LOAD1::Palette Green[0:N-1] */ + + +#define GEN11_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteGreen0N1_bits 8 +#define GEN10_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteGreen0N1_bits 8 +#define GEN9_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteGreen0N1_bits 8 +#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteGreen0N1_bits 8 +#define GEN75_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteGreen0N1_bits 8 +#define GEN7_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteGreen0N1_bits 8 +#define GEN6_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteGreen0N1_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteGreen0N1_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteGreen0N1_start 8 +#define GEN10_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteGreen0N1_start 8 +#define GEN9_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteGreen0N1_start 8 +#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteGreen0N1_start 8 +#define GEN75_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteGreen0N1_start 8 +#define GEN7_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteGreen0N1_start 8 +#define GEN6_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteGreen0N1_start 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteGreen0N1_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_PALETTE_LOAD1::Palette Red[0:N-1] */ + + +#define GEN11_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteRed0N1_bits 8 +#define GEN10_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteRed0N1_bits 8 +#define GEN9_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteRed0N1_bits 8 +#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteRed0N1_bits 8 +#define GEN75_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteRed0N1_bits 8 +#define GEN7_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteRed0N1_bits 8 +#define GEN6_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteRed0N1_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteRed0N1_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteRed0N1_start 16 +#define GEN10_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteRed0N1_start 16 +#define GEN9_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteRed0N1_start 16 +#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteRed0N1_start 16 +#define GEN75_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteRed0N1_start 16 +#define GEN7_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteRed0N1_start 16 +#define GEN6_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteRed0N1_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_PALETTE_LOAD1_PaletteRed0N1_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS */ + + +#define GEN6_3DSTATE_SAMPLER_STATE_POINTERS_length 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS::3D Command Opcode */ + + +#define GEN6_3DSTATE_SAMPLER_STATE_POINTERS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_SAMPLER_STATE_POINTERS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 24; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS::3D Command Sub Opcode */ + + +#define GEN6_3DSTATE_SAMPLER_STATE_POINTERS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_SAMPLER_STATE_POINTERS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS::Command SubType */ + + +#define GEN6_3DSTATE_SAMPLER_STATE_POINTERS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_SAMPLER_STATE_POINTERS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS::Command Type */ + + +#define GEN6_3DSTATE_SAMPLER_STATE_POINTERS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_SAMPLER_STATE_POINTERS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS::DWord Length */ + + +#define GEN6_3DSTATE_SAMPLER_STATE_POINTERS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_SAMPLER_STATE_POINTERS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS::GS Sampler State Change */ + + +#define GEN6_3DSTATE_SAMPLER_STATE_POINTERS_GSSamplerStateChange_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_GSSamplerStateChange_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_SAMPLER_STATE_POINTERS_GSSamplerStateChange_start 9 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_GSSamplerStateChange_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 9; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS::PS Sampler State Change */ + + +#define GEN6_3DSTATE_SAMPLER_STATE_POINTERS_PSSamplerStateChange_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_PSSamplerStateChange_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_SAMPLER_STATE_POINTERS_PSSamplerStateChange_start 12 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_PSSamplerStateChange_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 12; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS::Pointer to GS Sampler State */ + + +#define GEN6_3DSTATE_SAMPLER_STATE_POINTERS_PointertoGSSamplerState_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_PointertoGSSamplerState_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_SAMPLER_STATE_POINTERS_PointertoGSSamplerState_start 69 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_PointertoGSSamplerState_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 69; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS::Pointer to PS Sampler State */ + + +#define GEN6_3DSTATE_SAMPLER_STATE_POINTERS_PointertoPSSamplerState_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_PointertoPSSamplerState_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_SAMPLER_STATE_POINTERS_PointertoPSSamplerState_start 101 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_PointertoPSSamplerState_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 101; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS::Pointer to VS Sampler State */ + + +#define GEN6_3DSTATE_SAMPLER_STATE_POINTERS_PointertoVSSamplerState_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_PointertoVSSamplerState_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_SAMPLER_STATE_POINTERS_PointertoVSSamplerState_start 37 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_PointertoVSSamplerState_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 37; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS::VS Sampler State Change */ + + +#define GEN6_3DSTATE_SAMPLER_STATE_POINTERS_VSSamplerStateChange_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_VSSamplerStateChange_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_SAMPLER_STATE_POINTERS_VSSamplerStateChange_start 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_VSSamplerStateChange_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS_DS */ + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_DS_length 2 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_DS_length 2 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_DS_length 2 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_DS_length 2 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_DS_length 2 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_DS_length 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_DS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS_DS::3D Command Opcode */ + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS_DS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_DS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS_DS::Command SubType */ + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandSubType_bits 2 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandSubType_bits 2 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandSubType_bits 2 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandSubType_bits 2 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandSubType_bits 2 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandSubType_start 27 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandSubType_start 27 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandSubType_start 27 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandSubType_start 27 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandSubType_start 27 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS_DS::Command Type */ + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandType_bits 3 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandType_bits 3 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandType_bits 3 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandType_bits 3 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandType_bits 3 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandType_start 29 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandType_start 29 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandType_start 29 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandType_start 29 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandType_start 29 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_DS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS_DS::DWord Length */ + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_DS_DWordLength_bits 8 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_DS_DWordLength_bits 8 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_DS_DWordLength_bits 8 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_DS_DWordLength_bits 8 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_DS_DWordLength_bits 8 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_DS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_DS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_DS_DWordLength_start 0 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_DS_DWordLength_start 0 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_DS_DWordLength_start 0 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_DS_DWordLength_start 0 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_DS_DWordLength_start 0 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_DS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_DS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS_DS::Pointer to DS Sampler State */ + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_DS_PointertoDSSamplerState_bits 27 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_DS_PointertoDSSamplerState_bits 27 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_DS_PointertoDSSamplerState_bits 27 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_DS_PointertoDSSamplerState_bits 27 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_DS_PointertoDSSamplerState_bits 27 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_DS_PointertoDSSamplerState_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_DS_PointertoDSSamplerState_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_DS_PointertoDSSamplerState_start 37 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_DS_PointertoDSSamplerState_start 37 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_DS_PointertoDSSamplerState_start 37 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_DS_PointertoDSSamplerState_start 37 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_DS_PointertoDSSamplerState_start 37 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_DS_PointertoDSSamplerState_start 37 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_DS_PointertoDSSamplerState_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 37; + case 10: return 37; + case 9: return 37; + case 8: return 37; + case 7: + if (devinfo->is_haswell) { + return 37; + } else { + return 37; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS_GS */ + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_GS_length 2 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_GS_length 2 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_GS_length 2 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_GS_length 2 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_GS_length 2 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS_length 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_GS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS_GS::3D Command Opcode */ + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS_GS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_GS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS_GS::Command SubType */ + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandSubType_bits 2 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandSubType_bits 2 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandSubType_bits 2 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandSubType_bits 2 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandSubType_bits 2 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandSubType_start 27 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandSubType_start 27 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandSubType_start 27 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandSubType_start 27 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandSubType_start 27 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS_GS::Command Type */ + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandType_bits 3 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandType_bits 3 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandType_bits 3 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandType_bits 3 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandType_bits 3 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandType_start 29 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandType_start 29 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandType_start 29 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandType_start 29 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandType_start 29 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_GS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS_GS::DWord Length */ + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_GS_DWordLength_bits 8 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_GS_DWordLength_bits 8 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_GS_DWordLength_bits 8 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_GS_DWordLength_bits 8 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_GS_DWordLength_bits 8 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_GS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_GS_DWordLength_start 0 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_GS_DWordLength_start 0 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_GS_DWordLength_start 0 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_GS_DWordLength_start 0 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_GS_DWordLength_start 0 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_GS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS_GS::Pointer to GS Sampler State */ + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_GS_PointertoGSSamplerState_bits 27 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_GS_PointertoGSSamplerState_bits 27 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_GS_PointertoGSSamplerState_bits 27 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_GS_PointertoGSSamplerState_bits 27 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_GS_PointertoGSSamplerState_bits 27 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS_PointertoGSSamplerState_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_GS_PointertoGSSamplerState_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_GS_PointertoGSSamplerState_start 37 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_GS_PointertoGSSamplerState_start 37 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_GS_PointertoGSSamplerState_start 37 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_GS_PointertoGSSamplerState_start 37 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_GS_PointertoGSSamplerState_start 37 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS_PointertoGSSamplerState_start 37 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_GS_PointertoGSSamplerState_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 37; + case 10: return 37; + case 9: return 37; + case 8: return 37; + case 7: + if (devinfo->is_haswell) { + return 37; + } else { + return 37; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS_HS */ + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_HS_length 2 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_HS_length 2 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_HS_length 2 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_HS_length 2 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_HS_length 2 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_HS_length 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_HS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS_HS::3D Command Opcode */ + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS_HS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_HS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS_HS::Command SubType */ + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandSubType_bits 2 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandSubType_bits 2 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandSubType_bits 2 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandSubType_bits 2 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandSubType_bits 2 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandSubType_start 27 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandSubType_start 27 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandSubType_start 27 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandSubType_start 27 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandSubType_start 27 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS_HS::Command Type */ + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandType_bits 3 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandType_bits 3 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandType_bits 3 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandType_bits 3 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandType_bits 3 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandType_start 29 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandType_start 29 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandType_start 29 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandType_start 29 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandType_start 29 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_HS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS_HS::DWord Length */ + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_HS_DWordLength_bits 8 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_HS_DWordLength_bits 8 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_HS_DWordLength_bits 8 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_HS_DWordLength_bits 8 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_HS_DWordLength_bits 8 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_HS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_HS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_HS_DWordLength_start 0 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_HS_DWordLength_start 0 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_HS_DWordLength_start 0 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_HS_DWordLength_start 0 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_HS_DWordLength_start 0 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_HS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_HS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS_HS::Pointer to HS Sampler State */ + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_HS_PointertoHSSamplerState_bits 27 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_HS_PointertoHSSamplerState_bits 27 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_HS_PointertoHSSamplerState_bits 27 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_HS_PointertoHSSamplerState_bits 27 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_HS_PointertoHSSamplerState_bits 27 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_HS_PointertoHSSamplerState_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_HS_PointertoHSSamplerState_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_HS_PointertoHSSamplerState_start 37 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_HS_PointertoHSSamplerState_start 37 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_HS_PointertoHSSamplerState_start 37 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_HS_PointertoHSSamplerState_start 37 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_HS_PointertoHSSamplerState_start 37 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_HS_PointertoHSSamplerState_start 37 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_HS_PointertoHSSamplerState_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 37; + case 10: return 37; + case 9: return 37; + case 8: return 37; + case 7: + if (devinfo->is_haswell) { + return 37; + } else { + return 37; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS_PS */ + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_PS_length 2 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_PS_length 2 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_PS_length 2 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_PS_length 2 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_PS_length 2 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS_length 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_PS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS_PS::3D Command Opcode */ + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS_PS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_PS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS_PS::Command SubType */ + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandSubType_bits 2 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandSubType_bits 2 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandSubType_bits 2 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandSubType_bits 2 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandSubType_bits 2 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandSubType_start 27 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandSubType_start 27 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandSubType_start 27 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandSubType_start 27 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandSubType_start 27 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS_PS::Command Type */ + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandType_bits 3 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandType_bits 3 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandType_bits 3 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandType_bits 3 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandType_bits 3 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandType_start 29 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandType_start 29 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandType_start 29 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandType_start 29 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandType_start 29 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_PS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS_PS::DWord Length */ + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_PS_DWordLength_bits 8 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_PS_DWordLength_bits 8 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_PS_DWordLength_bits 8 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_PS_DWordLength_bits 8 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_PS_DWordLength_bits 8 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_PS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_PS_DWordLength_start 0 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_PS_DWordLength_start 0 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_PS_DWordLength_start 0 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_PS_DWordLength_start 0 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_PS_DWordLength_start 0 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_PS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS_PS::Pointer to PS Sampler State */ + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_PS_PointertoPSSamplerState_bits 27 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_PS_PointertoPSSamplerState_bits 27 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_PS_PointertoPSSamplerState_bits 27 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_PS_PointertoPSSamplerState_bits 27 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_PS_PointertoPSSamplerState_bits 27 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS_PointertoPSSamplerState_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_PS_PointertoPSSamplerState_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_PS_PointertoPSSamplerState_start 37 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_PS_PointertoPSSamplerState_start 37 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_PS_PointertoPSSamplerState_start 37 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_PS_PointertoPSSamplerState_start 37 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_PS_PointertoPSSamplerState_start 37 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS_PointertoPSSamplerState_start 37 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_PS_PointertoPSSamplerState_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 37; + case 10: return 37; + case 9: return 37; + case 8: return 37; + case 7: + if (devinfo->is_haswell) { + return 37; + } else { + return 37; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS_VS */ + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_VS_length 2 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_VS_length 2 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_VS_length 2 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_VS_length 2 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_VS_length 2 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS_length 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_VS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS_VS::3D Command Opcode */ + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS_VS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_VS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS_VS::Command SubType */ + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandSubType_bits 2 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandSubType_bits 2 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandSubType_bits 2 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandSubType_bits 2 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandSubType_bits 2 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandSubType_start 27 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandSubType_start 27 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandSubType_start 27 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandSubType_start 27 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandSubType_start 27 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS_VS::Command Type */ + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandType_bits 3 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandType_bits 3 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandType_bits 3 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandType_bits 3 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandType_bits 3 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandType_start 29 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandType_start 29 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandType_start 29 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandType_start 29 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandType_start 29 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_VS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS_VS::DWord Length */ + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_VS_DWordLength_bits 8 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_VS_DWordLength_bits 8 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_VS_DWordLength_bits 8 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_VS_DWordLength_bits 8 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_VS_DWordLength_bits 8 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_VS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_VS_DWordLength_start 0 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_VS_DWordLength_start 0 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_VS_DWordLength_start 0 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_VS_DWordLength_start 0 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_VS_DWordLength_start 0 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_VS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLER_STATE_POINTERS_VS::Pointer to VS Sampler State */ + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_VS_PointertoVSSamplerState_bits 27 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_VS_PointertoVSSamplerState_bits 27 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_VS_PointertoVSSamplerState_bits 27 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_VS_PointertoVSSamplerState_bits 27 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_VS_PointertoVSSamplerState_bits 27 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS_PointertoVSSamplerState_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_VS_PointertoVSSamplerState_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLER_STATE_POINTERS_VS_PointertoVSSamplerState_start 37 +#define GEN10_3DSTATE_SAMPLER_STATE_POINTERS_VS_PointertoVSSamplerState_start 37 +#define GEN9_3DSTATE_SAMPLER_STATE_POINTERS_VS_PointertoVSSamplerState_start 37 +#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_VS_PointertoVSSamplerState_start 37 +#define GEN75_3DSTATE_SAMPLER_STATE_POINTERS_VS_PointertoVSSamplerState_start 37 +#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS_PointertoVSSamplerState_start 37 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLER_STATE_POINTERS_VS_PointertoVSSamplerState_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 37; + case 10: return 37; + case 9: return 37; + case 8: return 37; + case 7: + if (devinfo->is_haswell) { + return 37; + } else { + return 37; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_MASK */ + + +#define GEN11_3DSTATE_SAMPLE_MASK_length 2 +#define GEN10_3DSTATE_SAMPLE_MASK_length 2 +#define GEN9_3DSTATE_SAMPLE_MASK_length 2 +#define GEN8_3DSTATE_SAMPLE_MASK_length 2 +#define GEN75_3DSTATE_SAMPLE_MASK_length 2 +#define GEN7_3DSTATE_SAMPLE_MASK_length 2 +#define GEN6_3DSTATE_SAMPLE_MASK_length 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_MASK_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_MASK::3D Command Opcode */ + + +#define GEN11_3DSTATE_SAMPLE_MASK_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_SAMPLE_MASK_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_SAMPLE_MASK_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_SAMPLE_MASK_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_SAMPLE_MASK_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_SAMPLE_MASK_3DCommandOpcode_bits 3 +#define GEN6_3DSTATE_SAMPLE_MASK_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_MASK_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_MASK_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_SAMPLE_MASK_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_SAMPLE_MASK_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_SAMPLE_MASK_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_SAMPLE_MASK_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_SAMPLE_MASK_3DCommandOpcode_start 24 +#define GEN6_3DSTATE_SAMPLE_MASK_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_MASK_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_MASK::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_SAMPLE_MASK_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_SAMPLE_MASK_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_SAMPLE_MASK_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_SAMPLE_MASK_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_SAMPLE_MASK_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_SAMPLE_MASK_3DCommandSubOpcode_bits 8 +#define GEN6_3DSTATE_SAMPLE_MASK_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_MASK_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_MASK_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_SAMPLE_MASK_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_SAMPLE_MASK_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_SAMPLE_MASK_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_SAMPLE_MASK_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_SAMPLE_MASK_3DCommandSubOpcode_start 16 +#define GEN6_3DSTATE_SAMPLE_MASK_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_MASK_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_MASK::Command SubType */ + + +#define GEN11_3DSTATE_SAMPLE_MASK_CommandSubType_bits 2 +#define GEN10_3DSTATE_SAMPLE_MASK_CommandSubType_bits 2 +#define GEN9_3DSTATE_SAMPLE_MASK_CommandSubType_bits 2 +#define GEN8_3DSTATE_SAMPLE_MASK_CommandSubType_bits 2 +#define GEN75_3DSTATE_SAMPLE_MASK_CommandSubType_bits 2 +#define GEN7_3DSTATE_SAMPLE_MASK_CommandSubType_bits 2 +#define GEN6_3DSTATE_SAMPLE_MASK_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_MASK_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_MASK_CommandSubType_start 27 +#define GEN10_3DSTATE_SAMPLE_MASK_CommandSubType_start 27 +#define GEN9_3DSTATE_SAMPLE_MASK_CommandSubType_start 27 +#define GEN8_3DSTATE_SAMPLE_MASK_CommandSubType_start 27 +#define GEN75_3DSTATE_SAMPLE_MASK_CommandSubType_start 27 +#define GEN7_3DSTATE_SAMPLE_MASK_CommandSubType_start 27 +#define GEN6_3DSTATE_SAMPLE_MASK_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_MASK_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_MASK::Command Type */ + + +#define GEN11_3DSTATE_SAMPLE_MASK_CommandType_bits 3 +#define GEN10_3DSTATE_SAMPLE_MASK_CommandType_bits 3 +#define GEN9_3DSTATE_SAMPLE_MASK_CommandType_bits 3 +#define GEN8_3DSTATE_SAMPLE_MASK_CommandType_bits 3 +#define GEN75_3DSTATE_SAMPLE_MASK_CommandType_bits 3 +#define GEN7_3DSTATE_SAMPLE_MASK_CommandType_bits 3 +#define GEN6_3DSTATE_SAMPLE_MASK_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_MASK_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_MASK_CommandType_start 29 +#define GEN10_3DSTATE_SAMPLE_MASK_CommandType_start 29 +#define GEN9_3DSTATE_SAMPLE_MASK_CommandType_start 29 +#define GEN8_3DSTATE_SAMPLE_MASK_CommandType_start 29 +#define GEN75_3DSTATE_SAMPLE_MASK_CommandType_start 29 +#define GEN7_3DSTATE_SAMPLE_MASK_CommandType_start 29 +#define GEN6_3DSTATE_SAMPLE_MASK_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_MASK_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_MASK::DWord Length */ + + +#define GEN11_3DSTATE_SAMPLE_MASK_DWordLength_bits 8 +#define GEN10_3DSTATE_SAMPLE_MASK_DWordLength_bits 8 +#define GEN9_3DSTATE_SAMPLE_MASK_DWordLength_bits 8 +#define GEN8_3DSTATE_SAMPLE_MASK_DWordLength_bits 8 +#define GEN75_3DSTATE_SAMPLE_MASK_DWordLength_bits 8 +#define GEN7_3DSTATE_SAMPLE_MASK_DWordLength_bits 8 +#define GEN6_3DSTATE_SAMPLE_MASK_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_MASK_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_MASK_DWordLength_start 0 +#define GEN10_3DSTATE_SAMPLE_MASK_DWordLength_start 0 +#define GEN9_3DSTATE_SAMPLE_MASK_DWordLength_start 0 +#define GEN8_3DSTATE_SAMPLE_MASK_DWordLength_start 0 +#define GEN75_3DSTATE_SAMPLE_MASK_DWordLength_start 0 +#define GEN7_3DSTATE_SAMPLE_MASK_DWordLength_start 0 +#define GEN6_3DSTATE_SAMPLE_MASK_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_MASK_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_MASK::Sample Mask */ + + +#define GEN11_3DSTATE_SAMPLE_MASK_SampleMask_bits 16 +#define GEN10_3DSTATE_SAMPLE_MASK_SampleMask_bits 16 +#define GEN9_3DSTATE_SAMPLE_MASK_SampleMask_bits 16 +#define GEN8_3DSTATE_SAMPLE_MASK_SampleMask_bits 16 +#define GEN75_3DSTATE_SAMPLE_MASK_SampleMask_bits 8 +#define GEN7_3DSTATE_SAMPLE_MASK_SampleMask_bits 8 +#define GEN6_3DSTATE_SAMPLE_MASK_SampleMask_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_MASK_SampleMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_MASK_SampleMask_start 32 +#define GEN10_3DSTATE_SAMPLE_MASK_SampleMask_start 32 +#define GEN9_3DSTATE_SAMPLE_MASK_SampleMask_start 32 +#define GEN8_3DSTATE_SAMPLE_MASK_SampleMask_start 32 +#define GEN75_3DSTATE_SAMPLE_MASK_SampleMask_start 32 +#define GEN7_3DSTATE_SAMPLE_MASK_SampleMask_start 32 +#define GEN6_3DSTATE_SAMPLE_MASK_SampleMask_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_MASK_SampleMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_length 9 +#define GEN10_3DSTATE_SAMPLE_PATTERN_length 9 +#define GEN9_3DSTATE_SAMPLE_PATTERN_length 9 +#define GEN8_3DSTATE_SAMPLE_PATTERN_length 9 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 9; + case 10: return 9; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::16x Sample0 X Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample0XOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample0XOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample0XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample0XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample0XOffset_start 36 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample0XOffset_start 36 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample0XOffset_start 36 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample0XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 36; + case 10: return 36; + case 9: return 36; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::16x Sample0 Y Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample0YOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample0YOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample0YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample0YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample0YOffset_start 32 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample0YOffset_start 32 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample0YOffset_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample0YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::16x Sample1 X Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample1XOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample1XOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample1XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample1XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample1XOffset_start 44 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample1XOffset_start 44 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample1XOffset_start 44 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample1XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 44; + case 10: return 44; + case 9: return 44; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::16x Sample1 Y Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample1YOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample1YOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample1YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample1YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample1YOffset_start 40 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample1YOffset_start 40 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample1YOffset_start 40 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample1YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 40; + case 10: return 40; + case 9: return 40; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::16x Sample10 X Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample10XOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample10XOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample10XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample10XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample10XOffset_start 116 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample10XOffset_start 116 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample10XOffset_start 116 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample10XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 116; + case 10: return 116; + case 9: return 116; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::16x Sample10 Y Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample10YOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample10YOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample10YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample10YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample10YOffset_start 112 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample10YOffset_start 112 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample10YOffset_start 112 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample10YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 112; + case 10: return 112; + case 9: return 112; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::16x Sample11 X Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample11XOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample11XOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample11XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample11XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample11XOffset_start 124 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample11XOffset_start 124 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample11XOffset_start 124 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample11XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 124; + case 10: return 124; + case 9: return 124; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::16x Sample11 Y Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample11YOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample11YOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample11YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample11YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample11YOffset_start 120 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample11YOffset_start 120 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample11YOffset_start 120 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample11YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 120; + case 10: return 120; + case 9: return 120; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::16x Sample12 X Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample12XOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample12XOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample12XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample12XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample12XOffset_start 132 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample12XOffset_start 132 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample12XOffset_start 132 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample12XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 132; + case 10: return 132; + case 9: return 132; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::16x Sample12 Y Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample12YOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample12YOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample12YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample12YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample12YOffset_start 128 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample12YOffset_start 128 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample12YOffset_start 128 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample12YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 128; + case 10: return 128; + case 9: return 128; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::16x Sample13 X Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample13XOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample13XOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample13XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample13XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample13XOffset_start 140 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample13XOffset_start 140 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample13XOffset_start 140 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample13XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 140; + case 10: return 140; + case 9: return 140; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::16x Sample13 Y Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample13YOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample13YOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample13YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample13YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample13YOffset_start 136 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample13YOffset_start 136 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample13YOffset_start 136 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample13YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 136; + case 10: return 136; + case 9: return 136; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::16x Sample14 X Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample14XOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample14XOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample14XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample14XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample14XOffset_start 148 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample14XOffset_start 148 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample14XOffset_start 148 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample14XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 148; + case 10: return 148; + case 9: return 148; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::16x Sample14 Y Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample14YOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample14YOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample14YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample14YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample14YOffset_start 144 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample14YOffset_start 144 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample14YOffset_start 144 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample14YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 144; + case 10: return 144; + case 9: return 144; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::16x Sample15 X Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample15XOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample15XOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample15XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample15XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample15XOffset_start 156 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample15XOffset_start 156 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample15XOffset_start 156 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample15XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 156; + case 10: return 156; + case 9: return 156; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::16x Sample15 Y Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample15YOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample15YOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample15YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample15YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample15YOffset_start 152 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample15YOffset_start 152 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample15YOffset_start 152 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample15YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 152; + case 10: return 152; + case 9: return 152; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::16x Sample2 X Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample2XOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample2XOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample2XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample2XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample2XOffset_start 52 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample2XOffset_start 52 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample2XOffset_start 52 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample2XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 52; + case 10: return 52; + case 9: return 52; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::16x Sample2 Y Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample2YOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample2YOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample2YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample2YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample2YOffset_start 48 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample2YOffset_start 48 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample2YOffset_start 48 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample2YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::16x Sample3 X Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample3XOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample3XOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample3XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample3XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample3XOffset_start 60 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample3XOffset_start 60 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample3XOffset_start 60 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample3XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 60; + case 10: return 60; + case 9: return 60; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::16x Sample3 Y Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample3YOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample3YOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample3YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample3YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample3YOffset_start 56 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample3YOffset_start 56 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample3YOffset_start 56 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample3YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 56; + case 10: return 56; + case 9: return 56; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::16x Sample4 X Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample4XOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample4XOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample4XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample4XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample4XOffset_start 68 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample4XOffset_start 68 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample4XOffset_start 68 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample4XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 68; + case 10: return 68; + case 9: return 68; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::16x Sample4 Y Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample4YOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample4YOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample4YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample4YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample4YOffset_start 64 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample4YOffset_start 64 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample4YOffset_start 64 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample4YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::16x Sample5 X Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample5XOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample5XOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample5XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample5XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample5XOffset_start 76 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample5XOffset_start 76 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample5XOffset_start 76 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample5XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 76; + case 10: return 76; + case 9: return 76; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::16x Sample5 Y Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample5YOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample5YOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample5YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample5YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample5YOffset_start 72 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample5YOffset_start 72 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample5YOffset_start 72 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample5YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 72; + case 10: return 72; + case 9: return 72; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::16x Sample6 X Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample6XOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample6XOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample6XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample6XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample6XOffset_start 84 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample6XOffset_start 84 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample6XOffset_start 84 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample6XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 84; + case 10: return 84; + case 9: return 84; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::16x Sample6 Y Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample6YOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample6YOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample6YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample6YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample6YOffset_start 80 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample6YOffset_start 80 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample6YOffset_start 80 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample6YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 80; + case 10: return 80; + case 9: return 80; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::16x Sample7 X Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample7XOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample7XOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample7XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample7XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample7XOffset_start 92 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample7XOffset_start 92 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample7XOffset_start 92 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample7XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 92; + case 10: return 92; + case 9: return 92; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::16x Sample7 Y Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample7YOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample7YOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample7YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample7YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample7YOffset_start 88 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample7YOffset_start 88 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample7YOffset_start 88 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample7YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 88; + case 10: return 88; + case 9: return 88; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::16x Sample8 X Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample8XOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample8XOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample8XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample8XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample8XOffset_start 100 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample8XOffset_start 100 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample8XOffset_start 100 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample8XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 100; + case 10: return 100; + case 9: return 100; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::16x Sample8 Y Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample8YOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample8YOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample8YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample8YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample8YOffset_start 96 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample8YOffset_start 96 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample8YOffset_start 96 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample8YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 96; + case 10: return 96; + case 9: return 96; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::16x Sample9 X Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample9XOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample9XOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample9XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample9XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample9XOffset_start 108 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample9XOffset_start 108 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample9XOffset_start 108 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample9XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 108; + case 10: return 108; + case 9: return 108; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::16x Sample9 Y Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample9YOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample9YOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample9YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample9YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_16xSample9YOffset_start 104 +#define GEN10_3DSTATE_SAMPLE_PATTERN_16xSample9YOffset_start 104 +#define GEN9_3DSTATE_SAMPLE_PATTERN_16xSample9YOffset_start 104 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_16xSample9YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 104; + case 10: return 104; + case 9: return 104; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::1x Sample0 X Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_1xSample0XOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_1xSample0XOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_1xSample0XOffset_bits 4 +#define GEN8_3DSTATE_SAMPLE_PATTERN_1xSample0XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_1xSample0XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_1xSample0XOffset_start 276 +#define GEN10_3DSTATE_SAMPLE_PATTERN_1xSample0XOffset_start 276 +#define GEN9_3DSTATE_SAMPLE_PATTERN_1xSample0XOffset_start 276 +#define GEN8_3DSTATE_SAMPLE_PATTERN_1xSample0XOffset_start 276 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_1xSample0XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 276; + case 10: return 276; + case 9: return 276; + case 8: return 276; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::1x Sample0 Y Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_1xSample0YOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_1xSample0YOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_1xSample0YOffset_bits 4 +#define GEN8_3DSTATE_SAMPLE_PATTERN_1xSample0YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_1xSample0YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_1xSample0YOffset_start 272 +#define GEN10_3DSTATE_SAMPLE_PATTERN_1xSample0YOffset_start 272 +#define GEN9_3DSTATE_SAMPLE_PATTERN_1xSample0YOffset_start 272 +#define GEN8_3DSTATE_SAMPLE_PATTERN_1xSample0YOffset_start 272 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_1xSample0YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 272; + case 10: return 272; + case 9: return 272; + case 8: return 272; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::2x Sample0 X Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_2xSample0XOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_2xSample0XOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_2xSample0XOffset_bits 4 +#define GEN8_3DSTATE_SAMPLE_PATTERN_2xSample0XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_2xSample0XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_2xSample0XOffset_start 260 +#define GEN10_3DSTATE_SAMPLE_PATTERN_2xSample0XOffset_start 260 +#define GEN9_3DSTATE_SAMPLE_PATTERN_2xSample0XOffset_start 260 +#define GEN8_3DSTATE_SAMPLE_PATTERN_2xSample0XOffset_start 260 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_2xSample0XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 260; + case 10: return 260; + case 9: return 260; + case 8: return 260; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::2x Sample0 Y Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_2xSample0YOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_2xSample0YOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_2xSample0YOffset_bits 4 +#define GEN8_3DSTATE_SAMPLE_PATTERN_2xSample0YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_2xSample0YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_2xSample0YOffset_start 256 +#define GEN10_3DSTATE_SAMPLE_PATTERN_2xSample0YOffset_start 256 +#define GEN9_3DSTATE_SAMPLE_PATTERN_2xSample0YOffset_start 256 +#define GEN8_3DSTATE_SAMPLE_PATTERN_2xSample0YOffset_start 256 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_2xSample0YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 256; + case 10: return 256; + case 9: return 256; + case 8: return 256; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::2x Sample1 X Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_2xSample1XOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_2xSample1XOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_2xSample1XOffset_bits 4 +#define GEN8_3DSTATE_SAMPLE_PATTERN_2xSample1XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_2xSample1XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_2xSample1XOffset_start 268 +#define GEN10_3DSTATE_SAMPLE_PATTERN_2xSample1XOffset_start 268 +#define GEN9_3DSTATE_SAMPLE_PATTERN_2xSample1XOffset_start 268 +#define GEN8_3DSTATE_SAMPLE_PATTERN_2xSample1XOffset_start 268 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_2xSample1XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 268; + case 10: return 268; + case 9: return 268; + case 8: return 268; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::2x Sample1 Y Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_2xSample1YOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_2xSample1YOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_2xSample1YOffset_bits 4 +#define GEN8_3DSTATE_SAMPLE_PATTERN_2xSample1YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_2xSample1YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_2xSample1YOffset_start 264 +#define GEN10_3DSTATE_SAMPLE_PATTERN_2xSample1YOffset_start 264 +#define GEN9_3DSTATE_SAMPLE_PATTERN_2xSample1YOffset_start 264 +#define GEN8_3DSTATE_SAMPLE_PATTERN_2xSample1YOffset_start 264 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_2xSample1YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 264; + case 10: return 264; + case 9: return 264; + case 8: return 264; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::3D Command Opcode */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_SAMPLE_PATTERN_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_SAMPLE_PATTERN_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_SAMPLE_PATTERN_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_SAMPLE_PATTERN_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_SAMPLE_PATTERN_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_SAMPLE_PATTERN_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_SAMPLE_PATTERN_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_SAMPLE_PATTERN_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_SAMPLE_PATTERN_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_SAMPLE_PATTERN_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_SAMPLE_PATTERN_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_SAMPLE_PATTERN_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::4x Sample0 X Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_4xSample0XOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_4xSample0XOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_4xSample0XOffset_bits 4 +#define GEN8_3DSTATE_SAMPLE_PATTERN_4xSample0XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_4xSample0XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_4xSample0XOffset_start 228 +#define GEN10_3DSTATE_SAMPLE_PATTERN_4xSample0XOffset_start 228 +#define GEN9_3DSTATE_SAMPLE_PATTERN_4xSample0XOffset_start 228 +#define GEN8_3DSTATE_SAMPLE_PATTERN_4xSample0XOffset_start 228 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_4xSample0XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 228; + case 10: return 228; + case 9: return 228; + case 8: return 228; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::4x Sample0 Y Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_4xSample0YOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_4xSample0YOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_4xSample0YOffset_bits 4 +#define GEN8_3DSTATE_SAMPLE_PATTERN_4xSample0YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_4xSample0YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_4xSample0YOffset_start 224 +#define GEN10_3DSTATE_SAMPLE_PATTERN_4xSample0YOffset_start 224 +#define GEN9_3DSTATE_SAMPLE_PATTERN_4xSample0YOffset_start 224 +#define GEN8_3DSTATE_SAMPLE_PATTERN_4xSample0YOffset_start 224 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_4xSample0YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 224; + case 10: return 224; + case 9: return 224; + case 8: return 224; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::4x Sample1 X Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_4xSample1XOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_4xSample1XOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_4xSample1XOffset_bits 4 +#define GEN8_3DSTATE_SAMPLE_PATTERN_4xSample1XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_4xSample1XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_4xSample1XOffset_start 236 +#define GEN10_3DSTATE_SAMPLE_PATTERN_4xSample1XOffset_start 236 +#define GEN9_3DSTATE_SAMPLE_PATTERN_4xSample1XOffset_start 236 +#define GEN8_3DSTATE_SAMPLE_PATTERN_4xSample1XOffset_start 236 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_4xSample1XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 236; + case 10: return 236; + case 9: return 236; + case 8: return 236; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::4x Sample1 Y Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_4xSample1YOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_4xSample1YOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_4xSample1YOffset_bits 4 +#define GEN8_3DSTATE_SAMPLE_PATTERN_4xSample1YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_4xSample1YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_4xSample1YOffset_start 232 +#define GEN10_3DSTATE_SAMPLE_PATTERN_4xSample1YOffset_start 232 +#define GEN9_3DSTATE_SAMPLE_PATTERN_4xSample1YOffset_start 232 +#define GEN8_3DSTATE_SAMPLE_PATTERN_4xSample1YOffset_start 232 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_4xSample1YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 232; + case 10: return 232; + case 9: return 232; + case 8: return 232; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::4x Sample2 X Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_4xSample2XOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_4xSample2XOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_4xSample2XOffset_bits 4 +#define GEN8_3DSTATE_SAMPLE_PATTERN_4xSample2XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_4xSample2XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_4xSample2XOffset_start 244 +#define GEN10_3DSTATE_SAMPLE_PATTERN_4xSample2XOffset_start 244 +#define GEN9_3DSTATE_SAMPLE_PATTERN_4xSample2XOffset_start 244 +#define GEN8_3DSTATE_SAMPLE_PATTERN_4xSample2XOffset_start 244 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_4xSample2XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 244; + case 10: return 244; + case 9: return 244; + case 8: return 244; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::4x Sample2 Y Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_4xSample2YOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_4xSample2YOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_4xSample2YOffset_bits 4 +#define GEN8_3DSTATE_SAMPLE_PATTERN_4xSample2YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_4xSample2YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_4xSample2YOffset_start 240 +#define GEN10_3DSTATE_SAMPLE_PATTERN_4xSample2YOffset_start 240 +#define GEN9_3DSTATE_SAMPLE_PATTERN_4xSample2YOffset_start 240 +#define GEN8_3DSTATE_SAMPLE_PATTERN_4xSample2YOffset_start 240 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_4xSample2YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 240; + case 10: return 240; + case 9: return 240; + case 8: return 240; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::4x Sample3 X Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_4xSample3XOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_4xSample3XOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_4xSample3XOffset_bits 4 +#define GEN8_3DSTATE_SAMPLE_PATTERN_4xSample3XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_4xSample3XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_4xSample3XOffset_start 252 +#define GEN10_3DSTATE_SAMPLE_PATTERN_4xSample3XOffset_start 252 +#define GEN9_3DSTATE_SAMPLE_PATTERN_4xSample3XOffset_start 252 +#define GEN8_3DSTATE_SAMPLE_PATTERN_4xSample3XOffset_start 252 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_4xSample3XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 252; + case 10: return 252; + case 9: return 252; + case 8: return 252; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::4x Sample3 Y Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_4xSample3YOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_4xSample3YOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_4xSample3YOffset_bits 4 +#define GEN8_3DSTATE_SAMPLE_PATTERN_4xSample3YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_4xSample3YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_4xSample3YOffset_start 248 +#define GEN10_3DSTATE_SAMPLE_PATTERN_4xSample3YOffset_start 248 +#define GEN9_3DSTATE_SAMPLE_PATTERN_4xSample3YOffset_start 248 +#define GEN8_3DSTATE_SAMPLE_PATTERN_4xSample3YOffset_start 248 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_4xSample3YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 248; + case 10: return 248; + case 9: return 248; + case 8: return 248; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::8x Sample0 X Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_8xSample0XOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_8xSample0XOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_8xSample0XOffset_bits 4 +#define GEN8_3DSTATE_SAMPLE_PATTERN_8xSample0XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_8xSample0XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_8xSample0XOffset_start 196 +#define GEN10_3DSTATE_SAMPLE_PATTERN_8xSample0XOffset_start 196 +#define GEN9_3DSTATE_SAMPLE_PATTERN_8xSample0XOffset_start 196 +#define GEN8_3DSTATE_SAMPLE_PATTERN_8xSample0XOffset_start 196 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_8xSample0XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 196; + case 10: return 196; + case 9: return 196; + case 8: return 196; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::8x Sample0 Y Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_8xSample0YOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_8xSample0YOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_8xSample0YOffset_bits 4 +#define GEN8_3DSTATE_SAMPLE_PATTERN_8xSample0YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_8xSample0YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_8xSample0YOffset_start 192 +#define GEN10_3DSTATE_SAMPLE_PATTERN_8xSample0YOffset_start 192 +#define GEN9_3DSTATE_SAMPLE_PATTERN_8xSample0YOffset_start 192 +#define GEN8_3DSTATE_SAMPLE_PATTERN_8xSample0YOffset_start 192 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_8xSample0YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 192; + case 10: return 192; + case 9: return 192; + case 8: return 192; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::8x Sample1 X Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_8xSample1XOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_8xSample1XOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_8xSample1XOffset_bits 4 +#define GEN8_3DSTATE_SAMPLE_PATTERN_8xSample1XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_8xSample1XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_8xSample1XOffset_start 204 +#define GEN10_3DSTATE_SAMPLE_PATTERN_8xSample1XOffset_start 204 +#define GEN9_3DSTATE_SAMPLE_PATTERN_8xSample1XOffset_start 204 +#define GEN8_3DSTATE_SAMPLE_PATTERN_8xSample1XOffset_start 204 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_8xSample1XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 204; + case 10: return 204; + case 9: return 204; + case 8: return 204; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::8x Sample1 Y Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_8xSample1YOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_8xSample1YOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_8xSample1YOffset_bits 4 +#define GEN8_3DSTATE_SAMPLE_PATTERN_8xSample1YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_8xSample1YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_8xSample1YOffset_start 200 +#define GEN10_3DSTATE_SAMPLE_PATTERN_8xSample1YOffset_start 200 +#define GEN9_3DSTATE_SAMPLE_PATTERN_8xSample1YOffset_start 200 +#define GEN8_3DSTATE_SAMPLE_PATTERN_8xSample1YOffset_start 200 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_8xSample1YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 200; + case 10: return 200; + case 9: return 200; + case 8: return 200; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::8x Sample2 X Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_8xSample2XOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_8xSample2XOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_8xSample2XOffset_bits 4 +#define GEN8_3DSTATE_SAMPLE_PATTERN_8xSample2XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_8xSample2XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_8xSample2XOffset_start 212 +#define GEN10_3DSTATE_SAMPLE_PATTERN_8xSample2XOffset_start 212 +#define GEN9_3DSTATE_SAMPLE_PATTERN_8xSample2XOffset_start 212 +#define GEN8_3DSTATE_SAMPLE_PATTERN_8xSample2XOffset_start 212 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_8xSample2XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 212; + case 10: return 212; + case 9: return 212; + case 8: return 212; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::8x Sample2 Y Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_8xSample2YOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_8xSample2YOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_8xSample2YOffset_bits 4 +#define GEN8_3DSTATE_SAMPLE_PATTERN_8xSample2YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_8xSample2YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_8xSample2YOffset_start 208 +#define GEN10_3DSTATE_SAMPLE_PATTERN_8xSample2YOffset_start 208 +#define GEN9_3DSTATE_SAMPLE_PATTERN_8xSample2YOffset_start 208 +#define GEN8_3DSTATE_SAMPLE_PATTERN_8xSample2YOffset_start 208 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_8xSample2YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 208; + case 10: return 208; + case 9: return 208; + case 8: return 208; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::8x Sample3 X Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_8xSample3XOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_8xSample3XOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_8xSample3XOffset_bits 4 +#define GEN8_3DSTATE_SAMPLE_PATTERN_8xSample3XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_8xSample3XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_8xSample3XOffset_start 220 +#define GEN10_3DSTATE_SAMPLE_PATTERN_8xSample3XOffset_start 220 +#define GEN9_3DSTATE_SAMPLE_PATTERN_8xSample3XOffset_start 220 +#define GEN8_3DSTATE_SAMPLE_PATTERN_8xSample3XOffset_start 220 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_8xSample3XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 220; + case 10: return 220; + case 9: return 220; + case 8: return 220; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::8x Sample3 Y Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_8xSample3YOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_8xSample3YOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_8xSample3YOffset_bits 4 +#define GEN8_3DSTATE_SAMPLE_PATTERN_8xSample3YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_8xSample3YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_8xSample3YOffset_start 216 +#define GEN10_3DSTATE_SAMPLE_PATTERN_8xSample3YOffset_start 216 +#define GEN9_3DSTATE_SAMPLE_PATTERN_8xSample3YOffset_start 216 +#define GEN8_3DSTATE_SAMPLE_PATTERN_8xSample3YOffset_start 216 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_8xSample3YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 216; + case 10: return 216; + case 9: return 216; + case 8: return 216; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::8x Sample4 X Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_8xSample4XOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_8xSample4XOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_8xSample4XOffset_bits 4 +#define GEN8_3DSTATE_SAMPLE_PATTERN_8xSample4XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_8xSample4XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_8xSample4XOffset_start 164 +#define GEN10_3DSTATE_SAMPLE_PATTERN_8xSample4XOffset_start 164 +#define GEN9_3DSTATE_SAMPLE_PATTERN_8xSample4XOffset_start 164 +#define GEN8_3DSTATE_SAMPLE_PATTERN_8xSample4XOffset_start 164 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_8xSample4XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 164; + case 10: return 164; + case 9: return 164; + case 8: return 164; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::8x Sample4 Y Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_8xSample4YOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_8xSample4YOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_8xSample4YOffset_bits 4 +#define GEN8_3DSTATE_SAMPLE_PATTERN_8xSample4YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_8xSample4YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_8xSample4YOffset_start 160 +#define GEN10_3DSTATE_SAMPLE_PATTERN_8xSample4YOffset_start 160 +#define GEN9_3DSTATE_SAMPLE_PATTERN_8xSample4YOffset_start 160 +#define GEN8_3DSTATE_SAMPLE_PATTERN_8xSample4YOffset_start 160 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_8xSample4YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 160; + case 10: return 160; + case 9: return 160; + case 8: return 160; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::8x Sample5 X Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_8xSample5XOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_8xSample5XOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_8xSample5XOffset_bits 4 +#define GEN8_3DSTATE_SAMPLE_PATTERN_8xSample5XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_8xSample5XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_8xSample5XOffset_start 172 +#define GEN10_3DSTATE_SAMPLE_PATTERN_8xSample5XOffset_start 172 +#define GEN9_3DSTATE_SAMPLE_PATTERN_8xSample5XOffset_start 172 +#define GEN8_3DSTATE_SAMPLE_PATTERN_8xSample5XOffset_start 172 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_8xSample5XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 172; + case 10: return 172; + case 9: return 172; + case 8: return 172; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::8x Sample5 Y Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_8xSample5YOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_8xSample5YOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_8xSample5YOffset_bits 4 +#define GEN8_3DSTATE_SAMPLE_PATTERN_8xSample5YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_8xSample5YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_8xSample5YOffset_start 168 +#define GEN10_3DSTATE_SAMPLE_PATTERN_8xSample5YOffset_start 168 +#define GEN9_3DSTATE_SAMPLE_PATTERN_8xSample5YOffset_start 168 +#define GEN8_3DSTATE_SAMPLE_PATTERN_8xSample5YOffset_start 168 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_8xSample5YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 168; + case 10: return 168; + case 9: return 168; + case 8: return 168; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::8x Sample6 X Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_8xSample6XOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_8xSample6XOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_8xSample6XOffset_bits 4 +#define GEN8_3DSTATE_SAMPLE_PATTERN_8xSample6XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_8xSample6XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_8xSample6XOffset_start 180 +#define GEN10_3DSTATE_SAMPLE_PATTERN_8xSample6XOffset_start 180 +#define GEN9_3DSTATE_SAMPLE_PATTERN_8xSample6XOffset_start 180 +#define GEN8_3DSTATE_SAMPLE_PATTERN_8xSample6XOffset_start 180 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_8xSample6XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 180; + case 10: return 180; + case 9: return 180; + case 8: return 180; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::8x Sample6 Y Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_8xSample6YOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_8xSample6YOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_8xSample6YOffset_bits 4 +#define GEN8_3DSTATE_SAMPLE_PATTERN_8xSample6YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_8xSample6YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_8xSample6YOffset_start 176 +#define GEN10_3DSTATE_SAMPLE_PATTERN_8xSample6YOffset_start 176 +#define GEN9_3DSTATE_SAMPLE_PATTERN_8xSample6YOffset_start 176 +#define GEN8_3DSTATE_SAMPLE_PATTERN_8xSample6YOffset_start 176 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_8xSample6YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 176; + case 10: return 176; + case 9: return 176; + case 8: return 176; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::8x Sample7 X Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_8xSample7XOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_8xSample7XOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_8xSample7XOffset_bits 4 +#define GEN8_3DSTATE_SAMPLE_PATTERN_8xSample7XOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_8xSample7XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_8xSample7XOffset_start 188 +#define GEN10_3DSTATE_SAMPLE_PATTERN_8xSample7XOffset_start 188 +#define GEN9_3DSTATE_SAMPLE_PATTERN_8xSample7XOffset_start 188 +#define GEN8_3DSTATE_SAMPLE_PATTERN_8xSample7XOffset_start 188 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_8xSample7XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 188; + case 10: return 188; + case 9: return 188; + case 8: return 188; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::8x Sample7 Y Offset */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_8xSample7YOffset_bits 4 +#define GEN10_3DSTATE_SAMPLE_PATTERN_8xSample7YOffset_bits 4 +#define GEN9_3DSTATE_SAMPLE_PATTERN_8xSample7YOffset_bits 4 +#define GEN8_3DSTATE_SAMPLE_PATTERN_8xSample7YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_8xSample7YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_8xSample7YOffset_start 184 +#define GEN10_3DSTATE_SAMPLE_PATTERN_8xSample7YOffset_start 184 +#define GEN9_3DSTATE_SAMPLE_PATTERN_8xSample7YOffset_start 184 +#define GEN8_3DSTATE_SAMPLE_PATTERN_8xSample7YOffset_start 184 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_8xSample7YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 184; + case 10: return 184; + case 9: return 184; + case 8: return 184; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::Command SubType */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_CommandSubType_bits 2 +#define GEN10_3DSTATE_SAMPLE_PATTERN_CommandSubType_bits 2 +#define GEN9_3DSTATE_SAMPLE_PATTERN_CommandSubType_bits 2 +#define GEN8_3DSTATE_SAMPLE_PATTERN_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_CommandSubType_start 27 +#define GEN10_3DSTATE_SAMPLE_PATTERN_CommandSubType_start 27 +#define GEN9_3DSTATE_SAMPLE_PATTERN_CommandSubType_start 27 +#define GEN8_3DSTATE_SAMPLE_PATTERN_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::Command Type */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_CommandType_bits 3 +#define GEN10_3DSTATE_SAMPLE_PATTERN_CommandType_bits 3 +#define GEN9_3DSTATE_SAMPLE_PATTERN_CommandType_bits 3 +#define GEN8_3DSTATE_SAMPLE_PATTERN_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_CommandType_start 29 +#define GEN10_3DSTATE_SAMPLE_PATTERN_CommandType_start 29 +#define GEN9_3DSTATE_SAMPLE_PATTERN_CommandType_start 29 +#define GEN8_3DSTATE_SAMPLE_PATTERN_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SAMPLE_PATTERN::DWord Length */ + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_DWordLength_bits 8 +#define GEN10_3DSTATE_SAMPLE_PATTERN_DWordLength_bits 8 +#define GEN9_3DSTATE_SAMPLE_PATTERN_DWordLength_bits 8 +#define GEN8_3DSTATE_SAMPLE_PATTERN_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SAMPLE_PATTERN_DWordLength_start 0 +#define GEN10_3DSTATE_SAMPLE_PATTERN_DWordLength_start 0 +#define GEN9_3DSTATE_SAMPLE_PATTERN_DWordLength_start 0 +#define GEN8_3DSTATE_SAMPLE_PATTERN_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SAMPLE_PATTERN_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE */ + + +#define GEN11_3DSTATE_SBE_length 6 +#define GEN10_3DSTATE_SBE_length 6 +#define GEN9_3DSTATE_SBE_length 6 +#define GEN8_3DSTATE_SBE_length 4 +#define GEN75_3DSTATE_SBE_length 14 +#define GEN7_3DSTATE_SBE_length 14 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 14; + } else { + return 14; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE::3D Command Opcode */ + + +#define GEN11_3DSTATE_SBE_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_SBE_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_SBE_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_SBE_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_SBE_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_SBE_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SBE_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_SBE_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_SBE_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_SBE_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_SBE_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_SBE_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_SBE_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_SBE_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_SBE_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_SBE_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_SBE_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_SBE_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SBE_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_SBE_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_SBE_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_SBE_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_SBE_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_SBE_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE::Attribute */ + + +#define GEN75_3DSTATE_SBE_Attribute_bits 16 +#define GEN7_3DSTATE_SBE_Attribute_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_Attribute_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_SBE_Attribute_start 0 +#define GEN7_3DSTATE_SBE_Attribute_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_Attribute_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE::Attribute 0 WrapShortest Enables */ + + +#define GEN75_3DSTATE_SBE_Attribute0WrapShortestEnables_bits 4 +#define GEN7_3DSTATE_SBE_Attribute0WrapShortestEnables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_Attribute0WrapShortestEnables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_SBE_Attribute0WrapShortestEnables_start 384 +#define GEN7_3DSTATE_SBE_Attribute0WrapShortestEnables_start 384 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_Attribute0WrapShortestEnables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 384; + } else { + return 384; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE::Attribute 1 WrapShortest Enables */ + + +#define GEN75_3DSTATE_SBE_Attribute1WrapShortestEnables_bits 4 +#define GEN7_3DSTATE_SBE_Attribute1WrapShortestEnables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_Attribute1WrapShortestEnables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_SBE_Attribute1WrapShortestEnables_start 388 +#define GEN7_3DSTATE_SBE_Attribute1WrapShortestEnables_start 388 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_Attribute1WrapShortestEnables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 388; + } else { + return 388; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE::Attribute 10 WrapShortest Enables */ + + +#define GEN75_3DSTATE_SBE_Attribute10WrapShortestEnables_bits 4 +#define GEN7_3DSTATE_SBE_Attribute10WrapShortestEnables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_Attribute10WrapShortestEnables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_SBE_Attribute10WrapShortestEnables_start 424 +#define GEN7_3DSTATE_SBE_Attribute10WrapShortestEnables_start 424 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_Attribute10WrapShortestEnables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 424; + } else { + return 424; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE::Attribute 11 WrapShortest Enables */ + + +#define GEN75_3DSTATE_SBE_Attribute11WrapShortestEnables_bits 4 +#define GEN7_3DSTATE_SBE_Attribute11WrapShortestEnables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_Attribute11WrapShortestEnables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_SBE_Attribute11WrapShortestEnables_start 428 +#define GEN7_3DSTATE_SBE_Attribute11WrapShortestEnables_start 428 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_Attribute11WrapShortestEnables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 428; + } else { + return 428; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE::Attribute 12 WrapShortest Enables */ + + +#define GEN75_3DSTATE_SBE_Attribute12WrapShortestEnables_bits 4 +#define GEN7_3DSTATE_SBE_Attribute12WrapShortestEnables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_Attribute12WrapShortestEnables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_SBE_Attribute12WrapShortestEnables_start 432 +#define GEN7_3DSTATE_SBE_Attribute12WrapShortestEnables_start 432 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_Attribute12WrapShortestEnables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 432; + } else { + return 432; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE::Attribute 13 WrapShortest Enables */ + + +#define GEN75_3DSTATE_SBE_Attribute13WrapShortestEnables_bits 4 +#define GEN7_3DSTATE_SBE_Attribute13WrapShortestEnables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_Attribute13WrapShortestEnables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_SBE_Attribute13WrapShortestEnables_start 436 +#define GEN7_3DSTATE_SBE_Attribute13WrapShortestEnables_start 436 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_Attribute13WrapShortestEnables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 436; + } else { + return 436; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE::Attribute 14 WrapShortest Enables */ + + +#define GEN75_3DSTATE_SBE_Attribute14WrapShortestEnables_bits 4 +#define GEN7_3DSTATE_SBE_Attribute14WrapShortestEnables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_Attribute14WrapShortestEnables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_SBE_Attribute14WrapShortestEnables_start 440 +#define GEN7_3DSTATE_SBE_Attribute14WrapShortestEnables_start 440 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_Attribute14WrapShortestEnables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 440; + } else { + return 440; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE::Attribute 15 WrapShortest Enables */ + + +#define GEN75_3DSTATE_SBE_Attribute15WrapShortestEnables_bits 4 +#define GEN7_3DSTATE_SBE_Attribute15WrapShortestEnables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_Attribute15WrapShortestEnables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_SBE_Attribute15WrapShortestEnables_start 444 +#define GEN7_3DSTATE_SBE_Attribute15WrapShortestEnables_start 444 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_Attribute15WrapShortestEnables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 444; + } else { + return 444; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE::Attribute 2 WrapShortest Enables */ + + +#define GEN75_3DSTATE_SBE_Attribute2WrapShortestEnables_bits 4 +#define GEN7_3DSTATE_SBE_Attribute2WrapShortestEnables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_Attribute2WrapShortestEnables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_SBE_Attribute2WrapShortestEnables_start 392 +#define GEN7_3DSTATE_SBE_Attribute2WrapShortestEnables_start 392 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_Attribute2WrapShortestEnables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 392; + } else { + return 392; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE::Attribute 3 WrapShortest Enables */ + + +#define GEN75_3DSTATE_SBE_Attribute3WrapShortestEnables_bits 4 +#define GEN7_3DSTATE_SBE_Attribute3WrapShortestEnables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_Attribute3WrapShortestEnables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_SBE_Attribute3WrapShortestEnables_start 396 +#define GEN7_3DSTATE_SBE_Attribute3WrapShortestEnables_start 396 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_Attribute3WrapShortestEnables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 396; + } else { + return 396; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE::Attribute 4 WrapShortest Enables */ + + +#define GEN75_3DSTATE_SBE_Attribute4WrapShortestEnables_bits 4 +#define GEN7_3DSTATE_SBE_Attribute4WrapShortestEnables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_Attribute4WrapShortestEnables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_SBE_Attribute4WrapShortestEnables_start 400 +#define GEN7_3DSTATE_SBE_Attribute4WrapShortestEnables_start 400 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_Attribute4WrapShortestEnables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 400; + } else { + return 400; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE::Attribute 5 WrapShortest Enables */ + + +#define GEN75_3DSTATE_SBE_Attribute5WrapShortestEnables_bits 4 +#define GEN7_3DSTATE_SBE_Attribute5WrapShortestEnables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_Attribute5WrapShortestEnables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_SBE_Attribute5WrapShortestEnables_start 404 +#define GEN7_3DSTATE_SBE_Attribute5WrapShortestEnables_start 404 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_Attribute5WrapShortestEnables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 404; + } else { + return 404; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE::Attribute 6 WrapShortest Enables */ + + +#define GEN75_3DSTATE_SBE_Attribute6WrapShortestEnables_bits 4 +#define GEN7_3DSTATE_SBE_Attribute6WrapShortestEnables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_Attribute6WrapShortestEnables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_SBE_Attribute6WrapShortestEnables_start 408 +#define GEN7_3DSTATE_SBE_Attribute6WrapShortestEnables_start 408 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_Attribute6WrapShortestEnables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 408; + } else { + return 408; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE::Attribute 7 WrapShortest Enables */ + + +#define GEN75_3DSTATE_SBE_Attribute7WrapShortestEnables_bits 4 +#define GEN7_3DSTATE_SBE_Attribute7WrapShortestEnables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_Attribute7WrapShortestEnables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_SBE_Attribute7WrapShortestEnables_start 412 +#define GEN7_3DSTATE_SBE_Attribute7WrapShortestEnables_start 412 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_Attribute7WrapShortestEnables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 412; + } else { + return 412; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE::Attribute 8 WrapShortest Enables */ + + +#define GEN75_3DSTATE_SBE_Attribute8WrapShortestEnables_bits 4 +#define GEN7_3DSTATE_SBE_Attribute8WrapShortestEnables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_Attribute8WrapShortestEnables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_SBE_Attribute8WrapShortestEnables_start 416 +#define GEN7_3DSTATE_SBE_Attribute8WrapShortestEnables_start 416 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_Attribute8WrapShortestEnables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 416; + } else { + return 416; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE::Attribute 9 WrapShortest Enables */ + + +#define GEN75_3DSTATE_SBE_Attribute9WrapShortestEnables_bits 4 +#define GEN7_3DSTATE_SBE_Attribute9WrapShortestEnables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_Attribute9WrapShortestEnables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_SBE_Attribute9WrapShortestEnables_start 420 +#define GEN7_3DSTATE_SBE_Attribute9WrapShortestEnables_start 420 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_Attribute9WrapShortestEnables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 420; + } else { + return 420; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE::Attribute Active Component Format */ + + +#define GEN11_3DSTATE_SBE_AttributeActiveComponentFormat_bits 2 +#define GEN10_3DSTATE_SBE_AttributeActiveComponentFormat_bits 2 +#define GEN9_3DSTATE_SBE_AttributeActiveComponentFormat_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_AttributeActiveComponentFormat_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SBE_AttributeActiveComponentFormat_start 0 +#define GEN10_3DSTATE_SBE_AttributeActiveComponentFormat_start 0 +#define GEN9_3DSTATE_SBE_AttributeActiveComponentFormat_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_AttributeActiveComponentFormat_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE::Attribute Swizzle Control Mode */ + + +#define GEN75_3DSTATE_SBE_AttributeSwizzleControlMode_bits 1 +#define GEN7_3DSTATE_SBE_AttributeSwizzleControlMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_AttributeSwizzleControlMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_SBE_AttributeSwizzleControlMode_start 60 +#define GEN7_3DSTATE_SBE_AttributeSwizzleControlMode_start 60 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_AttributeSwizzleControlMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 60; + } else { + return 60; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE::Attribute Swizzle Enable */ + + +#define GEN11_3DSTATE_SBE_AttributeSwizzleEnable_bits 1 +#define GEN10_3DSTATE_SBE_AttributeSwizzleEnable_bits 1 +#define GEN9_3DSTATE_SBE_AttributeSwizzleEnable_bits 1 +#define GEN8_3DSTATE_SBE_AttributeSwizzleEnable_bits 1 +#define GEN75_3DSTATE_SBE_AttributeSwizzleEnable_bits 1 +#define GEN7_3DSTATE_SBE_AttributeSwizzleEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_AttributeSwizzleEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SBE_AttributeSwizzleEnable_start 53 +#define GEN10_3DSTATE_SBE_AttributeSwizzleEnable_start 53 +#define GEN9_3DSTATE_SBE_AttributeSwizzleEnable_start 53 +#define GEN8_3DSTATE_SBE_AttributeSwizzleEnable_start 53 +#define GEN75_3DSTATE_SBE_AttributeSwizzleEnable_start 53 +#define GEN7_3DSTATE_SBE_AttributeSwizzleEnable_start 53 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_AttributeSwizzleEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 53; + case 10: return 53; + case 9: return 53; + case 8: return 53; + case 7: + if (devinfo->is_haswell) { + return 53; + } else { + return 53; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE::Command SubType */ + + +#define GEN11_3DSTATE_SBE_CommandSubType_bits 2 +#define GEN10_3DSTATE_SBE_CommandSubType_bits 2 +#define GEN9_3DSTATE_SBE_CommandSubType_bits 2 +#define GEN8_3DSTATE_SBE_CommandSubType_bits 2 +#define GEN75_3DSTATE_SBE_CommandSubType_bits 2 +#define GEN7_3DSTATE_SBE_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SBE_CommandSubType_start 27 +#define GEN10_3DSTATE_SBE_CommandSubType_start 27 +#define GEN9_3DSTATE_SBE_CommandSubType_start 27 +#define GEN8_3DSTATE_SBE_CommandSubType_start 27 +#define GEN75_3DSTATE_SBE_CommandSubType_start 27 +#define GEN7_3DSTATE_SBE_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE::Command Type */ + + +#define GEN11_3DSTATE_SBE_CommandType_bits 3 +#define GEN10_3DSTATE_SBE_CommandType_bits 3 +#define GEN9_3DSTATE_SBE_CommandType_bits 3 +#define GEN8_3DSTATE_SBE_CommandType_bits 3 +#define GEN75_3DSTATE_SBE_CommandType_bits 3 +#define GEN7_3DSTATE_SBE_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SBE_CommandType_start 29 +#define GEN10_3DSTATE_SBE_CommandType_start 29 +#define GEN9_3DSTATE_SBE_CommandType_start 29 +#define GEN8_3DSTATE_SBE_CommandType_start 29 +#define GEN75_3DSTATE_SBE_CommandType_start 29 +#define GEN7_3DSTATE_SBE_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE::Constant Interpolation Enable */ + + +#define GEN11_3DSTATE_SBE_ConstantInterpolationEnable_bits 32 +#define GEN10_3DSTATE_SBE_ConstantInterpolationEnable_bits 32 +#define GEN9_3DSTATE_SBE_ConstantInterpolationEnable_bits 32 +#define GEN8_3DSTATE_SBE_ConstantInterpolationEnable_bits 32 +#define GEN75_3DSTATE_SBE_ConstantInterpolationEnable_bits 32 +#define GEN7_3DSTATE_SBE_ConstantInterpolationEnable_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_ConstantInterpolationEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SBE_ConstantInterpolationEnable_start 96 +#define GEN10_3DSTATE_SBE_ConstantInterpolationEnable_start 96 +#define GEN9_3DSTATE_SBE_ConstantInterpolationEnable_start 96 +#define GEN8_3DSTATE_SBE_ConstantInterpolationEnable_start 96 +#define GEN75_3DSTATE_SBE_ConstantInterpolationEnable_start 352 +#define GEN7_3DSTATE_SBE_ConstantInterpolationEnable_start 352 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_ConstantInterpolationEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 96; + case 10: return 96; + case 9: return 96; + case 8: return 96; + case 7: + if (devinfo->is_haswell) { + return 352; + } else { + return 352; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE::DWord Length */ + + +#define GEN11_3DSTATE_SBE_DWordLength_bits 8 +#define GEN10_3DSTATE_SBE_DWordLength_bits 8 +#define GEN9_3DSTATE_SBE_DWordLength_bits 8 +#define GEN8_3DSTATE_SBE_DWordLength_bits 8 +#define GEN75_3DSTATE_SBE_DWordLength_bits 8 +#define GEN7_3DSTATE_SBE_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SBE_DWordLength_start 0 +#define GEN10_3DSTATE_SBE_DWordLength_start 0 +#define GEN9_3DSTATE_SBE_DWordLength_start 0 +#define GEN8_3DSTATE_SBE_DWordLength_start 0 +#define GEN75_3DSTATE_SBE_DWordLength_start 0 +#define GEN7_3DSTATE_SBE_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE::Force Vertex URB Entry Read Length */ + + +#define GEN11_3DSTATE_SBE_ForceVertexURBEntryReadLength_bits 1 +#define GEN10_3DSTATE_SBE_ForceVertexURBEntryReadLength_bits 1 +#define GEN9_3DSTATE_SBE_ForceVertexURBEntryReadLength_bits 1 +#define GEN8_3DSTATE_SBE_ForceVertexURBEntryReadLength_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_ForceVertexURBEntryReadLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SBE_ForceVertexURBEntryReadLength_start 61 +#define GEN10_3DSTATE_SBE_ForceVertexURBEntryReadLength_start 61 +#define GEN9_3DSTATE_SBE_ForceVertexURBEntryReadLength_start 61 +#define GEN8_3DSTATE_SBE_ForceVertexURBEntryReadLength_start 61 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_ForceVertexURBEntryReadLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 61; + case 10: return 61; + case 9: return 61; + case 8: return 61; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE::Force Vertex URB Entry Read Offset */ + + +#define GEN11_3DSTATE_SBE_ForceVertexURBEntryReadOffset_bits 1 +#define GEN10_3DSTATE_SBE_ForceVertexURBEntryReadOffset_bits 1 +#define GEN9_3DSTATE_SBE_ForceVertexURBEntryReadOffset_bits 1 +#define GEN8_3DSTATE_SBE_ForceVertexURBEntryReadOffset_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_ForceVertexURBEntryReadOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SBE_ForceVertexURBEntryReadOffset_start 60 +#define GEN10_3DSTATE_SBE_ForceVertexURBEntryReadOffset_start 60 +#define GEN9_3DSTATE_SBE_ForceVertexURBEntryReadOffset_start 60 +#define GEN8_3DSTATE_SBE_ForceVertexURBEntryReadOffset_start 60 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_ForceVertexURBEntryReadOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 60; + case 10: return 60; + case 9: return 60; + case 8: return 60; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE::Number of SF Output Attributes */ + + +#define GEN11_3DSTATE_SBE_NumberofSFOutputAttributes_bits 6 +#define GEN10_3DSTATE_SBE_NumberofSFOutputAttributes_bits 6 +#define GEN9_3DSTATE_SBE_NumberofSFOutputAttributes_bits 6 +#define GEN8_3DSTATE_SBE_NumberofSFOutputAttributes_bits 6 +#define GEN75_3DSTATE_SBE_NumberofSFOutputAttributes_bits 6 +#define GEN7_3DSTATE_SBE_NumberofSFOutputAttributes_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_NumberofSFOutputAttributes_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SBE_NumberofSFOutputAttributes_start 54 +#define GEN10_3DSTATE_SBE_NumberofSFOutputAttributes_start 54 +#define GEN9_3DSTATE_SBE_NumberofSFOutputAttributes_start 54 +#define GEN8_3DSTATE_SBE_NumberofSFOutputAttributes_start 54 +#define GEN75_3DSTATE_SBE_NumberofSFOutputAttributes_start 54 +#define GEN7_3DSTATE_SBE_NumberofSFOutputAttributes_start 54 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_NumberofSFOutputAttributes_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 54; + case 10: return 54; + case 9: return 54; + case 8: return 54; + case 7: + if (devinfo->is_haswell) { + return 54; + } else { + return 54; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE::Point Sprite Texture Coordinate Enable */ + + +#define GEN11_3DSTATE_SBE_PointSpriteTextureCoordinateEnable_bits 32 +#define GEN10_3DSTATE_SBE_PointSpriteTextureCoordinateEnable_bits 32 +#define GEN9_3DSTATE_SBE_PointSpriteTextureCoordinateEnable_bits 32 +#define GEN8_3DSTATE_SBE_PointSpriteTextureCoordinateEnable_bits 32 +#define GEN75_3DSTATE_SBE_PointSpriteTextureCoordinateEnable_bits 32 +#define GEN7_3DSTATE_SBE_PointSpriteTextureCoordinateEnable_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_PointSpriteTextureCoordinateEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SBE_PointSpriteTextureCoordinateEnable_start 64 +#define GEN10_3DSTATE_SBE_PointSpriteTextureCoordinateEnable_start 64 +#define GEN9_3DSTATE_SBE_PointSpriteTextureCoordinateEnable_start 64 +#define GEN8_3DSTATE_SBE_PointSpriteTextureCoordinateEnable_start 64 +#define GEN75_3DSTATE_SBE_PointSpriteTextureCoordinateEnable_start 320 +#define GEN7_3DSTATE_SBE_PointSpriteTextureCoordinateEnable_start 320 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_PointSpriteTextureCoordinateEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 320; + } else { + return 320; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE::Point Sprite Texture Coordinate Origin */ + + +#define GEN11_3DSTATE_SBE_PointSpriteTextureCoordinateOrigin_bits 1 +#define GEN10_3DSTATE_SBE_PointSpriteTextureCoordinateOrigin_bits 1 +#define GEN9_3DSTATE_SBE_PointSpriteTextureCoordinateOrigin_bits 1 +#define GEN8_3DSTATE_SBE_PointSpriteTextureCoordinateOrigin_bits 1 +#define GEN75_3DSTATE_SBE_PointSpriteTextureCoordinateOrigin_bits 1 +#define GEN7_3DSTATE_SBE_PointSpriteTextureCoordinateOrigin_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_PointSpriteTextureCoordinateOrigin_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SBE_PointSpriteTextureCoordinateOrigin_start 52 +#define GEN10_3DSTATE_SBE_PointSpriteTextureCoordinateOrigin_start 52 +#define GEN9_3DSTATE_SBE_PointSpriteTextureCoordinateOrigin_start 52 +#define GEN8_3DSTATE_SBE_PointSpriteTextureCoordinateOrigin_start 52 +#define GEN75_3DSTATE_SBE_PointSpriteTextureCoordinateOrigin_start 52 +#define GEN7_3DSTATE_SBE_PointSpriteTextureCoordinateOrigin_start 52 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_PointSpriteTextureCoordinateOrigin_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 52; + case 10: return 52; + case 9: return 52; + case 8: return 52; + case 7: + if (devinfo->is_haswell) { + return 52; + } else { + return 52; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE::Primitive ID Override Attribute Select */ + + +#define GEN11_3DSTATE_SBE_PrimitiveIDOverrideAttributeSelect_bits 5 +#define GEN10_3DSTATE_SBE_PrimitiveIDOverrideAttributeSelect_bits 5 +#define GEN9_3DSTATE_SBE_PrimitiveIDOverrideAttributeSelect_bits 5 +#define GEN8_3DSTATE_SBE_PrimitiveIDOverrideAttributeSelect_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_PrimitiveIDOverrideAttributeSelect_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SBE_PrimitiveIDOverrideAttributeSelect_start 32 +#define GEN10_3DSTATE_SBE_PrimitiveIDOverrideAttributeSelect_start 32 +#define GEN9_3DSTATE_SBE_PrimitiveIDOverrideAttributeSelect_start 32 +#define GEN8_3DSTATE_SBE_PrimitiveIDOverrideAttributeSelect_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_PrimitiveIDOverrideAttributeSelect_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE::Primitive ID Override Component W */ + + +#define GEN11_3DSTATE_SBE_PrimitiveIDOverrideComponentW_bits 1 +#define GEN10_3DSTATE_SBE_PrimitiveIDOverrideComponentW_bits 1 +#define GEN9_3DSTATE_SBE_PrimitiveIDOverrideComponentW_bits 1 +#define GEN8_3DSTATE_SBE_PrimitiveIDOverrideComponentW_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_PrimitiveIDOverrideComponentW_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SBE_PrimitiveIDOverrideComponentW_start 51 +#define GEN10_3DSTATE_SBE_PrimitiveIDOverrideComponentW_start 51 +#define GEN9_3DSTATE_SBE_PrimitiveIDOverrideComponentW_start 51 +#define GEN8_3DSTATE_SBE_PrimitiveIDOverrideComponentW_start 51 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_PrimitiveIDOverrideComponentW_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 51; + case 10: return 51; + case 9: return 51; + case 8: return 51; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE::Primitive ID Override Component X */ + + +#define GEN11_3DSTATE_SBE_PrimitiveIDOverrideComponentX_bits 1 +#define GEN10_3DSTATE_SBE_PrimitiveIDOverrideComponentX_bits 1 +#define GEN9_3DSTATE_SBE_PrimitiveIDOverrideComponentX_bits 1 +#define GEN8_3DSTATE_SBE_PrimitiveIDOverrideComponentX_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_PrimitiveIDOverrideComponentX_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SBE_PrimitiveIDOverrideComponentX_start 48 +#define GEN10_3DSTATE_SBE_PrimitiveIDOverrideComponentX_start 48 +#define GEN9_3DSTATE_SBE_PrimitiveIDOverrideComponentX_start 48 +#define GEN8_3DSTATE_SBE_PrimitiveIDOverrideComponentX_start 48 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_PrimitiveIDOverrideComponentX_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 48; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE::Primitive ID Override Component Y */ + + +#define GEN11_3DSTATE_SBE_PrimitiveIDOverrideComponentY_bits 1 +#define GEN10_3DSTATE_SBE_PrimitiveIDOverrideComponentY_bits 1 +#define GEN9_3DSTATE_SBE_PrimitiveIDOverrideComponentY_bits 1 +#define GEN8_3DSTATE_SBE_PrimitiveIDOverrideComponentY_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_PrimitiveIDOverrideComponentY_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SBE_PrimitiveIDOverrideComponentY_start 49 +#define GEN10_3DSTATE_SBE_PrimitiveIDOverrideComponentY_start 49 +#define GEN9_3DSTATE_SBE_PrimitiveIDOverrideComponentY_start 49 +#define GEN8_3DSTATE_SBE_PrimitiveIDOverrideComponentY_start 49 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_PrimitiveIDOverrideComponentY_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 49; + case 10: return 49; + case 9: return 49; + case 8: return 49; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE::Primitive ID Override Component Z */ + + +#define GEN11_3DSTATE_SBE_PrimitiveIDOverrideComponentZ_bits 1 +#define GEN10_3DSTATE_SBE_PrimitiveIDOverrideComponentZ_bits 1 +#define GEN9_3DSTATE_SBE_PrimitiveIDOverrideComponentZ_bits 1 +#define GEN8_3DSTATE_SBE_PrimitiveIDOverrideComponentZ_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_PrimitiveIDOverrideComponentZ_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SBE_PrimitiveIDOverrideComponentZ_start 50 +#define GEN10_3DSTATE_SBE_PrimitiveIDOverrideComponentZ_start 50 +#define GEN9_3DSTATE_SBE_PrimitiveIDOverrideComponentZ_start 50 +#define GEN8_3DSTATE_SBE_PrimitiveIDOverrideComponentZ_start 50 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_PrimitiveIDOverrideComponentZ_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 50; + case 10: return 50; + case 9: return 50; + case 8: return 50; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE::Vertex URB Entry Read Length */ + + +#define GEN11_3DSTATE_SBE_VertexURBEntryReadLength_bits 5 +#define GEN10_3DSTATE_SBE_VertexURBEntryReadLength_bits 5 +#define GEN9_3DSTATE_SBE_VertexURBEntryReadLength_bits 5 +#define GEN8_3DSTATE_SBE_VertexURBEntryReadLength_bits 5 +#define GEN75_3DSTATE_SBE_VertexURBEntryReadLength_bits 5 +#define GEN7_3DSTATE_SBE_VertexURBEntryReadLength_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_VertexURBEntryReadLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 5; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SBE_VertexURBEntryReadLength_start 43 +#define GEN10_3DSTATE_SBE_VertexURBEntryReadLength_start 43 +#define GEN9_3DSTATE_SBE_VertexURBEntryReadLength_start 43 +#define GEN8_3DSTATE_SBE_VertexURBEntryReadLength_start 43 +#define GEN75_3DSTATE_SBE_VertexURBEntryReadLength_start 43 +#define GEN7_3DSTATE_SBE_VertexURBEntryReadLength_start 43 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_VertexURBEntryReadLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 43; + case 10: return 43; + case 9: return 43; + case 8: return 43; + case 7: + if (devinfo->is_haswell) { + return 43; + } else { + return 43; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE::Vertex URB Entry Read Offset */ + + +#define GEN11_3DSTATE_SBE_VertexURBEntryReadOffset_bits 6 +#define GEN10_3DSTATE_SBE_VertexURBEntryReadOffset_bits 6 +#define GEN9_3DSTATE_SBE_VertexURBEntryReadOffset_bits 6 +#define GEN8_3DSTATE_SBE_VertexURBEntryReadOffset_bits 6 +#define GEN75_3DSTATE_SBE_VertexURBEntryReadOffset_bits 6 +#define GEN7_3DSTATE_SBE_VertexURBEntryReadOffset_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_VertexURBEntryReadOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SBE_VertexURBEntryReadOffset_start 37 +#define GEN10_3DSTATE_SBE_VertexURBEntryReadOffset_start 37 +#define GEN9_3DSTATE_SBE_VertexURBEntryReadOffset_start 37 +#define GEN8_3DSTATE_SBE_VertexURBEntryReadOffset_start 37 +#define GEN75_3DSTATE_SBE_VertexURBEntryReadOffset_start 36 +#define GEN7_3DSTATE_SBE_VertexURBEntryReadOffset_start 36 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_VertexURBEntryReadOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 37; + case 10: return 37; + case 9: return 37; + case 8: return 37; + case 7: + if (devinfo->is_haswell) { + return 36; + } else { + return 36; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE_SWIZ */ + + +#define GEN11_3DSTATE_SBE_SWIZ_length 11 +#define GEN10_3DSTATE_SBE_SWIZ_length 11 +#define GEN9_3DSTATE_SBE_SWIZ_length 11 +#define GEN8_3DSTATE_SBE_SWIZ_length 11 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_SWIZ_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE_SWIZ::3D Command Opcode */ + + +#define GEN11_3DSTATE_SBE_SWIZ_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_SBE_SWIZ_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_SBE_SWIZ_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_SBE_SWIZ_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_SWIZ_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SBE_SWIZ_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_SBE_SWIZ_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_SBE_SWIZ_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_SBE_SWIZ_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_SWIZ_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE_SWIZ::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_SBE_SWIZ_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_SBE_SWIZ_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_SBE_SWIZ_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_SBE_SWIZ_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_SWIZ_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SBE_SWIZ_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_SBE_SWIZ_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_SBE_SWIZ_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_SBE_SWIZ_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_SWIZ_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE_SWIZ::Attribute */ + + +#define GEN11_3DSTATE_SBE_SWIZ_Attribute_bits 16 +#define GEN10_3DSTATE_SBE_SWIZ_Attribute_bits 16 +#define GEN9_3DSTATE_SBE_SWIZ_Attribute_bits 16 +#define GEN8_3DSTATE_SBE_SWIZ_Attribute_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_SWIZ_Attribute_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SBE_SWIZ_Attribute_start 0 +#define GEN10_3DSTATE_SBE_SWIZ_Attribute_start 0 +#define GEN9_3DSTATE_SBE_SWIZ_Attribute_start 0 +#define GEN8_3DSTATE_SBE_SWIZ_Attribute_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_SWIZ_Attribute_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE_SWIZ::Attribute Wrap Shortest Enables */ + + +#define GEN11_3DSTATE_SBE_SWIZ_AttributeWrapShortestEnables_bits 4 +#define GEN10_3DSTATE_SBE_SWIZ_AttributeWrapShortestEnables_bits 4 +#define GEN9_3DSTATE_SBE_SWIZ_AttributeWrapShortestEnables_bits 4 +#define GEN8_3DSTATE_SBE_SWIZ_AttributeWrapShortestEnables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_SWIZ_AttributeWrapShortestEnables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SBE_SWIZ_AttributeWrapShortestEnables_start 0 +#define GEN10_3DSTATE_SBE_SWIZ_AttributeWrapShortestEnables_start 0 +#define GEN9_3DSTATE_SBE_SWIZ_AttributeWrapShortestEnables_start 0 +#define GEN8_3DSTATE_SBE_SWIZ_AttributeWrapShortestEnables_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_SWIZ_AttributeWrapShortestEnables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE_SWIZ::Command SubType */ + + +#define GEN11_3DSTATE_SBE_SWIZ_CommandSubType_bits 2 +#define GEN10_3DSTATE_SBE_SWIZ_CommandSubType_bits 2 +#define GEN9_3DSTATE_SBE_SWIZ_CommandSubType_bits 2 +#define GEN8_3DSTATE_SBE_SWIZ_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_SWIZ_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SBE_SWIZ_CommandSubType_start 27 +#define GEN10_3DSTATE_SBE_SWIZ_CommandSubType_start 27 +#define GEN9_3DSTATE_SBE_SWIZ_CommandSubType_start 27 +#define GEN8_3DSTATE_SBE_SWIZ_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_SWIZ_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE_SWIZ::Command Type */ + + +#define GEN11_3DSTATE_SBE_SWIZ_CommandType_bits 3 +#define GEN10_3DSTATE_SBE_SWIZ_CommandType_bits 3 +#define GEN9_3DSTATE_SBE_SWIZ_CommandType_bits 3 +#define GEN8_3DSTATE_SBE_SWIZ_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_SWIZ_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SBE_SWIZ_CommandType_start 29 +#define GEN10_3DSTATE_SBE_SWIZ_CommandType_start 29 +#define GEN9_3DSTATE_SBE_SWIZ_CommandType_start 29 +#define GEN8_3DSTATE_SBE_SWIZ_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_SWIZ_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SBE_SWIZ::DWord Length */ + + +#define GEN11_3DSTATE_SBE_SWIZ_DWordLength_bits 8 +#define GEN10_3DSTATE_SBE_SWIZ_DWordLength_bits 8 +#define GEN9_3DSTATE_SBE_SWIZ_DWordLength_bits 8 +#define GEN8_3DSTATE_SBE_SWIZ_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_SWIZ_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SBE_SWIZ_DWordLength_start 0 +#define GEN10_3DSTATE_SBE_SWIZ_DWordLength_start 0 +#define GEN9_3DSTATE_SBE_SWIZ_DWordLength_start 0 +#define GEN8_3DSTATE_SBE_SWIZ_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SBE_SWIZ_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SCISSOR_STATE_POINTERS */ + + +#define GEN11_3DSTATE_SCISSOR_STATE_POINTERS_length 2 +#define GEN10_3DSTATE_SCISSOR_STATE_POINTERS_length 2 +#define GEN9_3DSTATE_SCISSOR_STATE_POINTERS_length 2 +#define GEN8_3DSTATE_SCISSOR_STATE_POINTERS_length 2 +#define GEN75_3DSTATE_SCISSOR_STATE_POINTERS_length 2 +#define GEN7_3DSTATE_SCISSOR_STATE_POINTERS_length 2 +#define GEN6_3DSTATE_SCISSOR_STATE_POINTERS_length 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SCISSOR_STATE_POINTERS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SCISSOR_STATE_POINTERS::3D Command Opcode */ + + +#define GEN11_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandOpcode_bits 3 +#define GEN6_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandOpcode_start 24 +#define GEN6_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SCISSOR_STATE_POINTERS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandSubOpcode_bits 8 +#define GEN6_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandSubOpcode_start 16 +#define GEN6_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SCISSOR_STATE_POINTERS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SCISSOR_STATE_POINTERS::Command SubType */ + + +#define GEN11_3DSTATE_SCISSOR_STATE_POINTERS_CommandSubType_bits 2 +#define GEN10_3DSTATE_SCISSOR_STATE_POINTERS_CommandSubType_bits 2 +#define GEN9_3DSTATE_SCISSOR_STATE_POINTERS_CommandSubType_bits 2 +#define GEN8_3DSTATE_SCISSOR_STATE_POINTERS_CommandSubType_bits 2 +#define GEN75_3DSTATE_SCISSOR_STATE_POINTERS_CommandSubType_bits 2 +#define GEN7_3DSTATE_SCISSOR_STATE_POINTERS_CommandSubType_bits 2 +#define GEN6_3DSTATE_SCISSOR_STATE_POINTERS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SCISSOR_STATE_POINTERS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SCISSOR_STATE_POINTERS_CommandSubType_start 27 +#define GEN10_3DSTATE_SCISSOR_STATE_POINTERS_CommandSubType_start 27 +#define GEN9_3DSTATE_SCISSOR_STATE_POINTERS_CommandSubType_start 27 +#define GEN8_3DSTATE_SCISSOR_STATE_POINTERS_CommandSubType_start 27 +#define GEN75_3DSTATE_SCISSOR_STATE_POINTERS_CommandSubType_start 27 +#define GEN7_3DSTATE_SCISSOR_STATE_POINTERS_CommandSubType_start 27 +#define GEN6_3DSTATE_SCISSOR_STATE_POINTERS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SCISSOR_STATE_POINTERS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SCISSOR_STATE_POINTERS::Command Type */ + + +#define GEN11_3DSTATE_SCISSOR_STATE_POINTERS_CommandType_bits 3 +#define GEN10_3DSTATE_SCISSOR_STATE_POINTERS_CommandType_bits 3 +#define GEN9_3DSTATE_SCISSOR_STATE_POINTERS_CommandType_bits 3 +#define GEN8_3DSTATE_SCISSOR_STATE_POINTERS_CommandType_bits 3 +#define GEN75_3DSTATE_SCISSOR_STATE_POINTERS_CommandType_bits 3 +#define GEN7_3DSTATE_SCISSOR_STATE_POINTERS_CommandType_bits 3 +#define GEN6_3DSTATE_SCISSOR_STATE_POINTERS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SCISSOR_STATE_POINTERS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SCISSOR_STATE_POINTERS_CommandType_start 29 +#define GEN10_3DSTATE_SCISSOR_STATE_POINTERS_CommandType_start 29 +#define GEN9_3DSTATE_SCISSOR_STATE_POINTERS_CommandType_start 29 +#define GEN8_3DSTATE_SCISSOR_STATE_POINTERS_CommandType_start 29 +#define GEN75_3DSTATE_SCISSOR_STATE_POINTERS_CommandType_start 29 +#define GEN7_3DSTATE_SCISSOR_STATE_POINTERS_CommandType_start 29 +#define GEN6_3DSTATE_SCISSOR_STATE_POINTERS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SCISSOR_STATE_POINTERS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SCISSOR_STATE_POINTERS::DWord Length */ + + +#define GEN11_3DSTATE_SCISSOR_STATE_POINTERS_DWordLength_bits 8 +#define GEN10_3DSTATE_SCISSOR_STATE_POINTERS_DWordLength_bits 8 +#define GEN9_3DSTATE_SCISSOR_STATE_POINTERS_DWordLength_bits 8 +#define GEN8_3DSTATE_SCISSOR_STATE_POINTERS_DWordLength_bits 8 +#define GEN75_3DSTATE_SCISSOR_STATE_POINTERS_DWordLength_bits 8 +#define GEN7_3DSTATE_SCISSOR_STATE_POINTERS_DWordLength_bits 8 +#define GEN6_3DSTATE_SCISSOR_STATE_POINTERS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SCISSOR_STATE_POINTERS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SCISSOR_STATE_POINTERS_DWordLength_start 0 +#define GEN10_3DSTATE_SCISSOR_STATE_POINTERS_DWordLength_start 0 +#define GEN9_3DSTATE_SCISSOR_STATE_POINTERS_DWordLength_start 0 +#define GEN8_3DSTATE_SCISSOR_STATE_POINTERS_DWordLength_start 0 +#define GEN75_3DSTATE_SCISSOR_STATE_POINTERS_DWordLength_start 0 +#define GEN7_3DSTATE_SCISSOR_STATE_POINTERS_DWordLength_start 0 +#define GEN6_3DSTATE_SCISSOR_STATE_POINTERS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SCISSOR_STATE_POINTERS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SCISSOR_STATE_POINTERS::Scissor Rect Pointer */ + + +#define GEN11_3DSTATE_SCISSOR_STATE_POINTERS_ScissorRectPointer_bits 27 +#define GEN10_3DSTATE_SCISSOR_STATE_POINTERS_ScissorRectPointer_bits 27 +#define GEN9_3DSTATE_SCISSOR_STATE_POINTERS_ScissorRectPointer_bits 27 +#define GEN8_3DSTATE_SCISSOR_STATE_POINTERS_ScissorRectPointer_bits 27 +#define GEN75_3DSTATE_SCISSOR_STATE_POINTERS_ScissorRectPointer_bits 27 +#define GEN7_3DSTATE_SCISSOR_STATE_POINTERS_ScissorRectPointer_bits 27 +#define GEN6_3DSTATE_SCISSOR_STATE_POINTERS_ScissorRectPointer_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SCISSOR_STATE_POINTERS_ScissorRectPointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SCISSOR_STATE_POINTERS_ScissorRectPointer_start 37 +#define GEN10_3DSTATE_SCISSOR_STATE_POINTERS_ScissorRectPointer_start 37 +#define GEN9_3DSTATE_SCISSOR_STATE_POINTERS_ScissorRectPointer_start 37 +#define GEN8_3DSTATE_SCISSOR_STATE_POINTERS_ScissorRectPointer_start 37 +#define GEN75_3DSTATE_SCISSOR_STATE_POINTERS_ScissorRectPointer_start 37 +#define GEN7_3DSTATE_SCISSOR_STATE_POINTERS_ScissorRectPointer_start 37 +#define GEN6_3DSTATE_SCISSOR_STATE_POINTERS_ScissorRectPointer_start 37 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SCISSOR_STATE_POINTERS_ScissorRectPointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 37; + case 10: return 37; + case 9: return 37; + case 8: return 37; + case 7: + if (devinfo->is_haswell) { + return 37; + } else { + return 37; + } + case 6: return 37; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF */ + + +#define GEN11_3DSTATE_SF_length 4 +#define GEN10_3DSTATE_SF_length 4 +#define GEN9_3DSTATE_SF_length 4 +#define GEN8_3DSTATE_SF_length 4 +#define GEN75_3DSTATE_SF_length 7 +#define GEN7_3DSTATE_SF_length 7 +#define GEN6_3DSTATE_SF_length 20 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 7; + } else { + return 7; + } + case 6: return 20; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::3D Command Opcode */ + + +#define GEN11_3DSTATE_SF_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_SF_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_SF_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_SF_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_SF_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_SF_3DCommandOpcode_bits 3 +#define GEN6_3DSTATE_SF_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SF_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_SF_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_SF_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_SF_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_SF_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_SF_3DCommandOpcode_start 24 +#define GEN6_3DSTATE_SF_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_SF_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_SF_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_SF_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_SF_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_SF_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_SF_3DCommandSubOpcode_bits 8 +#define GEN6_3DSTATE_SF_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SF_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_SF_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_SF_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_SF_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_SF_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_SF_3DCommandSubOpcode_start 16 +#define GEN6_3DSTATE_SF_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::AA Line Distance Mode */ + + +#define GEN11_3DSTATE_SF_AALineDistanceMode_bits 1 +#define GEN10_3DSTATE_SF_AALineDistanceMode_bits 1 +#define GEN9_3DSTATE_SF_AALineDistanceMode_bits 1 +#define GEN8_3DSTATE_SF_AALineDistanceMode_bits 1 +#define GEN75_3DSTATE_SF_AALineDistanceMode_bits 1 +#define GEN7_3DSTATE_SF_AALineDistanceMode_bits 1 +#define GEN6_3DSTATE_SF_AALineDistanceMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_AALineDistanceMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SF_AALineDistanceMode_start 110 +#define GEN10_3DSTATE_SF_AALineDistanceMode_start 110 +#define GEN9_3DSTATE_SF_AALineDistanceMode_start 110 +#define GEN8_3DSTATE_SF_AALineDistanceMode_start 110 +#define GEN75_3DSTATE_SF_AALineDistanceMode_start 110 +#define GEN7_3DSTATE_SF_AALineDistanceMode_start 110 +#define GEN6_3DSTATE_SF_AALineDistanceMode_start 142 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_AALineDistanceMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 110; + case 10: return 110; + case 9: return 110; + case 8: return 110; + case 7: + if (devinfo->is_haswell) { + return 110; + } else { + return 110; + } + case 6: return 142; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Anti-Aliasing Enable */ + + +#define GEN75_3DSTATE_SF_AntiAliasingEnable_bits 1 +#define GEN7_3DSTATE_SF_AntiAliasingEnable_bits 1 +#define GEN6_3DSTATE_SF_AntiAliasingEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_AntiAliasingEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_SF_AntiAliasingEnable_start 95 +#define GEN7_3DSTATE_SF_AntiAliasingEnable_start 95 +#define GEN6_3DSTATE_SF_AntiAliasingEnable_start 127 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_AntiAliasingEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 95; + } else { + return 95; + } + case 6: return 127; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Attribute */ + + +#define GEN6_3DSTATE_SF_Attribute_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_Attribute_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_SF_Attribute_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_Attribute_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Attribute 0 WrapShortest Enables */ + + +#define GEN6_3DSTATE_SF_Attribute0WrapShortestEnables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_Attribute0WrapShortestEnables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_SF_Attribute0WrapShortestEnables_start 576 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_Attribute0WrapShortestEnables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 576; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Attribute 1 WrapShortest Enables */ + + +#define GEN6_3DSTATE_SF_Attribute1WrapShortestEnables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_Attribute1WrapShortestEnables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_SF_Attribute1WrapShortestEnables_start 580 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_Attribute1WrapShortestEnables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 580; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Attribute 10 WrapShortest Enables */ + + +#define GEN6_3DSTATE_SF_Attribute10WrapShortestEnables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_Attribute10WrapShortestEnables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_SF_Attribute10WrapShortestEnables_start 616 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_Attribute10WrapShortestEnables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 616; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Attribute 11 WrapShortest Enables */ + + +#define GEN6_3DSTATE_SF_Attribute11WrapShortestEnables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_Attribute11WrapShortestEnables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_SF_Attribute11WrapShortestEnables_start 620 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_Attribute11WrapShortestEnables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 620; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Attribute 12 WrapShortest Enables */ + + +#define GEN6_3DSTATE_SF_Attribute12WrapShortestEnables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_Attribute12WrapShortestEnables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_SF_Attribute12WrapShortestEnables_start 624 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_Attribute12WrapShortestEnables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 624; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Attribute 13 WrapShortest Enables */ + + +#define GEN6_3DSTATE_SF_Attribute13WrapShortestEnables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_Attribute13WrapShortestEnables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_SF_Attribute13WrapShortestEnables_start 628 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_Attribute13WrapShortestEnables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 628; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Attribute 14 WrapShortest Enables */ + + +#define GEN6_3DSTATE_SF_Attribute14WrapShortestEnables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_Attribute14WrapShortestEnables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_SF_Attribute14WrapShortestEnables_start 632 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_Attribute14WrapShortestEnables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 632; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Attribute 15 WrapShortest Enables */ + + +#define GEN6_3DSTATE_SF_Attribute15WrapShortestEnables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_Attribute15WrapShortestEnables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_SF_Attribute15WrapShortestEnables_start 636 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_Attribute15WrapShortestEnables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 636; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Attribute 2 WrapShortest Enables */ + + +#define GEN6_3DSTATE_SF_Attribute2WrapShortestEnables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_Attribute2WrapShortestEnables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_SF_Attribute2WrapShortestEnables_start 584 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_Attribute2WrapShortestEnables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 584; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Attribute 3 WrapShortest Enables */ + + +#define GEN6_3DSTATE_SF_Attribute3WrapShortestEnables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_Attribute3WrapShortestEnables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_SF_Attribute3WrapShortestEnables_start 588 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_Attribute3WrapShortestEnables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 588; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Attribute 4 WrapShortest Enables */ + + +#define GEN6_3DSTATE_SF_Attribute4WrapShortestEnables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_Attribute4WrapShortestEnables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_SF_Attribute4WrapShortestEnables_start 592 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_Attribute4WrapShortestEnables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 592; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Attribute 5 WrapShortest Enables */ + + +#define GEN6_3DSTATE_SF_Attribute5WrapShortestEnables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_Attribute5WrapShortestEnables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_SF_Attribute5WrapShortestEnables_start 596 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_Attribute5WrapShortestEnables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 596; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Attribute 6 WrapShortest Enables */ + + +#define GEN6_3DSTATE_SF_Attribute6WrapShortestEnables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_Attribute6WrapShortestEnables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_SF_Attribute6WrapShortestEnables_start 600 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_Attribute6WrapShortestEnables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 600; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Attribute 7 WrapShortest Enables */ + + +#define GEN6_3DSTATE_SF_Attribute7WrapShortestEnables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_Attribute7WrapShortestEnables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_SF_Attribute7WrapShortestEnables_start 604 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_Attribute7WrapShortestEnables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 604; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Attribute 8 WrapShortest Enables */ + + +#define GEN6_3DSTATE_SF_Attribute8WrapShortestEnables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_Attribute8WrapShortestEnables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_SF_Attribute8WrapShortestEnables_start 608 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_Attribute8WrapShortestEnables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 608; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Attribute 9 WrapShortest Enables */ + + +#define GEN6_3DSTATE_SF_Attribute9WrapShortestEnables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_Attribute9WrapShortestEnables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_SF_Attribute9WrapShortestEnables_start 612 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_Attribute9WrapShortestEnables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 612; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Attribute Swizzle Enable */ + + +#define GEN6_3DSTATE_SF_AttributeSwizzleEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_AttributeSwizzleEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_SF_AttributeSwizzleEnable_start 53 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_AttributeSwizzleEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 53; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::BackFace Fill Mode */ + + +#define GEN75_3DSTATE_SF_BackFaceFillMode_bits 2 +#define GEN7_3DSTATE_SF_BackFaceFillMode_bits 2 +#define GEN6_3DSTATE_SF_BackFaceFillMode_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_BackFaceFillMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_SF_BackFaceFillMode_start 35 +#define GEN7_3DSTATE_SF_BackFaceFillMode_start 35 +#define GEN6_3DSTATE_SF_BackFaceFillMode_start 67 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_BackFaceFillMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 35; + } else { + return 35; + } + case 6: return 67; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::CHV Line Width */ + + +#define GEN8_3DSTATE_SF_CHVLineWidth_bits 18 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_CHVLineWidth_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 18; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_3DSTATE_SF_CHVLineWidth_start 44 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_CHVLineWidth_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 44; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Command SubType */ + + +#define GEN11_3DSTATE_SF_CommandSubType_bits 2 +#define GEN10_3DSTATE_SF_CommandSubType_bits 2 +#define GEN9_3DSTATE_SF_CommandSubType_bits 2 +#define GEN8_3DSTATE_SF_CommandSubType_bits 2 +#define GEN75_3DSTATE_SF_CommandSubType_bits 2 +#define GEN7_3DSTATE_SF_CommandSubType_bits 2 +#define GEN6_3DSTATE_SF_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SF_CommandSubType_start 27 +#define GEN10_3DSTATE_SF_CommandSubType_start 27 +#define GEN9_3DSTATE_SF_CommandSubType_start 27 +#define GEN8_3DSTATE_SF_CommandSubType_start 27 +#define GEN75_3DSTATE_SF_CommandSubType_start 27 +#define GEN7_3DSTATE_SF_CommandSubType_start 27 +#define GEN6_3DSTATE_SF_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Command Type */ + + +#define GEN11_3DSTATE_SF_CommandType_bits 3 +#define GEN10_3DSTATE_SF_CommandType_bits 3 +#define GEN9_3DSTATE_SF_CommandType_bits 3 +#define GEN8_3DSTATE_SF_CommandType_bits 3 +#define GEN75_3DSTATE_SF_CommandType_bits 3 +#define GEN7_3DSTATE_SF_CommandType_bits 3 +#define GEN6_3DSTATE_SF_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SF_CommandType_start 29 +#define GEN10_3DSTATE_SF_CommandType_start 29 +#define GEN9_3DSTATE_SF_CommandType_start 29 +#define GEN8_3DSTATE_SF_CommandType_start 29 +#define GEN75_3DSTATE_SF_CommandType_start 29 +#define GEN7_3DSTATE_SF_CommandType_start 29 +#define GEN6_3DSTATE_SF_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Constant Interpolation Enable */ + + +#define GEN6_3DSTATE_SF_ConstantInterpolationEnable_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_ConstantInterpolationEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_SF_ConstantInterpolationEnable_start 544 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_ConstantInterpolationEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 544; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Cull Mode */ + + +#define GEN75_3DSTATE_SF_CullMode_bits 2 +#define GEN7_3DSTATE_SF_CullMode_bits 2 +#define GEN6_3DSTATE_SF_CullMode_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_CullMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_SF_CullMode_start 93 +#define GEN7_3DSTATE_SF_CullMode_start 93 +#define GEN6_3DSTATE_SF_CullMode_start 125 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_CullMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 93; + } else { + return 93; + } + case 6: return 125; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::DWord Length */ + + +#define GEN11_3DSTATE_SF_DWordLength_bits 8 +#define GEN10_3DSTATE_SF_DWordLength_bits 8 +#define GEN9_3DSTATE_SF_DWordLength_bits 8 +#define GEN8_3DSTATE_SF_DWordLength_bits 8 +#define GEN75_3DSTATE_SF_DWordLength_bits 8 +#define GEN7_3DSTATE_SF_DWordLength_bits 8 +#define GEN6_3DSTATE_SF_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SF_DWordLength_start 0 +#define GEN10_3DSTATE_SF_DWordLength_start 0 +#define GEN9_3DSTATE_SF_DWordLength_start 0 +#define GEN8_3DSTATE_SF_DWordLength_start 0 +#define GEN75_3DSTATE_SF_DWordLength_start 0 +#define GEN7_3DSTATE_SF_DWordLength_start 0 +#define GEN6_3DSTATE_SF_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Depth Buffer Surface Format */ + + +#define GEN75_3DSTATE_SF_DepthBufferSurfaceFormat_bits 3 +#define GEN7_3DSTATE_SF_DepthBufferSurfaceFormat_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_DepthBufferSurfaceFormat_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_SF_DepthBufferSurfaceFormat_start 44 +#define GEN7_3DSTATE_SF_DepthBufferSurfaceFormat_start 44 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_DepthBufferSurfaceFormat_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 44; + } else { + return 44; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Front Winding */ + + +#define GEN75_3DSTATE_SF_FrontWinding_bits 1 +#define GEN7_3DSTATE_SF_FrontWinding_bits 1 +#define GEN6_3DSTATE_SF_FrontWinding_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_FrontWinding_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_SF_FrontWinding_start 32 +#define GEN7_3DSTATE_SF_FrontWinding_start 32 +#define GEN6_3DSTATE_SF_FrontWinding_start 64 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_FrontWinding_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 64; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::FrontFace Fill Mode */ + + +#define GEN75_3DSTATE_SF_FrontFaceFillMode_bits 2 +#define GEN7_3DSTATE_SF_FrontFaceFillMode_bits 2 +#define GEN6_3DSTATE_SF_FrontFaceFillMode_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_FrontFaceFillMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_SF_FrontFaceFillMode_start 37 +#define GEN7_3DSTATE_SF_FrontFaceFillMode_start 37 +#define GEN6_3DSTATE_SF_FrontFaceFillMode_start 69 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_FrontFaceFillMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 37; + } else { + return 37; + } + case 6: return 69; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Global Depth Offset Clamp */ + + +#define GEN75_3DSTATE_SF_GlobalDepthOffsetClamp_bits 32 +#define GEN7_3DSTATE_SF_GlobalDepthOffsetClamp_bits 32 +#define GEN6_3DSTATE_SF_GlobalDepthOffsetClamp_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_GlobalDepthOffsetClamp_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_SF_GlobalDepthOffsetClamp_start 192 +#define GEN7_3DSTATE_SF_GlobalDepthOffsetClamp_start 192 +#define GEN6_3DSTATE_SF_GlobalDepthOffsetClamp_start 224 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_GlobalDepthOffsetClamp_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 192; + } else { + return 192; + } + case 6: return 224; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Global Depth Offset Constant */ + + +#define GEN75_3DSTATE_SF_GlobalDepthOffsetConstant_bits 32 +#define GEN7_3DSTATE_SF_GlobalDepthOffsetConstant_bits 32 +#define GEN6_3DSTATE_SF_GlobalDepthOffsetConstant_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_GlobalDepthOffsetConstant_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_SF_GlobalDepthOffsetConstant_start 128 +#define GEN7_3DSTATE_SF_GlobalDepthOffsetConstant_start 128 +#define GEN6_3DSTATE_SF_GlobalDepthOffsetConstant_start 160 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_GlobalDepthOffsetConstant_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 128; + } else { + return 128; + } + case 6: return 160; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Global Depth Offset Enable Point */ + + +#define GEN75_3DSTATE_SF_GlobalDepthOffsetEnablePoint_bits 1 +#define GEN7_3DSTATE_SF_GlobalDepthOffsetEnablePoint_bits 1 +#define GEN6_3DSTATE_SF_GlobalDepthOffsetEnablePoint_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_GlobalDepthOffsetEnablePoint_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_SF_GlobalDepthOffsetEnablePoint_start 39 +#define GEN7_3DSTATE_SF_GlobalDepthOffsetEnablePoint_start 39 +#define GEN6_3DSTATE_SF_GlobalDepthOffsetEnablePoint_start 71 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_GlobalDepthOffsetEnablePoint_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 39; + } else { + return 39; + } + case 6: return 71; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Global Depth Offset Enable Solid */ + + +#define GEN75_3DSTATE_SF_GlobalDepthOffsetEnableSolid_bits 1 +#define GEN7_3DSTATE_SF_GlobalDepthOffsetEnableSolid_bits 1 +#define GEN6_3DSTATE_SF_GlobalDepthOffsetEnableSolid_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_GlobalDepthOffsetEnableSolid_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_SF_GlobalDepthOffsetEnableSolid_start 41 +#define GEN7_3DSTATE_SF_GlobalDepthOffsetEnableSolid_start 41 +#define GEN6_3DSTATE_SF_GlobalDepthOffsetEnableSolid_start 73 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_GlobalDepthOffsetEnableSolid_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 41; + } else { + return 41; + } + case 6: return 73; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Global Depth Offset Enable Wireframe */ + + +#define GEN75_3DSTATE_SF_GlobalDepthOffsetEnableWireframe_bits 1 +#define GEN7_3DSTATE_SF_GlobalDepthOffsetEnableWireframe_bits 1 +#define GEN6_3DSTATE_SF_GlobalDepthOffsetEnableWireframe_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_GlobalDepthOffsetEnableWireframe_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_SF_GlobalDepthOffsetEnableWireframe_start 40 +#define GEN7_3DSTATE_SF_GlobalDepthOffsetEnableWireframe_start 40 +#define GEN6_3DSTATE_SF_GlobalDepthOffsetEnableWireframe_start 72 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_GlobalDepthOffsetEnableWireframe_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 40; + } else { + return 40; + } + case 6: return 72; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Global Depth Offset Scale */ + + +#define GEN75_3DSTATE_SF_GlobalDepthOffsetScale_bits 32 +#define GEN7_3DSTATE_SF_GlobalDepthOffsetScale_bits 32 +#define GEN6_3DSTATE_SF_GlobalDepthOffsetScale_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_GlobalDepthOffsetScale_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_SF_GlobalDepthOffsetScale_start 160 +#define GEN7_3DSTATE_SF_GlobalDepthOffsetScale_start 160 +#define GEN6_3DSTATE_SF_GlobalDepthOffsetScale_start 192 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_GlobalDepthOffsetScale_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 160; + } else { + return 160; + } + case 6: return 192; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Last Pixel Enable */ + + +#define GEN11_3DSTATE_SF_LastPixelEnable_bits 1 +#define GEN10_3DSTATE_SF_LastPixelEnable_bits 1 +#define GEN9_3DSTATE_SF_LastPixelEnable_bits 1 +#define GEN8_3DSTATE_SF_LastPixelEnable_bits 1 +#define GEN75_3DSTATE_SF_LastPixelEnable_bits 1 +#define GEN7_3DSTATE_SF_LastPixelEnable_bits 1 +#define GEN6_3DSTATE_SF_LastPixelEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_LastPixelEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SF_LastPixelEnable_start 127 +#define GEN10_3DSTATE_SF_LastPixelEnable_start 127 +#define GEN9_3DSTATE_SF_LastPixelEnable_start 127 +#define GEN8_3DSTATE_SF_LastPixelEnable_start 127 +#define GEN75_3DSTATE_SF_LastPixelEnable_start 127 +#define GEN7_3DSTATE_SF_LastPixelEnable_start 127 +#define GEN6_3DSTATE_SF_LastPixelEnable_start 159 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_LastPixelEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 127; + case 10: return 127; + case 9: return 127; + case 8: return 127; + case 7: + if (devinfo->is_haswell) { + return 127; + } else { + return 127; + } + case 6: return 159; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Legacy Global Depth Bias Enable */ + + +#define GEN11_3DSTATE_SF_LegacyGlobalDepthBiasEnable_bits 1 +#define GEN10_3DSTATE_SF_LegacyGlobalDepthBiasEnable_bits 1 +#define GEN9_3DSTATE_SF_LegacyGlobalDepthBiasEnable_bits 1 +#define GEN8_3DSTATE_SF_LegacyGlobalDepthBiasEnable_bits 1 +#define GEN75_3DSTATE_SF_LegacyGlobalDepthBiasEnable_bits 1 +#define GEN7_3DSTATE_SF_LegacyGlobalDepthBiasEnable_bits 1 +#define GEN6_3DSTATE_SF_LegacyGlobalDepthBiasEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_LegacyGlobalDepthBiasEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SF_LegacyGlobalDepthBiasEnable_start 43 +#define GEN10_3DSTATE_SF_LegacyGlobalDepthBiasEnable_start 43 +#define GEN9_3DSTATE_SF_LegacyGlobalDepthBiasEnable_start 43 +#define GEN8_3DSTATE_SF_LegacyGlobalDepthBiasEnable_start 43 +#define GEN75_3DSTATE_SF_LegacyGlobalDepthBiasEnable_start 43 +#define GEN7_3DSTATE_SF_LegacyGlobalDepthBiasEnable_start 43 +#define GEN6_3DSTATE_SF_LegacyGlobalDepthBiasEnable_start 75 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_LegacyGlobalDepthBiasEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 43; + case 10: return 43; + case 9: return 43; + case 8: return 43; + case 7: + if (devinfo->is_haswell) { + return 43; + } else { + return 43; + } + case 6: return 75; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Line End Cap Antialiasing Region Width */ + + +#define GEN11_3DSTATE_SF_LineEndCapAntialiasingRegionWidth_bits 2 +#define GEN10_3DSTATE_SF_LineEndCapAntialiasingRegionWidth_bits 2 +#define GEN9_3DSTATE_SF_LineEndCapAntialiasingRegionWidth_bits 2 +#define GEN8_3DSTATE_SF_LineEndCapAntialiasingRegionWidth_bits 2 +#define GEN75_3DSTATE_SF_LineEndCapAntialiasingRegionWidth_bits 2 +#define GEN7_3DSTATE_SF_LineEndCapAntialiasingRegionWidth_bits 2 +#define GEN6_3DSTATE_SF_LineEndCapAntialiasingRegionWidth_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_LineEndCapAntialiasingRegionWidth_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SF_LineEndCapAntialiasingRegionWidth_start 80 +#define GEN10_3DSTATE_SF_LineEndCapAntialiasingRegionWidth_start 80 +#define GEN9_3DSTATE_SF_LineEndCapAntialiasingRegionWidth_start 80 +#define GEN8_3DSTATE_SF_LineEndCapAntialiasingRegionWidth_start 80 +#define GEN75_3DSTATE_SF_LineEndCapAntialiasingRegionWidth_start 80 +#define GEN7_3DSTATE_SF_LineEndCapAntialiasingRegionWidth_start 80 +#define GEN6_3DSTATE_SF_LineEndCapAntialiasingRegionWidth_start 112 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_LineEndCapAntialiasingRegionWidth_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 80; + case 10: return 80; + case 9: return 80; + case 8: return 80; + case 7: + if (devinfo->is_haswell) { + return 80; + } else { + return 80; + } + case 6: return 112; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Line Stipple Enable */ + + +#define GEN75_3DSTATE_SF_LineStippleEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_LineStippleEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_SF_LineStippleEnable_start 78 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_LineStippleEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 78; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Line Strip/List Provoking Vertex Select */ + + +#define GEN11_3DSTATE_SF_LineStripListProvokingVertexSelect_bits 2 +#define GEN10_3DSTATE_SF_LineStripListProvokingVertexSelect_bits 2 +#define GEN9_3DSTATE_SF_LineStripListProvokingVertexSelect_bits 2 +#define GEN8_3DSTATE_SF_LineStripListProvokingVertexSelect_bits 2 +#define GEN75_3DSTATE_SF_LineStripListProvokingVertexSelect_bits 2 +#define GEN7_3DSTATE_SF_LineStripListProvokingVertexSelect_bits 2 +#define GEN6_3DSTATE_SF_LineStripListProvokingVertexSelect_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_LineStripListProvokingVertexSelect_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SF_LineStripListProvokingVertexSelect_start 123 +#define GEN10_3DSTATE_SF_LineStripListProvokingVertexSelect_start 123 +#define GEN9_3DSTATE_SF_LineStripListProvokingVertexSelect_start 123 +#define GEN8_3DSTATE_SF_LineStripListProvokingVertexSelect_start 123 +#define GEN75_3DSTATE_SF_LineStripListProvokingVertexSelect_start 123 +#define GEN7_3DSTATE_SF_LineStripListProvokingVertexSelect_start 123 +#define GEN6_3DSTATE_SF_LineStripListProvokingVertexSelect_start 155 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_LineStripListProvokingVertexSelect_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 123; + case 10: return 123; + case 9: return 123; + case 8: return 123; + case 7: + if (devinfo->is_haswell) { + return 123; + } else { + return 123; + } + case 6: return 155; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Line Width */ + + +#define GEN11_3DSTATE_SF_LineWidth_bits 18 +#define GEN10_3DSTATE_SF_LineWidth_bits 18 +#define GEN9_3DSTATE_SF_LineWidth_bits 18 +#define GEN8_3DSTATE_SF_LineWidth_bits 10 +#define GEN75_3DSTATE_SF_LineWidth_bits 10 +#define GEN7_3DSTATE_SF_LineWidth_bits 10 +#define GEN6_3DSTATE_SF_LineWidth_bits 10 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_LineWidth_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 18; + case 10: return 18; + case 9: return 18; + case 8: return 10; + case 7: + if (devinfo->is_haswell) { + return 10; + } else { + return 10; + } + case 6: return 10; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SF_LineWidth_start 44 +#define GEN10_3DSTATE_SF_LineWidth_start 44 +#define GEN9_3DSTATE_SF_LineWidth_start 44 +#define GEN8_3DSTATE_SF_LineWidth_start 82 +#define GEN75_3DSTATE_SF_LineWidth_start 82 +#define GEN7_3DSTATE_SF_LineWidth_start 82 +#define GEN6_3DSTATE_SF_LineWidth_start 114 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_LineWidth_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 44; + case 10: return 44; + case 9: return 44; + case 8: return 82; + case 7: + if (devinfo->is_haswell) { + return 82; + } else { + return 82; + } + case 6: return 114; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Multisample Rasterization Mode */ + + +#define GEN75_3DSTATE_SF_MultisampleRasterizationMode_bits 2 +#define GEN7_3DSTATE_SF_MultisampleRasterizationMode_bits 2 +#define GEN6_3DSTATE_SF_MultisampleRasterizationMode_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_MultisampleRasterizationMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_SF_MultisampleRasterizationMode_start 72 +#define GEN7_3DSTATE_SF_MultisampleRasterizationMode_start 72 +#define GEN6_3DSTATE_SF_MultisampleRasterizationMode_start 104 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_MultisampleRasterizationMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 72; + } else { + return 72; + } + case 6: return 104; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Number of SF Output Attributes */ + + +#define GEN6_3DSTATE_SF_NumberofSFOutputAttributes_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_NumberofSFOutputAttributes_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 6; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_SF_NumberofSFOutputAttributes_start 54 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_NumberofSFOutputAttributes_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 54; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Point Sprite Texture Coordinate Enable */ + + +#define GEN6_3DSTATE_SF_PointSpriteTextureCoordinateEnable_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_PointSpriteTextureCoordinateEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_SF_PointSpriteTextureCoordinateEnable_start 512 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_PointSpriteTextureCoordinateEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 512; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Point Sprite Texture Coordinate Origin */ + + +#define GEN6_3DSTATE_SF_PointSpriteTextureCoordinateOrigin_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_PointSpriteTextureCoordinateOrigin_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_SF_PointSpriteTextureCoordinateOrigin_start 52 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_PointSpriteTextureCoordinateOrigin_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 52; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Point Width */ + + +#define GEN11_3DSTATE_SF_PointWidth_bits 11 +#define GEN10_3DSTATE_SF_PointWidth_bits 11 +#define GEN9_3DSTATE_SF_PointWidth_bits 11 +#define GEN8_3DSTATE_SF_PointWidth_bits 11 +#define GEN75_3DSTATE_SF_PointWidth_bits 11 +#define GEN7_3DSTATE_SF_PointWidth_bits 11 +#define GEN6_3DSTATE_SF_PointWidth_bits 11 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_PointWidth_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 11; + } else { + return 11; + } + case 6: return 11; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SF_PointWidth_start 96 +#define GEN10_3DSTATE_SF_PointWidth_start 96 +#define GEN9_3DSTATE_SF_PointWidth_start 96 +#define GEN8_3DSTATE_SF_PointWidth_start 96 +#define GEN75_3DSTATE_SF_PointWidth_start 96 +#define GEN7_3DSTATE_SF_PointWidth_start 96 +#define GEN6_3DSTATE_SF_PointWidth_start 128 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_PointWidth_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 96; + case 10: return 96; + case 9: return 96; + case 8: return 96; + case 7: + if (devinfo->is_haswell) { + return 96; + } else { + return 96; + } + case 6: return 128; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Point Width Source */ + + +#define GEN11_3DSTATE_SF_PointWidthSource_bits 1 +#define GEN10_3DSTATE_SF_PointWidthSource_bits 1 +#define GEN9_3DSTATE_SF_PointWidthSource_bits 1 +#define GEN8_3DSTATE_SF_PointWidthSource_bits 1 +#define GEN75_3DSTATE_SF_PointWidthSource_bits 1 +#define GEN7_3DSTATE_SF_PointWidthSource_bits 1 +#define GEN6_3DSTATE_SF_PointWidthSource_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_PointWidthSource_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SF_PointWidthSource_start 107 +#define GEN10_3DSTATE_SF_PointWidthSource_start 107 +#define GEN9_3DSTATE_SF_PointWidthSource_start 107 +#define GEN8_3DSTATE_SF_PointWidthSource_start 107 +#define GEN75_3DSTATE_SF_PointWidthSource_start 107 +#define GEN7_3DSTATE_SF_PointWidthSource_start 107 +#define GEN6_3DSTATE_SF_PointWidthSource_start 139 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_PointWidthSource_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 107; + case 10: return 107; + case 9: return 107; + case 8: return 107; + case 7: + if (devinfo->is_haswell) { + return 107; + } else { + return 107; + } + case 6: return 139; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::RT Independent Rasterization Enable */ + + +#define GEN75_3DSTATE_SF_RTIndependentRasterizationEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_RTIndependentRasterizationEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_SF_RTIndependentRasterizationEnable_start 74 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_RTIndependentRasterizationEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 74; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Scissor Rectangle Enable */ + + +#define GEN75_3DSTATE_SF_ScissorRectangleEnable_bits 1 +#define GEN7_3DSTATE_SF_ScissorRectangleEnable_bits 1 +#define GEN6_3DSTATE_SF_ScissorRectangleEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_ScissorRectangleEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_SF_ScissorRectangleEnable_start 75 +#define GEN7_3DSTATE_SF_ScissorRectangleEnable_start 75 +#define GEN6_3DSTATE_SF_ScissorRectangleEnable_start 107 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_ScissorRectangleEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 75; + } else { + return 75; + } + case 6: return 107; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Smooth Point Enable */ + + +#define GEN11_3DSTATE_SF_SmoothPointEnable_bits 1 +#define GEN10_3DSTATE_SF_SmoothPointEnable_bits 1 +#define GEN9_3DSTATE_SF_SmoothPointEnable_bits 1 +#define GEN8_3DSTATE_SF_SmoothPointEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_SmoothPointEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SF_SmoothPointEnable_start 109 +#define GEN10_3DSTATE_SF_SmoothPointEnable_start 109 +#define GEN9_3DSTATE_SF_SmoothPointEnable_start 109 +#define GEN8_3DSTATE_SF_SmoothPointEnable_start 109 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_SmoothPointEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 109; + case 10: return 109; + case 9: return 109; + case 8: return 109; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Statistics Enable */ + + +#define GEN11_3DSTATE_SF_StatisticsEnable_bits 1 +#define GEN10_3DSTATE_SF_StatisticsEnable_bits 1 +#define GEN9_3DSTATE_SF_StatisticsEnable_bits 1 +#define GEN8_3DSTATE_SF_StatisticsEnable_bits 1 +#define GEN75_3DSTATE_SF_StatisticsEnable_bits 1 +#define GEN7_3DSTATE_SF_StatisticsEnable_bits 1 +#define GEN6_3DSTATE_SF_StatisticsEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_StatisticsEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SF_StatisticsEnable_start 42 +#define GEN10_3DSTATE_SF_StatisticsEnable_start 42 +#define GEN9_3DSTATE_SF_StatisticsEnable_start 42 +#define GEN8_3DSTATE_SF_StatisticsEnable_start 42 +#define GEN75_3DSTATE_SF_StatisticsEnable_start 42 +#define GEN7_3DSTATE_SF_StatisticsEnable_start 42 +#define GEN6_3DSTATE_SF_StatisticsEnable_start 74 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_StatisticsEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 42; + case 10: return 42; + case 9: return 42; + case 8: return 42; + case 7: + if (devinfo->is_haswell) { + return 42; + } else { + return 42; + } + case 6: return 74; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Triangle Fan Provoking Vertex Select */ + + +#define GEN11_3DSTATE_SF_TriangleFanProvokingVertexSelect_bits 2 +#define GEN10_3DSTATE_SF_TriangleFanProvokingVertexSelect_bits 2 +#define GEN9_3DSTATE_SF_TriangleFanProvokingVertexSelect_bits 2 +#define GEN8_3DSTATE_SF_TriangleFanProvokingVertexSelect_bits 2 +#define GEN75_3DSTATE_SF_TriangleFanProvokingVertexSelect_bits 2 +#define GEN7_3DSTATE_SF_TriangleFanProvokingVertexSelect_bits 2 +#define GEN6_3DSTATE_SF_TriangleFanProvokingVertexSelect_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_TriangleFanProvokingVertexSelect_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SF_TriangleFanProvokingVertexSelect_start 121 +#define GEN10_3DSTATE_SF_TriangleFanProvokingVertexSelect_start 121 +#define GEN9_3DSTATE_SF_TriangleFanProvokingVertexSelect_start 121 +#define GEN8_3DSTATE_SF_TriangleFanProvokingVertexSelect_start 121 +#define GEN75_3DSTATE_SF_TriangleFanProvokingVertexSelect_start 121 +#define GEN7_3DSTATE_SF_TriangleFanProvokingVertexSelect_start 121 +#define GEN6_3DSTATE_SF_TriangleFanProvokingVertexSelect_start 153 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_TriangleFanProvokingVertexSelect_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 121; + case 10: return 121; + case 9: return 121; + case 8: return 121; + case 7: + if (devinfo->is_haswell) { + return 121; + } else { + return 121; + } + case 6: return 153; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Triangle Strip/List Provoking Vertex Select */ + + +#define GEN11_3DSTATE_SF_TriangleStripListProvokingVertexSelect_bits 2 +#define GEN10_3DSTATE_SF_TriangleStripListProvokingVertexSelect_bits 2 +#define GEN9_3DSTATE_SF_TriangleStripListProvokingVertexSelect_bits 2 +#define GEN8_3DSTATE_SF_TriangleStripListProvokingVertexSelect_bits 2 +#define GEN75_3DSTATE_SF_TriangleStripListProvokingVertexSelect_bits 2 +#define GEN7_3DSTATE_SF_TriangleStripListProvokingVertexSelect_bits 2 +#define GEN6_3DSTATE_SF_TriangleStripListProvokingVertexSelect_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_TriangleStripListProvokingVertexSelect_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SF_TriangleStripListProvokingVertexSelect_start 125 +#define GEN10_3DSTATE_SF_TriangleStripListProvokingVertexSelect_start 125 +#define GEN9_3DSTATE_SF_TriangleStripListProvokingVertexSelect_start 125 +#define GEN8_3DSTATE_SF_TriangleStripListProvokingVertexSelect_start 125 +#define GEN75_3DSTATE_SF_TriangleStripListProvokingVertexSelect_start 125 +#define GEN7_3DSTATE_SF_TriangleStripListProvokingVertexSelect_start 125 +#define GEN6_3DSTATE_SF_TriangleStripListProvokingVertexSelect_start 157 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_TriangleStripListProvokingVertexSelect_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 125; + case 10: return 125; + case 9: return 125; + case 8: return 125; + case 7: + if (devinfo->is_haswell) { + return 125; + } else { + return 125; + } + case 6: return 157; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Vertex Sub Pixel Precision Select */ + + +#define GEN11_3DSTATE_SF_VertexSubPixelPrecisionSelect_bits 1 +#define GEN10_3DSTATE_SF_VertexSubPixelPrecisionSelect_bits 1 +#define GEN9_3DSTATE_SF_VertexSubPixelPrecisionSelect_bits 1 +#define GEN8_3DSTATE_SF_VertexSubPixelPrecisionSelect_bits 1 +#define GEN75_3DSTATE_SF_VertexSubPixelPrecisionSelect_bits 1 +#define GEN7_3DSTATE_SF_VertexSubPixelPrecisionSelect_bits 1 +#define GEN6_3DSTATE_SF_VertexSubPixelPrecisionSelect_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_VertexSubPixelPrecisionSelect_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SF_VertexSubPixelPrecisionSelect_start 108 +#define GEN10_3DSTATE_SF_VertexSubPixelPrecisionSelect_start 108 +#define GEN9_3DSTATE_SF_VertexSubPixelPrecisionSelect_start 108 +#define GEN8_3DSTATE_SF_VertexSubPixelPrecisionSelect_start 108 +#define GEN75_3DSTATE_SF_VertexSubPixelPrecisionSelect_start 108 +#define GEN7_3DSTATE_SF_VertexSubPixelPrecisionSelect_start 108 +#define GEN6_3DSTATE_SF_VertexSubPixelPrecisionSelect_start 140 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_VertexSubPixelPrecisionSelect_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 108; + case 10: return 108; + case 9: return 108; + case 8: return 108; + case 7: + if (devinfo->is_haswell) { + return 108; + } else { + return 108; + } + case 6: return 140; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Vertex URB Entry Read Length */ + + +#define GEN6_3DSTATE_SF_VertexURBEntryReadLength_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_VertexURBEntryReadLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 5; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_SF_VertexURBEntryReadLength_start 43 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_VertexURBEntryReadLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 43; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Vertex URB Entry Read Offset */ + + +#define GEN6_3DSTATE_SF_VertexURBEntryReadOffset_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_VertexURBEntryReadOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 6; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_SF_VertexURBEntryReadOffset_start 36 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_VertexURBEntryReadOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 36; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SF::Viewport Transform Enable */ + + +#define GEN11_3DSTATE_SF_ViewportTransformEnable_bits 1 +#define GEN10_3DSTATE_SF_ViewportTransformEnable_bits 1 +#define GEN9_3DSTATE_SF_ViewportTransformEnable_bits 1 +#define GEN8_3DSTATE_SF_ViewportTransformEnable_bits 1 +#define GEN75_3DSTATE_SF_ViewportTransformEnable_bits 1 +#define GEN7_3DSTATE_SF_ViewportTransformEnable_bits 1 +#define GEN6_3DSTATE_SF_ViewportTransformEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_ViewportTransformEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SF_ViewportTransformEnable_start 33 +#define GEN10_3DSTATE_SF_ViewportTransformEnable_start 33 +#define GEN9_3DSTATE_SF_ViewportTransformEnable_start 33 +#define GEN8_3DSTATE_SF_ViewportTransformEnable_start 33 +#define GEN75_3DSTATE_SF_ViewportTransformEnable_start 33 +#define GEN7_3DSTATE_SF_ViewportTransformEnable_start 33 +#define GEN6_3DSTATE_SF_ViewportTransformEnable_start 65 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SF_ViewportTransformEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 33; + case 10: return 33; + case 9: return 33; + case 8: return 33; + case 7: + if (devinfo->is_haswell) { + return 33; + } else { + return 33; + } + case 6: return 65; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SO_BUFFER */ + + +#define GEN11_3DSTATE_SO_BUFFER_length 8 +#define GEN10_3DSTATE_SO_BUFFER_length 8 +#define GEN9_3DSTATE_SO_BUFFER_length 8 +#define GEN8_3DSTATE_SO_BUFFER_length 8 +#define GEN75_3DSTATE_SO_BUFFER_length 4 +#define GEN7_3DSTATE_SO_BUFFER_length 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_BUFFER_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SO_BUFFER::3D Command Opcode */ + + +#define GEN11_3DSTATE_SO_BUFFER_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_SO_BUFFER_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_SO_BUFFER_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_SO_BUFFER_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_SO_BUFFER_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_SO_BUFFER_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_BUFFER_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SO_BUFFER_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_SO_BUFFER_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_SO_BUFFER_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_SO_BUFFER_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_SO_BUFFER_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_SO_BUFFER_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_BUFFER_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SO_BUFFER::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_SO_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_SO_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_SO_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_SO_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_SO_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_SO_BUFFER_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_BUFFER_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SO_BUFFER_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_SO_BUFFER_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_SO_BUFFER_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_SO_BUFFER_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_SO_BUFFER_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_SO_BUFFER_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_BUFFER_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SO_BUFFER::Command SubType */ + + +#define GEN11_3DSTATE_SO_BUFFER_CommandSubType_bits 2 +#define GEN10_3DSTATE_SO_BUFFER_CommandSubType_bits 2 +#define GEN9_3DSTATE_SO_BUFFER_CommandSubType_bits 2 +#define GEN8_3DSTATE_SO_BUFFER_CommandSubType_bits 2 +#define GEN75_3DSTATE_SO_BUFFER_CommandSubType_bits 2 +#define GEN7_3DSTATE_SO_BUFFER_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_BUFFER_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SO_BUFFER_CommandSubType_start 27 +#define GEN10_3DSTATE_SO_BUFFER_CommandSubType_start 27 +#define GEN9_3DSTATE_SO_BUFFER_CommandSubType_start 27 +#define GEN8_3DSTATE_SO_BUFFER_CommandSubType_start 27 +#define GEN75_3DSTATE_SO_BUFFER_CommandSubType_start 27 +#define GEN7_3DSTATE_SO_BUFFER_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_BUFFER_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SO_BUFFER::Command Type */ + + +#define GEN11_3DSTATE_SO_BUFFER_CommandType_bits 3 +#define GEN10_3DSTATE_SO_BUFFER_CommandType_bits 3 +#define GEN9_3DSTATE_SO_BUFFER_CommandType_bits 3 +#define GEN8_3DSTATE_SO_BUFFER_CommandType_bits 3 +#define GEN75_3DSTATE_SO_BUFFER_CommandType_bits 3 +#define GEN7_3DSTATE_SO_BUFFER_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_BUFFER_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SO_BUFFER_CommandType_start 29 +#define GEN10_3DSTATE_SO_BUFFER_CommandType_start 29 +#define GEN9_3DSTATE_SO_BUFFER_CommandType_start 29 +#define GEN8_3DSTATE_SO_BUFFER_CommandType_start 29 +#define GEN75_3DSTATE_SO_BUFFER_CommandType_start 29 +#define GEN7_3DSTATE_SO_BUFFER_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_BUFFER_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SO_BUFFER::DWord Length */ + + +#define GEN11_3DSTATE_SO_BUFFER_DWordLength_bits 8 +#define GEN10_3DSTATE_SO_BUFFER_DWordLength_bits 8 +#define GEN9_3DSTATE_SO_BUFFER_DWordLength_bits 8 +#define GEN8_3DSTATE_SO_BUFFER_DWordLength_bits 8 +#define GEN75_3DSTATE_SO_BUFFER_DWordLength_bits 8 +#define GEN7_3DSTATE_SO_BUFFER_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_BUFFER_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SO_BUFFER_DWordLength_start 0 +#define GEN10_3DSTATE_SO_BUFFER_DWordLength_start 0 +#define GEN9_3DSTATE_SO_BUFFER_DWordLength_start 0 +#define GEN8_3DSTATE_SO_BUFFER_DWordLength_start 0 +#define GEN75_3DSTATE_SO_BUFFER_DWordLength_start 0 +#define GEN7_3DSTATE_SO_BUFFER_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_BUFFER_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SO_BUFFER::MOCS */ + + +#define GEN11_3DSTATE_SO_BUFFER_MOCS_bits 7 +#define GEN10_3DSTATE_SO_BUFFER_MOCS_bits 7 +#define GEN9_3DSTATE_SO_BUFFER_MOCS_bits 7 +#define GEN8_3DSTATE_SO_BUFFER_MOCS_bits 7 +#define GEN75_3DSTATE_SO_BUFFER_MOCS_bits 4 +#define GEN7_3DSTATE_SO_BUFFER_MOCS_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_BUFFER_MOCS_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SO_BUFFER_MOCS_start 54 +#define GEN10_3DSTATE_SO_BUFFER_MOCS_start 54 +#define GEN9_3DSTATE_SO_BUFFER_MOCS_start 54 +#define GEN8_3DSTATE_SO_BUFFER_MOCS_start 54 +#define GEN75_3DSTATE_SO_BUFFER_MOCS_start 57 +#define GEN7_3DSTATE_SO_BUFFER_MOCS_start 57 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_BUFFER_MOCS_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 54; + case 10: return 54; + case 9: return 54; + case 8: return 54; + case 7: + if (devinfo->is_haswell) { + return 57; + } else { + return 57; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SO_BUFFER::SO Buffer Enable */ + + +#define GEN11_3DSTATE_SO_BUFFER_SOBufferEnable_bits 1 +#define GEN10_3DSTATE_SO_BUFFER_SOBufferEnable_bits 1 +#define GEN9_3DSTATE_SO_BUFFER_SOBufferEnable_bits 1 +#define GEN8_3DSTATE_SO_BUFFER_SOBufferEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_BUFFER_SOBufferEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SO_BUFFER_SOBufferEnable_start 63 +#define GEN10_3DSTATE_SO_BUFFER_SOBufferEnable_start 63 +#define GEN9_3DSTATE_SO_BUFFER_SOBufferEnable_start 63 +#define GEN8_3DSTATE_SO_BUFFER_SOBufferEnable_start 63 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_BUFFER_SOBufferEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 63; + case 10: return 63; + case 9: return 63; + case 8: return 63; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SO_BUFFER::SO Buffer Index */ + + +#define GEN11_3DSTATE_SO_BUFFER_SOBufferIndex_bits 2 +#define GEN10_3DSTATE_SO_BUFFER_SOBufferIndex_bits 2 +#define GEN9_3DSTATE_SO_BUFFER_SOBufferIndex_bits 2 +#define GEN8_3DSTATE_SO_BUFFER_SOBufferIndex_bits 2 +#define GEN75_3DSTATE_SO_BUFFER_SOBufferIndex_bits 2 +#define GEN7_3DSTATE_SO_BUFFER_SOBufferIndex_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_BUFFER_SOBufferIndex_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SO_BUFFER_SOBufferIndex_start 61 +#define GEN10_3DSTATE_SO_BUFFER_SOBufferIndex_start 61 +#define GEN9_3DSTATE_SO_BUFFER_SOBufferIndex_start 61 +#define GEN8_3DSTATE_SO_BUFFER_SOBufferIndex_start 61 +#define GEN75_3DSTATE_SO_BUFFER_SOBufferIndex_start 61 +#define GEN7_3DSTATE_SO_BUFFER_SOBufferIndex_start 61 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_BUFFER_SOBufferIndex_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 61; + case 10: return 61; + case 9: return 61; + case 8: return 61; + case 7: + if (devinfo->is_haswell) { + return 61; + } else { + return 61; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SO_BUFFER::Stream Offset */ + + +#define GEN11_3DSTATE_SO_BUFFER_StreamOffset_bits 32 +#define GEN10_3DSTATE_SO_BUFFER_StreamOffset_bits 32 +#define GEN9_3DSTATE_SO_BUFFER_StreamOffset_bits 32 +#define GEN8_3DSTATE_SO_BUFFER_StreamOffset_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_BUFFER_StreamOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SO_BUFFER_StreamOffset_start 224 +#define GEN10_3DSTATE_SO_BUFFER_StreamOffset_start 224 +#define GEN9_3DSTATE_SO_BUFFER_StreamOffset_start 224 +#define GEN8_3DSTATE_SO_BUFFER_StreamOffset_start 224 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_BUFFER_StreamOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 224; + case 10: return 224; + case 9: return 224; + case 8: return 224; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SO_BUFFER::Stream Offset Write Enable */ + + +#define GEN11_3DSTATE_SO_BUFFER_StreamOffsetWriteEnable_bits 1 +#define GEN10_3DSTATE_SO_BUFFER_StreamOffsetWriteEnable_bits 1 +#define GEN9_3DSTATE_SO_BUFFER_StreamOffsetWriteEnable_bits 1 +#define GEN8_3DSTATE_SO_BUFFER_StreamOffsetWriteEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_BUFFER_StreamOffsetWriteEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SO_BUFFER_StreamOffsetWriteEnable_start 53 +#define GEN10_3DSTATE_SO_BUFFER_StreamOffsetWriteEnable_start 53 +#define GEN9_3DSTATE_SO_BUFFER_StreamOffsetWriteEnable_start 53 +#define GEN8_3DSTATE_SO_BUFFER_StreamOffsetWriteEnable_start 53 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_BUFFER_StreamOffsetWriteEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 53; + case 10: return 53; + case 9: return 53; + case 8: return 53; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SO_BUFFER::Stream Output Buffer Offset Address */ + + +#define GEN11_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddress_bits 46 +#define GEN10_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddress_bits 46 +#define GEN9_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddress_bits 46 +#define GEN8_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddress_bits 46 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 46; + case 10: return 46; + case 9: return 46; + case 8: return 46; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddress_start 162 +#define GEN10_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddress_start 162 +#define GEN9_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddress_start 162 +#define GEN8_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddress_start 162 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 162; + case 10: return 162; + case 9: return 162; + case 8: return 162; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SO_BUFFER::Stream Output Buffer Offset Address Enable */ + + +#define GEN11_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddressEnable_bits 1 +#define GEN10_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddressEnable_bits 1 +#define GEN9_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddressEnable_bits 1 +#define GEN8_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddressEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddressEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddressEnable_start 52 +#define GEN10_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddressEnable_start 52 +#define GEN9_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddressEnable_start 52 +#define GEN8_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddressEnable_start 52 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_BUFFER_StreamOutputBufferOffsetAddressEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 52; + case 10: return 52; + case 9: return 52; + case 8: return 52; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SO_BUFFER::Surface Base Address */ + + +#define GEN11_3DSTATE_SO_BUFFER_SurfaceBaseAddress_bits 46 +#define GEN10_3DSTATE_SO_BUFFER_SurfaceBaseAddress_bits 46 +#define GEN9_3DSTATE_SO_BUFFER_SurfaceBaseAddress_bits 46 +#define GEN8_3DSTATE_SO_BUFFER_SurfaceBaseAddress_bits 46 +#define GEN75_3DSTATE_SO_BUFFER_SurfaceBaseAddress_bits 30 +#define GEN7_3DSTATE_SO_BUFFER_SurfaceBaseAddress_bits 30 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_BUFFER_SurfaceBaseAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 46; + case 10: return 46; + case 9: return 46; + case 8: return 46; + case 7: + if (devinfo->is_haswell) { + return 30; + } else { + return 30; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SO_BUFFER_SurfaceBaseAddress_start 66 +#define GEN10_3DSTATE_SO_BUFFER_SurfaceBaseAddress_start 66 +#define GEN9_3DSTATE_SO_BUFFER_SurfaceBaseAddress_start 66 +#define GEN8_3DSTATE_SO_BUFFER_SurfaceBaseAddress_start 66 +#define GEN75_3DSTATE_SO_BUFFER_SurfaceBaseAddress_start 66 +#define GEN7_3DSTATE_SO_BUFFER_SurfaceBaseAddress_start 66 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_BUFFER_SurfaceBaseAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 66; + case 10: return 66; + case 9: return 66; + case 8: return 66; + case 7: + if (devinfo->is_haswell) { + return 66; + } else { + return 66; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SO_BUFFER::Surface End Address */ + + +#define GEN75_3DSTATE_SO_BUFFER_SurfaceEndAddress_bits 30 +#define GEN7_3DSTATE_SO_BUFFER_SurfaceEndAddress_bits 30 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_BUFFER_SurfaceEndAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 30; + } else { + return 30; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_SO_BUFFER_SurfaceEndAddress_start 98 +#define GEN7_3DSTATE_SO_BUFFER_SurfaceEndAddress_start 98 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_BUFFER_SurfaceEndAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 98; + } else { + return 98; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SO_BUFFER::Surface Pitch */ + + +#define GEN75_3DSTATE_SO_BUFFER_SurfacePitch_bits 12 +#define GEN7_3DSTATE_SO_BUFFER_SurfacePitch_bits 12 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_BUFFER_SurfacePitch_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 12; + } else { + return 12; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_SO_BUFFER_SurfacePitch_start 32 +#define GEN7_3DSTATE_SO_BUFFER_SurfacePitch_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_BUFFER_SurfacePitch_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SO_BUFFER::Surface Size */ + + +#define GEN11_3DSTATE_SO_BUFFER_SurfaceSize_bits 30 +#define GEN10_3DSTATE_SO_BUFFER_SurfaceSize_bits 30 +#define GEN9_3DSTATE_SO_BUFFER_SurfaceSize_bits 30 +#define GEN8_3DSTATE_SO_BUFFER_SurfaceSize_bits 30 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_BUFFER_SurfaceSize_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 30; + case 10: return 30; + case 9: return 30; + case 8: return 30; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SO_BUFFER_SurfaceSize_start 128 +#define GEN10_3DSTATE_SO_BUFFER_SurfaceSize_start 128 +#define GEN9_3DSTATE_SO_BUFFER_SurfaceSize_start 128 +#define GEN8_3DSTATE_SO_BUFFER_SurfaceSize_start 128 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_BUFFER_SurfaceSize_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 128; + case 10: return 128; + case 9: return 128; + case 8: return 128; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SO_DECL_LIST */ + + + + + +/* 3DSTATE_SO_DECL_LIST::3D Command Opcode */ + + +#define GEN11_3DSTATE_SO_DECL_LIST_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_SO_DECL_LIST_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_SO_DECL_LIST_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_SO_DECL_LIST_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_SO_DECL_LIST_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_SO_DECL_LIST_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_DECL_LIST_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SO_DECL_LIST_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_SO_DECL_LIST_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_SO_DECL_LIST_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_SO_DECL_LIST_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_SO_DECL_LIST_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_SO_DECL_LIST_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_DECL_LIST_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SO_DECL_LIST::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_SO_DECL_LIST_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_SO_DECL_LIST_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_SO_DECL_LIST_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_SO_DECL_LIST_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_SO_DECL_LIST_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_SO_DECL_LIST_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_DECL_LIST_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SO_DECL_LIST_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_SO_DECL_LIST_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_SO_DECL_LIST_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_SO_DECL_LIST_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_SO_DECL_LIST_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_SO_DECL_LIST_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_DECL_LIST_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SO_DECL_LIST::Command SubType */ + + +#define GEN11_3DSTATE_SO_DECL_LIST_CommandSubType_bits 2 +#define GEN10_3DSTATE_SO_DECL_LIST_CommandSubType_bits 2 +#define GEN9_3DSTATE_SO_DECL_LIST_CommandSubType_bits 2 +#define GEN8_3DSTATE_SO_DECL_LIST_CommandSubType_bits 2 +#define GEN75_3DSTATE_SO_DECL_LIST_CommandSubType_bits 2 +#define GEN7_3DSTATE_SO_DECL_LIST_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_DECL_LIST_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SO_DECL_LIST_CommandSubType_start 27 +#define GEN10_3DSTATE_SO_DECL_LIST_CommandSubType_start 27 +#define GEN9_3DSTATE_SO_DECL_LIST_CommandSubType_start 27 +#define GEN8_3DSTATE_SO_DECL_LIST_CommandSubType_start 27 +#define GEN75_3DSTATE_SO_DECL_LIST_CommandSubType_start 27 +#define GEN7_3DSTATE_SO_DECL_LIST_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_DECL_LIST_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SO_DECL_LIST::Command Type */ + + +#define GEN11_3DSTATE_SO_DECL_LIST_CommandType_bits 3 +#define GEN10_3DSTATE_SO_DECL_LIST_CommandType_bits 3 +#define GEN9_3DSTATE_SO_DECL_LIST_CommandType_bits 3 +#define GEN8_3DSTATE_SO_DECL_LIST_CommandType_bits 3 +#define GEN75_3DSTATE_SO_DECL_LIST_CommandType_bits 3 +#define GEN7_3DSTATE_SO_DECL_LIST_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_DECL_LIST_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SO_DECL_LIST_CommandType_start 29 +#define GEN10_3DSTATE_SO_DECL_LIST_CommandType_start 29 +#define GEN9_3DSTATE_SO_DECL_LIST_CommandType_start 29 +#define GEN8_3DSTATE_SO_DECL_LIST_CommandType_start 29 +#define GEN75_3DSTATE_SO_DECL_LIST_CommandType_start 29 +#define GEN7_3DSTATE_SO_DECL_LIST_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_DECL_LIST_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SO_DECL_LIST::DWord Length */ + + +#define GEN11_3DSTATE_SO_DECL_LIST_DWordLength_bits 9 +#define GEN10_3DSTATE_SO_DECL_LIST_DWordLength_bits 9 +#define GEN9_3DSTATE_SO_DECL_LIST_DWordLength_bits 9 +#define GEN8_3DSTATE_SO_DECL_LIST_DWordLength_bits 9 +#define GEN75_3DSTATE_SO_DECL_LIST_DWordLength_bits 9 +#define GEN7_3DSTATE_SO_DECL_LIST_DWordLength_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_DECL_LIST_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 9; + case 10: return 9; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 9; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SO_DECL_LIST_DWordLength_start 0 +#define GEN10_3DSTATE_SO_DECL_LIST_DWordLength_start 0 +#define GEN9_3DSTATE_SO_DECL_LIST_DWordLength_start 0 +#define GEN8_3DSTATE_SO_DECL_LIST_DWordLength_start 0 +#define GEN75_3DSTATE_SO_DECL_LIST_DWordLength_start 0 +#define GEN7_3DSTATE_SO_DECL_LIST_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_DECL_LIST_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SO_DECL_LIST::Entry */ + + +#define GEN11_3DSTATE_SO_DECL_LIST_Entry_bits 64 +#define GEN10_3DSTATE_SO_DECL_LIST_Entry_bits 64 +#define GEN9_3DSTATE_SO_DECL_LIST_Entry_bits 64 +#define GEN8_3DSTATE_SO_DECL_LIST_Entry_bits 64 +#define GEN75_3DSTATE_SO_DECL_LIST_Entry_bits 64 +#define GEN7_3DSTATE_SO_DECL_LIST_Entry_bits 64 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_DECL_LIST_Entry_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SO_DECL_LIST_Entry_start 0 +#define GEN10_3DSTATE_SO_DECL_LIST_Entry_start 0 +#define GEN9_3DSTATE_SO_DECL_LIST_Entry_start 0 +#define GEN8_3DSTATE_SO_DECL_LIST_Entry_start 0 +#define GEN75_3DSTATE_SO_DECL_LIST_Entry_start 0 +#define GEN7_3DSTATE_SO_DECL_LIST_Entry_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_DECL_LIST_Entry_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SO_DECL_LIST::Num Entries [0] */ + + +#define GEN11_3DSTATE_SO_DECL_LIST_NumEntries0_bits 8 +#define GEN10_3DSTATE_SO_DECL_LIST_NumEntries0_bits 8 +#define GEN9_3DSTATE_SO_DECL_LIST_NumEntries0_bits 8 +#define GEN8_3DSTATE_SO_DECL_LIST_NumEntries0_bits 8 +#define GEN75_3DSTATE_SO_DECL_LIST_NumEntries0_bits 8 +#define GEN7_3DSTATE_SO_DECL_LIST_NumEntries0_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_DECL_LIST_NumEntries0_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SO_DECL_LIST_NumEntries0_start 64 +#define GEN10_3DSTATE_SO_DECL_LIST_NumEntries0_start 64 +#define GEN9_3DSTATE_SO_DECL_LIST_NumEntries0_start 64 +#define GEN8_3DSTATE_SO_DECL_LIST_NumEntries0_start 64 +#define GEN75_3DSTATE_SO_DECL_LIST_NumEntries0_start 64 +#define GEN7_3DSTATE_SO_DECL_LIST_NumEntries0_start 64 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_DECL_LIST_NumEntries0_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SO_DECL_LIST::Num Entries [1] */ + + +#define GEN11_3DSTATE_SO_DECL_LIST_NumEntries1_bits 8 +#define GEN10_3DSTATE_SO_DECL_LIST_NumEntries1_bits 8 +#define GEN9_3DSTATE_SO_DECL_LIST_NumEntries1_bits 8 +#define GEN8_3DSTATE_SO_DECL_LIST_NumEntries1_bits 8 +#define GEN75_3DSTATE_SO_DECL_LIST_NumEntries1_bits 8 +#define GEN7_3DSTATE_SO_DECL_LIST_NumEntries1_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_DECL_LIST_NumEntries1_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SO_DECL_LIST_NumEntries1_start 72 +#define GEN10_3DSTATE_SO_DECL_LIST_NumEntries1_start 72 +#define GEN9_3DSTATE_SO_DECL_LIST_NumEntries1_start 72 +#define GEN8_3DSTATE_SO_DECL_LIST_NumEntries1_start 72 +#define GEN75_3DSTATE_SO_DECL_LIST_NumEntries1_start 72 +#define GEN7_3DSTATE_SO_DECL_LIST_NumEntries1_start 72 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_DECL_LIST_NumEntries1_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 72; + case 10: return 72; + case 9: return 72; + case 8: return 72; + case 7: + if (devinfo->is_haswell) { + return 72; + } else { + return 72; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SO_DECL_LIST::Num Entries [2] */ + + +#define GEN11_3DSTATE_SO_DECL_LIST_NumEntries2_bits 8 +#define GEN10_3DSTATE_SO_DECL_LIST_NumEntries2_bits 8 +#define GEN9_3DSTATE_SO_DECL_LIST_NumEntries2_bits 8 +#define GEN8_3DSTATE_SO_DECL_LIST_NumEntries2_bits 8 +#define GEN75_3DSTATE_SO_DECL_LIST_NumEntries2_bits 8 +#define GEN7_3DSTATE_SO_DECL_LIST_NumEntries2_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_DECL_LIST_NumEntries2_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SO_DECL_LIST_NumEntries2_start 80 +#define GEN10_3DSTATE_SO_DECL_LIST_NumEntries2_start 80 +#define GEN9_3DSTATE_SO_DECL_LIST_NumEntries2_start 80 +#define GEN8_3DSTATE_SO_DECL_LIST_NumEntries2_start 80 +#define GEN75_3DSTATE_SO_DECL_LIST_NumEntries2_start 80 +#define GEN7_3DSTATE_SO_DECL_LIST_NumEntries2_start 80 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_DECL_LIST_NumEntries2_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 80; + case 10: return 80; + case 9: return 80; + case 8: return 80; + case 7: + if (devinfo->is_haswell) { + return 80; + } else { + return 80; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SO_DECL_LIST::Num Entries [3] */ + + +#define GEN11_3DSTATE_SO_DECL_LIST_NumEntries3_bits 8 +#define GEN10_3DSTATE_SO_DECL_LIST_NumEntries3_bits 8 +#define GEN9_3DSTATE_SO_DECL_LIST_NumEntries3_bits 8 +#define GEN8_3DSTATE_SO_DECL_LIST_NumEntries3_bits 8 +#define GEN75_3DSTATE_SO_DECL_LIST_NumEntries3_bits 8 +#define GEN7_3DSTATE_SO_DECL_LIST_NumEntries3_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_DECL_LIST_NumEntries3_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SO_DECL_LIST_NumEntries3_start 88 +#define GEN10_3DSTATE_SO_DECL_LIST_NumEntries3_start 88 +#define GEN9_3DSTATE_SO_DECL_LIST_NumEntries3_start 88 +#define GEN8_3DSTATE_SO_DECL_LIST_NumEntries3_start 88 +#define GEN75_3DSTATE_SO_DECL_LIST_NumEntries3_start 88 +#define GEN7_3DSTATE_SO_DECL_LIST_NumEntries3_start 88 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_DECL_LIST_NumEntries3_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 88; + case 10: return 88; + case 9: return 88; + case 8: return 88; + case 7: + if (devinfo->is_haswell) { + return 88; + } else { + return 88; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SO_DECL_LIST::Stream to Buffer Selects [0] */ + + +#define GEN11_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects0_bits 4 +#define GEN10_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects0_bits 4 +#define GEN9_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects0_bits 4 +#define GEN8_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects0_bits 4 +#define GEN75_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects0_bits 4 +#define GEN7_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects0_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects0_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects0_start 32 +#define GEN10_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects0_start 32 +#define GEN9_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects0_start 32 +#define GEN8_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects0_start 32 +#define GEN75_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects0_start 32 +#define GEN7_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects0_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects0_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SO_DECL_LIST::Stream to Buffer Selects [1] */ + + +#define GEN11_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects1_bits 4 +#define GEN10_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects1_bits 4 +#define GEN9_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects1_bits 4 +#define GEN8_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects1_bits 4 +#define GEN75_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects1_bits 4 +#define GEN7_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects1_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects1_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects1_start 36 +#define GEN10_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects1_start 36 +#define GEN9_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects1_start 36 +#define GEN8_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects1_start 36 +#define GEN75_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects1_start 36 +#define GEN7_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects1_start 36 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects1_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 36; + case 10: return 36; + case 9: return 36; + case 8: return 36; + case 7: + if (devinfo->is_haswell) { + return 36; + } else { + return 36; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SO_DECL_LIST::Stream to Buffer Selects [2] */ + + +#define GEN11_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects2_bits 4 +#define GEN10_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects2_bits 4 +#define GEN9_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects2_bits 4 +#define GEN8_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects2_bits 4 +#define GEN75_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects2_bits 4 +#define GEN7_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects2_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects2_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects2_start 40 +#define GEN10_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects2_start 40 +#define GEN9_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects2_start 40 +#define GEN8_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects2_start 40 +#define GEN75_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects2_start 40 +#define GEN7_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects2_start 40 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects2_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 40; + case 10: return 40; + case 9: return 40; + case 8: return 40; + case 7: + if (devinfo->is_haswell) { + return 40; + } else { + return 40; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_SO_DECL_LIST::Stream to Buffer Selects [3] */ + + +#define GEN11_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects3_bits 4 +#define GEN10_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects3_bits 4 +#define GEN9_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects3_bits 4 +#define GEN8_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects3_bits 4 +#define GEN75_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects3_bits 4 +#define GEN7_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects3_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects3_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects3_start 44 +#define GEN10_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects3_start 44 +#define GEN9_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects3_start 44 +#define GEN8_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects3_start 44 +#define GEN75_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects3_start 44 +#define GEN7_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects3_start 44 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_SO_DECL_LIST_StreamtoBufferSelects3_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 44; + case 10: return 44; + case 9: return 44; + case 8: return 44; + case 7: + if (devinfo->is_haswell) { + return 44; + } else { + return 44; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STENCIL_BUFFER */ + + +#define GEN11_3DSTATE_STENCIL_BUFFER_length 5 +#define GEN10_3DSTATE_STENCIL_BUFFER_length 5 +#define GEN9_3DSTATE_STENCIL_BUFFER_length 5 +#define GEN8_3DSTATE_STENCIL_BUFFER_length 5 +#define GEN75_3DSTATE_STENCIL_BUFFER_length 3 +#define GEN7_3DSTATE_STENCIL_BUFFER_length 3 +#define GEN6_3DSTATE_STENCIL_BUFFER_length 3 +#define GEN5_3DSTATE_STENCIL_BUFFER_length 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STENCIL_BUFFER_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STENCIL_BUFFER::3D Command Opcode */ + + +#define GEN11_3DSTATE_STENCIL_BUFFER_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_STENCIL_BUFFER_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_STENCIL_BUFFER_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_STENCIL_BUFFER_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_STENCIL_BUFFER_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_STENCIL_BUFFER_3DCommandOpcode_bits 3 +#define GEN6_3DSTATE_STENCIL_BUFFER_3DCommandOpcode_bits 3 +#define GEN5_3DSTATE_STENCIL_BUFFER_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STENCIL_BUFFER_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_STENCIL_BUFFER_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_STENCIL_BUFFER_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_STENCIL_BUFFER_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_STENCIL_BUFFER_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_STENCIL_BUFFER_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_STENCIL_BUFFER_3DCommandOpcode_start 24 +#define GEN6_3DSTATE_STENCIL_BUFFER_3DCommandOpcode_start 24 +#define GEN5_3DSTATE_STENCIL_BUFFER_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STENCIL_BUFFER_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 24; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STENCIL_BUFFER::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_STENCIL_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_STENCIL_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_STENCIL_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_STENCIL_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_STENCIL_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_STENCIL_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN6_3DSTATE_STENCIL_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN5_3DSTATE_STENCIL_BUFFER_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STENCIL_BUFFER_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_STENCIL_BUFFER_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_STENCIL_BUFFER_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_STENCIL_BUFFER_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_STENCIL_BUFFER_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_STENCIL_BUFFER_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_STENCIL_BUFFER_3DCommandSubOpcode_start 16 +#define GEN6_3DSTATE_STENCIL_BUFFER_3DCommandSubOpcode_start 16 +#define GEN5_3DSTATE_STENCIL_BUFFER_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STENCIL_BUFFER_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STENCIL_BUFFER::Command SubType */ + + +#define GEN11_3DSTATE_STENCIL_BUFFER_CommandSubType_bits 2 +#define GEN10_3DSTATE_STENCIL_BUFFER_CommandSubType_bits 2 +#define GEN9_3DSTATE_STENCIL_BUFFER_CommandSubType_bits 2 +#define GEN8_3DSTATE_STENCIL_BUFFER_CommandSubType_bits 2 +#define GEN75_3DSTATE_STENCIL_BUFFER_CommandSubType_bits 2 +#define GEN7_3DSTATE_STENCIL_BUFFER_CommandSubType_bits 2 +#define GEN6_3DSTATE_STENCIL_BUFFER_CommandSubType_bits 2 +#define GEN5_3DSTATE_STENCIL_BUFFER_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STENCIL_BUFFER_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_STENCIL_BUFFER_CommandSubType_start 27 +#define GEN10_3DSTATE_STENCIL_BUFFER_CommandSubType_start 27 +#define GEN9_3DSTATE_STENCIL_BUFFER_CommandSubType_start 27 +#define GEN8_3DSTATE_STENCIL_BUFFER_CommandSubType_start 27 +#define GEN75_3DSTATE_STENCIL_BUFFER_CommandSubType_start 27 +#define GEN7_3DSTATE_STENCIL_BUFFER_CommandSubType_start 27 +#define GEN6_3DSTATE_STENCIL_BUFFER_CommandSubType_start 27 +#define GEN5_3DSTATE_STENCIL_BUFFER_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STENCIL_BUFFER_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STENCIL_BUFFER::Command Type */ + + +#define GEN11_3DSTATE_STENCIL_BUFFER_CommandType_bits 3 +#define GEN10_3DSTATE_STENCIL_BUFFER_CommandType_bits 3 +#define GEN9_3DSTATE_STENCIL_BUFFER_CommandType_bits 3 +#define GEN8_3DSTATE_STENCIL_BUFFER_CommandType_bits 3 +#define GEN75_3DSTATE_STENCIL_BUFFER_CommandType_bits 3 +#define GEN7_3DSTATE_STENCIL_BUFFER_CommandType_bits 3 +#define GEN6_3DSTATE_STENCIL_BUFFER_CommandType_bits 3 +#define GEN5_3DSTATE_STENCIL_BUFFER_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STENCIL_BUFFER_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_STENCIL_BUFFER_CommandType_start 29 +#define GEN10_3DSTATE_STENCIL_BUFFER_CommandType_start 29 +#define GEN9_3DSTATE_STENCIL_BUFFER_CommandType_start 29 +#define GEN8_3DSTATE_STENCIL_BUFFER_CommandType_start 29 +#define GEN75_3DSTATE_STENCIL_BUFFER_CommandType_start 29 +#define GEN7_3DSTATE_STENCIL_BUFFER_CommandType_start 29 +#define GEN6_3DSTATE_STENCIL_BUFFER_CommandType_start 29 +#define GEN5_3DSTATE_STENCIL_BUFFER_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STENCIL_BUFFER_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 29; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STENCIL_BUFFER::DWord Length */ + + +#define GEN11_3DSTATE_STENCIL_BUFFER_DWordLength_bits 8 +#define GEN10_3DSTATE_STENCIL_BUFFER_DWordLength_bits 8 +#define GEN9_3DSTATE_STENCIL_BUFFER_DWordLength_bits 8 +#define GEN8_3DSTATE_STENCIL_BUFFER_DWordLength_bits 8 +#define GEN75_3DSTATE_STENCIL_BUFFER_DWordLength_bits 8 +#define GEN7_3DSTATE_STENCIL_BUFFER_DWordLength_bits 8 +#define GEN6_3DSTATE_STENCIL_BUFFER_DWordLength_bits 8 +#define GEN5_3DSTATE_STENCIL_BUFFER_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STENCIL_BUFFER_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_STENCIL_BUFFER_DWordLength_start 0 +#define GEN10_3DSTATE_STENCIL_BUFFER_DWordLength_start 0 +#define GEN9_3DSTATE_STENCIL_BUFFER_DWordLength_start 0 +#define GEN8_3DSTATE_STENCIL_BUFFER_DWordLength_start 0 +#define GEN75_3DSTATE_STENCIL_BUFFER_DWordLength_start 0 +#define GEN7_3DSTATE_STENCIL_BUFFER_DWordLength_start 0 +#define GEN6_3DSTATE_STENCIL_BUFFER_DWordLength_start 0 +#define GEN5_3DSTATE_STENCIL_BUFFER_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STENCIL_BUFFER_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STENCIL_BUFFER::MOCS */ + + +#define GEN11_3DSTATE_STENCIL_BUFFER_MOCS_bits 7 +#define GEN10_3DSTATE_STENCIL_BUFFER_MOCS_bits 7 +#define GEN9_3DSTATE_STENCIL_BUFFER_MOCS_bits 7 +#define GEN8_3DSTATE_STENCIL_BUFFER_MOCS_bits 7 +#define GEN75_3DSTATE_STENCIL_BUFFER_MOCS_bits 4 +#define GEN7_3DSTATE_STENCIL_BUFFER_MOCS_bits 4 +#define GEN6_3DSTATE_STENCIL_BUFFER_MOCS_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STENCIL_BUFFER_MOCS_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_STENCIL_BUFFER_MOCS_start 54 +#define GEN10_3DSTATE_STENCIL_BUFFER_MOCS_start 54 +#define GEN9_3DSTATE_STENCIL_BUFFER_MOCS_start 54 +#define GEN8_3DSTATE_STENCIL_BUFFER_MOCS_start 54 +#define GEN75_3DSTATE_STENCIL_BUFFER_MOCS_start 57 +#define GEN7_3DSTATE_STENCIL_BUFFER_MOCS_start 57 +#define GEN6_3DSTATE_STENCIL_BUFFER_MOCS_start 57 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STENCIL_BUFFER_MOCS_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 54; + case 10: return 54; + case 9: return 54; + case 8: return 54; + case 7: + if (devinfo->is_haswell) { + return 57; + } else { + return 57; + } + case 6: return 57; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STENCIL_BUFFER::Stencil Buffer Enable */ + + +#define GEN11_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_bits 1 +#define GEN10_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_bits 1 +#define GEN9_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_bits 1 +#define GEN8_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_bits 1 +#define GEN75_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_start 63 +#define GEN10_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_start 63 +#define GEN9_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_start 63 +#define GEN8_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_start 63 +#define GEN75_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_start 63 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STENCIL_BUFFER_StencilBufferEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 63; + case 10: return 63; + case 9: return 63; + case 8: return 63; + case 7: + if (devinfo->is_haswell) { + return 63; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STENCIL_BUFFER::Surface Base Address */ + + +#define GEN11_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_bits 64 +#define GEN10_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_bits 64 +#define GEN9_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_bits 64 +#define GEN8_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_bits 64 +#define GEN75_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_bits 32 +#define GEN7_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_bits 32 +#define GEN6_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_bits 32 +#define GEN5_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start 64 +#define GEN10_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start 64 +#define GEN9_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start 64 +#define GEN8_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start 64 +#define GEN75_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start 64 +#define GEN7_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start 64 +#define GEN6_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start 64 +#define GEN5_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start 64 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STENCIL_BUFFER_SurfaceBaseAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 64; + case 5: return 64; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STENCIL_BUFFER::Surface Pitch */ + + +#define GEN11_3DSTATE_STENCIL_BUFFER_SurfacePitch_bits 17 +#define GEN10_3DSTATE_STENCIL_BUFFER_SurfacePitch_bits 17 +#define GEN9_3DSTATE_STENCIL_BUFFER_SurfacePitch_bits 17 +#define GEN8_3DSTATE_STENCIL_BUFFER_SurfacePitch_bits 17 +#define GEN75_3DSTATE_STENCIL_BUFFER_SurfacePitch_bits 17 +#define GEN7_3DSTATE_STENCIL_BUFFER_SurfacePitch_bits 17 +#define GEN6_3DSTATE_STENCIL_BUFFER_SurfacePitch_bits 17 +#define GEN5_3DSTATE_STENCIL_BUFFER_SurfacePitch_bits 17 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STENCIL_BUFFER_SurfacePitch_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 17; + case 10: return 17; + case 9: return 17; + case 8: return 17; + case 7: + if (devinfo->is_haswell) { + return 17; + } else { + return 17; + } + case 6: return 17; + case 5: return 17; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_STENCIL_BUFFER_SurfacePitch_start 32 +#define GEN10_3DSTATE_STENCIL_BUFFER_SurfacePitch_start 32 +#define GEN9_3DSTATE_STENCIL_BUFFER_SurfacePitch_start 32 +#define GEN8_3DSTATE_STENCIL_BUFFER_SurfacePitch_start 32 +#define GEN75_3DSTATE_STENCIL_BUFFER_SurfacePitch_start 32 +#define GEN7_3DSTATE_STENCIL_BUFFER_SurfacePitch_start 32 +#define GEN6_3DSTATE_STENCIL_BUFFER_SurfacePitch_start 32 +#define GEN5_3DSTATE_STENCIL_BUFFER_SurfacePitch_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STENCIL_BUFFER_SurfacePitch_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STENCIL_BUFFER::Surface QPitch */ + + +#define GEN11_3DSTATE_STENCIL_BUFFER_SurfaceQPitch_bits 15 +#define GEN10_3DSTATE_STENCIL_BUFFER_SurfaceQPitch_bits 15 +#define GEN9_3DSTATE_STENCIL_BUFFER_SurfaceQPitch_bits 15 +#define GEN8_3DSTATE_STENCIL_BUFFER_SurfaceQPitch_bits 15 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STENCIL_BUFFER_SurfaceQPitch_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 15; + case 10: return 15; + case 9: return 15; + case 8: return 15; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_STENCIL_BUFFER_SurfaceQPitch_start 128 +#define GEN10_3DSTATE_STENCIL_BUFFER_SurfaceQPitch_start 128 +#define GEN9_3DSTATE_STENCIL_BUFFER_SurfaceQPitch_start 128 +#define GEN8_3DSTATE_STENCIL_BUFFER_SurfaceQPitch_start 128 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STENCIL_BUFFER_SurfaceQPitch_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 128; + case 10: return 128; + case 9: return 128; + case 8: return 128; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STREAMOUT */ + + +#define GEN11_3DSTATE_STREAMOUT_length 5 +#define GEN10_3DSTATE_STREAMOUT_length 5 +#define GEN9_3DSTATE_STREAMOUT_length 5 +#define GEN8_3DSTATE_STREAMOUT_length 5 +#define GEN75_3DSTATE_STREAMOUT_length 3 +#define GEN7_3DSTATE_STREAMOUT_length 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STREAMOUT::3D Command Opcode */ + + +#define GEN11_3DSTATE_STREAMOUT_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_STREAMOUT_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_STREAMOUT_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_STREAMOUT_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_STREAMOUT_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_STREAMOUT_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_STREAMOUT_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_STREAMOUT_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_STREAMOUT_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_STREAMOUT_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_STREAMOUT_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_STREAMOUT_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STREAMOUT::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_STREAMOUT_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_STREAMOUT_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_STREAMOUT_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_STREAMOUT_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_STREAMOUT_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_STREAMOUT_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_STREAMOUT_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_STREAMOUT_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_STREAMOUT_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_STREAMOUT_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_STREAMOUT_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_STREAMOUT_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STREAMOUT::Buffer 0 Surface Pitch */ + + +#define GEN11_3DSTATE_STREAMOUT_Buffer0SurfacePitch_bits 12 +#define GEN10_3DSTATE_STREAMOUT_Buffer0SurfacePitch_bits 12 +#define GEN9_3DSTATE_STREAMOUT_Buffer0SurfacePitch_bits 12 +#define GEN8_3DSTATE_STREAMOUT_Buffer0SurfacePitch_bits 12 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_Buffer0SurfacePitch_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 12; + case 10: return 12; + case 9: return 12; + case 8: return 12; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_STREAMOUT_Buffer0SurfacePitch_start 96 +#define GEN10_3DSTATE_STREAMOUT_Buffer0SurfacePitch_start 96 +#define GEN9_3DSTATE_STREAMOUT_Buffer0SurfacePitch_start 96 +#define GEN8_3DSTATE_STREAMOUT_Buffer0SurfacePitch_start 96 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_Buffer0SurfacePitch_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 96; + case 10: return 96; + case 9: return 96; + case 8: return 96; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STREAMOUT::Buffer 1 Surface Pitch */ + + +#define GEN11_3DSTATE_STREAMOUT_Buffer1SurfacePitch_bits 12 +#define GEN10_3DSTATE_STREAMOUT_Buffer1SurfacePitch_bits 12 +#define GEN9_3DSTATE_STREAMOUT_Buffer1SurfacePitch_bits 12 +#define GEN8_3DSTATE_STREAMOUT_Buffer1SurfacePitch_bits 12 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_Buffer1SurfacePitch_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 12; + case 10: return 12; + case 9: return 12; + case 8: return 12; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_STREAMOUT_Buffer1SurfacePitch_start 112 +#define GEN10_3DSTATE_STREAMOUT_Buffer1SurfacePitch_start 112 +#define GEN9_3DSTATE_STREAMOUT_Buffer1SurfacePitch_start 112 +#define GEN8_3DSTATE_STREAMOUT_Buffer1SurfacePitch_start 112 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_Buffer1SurfacePitch_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 112; + case 10: return 112; + case 9: return 112; + case 8: return 112; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STREAMOUT::Buffer 2 Surface Pitch */ + + +#define GEN11_3DSTATE_STREAMOUT_Buffer2SurfacePitch_bits 12 +#define GEN10_3DSTATE_STREAMOUT_Buffer2SurfacePitch_bits 12 +#define GEN9_3DSTATE_STREAMOUT_Buffer2SurfacePitch_bits 12 +#define GEN8_3DSTATE_STREAMOUT_Buffer2SurfacePitch_bits 12 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_Buffer2SurfacePitch_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 12; + case 10: return 12; + case 9: return 12; + case 8: return 12; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_STREAMOUT_Buffer2SurfacePitch_start 128 +#define GEN10_3DSTATE_STREAMOUT_Buffer2SurfacePitch_start 128 +#define GEN9_3DSTATE_STREAMOUT_Buffer2SurfacePitch_start 128 +#define GEN8_3DSTATE_STREAMOUT_Buffer2SurfacePitch_start 128 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_Buffer2SurfacePitch_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 128; + case 10: return 128; + case 9: return 128; + case 8: return 128; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STREAMOUT::Buffer 3 Surface Pitch */ + + +#define GEN11_3DSTATE_STREAMOUT_Buffer3SurfacePitch_bits 12 +#define GEN10_3DSTATE_STREAMOUT_Buffer3SurfacePitch_bits 12 +#define GEN9_3DSTATE_STREAMOUT_Buffer3SurfacePitch_bits 12 +#define GEN8_3DSTATE_STREAMOUT_Buffer3SurfacePitch_bits 12 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_Buffer3SurfacePitch_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 12; + case 10: return 12; + case 9: return 12; + case 8: return 12; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_STREAMOUT_Buffer3SurfacePitch_start 144 +#define GEN10_3DSTATE_STREAMOUT_Buffer3SurfacePitch_start 144 +#define GEN9_3DSTATE_STREAMOUT_Buffer3SurfacePitch_start 144 +#define GEN8_3DSTATE_STREAMOUT_Buffer3SurfacePitch_start 144 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_Buffer3SurfacePitch_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 144; + case 10: return 144; + case 9: return 144; + case 8: return 144; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STREAMOUT::Command SubType */ + + +#define GEN11_3DSTATE_STREAMOUT_CommandSubType_bits 2 +#define GEN10_3DSTATE_STREAMOUT_CommandSubType_bits 2 +#define GEN9_3DSTATE_STREAMOUT_CommandSubType_bits 2 +#define GEN8_3DSTATE_STREAMOUT_CommandSubType_bits 2 +#define GEN75_3DSTATE_STREAMOUT_CommandSubType_bits 2 +#define GEN7_3DSTATE_STREAMOUT_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_STREAMOUT_CommandSubType_start 27 +#define GEN10_3DSTATE_STREAMOUT_CommandSubType_start 27 +#define GEN9_3DSTATE_STREAMOUT_CommandSubType_start 27 +#define GEN8_3DSTATE_STREAMOUT_CommandSubType_start 27 +#define GEN75_3DSTATE_STREAMOUT_CommandSubType_start 27 +#define GEN7_3DSTATE_STREAMOUT_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STREAMOUT::Command Type */ + + +#define GEN11_3DSTATE_STREAMOUT_CommandType_bits 3 +#define GEN10_3DSTATE_STREAMOUT_CommandType_bits 3 +#define GEN9_3DSTATE_STREAMOUT_CommandType_bits 3 +#define GEN8_3DSTATE_STREAMOUT_CommandType_bits 3 +#define GEN75_3DSTATE_STREAMOUT_CommandType_bits 3 +#define GEN7_3DSTATE_STREAMOUT_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_STREAMOUT_CommandType_start 29 +#define GEN10_3DSTATE_STREAMOUT_CommandType_start 29 +#define GEN9_3DSTATE_STREAMOUT_CommandType_start 29 +#define GEN8_3DSTATE_STREAMOUT_CommandType_start 29 +#define GEN75_3DSTATE_STREAMOUT_CommandType_start 29 +#define GEN7_3DSTATE_STREAMOUT_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STREAMOUT::DWord Length */ + + +#define GEN11_3DSTATE_STREAMOUT_DWordLength_bits 8 +#define GEN10_3DSTATE_STREAMOUT_DWordLength_bits 8 +#define GEN9_3DSTATE_STREAMOUT_DWordLength_bits 8 +#define GEN8_3DSTATE_STREAMOUT_DWordLength_bits 8 +#define GEN75_3DSTATE_STREAMOUT_DWordLength_bits 8 +#define GEN7_3DSTATE_STREAMOUT_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_STREAMOUT_DWordLength_start 0 +#define GEN10_3DSTATE_STREAMOUT_DWordLength_start 0 +#define GEN9_3DSTATE_STREAMOUT_DWordLength_start 0 +#define GEN8_3DSTATE_STREAMOUT_DWordLength_start 0 +#define GEN75_3DSTATE_STREAMOUT_DWordLength_start 0 +#define GEN7_3DSTATE_STREAMOUT_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STREAMOUT::Force Rendering */ + + +#define GEN11_3DSTATE_STREAMOUT_ForceRendering_bits 2 +#define GEN10_3DSTATE_STREAMOUT_ForceRendering_bits 2 +#define GEN9_3DSTATE_STREAMOUT_ForceRendering_bits 2 +#define GEN8_3DSTATE_STREAMOUT_ForceRendering_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_ForceRendering_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_STREAMOUT_ForceRendering_start 55 +#define GEN10_3DSTATE_STREAMOUT_ForceRendering_start 55 +#define GEN9_3DSTATE_STREAMOUT_ForceRendering_start 55 +#define GEN8_3DSTATE_STREAMOUT_ForceRendering_start 55 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_ForceRendering_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 55; + case 10: return 55; + case 9: return 55; + case 8: return 55; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STREAMOUT::Render Stream Select */ + + +#define GEN11_3DSTATE_STREAMOUT_RenderStreamSelect_bits 2 +#define GEN10_3DSTATE_STREAMOUT_RenderStreamSelect_bits 2 +#define GEN9_3DSTATE_STREAMOUT_RenderStreamSelect_bits 2 +#define GEN8_3DSTATE_STREAMOUT_RenderStreamSelect_bits 2 +#define GEN75_3DSTATE_STREAMOUT_RenderStreamSelect_bits 2 +#define GEN7_3DSTATE_STREAMOUT_RenderStreamSelect_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_RenderStreamSelect_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_STREAMOUT_RenderStreamSelect_start 59 +#define GEN10_3DSTATE_STREAMOUT_RenderStreamSelect_start 59 +#define GEN9_3DSTATE_STREAMOUT_RenderStreamSelect_start 59 +#define GEN8_3DSTATE_STREAMOUT_RenderStreamSelect_start 59 +#define GEN75_3DSTATE_STREAMOUT_RenderStreamSelect_start 59 +#define GEN7_3DSTATE_STREAMOUT_RenderStreamSelect_start 59 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_RenderStreamSelect_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 59; + case 10: return 59; + case 9: return 59; + case 8: return 59; + case 7: + if (devinfo->is_haswell) { + return 59; + } else { + return 59; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STREAMOUT::Rendering Disable */ + + +#define GEN11_3DSTATE_STREAMOUT_RenderingDisable_bits 1 +#define GEN10_3DSTATE_STREAMOUT_RenderingDisable_bits 1 +#define GEN9_3DSTATE_STREAMOUT_RenderingDisable_bits 1 +#define GEN8_3DSTATE_STREAMOUT_RenderingDisable_bits 1 +#define GEN75_3DSTATE_STREAMOUT_RenderingDisable_bits 1 +#define GEN7_3DSTATE_STREAMOUT_RenderingDisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_RenderingDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_STREAMOUT_RenderingDisable_start 62 +#define GEN10_3DSTATE_STREAMOUT_RenderingDisable_start 62 +#define GEN9_3DSTATE_STREAMOUT_RenderingDisable_start 62 +#define GEN8_3DSTATE_STREAMOUT_RenderingDisable_start 62 +#define GEN75_3DSTATE_STREAMOUT_RenderingDisable_start 62 +#define GEN7_3DSTATE_STREAMOUT_RenderingDisable_start 62 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_RenderingDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 62; + case 10: return 62; + case 9: return 62; + case 8: return 62; + case 7: + if (devinfo->is_haswell) { + return 62; + } else { + return 62; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STREAMOUT::Reorder Mode */ + + +#define GEN11_3DSTATE_STREAMOUT_ReorderMode_bits 1 +#define GEN10_3DSTATE_STREAMOUT_ReorderMode_bits 1 +#define GEN9_3DSTATE_STREAMOUT_ReorderMode_bits 1 +#define GEN8_3DSTATE_STREAMOUT_ReorderMode_bits 1 +#define GEN75_3DSTATE_STREAMOUT_ReorderMode_bits 1 +#define GEN7_3DSTATE_STREAMOUT_ReorderMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_ReorderMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_STREAMOUT_ReorderMode_start 58 +#define GEN10_3DSTATE_STREAMOUT_ReorderMode_start 58 +#define GEN9_3DSTATE_STREAMOUT_ReorderMode_start 58 +#define GEN8_3DSTATE_STREAMOUT_ReorderMode_start 58 +#define GEN75_3DSTATE_STREAMOUT_ReorderMode_start 58 +#define GEN7_3DSTATE_STREAMOUT_ReorderMode_start 58 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_ReorderMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 58; + case 10: return 58; + case 9: return 58; + case 8: return 58; + case 7: + if (devinfo->is_haswell) { + return 58; + } else { + return 58; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STREAMOUT::SO Buffer Enable [0] */ + + +#define GEN75_3DSTATE_STREAMOUT_SOBufferEnable0_bits 1 +#define GEN7_3DSTATE_STREAMOUT_SOBufferEnable0_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_SOBufferEnable0_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_STREAMOUT_SOBufferEnable0_start 40 +#define GEN7_3DSTATE_STREAMOUT_SOBufferEnable0_start 40 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_SOBufferEnable0_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 40; + } else { + return 40; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STREAMOUT::SO Buffer Enable [1] */ + + +#define GEN75_3DSTATE_STREAMOUT_SOBufferEnable1_bits 1 +#define GEN7_3DSTATE_STREAMOUT_SOBufferEnable1_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_SOBufferEnable1_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_STREAMOUT_SOBufferEnable1_start 41 +#define GEN7_3DSTATE_STREAMOUT_SOBufferEnable1_start 41 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_SOBufferEnable1_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 41; + } else { + return 41; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STREAMOUT::SO Buffer Enable [2] */ + + +#define GEN75_3DSTATE_STREAMOUT_SOBufferEnable2_bits 1 +#define GEN7_3DSTATE_STREAMOUT_SOBufferEnable2_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_SOBufferEnable2_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_STREAMOUT_SOBufferEnable2_start 42 +#define GEN7_3DSTATE_STREAMOUT_SOBufferEnable2_start 42 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_SOBufferEnable2_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 42; + } else { + return 42; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STREAMOUT::SO Buffer Enable [3] */ + + +#define GEN75_3DSTATE_STREAMOUT_SOBufferEnable3_bits 1 +#define GEN7_3DSTATE_STREAMOUT_SOBufferEnable3_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_SOBufferEnable3_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_STREAMOUT_SOBufferEnable3_start 43 +#define GEN7_3DSTATE_STREAMOUT_SOBufferEnable3_start 43 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_SOBufferEnable3_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 43; + } else { + return 43; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STREAMOUT::SO Function Enable */ + + +#define GEN11_3DSTATE_STREAMOUT_SOFunctionEnable_bits 1 +#define GEN10_3DSTATE_STREAMOUT_SOFunctionEnable_bits 1 +#define GEN9_3DSTATE_STREAMOUT_SOFunctionEnable_bits 1 +#define GEN8_3DSTATE_STREAMOUT_SOFunctionEnable_bits 1 +#define GEN75_3DSTATE_STREAMOUT_SOFunctionEnable_bits 1 +#define GEN7_3DSTATE_STREAMOUT_SOFunctionEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_SOFunctionEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_STREAMOUT_SOFunctionEnable_start 63 +#define GEN10_3DSTATE_STREAMOUT_SOFunctionEnable_start 63 +#define GEN9_3DSTATE_STREAMOUT_SOFunctionEnable_start 63 +#define GEN8_3DSTATE_STREAMOUT_SOFunctionEnable_start 63 +#define GEN75_3DSTATE_STREAMOUT_SOFunctionEnable_start 63 +#define GEN7_3DSTATE_STREAMOUT_SOFunctionEnable_start 63 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_SOFunctionEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 63; + case 10: return 63; + case 9: return 63; + case 8: return 63; + case 7: + if (devinfo->is_haswell) { + return 63; + } else { + return 63; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STREAMOUT::SO Statistics Enable */ + + +#define GEN11_3DSTATE_STREAMOUT_SOStatisticsEnable_bits 1 +#define GEN10_3DSTATE_STREAMOUT_SOStatisticsEnable_bits 1 +#define GEN9_3DSTATE_STREAMOUT_SOStatisticsEnable_bits 1 +#define GEN8_3DSTATE_STREAMOUT_SOStatisticsEnable_bits 1 +#define GEN75_3DSTATE_STREAMOUT_SOStatisticsEnable_bits 1 +#define GEN7_3DSTATE_STREAMOUT_SOStatisticsEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_SOStatisticsEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_STREAMOUT_SOStatisticsEnable_start 57 +#define GEN10_3DSTATE_STREAMOUT_SOStatisticsEnable_start 57 +#define GEN9_3DSTATE_STREAMOUT_SOStatisticsEnable_start 57 +#define GEN8_3DSTATE_STREAMOUT_SOStatisticsEnable_start 57 +#define GEN75_3DSTATE_STREAMOUT_SOStatisticsEnable_start 57 +#define GEN7_3DSTATE_STREAMOUT_SOStatisticsEnable_start 57 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_SOStatisticsEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 57; + case 10: return 57; + case 9: return 57; + case 8: return 57; + case 7: + if (devinfo->is_haswell) { + return 57; + } else { + return 57; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STREAMOUT::Stream 0 Vertex Read Length */ + + +#define GEN11_3DSTATE_STREAMOUT_Stream0VertexReadLength_bits 5 +#define GEN10_3DSTATE_STREAMOUT_Stream0VertexReadLength_bits 5 +#define GEN9_3DSTATE_STREAMOUT_Stream0VertexReadLength_bits 5 +#define GEN8_3DSTATE_STREAMOUT_Stream0VertexReadLength_bits 5 +#define GEN75_3DSTATE_STREAMOUT_Stream0VertexReadLength_bits 5 +#define GEN7_3DSTATE_STREAMOUT_Stream0VertexReadLength_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_Stream0VertexReadLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 5; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_STREAMOUT_Stream0VertexReadLength_start 64 +#define GEN10_3DSTATE_STREAMOUT_Stream0VertexReadLength_start 64 +#define GEN9_3DSTATE_STREAMOUT_Stream0VertexReadLength_start 64 +#define GEN8_3DSTATE_STREAMOUT_Stream0VertexReadLength_start 64 +#define GEN75_3DSTATE_STREAMOUT_Stream0VertexReadLength_start 64 +#define GEN7_3DSTATE_STREAMOUT_Stream0VertexReadLength_start 64 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_Stream0VertexReadLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STREAMOUT::Stream 0 Vertex Read Offset */ + + +#define GEN11_3DSTATE_STREAMOUT_Stream0VertexReadOffset_bits 1 +#define GEN10_3DSTATE_STREAMOUT_Stream0VertexReadOffset_bits 1 +#define GEN9_3DSTATE_STREAMOUT_Stream0VertexReadOffset_bits 1 +#define GEN8_3DSTATE_STREAMOUT_Stream0VertexReadOffset_bits 1 +#define GEN75_3DSTATE_STREAMOUT_Stream0VertexReadOffset_bits 1 +#define GEN7_3DSTATE_STREAMOUT_Stream0VertexReadOffset_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_Stream0VertexReadOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_STREAMOUT_Stream0VertexReadOffset_start 69 +#define GEN10_3DSTATE_STREAMOUT_Stream0VertexReadOffset_start 69 +#define GEN9_3DSTATE_STREAMOUT_Stream0VertexReadOffset_start 69 +#define GEN8_3DSTATE_STREAMOUT_Stream0VertexReadOffset_start 69 +#define GEN75_3DSTATE_STREAMOUT_Stream0VertexReadOffset_start 69 +#define GEN7_3DSTATE_STREAMOUT_Stream0VertexReadOffset_start 69 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_Stream0VertexReadOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 69; + case 10: return 69; + case 9: return 69; + case 8: return 69; + case 7: + if (devinfo->is_haswell) { + return 69; + } else { + return 69; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STREAMOUT::Stream 1 Vertex Read Length */ + + +#define GEN11_3DSTATE_STREAMOUT_Stream1VertexReadLength_bits 5 +#define GEN10_3DSTATE_STREAMOUT_Stream1VertexReadLength_bits 5 +#define GEN9_3DSTATE_STREAMOUT_Stream1VertexReadLength_bits 5 +#define GEN8_3DSTATE_STREAMOUT_Stream1VertexReadLength_bits 5 +#define GEN75_3DSTATE_STREAMOUT_Stream1VertexReadLength_bits 5 +#define GEN7_3DSTATE_STREAMOUT_Stream1VertexReadLength_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_Stream1VertexReadLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 5; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_STREAMOUT_Stream1VertexReadLength_start 72 +#define GEN10_3DSTATE_STREAMOUT_Stream1VertexReadLength_start 72 +#define GEN9_3DSTATE_STREAMOUT_Stream1VertexReadLength_start 72 +#define GEN8_3DSTATE_STREAMOUT_Stream1VertexReadLength_start 72 +#define GEN75_3DSTATE_STREAMOUT_Stream1VertexReadLength_start 72 +#define GEN7_3DSTATE_STREAMOUT_Stream1VertexReadLength_start 72 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_Stream1VertexReadLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 72; + case 10: return 72; + case 9: return 72; + case 8: return 72; + case 7: + if (devinfo->is_haswell) { + return 72; + } else { + return 72; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STREAMOUT::Stream 1 Vertex Read Offset */ + + +#define GEN11_3DSTATE_STREAMOUT_Stream1VertexReadOffset_bits 1 +#define GEN10_3DSTATE_STREAMOUT_Stream1VertexReadOffset_bits 1 +#define GEN9_3DSTATE_STREAMOUT_Stream1VertexReadOffset_bits 1 +#define GEN8_3DSTATE_STREAMOUT_Stream1VertexReadOffset_bits 1 +#define GEN75_3DSTATE_STREAMOUT_Stream1VertexReadOffset_bits 1 +#define GEN7_3DSTATE_STREAMOUT_Stream1VertexReadOffset_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_Stream1VertexReadOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_STREAMOUT_Stream1VertexReadOffset_start 77 +#define GEN10_3DSTATE_STREAMOUT_Stream1VertexReadOffset_start 77 +#define GEN9_3DSTATE_STREAMOUT_Stream1VertexReadOffset_start 77 +#define GEN8_3DSTATE_STREAMOUT_Stream1VertexReadOffset_start 77 +#define GEN75_3DSTATE_STREAMOUT_Stream1VertexReadOffset_start 77 +#define GEN7_3DSTATE_STREAMOUT_Stream1VertexReadOffset_start 77 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_Stream1VertexReadOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 77; + case 10: return 77; + case 9: return 77; + case 8: return 77; + case 7: + if (devinfo->is_haswell) { + return 77; + } else { + return 77; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STREAMOUT::Stream 2 Vertex Read Length */ + + +#define GEN11_3DSTATE_STREAMOUT_Stream2VertexReadLength_bits 5 +#define GEN10_3DSTATE_STREAMOUT_Stream2VertexReadLength_bits 5 +#define GEN9_3DSTATE_STREAMOUT_Stream2VertexReadLength_bits 5 +#define GEN8_3DSTATE_STREAMOUT_Stream2VertexReadLength_bits 5 +#define GEN75_3DSTATE_STREAMOUT_Stream2VertexReadLength_bits 5 +#define GEN7_3DSTATE_STREAMOUT_Stream2VertexReadLength_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_Stream2VertexReadLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 5; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_STREAMOUT_Stream2VertexReadLength_start 80 +#define GEN10_3DSTATE_STREAMOUT_Stream2VertexReadLength_start 80 +#define GEN9_3DSTATE_STREAMOUT_Stream2VertexReadLength_start 80 +#define GEN8_3DSTATE_STREAMOUT_Stream2VertexReadLength_start 80 +#define GEN75_3DSTATE_STREAMOUT_Stream2VertexReadLength_start 80 +#define GEN7_3DSTATE_STREAMOUT_Stream2VertexReadLength_start 80 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_Stream2VertexReadLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 80; + case 10: return 80; + case 9: return 80; + case 8: return 80; + case 7: + if (devinfo->is_haswell) { + return 80; + } else { + return 80; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STREAMOUT::Stream 2 Vertex Read Offset */ + + +#define GEN11_3DSTATE_STREAMOUT_Stream2VertexReadOffset_bits 1 +#define GEN10_3DSTATE_STREAMOUT_Stream2VertexReadOffset_bits 1 +#define GEN9_3DSTATE_STREAMOUT_Stream2VertexReadOffset_bits 1 +#define GEN8_3DSTATE_STREAMOUT_Stream2VertexReadOffset_bits 1 +#define GEN75_3DSTATE_STREAMOUT_Stream2VertexReadOffset_bits 1 +#define GEN7_3DSTATE_STREAMOUT_Stream2VertexReadOffset_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_Stream2VertexReadOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_STREAMOUT_Stream2VertexReadOffset_start 85 +#define GEN10_3DSTATE_STREAMOUT_Stream2VertexReadOffset_start 85 +#define GEN9_3DSTATE_STREAMOUT_Stream2VertexReadOffset_start 85 +#define GEN8_3DSTATE_STREAMOUT_Stream2VertexReadOffset_start 85 +#define GEN75_3DSTATE_STREAMOUT_Stream2VertexReadOffset_start 85 +#define GEN7_3DSTATE_STREAMOUT_Stream2VertexReadOffset_start 85 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_Stream2VertexReadOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 85; + case 10: return 85; + case 9: return 85; + case 8: return 85; + case 7: + if (devinfo->is_haswell) { + return 85; + } else { + return 85; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STREAMOUT::Stream 3 Vertex Read Length */ + + +#define GEN11_3DSTATE_STREAMOUT_Stream3VertexReadLength_bits 5 +#define GEN10_3DSTATE_STREAMOUT_Stream3VertexReadLength_bits 5 +#define GEN9_3DSTATE_STREAMOUT_Stream3VertexReadLength_bits 5 +#define GEN8_3DSTATE_STREAMOUT_Stream3VertexReadLength_bits 5 +#define GEN75_3DSTATE_STREAMOUT_Stream3VertexReadLength_bits 5 +#define GEN7_3DSTATE_STREAMOUT_Stream3VertexReadLength_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_Stream3VertexReadLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 5; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_STREAMOUT_Stream3VertexReadLength_start 88 +#define GEN10_3DSTATE_STREAMOUT_Stream3VertexReadLength_start 88 +#define GEN9_3DSTATE_STREAMOUT_Stream3VertexReadLength_start 88 +#define GEN8_3DSTATE_STREAMOUT_Stream3VertexReadLength_start 88 +#define GEN75_3DSTATE_STREAMOUT_Stream3VertexReadLength_start 88 +#define GEN7_3DSTATE_STREAMOUT_Stream3VertexReadLength_start 88 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_Stream3VertexReadLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 88; + case 10: return 88; + case 9: return 88; + case 8: return 88; + case 7: + if (devinfo->is_haswell) { + return 88; + } else { + return 88; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_STREAMOUT::Stream 3 Vertex Read Offset */ + + +#define GEN11_3DSTATE_STREAMOUT_Stream3VertexReadOffset_bits 1 +#define GEN10_3DSTATE_STREAMOUT_Stream3VertexReadOffset_bits 1 +#define GEN9_3DSTATE_STREAMOUT_Stream3VertexReadOffset_bits 1 +#define GEN8_3DSTATE_STREAMOUT_Stream3VertexReadOffset_bits 1 +#define GEN75_3DSTATE_STREAMOUT_Stream3VertexReadOffset_bits 1 +#define GEN7_3DSTATE_STREAMOUT_Stream3VertexReadOffset_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_Stream3VertexReadOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_STREAMOUT_Stream3VertexReadOffset_start 93 +#define GEN10_3DSTATE_STREAMOUT_Stream3VertexReadOffset_start 93 +#define GEN9_3DSTATE_STREAMOUT_Stream3VertexReadOffset_start 93 +#define GEN8_3DSTATE_STREAMOUT_Stream3VertexReadOffset_start 93 +#define GEN75_3DSTATE_STREAMOUT_Stream3VertexReadOffset_start 93 +#define GEN7_3DSTATE_STREAMOUT_Stream3VertexReadOffset_start 93 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_STREAMOUT_Stream3VertexReadOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 93; + case 10: return 93; + case 9: return 93; + case 8: return 93; + case 7: + if (devinfo->is_haswell) { + return 93; + } else { + return 93; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_TE */ + + +#define GEN11_3DSTATE_TE_length 4 +#define GEN10_3DSTATE_TE_length 4 +#define GEN9_3DSTATE_TE_length 4 +#define GEN8_3DSTATE_TE_length 4 +#define GEN75_3DSTATE_TE_length 4 +#define GEN7_3DSTATE_TE_length 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_TE_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_TE::3D Command Opcode */ + + +#define GEN11_3DSTATE_TE_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_TE_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_TE_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_TE_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_TE_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_TE_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_TE_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_TE_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_TE_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_TE_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_TE_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_TE_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_TE_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_TE_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_TE::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_TE_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_TE_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_TE_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_TE_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_TE_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_TE_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_TE_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_TE_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_TE_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_TE_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_TE_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_TE_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_TE_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_TE_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_TE::Command SubType */ + + +#define GEN11_3DSTATE_TE_CommandSubType_bits 2 +#define GEN10_3DSTATE_TE_CommandSubType_bits 2 +#define GEN9_3DSTATE_TE_CommandSubType_bits 2 +#define GEN8_3DSTATE_TE_CommandSubType_bits 2 +#define GEN75_3DSTATE_TE_CommandSubType_bits 2 +#define GEN7_3DSTATE_TE_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_TE_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_TE_CommandSubType_start 27 +#define GEN10_3DSTATE_TE_CommandSubType_start 27 +#define GEN9_3DSTATE_TE_CommandSubType_start 27 +#define GEN8_3DSTATE_TE_CommandSubType_start 27 +#define GEN75_3DSTATE_TE_CommandSubType_start 27 +#define GEN7_3DSTATE_TE_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_TE_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_TE::Command Type */ + + +#define GEN11_3DSTATE_TE_CommandType_bits 3 +#define GEN10_3DSTATE_TE_CommandType_bits 3 +#define GEN9_3DSTATE_TE_CommandType_bits 3 +#define GEN8_3DSTATE_TE_CommandType_bits 3 +#define GEN75_3DSTATE_TE_CommandType_bits 3 +#define GEN7_3DSTATE_TE_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_TE_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_TE_CommandType_start 29 +#define GEN10_3DSTATE_TE_CommandType_start 29 +#define GEN9_3DSTATE_TE_CommandType_start 29 +#define GEN8_3DSTATE_TE_CommandType_start 29 +#define GEN75_3DSTATE_TE_CommandType_start 29 +#define GEN7_3DSTATE_TE_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_TE_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_TE::DWord Length */ + + +#define GEN11_3DSTATE_TE_DWordLength_bits 8 +#define GEN10_3DSTATE_TE_DWordLength_bits 8 +#define GEN9_3DSTATE_TE_DWordLength_bits 8 +#define GEN8_3DSTATE_TE_DWordLength_bits 8 +#define GEN75_3DSTATE_TE_DWordLength_bits 8 +#define GEN7_3DSTATE_TE_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_TE_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_TE_DWordLength_start 0 +#define GEN10_3DSTATE_TE_DWordLength_start 0 +#define GEN9_3DSTATE_TE_DWordLength_start 0 +#define GEN8_3DSTATE_TE_DWordLength_start 0 +#define GEN75_3DSTATE_TE_DWordLength_start 0 +#define GEN7_3DSTATE_TE_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_TE_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_TE::Maximum Tessellation Factor Not Odd */ + + +#define GEN11_3DSTATE_TE_MaximumTessellationFactorNotOdd_bits 32 +#define GEN10_3DSTATE_TE_MaximumTessellationFactorNotOdd_bits 32 +#define GEN9_3DSTATE_TE_MaximumTessellationFactorNotOdd_bits 32 +#define GEN8_3DSTATE_TE_MaximumTessellationFactorNotOdd_bits 32 +#define GEN75_3DSTATE_TE_MaximumTessellationFactorNotOdd_bits 32 +#define GEN7_3DSTATE_TE_MaximumTessellationFactorNotOdd_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_TE_MaximumTessellationFactorNotOdd_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_TE_MaximumTessellationFactorNotOdd_start 96 +#define GEN10_3DSTATE_TE_MaximumTessellationFactorNotOdd_start 96 +#define GEN9_3DSTATE_TE_MaximumTessellationFactorNotOdd_start 96 +#define GEN8_3DSTATE_TE_MaximumTessellationFactorNotOdd_start 96 +#define GEN75_3DSTATE_TE_MaximumTessellationFactorNotOdd_start 96 +#define GEN7_3DSTATE_TE_MaximumTessellationFactorNotOdd_start 96 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_TE_MaximumTessellationFactorNotOdd_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 96; + case 10: return 96; + case 9: return 96; + case 8: return 96; + case 7: + if (devinfo->is_haswell) { + return 96; + } else { + return 96; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_TE::Maximum Tessellation Factor Odd */ + + +#define GEN11_3DSTATE_TE_MaximumTessellationFactorOdd_bits 32 +#define GEN10_3DSTATE_TE_MaximumTessellationFactorOdd_bits 32 +#define GEN9_3DSTATE_TE_MaximumTessellationFactorOdd_bits 32 +#define GEN8_3DSTATE_TE_MaximumTessellationFactorOdd_bits 32 +#define GEN75_3DSTATE_TE_MaximumTessellationFactorOdd_bits 32 +#define GEN7_3DSTATE_TE_MaximumTessellationFactorOdd_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_TE_MaximumTessellationFactorOdd_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_TE_MaximumTessellationFactorOdd_start 64 +#define GEN10_3DSTATE_TE_MaximumTessellationFactorOdd_start 64 +#define GEN9_3DSTATE_TE_MaximumTessellationFactorOdd_start 64 +#define GEN8_3DSTATE_TE_MaximumTessellationFactorOdd_start 64 +#define GEN75_3DSTATE_TE_MaximumTessellationFactorOdd_start 64 +#define GEN7_3DSTATE_TE_MaximumTessellationFactorOdd_start 64 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_TE_MaximumTessellationFactorOdd_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_TE::Output Topology */ + + +#define GEN11_3DSTATE_TE_OutputTopology_bits 2 +#define GEN10_3DSTATE_TE_OutputTopology_bits 2 +#define GEN9_3DSTATE_TE_OutputTopology_bits 2 +#define GEN8_3DSTATE_TE_OutputTopology_bits 2 +#define GEN75_3DSTATE_TE_OutputTopology_bits 2 +#define GEN7_3DSTATE_TE_OutputTopology_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_TE_OutputTopology_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_TE_OutputTopology_start 40 +#define GEN10_3DSTATE_TE_OutputTopology_start 40 +#define GEN9_3DSTATE_TE_OutputTopology_start 40 +#define GEN8_3DSTATE_TE_OutputTopology_start 40 +#define GEN75_3DSTATE_TE_OutputTopology_start 40 +#define GEN7_3DSTATE_TE_OutputTopology_start 40 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_TE_OutputTopology_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 40; + case 10: return 40; + case 9: return 40; + case 8: return 40; + case 7: + if (devinfo->is_haswell) { + return 40; + } else { + return 40; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_TE::Partitioning */ + + +#define GEN11_3DSTATE_TE_Partitioning_bits 2 +#define GEN10_3DSTATE_TE_Partitioning_bits 2 +#define GEN9_3DSTATE_TE_Partitioning_bits 2 +#define GEN8_3DSTATE_TE_Partitioning_bits 2 +#define GEN75_3DSTATE_TE_Partitioning_bits 2 +#define GEN7_3DSTATE_TE_Partitioning_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_TE_Partitioning_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_TE_Partitioning_start 44 +#define GEN10_3DSTATE_TE_Partitioning_start 44 +#define GEN9_3DSTATE_TE_Partitioning_start 44 +#define GEN8_3DSTATE_TE_Partitioning_start 44 +#define GEN75_3DSTATE_TE_Partitioning_start 44 +#define GEN7_3DSTATE_TE_Partitioning_start 44 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_TE_Partitioning_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 44; + case 10: return 44; + case 9: return 44; + case 8: return 44; + case 7: + if (devinfo->is_haswell) { + return 44; + } else { + return 44; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_TE::TE Domain */ + + +#define GEN11_3DSTATE_TE_TEDomain_bits 2 +#define GEN10_3DSTATE_TE_TEDomain_bits 2 +#define GEN9_3DSTATE_TE_TEDomain_bits 2 +#define GEN8_3DSTATE_TE_TEDomain_bits 2 +#define GEN75_3DSTATE_TE_TEDomain_bits 2 +#define GEN7_3DSTATE_TE_TEDomain_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_TE_TEDomain_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_TE_TEDomain_start 36 +#define GEN10_3DSTATE_TE_TEDomain_start 36 +#define GEN9_3DSTATE_TE_TEDomain_start 36 +#define GEN8_3DSTATE_TE_TEDomain_start 36 +#define GEN75_3DSTATE_TE_TEDomain_start 36 +#define GEN7_3DSTATE_TE_TEDomain_start 36 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_TE_TEDomain_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 36; + case 10: return 36; + case 9: return 36; + case 8: return 36; + case 7: + if (devinfo->is_haswell) { + return 36; + } else { + return 36; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_TE::TE Enable */ + + +#define GEN11_3DSTATE_TE_TEEnable_bits 1 +#define GEN10_3DSTATE_TE_TEEnable_bits 1 +#define GEN9_3DSTATE_TE_TEEnable_bits 1 +#define GEN8_3DSTATE_TE_TEEnable_bits 1 +#define GEN75_3DSTATE_TE_TEEnable_bits 1 +#define GEN7_3DSTATE_TE_TEEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_TE_TEEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_TE_TEEnable_start 32 +#define GEN10_3DSTATE_TE_TEEnable_start 32 +#define GEN9_3DSTATE_TE_TEEnable_start 32 +#define GEN8_3DSTATE_TE_TEEnable_start 32 +#define GEN75_3DSTATE_TE_TEEnable_start 32 +#define GEN7_3DSTATE_TE_TEEnable_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_TE_TEEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_TE::TE Mode */ + + +#define GEN11_3DSTATE_TE_TEMode_bits 2 +#define GEN10_3DSTATE_TE_TEMode_bits 2 +#define GEN9_3DSTATE_TE_TEMode_bits 2 +#define GEN8_3DSTATE_TE_TEMode_bits 2 +#define GEN75_3DSTATE_TE_TEMode_bits 2 +#define GEN7_3DSTATE_TE_TEMode_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_TE_TEMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_TE_TEMode_start 33 +#define GEN10_3DSTATE_TE_TEMode_start 33 +#define GEN9_3DSTATE_TE_TEMode_start 33 +#define GEN8_3DSTATE_TE_TEMode_start 33 +#define GEN75_3DSTATE_TE_TEMode_start 33 +#define GEN7_3DSTATE_TE_TEMode_start 33 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_TE_TEMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 33; + case 10: return 33; + case 9: return 33; + case 8: return 33; + case 7: + if (devinfo->is_haswell) { + return 33; + } else { + return 33; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB */ + + +#define GEN6_3DSTATE_URB_length 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB::3D Command Opcode */ + + +#define GEN6_3DSTATE_URB_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_URB_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 24; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB::3D Command Sub Opcode */ + + +#define GEN6_3DSTATE_URB_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_URB_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB::Command SubType */ + + +#define GEN6_3DSTATE_URB_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_URB_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB::Command Type */ + + +#define GEN6_3DSTATE_URB_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_URB_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB::DWord Length */ + + +#define GEN6_3DSTATE_URB_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_URB_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB::GS Number of URB Entries */ + + +#define GEN6_3DSTATE_URB_GSNumberofURBEntries_bits 10 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_GSNumberofURBEntries_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 10; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_URB_GSNumberofURBEntries_start 72 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_GSNumberofURBEntries_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 72; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB::GS URB Entry Allocation Size */ + + +#define GEN6_3DSTATE_URB_GSURBEntryAllocationSize_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_GSURBEntryAllocationSize_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_URB_GSURBEntryAllocationSize_start 64 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_GSURBEntryAllocationSize_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 64; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB::VS Number of URB Entries */ + + +#define GEN6_3DSTATE_URB_VSNumberofURBEntries_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_VSNumberofURBEntries_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_URB_VSNumberofURBEntries_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_VSNumberofURBEntries_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB::VS URB Entry Allocation Size */ + + +#define GEN6_3DSTATE_URB_VSURBEntryAllocationSize_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_VSURBEntryAllocationSize_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_URB_VSURBEntryAllocationSize_start 48 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_VSURBEntryAllocationSize_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 48; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_CLEAR */ + + +#define GEN11_3DSTATE_URB_CLEAR_length 2 +#define GEN10_3DSTATE_URB_CLEAR_length 2 +#define GEN9_3DSTATE_URB_CLEAR_length 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_CLEAR_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_CLEAR::3D Command Opcode */ + + +#define GEN11_3DSTATE_URB_CLEAR_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_URB_CLEAR_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_URB_CLEAR_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_CLEAR_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_CLEAR_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_URB_CLEAR_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_URB_CLEAR_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_CLEAR_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_CLEAR::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_URB_CLEAR_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_URB_CLEAR_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_URB_CLEAR_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_CLEAR_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_CLEAR_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_URB_CLEAR_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_URB_CLEAR_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_CLEAR_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_CLEAR::Command SubType */ + + +#define GEN11_3DSTATE_URB_CLEAR_CommandSubType_bits 2 +#define GEN10_3DSTATE_URB_CLEAR_CommandSubType_bits 2 +#define GEN9_3DSTATE_URB_CLEAR_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_CLEAR_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_CLEAR_CommandSubType_start 27 +#define GEN10_3DSTATE_URB_CLEAR_CommandSubType_start 27 +#define GEN9_3DSTATE_URB_CLEAR_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_CLEAR_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_CLEAR::Command Type */ + + +#define GEN11_3DSTATE_URB_CLEAR_CommandType_bits 3 +#define GEN10_3DSTATE_URB_CLEAR_CommandType_bits 3 +#define GEN9_3DSTATE_URB_CLEAR_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_CLEAR_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_CLEAR_CommandType_start 29 +#define GEN10_3DSTATE_URB_CLEAR_CommandType_start 29 +#define GEN9_3DSTATE_URB_CLEAR_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_CLEAR_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_CLEAR::DWord Length */ + + +#define GEN11_3DSTATE_URB_CLEAR_DWordLength_bits 8 +#define GEN10_3DSTATE_URB_CLEAR_DWordLength_bits 8 +#define GEN9_3DSTATE_URB_CLEAR_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_CLEAR_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_CLEAR_DWordLength_start 0 +#define GEN10_3DSTATE_URB_CLEAR_DWordLength_start 0 +#define GEN9_3DSTATE_URB_CLEAR_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_CLEAR_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_CLEAR::URB Address */ + + +#define GEN11_3DSTATE_URB_CLEAR_URBAddress_bits 15 +#define GEN10_3DSTATE_URB_CLEAR_URBAddress_bits 15 +#define GEN9_3DSTATE_URB_CLEAR_URBAddress_bits 15 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_CLEAR_URBAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 15; + case 10: return 15; + case 9: return 15; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_CLEAR_URBAddress_start 32 +#define GEN10_3DSTATE_URB_CLEAR_URBAddress_start 32 +#define GEN9_3DSTATE_URB_CLEAR_URBAddress_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_CLEAR_URBAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_CLEAR::URB Clear Length */ + + +#define GEN11_3DSTATE_URB_CLEAR_URBClearLength_bits 14 +#define GEN10_3DSTATE_URB_CLEAR_URBClearLength_bits 14 +#define GEN9_3DSTATE_URB_CLEAR_URBClearLength_bits 14 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_CLEAR_URBClearLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 14; + case 10: return 14; + case 9: return 14; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_CLEAR_URBClearLength_start 48 +#define GEN10_3DSTATE_URB_CLEAR_URBClearLength_start 48 +#define GEN9_3DSTATE_URB_CLEAR_URBClearLength_start 48 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_CLEAR_URBClearLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_DS */ + + +#define GEN11_3DSTATE_URB_DS_length 2 +#define GEN10_3DSTATE_URB_DS_length 2 +#define GEN9_3DSTATE_URB_DS_length 2 +#define GEN8_3DSTATE_URB_DS_length 2 +#define GEN75_3DSTATE_URB_DS_length 2 +#define GEN7_3DSTATE_URB_DS_length 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_DS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_DS::3D Command Opcode */ + + +#define GEN11_3DSTATE_URB_DS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_URB_DS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_URB_DS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_URB_DS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_URB_DS_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_URB_DS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_DS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_DS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_URB_DS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_URB_DS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_URB_DS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_URB_DS_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_URB_DS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_DS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_DS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_URB_DS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_URB_DS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_URB_DS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_URB_DS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_URB_DS_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_URB_DS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_DS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_DS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_URB_DS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_URB_DS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_URB_DS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_URB_DS_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_URB_DS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_DS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_DS::Command SubType */ + + +#define GEN11_3DSTATE_URB_DS_CommandSubType_bits 2 +#define GEN10_3DSTATE_URB_DS_CommandSubType_bits 2 +#define GEN9_3DSTATE_URB_DS_CommandSubType_bits 2 +#define GEN8_3DSTATE_URB_DS_CommandSubType_bits 2 +#define GEN75_3DSTATE_URB_DS_CommandSubType_bits 2 +#define GEN7_3DSTATE_URB_DS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_DS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_DS_CommandSubType_start 27 +#define GEN10_3DSTATE_URB_DS_CommandSubType_start 27 +#define GEN9_3DSTATE_URB_DS_CommandSubType_start 27 +#define GEN8_3DSTATE_URB_DS_CommandSubType_start 27 +#define GEN75_3DSTATE_URB_DS_CommandSubType_start 27 +#define GEN7_3DSTATE_URB_DS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_DS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_DS::Command Type */ + + +#define GEN11_3DSTATE_URB_DS_CommandType_bits 3 +#define GEN10_3DSTATE_URB_DS_CommandType_bits 3 +#define GEN9_3DSTATE_URB_DS_CommandType_bits 3 +#define GEN8_3DSTATE_URB_DS_CommandType_bits 3 +#define GEN75_3DSTATE_URB_DS_CommandType_bits 3 +#define GEN7_3DSTATE_URB_DS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_DS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_DS_CommandType_start 29 +#define GEN10_3DSTATE_URB_DS_CommandType_start 29 +#define GEN9_3DSTATE_URB_DS_CommandType_start 29 +#define GEN8_3DSTATE_URB_DS_CommandType_start 29 +#define GEN75_3DSTATE_URB_DS_CommandType_start 29 +#define GEN7_3DSTATE_URB_DS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_DS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_DS::DS Number of URB Entries */ + + +#define GEN11_3DSTATE_URB_DS_DSNumberofURBEntries_bits 16 +#define GEN10_3DSTATE_URB_DS_DSNumberofURBEntries_bits 16 +#define GEN9_3DSTATE_URB_DS_DSNumberofURBEntries_bits 16 +#define GEN8_3DSTATE_URB_DS_DSNumberofURBEntries_bits 16 +#define GEN75_3DSTATE_URB_DS_DSNumberofURBEntries_bits 16 +#define GEN7_3DSTATE_URB_DS_DSNumberofURBEntries_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_DS_DSNumberofURBEntries_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_DS_DSNumberofURBEntries_start 32 +#define GEN10_3DSTATE_URB_DS_DSNumberofURBEntries_start 32 +#define GEN9_3DSTATE_URB_DS_DSNumberofURBEntries_start 32 +#define GEN8_3DSTATE_URB_DS_DSNumberofURBEntries_start 32 +#define GEN75_3DSTATE_URB_DS_DSNumberofURBEntries_start 32 +#define GEN7_3DSTATE_URB_DS_DSNumberofURBEntries_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_DS_DSNumberofURBEntries_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_DS::DS URB Entry Allocation Size */ + + +#define GEN11_3DSTATE_URB_DS_DSURBEntryAllocationSize_bits 9 +#define GEN10_3DSTATE_URB_DS_DSURBEntryAllocationSize_bits 9 +#define GEN9_3DSTATE_URB_DS_DSURBEntryAllocationSize_bits 9 +#define GEN8_3DSTATE_URB_DS_DSURBEntryAllocationSize_bits 9 +#define GEN75_3DSTATE_URB_DS_DSURBEntryAllocationSize_bits 9 +#define GEN7_3DSTATE_URB_DS_DSURBEntryAllocationSize_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_DS_DSURBEntryAllocationSize_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 9; + case 10: return 9; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 9; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_DS_DSURBEntryAllocationSize_start 48 +#define GEN10_3DSTATE_URB_DS_DSURBEntryAllocationSize_start 48 +#define GEN9_3DSTATE_URB_DS_DSURBEntryAllocationSize_start 48 +#define GEN8_3DSTATE_URB_DS_DSURBEntryAllocationSize_start 48 +#define GEN75_3DSTATE_URB_DS_DSURBEntryAllocationSize_start 48 +#define GEN7_3DSTATE_URB_DS_DSURBEntryAllocationSize_start 48 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_DS_DSURBEntryAllocationSize_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 48; + case 7: + if (devinfo->is_haswell) { + return 48; + } else { + return 48; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_DS::DS URB Starting Address */ + + +#define GEN11_3DSTATE_URB_DS_DSURBStartingAddress_bits 7 +#define GEN10_3DSTATE_URB_DS_DSURBStartingAddress_bits 7 +#define GEN9_3DSTATE_URB_DS_DSURBStartingAddress_bits 7 +#define GEN8_3DSTATE_URB_DS_DSURBStartingAddress_bits 7 +#define GEN75_3DSTATE_URB_DS_DSURBStartingAddress_bits 6 +#define GEN7_3DSTATE_URB_DS_DSURBStartingAddress_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_DS_DSURBStartingAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 5; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_DS_DSURBStartingAddress_start 57 +#define GEN10_3DSTATE_URB_DS_DSURBStartingAddress_start 57 +#define GEN9_3DSTATE_URB_DS_DSURBStartingAddress_start 57 +#define GEN8_3DSTATE_URB_DS_DSURBStartingAddress_start 57 +#define GEN75_3DSTATE_URB_DS_DSURBStartingAddress_start 57 +#define GEN7_3DSTATE_URB_DS_DSURBStartingAddress_start 57 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_DS_DSURBStartingAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 57; + case 10: return 57; + case 9: return 57; + case 8: return 57; + case 7: + if (devinfo->is_haswell) { + return 57; + } else { + return 57; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_DS::DWord Length */ + + +#define GEN11_3DSTATE_URB_DS_DWordLength_bits 8 +#define GEN10_3DSTATE_URB_DS_DWordLength_bits 8 +#define GEN9_3DSTATE_URB_DS_DWordLength_bits 8 +#define GEN8_3DSTATE_URB_DS_DWordLength_bits 8 +#define GEN75_3DSTATE_URB_DS_DWordLength_bits 8 +#define GEN7_3DSTATE_URB_DS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_DS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_DS_DWordLength_start 0 +#define GEN10_3DSTATE_URB_DS_DWordLength_start 0 +#define GEN9_3DSTATE_URB_DS_DWordLength_start 0 +#define GEN8_3DSTATE_URB_DS_DWordLength_start 0 +#define GEN75_3DSTATE_URB_DS_DWordLength_start 0 +#define GEN7_3DSTATE_URB_DS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_DS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_GS */ + + +#define GEN11_3DSTATE_URB_GS_length 2 +#define GEN10_3DSTATE_URB_GS_length 2 +#define GEN9_3DSTATE_URB_GS_length 2 +#define GEN8_3DSTATE_URB_GS_length 2 +#define GEN75_3DSTATE_URB_GS_length 2 +#define GEN7_3DSTATE_URB_GS_length 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_GS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_GS::3D Command Opcode */ + + +#define GEN11_3DSTATE_URB_GS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_URB_GS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_URB_GS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_URB_GS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_URB_GS_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_URB_GS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_GS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_GS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_URB_GS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_URB_GS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_URB_GS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_URB_GS_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_URB_GS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_GS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_GS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_URB_GS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_URB_GS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_URB_GS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_URB_GS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_URB_GS_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_URB_GS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_GS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_GS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_URB_GS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_URB_GS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_URB_GS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_URB_GS_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_URB_GS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_GS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_GS::Command SubType */ + + +#define GEN11_3DSTATE_URB_GS_CommandSubType_bits 2 +#define GEN10_3DSTATE_URB_GS_CommandSubType_bits 2 +#define GEN9_3DSTATE_URB_GS_CommandSubType_bits 2 +#define GEN8_3DSTATE_URB_GS_CommandSubType_bits 2 +#define GEN75_3DSTATE_URB_GS_CommandSubType_bits 2 +#define GEN7_3DSTATE_URB_GS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_GS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_GS_CommandSubType_start 27 +#define GEN10_3DSTATE_URB_GS_CommandSubType_start 27 +#define GEN9_3DSTATE_URB_GS_CommandSubType_start 27 +#define GEN8_3DSTATE_URB_GS_CommandSubType_start 27 +#define GEN75_3DSTATE_URB_GS_CommandSubType_start 27 +#define GEN7_3DSTATE_URB_GS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_GS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_GS::Command Type */ + + +#define GEN11_3DSTATE_URB_GS_CommandType_bits 3 +#define GEN10_3DSTATE_URB_GS_CommandType_bits 3 +#define GEN9_3DSTATE_URB_GS_CommandType_bits 3 +#define GEN8_3DSTATE_URB_GS_CommandType_bits 3 +#define GEN75_3DSTATE_URB_GS_CommandType_bits 3 +#define GEN7_3DSTATE_URB_GS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_GS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_GS_CommandType_start 29 +#define GEN10_3DSTATE_URB_GS_CommandType_start 29 +#define GEN9_3DSTATE_URB_GS_CommandType_start 29 +#define GEN8_3DSTATE_URB_GS_CommandType_start 29 +#define GEN75_3DSTATE_URB_GS_CommandType_start 29 +#define GEN7_3DSTATE_URB_GS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_GS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_GS::DWord Length */ + + +#define GEN11_3DSTATE_URB_GS_DWordLength_bits 8 +#define GEN10_3DSTATE_URB_GS_DWordLength_bits 8 +#define GEN9_3DSTATE_URB_GS_DWordLength_bits 8 +#define GEN8_3DSTATE_URB_GS_DWordLength_bits 8 +#define GEN75_3DSTATE_URB_GS_DWordLength_bits 8 +#define GEN7_3DSTATE_URB_GS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_GS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_GS_DWordLength_start 0 +#define GEN10_3DSTATE_URB_GS_DWordLength_start 0 +#define GEN9_3DSTATE_URB_GS_DWordLength_start 0 +#define GEN8_3DSTATE_URB_GS_DWordLength_start 0 +#define GEN75_3DSTATE_URB_GS_DWordLength_start 0 +#define GEN7_3DSTATE_URB_GS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_GS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_GS::GS Number of URB Entries */ + + +#define GEN11_3DSTATE_URB_GS_GSNumberofURBEntries_bits 16 +#define GEN10_3DSTATE_URB_GS_GSNumberofURBEntries_bits 16 +#define GEN9_3DSTATE_URB_GS_GSNumberofURBEntries_bits 16 +#define GEN8_3DSTATE_URB_GS_GSNumberofURBEntries_bits 16 +#define GEN75_3DSTATE_URB_GS_GSNumberofURBEntries_bits 16 +#define GEN7_3DSTATE_URB_GS_GSNumberofURBEntries_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_GS_GSNumberofURBEntries_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_GS_GSNumberofURBEntries_start 32 +#define GEN10_3DSTATE_URB_GS_GSNumberofURBEntries_start 32 +#define GEN9_3DSTATE_URB_GS_GSNumberofURBEntries_start 32 +#define GEN8_3DSTATE_URB_GS_GSNumberofURBEntries_start 32 +#define GEN75_3DSTATE_URB_GS_GSNumberofURBEntries_start 32 +#define GEN7_3DSTATE_URB_GS_GSNumberofURBEntries_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_GS_GSNumberofURBEntries_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_GS::GS URB Entry Allocation Size */ + + +#define GEN11_3DSTATE_URB_GS_GSURBEntryAllocationSize_bits 9 +#define GEN10_3DSTATE_URB_GS_GSURBEntryAllocationSize_bits 9 +#define GEN9_3DSTATE_URB_GS_GSURBEntryAllocationSize_bits 9 +#define GEN8_3DSTATE_URB_GS_GSURBEntryAllocationSize_bits 9 +#define GEN75_3DSTATE_URB_GS_GSURBEntryAllocationSize_bits 9 +#define GEN7_3DSTATE_URB_GS_GSURBEntryAllocationSize_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_GS_GSURBEntryAllocationSize_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 9; + case 10: return 9; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 9; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_GS_GSURBEntryAllocationSize_start 48 +#define GEN10_3DSTATE_URB_GS_GSURBEntryAllocationSize_start 48 +#define GEN9_3DSTATE_URB_GS_GSURBEntryAllocationSize_start 48 +#define GEN8_3DSTATE_URB_GS_GSURBEntryAllocationSize_start 48 +#define GEN75_3DSTATE_URB_GS_GSURBEntryAllocationSize_start 48 +#define GEN7_3DSTATE_URB_GS_GSURBEntryAllocationSize_start 48 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_GS_GSURBEntryAllocationSize_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 48; + case 7: + if (devinfo->is_haswell) { + return 48; + } else { + return 48; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_GS::GS URB Starting Address */ + + +#define GEN11_3DSTATE_URB_GS_GSURBStartingAddress_bits 7 +#define GEN10_3DSTATE_URB_GS_GSURBStartingAddress_bits 7 +#define GEN9_3DSTATE_URB_GS_GSURBStartingAddress_bits 7 +#define GEN8_3DSTATE_URB_GS_GSURBStartingAddress_bits 7 +#define GEN75_3DSTATE_URB_GS_GSURBStartingAddress_bits 6 +#define GEN7_3DSTATE_URB_GS_GSURBStartingAddress_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_GS_GSURBStartingAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 5; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_GS_GSURBStartingAddress_start 57 +#define GEN10_3DSTATE_URB_GS_GSURBStartingAddress_start 57 +#define GEN9_3DSTATE_URB_GS_GSURBStartingAddress_start 57 +#define GEN8_3DSTATE_URB_GS_GSURBStartingAddress_start 57 +#define GEN75_3DSTATE_URB_GS_GSURBStartingAddress_start 57 +#define GEN7_3DSTATE_URB_GS_GSURBStartingAddress_start 57 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_GS_GSURBStartingAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 57; + case 10: return 57; + case 9: return 57; + case 8: return 57; + case 7: + if (devinfo->is_haswell) { + return 57; + } else { + return 57; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_HS */ + + +#define GEN11_3DSTATE_URB_HS_length 2 +#define GEN10_3DSTATE_URB_HS_length 2 +#define GEN9_3DSTATE_URB_HS_length 2 +#define GEN8_3DSTATE_URB_HS_length 2 +#define GEN75_3DSTATE_URB_HS_length 2 +#define GEN7_3DSTATE_URB_HS_length 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_HS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_HS::3D Command Opcode */ + + +#define GEN11_3DSTATE_URB_HS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_URB_HS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_URB_HS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_URB_HS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_URB_HS_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_URB_HS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_HS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_HS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_URB_HS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_URB_HS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_URB_HS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_URB_HS_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_URB_HS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_HS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_HS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_URB_HS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_URB_HS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_URB_HS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_URB_HS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_URB_HS_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_URB_HS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_HS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_HS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_URB_HS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_URB_HS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_URB_HS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_URB_HS_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_URB_HS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_HS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_HS::Command SubType */ + + +#define GEN11_3DSTATE_URB_HS_CommandSubType_bits 2 +#define GEN10_3DSTATE_URB_HS_CommandSubType_bits 2 +#define GEN9_3DSTATE_URB_HS_CommandSubType_bits 2 +#define GEN8_3DSTATE_URB_HS_CommandSubType_bits 2 +#define GEN75_3DSTATE_URB_HS_CommandSubType_bits 2 +#define GEN7_3DSTATE_URB_HS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_HS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_HS_CommandSubType_start 27 +#define GEN10_3DSTATE_URB_HS_CommandSubType_start 27 +#define GEN9_3DSTATE_URB_HS_CommandSubType_start 27 +#define GEN8_3DSTATE_URB_HS_CommandSubType_start 27 +#define GEN75_3DSTATE_URB_HS_CommandSubType_start 27 +#define GEN7_3DSTATE_URB_HS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_HS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_HS::Command Type */ + + +#define GEN11_3DSTATE_URB_HS_CommandType_bits 3 +#define GEN10_3DSTATE_URB_HS_CommandType_bits 3 +#define GEN9_3DSTATE_URB_HS_CommandType_bits 3 +#define GEN8_3DSTATE_URB_HS_CommandType_bits 3 +#define GEN75_3DSTATE_URB_HS_CommandType_bits 3 +#define GEN7_3DSTATE_URB_HS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_HS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_HS_CommandType_start 29 +#define GEN10_3DSTATE_URB_HS_CommandType_start 29 +#define GEN9_3DSTATE_URB_HS_CommandType_start 29 +#define GEN8_3DSTATE_URB_HS_CommandType_start 29 +#define GEN75_3DSTATE_URB_HS_CommandType_start 29 +#define GEN7_3DSTATE_URB_HS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_HS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_HS::DWord Length */ + + +#define GEN11_3DSTATE_URB_HS_DWordLength_bits 8 +#define GEN10_3DSTATE_URB_HS_DWordLength_bits 8 +#define GEN9_3DSTATE_URB_HS_DWordLength_bits 8 +#define GEN8_3DSTATE_URB_HS_DWordLength_bits 8 +#define GEN75_3DSTATE_URB_HS_DWordLength_bits 8 +#define GEN7_3DSTATE_URB_HS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_HS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_HS_DWordLength_start 0 +#define GEN10_3DSTATE_URB_HS_DWordLength_start 0 +#define GEN9_3DSTATE_URB_HS_DWordLength_start 0 +#define GEN8_3DSTATE_URB_HS_DWordLength_start 0 +#define GEN75_3DSTATE_URB_HS_DWordLength_start 0 +#define GEN7_3DSTATE_URB_HS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_HS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_HS::HS Number of URB Entries */ + + +#define GEN11_3DSTATE_URB_HS_HSNumberofURBEntries_bits 16 +#define GEN10_3DSTATE_URB_HS_HSNumberofURBEntries_bits 16 +#define GEN9_3DSTATE_URB_HS_HSNumberofURBEntries_bits 16 +#define GEN8_3DSTATE_URB_HS_HSNumberofURBEntries_bits 16 +#define GEN75_3DSTATE_URB_HS_HSNumberofURBEntries_bits 16 +#define GEN7_3DSTATE_URB_HS_HSNumberofURBEntries_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_HS_HSNumberofURBEntries_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_HS_HSNumberofURBEntries_start 32 +#define GEN10_3DSTATE_URB_HS_HSNumberofURBEntries_start 32 +#define GEN9_3DSTATE_URB_HS_HSNumberofURBEntries_start 32 +#define GEN8_3DSTATE_URB_HS_HSNumberofURBEntries_start 32 +#define GEN75_3DSTATE_URB_HS_HSNumberofURBEntries_start 32 +#define GEN7_3DSTATE_URB_HS_HSNumberofURBEntries_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_HS_HSNumberofURBEntries_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_HS::HS URB Entry Allocation Size */ + + +#define GEN11_3DSTATE_URB_HS_HSURBEntryAllocationSize_bits 9 +#define GEN10_3DSTATE_URB_HS_HSURBEntryAllocationSize_bits 9 +#define GEN9_3DSTATE_URB_HS_HSURBEntryAllocationSize_bits 9 +#define GEN8_3DSTATE_URB_HS_HSURBEntryAllocationSize_bits 9 +#define GEN75_3DSTATE_URB_HS_HSURBEntryAllocationSize_bits 9 +#define GEN7_3DSTATE_URB_HS_HSURBEntryAllocationSize_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_HS_HSURBEntryAllocationSize_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 9; + case 10: return 9; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 9; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_HS_HSURBEntryAllocationSize_start 48 +#define GEN10_3DSTATE_URB_HS_HSURBEntryAllocationSize_start 48 +#define GEN9_3DSTATE_URB_HS_HSURBEntryAllocationSize_start 48 +#define GEN8_3DSTATE_URB_HS_HSURBEntryAllocationSize_start 48 +#define GEN75_3DSTATE_URB_HS_HSURBEntryAllocationSize_start 48 +#define GEN7_3DSTATE_URB_HS_HSURBEntryAllocationSize_start 48 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_HS_HSURBEntryAllocationSize_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 48; + case 7: + if (devinfo->is_haswell) { + return 48; + } else { + return 48; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_HS::HS URB Starting Address */ + + +#define GEN11_3DSTATE_URB_HS_HSURBStartingAddress_bits 7 +#define GEN10_3DSTATE_URB_HS_HSURBStartingAddress_bits 7 +#define GEN9_3DSTATE_URB_HS_HSURBStartingAddress_bits 7 +#define GEN8_3DSTATE_URB_HS_HSURBStartingAddress_bits 7 +#define GEN75_3DSTATE_URB_HS_HSURBStartingAddress_bits 6 +#define GEN7_3DSTATE_URB_HS_HSURBStartingAddress_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_HS_HSURBStartingAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 5; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_HS_HSURBStartingAddress_start 57 +#define GEN10_3DSTATE_URB_HS_HSURBStartingAddress_start 57 +#define GEN9_3DSTATE_URB_HS_HSURBStartingAddress_start 57 +#define GEN8_3DSTATE_URB_HS_HSURBStartingAddress_start 57 +#define GEN75_3DSTATE_URB_HS_HSURBStartingAddress_start 57 +#define GEN7_3DSTATE_URB_HS_HSURBStartingAddress_start 57 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_HS_HSURBStartingAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 57; + case 10: return 57; + case 9: return 57; + case 8: return 57; + case 7: + if (devinfo->is_haswell) { + return 57; + } else { + return 57; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_VS */ + + +#define GEN11_3DSTATE_URB_VS_length 2 +#define GEN10_3DSTATE_URB_VS_length 2 +#define GEN9_3DSTATE_URB_VS_length 2 +#define GEN8_3DSTATE_URB_VS_length 2 +#define GEN75_3DSTATE_URB_VS_length 2 +#define GEN7_3DSTATE_URB_VS_length 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_VS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_VS::3D Command Opcode */ + + +#define GEN11_3DSTATE_URB_VS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_URB_VS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_URB_VS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_URB_VS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_URB_VS_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_URB_VS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_VS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_VS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_URB_VS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_URB_VS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_URB_VS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_URB_VS_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_URB_VS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_VS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_VS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_URB_VS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_URB_VS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_URB_VS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_URB_VS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_URB_VS_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_URB_VS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_VS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_VS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_URB_VS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_URB_VS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_URB_VS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_URB_VS_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_URB_VS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_VS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_VS::Command SubType */ + + +#define GEN11_3DSTATE_URB_VS_CommandSubType_bits 2 +#define GEN10_3DSTATE_URB_VS_CommandSubType_bits 2 +#define GEN9_3DSTATE_URB_VS_CommandSubType_bits 2 +#define GEN8_3DSTATE_URB_VS_CommandSubType_bits 2 +#define GEN75_3DSTATE_URB_VS_CommandSubType_bits 2 +#define GEN7_3DSTATE_URB_VS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_VS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_VS_CommandSubType_start 27 +#define GEN10_3DSTATE_URB_VS_CommandSubType_start 27 +#define GEN9_3DSTATE_URB_VS_CommandSubType_start 27 +#define GEN8_3DSTATE_URB_VS_CommandSubType_start 27 +#define GEN75_3DSTATE_URB_VS_CommandSubType_start 27 +#define GEN7_3DSTATE_URB_VS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_VS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_VS::Command Type */ + + +#define GEN11_3DSTATE_URB_VS_CommandType_bits 3 +#define GEN10_3DSTATE_URB_VS_CommandType_bits 3 +#define GEN9_3DSTATE_URB_VS_CommandType_bits 3 +#define GEN8_3DSTATE_URB_VS_CommandType_bits 3 +#define GEN75_3DSTATE_URB_VS_CommandType_bits 3 +#define GEN7_3DSTATE_URB_VS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_VS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_VS_CommandType_start 29 +#define GEN10_3DSTATE_URB_VS_CommandType_start 29 +#define GEN9_3DSTATE_URB_VS_CommandType_start 29 +#define GEN8_3DSTATE_URB_VS_CommandType_start 29 +#define GEN75_3DSTATE_URB_VS_CommandType_start 29 +#define GEN7_3DSTATE_URB_VS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_VS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_VS::DWord Length */ + + +#define GEN11_3DSTATE_URB_VS_DWordLength_bits 8 +#define GEN10_3DSTATE_URB_VS_DWordLength_bits 8 +#define GEN9_3DSTATE_URB_VS_DWordLength_bits 8 +#define GEN8_3DSTATE_URB_VS_DWordLength_bits 8 +#define GEN75_3DSTATE_URB_VS_DWordLength_bits 8 +#define GEN7_3DSTATE_URB_VS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_VS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_VS_DWordLength_start 0 +#define GEN10_3DSTATE_URB_VS_DWordLength_start 0 +#define GEN9_3DSTATE_URB_VS_DWordLength_start 0 +#define GEN8_3DSTATE_URB_VS_DWordLength_start 0 +#define GEN75_3DSTATE_URB_VS_DWordLength_start 0 +#define GEN7_3DSTATE_URB_VS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_VS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_VS::VS Number of URB Entries */ + + +#define GEN11_3DSTATE_URB_VS_VSNumberofURBEntries_bits 16 +#define GEN10_3DSTATE_URB_VS_VSNumberofURBEntries_bits 16 +#define GEN9_3DSTATE_URB_VS_VSNumberofURBEntries_bits 16 +#define GEN8_3DSTATE_URB_VS_VSNumberofURBEntries_bits 16 +#define GEN75_3DSTATE_URB_VS_VSNumberofURBEntries_bits 16 +#define GEN7_3DSTATE_URB_VS_VSNumberofURBEntries_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_VS_VSNumberofURBEntries_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_VS_VSNumberofURBEntries_start 32 +#define GEN10_3DSTATE_URB_VS_VSNumberofURBEntries_start 32 +#define GEN9_3DSTATE_URB_VS_VSNumberofURBEntries_start 32 +#define GEN8_3DSTATE_URB_VS_VSNumberofURBEntries_start 32 +#define GEN75_3DSTATE_URB_VS_VSNumberofURBEntries_start 32 +#define GEN7_3DSTATE_URB_VS_VSNumberofURBEntries_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_VS_VSNumberofURBEntries_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_VS::VS URB Entry Allocation Size */ + + +#define GEN11_3DSTATE_URB_VS_VSURBEntryAllocationSize_bits 9 +#define GEN10_3DSTATE_URB_VS_VSURBEntryAllocationSize_bits 9 +#define GEN9_3DSTATE_URB_VS_VSURBEntryAllocationSize_bits 9 +#define GEN8_3DSTATE_URB_VS_VSURBEntryAllocationSize_bits 9 +#define GEN75_3DSTATE_URB_VS_VSURBEntryAllocationSize_bits 9 +#define GEN7_3DSTATE_URB_VS_VSURBEntryAllocationSize_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_VS_VSURBEntryAllocationSize_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 9; + case 10: return 9; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 9; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_VS_VSURBEntryAllocationSize_start 48 +#define GEN10_3DSTATE_URB_VS_VSURBEntryAllocationSize_start 48 +#define GEN9_3DSTATE_URB_VS_VSURBEntryAllocationSize_start 48 +#define GEN8_3DSTATE_URB_VS_VSURBEntryAllocationSize_start 48 +#define GEN75_3DSTATE_URB_VS_VSURBEntryAllocationSize_start 48 +#define GEN7_3DSTATE_URB_VS_VSURBEntryAllocationSize_start 48 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_VS_VSURBEntryAllocationSize_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 48; + case 7: + if (devinfo->is_haswell) { + return 48; + } else { + return 48; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_URB_VS::VS URB Starting Address */ + + +#define GEN11_3DSTATE_URB_VS_VSURBStartingAddress_bits 7 +#define GEN10_3DSTATE_URB_VS_VSURBStartingAddress_bits 7 +#define GEN9_3DSTATE_URB_VS_VSURBStartingAddress_bits 7 +#define GEN8_3DSTATE_URB_VS_VSURBStartingAddress_bits 7 +#define GEN75_3DSTATE_URB_VS_VSURBStartingAddress_bits 6 +#define GEN7_3DSTATE_URB_VS_VSURBStartingAddress_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_VS_VSURBStartingAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 5; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_URB_VS_VSURBStartingAddress_start 57 +#define GEN10_3DSTATE_URB_VS_VSURBStartingAddress_start 57 +#define GEN9_3DSTATE_URB_VS_VSURBStartingAddress_start 57 +#define GEN8_3DSTATE_URB_VS_VSURBStartingAddress_start 57 +#define GEN75_3DSTATE_URB_VS_VSURBStartingAddress_start 57 +#define GEN7_3DSTATE_URB_VS_VSURBStartingAddress_start 57 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_URB_VS_VSURBStartingAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 57; + case 10: return 57; + case 9: return 57; + case 8: return 57; + case 7: + if (devinfo->is_haswell) { + return 57; + } else { + return 57; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VERTEX_BUFFERS */ + + + + + +/* 3DSTATE_VERTEX_BUFFERS::3D Command Opcode */ + + +#define GEN11_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_bits 3 +#define GEN6_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_bits 3 +#define GEN5_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_bits 3 +#define GEN45_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_bits 3 +#define GEN4_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_start 24 +#define GEN6_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_start 24 +#define GEN5_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_start 24 +#define GEN45_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_start 24 +#define GEN4_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VERTEX_BUFFERS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 24; + case 4: + if (devinfo->is_g4x) { + return 24; + } else { + return 24; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VERTEX_BUFFERS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_bits 8 +#define GEN6_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_bits 8 +#define GEN5_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_bits 8 +#define GEN45_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_bits 8 +#define GEN4_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_start 16 +#define GEN6_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_start 16 +#define GEN5_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_start 16 +#define GEN45_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_start 16 +#define GEN4_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VERTEX_BUFFERS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VERTEX_BUFFERS::Command SubType */ + + +#define GEN11_3DSTATE_VERTEX_BUFFERS_CommandSubType_bits 2 +#define GEN10_3DSTATE_VERTEX_BUFFERS_CommandSubType_bits 2 +#define GEN9_3DSTATE_VERTEX_BUFFERS_CommandSubType_bits 2 +#define GEN8_3DSTATE_VERTEX_BUFFERS_CommandSubType_bits 2 +#define GEN75_3DSTATE_VERTEX_BUFFERS_CommandSubType_bits 2 +#define GEN7_3DSTATE_VERTEX_BUFFERS_CommandSubType_bits 2 +#define GEN6_3DSTATE_VERTEX_BUFFERS_CommandSubType_bits 2 +#define GEN5_3DSTATE_VERTEX_BUFFERS_CommandSubType_bits 2 +#define GEN45_3DSTATE_VERTEX_BUFFERS_CommandSubType_bits 2 +#define GEN4_3DSTATE_VERTEX_BUFFERS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VERTEX_BUFFERS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VERTEX_BUFFERS_CommandSubType_start 27 +#define GEN10_3DSTATE_VERTEX_BUFFERS_CommandSubType_start 27 +#define GEN9_3DSTATE_VERTEX_BUFFERS_CommandSubType_start 27 +#define GEN8_3DSTATE_VERTEX_BUFFERS_CommandSubType_start 27 +#define GEN75_3DSTATE_VERTEX_BUFFERS_CommandSubType_start 27 +#define GEN7_3DSTATE_VERTEX_BUFFERS_CommandSubType_start 27 +#define GEN6_3DSTATE_VERTEX_BUFFERS_CommandSubType_start 27 +#define GEN5_3DSTATE_VERTEX_BUFFERS_CommandSubType_start 27 +#define GEN45_3DSTATE_VERTEX_BUFFERS_CommandSubType_start 27 +#define GEN4_3DSTATE_VERTEX_BUFFERS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VERTEX_BUFFERS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VERTEX_BUFFERS::Command Type */ + + +#define GEN11_3DSTATE_VERTEX_BUFFERS_CommandType_bits 3 +#define GEN10_3DSTATE_VERTEX_BUFFERS_CommandType_bits 3 +#define GEN9_3DSTATE_VERTEX_BUFFERS_CommandType_bits 3 +#define GEN8_3DSTATE_VERTEX_BUFFERS_CommandType_bits 3 +#define GEN75_3DSTATE_VERTEX_BUFFERS_CommandType_bits 3 +#define GEN7_3DSTATE_VERTEX_BUFFERS_CommandType_bits 3 +#define GEN6_3DSTATE_VERTEX_BUFFERS_CommandType_bits 3 +#define GEN5_3DSTATE_VERTEX_BUFFERS_CommandType_bits 3 +#define GEN45_3DSTATE_VERTEX_BUFFERS_CommandType_bits 3 +#define GEN4_3DSTATE_VERTEX_BUFFERS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VERTEX_BUFFERS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VERTEX_BUFFERS_CommandType_start 29 +#define GEN10_3DSTATE_VERTEX_BUFFERS_CommandType_start 29 +#define GEN9_3DSTATE_VERTEX_BUFFERS_CommandType_start 29 +#define GEN8_3DSTATE_VERTEX_BUFFERS_CommandType_start 29 +#define GEN75_3DSTATE_VERTEX_BUFFERS_CommandType_start 29 +#define GEN7_3DSTATE_VERTEX_BUFFERS_CommandType_start 29 +#define GEN6_3DSTATE_VERTEX_BUFFERS_CommandType_start 29 +#define GEN5_3DSTATE_VERTEX_BUFFERS_CommandType_start 29 +#define GEN45_3DSTATE_VERTEX_BUFFERS_CommandType_start 29 +#define GEN4_3DSTATE_VERTEX_BUFFERS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VERTEX_BUFFERS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 29; + case 4: + if (devinfo->is_g4x) { + return 29; + } else { + return 29; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VERTEX_BUFFERS::DWord Length */ + + +#define GEN11_3DSTATE_VERTEX_BUFFERS_DWordLength_bits 8 +#define GEN10_3DSTATE_VERTEX_BUFFERS_DWordLength_bits 8 +#define GEN9_3DSTATE_VERTEX_BUFFERS_DWordLength_bits 8 +#define GEN8_3DSTATE_VERTEX_BUFFERS_DWordLength_bits 8 +#define GEN75_3DSTATE_VERTEX_BUFFERS_DWordLength_bits 8 +#define GEN7_3DSTATE_VERTEX_BUFFERS_DWordLength_bits 8 +#define GEN6_3DSTATE_VERTEX_BUFFERS_DWordLength_bits 8 +#define GEN5_3DSTATE_VERTEX_BUFFERS_DWordLength_bits 8 +#define GEN45_3DSTATE_VERTEX_BUFFERS_DWordLength_bits 8 +#define GEN4_3DSTATE_VERTEX_BUFFERS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VERTEX_BUFFERS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VERTEX_BUFFERS_DWordLength_start 0 +#define GEN10_3DSTATE_VERTEX_BUFFERS_DWordLength_start 0 +#define GEN9_3DSTATE_VERTEX_BUFFERS_DWordLength_start 0 +#define GEN8_3DSTATE_VERTEX_BUFFERS_DWordLength_start 0 +#define GEN75_3DSTATE_VERTEX_BUFFERS_DWordLength_start 0 +#define GEN7_3DSTATE_VERTEX_BUFFERS_DWordLength_start 0 +#define GEN6_3DSTATE_VERTEX_BUFFERS_DWordLength_start 0 +#define GEN5_3DSTATE_VERTEX_BUFFERS_DWordLength_start 0 +#define GEN45_3DSTATE_VERTEX_BUFFERS_DWordLength_start 0 +#define GEN4_3DSTATE_VERTEX_BUFFERS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VERTEX_BUFFERS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VERTEX_BUFFERS::Vertex Buffer State */ + + +#define GEN11_3DSTATE_VERTEX_BUFFERS_VertexBufferState_bits 128 +#define GEN10_3DSTATE_VERTEX_BUFFERS_VertexBufferState_bits 128 +#define GEN9_3DSTATE_VERTEX_BUFFERS_VertexBufferState_bits 128 +#define GEN8_3DSTATE_VERTEX_BUFFERS_VertexBufferState_bits 128 +#define GEN75_3DSTATE_VERTEX_BUFFERS_VertexBufferState_bits 128 +#define GEN7_3DSTATE_VERTEX_BUFFERS_VertexBufferState_bits 128 +#define GEN6_3DSTATE_VERTEX_BUFFERS_VertexBufferState_bits 128 +#define GEN5_3DSTATE_VERTEX_BUFFERS_VertexBufferState_bits 128 +#define GEN45_3DSTATE_VERTEX_BUFFERS_VertexBufferState_bits 128 +#define GEN4_3DSTATE_VERTEX_BUFFERS_VertexBufferState_bits 128 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VERTEX_BUFFERS_VertexBufferState_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 128; + case 10: return 128; + case 9: return 128; + case 8: return 128; + case 7: + if (devinfo->is_haswell) { + return 128; + } else { + return 128; + } + case 6: return 128; + case 5: return 128; + case 4: + if (devinfo->is_g4x) { + return 128; + } else { + return 128; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VERTEX_BUFFERS_VertexBufferState_start 0 +#define GEN10_3DSTATE_VERTEX_BUFFERS_VertexBufferState_start 0 +#define GEN9_3DSTATE_VERTEX_BUFFERS_VertexBufferState_start 0 +#define GEN8_3DSTATE_VERTEX_BUFFERS_VertexBufferState_start 0 +#define GEN75_3DSTATE_VERTEX_BUFFERS_VertexBufferState_start 0 +#define GEN7_3DSTATE_VERTEX_BUFFERS_VertexBufferState_start 0 +#define GEN6_3DSTATE_VERTEX_BUFFERS_VertexBufferState_start 0 +#define GEN5_3DSTATE_VERTEX_BUFFERS_VertexBufferState_start 0 +#define GEN45_3DSTATE_VERTEX_BUFFERS_VertexBufferState_start 0 +#define GEN4_3DSTATE_VERTEX_BUFFERS_VertexBufferState_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VERTEX_BUFFERS_VertexBufferState_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VERTEX_ELEMENTS */ + + + + + +/* 3DSTATE_VERTEX_ELEMENTS::3D Command Opcode */ + + +#define GEN11_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_bits 3 +#define GEN6_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_bits 3 +#define GEN5_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_bits 3 +#define GEN45_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_bits 3 +#define GEN4_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_start 24 +#define GEN6_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_start 24 +#define GEN5_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_start 24 +#define GEN45_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_start 24 +#define GEN4_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VERTEX_ELEMENTS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 24; + case 4: + if (devinfo->is_g4x) { + return 24; + } else { + return 24; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VERTEX_ELEMENTS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_bits 8 +#define GEN6_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_bits 8 +#define GEN5_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_bits 8 +#define GEN45_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_bits 8 +#define GEN4_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_start 16 +#define GEN6_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_start 16 +#define GEN5_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_start 16 +#define GEN45_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_start 16 +#define GEN4_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VERTEX_ELEMENTS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VERTEX_ELEMENTS::Command SubType */ + + +#define GEN11_3DSTATE_VERTEX_ELEMENTS_CommandSubType_bits 2 +#define GEN10_3DSTATE_VERTEX_ELEMENTS_CommandSubType_bits 2 +#define GEN9_3DSTATE_VERTEX_ELEMENTS_CommandSubType_bits 2 +#define GEN8_3DSTATE_VERTEX_ELEMENTS_CommandSubType_bits 2 +#define GEN75_3DSTATE_VERTEX_ELEMENTS_CommandSubType_bits 2 +#define GEN7_3DSTATE_VERTEX_ELEMENTS_CommandSubType_bits 2 +#define GEN6_3DSTATE_VERTEX_ELEMENTS_CommandSubType_bits 2 +#define GEN5_3DSTATE_VERTEX_ELEMENTS_CommandSubType_bits 2 +#define GEN45_3DSTATE_VERTEX_ELEMENTS_CommandSubType_bits 2 +#define GEN4_3DSTATE_VERTEX_ELEMENTS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VERTEX_ELEMENTS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VERTEX_ELEMENTS_CommandSubType_start 27 +#define GEN10_3DSTATE_VERTEX_ELEMENTS_CommandSubType_start 27 +#define GEN9_3DSTATE_VERTEX_ELEMENTS_CommandSubType_start 27 +#define GEN8_3DSTATE_VERTEX_ELEMENTS_CommandSubType_start 27 +#define GEN75_3DSTATE_VERTEX_ELEMENTS_CommandSubType_start 27 +#define GEN7_3DSTATE_VERTEX_ELEMENTS_CommandSubType_start 27 +#define GEN6_3DSTATE_VERTEX_ELEMENTS_CommandSubType_start 27 +#define GEN5_3DSTATE_VERTEX_ELEMENTS_CommandSubType_start 27 +#define GEN45_3DSTATE_VERTEX_ELEMENTS_CommandSubType_start 27 +#define GEN4_3DSTATE_VERTEX_ELEMENTS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VERTEX_ELEMENTS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VERTEX_ELEMENTS::Command Type */ + + +#define GEN11_3DSTATE_VERTEX_ELEMENTS_CommandType_bits 3 +#define GEN10_3DSTATE_VERTEX_ELEMENTS_CommandType_bits 3 +#define GEN9_3DSTATE_VERTEX_ELEMENTS_CommandType_bits 3 +#define GEN8_3DSTATE_VERTEX_ELEMENTS_CommandType_bits 3 +#define GEN75_3DSTATE_VERTEX_ELEMENTS_CommandType_bits 3 +#define GEN7_3DSTATE_VERTEX_ELEMENTS_CommandType_bits 3 +#define GEN6_3DSTATE_VERTEX_ELEMENTS_CommandType_bits 3 +#define GEN5_3DSTATE_VERTEX_ELEMENTS_CommandType_bits 3 +#define GEN45_3DSTATE_VERTEX_ELEMENTS_CommandType_bits 3 +#define GEN4_3DSTATE_VERTEX_ELEMENTS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VERTEX_ELEMENTS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VERTEX_ELEMENTS_CommandType_start 29 +#define GEN10_3DSTATE_VERTEX_ELEMENTS_CommandType_start 29 +#define GEN9_3DSTATE_VERTEX_ELEMENTS_CommandType_start 29 +#define GEN8_3DSTATE_VERTEX_ELEMENTS_CommandType_start 29 +#define GEN75_3DSTATE_VERTEX_ELEMENTS_CommandType_start 29 +#define GEN7_3DSTATE_VERTEX_ELEMENTS_CommandType_start 29 +#define GEN6_3DSTATE_VERTEX_ELEMENTS_CommandType_start 29 +#define GEN5_3DSTATE_VERTEX_ELEMENTS_CommandType_start 29 +#define GEN45_3DSTATE_VERTEX_ELEMENTS_CommandType_start 29 +#define GEN4_3DSTATE_VERTEX_ELEMENTS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VERTEX_ELEMENTS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 29; + case 4: + if (devinfo->is_g4x) { + return 29; + } else { + return 29; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VERTEX_ELEMENTS::DWord Length */ + + +#define GEN11_3DSTATE_VERTEX_ELEMENTS_DWordLength_bits 8 +#define GEN10_3DSTATE_VERTEX_ELEMENTS_DWordLength_bits 8 +#define GEN9_3DSTATE_VERTEX_ELEMENTS_DWordLength_bits 8 +#define GEN8_3DSTATE_VERTEX_ELEMENTS_DWordLength_bits 8 +#define GEN75_3DSTATE_VERTEX_ELEMENTS_DWordLength_bits 8 +#define GEN7_3DSTATE_VERTEX_ELEMENTS_DWordLength_bits 8 +#define GEN6_3DSTATE_VERTEX_ELEMENTS_DWordLength_bits 8 +#define GEN5_3DSTATE_VERTEX_ELEMENTS_DWordLength_bits 8 +#define GEN45_3DSTATE_VERTEX_ELEMENTS_DWordLength_bits 8 +#define GEN4_3DSTATE_VERTEX_ELEMENTS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VERTEX_ELEMENTS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VERTEX_ELEMENTS_DWordLength_start 0 +#define GEN10_3DSTATE_VERTEX_ELEMENTS_DWordLength_start 0 +#define GEN9_3DSTATE_VERTEX_ELEMENTS_DWordLength_start 0 +#define GEN8_3DSTATE_VERTEX_ELEMENTS_DWordLength_start 0 +#define GEN75_3DSTATE_VERTEX_ELEMENTS_DWordLength_start 0 +#define GEN7_3DSTATE_VERTEX_ELEMENTS_DWordLength_start 0 +#define GEN6_3DSTATE_VERTEX_ELEMENTS_DWordLength_start 0 +#define GEN5_3DSTATE_VERTEX_ELEMENTS_DWordLength_start 0 +#define GEN45_3DSTATE_VERTEX_ELEMENTS_DWordLength_start 0 +#define GEN4_3DSTATE_VERTEX_ELEMENTS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VERTEX_ELEMENTS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VERTEX_ELEMENTS::Element */ + + +#define GEN11_3DSTATE_VERTEX_ELEMENTS_Element_bits 64 +#define GEN10_3DSTATE_VERTEX_ELEMENTS_Element_bits 64 +#define GEN9_3DSTATE_VERTEX_ELEMENTS_Element_bits 64 +#define GEN8_3DSTATE_VERTEX_ELEMENTS_Element_bits 64 +#define GEN75_3DSTATE_VERTEX_ELEMENTS_Element_bits 64 +#define GEN7_3DSTATE_VERTEX_ELEMENTS_Element_bits 64 +#define GEN6_3DSTATE_VERTEX_ELEMENTS_Element_bits 64 +#define GEN5_3DSTATE_VERTEX_ELEMENTS_Element_bits 64 +#define GEN45_3DSTATE_VERTEX_ELEMENTS_Element_bits 64 +#define GEN4_3DSTATE_VERTEX_ELEMENTS_Element_bits 64 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VERTEX_ELEMENTS_Element_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 64; + case 5: return 64; + case 4: + if (devinfo->is_g4x) { + return 64; + } else { + return 64; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VERTEX_ELEMENTS_Element_start 0 +#define GEN10_3DSTATE_VERTEX_ELEMENTS_Element_start 0 +#define GEN9_3DSTATE_VERTEX_ELEMENTS_Element_start 0 +#define GEN8_3DSTATE_VERTEX_ELEMENTS_Element_start 0 +#define GEN75_3DSTATE_VERTEX_ELEMENTS_Element_start 0 +#define GEN7_3DSTATE_VERTEX_ELEMENTS_Element_start 0 +#define GEN6_3DSTATE_VERTEX_ELEMENTS_Element_start 0 +#define GEN5_3DSTATE_VERTEX_ELEMENTS_Element_start 0 +#define GEN45_3DSTATE_VERTEX_ELEMENTS_Element_start 0 +#define GEN4_3DSTATE_VERTEX_ELEMENTS_Element_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VERTEX_ELEMENTS_Element_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF */ + + +#define GEN11_3DSTATE_VF_length 2 +#define GEN10_3DSTATE_VF_length 2 +#define GEN9_3DSTATE_VF_length 2 +#define GEN8_3DSTATE_VF_length 2 +#define GEN75_3DSTATE_VF_length 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF::3D Command Opcode */ + + +#define GEN11_3DSTATE_VF_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_VF_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_VF_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_VF_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_VF_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_VF_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_VF_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_VF_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_VF_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_VF_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_VF_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_VF_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_VF_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_VF_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_VF_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_VF_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_VF_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_VF_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF::Command SubType */ + + +#define GEN11_3DSTATE_VF_CommandSubType_bits 2 +#define GEN10_3DSTATE_VF_CommandSubType_bits 2 +#define GEN9_3DSTATE_VF_CommandSubType_bits 2 +#define GEN8_3DSTATE_VF_CommandSubType_bits 2 +#define GEN75_3DSTATE_VF_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_CommandSubType_start 27 +#define GEN10_3DSTATE_VF_CommandSubType_start 27 +#define GEN9_3DSTATE_VF_CommandSubType_start 27 +#define GEN8_3DSTATE_VF_CommandSubType_start 27 +#define GEN75_3DSTATE_VF_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF::Command Type */ + + +#define GEN11_3DSTATE_VF_CommandType_bits 3 +#define GEN10_3DSTATE_VF_CommandType_bits 3 +#define GEN9_3DSTATE_VF_CommandType_bits 3 +#define GEN8_3DSTATE_VF_CommandType_bits 3 +#define GEN75_3DSTATE_VF_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_CommandType_start 29 +#define GEN10_3DSTATE_VF_CommandType_start 29 +#define GEN9_3DSTATE_VF_CommandType_start 29 +#define GEN8_3DSTATE_VF_CommandType_start 29 +#define GEN75_3DSTATE_VF_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF::Component Packing Enable */ + + +#define GEN11_3DSTATE_VF_ComponentPackingEnable_bits 1 +#define GEN10_3DSTATE_VF_ComponentPackingEnable_bits 1 +#define GEN9_3DSTATE_VF_ComponentPackingEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_ComponentPackingEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_ComponentPackingEnable_start 9 +#define GEN10_3DSTATE_VF_ComponentPackingEnable_start 9 +#define GEN9_3DSTATE_VF_ComponentPackingEnable_start 9 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_ComponentPackingEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 9; + case 10: return 9; + case 9: return 9; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF::Cut Index */ + + +#define GEN11_3DSTATE_VF_CutIndex_bits 32 +#define GEN10_3DSTATE_VF_CutIndex_bits 32 +#define GEN9_3DSTATE_VF_CutIndex_bits 32 +#define GEN8_3DSTATE_VF_CutIndex_bits 32 +#define GEN75_3DSTATE_VF_CutIndex_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_CutIndex_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_CutIndex_start 32 +#define GEN10_3DSTATE_VF_CutIndex_start 32 +#define GEN9_3DSTATE_VF_CutIndex_start 32 +#define GEN8_3DSTATE_VF_CutIndex_start 32 +#define GEN75_3DSTATE_VF_CutIndex_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_CutIndex_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF::DWord Length */ + + +#define GEN11_3DSTATE_VF_DWordLength_bits 8 +#define GEN10_3DSTATE_VF_DWordLength_bits 8 +#define GEN9_3DSTATE_VF_DWordLength_bits 8 +#define GEN8_3DSTATE_VF_DWordLength_bits 8 +#define GEN75_3DSTATE_VF_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_DWordLength_start 0 +#define GEN10_3DSTATE_VF_DWordLength_start 0 +#define GEN9_3DSTATE_VF_DWordLength_start 0 +#define GEN8_3DSTATE_VF_DWordLength_start 0 +#define GEN75_3DSTATE_VF_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF::Indexed Draw Cut Index Enable */ + + +#define GEN11_3DSTATE_VF_IndexedDrawCutIndexEnable_bits 1 +#define GEN10_3DSTATE_VF_IndexedDrawCutIndexEnable_bits 1 +#define GEN9_3DSTATE_VF_IndexedDrawCutIndexEnable_bits 1 +#define GEN8_3DSTATE_VF_IndexedDrawCutIndexEnable_bits 1 +#define GEN75_3DSTATE_VF_IndexedDrawCutIndexEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_IndexedDrawCutIndexEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_IndexedDrawCutIndexEnable_start 8 +#define GEN10_3DSTATE_VF_IndexedDrawCutIndexEnable_start 8 +#define GEN9_3DSTATE_VF_IndexedDrawCutIndexEnable_start 8 +#define GEN8_3DSTATE_VF_IndexedDrawCutIndexEnable_start 8 +#define GEN75_3DSTATE_VF_IndexedDrawCutIndexEnable_start 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_IndexedDrawCutIndexEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF::Sequential Draw Cut Index Enable */ + + +#define GEN11_3DSTATE_VF_SequentialDrawCutIndexEnable_bits 1 +#define GEN10_3DSTATE_VF_SequentialDrawCutIndexEnable_bits 1 +#define GEN9_3DSTATE_VF_SequentialDrawCutIndexEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SequentialDrawCutIndexEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_SequentialDrawCutIndexEnable_start 10 +#define GEN10_3DSTATE_VF_SequentialDrawCutIndexEnable_start 10 +#define GEN9_3DSTATE_VF_SequentialDrawCutIndexEnable_start 10 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SequentialDrawCutIndexEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 10; + case 10: return 10; + case 9: return 10; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF::VertexID Offset Enable */ + + +#define GEN11_3DSTATE_VF_VertexIDOffsetEnable_bits 1 +#define GEN10_3DSTATE_VF_VertexIDOffsetEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_VertexIDOffsetEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_VertexIDOffsetEnable_start 11 +#define GEN10_3DSTATE_VF_VertexIDOffsetEnable_start 11 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_VertexIDOffsetEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_COMPONENT_PACKING */ + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_length 5 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_length 5 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_length 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_COMPONENT_PACKING::3D Command Opcode */ + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_COMPONENT_PACKING::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_COMPONENT_PACKING::Command SubType */ + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_CommandSubType_bits 2 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_CommandSubType_bits 2 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_CommandSubType_start 27 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_CommandSubType_start 27 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_COMPONENT_PACKING::Command Type */ + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_CommandType_bits 3 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_CommandType_bits 3 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_CommandType_start 29 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_CommandType_start 29 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_COMPONENT_PACKING::DWord Length */ + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_DWordLength_bits 8 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_DWordLength_bits 8 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_DWordLength_start 0 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_DWordLength_start 0 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 00 Enables */ + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement00Enables_bits 4 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement00Enables_bits 4 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement00Enables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement00Enables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement00Enables_start 32 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement00Enables_start 32 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement00Enables_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement00Enables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 01 Enables */ + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement01Enables_bits 4 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement01Enables_bits 4 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement01Enables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement01Enables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement01Enables_start 36 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement01Enables_start 36 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement01Enables_start 36 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement01Enables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 36; + case 10: return 36; + case 9: return 36; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 02 Enables */ + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement02Enables_bits 4 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement02Enables_bits 4 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement02Enables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement02Enables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement02Enables_start 40 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement02Enables_start 40 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement02Enables_start 40 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement02Enables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 40; + case 10: return 40; + case 9: return 40; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 03 Enables */ + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement03Enables_bits 4 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement03Enables_bits 4 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement03Enables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement03Enables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement03Enables_start 44 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement03Enables_start 44 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement03Enables_start 44 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement03Enables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 44; + case 10: return 44; + case 9: return 44; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 04 Enables */ + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement04Enables_bits 4 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement04Enables_bits 4 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement04Enables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement04Enables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement04Enables_start 48 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement04Enables_start 48 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement04Enables_start 48 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement04Enables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 05 Enables */ + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement05Enables_bits 4 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement05Enables_bits 4 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement05Enables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement05Enables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement05Enables_start 52 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement05Enables_start 52 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement05Enables_start 52 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement05Enables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 52; + case 10: return 52; + case 9: return 52; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 06 Enables */ + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement06Enables_bits 4 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement06Enables_bits 4 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement06Enables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement06Enables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement06Enables_start 56 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement06Enables_start 56 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement06Enables_start 56 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement06Enables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 56; + case 10: return 56; + case 9: return 56; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 07 Enables */ + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement07Enables_bits 4 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement07Enables_bits 4 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement07Enables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement07Enables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement07Enables_start 60 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement07Enables_start 60 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement07Enables_start 60 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement07Enables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 60; + case 10: return 60; + case 9: return 60; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 08 Enables */ + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement08Enables_bits 4 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement08Enables_bits 4 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement08Enables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement08Enables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement08Enables_start 64 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement08Enables_start 64 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement08Enables_start 64 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement08Enables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 09 Enables */ + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement09Enables_bits 4 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement09Enables_bits 4 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement09Enables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement09Enables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement09Enables_start 68 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement09Enables_start 68 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement09Enables_start 68 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement09Enables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 68; + case 10: return 68; + case 9: return 68; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 10 Enables */ + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement10Enables_bits 4 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement10Enables_bits 4 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement10Enables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement10Enables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement10Enables_start 72 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement10Enables_start 72 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement10Enables_start 72 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement10Enables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 72; + case 10: return 72; + case 9: return 72; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 11 Enables */ + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement11Enables_bits 4 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement11Enables_bits 4 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement11Enables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement11Enables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement11Enables_start 76 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement11Enables_start 76 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement11Enables_start 76 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement11Enables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 76; + case 10: return 76; + case 9: return 76; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 12 Enables */ + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement12Enables_bits 4 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement12Enables_bits 4 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement12Enables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement12Enables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement12Enables_start 80 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement12Enables_start 80 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement12Enables_start 80 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement12Enables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 80; + case 10: return 80; + case 9: return 80; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 13 Enables */ + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement13Enables_bits 4 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement13Enables_bits 4 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement13Enables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement13Enables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement13Enables_start 84 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement13Enables_start 84 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement13Enables_start 84 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement13Enables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 84; + case 10: return 84; + case 9: return 84; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 14 Enables */ + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement14Enables_bits 4 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement14Enables_bits 4 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement14Enables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement14Enables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement14Enables_start 88 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement14Enables_start 88 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement14Enables_start 88 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement14Enables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 88; + case 10: return 88; + case 9: return 88; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 15 Enables */ + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement15Enables_bits 4 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement15Enables_bits 4 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement15Enables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement15Enables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement15Enables_start 92 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement15Enables_start 92 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement15Enables_start 92 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement15Enables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 92; + case 10: return 92; + case 9: return 92; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 16 Enables */ + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement16Enables_bits 4 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement16Enables_bits 4 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement16Enables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement16Enables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement16Enables_start 96 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement16Enables_start 96 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement16Enables_start 96 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement16Enables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 96; + case 10: return 96; + case 9: return 96; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 17 Enables */ + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement17Enables_bits 4 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement17Enables_bits 4 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement17Enables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement17Enables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement17Enables_start 100 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement17Enables_start 100 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement17Enables_start 100 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement17Enables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 100; + case 10: return 100; + case 9: return 100; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 18 Enables */ + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement18Enables_bits 4 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement18Enables_bits 4 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement18Enables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement18Enables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement18Enables_start 104 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement18Enables_start 104 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement18Enables_start 104 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement18Enables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 104; + case 10: return 104; + case 9: return 104; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 19 Enables */ + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement19Enables_bits 4 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement19Enables_bits 4 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement19Enables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement19Enables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement19Enables_start 108 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement19Enables_start 108 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement19Enables_start 108 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement19Enables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 108; + case 10: return 108; + case 9: return 108; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 20 Enables */ + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement20Enables_bits 4 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement20Enables_bits 4 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement20Enables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement20Enables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement20Enables_start 112 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement20Enables_start 112 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement20Enables_start 112 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement20Enables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 112; + case 10: return 112; + case 9: return 112; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 21 Enables */ + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement21Enables_bits 4 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement21Enables_bits 4 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement21Enables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement21Enables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement21Enables_start 116 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement21Enables_start 116 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement21Enables_start 116 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement21Enables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 116; + case 10: return 116; + case 9: return 116; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 22 Enables */ + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement22Enables_bits 4 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement22Enables_bits 4 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement22Enables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement22Enables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement22Enables_start 120 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement22Enables_start 120 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement22Enables_start 120 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement22Enables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 120; + case 10: return 120; + case 9: return 120; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 23 Enables */ + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement23Enables_bits 4 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement23Enables_bits 4 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement23Enables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement23Enables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement23Enables_start 124 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement23Enables_start 124 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement23Enables_start 124 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement23Enables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 124; + case 10: return 124; + case 9: return 124; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 24 Enables */ + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement24Enables_bits 4 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement24Enables_bits 4 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement24Enables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement24Enables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement24Enables_start 128 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement24Enables_start 128 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement24Enables_start 128 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement24Enables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 128; + case 10: return 128; + case 9: return 128; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 25 Enables */ + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement25Enables_bits 4 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement25Enables_bits 4 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement25Enables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement25Enables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement25Enables_start 132 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement25Enables_start 132 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement25Enables_start 132 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement25Enables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 132; + case 10: return 132; + case 9: return 132; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 26 Enables */ + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement26Enables_bits 4 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement26Enables_bits 4 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement26Enables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement26Enables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement26Enables_start 136 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement26Enables_start 136 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement26Enables_start 136 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement26Enables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 136; + case 10: return 136; + case 9: return 136; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 27 Enables */ + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement27Enables_bits 4 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement27Enables_bits 4 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement27Enables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement27Enables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement27Enables_start 140 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement27Enables_start 140 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement27Enables_start 140 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement27Enables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 140; + case 10: return 140; + case 9: return 140; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 28 Enables */ + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement28Enables_bits 4 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement28Enables_bits 4 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement28Enables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement28Enables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement28Enables_start 144 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement28Enables_start 144 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement28Enables_start 144 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement28Enables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 144; + case 10: return 144; + case 9: return 144; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 29 Enables */ + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement29Enables_bits 4 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement29Enables_bits 4 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement29Enables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement29Enables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement29Enables_start 148 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement29Enables_start 148 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement29Enables_start 148 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement29Enables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 148; + case 10: return 148; + case 9: return 148; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 30 Enables */ + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement30Enables_bits 4 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement30Enables_bits 4 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement30Enables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement30Enables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement30Enables_start 152 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement30Enables_start 152 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement30Enables_start 152 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement30Enables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 152; + case 10: return 152; + case 9: return 152; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_COMPONENT_PACKING::Vertex Element 31 Enables */ + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement31Enables_bits 4 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement31Enables_bits 4 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement31Enables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement31Enables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_COMPONENT_PACKING_VertexElement31Enables_start 156 +#define GEN10_3DSTATE_VF_COMPONENT_PACKING_VertexElement31Enables_start 156 +#define GEN9_3DSTATE_VF_COMPONENT_PACKING_VertexElement31Enables_start 156 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_COMPONENT_PACKING_VertexElement31Enables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 156; + case 10: return 156; + case 9: return 156; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_INSTANCING */ + + +#define GEN11_3DSTATE_VF_INSTANCING_length 3 +#define GEN10_3DSTATE_VF_INSTANCING_length 3 +#define GEN9_3DSTATE_VF_INSTANCING_length 3 +#define GEN8_3DSTATE_VF_INSTANCING_length 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_INSTANCING_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_INSTANCING::3D Command Opcode */ + + +#define GEN11_3DSTATE_VF_INSTANCING_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_VF_INSTANCING_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_VF_INSTANCING_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_VF_INSTANCING_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_INSTANCING_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_INSTANCING_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_VF_INSTANCING_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_VF_INSTANCING_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_VF_INSTANCING_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_INSTANCING_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_INSTANCING::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_VF_INSTANCING_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_VF_INSTANCING_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_VF_INSTANCING_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_VF_INSTANCING_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_INSTANCING_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_INSTANCING_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_VF_INSTANCING_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_VF_INSTANCING_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_VF_INSTANCING_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_INSTANCING_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_INSTANCING::Command SubType */ + + +#define GEN11_3DSTATE_VF_INSTANCING_CommandSubType_bits 2 +#define GEN10_3DSTATE_VF_INSTANCING_CommandSubType_bits 2 +#define GEN9_3DSTATE_VF_INSTANCING_CommandSubType_bits 2 +#define GEN8_3DSTATE_VF_INSTANCING_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_INSTANCING_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_INSTANCING_CommandSubType_start 27 +#define GEN10_3DSTATE_VF_INSTANCING_CommandSubType_start 27 +#define GEN9_3DSTATE_VF_INSTANCING_CommandSubType_start 27 +#define GEN8_3DSTATE_VF_INSTANCING_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_INSTANCING_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_INSTANCING::Command Type */ + + +#define GEN11_3DSTATE_VF_INSTANCING_CommandType_bits 3 +#define GEN10_3DSTATE_VF_INSTANCING_CommandType_bits 3 +#define GEN9_3DSTATE_VF_INSTANCING_CommandType_bits 3 +#define GEN8_3DSTATE_VF_INSTANCING_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_INSTANCING_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_INSTANCING_CommandType_start 29 +#define GEN10_3DSTATE_VF_INSTANCING_CommandType_start 29 +#define GEN9_3DSTATE_VF_INSTANCING_CommandType_start 29 +#define GEN8_3DSTATE_VF_INSTANCING_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_INSTANCING_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_INSTANCING::DWord Length */ + + +#define GEN11_3DSTATE_VF_INSTANCING_DWordLength_bits 8 +#define GEN10_3DSTATE_VF_INSTANCING_DWordLength_bits 8 +#define GEN9_3DSTATE_VF_INSTANCING_DWordLength_bits 8 +#define GEN8_3DSTATE_VF_INSTANCING_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_INSTANCING_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_INSTANCING_DWordLength_start 0 +#define GEN10_3DSTATE_VF_INSTANCING_DWordLength_start 0 +#define GEN9_3DSTATE_VF_INSTANCING_DWordLength_start 0 +#define GEN8_3DSTATE_VF_INSTANCING_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_INSTANCING_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_INSTANCING::Instance Data Step Rate */ + + +#define GEN11_3DSTATE_VF_INSTANCING_InstanceDataStepRate_bits 32 +#define GEN10_3DSTATE_VF_INSTANCING_InstanceDataStepRate_bits 32 +#define GEN9_3DSTATE_VF_INSTANCING_InstanceDataStepRate_bits 32 +#define GEN8_3DSTATE_VF_INSTANCING_InstanceDataStepRate_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_INSTANCING_InstanceDataStepRate_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_INSTANCING_InstanceDataStepRate_start 64 +#define GEN10_3DSTATE_VF_INSTANCING_InstanceDataStepRate_start 64 +#define GEN9_3DSTATE_VF_INSTANCING_InstanceDataStepRate_start 64 +#define GEN8_3DSTATE_VF_INSTANCING_InstanceDataStepRate_start 64 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_INSTANCING_InstanceDataStepRate_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_INSTANCING::Instancing Enable */ + + +#define GEN11_3DSTATE_VF_INSTANCING_InstancingEnable_bits 1 +#define GEN10_3DSTATE_VF_INSTANCING_InstancingEnable_bits 1 +#define GEN9_3DSTATE_VF_INSTANCING_InstancingEnable_bits 1 +#define GEN8_3DSTATE_VF_INSTANCING_InstancingEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_INSTANCING_InstancingEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_INSTANCING_InstancingEnable_start 40 +#define GEN10_3DSTATE_VF_INSTANCING_InstancingEnable_start 40 +#define GEN9_3DSTATE_VF_INSTANCING_InstancingEnable_start 40 +#define GEN8_3DSTATE_VF_INSTANCING_InstancingEnable_start 40 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_INSTANCING_InstancingEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 40; + case 10: return 40; + case 9: return 40; + case 8: return 40; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_INSTANCING::Vertex Element Index */ + + +#define GEN11_3DSTATE_VF_INSTANCING_VertexElementIndex_bits 6 +#define GEN10_3DSTATE_VF_INSTANCING_VertexElementIndex_bits 6 +#define GEN9_3DSTATE_VF_INSTANCING_VertexElementIndex_bits 6 +#define GEN8_3DSTATE_VF_INSTANCING_VertexElementIndex_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_INSTANCING_VertexElementIndex_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_INSTANCING_VertexElementIndex_start 32 +#define GEN10_3DSTATE_VF_INSTANCING_VertexElementIndex_start 32 +#define GEN9_3DSTATE_VF_INSTANCING_VertexElementIndex_start 32 +#define GEN8_3DSTATE_VF_INSTANCING_VertexElementIndex_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_INSTANCING_VertexElementIndex_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_SGVS */ + + +#define GEN11_3DSTATE_VF_SGVS_length 2 +#define GEN10_3DSTATE_VF_SGVS_length 2 +#define GEN9_3DSTATE_VF_SGVS_length 2 +#define GEN8_3DSTATE_VF_SGVS_length 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_SGVS::3D Command Opcode */ + + +#define GEN11_3DSTATE_VF_SGVS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_VF_SGVS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_VF_SGVS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_VF_SGVS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_SGVS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_VF_SGVS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_VF_SGVS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_VF_SGVS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_SGVS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_VF_SGVS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_VF_SGVS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_VF_SGVS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_VF_SGVS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_SGVS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_VF_SGVS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_VF_SGVS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_VF_SGVS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_SGVS::Command SubType */ + + +#define GEN11_3DSTATE_VF_SGVS_CommandSubType_bits 2 +#define GEN10_3DSTATE_VF_SGVS_CommandSubType_bits 2 +#define GEN9_3DSTATE_VF_SGVS_CommandSubType_bits 2 +#define GEN8_3DSTATE_VF_SGVS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_SGVS_CommandSubType_start 27 +#define GEN10_3DSTATE_VF_SGVS_CommandSubType_start 27 +#define GEN9_3DSTATE_VF_SGVS_CommandSubType_start 27 +#define GEN8_3DSTATE_VF_SGVS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_SGVS::Command Type */ + + +#define GEN11_3DSTATE_VF_SGVS_CommandType_bits 3 +#define GEN10_3DSTATE_VF_SGVS_CommandType_bits 3 +#define GEN9_3DSTATE_VF_SGVS_CommandType_bits 3 +#define GEN8_3DSTATE_VF_SGVS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_SGVS_CommandType_start 29 +#define GEN10_3DSTATE_VF_SGVS_CommandType_start 29 +#define GEN9_3DSTATE_VF_SGVS_CommandType_start 29 +#define GEN8_3DSTATE_VF_SGVS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_SGVS::DWord Length */ + + +#define GEN11_3DSTATE_VF_SGVS_DWordLength_bits 8 +#define GEN10_3DSTATE_VF_SGVS_DWordLength_bits 8 +#define GEN9_3DSTATE_VF_SGVS_DWordLength_bits 8 +#define GEN8_3DSTATE_VF_SGVS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_SGVS_DWordLength_start 0 +#define GEN10_3DSTATE_VF_SGVS_DWordLength_start 0 +#define GEN9_3DSTATE_VF_SGVS_DWordLength_start 0 +#define GEN8_3DSTATE_VF_SGVS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_SGVS::InstanceID Component Number */ + + +#define GEN11_3DSTATE_VF_SGVS_InstanceIDComponentNumber_bits 2 +#define GEN10_3DSTATE_VF_SGVS_InstanceIDComponentNumber_bits 2 +#define GEN9_3DSTATE_VF_SGVS_InstanceIDComponentNumber_bits 2 +#define GEN8_3DSTATE_VF_SGVS_InstanceIDComponentNumber_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_InstanceIDComponentNumber_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_SGVS_InstanceIDComponentNumber_start 61 +#define GEN10_3DSTATE_VF_SGVS_InstanceIDComponentNumber_start 61 +#define GEN9_3DSTATE_VF_SGVS_InstanceIDComponentNumber_start 61 +#define GEN8_3DSTATE_VF_SGVS_InstanceIDComponentNumber_start 61 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_InstanceIDComponentNumber_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 61; + case 10: return 61; + case 9: return 61; + case 8: return 61; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_SGVS::InstanceID Element Offset */ + + +#define GEN11_3DSTATE_VF_SGVS_InstanceIDElementOffset_bits 6 +#define GEN10_3DSTATE_VF_SGVS_InstanceIDElementOffset_bits 6 +#define GEN9_3DSTATE_VF_SGVS_InstanceIDElementOffset_bits 6 +#define GEN8_3DSTATE_VF_SGVS_InstanceIDElementOffset_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_InstanceIDElementOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_SGVS_InstanceIDElementOffset_start 48 +#define GEN10_3DSTATE_VF_SGVS_InstanceIDElementOffset_start 48 +#define GEN9_3DSTATE_VF_SGVS_InstanceIDElementOffset_start 48 +#define GEN8_3DSTATE_VF_SGVS_InstanceIDElementOffset_start 48 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_InstanceIDElementOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 48; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_SGVS::InstanceID Enable */ + + +#define GEN11_3DSTATE_VF_SGVS_InstanceIDEnable_bits 1 +#define GEN10_3DSTATE_VF_SGVS_InstanceIDEnable_bits 1 +#define GEN9_3DSTATE_VF_SGVS_InstanceIDEnable_bits 1 +#define GEN8_3DSTATE_VF_SGVS_InstanceIDEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_InstanceIDEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_SGVS_InstanceIDEnable_start 63 +#define GEN10_3DSTATE_VF_SGVS_InstanceIDEnable_start 63 +#define GEN9_3DSTATE_VF_SGVS_InstanceIDEnable_start 63 +#define GEN8_3DSTATE_VF_SGVS_InstanceIDEnable_start 63 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_InstanceIDEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 63; + case 10: return 63; + case 9: return 63; + case 8: return 63; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_SGVS::VertexID Component Number */ + + +#define GEN11_3DSTATE_VF_SGVS_VertexIDComponentNumber_bits 2 +#define GEN10_3DSTATE_VF_SGVS_VertexIDComponentNumber_bits 2 +#define GEN9_3DSTATE_VF_SGVS_VertexIDComponentNumber_bits 2 +#define GEN8_3DSTATE_VF_SGVS_VertexIDComponentNumber_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_VertexIDComponentNumber_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_SGVS_VertexIDComponentNumber_start 45 +#define GEN10_3DSTATE_VF_SGVS_VertexIDComponentNumber_start 45 +#define GEN9_3DSTATE_VF_SGVS_VertexIDComponentNumber_start 45 +#define GEN8_3DSTATE_VF_SGVS_VertexIDComponentNumber_start 45 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_VertexIDComponentNumber_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 45; + case 10: return 45; + case 9: return 45; + case 8: return 45; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_SGVS::VertexID Element Offset */ + + +#define GEN11_3DSTATE_VF_SGVS_VertexIDElementOffset_bits 6 +#define GEN10_3DSTATE_VF_SGVS_VertexIDElementOffset_bits 6 +#define GEN9_3DSTATE_VF_SGVS_VertexIDElementOffset_bits 6 +#define GEN8_3DSTATE_VF_SGVS_VertexIDElementOffset_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_VertexIDElementOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_SGVS_VertexIDElementOffset_start 32 +#define GEN10_3DSTATE_VF_SGVS_VertexIDElementOffset_start 32 +#define GEN9_3DSTATE_VF_SGVS_VertexIDElementOffset_start 32 +#define GEN8_3DSTATE_VF_SGVS_VertexIDElementOffset_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_VertexIDElementOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_SGVS::VertexID Enable */ + + +#define GEN11_3DSTATE_VF_SGVS_VertexIDEnable_bits 1 +#define GEN10_3DSTATE_VF_SGVS_VertexIDEnable_bits 1 +#define GEN9_3DSTATE_VF_SGVS_VertexIDEnable_bits 1 +#define GEN8_3DSTATE_VF_SGVS_VertexIDEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_VertexIDEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_SGVS_VertexIDEnable_start 47 +#define GEN10_3DSTATE_VF_SGVS_VertexIDEnable_start 47 +#define GEN9_3DSTATE_VF_SGVS_VertexIDEnable_start 47 +#define GEN8_3DSTATE_VF_SGVS_VertexIDEnable_start 47 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_VertexIDEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 47; + case 10: return 47; + case 9: return 47; + case 8: return 47; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_SGVS_2 */ + + +#define GEN11_3DSTATE_VF_SGVS_2_length 3 +#define GEN10_3DSTATE_VF_SGVS_2_length 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_2_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_SGVS_2::3D Command Opcode */ + + +#define GEN11_3DSTATE_VF_SGVS_2_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_VF_SGVS_2_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_2_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_SGVS_2_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_VF_SGVS_2_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_2_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_SGVS_2::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_VF_SGVS_2_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_VF_SGVS_2_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_2_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_SGVS_2_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_VF_SGVS_2_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_2_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_SGVS_2::Command SubType */ + + +#define GEN11_3DSTATE_VF_SGVS_2_CommandSubType_bits 2 +#define GEN10_3DSTATE_VF_SGVS_2_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_2_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_SGVS_2_CommandSubType_start 27 +#define GEN10_3DSTATE_VF_SGVS_2_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_2_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_SGVS_2::Command Type */ + + +#define GEN11_3DSTATE_VF_SGVS_2_CommandType_bits 3 +#define GEN10_3DSTATE_VF_SGVS_2_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_2_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_SGVS_2_CommandType_start 29 +#define GEN10_3DSTATE_VF_SGVS_2_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_2_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_SGVS_2::DWord Length */ + + +#define GEN11_3DSTATE_VF_SGVS_2_DWordLength_bits 8 +#define GEN10_3DSTATE_VF_SGVS_2_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_2_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_SGVS_2_DWordLength_start 0 +#define GEN10_3DSTATE_VF_SGVS_2_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_2_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_SGVS_2::XP0 Component Number */ + + +#define GEN11_3DSTATE_VF_SGVS_2_XP0ComponentNumber_bits 2 +#define GEN10_3DSTATE_VF_SGVS_2_XP0ComponentNumber_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_2_XP0ComponentNumber_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_SGVS_2_XP0ComponentNumber_start 45 +#define GEN10_3DSTATE_VF_SGVS_2_XP0ComponentNumber_start 45 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_2_XP0ComponentNumber_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 45; + case 10: return 45; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_SGVS_2::XP0 Element Offset */ + + +#define GEN11_3DSTATE_VF_SGVS_2_XP0ElementOffset_bits 6 +#define GEN10_3DSTATE_VF_SGVS_2_XP0ElementOffset_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_2_XP0ElementOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_SGVS_2_XP0ElementOffset_start 32 +#define GEN10_3DSTATE_VF_SGVS_2_XP0ElementOffset_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_2_XP0ElementOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_SGVS_2::XP0 Enable */ + + +#define GEN11_3DSTATE_VF_SGVS_2_XP0Enable_bits 1 +#define GEN10_3DSTATE_VF_SGVS_2_XP0Enable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_2_XP0Enable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_SGVS_2_XP0Enable_start 47 +#define GEN10_3DSTATE_VF_SGVS_2_XP0Enable_start 47 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_2_XP0Enable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 47; + case 10: return 47; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_SGVS_2::XP0 Source Select */ + + +#define GEN11_3DSTATE_VF_SGVS_2_XP0SourceSelect_bits 1 +#define GEN10_3DSTATE_VF_SGVS_2_XP0SourceSelect_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_2_XP0SourceSelect_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_SGVS_2_XP0SourceSelect_start 44 +#define GEN10_3DSTATE_VF_SGVS_2_XP0SourceSelect_start 44 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_2_XP0SourceSelect_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 44; + case 10: return 44; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_SGVS_2::XP1 Component Number */ + + +#define GEN11_3DSTATE_VF_SGVS_2_XP1ComponentNumber_bits 2 +#define GEN10_3DSTATE_VF_SGVS_2_XP1ComponentNumber_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_2_XP1ComponentNumber_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_SGVS_2_XP1ComponentNumber_start 61 +#define GEN10_3DSTATE_VF_SGVS_2_XP1ComponentNumber_start 61 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_2_XP1ComponentNumber_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 61; + case 10: return 61; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_SGVS_2::XP1 Element Offset */ + + +#define GEN11_3DSTATE_VF_SGVS_2_XP1ElementOffset_bits 6 +#define GEN10_3DSTATE_VF_SGVS_2_XP1ElementOffset_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_2_XP1ElementOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_SGVS_2_XP1ElementOffset_start 48 +#define GEN10_3DSTATE_VF_SGVS_2_XP1ElementOffset_start 48 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_2_XP1ElementOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_SGVS_2::XP1 Enable */ + + +#define GEN11_3DSTATE_VF_SGVS_2_XP1Enable_bits 1 +#define GEN10_3DSTATE_VF_SGVS_2_XP1Enable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_2_XP1Enable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_SGVS_2_XP1Enable_start 63 +#define GEN10_3DSTATE_VF_SGVS_2_XP1Enable_start 63 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_2_XP1Enable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 63; + case 10: return 63; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_SGVS_2::XP1 Source Select */ + + +#define GEN11_3DSTATE_VF_SGVS_2_XP1SourceSelect_bits 1 +#define GEN10_3DSTATE_VF_SGVS_2_XP1SourceSelect_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_2_XP1SourceSelect_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_SGVS_2_XP1SourceSelect_start 60 +#define GEN10_3DSTATE_VF_SGVS_2_XP1SourceSelect_start 60 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_2_XP1SourceSelect_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 60; + case 10: return 60; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_SGVS_2::XP2 Component Number */ + + +#define GEN11_3DSTATE_VF_SGVS_2_XP2ComponentNumber_bits 2 +#define GEN10_3DSTATE_VF_SGVS_2_XP2ComponentNumber_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_2_XP2ComponentNumber_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_SGVS_2_XP2ComponentNumber_start 77 +#define GEN10_3DSTATE_VF_SGVS_2_XP2ComponentNumber_start 77 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_2_XP2ComponentNumber_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 77; + case 10: return 77; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_SGVS_2::XP2 Element Offset */ + + +#define GEN11_3DSTATE_VF_SGVS_2_XP2ElementOffset_bits 6 +#define GEN10_3DSTATE_VF_SGVS_2_XP2ElementOffset_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_2_XP2ElementOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_SGVS_2_XP2ElementOffset_start 64 +#define GEN10_3DSTATE_VF_SGVS_2_XP2ElementOffset_start 64 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_2_XP2ElementOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_SGVS_2::XP2 Enable */ + + +#define GEN11_3DSTATE_VF_SGVS_2_XP2Enable_bits 1 +#define GEN10_3DSTATE_VF_SGVS_2_XP2Enable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_2_XP2Enable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_SGVS_2_XP2Enable_start 79 +#define GEN10_3DSTATE_VF_SGVS_2_XP2Enable_start 79 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_SGVS_2_XP2Enable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 79; + case 10: return 79; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_STATISTICS */ + + +#define GEN11_3DSTATE_VF_STATISTICS_length 1 +#define GEN10_3DSTATE_VF_STATISTICS_length 1 +#define GEN9_3DSTATE_VF_STATISTICS_length 1 +#define GEN8_3DSTATE_VF_STATISTICS_length 1 +#define GEN75_3DSTATE_VF_STATISTICS_length 1 +#define GEN7_3DSTATE_VF_STATISTICS_length 1 +#define GEN6_3DSTATE_VF_STATISTICS_length 1 +#define GEN5_3DSTATE_VF_STATISTICS_length 1 +#define GEN45_3DSTATE_VF_STATISTICS_length 1 +#define GEN4_3DSTATE_VF_STATISTICS_length 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_STATISTICS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_STATISTICS::3D Command Opcode */ + + +#define GEN11_3DSTATE_VF_STATISTICS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_VF_STATISTICS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_VF_STATISTICS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_VF_STATISTICS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_VF_STATISTICS_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_VF_STATISTICS_3DCommandOpcode_bits 3 +#define GEN6_3DSTATE_VF_STATISTICS_3DCommandOpcode_bits 3 +#define GEN5_3DSTATE_VF_STATISTICS_3DCommandOpcode_bits 3 +#define GEN45_3DSTATE_VF_STATISTICS_3DCommandOpcode_bits 3 +#define GEN4_3DSTATE_VF_STATISTICS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_STATISTICS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_STATISTICS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_VF_STATISTICS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_VF_STATISTICS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_VF_STATISTICS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_VF_STATISTICS_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_VF_STATISTICS_3DCommandOpcode_start 24 +#define GEN6_3DSTATE_VF_STATISTICS_3DCommandOpcode_start 24 +#define GEN5_3DSTATE_VF_STATISTICS_3DCommandOpcode_start 24 +#define GEN45_3DSTATE_VF_STATISTICS_3DCommandOpcode_start 24 +#define GEN4_3DSTATE_VF_STATISTICS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_STATISTICS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 24; + case 4: + if (devinfo->is_g4x) { + return 24; + } else { + return 24; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_STATISTICS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_bits 8 +#define GEN6_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_bits 8 +#define GEN5_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_bits 8 +#define GEN45_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_bits 8 +#define GEN4_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_start 16 +#define GEN6_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_start 16 +#define GEN5_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_start 16 +#define GEN45_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_start 16 +#define GEN4_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_STATISTICS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_STATISTICS::Command SubType */ + + +#define GEN11_3DSTATE_VF_STATISTICS_CommandSubType_bits 2 +#define GEN10_3DSTATE_VF_STATISTICS_CommandSubType_bits 2 +#define GEN9_3DSTATE_VF_STATISTICS_CommandSubType_bits 2 +#define GEN8_3DSTATE_VF_STATISTICS_CommandSubType_bits 2 +#define GEN75_3DSTATE_VF_STATISTICS_CommandSubType_bits 2 +#define GEN7_3DSTATE_VF_STATISTICS_CommandSubType_bits 2 +#define GEN6_3DSTATE_VF_STATISTICS_CommandSubType_bits 2 +#define GEN5_3DSTATE_VF_STATISTICS_CommandSubType_bits 2 +#define GEN45_3DSTATE_VF_STATISTICS_CommandSubType_bits 2 +#define GEN4_3DSTATE_VF_STATISTICS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_STATISTICS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_STATISTICS_CommandSubType_start 27 +#define GEN10_3DSTATE_VF_STATISTICS_CommandSubType_start 27 +#define GEN9_3DSTATE_VF_STATISTICS_CommandSubType_start 27 +#define GEN8_3DSTATE_VF_STATISTICS_CommandSubType_start 27 +#define GEN75_3DSTATE_VF_STATISTICS_CommandSubType_start 27 +#define GEN7_3DSTATE_VF_STATISTICS_CommandSubType_start 27 +#define GEN6_3DSTATE_VF_STATISTICS_CommandSubType_start 27 +#define GEN5_3DSTATE_VF_STATISTICS_CommandSubType_start 27 +#define GEN45_3DSTATE_VF_STATISTICS_CommandSubType_start 27 +#define GEN4_3DSTATE_VF_STATISTICS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_STATISTICS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_STATISTICS::Command Type */ + + +#define GEN11_3DSTATE_VF_STATISTICS_CommandType_bits 3 +#define GEN10_3DSTATE_VF_STATISTICS_CommandType_bits 3 +#define GEN9_3DSTATE_VF_STATISTICS_CommandType_bits 3 +#define GEN8_3DSTATE_VF_STATISTICS_CommandType_bits 3 +#define GEN75_3DSTATE_VF_STATISTICS_CommandType_bits 3 +#define GEN7_3DSTATE_VF_STATISTICS_CommandType_bits 3 +#define GEN6_3DSTATE_VF_STATISTICS_CommandType_bits 3 +#define GEN5_3DSTATE_VF_STATISTICS_CommandType_bits 3 +#define GEN45_3DSTATE_VF_STATISTICS_CommandType_bits 3 +#define GEN4_3DSTATE_VF_STATISTICS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_STATISTICS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_STATISTICS_CommandType_start 29 +#define GEN10_3DSTATE_VF_STATISTICS_CommandType_start 29 +#define GEN9_3DSTATE_VF_STATISTICS_CommandType_start 29 +#define GEN8_3DSTATE_VF_STATISTICS_CommandType_start 29 +#define GEN75_3DSTATE_VF_STATISTICS_CommandType_start 29 +#define GEN7_3DSTATE_VF_STATISTICS_CommandType_start 29 +#define GEN6_3DSTATE_VF_STATISTICS_CommandType_start 29 +#define GEN5_3DSTATE_VF_STATISTICS_CommandType_start 29 +#define GEN45_3DSTATE_VF_STATISTICS_CommandType_start 29 +#define GEN4_3DSTATE_VF_STATISTICS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_STATISTICS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 29; + case 4: + if (devinfo->is_g4x) { + return 29; + } else { + return 29; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_STATISTICS::Statistics Enable */ + + +#define GEN11_3DSTATE_VF_STATISTICS_StatisticsEnable_bits 1 +#define GEN10_3DSTATE_VF_STATISTICS_StatisticsEnable_bits 1 +#define GEN9_3DSTATE_VF_STATISTICS_StatisticsEnable_bits 1 +#define GEN8_3DSTATE_VF_STATISTICS_StatisticsEnable_bits 1 +#define GEN75_3DSTATE_VF_STATISTICS_StatisticsEnable_bits 1 +#define GEN7_3DSTATE_VF_STATISTICS_StatisticsEnable_bits 1 +#define GEN6_3DSTATE_VF_STATISTICS_StatisticsEnable_bits 1 +#define GEN5_3DSTATE_VF_STATISTICS_StatisticsEnable_bits 1 +#define GEN45_3DSTATE_VF_STATISTICS_StatisticsEnable_bits 1 +#define GEN4_3DSTATE_VF_STATISTICS_StatisticsEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_STATISTICS_StatisticsEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_STATISTICS_StatisticsEnable_start 0 +#define GEN10_3DSTATE_VF_STATISTICS_StatisticsEnable_start 0 +#define GEN9_3DSTATE_VF_STATISTICS_StatisticsEnable_start 0 +#define GEN8_3DSTATE_VF_STATISTICS_StatisticsEnable_start 0 +#define GEN75_3DSTATE_VF_STATISTICS_StatisticsEnable_start 0 +#define GEN7_3DSTATE_VF_STATISTICS_StatisticsEnable_start 0 +#define GEN6_3DSTATE_VF_STATISTICS_StatisticsEnable_start 0 +#define GEN5_3DSTATE_VF_STATISTICS_StatisticsEnable_start 0 +#define GEN45_3DSTATE_VF_STATISTICS_StatisticsEnable_start 0 +#define GEN4_3DSTATE_VF_STATISTICS_StatisticsEnable_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_STATISTICS_StatisticsEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_TOPOLOGY */ + + +#define GEN11_3DSTATE_VF_TOPOLOGY_length 2 +#define GEN10_3DSTATE_VF_TOPOLOGY_length 2 +#define GEN9_3DSTATE_VF_TOPOLOGY_length 2 +#define GEN8_3DSTATE_VF_TOPOLOGY_length 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_TOPOLOGY_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_TOPOLOGY::3D Command Opcode */ + + +#define GEN11_3DSTATE_VF_TOPOLOGY_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_VF_TOPOLOGY_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_VF_TOPOLOGY_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_VF_TOPOLOGY_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_TOPOLOGY_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_TOPOLOGY_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_VF_TOPOLOGY_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_VF_TOPOLOGY_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_VF_TOPOLOGY_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_TOPOLOGY_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_TOPOLOGY::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_VF_TOPOLOGY_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_VF_TOPOLOGY_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_VF_TOPOLOGY_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_VF_TOPOLOGY_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_TOPOLOGY_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_TOPOLOGY_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_VF_TOPOLOGY_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_VF_TOPOLOGY_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_VF_TOPOLOGY_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_TOPOLOGY_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_TOPOLOGY::Command SubType */ + + +#define GEN11_3DSTATE_VF_TOPOLOGY_CommandSubType_bits 2 +#define GEN10_3DSTATE_VF_TOPOLOGY_CommandSubType_bits 2 +#define GEN9_3DSTATE_VF_TOPOLOGY_CommandSubType_bits 2 +#define GEN8_3DSTATE_VF_TOPOLOGY_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_TOPOLOGY_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_TOPOLOGY_CommandSubType_start 27 +#define GEN10_3DSTATE_VF_TOPOLOGY_CommandSubType_start 27 +#define GEN9_3DSTATE_VF_TOPOLOGY_CommandSubType_start 27 +#define GEN8_3DSTATE_VF_TOPOLOGY_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_TOPOLOGY_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_TOPOLOGY::Command Type */ + + +#define GEN11_3DSTATE_VF_TOPOLOGY_CommandType_bits 3 +#define GEN10_3DSTATE_VF_TOPOLOGY_CommandType_bits 3 +#define GEN9_3DSTATE_VF_TOPOLOGY_CommandType_bits 3 +#define GEN8_3DSTATE_VF_TOPOLOGY_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_TOPOLOGY_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_TOPOLOGY_CommandType_start 29 +#define GEN10_3DSTATE_VF_TOPOLOGY_CommandType_start 29 +#define GEN9_3DSTATE_VF_TOPOLOGY_CommandType_start 29 +#define GEN8_3DSTATE_VF_TOPOLOGY_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_TOPOLOGY_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_TOPOLOGY::DWord Length */ + + +#define GEN11_3DSTATE_VF_TOPOLOGY_DWordLength_bits 8 +#define GEN10_3DSTATE_VF_TOPOLOGY_DWordLength_bits 8 +#define GEN9_3DSTATE_VF_TOPOLOGY_DWordLength_bits 8 +#define GEN8_3DSTATE_VF_TOPOLOGY_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_TOPOLOGY_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_TOPOLOGY_DWordLength_start 0 +#define GEN10_3DSTATE_VF_TOPOLOGY_DWordLength_start 0 +#define GEN9_3DSTATE_VF_TOPOLOGY_DWordLength_start 0 +#define GEN8_3DSTATE_VF_TOPOLOGY_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_TOPOLOGY_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VF_TOPOLOGY::Primitive Topology Type */ + + +#define GEN11_3DSTATE_VF_TOPOLOGY_PrimitiveTopologyType_bits 6 +#define GEN10_3DSTATE_VF_TOPOLOGY_PrimitiveTopologyType_bits 6 +#define GEN9_3DSTATE_VF_TOPOLOGY_PrimitiveTopologyType_bits 6 +#define GEN8_3DSTATE_VF_TOPOLOGY_PrimitiveTopologyType_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_TOPOLOGY_PrimitiveTopologyType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VF_TOPOLOGY_PrimitiveTopologyType_start 32 +#define GEN10_3DSTATE_VF_TOPOLOGY_PrimitiveTopologyType_start 32 +#define GEN9_3DSTATE_VF_TOPOLOGY_PrimitiveTopologyType_start 32 +#define GEN8_3DSTATE_VF_TOPOLOGY_PrimitiveTopologyType_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VF_TOPOLOGY_PrimitiveTopologyType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VIEWPORT_STATE_POINTERS */ + + +#define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS_length 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VIEWPORT_STATE_POINTERS::3D Command Opcode */ + + +#define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 24; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VIEWPORT_STATE_POINTERS::3D Command Sub Opcode */ + + +#define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VIEWPORT_STATE_POINTERS::CC Viewport State Change */ + + +#define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS_CCViewportStateChange_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_CCViewportStateChange_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS_CCViewportStateChange_start 12 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_CCViewportStateChange_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 12; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VIEWPORT_STATE_POINTERS::CLIP Viewport State Change */ + + +#define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS_CLIPViewportStateChange_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_CLIPViewportStateChange_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS_CLIPViewportStateChange_start 10 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_CLIPViewportStateChange_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 10; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VIEWPORT_STATE_POINTERS::Command SubType */ + + +#define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VIEWPORT_STATE_POINTERS::Command Type */ + + +#define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VIEWPORT_STATE_POINTERS::DWord Length */ + + +#define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VIEWPORT_STATE_POINTERS::Pointer to CC_VIEWPORT */ + + +#define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS_PointertoCC_VIEWPORT_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_PointertoCC_VIEWPORT_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS_PointertoCC_VIEWPORT_start 101 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_PointertoCC_VIEWPORT_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 101; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VIEWPORT_STATE_POINTERS::Pointer to CLIP_VIEWPORT */ + + +#define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS_PointertoCLIP_VIEWPORT_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_PointertoCLIP_VIEWPORT_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS_PointertoCLIP_VIEWPORT_start 37 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_PointertoCLIP_VIEWPORT_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 37; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VIEWPORT_STATE_POINTERS::Pointer to SF_VIEWPORT */ + + +#define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS_PointertoSF_VIEWPORT_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_PointertoSF_VIEWPORT_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS_PointertoSF_VIEWPORT_start 69 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_PointertoSF_VIEWPORT_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 69; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VIEWPORT_STATE_POINTERS::SF Viewport State Change */ + + +#define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS_SFViewportStateChange_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_SFViewportStateChange_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS_SFViewportStateChange_start 11 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_SFViewportStateChange_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 11; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VIEWPORT_STATE_POINTERS_CC */ + + +#define GEN11_3DSTATE_VIEWPORT_STATE_POINTERS_CC_length 2 +#define GEN10_3DSTATE_VIEWPORT_STATE_POINTERS_CC_length 2 +#define GEN9_3DSTATE_VIEWPORT_STATE_POINTERS_CC_length 2 +#define GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_CC_length 2 +#define GEN75_3DSTATE_VIEWPORT_STATE_POINTERS_CC_length 2 +#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC_length 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_CC_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VIEWPORT_STATE_POINTERS_CC::3D Command Opcode */ + + +#define GEN11_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VIEWPORT_STATE_POINTERS_CC::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_CC_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VIEWPORT_STATE_POINTERS_CC::CC Viewport Pointer */ + + +#define GEN11_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CCViewportPointer_bits 27 +#define GEN10_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CCViewportPointer_bits 27 +#define GEN9_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CCViewportPointer_bits 27 +#define GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CCViewportPointer_bits 27 +#define GEN75_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CCViewportPointer_bits 27 +#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CCViewportPointer_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CCViewportPointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CCViewportPointer_start 37 +#define GEN10_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CCViewportPointer_start 37 +#define GEN9_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CCViewportPointer_start 37 +#define GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CCViewportPointer_start 37 +#define GEN75_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CCViewportPointer_start 37 +#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CCViewportPointer_start 37 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CCViewportPointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 37; + case 10: return 37; + case 9: return 37; + case 8: return 37; + case 7: + if (devinfo->is_haswell) { + return 37; + } else { + return 37; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VIEWPORT_STATE_POINTERS_CC::Command SubType */ + + +#define GEN11_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandSubType_bits 2 +#define GEN10_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandSubType_bits 2 +#define GEN9_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandSubType_bits 2 +#define GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandSubType_bits 2 +#define GEN75_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandSubType_bits 2 +#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandSubType_start 27 +#define GEN10_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandSubType_start 27 +#define GEN9_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandSubType_start 27 +#define GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandSubType_start 27 +#define GEN75_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandSubType_start 27 +#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VIEWPORT_STATE_POINTERS_CC::Command Type */ + + +#define GEN11_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandType_bits 3 +#define GEN10_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandType_bits 3 +#define GEN9_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandType_bits 3 +#define GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandType_bits 3 +#define GEN75_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandType_bits 3 +#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandType_start 29 +#define GEN10_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandType_start 29 +#define GEN9_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandType_start 29 +#define GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandType_start 29 +#define GEN75_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandType_start 29 +#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_CC_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VIEWPORT_STATE_POINTERS_CC::DWord Length */ + + +#define GEN11_3DSTATE_VIEWPORT_STATE_POINTERS_CC_DWordLength_bits 8 +#define GEN10_3DSTATE_VIEWPORT_STATE_POINTERS_CC_DWordLength_bits 8 +#define GEN9_3DSTATE_VIEWPORT_STATE_POINTERS_CC_DWordLength_bits 8 +#define GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_CC_DWordLength_bits 8 +#define GEN75_3DSTATE_VIEWPORT_STATE_POINTERS_CC_DWordLength_bits 8 +#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_CC_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VIEWPORT_STATE_POINTERS_CC_DWordLength_start 0 +#define GEN10_3DSTATE_VIEWPORT_STATE_POINTERS_CC_DWordLength_start 0 +#define GEN9_3DSTATE_VIEWPORT_STATE_POINTERS_CC_DWordLength_start 0 +#define GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_CC_DWordLength_start 0 +#define GEN75_3DSTATE_VIEWPORT_STATE_POINTERS_CC_DWordLength_start 0 +#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_CC_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP */ + + +#define GEN11_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_length 2 +#define GEN10_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_length 2 +#define GEN9_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_length 2 +#define GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_length 2 +#define GEN75_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_length 2 +#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_length 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP::3D Command Opcode */ + + +#define GEN11_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP::Command SubType */ + + +#define GEN11_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandSubType_bits 2 +#define GEN10_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandSubType_bits 2 +#define GEN9_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandSubType_bits 2 +#define GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandSubType_bits 2 +#define GEN75_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandSubType_bits 2 +#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandSubType_start 27 +#define GEN10_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandSubType_start 27 +#define GEN9_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandSubType_start 27 +#define GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandSubType_start 27 +#define GEN75_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandSubType_start 27 +#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP::Command Type */ + + +#define GEN11_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandType_bits 3 +#define GEN10_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandType_bits 3 +#define GEN9_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandType_bits 3 +#define GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandType_bits 3 +#define GEN75_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandType_bits 3 +#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandType_start 29 +#define GEN10_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandType_start 29 +#define GEN9_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandType_start 29 +#define GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandType_start 29 +#define GEN75_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandType_start 29 +#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP::DWord Length */ + + +#define GEN11_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_DWordLength_bits 8 +#define GEN10_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_DWordLength_bits 8 +#define GEN9_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_DWordLength_bits 8 +#define GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_DWordLength_bits 8 +#define GEN75_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_DWordLength_bits 8 +#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_DWordLength_start 0 +#define GEN10_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_DWordLength_start 0 +#define GEN9_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_DWordLength_start 0 +#define GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_DWordLength_start 0 +#define GEN75_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_DWordLength_start 0 +#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP::SF Clip Viewport Pointer */ + + +#define GEN11_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_SFClipViewportPointer_bits 26 +#define GEN10_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_SFClipViewportPointer_bits 26 +#define GEN9_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_SFClipViewportPointer_bits 26 +#define GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_SFClipViewportPointer_bits 26 +#define GEN75_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_SFClipViewportPointer_bits 26 +#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_SFClipViewportPointer_bits 26 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_SFClipViewportPointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 26; + case 10: return 26; + case 9: return 26; + case 8: return 26; + case 7: + if (devinfo->is_haswell) { + return 26; + } else { + return 26; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_SFClipViewportPointer_start 38 +#define GEN10_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_SFClipViewportPointer_start 38 +#define GEN9_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_SFClipViewportPointer_start 38 +#define GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_SFClipViewportPointer_start 38 +#define GEN75_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_SFClipViewportPointer_start 38 +#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_SFClipViewportPointer_start 38 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP_SFClipViewportPointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 38; + case 10: return 38; + case 9: return 38; + case 8: return 38; + case 7: + if (devinfo->is_haswell) { + return 38; + } else { + return 38; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VS */ + + +#define GEN11_3DSTATE_VS_length 9 +#define GEN10_3DSTATE_VS_length 9 +#define GEN9_3DSTATE_VS_length 9 +#define GEN8_3DSTATE_VS_length 9 +#define GEN75_3DSTATE_VS_length 6 +#define GEN7_3DSTATE_VS_length 6 +#define GEN6_3DSTATE_VS_length 6 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 9; + case 10: return 9; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 6; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VS::3D Command Opcode */ + + +#define GEN11_3DSTATE_VS_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_VS_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_VS_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_VS_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_VS_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_VS_3DCommandOpcode_bits 3 +#define GEN6_3DSTATE_VS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VS_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_VS_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_VS_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_VS_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_VS_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_VS_3DCommandOpcode_start 24 +#define GEN6_3DSTATE_VS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VS::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_VS_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_VS_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_VS_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_VS_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_VS_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_VS_3DCommandSubOpcode_bits 8 +#define GEN6_3DSTATE_VS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VS_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_VS_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_VS_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_VS_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_VS_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_VS_3DCommandSubOpcode_start 16 +#define GEN6_3DSTATE_VS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VS::Accesses UAV */ + + +#define GEN11_3DSTATE_VS_AccessesUAV_bits 1 +#define GEN10_3DSTATE_VS_AccessesUAV_bits 1 +#define GEN9_3DSTATE_VS_AccessesUAV_bits 1 +#define GEN8_3DSTATE_VS_AccessesUAV_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_AccessesUAV_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VS_AccessesUAV_start 108 +#define GEN10_3DSTATE_VS_AccessesUAV_start 108 +#define GEN9_3DSTATE_VS_AccessesUAV_start 108 +#define GEN8_3DSTATE_VS_AccessesUAV_start 108 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_AccessesUAV_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 108; + case 10: return 108; + case 9: return 108; + case 8: return 108; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VS::Binding Table Entry Count */ + + +#define GEN11_3DSTATE_VS_BindingTableEntryCount_bits 8 +#define GEN10_3DSTATE_VS_BindingTableEntryCount_bits 8 +#define GEN9_3DSTATE_VS_BindingTableEntryCount_bits 8 +#define GEN8_3DSTATE_VS_BindingTableEntryCount_bits 8 +#define GEN75_3DSTATE_VS_BindingTableEntryCount_bits 8 +#define GEN7_3DSTATE_VS_BindingTableEntryCount_bits 8 +#define GEN6_3DSTATE_VS_BindingTableEntryCount_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_BindingTableEntryCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VS_BindingTableEntryCount_start 114 +#define GEN10_3DSTATE_VS_BindingTableEntryCount_start 114 +#define GEN9_3DSTATE_VS_BindingTableEntryCount_start 114 +#define GEN8_3DSTATE_VS_BindingTableEntryCount_start 114 +#define GEN75_3DSTATE_VS_BindingTableEntryCount_start 82 +#define GEN7_3DSTATE_VS_BindingTableEntryCount_start 82 +#define GEN6_3DSTATE_VS_BindingTableEntryCount_start 82 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_BindingTableEntryCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 114; + case 10: return 114; + case 9: return 114; + case 8: return 114; + case 7: + if (devinfo->is_haswell) { + return 82; + } else { + return 82; + } + case 6: return 82; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VS::Command SubType */ + + +#define GEN11_3DSTATE_VS_CommandSubType_bits 2 +#define GEN10_3DSTATE_VS_CommandSubType_bits 2 +#define GEN9_3DSTATE_VS_CommandSubType_bits 2 +#define GEN8_3DSTATE_VS_CommandSubType_bits 2 +#define GEN75_3DSTATE_VS_CommandSubType_bits 2 +#define GEN7_3DSTATE_VS_CommandSubType_bits 2 +#define GEN6_3DSTATE_VS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VS_CommandSubType_start 27 +#define GEN10_3DSTATE_VS_CommandSubType_start 27 +#define GEN9_3DSTATE_VS_CommandSubType_start 27 +#define GEN8_3DSTATE_VS_CommandSubType_start 27 +#define GEN75_3DSTATE_VS_CommandSubType_start 27 +#define GEN7_3DSTATE_VS_CommandSubType_start 27 +#define GEN6_3DSTATE_VS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VS::Command Type */ + + +#define GEN11_3DSTATE_VS_CommandType_bits 3 +#define GEN10_3DSTATE_VS_CommandType_bits 3 +#define GEN9_3DSTATE_VS_CommandType_bits 3 +#define GEN8_3DSTATE_VS_CommandType_bits 3 +#define GEN75_3DSTATE_VS_CommandType_bits 3 +#define GEN7_3DSTATE_VS_CommandType_bits 3 +#define GEN6_3DSTATE_VS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VS_CommandType_start 29 +#define GEN10_3DSTATE_VS_CommandType_start 29 +#define GEN9_3DSTATE_VS_CommandType_start 29 +#define GEN8_3DSTATE_VS_CommandType_start 29 +#define GEN75_3DSTATE_VS_CommandType_start 29 +#define GEN7_3DSTATE_VS_CommandType_start 29 +#define GEN6_3DSTATE_VS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VS::DWord Length */ + + +#define GEN11_3DSTATE_VS_DWordLength_bits 8 +#define GEN10_3DSTATE_VS_DWordLength_bits 8 +#define GEN9_3DSTATE_VS_DWordLength_bits 8 +#define GEN8_3DSTATE_VS_DWordLength_bits 8 +#define GEN75_3DSTATE_VS_DWordLength_bits 8 +#define GEN7_3DSTATE_VS_DWordLength_bits 8 +#define GEN6_3DSTATE_VS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VS_DWordLength_start 0 +#define GEN10_3DSTATE_VS_DWordLength_start 0 +#define GEN9_3DSTATE_VS_DWordLength_start 0 +#define GEN8_3DSTATE_VS_DWordLength_start 0 +#define GEN75_3DSTATE_VS_DWordLength_start 0 +#define GEN7_3DSTATE_VS_DWordLength_start 0 +#define GEN6_3DSTATE_VS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VS::Dispatch GRF Start Register For URB Data */ + + +#define GEN11_3DSTATE_VS_DispatchGRFStartRegisterForURBData_bits 5 +#define GEN10_3DSTATE_VS_DispatchGRFStartRegisterForURBData_bits 5 +#define GEN9_3DSTATE_VS_DispatchGRFStartRegisterForURBData_bits 5 +#define GEN8_3DSTATE_VS_DispatchGRFStartRegisterForURBData_bits 5 +#define GEN75_3DSTATE_VS_DispatchGRFStartRegisterForURBData_bits 5 +#define GEN7_3DSTATE_VS_DispatchGRFStartRegisterForURBData_bits 5 +#define GEN6_3DSTATE_VS_DispatchGRFStartRegisterForURBData_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_DispatchGRFStartRegisterForURBData_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 5; + } + case 6: return 5; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VS_DispatchGRFStartRegisterForURBData_start 212 +#define GEN10_3DSTATE_VS_DispatchGRFStartRegisterForURBData_start 212 +#define GEN9_3DSTATE_VS_DispatchGRFStartRegisterForURBData_start 212 +#define GEN8_3DSTATE_VS_DispatchGRFStartRegisterForURBData_start 212 +#define GEN75_3DSTATE_VS_DispatchGRFStartRegisterForURBData_start 148 +#define GEN7_3DSTATE_VS_DispatchGRFStartRegisterForURBData_start 148 +#define GEN6_3DSTATE_VS_DispatchGRFStartRegisterForURBData_start 148 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_DispatchGRFStartRegisterForURBData_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 212; + case 10: return 212; + case 9: return 212; + case 8: return 212; + case 7: + if (devinfo->is_haswell) { + return 148; + } else { + return 148; + } + case 6: return 148; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VS::Enable */ + + +#define GEN11_3DSTATE_VS_Enable_bits 1 +#define GEN10_3DSTATE_VS_Enable_bits 1 +#define GEN9_3DSTATE_VS_Enable_bits 1 +#define GEN8_3DSTATE_VS_Enable_bits 1 +#define GEN75_3DSTATE_VS_Enable_bits 1 +#define GEN7_3DSTATE_VS_Enable_bits 1 +#define GEN6_3DSTATE_VS_Enable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_Enable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VS_Enable_start 224 +#define GEN10_3DSTATE_VS_Enable_start 224 +#define GEN9_3DSTATE_VS_Enable_start 224 +#define GEN8_3DSTATE_VS_Enable_start 224 +#define GEN75_3DSTATE_VS_Enable_start 160 +#define GEN7_3DSTATE_VS_Enable_start 160 +#define GEN6_3DSTATE_VS_Enable_start 160 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_Enable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 224; + case 10: return 224; + case 9: return 224; + case 8: return 224; + case 7: + if (devinfo->is_haswell) { + return 160; + } else { + return 160; + } + case 6: return 160; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VS::Floating Point Mode */ + + +#define GEN11_3DSTATE_VS_FloatingPointMode_bits 1 +#define GEN10_3DSTATE_VS_FloatingPointMode_bits 1 +#define GEN9_3DSTATE_VS_FloatingPointMode_bits 1 +#define GEN8_3DSTATE_VS_FloatingPointMode_bits 1 +#define GEN75_3DSTATE_VS_FloatingPointMode_bits 1 +#define GEN7_3DSTATE_VS_FloatingPointMode_bits 1 +#define GEN6_3DSTATE_VS_FloatingPointMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_FloatingPointMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VS_FloatingPointMode_start 112 +#define GEN10_3DSTATE_VS_FloatingPointMode_start 112 +#define GEN9_3DSTATE_VS_FloatingPointMode_start 112 +#define GEN8_3DSTATE_VS_FloatingPointMode_start 112 +#define GEN75_3DSTATE_VS_FloatingPointMode_start 80 +#define GEN7_3DSTATE_VS_FloatingPointMode_start 80 +#define GEN6_3DSTATE_VS_FloatingPointMode_start 80 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_FloatingPointMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 112; + case 10: return 112; + case 9: return 112; + case 8: return 112; + case 7: + if (devinfo->is_haswell) { + return 80; + } else { + return 80; + } + case 6: return 80; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VS::Illegal Opcode Exception Enable */ + + +#define GEN11_3DSTATE_VS_IllegalOpcodeExceptionEnable_bits 1 +#define GEN10_3DSTATE_VS_IllegalOpcodeExceptionEnable_bits 1 +#define GEN9_3DSTATE_VS_IllegalOpcodeExceptionEnable_bits 1 +#define GEN8_3DSTATE_VS_IllegalOpcodeExceptionEnable_bits 1 +#define GEN75_3DSTATE_VS_IllegalOpcodeExceptionEnable_bits 1 +#define GEN7_3DSTATE_VS_IllegalOpcodeExceptionEnable_bits 1 +#define GEN6_3DSTATE_VS_IllegalOpcodeExceptionEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_IllegalOpcodeExceptionEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VS_IllegalOpcodeExceptionEnable_start 109 +#define GEN10_3DSTATE_VS_IllegalOpcodeExceptionEnable_start 109 +#define GEN9_3DSTATE_VS_IllegalOpcodeExceptionEnable_start 109 +#define GEN8_3DSTATE_VS_IllegalOpcodeExceptionEnable_start 109 +#define GEN75_3DSTATE_VS_IllegalOpcodeExceptionEnable_start 77 +#define GEN7_3DSTATE_VS_IllegalOpcodeExceptionEnable_start 77 +#define GEN6_3DSTATE_VS_IllegalOpcodeExceptionEnable_start 77 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_IllegalOpcodeExceptionEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 109; + case 10: return 109; + case 9: return 109; + case 8: return 109; + case 7: + if (devinfo->is_haswell) { + return 77; + } else { + return 77; + } + case 6: return 77; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VS::Kernel Start Pointer */ + + +#define GEN11_3DSTATE_VS_KernelStartPointer_bits 58 +#define GEN10_3DSTATE_VS_KernelStartPointer_bits 58 +#define GEN9_3DSTATE_VS_KernelStartPointer_bits 58 +#define GEN8_3DSTATE_VS_KernelStartPointer_bits 58 +#define GEN75_3DSTATE_VS_KernelStartPointer_bits 26 +#define GEN7_3DSTATE_VS_KernelStartPointer_bits 26 +#define GEN6_3DSTATE_VS_KernelStartPointer_bits 26 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_KernelStartPointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 58; + case 10: return 58; + case 9: return 58; + case 8: return 58; + case 7: + if (devinfo->is_haswell) { + return 26; + } else { + return 26; + } + case 6: return 26; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VS_KernelStartPointer_start 38 +#define GEN10_3DSTATE_VS_KernelStartPointer_start 38 +#define GEN9_3DSTATE_VS_KernelStartPointer_start 38 +#define GEN8_3DSTATE_VS_KernelStartPointer_start 38 +#define GEN75_3DSTATE_VS_KernelStartPointer_start 38 +#define GEN7_3DSTATE_VS_KernelStartPointer_start 38 +#define GEN6_3DSTATE_VS_KernelStartPointer_start 38 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_KernelStartPointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 38; + case 10: return 38; + case 9: return 38; + case 8: return 38; + case 7: + if (devinfo->is_haswell) { + return 38; + } else { + return 38; + } + case 6: return 38; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VS::Maximum Number of Threads */ + + +#define GEN11_3DSTATE_VS_MaximumNumberofThreads_bits 10 +#define GEN10_3DSTATE_VS_MaximumNumberofThreads_bits 10 +#define GEN9_3DSTATE_VS_MaximumNumberofThreads_bits 9 +#define GEN8_3DSTATE_VS_MaximumNumberofThreads_bits 9 +#define GEN75_3DSTATE_VS_MaximumNumberofThreads_bits 9 +#define GEN7_3DSTATE_VS_MaximumNumberofThreads_bits 7 +#define GEN6_3DSTATE_VS_MaximumNumberofThreads_bits 7 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_MaximumNumberofThreads_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 10; + case 10: return 10; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 7; + } + case 6: return 7; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VS_MaximumNumberofThreads_start 246 +#define GEN10_3DSTATE_VS_MaximumNumberofThreads_start 246 +#define GEN9_3DSTATE_VS_MaximumNumberofThreads_start 247 +#define GEN8_3DSTATE_VS_MaximumNumberofThreads_start 247 +#define GEN75_3DSTATE_VS_MaximumNumberofThreads_start 183 +#define GEN7_3DSTATE_VS_MaximumNumberofThreads_start 185 +#define GEN6_3DSTATE_VS_MaximumNumberofThreads_start 185 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_MaximumNumberofThreads_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 246; + case 10: return 246; + case 9: return 247; + case 8: return 247; + case 7: + if (devinfo->is_haswell) { + return 183; + } else { + return 185; + } + case 6: return 185; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VS::Per-Thread Scratch Space */ + + +#define GEN11_3DSTATE_VS_PerThreadScratchSpace_bits 4 +#define GEN10_3DSTATE_VS_PerThreadScratchSpace_bits 4 +#define GEN9_3DSTATE_VS_PerThreadScratchSpace_bits 4 +#define GEN8_3DSTATE_VS_PerThreadScratchSpace_bits 4 +#define GEN75_3DSTATE_VS_PerThreadScratchSpace_bits 4 +#define GEN7_3DSTATE_VS_PerThreadScratchSpace_bits 4 +#define GEN6_3DSTATE_VS_PerThreadScratchSpace_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_PerThreadScratchSpace_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VS_PerThreadScratchSpace_start 128 +#define GEN10_3DSTATE_VS_PerThreadScratchSpace_start 128 +#define GEN9_3DSTATE_VS_PerThreadScratchSpace_start 128 +#define GEN8_3DSTATE_VS_PerThreadScratchSpace_start 128 +#define GEN75_3DSTATE_VS_PerThreadScratchSpace_start 96 +#define GEN7_3DSTATE_VS_PerThreadScratchSpace_start 96 +#define GEN6_3DSTATE_VS_PerThreadScratchSpace_start 96 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_PerThreadScratchSpace_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 128; + case 10: return 128; + case 9: return 128; + case 8: return 128; + case 7: + if (devinfo->is_haswell) { + return 96; + } else { + return 96; + } + case 6: return 96; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VS::SIMD8 Dispatch Enable */ + + +#define GEN11_3DSTATE_VS_SIMD8DispatchEnable_bits 1 +#define GEN10_3DSTATE_VS_SIMD8DispatchEnable_bits 1 +#define GEN9_3DSTATE_VS_SIMD8DispatchEnable_bits 1 +#define GEN8_3DSTATE_VS_SIMD8DispatchEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_SIMD8DispatchEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VS_SIMD8DispatchEnable_start 226 +#define GEN10_3DSTATE_VS_SIMD8DispatchEnable_start 226 +#define GEN9_3DSTATE_VS_SIMD8DispatchEnable_start 226 +#define GEN8_3DSTATE_VS_SIMD8DispatchEnable_start 226 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_SIMD8DispatchEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 226; + case 10: return 226; + case 9: return 226; + case 8: return 226; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VS::SIMD8 Single Instance Dispatch Enable */ + + +#define GEN11_3DSTATE_VS_SIMD8SingleInstanceDispatchEnable_bits 1 +#define GEN10_3DSTATE_VS_SIMD8SingleInstanceDispatchEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_SIMD8SingleInstanceDispatchEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VS_SIMD8SingleInstanceDispatchEnable_start 233 +#define GEN10_3DSTATE_VS_SIMD8SingleInstanceDispatchEnable_start 233 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_SIMD8SingleInstanceDispatchEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 233; + case 10: return 233; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VS::Sampler Count */ + + +#define GEN11_3DSTATE_VS_SamplerCount_bits 3 +#define GEN10_3DSTATE_VS_SamplerCount_bits 3 +#define GEN9_3DSTATE_VS_SamplerCount_bits 3 +#define GEN8_3DSTATE_VS_SamplerCount_bits 3 +#define GEN75_3DSTATE_VS_SamplerCount_bits 3 +#define GEN7_3DSTATE_VS_SamplerCount_bits 3 +#define GEN6_3DSTATE_VS_SamplerCount_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_SamplerCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VS_SamplerCount_start 123 +#define GEN10_3DSTATE_VS_SamplerCount_start 123 +#define GEN9_3DSTATE_VS_SamplerCount_start 123 +#define GEN8_3DSTATE_VS_SamplerCount_start 123 +#define GEN75_3DSTATE_VS_SamplerCount_start 91 +#define GEN7_3DSTATE_VS_SamplerCount_start 91 +#define GEN6_3DSTATE_VS_SamplerCount_start 91 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_SamplerCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 123; + case 10: return 123; + case 9: return 123; + case 8: return 123; + case 7: + if (devinfo->is_haswell) { + return 91; + } else { + return 91; + } + case 6: return 91; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VS::Scratch Space Base Pointer */ + + +#define GEN11_3DSTATE_VS_ScratchSpaceBasePointer_bits 54 +#define GEN10_3DSTATE_VS_ScratchSpaceBasePointer_bits 54 +#define GEN9_3DSTATE_VS_ScratchSpaceBasePointer_bits 54 +#define GEN8_3DSTATE_VS_ScratchSpaceBasePointer_bits 54 +#define GEN75_3DSTATE_VS_ScratchSpaceBasePointer_bits 22 +#define GEN7_3DSTATE_VS_ScratchSpaceBasePointer_bits 22 +#define GEN6_3DSTATE_VS_ScratchSpaceBasePointer_bits 22 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_ScratchSpaceBasePointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 54; + case 10: return 54; + case 9: return 54; + case 8: return 54; + case 7: + if (devinfo->is_haswell) { + return 22; + } else { + return 22; + } + case 6: return 22; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VS_ScratchSpaceBasePointer_start 138 +#define GEN10_3DSTATE_VS_ScratchSpaceBasePointer_start 138 +#define GEN9_3DSTATE_VS_ScratchSpaceBasePointer_start 138 +#define GEN8_3DSTATE_VS_ScratchSpaceBasePointer_start 138 +#define GEN75_3DSTATE_VS_ScratchSpaceBasePointer_start 106 +#define GEN7_3DSTATE_VS_ScratchSpaceBasePointer_start 106 +#define GEN6_3DSTATE_VS_ScratchSpaceBasePointer_start 106 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_ScratchSpaceBasePointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 138; + case 10: return 138; + case 9: return 138; + case 8: return 138; + case 7: + if (devinfo->is_haswell) { + return 106; + } else { + return 106; + } + case 6: return 106; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VS::Single Vertex Dispatch */ + + +#define GEN10_3DSTATE_VS_SingleVertexDispatch_bits 1 +#define GEN9_3DSTATE_VS_SingleVertexDispatch_bits 1 +#define GEN8_3DSTATE_VS_SingleVertexDispatch_bits 1 +#define GEN75_3DSTATE_VS_SingleVertexDispatch_bits 1 +#define GEN7_3DSTATE_VS_SingleVertexDispatch_bits 1 +#define GEN6_3DSTATE_VS_SingleVertexDispatch_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_SingleVertexDispatch_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_3DSTATE_VS_SingleVertexDispatch_start 127 +#define GEN9_3DSTATE_VS_SingleVertexDispatch_start 127 +#define GEN8_3DSTATE_VS_SingleVertexDispatch_start 127 +#define GEN75_3DSTATE_VS_SingleVertexDispatch_start 95 +#define GEN7_3DSTATE_VS_SingleVertexDispatch_start 95 +#define GEN6_3DSTATE_VS_SingleVertexDispatch_start 95 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_SingleVertexDispatch_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 127; + case 9: return 127; + case 8: return 127; + case 7: + if (devinfo->is_haswell) { + return 95; + } else { + return 95; + } + case 6: return 95; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VS::Software Exception Enable */ + + +#define GEN11_3DSTATE_VS_SoftwareExceptionEnable_bits 1 +#define GEN10_3DSTATE_VS_SoftwareExceptionEnable_bits 1 +#define GEN9_3DSTATE_VS_SoftwareExceptionEnable_bits 1 +#define GEN8_3DSTATE_VS_SoftwareExceptionEnable_bits 1 +#define GEN75_3DSTATE_VS_SoftwareExceptionEnable_bits 1 +#define GEN7_3DSTATE_VS_SoftwareExceptionEnable_bits 1 +#define GEN6_3DSTATE_VS_SoftwareExceptionEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_SoftwareExceptionEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VS_SoftwareExceptionEnable_start 103 +#define GEN10_3DSTATE_VS_SoftwareExceptionEnable_start 103 +#define GEN9_3DSTATE_VS_SoftwareExceptionEnable_start 103 +#define GEN8_3DSTATE_VS_SoftwareExceptionEnable_start 103 +#define GEN75_3DSTATE_VS_SoftwareExceptionEnable_start 71 +#define GEN7_3DSTATE_VS_SoftwareExceptionEnable_start 71 +#define GEN6_3DSTATE_VS_SoftwareExceptionEnable_start 71 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_SoftwareExceptionEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 103; + case 10: return 103; + case 9: return 103; + case 8: return 103; + case 7: + if (devinfo->is_haswell) { + return 71; + } else { + return 71; + } + case 6: return 71; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VS::Statistics Enable */ + + +#define GEN11_3DSTATE_VS_StatisticsEnable_bits 1 +#define GEN10_3DSTATE_VS_StatisticsEnable_bits 1 +#define GEN9_3DSTATE_VS_StatisticsEnable_bits 1 +#define GEN8_3DSTATE_VS_StatisticsEnable_bits 1 +#define GEN75_3DSTATE_VS_StatisticsEnable_bits 1 +#define GEN7_3DSTATE_VS_StatisticsEnable_bits 1 +#define GEN6_3DSTATE_VS_StatisticsEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_StatisticsEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VS_StatisticsEnable_start 234 +#define GEN10_3DSTATE_VS_StatisticsEnable_start 234 +#define GEN9_3DSTATE_VS_StatisticsEnable_start 234 +#define GEN8_3DSTATE_VS_StatisticsEnable_start 234 +#define GEN75_3DSTATE_VS_StatisticsEnable_start 170 +#define GEN7_3DSTATE_VS_StatisticsEnable_start 170 +#define GEN6_3DSTATE_VS_StatisticsEnable_start 170 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_StatisticsEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 234; + case 10: return 234; + case 9: return 234; + case 8: return 234; + case 7: + if (devinfo->is_haswell) { + return 170; + } else { + return 170; + } + case 6: return 170; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VS::Thread Dispatch Priority */ + + +#define GEN11_3DSTATE_VS_ThreadDispatchPriority_bits 1 +#define GEN10_3DSTATE_VS_ThreadDispatchPriority_bits 1 +#define GEN9_3DSTATE_VS_ThreadDispatchPriority_bits 1 +#define GEN8_3DSTATE_VS_ThreadDispatchPriority_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_ThreadDispatchPriority_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VS_ThreadDispatchPriority_start 113 +#define GEN10_3DSTATE_VS_ThreadDispatchPriority_start 113 +#define GEN9_3DSTATE_VS_ThreadDispatchPriority_start 113 +#define GEN8_3DSTATE_VS_ThreadDispatchPriority_start 113 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_ThreadDispatchPriority_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 113; + case 10: return 113; + case 9: return 113; + case 8: return 113; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VS::Thread Priority */ + + +#define GEN75_3DSTATE_VS_ThreadPriority_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_ThreadPriority_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_VS_ThreadPriority_start 81 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_ThreadPriority_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 81; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VS::User Clip Distance Clip Test Enable Bitmask */ + + +#define GEN11_3DSTATE_VS_UserClipDistanceClipTestEnableBitmask_bits 8 +#define GEN10_3DSTATE_VS_UserClipDistanceClipTestEnableBitmask_bits 8 +#define GEN9_3DSTATE_VS_UserClipDistanceClipTestEnableBitmask_bits 8 +#define GEN8_3DSTATE_VS_UserClipDistanceClipTestEnableBitmask_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_UserClipDistanceClipTestEnableBitmask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VS_UserClipDistanceClipTestEnableBitmask_start 264 +#define GEN10_3DSTATE_VS_UserClipDistanceClipTestEnableBitmask_start 264 +#define GEN9_3DSTATE_VS_UserClipDistanceClipTestEnableBitmask_start 264 +#define GEN8_3DSTATE_VS_UserClipDistanceClipTestEnableBitmask_start 264 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_UserClipDistanceClipTestEnableBitmask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 264; + case 10: return 264; + case 9: return 264; + case 8: return 264; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VS::User Clip Distance Cull Test Enable Bitmask */ + + +#define GEN11_3DSTATE_VS_UserClipDistanceCullTestEnableBitmask_bits 8 +#define GEN10_3DSTATE_VS_UserClipDistanceCullTestEnableBitmask_bits 8 +#define GEN9_3DSTATE_VS_UserClipDistanceCullTestEnableBitmask_bits 8 +#define GEN8_3DSTATE_VS_UserClipDistanceCullTestEnableBitmask_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_UserClipDistanceCullTestEnableBitmask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VS_UserClipDistanceCullTestEnableBitmask_start 256 +#define GEN10_3DSTATE_VS_UserClipDistanceCullTestEnableBitmask_start 256 +#define GEN9_3DSTATE_VS_UserClipDistanceCullTestEnableBitmask_start 256 +#define GEN8_3DSTATE_VS_UserClipDistanceCullTestEnableBitmask_start 256 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_UserClipDistanceCullTestEnableBitmask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 256; + case 10: return 256; + case 9: return 256; + case 8: return 256; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VS::VS accesses UAV */ + + +#define GEN75_3DSTATE_VS_VSaccessesUAV_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_VSaccessesUAV_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_VS_VSaccessesUAV_start 76 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_VSaccessesUAV_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 76; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VS::Vector Mask Enable */ + + +#define GEN11_3DSTATE_VS_VectorMaskEnable_bits 1 +#define GEN10_3DSTATE_VS_VectorMaskEnable_bits 1 +#define GEN9_3DSTATE_VS_VectorMaskEnable_bits 1 +#define GEN8_3DSTATE_VS_VectorMaskEnable_bits 1 +#define GEN75_3DSTATE_VS_VectorMaskEnable_bits 1 +#define GEN7_3DSTATE_VS_VectorMaskEnable_bits 1 +#define GEN6_3DSTATE_VS_VectorMaskEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_VectorMaskEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VS_VectorMaskEnable_start 126 +#define GEN10_3DSTATE_VS_VectorMaskEnable_start 126 +#define GEN9_3DSTATE_VS_VectorMaskEnable_start 126 +#define GEN8_3DSTATE_VS_VectorMaskEnable_start 126 +#define GEN75_3DSTATE_VS_VectorMaskEnable_start 94 +#define GEN7_3DSTATE_VS_VectorMaskEnable_start 94 +#define GEN6_3DSTATE_VS_VectorMaskEnable_start 94 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_VectorMaskEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 126; + case 10: return 126; + case 9: return 126; + case 8: return 126; + case 7: + if (devinfo->is_haswell) { + return 94; + } else { + return 94; + } + case 6: return 94; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VS::Vertex Cache Disable */ + + +#define GEN11_3DSTATE_VS_VertexCacheDisable_bits 1 +#define GEN10_3DSTATE_VS_VertexCacheDisable_bits 1 +#define GEN9_3DSTATE_VS_VertexCacheDisable_bits 1 +#define GEN8_3DSTATE_VS_VertexCacheDisable_bits 1 +#define GEN75_3DSTATE_VS_VertexCacheDisable_bits 1 +#define GEN7_3DSTATE_VS_VertexCacheDisable_bits 1 +#define GEN6_3DSTATE_VS_VertexCacheDisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_VertexCacheDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VS_VertexCacheDisable_start 225 +#define GEN10_3DSTATE_VS_VertexCacheDisable_start 225 +#define GEN9_3DSTATE_VS_VertexCacheDisable_start 225 +#define GEN8_3DSTATE_VS_VertexCacheDisable_start 225 +#define GEN75_3DSTATE_VS_VertexCacheDisable_start 161 +#define GEN7_3DSTATE_VS_VertexCacheDisable_start 161 +#define GEN6_3DSTATE_VS_VertexCacheDisable_start 161 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_VertexCacheDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 225; + case 10: return 225; + case 9: return 225; + case 8: return 225; + case 7: + if (devinfo->is_haswell) { + return 161; + } else { + return 161; + } + case 6: return 161; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VS::Vertex URB Entry Output Length */ + + +#define GEN11_3DSTATE_VS_VertexURBEntryOutputLength_bits 5 +#define GEN10_3DSTATE_VS_VertexURBEntryOutputLength_bits 5 +#define GEN9_3DSTATE_VS_VertexURBEntryOutputLength_bits 5 +#define GEN8_3DSTATE_VS_VertexURBEntryOutputLength_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_VertexURBEntryOutputLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VS_VertexURBEntryOutputLength_start 272 +#define GEN10_3DSTATE_VS_VertexURBEntryOutputLength_start 272 +#define GEN9_3DSTATE_VS_VertexURBEntryOutputLength_start 272 +#define GEN8_3DSTATE_VS_VertexURBEntryOutputLength_start 272 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_VertexURBEntryOutputLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 272; + case 10: return 272; + case 9: return 272; + case 8: return 272; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VS::Vertex URB Entry Output Read Offset */ + + +#define GEN11_3DSTATE_VS_VertexURBEntryOutputReadOffset_bits 6 +#define GEN10_3DSTATE_VS_VertexURBEntryOutputReadOffset_bits 6 +#define GEN9_3DSTATE_VS_VertexURBEntryOutputReadOffset_bits 6 +#define GEN8_3DSTATE_VS_VertexURBEntryOutputReadOffset_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_VertexURBEntryOutputReadOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VS_VertexURBEntryOutputReadOffset_start 277 +#define GEN10_3DSTATE_VS_VertexURBEntryOutputReadOffset_start 277 +#define GEN9_3DSTATE_VS_VertexURBEntryOutputReadOffset_start 277 +#define GEN8_3DSTATE_VS_VertexURBEntryOutputReadOffset_start 277 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_VertexURBEntryOutputReadOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 277; + case 10: return 277; + case 9: return 277; + case 8: return 277; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VS::Vertex URB Entry Read Length */ + + +#define GEN11_3DSTATE_VS_VertexURBEntryReadLength_bits 6 +#define GEN10_3DSTATE_VS_VertexURBEntryReadLength_bits 6 +#define GEN9_3DSTATE_VS_VertexURBEntryReadLength_bits 6 +#define GEN8_3DSTATE_VS_VertexURBEntryReadLength_bits 6 +#define GEN75_3DSTATE_VS_VertexURBEntryReadLength_bits 6 +#define GEN7_3DSTATE_VS_VertexURBEntryReadLength_bits 6 +#define GEN6_3DSTATE_VS_VertexURBEntryReadLength_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_VertexURBEntryReadLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 6; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VS_VertexURBEntryReadLength_start 203 +#define GEN10_3DSTATE_VS_VertexURBEntryReadLength_start 203 +#define GEN9_3DSTATE_VS_VertexURBEntryReadLength_start 203 +#define GEN8_3DSTATE_VS_VertexURBEntryReadLength_start 203 +#define GEN75_3DSTATE_VS_VertexURBEntryReadLength_start 139 +#define GEN7_3DSTATE_VS_VertexURBEntryReadLength_start 139 +#define GEN6_3DSTATE_VS_VertexURBEntryReadLength_start 139 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_VertexURBEntryReadLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 203; + case 10: return 203; + case 9: return 203; + case 8: return 203; + case 7: + if (devinfo->is_haswell) { + return 139; + } else { + return 139; + } + case 6: return 139; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_VS::Vertex URB Entry Read Offset */ + + +#define GEN11_3DSTATE_VS_VertexURBEntryReadOffset_bits 6 +#define GEN10_3DSTATE_VS_VertexURBEntryReadOffset_bits 6 +#define GEN9_3DSTATE_VS_VertexURBEntryReadOffset_bits 6 +#define GEN8_3DSTATE_VS_VertexURBEntryReadOffset_bits 6 +#define GEN75_3DSTATE_VS_VertexURBEntryReadOffset_bits 6 +#define GEN7_3DSTATE_VS_VertexURBEntryReadOffset_bits 6 +#define GEN6_3DSTATE_VS_VertexURBEntryReadOffset_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_VertexURBEntryReadOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 6; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_VS_VertexURBEntryReadOffset_start 196 +#define GEN10_3DSTATE_VS_VertexURBEntryReadOffset_start 196 +#define GEN9_3DSTATE_VS_VertexURBEntryReadOffset_start 196 +#define GEN8_3DSTATE_VS_VertexURBEntryReadOffset_start 196 +#define GEN75_3DSTATE_VS_VertexURBEntryReadOffset_start 132 +#define GEN7_3DSTATE_VS_VertexURBEntryReadOffset_start 132 +#define GEN6_3DSTATE_VS_VertexURBEntryReadOffset_start 132 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_VS_VertexURBEntryReadOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 196; + case 10: return 196; + case 9: return 196; + case 8: return 196; + case 7: + if (devinfo->is_haswell) { + return 132; + } else { + return 132; + } + case 6: return 132; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM */ + + +#define GEN11_3DSTATE_WM_length 2 +#define GEN10_3DSTATE_WM_length 2 +#define GEN9_3DSTATE_WM_length 2 +#define GEN8_3DSTATE_WM_length 2 +#define GEN75_3DSTATE_WM_length 3 +#define GEN7_3DSTATE_WM_length 3 +#define GEN6_3DSTATE_WM_length 9 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 9; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::16 Pixel Dispatch Enable */ + + +#define GEN6_3DSTATE_WM_16PixelDispatchEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_16PixelDispatchEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_WM_16PixelDispatchEnable_start 161 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_16PixelDispatchEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 161; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::32 Pixel Dispatch Enable */ + + +#define GEN6_3DSTATE_WM_32PixelDispatchEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_32PixelDispatchEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_WM_32PixelDispatchEnable_start 162 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_32PixelDispatchEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 162; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::3D Command Opcode */ + + +#define GEN11_3DSTATE_WM_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_WM_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_WM_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_WM_3DCommandOpcode_bits 3 +#define GEN75_3DSTATE_WM_3DCommandOpcode_bits 3 +#define GEN7_3DSTATE_WM_3DCommandOpcode_bits 3 +#define GEN6_3DSTATE_WM_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_WM_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_WM_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_WM_3DCommandOpcode_start 24 +#define GEN75_3DSTATE_WM_3DCommandOpcode_start 24 +#define GEN7_3DSTATE_WM_3DCommandOpcode_start 24 +#define GEN6_3DSTATE_WM_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_WM_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_WM_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_WM_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_WM_3DCommandSubOpcode_bits 8 +#define GEN75_3DSTATE_WM_3DCommandSubOpcode_bits 8 +#define GEN7_3DSTATE_WM_3DCommandSubOpcode_bits 8 +#define GEN6_3DSTATE_WM_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_WM_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_WM_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_WM_3DCommandSubOpcode_start 16 +#define GEN75_3DSTATE_WM_3DCommandSubOpcode_start 16 +#define GEN7_3DSTATE_WM_3DCommandSubOpcode_start 16 +#define GEN6_3DSTATE_WM_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::8 Pixel Dispatch Enable */ + + +#define GEN6_3DSTATE_WM_8PixelDispatchEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_8PixelDispatchEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_WM_8PixelDispatchEnable_start 160 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_8PixelDispatchEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 160; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Barycentric Interpolation Mode */ + + +#define GEN11_3DSTATE_WM_BarycentricInterpolationMode_bits 6 +#define GEN10_3DSTATE_WM_BarycentricInterpolationMode_bits 6 +#define GEN9_3DSTATE_WM_BarycentricInterpolationMode_bits 6 +#define GEN8_3DSTATE_WM_BarycentricInterpolationMode_bits 6 +#define GEN75_3DSTATE_WM_BarycentricInterpolationMode_bits 6 +#define GEN7_3DSTATE_WM_BarycentricInterpolationMode_bits 6 +#define GEN6_3DSTATE_WM_BarycentricInterpolationMode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_BarycentricInterpolationMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 6; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_BarycentricInterpolationMode_start 43 +#define GEN10_3DSTATE_WM_BarycentricInterpolationMode_start 43 +#define GEN9_3DSTATE_WM_BarycentricInterpolationMode_start 43 +#define GEN8_3DSTATE_WM_BarycentricInterpolationMode_start 43 +#define GEN75_3DSTATE_WM_BarycentricInterpolationMode_start 43 +#define GEN7_3DSTATE_WM_BarycentricInterpolationMode_start 43 +#define GEN6_3DSTATE_WM_BarycentricInterpolationMode_start 202 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_BarycentricInterpolationMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 43; + case 10: return 43; + case 9: return 43; + case 8: return 43; + case 7: + if (devinfo->is_haswell) { + return 43; + } else { + return 43; + } + case 6: return 202; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Binding Table Entry Count */ + + +#define GEN6_3DSTATE_WM_BindingTableEntryCount_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_BindingTableEntryCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_WM_BindingTableEntryCount_start 82 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_BindingTableEntryCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 82; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Command SubType */ + + +#define GEN11_3DSTATE_WM_CommandSubType_bits 2 +#define GEN10_3DSTATE_WM_CommandSubType_bits 2 +#define GEN9_3DSTATE_WM_CommandSubType_bits 2 +#define GEN8_3DSTATE_WM_CommandSubType_bits 2 +#define GEN75_3DSTATE_WM_CommandSubType_bits 2 +#define GEN7_3DSTATE_WM_CommandSubType_bits 2 +#define GEN6_3DSTATE_WM_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_CommandSubType_start 27 +#define GEN10_3DSTATE_WM_CommandSubType_start 27 +#define GEN9_3DSTATE_WM_CommandSubType_start 27 +#define GEN8_3DSTATE_WM_CommandSubType_start 27 +#define GEN75_3DSTATE_WM_CommandSubType_start 27 +#define GEN7_3DSTATE_WM_CommandSubType_start 27 +#define GEN6_3DSTATE_WM_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Command Type */ + + +#define GEN11_3DSTATE_WM_CommandType_bits 3 +#define GEN10_3DSTATE_WM_CommandType_bits 3 +#define GEN9_3DSTATE_WM_CommandType_bits 3 +#define GEN8_3DSTATE_WM_CommandType_bits 3 +#define GEN75_3DSTATE_WM_CommandType_bits 3 +#define GEN7_3DSTATE_WM_CommandType_bits 3 +#define GEN6_3DSTATE_WM_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_CommandType_start 29 +#define GEN10_3DSTATE_WM_CommandType_start 29 +#define GEN9_3DSTATE_WM_CommandType_start 29 +#define GEN8_3DSTATE_WM_CommandType_start 29 +#define GEN75_3DSTATE_WM_CommandType_start 29 +#define GEN7_3DSTATE_WM_CommandType_start 29 +#define GEN6_3DSTATE_WM_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::DWord Length */ + + +#define GEN11_3DSTATE_WM_DWordLength_bits 8 +#define GEN10_3DSTATE_WM_DWordLength_bits 8 +#define GEN9_3DSTATE_WM_DWordLength_bits 8 +#define GEN8_3DSTATE_WM_DWordLength_bits 8 +#define GEN75_3DSTATE_WM_DWordLength_bits 8 +#define GEN7_3DSTATE_WM_DWordLength_bits 8 +#define GEN6_3DSTATE_WM_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_DWordLength_start 0 +#define GEN10_3DSTATE_WM_DWordLength_start 0 +#define GEN9_3DSTATE_WM_DWordLength_start 0 +#define GEN8_3DSTATE_WM_DWordLength_start 0 +#define GEN75_3DSTATE_WM_DWordLength_start 0 +#define GEN7_3DSTATE_WM_DWordLength_start 0 +#define GEN6_3DSTATE_WM_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Depth Buffer Clear */ + + +#define GEN75_3DSTATE_WM_DepthBufferClear_bits 1 +#define GEN7_3DSTATE_WM_DepthBufferClear_bits 1 +#define GEN6_3DSTATE_WM_DepthBufferClear_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DepthBufferClear_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_WM_DepthBufferClear_start 62 +#define GEN7_3DSTATE_WM_DepthBufferClear_start 62 +#define GEN6_3DSTATE_WM_DepthBufferClear_start 158 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DepthBufferClear_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 62; + } else { + return 62; + } + case 6: return 158; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Depth Buffer Resolve Enable */ + + +#define GEN75_3DSTATE_WM_DepthBufferResolveEnable_bits 1 +#define GEN7_3DSTATE_WM_DepthBufferResolveEnable_bits 1 +#define GEN6_3DSTATE_WM_DepthBufferResolveEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DepthBufferResolveEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_WM_DepthBufferResolveEnable_start 60 +#define GEN7_3DSTATE_WM_DepthBufferResolveEnable_start 60 +#define GEN6_3DSTATE_WM_DepthBufferResolveEnable_start 156 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DepthBufferResolveEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 60; + } else { + return 60; + } + case 6: return 156; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Dispatch GRF Start Register For Constant/Setup Data 0 */ + + +#define GEN6_3DSTATE_WM_DispatchGRFStartRegisterForConstantSetupData0_bits 7 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DispatchGRFStartRegisterForConstantSetupData0_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 7; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_WM_DispatchGRFStartRegisterForConstantSetupData0_start 144 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DispatchGRFStartRegisterForConstantSetupData0_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 144; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Dispatch GRF Start Register For Constant/Setup Data 1 */ + + +#define GEN6_3DSTATE_WM_DispatchGRFStartRegisterForConstantSetupData1_bits 7 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DispatchGRFStartRegisterForConstantSetupData1_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 7; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_WM_DispatchGRFStartRegisterForConstantSetupData1_start 136 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DispatchGRFStartRegisterForConstantSetupData1_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 136; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Dispatch GRF Start Register For Constant/Setup Data 2 */ + + +#define GEN6_3DSTATE_WM_DispatchGRFStartRegisterForConstantSetupData2_bits 7 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DispatchGRFStartRegisterForConstantSetupData2_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 7; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_WM_DispatchGRFStartRegisterForConstantSetupData2_start 128 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DispatchGRFStartRegisterForConstantSetupData2_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 128; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Dual Source Blend Enable */ + + +#define GEN6_3DSTATE_WM_DualSourceBlendEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DualSourceBlendEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_WM_DualSourceBlendEnable_start 167 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DualSourceBlendEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 167; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Early Depth/Stencil Control */ + + +#define GEN11_3DSTATE_WM_EarlyDepthStencilControl_bits 2 +#define GEN10_3DSTATE_WM_EarlyDepthStencilControl_bits 2 +#define GEN9_3DSTATE_WM_EarlyDepthStencilControl_bits 2 +#define GEN8_3DSTATE_WM_EarlyDepthStencilControl_bits 2 +#define GEN75_3DSTATE_WM_EarlyDepthStencilControl_bits 2 +#define GEN7_3DSTATE_WM_EarlyDepthStencilControl_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_EarlyDepthStencilControl_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_EarlyDepthStencilControl_start 53 +#define GEN10_3DSTATE_WM_EarlyDepthStencilControl_start 53 +#define GEN9_3DSTATE_WM_EarlyDepthStencilControl_start 53 +#define GEN8_3DSTATE_WM_EarlyDepthStencilControl_start 53 +#define GEN75_3DSTATE_WM_EarlyDepthStencilControl_start 53 +#define GEN7_3DSTATE_WM_EarlyDepthStencilControl_start 53 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_EarlyDepthStencilControl_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 53; + case 10: return 53; + case 9: return 53; + case 8: return 53; + case 7: + if (devinfo->is_haswell) { + return 53; + } else { + return 53; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Floating Point Mode */ + + +#define GEN6_3DSTATE_WM_FloatingPointMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_FloatingPointMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_WM_FloatingPointMode_start 80 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_FloatingPointMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 80; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Force Kill Pixel Enable */ + + +#define GEN11_3DSTATE_WM_ForceKillPixelEnable_bits 2 +#define GEN10_3DSTATE_WM_ForceKillPixelEnable_bits 2 +#define GEN9_3DSTATE_WM_ForceKillPixelEnable_bits 2 +#define GEN8_3DSTATE_WM_ForceKillPixelEnable_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_ForceKillPixelEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_ForceKillPixelEnable_start 32 +#define GEN10_3DSTATE_WM_ForceKillPixelEnable_start 32 +#define GEN9_3DSTATE_WM_ForceKillPixelEnable_start 32 +#define GEN8_3DSTATE_WM_ForceKillPixelEnable_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_ForceKillPixelEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Force Thread Dispatch Enable */ + + +#define GEN11_3DSTATE_WM_ForceThreadDispatchEnable_bits 2 +#define GEN10_3DSTATE_WM_ForceThreadDispatchEnable_bits 2 +#define GEN9_3DSTATE_WM_ForceThreadDispatchEnable_bits 2 +#define GEN8_3DSTATE_WM_ForceThreadDispatchEnable_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_ForceThreadDispatchEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_ForceThreadDispatchEnable_start 51 +#define GEN10_3DSTATE_WM_ForceThreadDispatchEnable_start 51 +#define GEN9_3DSTATE_WM_ForceThreadDispatchEnable_start 51 +#define GEN8_3DSTATE_WM_ForceThreadDispatchEnable_start 51 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_ForceThreadDispatchEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 51; + case 10: return 51; + case 9: return 51; + case 8: return 51; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Hierarchical Depth Buffer Resolve Enable */ + + +#define GEN75_3DSTATE_WM_HierarchicalDepthBufferResolveEnable_bits 1 +#define GEN7_3DSTATE_WM_HierarchicalDepthBufferResolveEnable_bits 1 +#define GEN6_3DSTATE_WM_HierarchicalDepthBufferResolveEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HierarchicalDepthBufferResolveEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_WM_HierarchicalDepthBufferResolveEnable_start 59 +#define GEN7_3DSTATE_WM_HierarchicalDepthBufferResolveEnable_start 59 +#define GEN6_3DSTATE_WM_HierarchicalDepthBufferResolveEnable_start 155 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HierarchicalDepthBufferResolveEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 59; + } else { + return 59; + } + case 6: return 155; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Illegal Opcode Exception Enable */ + + +#define GEN6_3DSTATE_WM_IllegalOpcodeExceptionEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_IllegalOpcodeExceptionEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_WM_IllegalOpcodeExceptionEnable_start 77 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_IllegalOpcodeExceptionEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 77; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Kernel Start Pointer 0 */ + + +#define GEN6_3DSTATE_WM_KernelStartPointer0_bits 26 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_KernelStartPointer0_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 26; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_WM_KernelStartPointer0_start 38 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_KernelStartPointer0_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 38; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Kernel Start Pointer 1 */ + + +#define GEN6_3DSTATE_WM_KernelStartPointer1_bits 26 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_KernelStartPointer1_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 26; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_WM_KernelStartPointer1_start 230 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_KernelStartPointer1_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 230; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Kernel Start Pointer 2 */ + + +#define GEN6_3DSTATE_WM_KernelStartPointer2_bits 26 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_KernelStartPointer2_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 26; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_WM_KernelStartPointer2_start 262 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_KernelStartPointer2_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 262; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Legacy Depth Buffer Clear Enable */ + + +#define GEN11_3DSTATE_WM_LegacyDepthBufferClearEnable_bits 1 +#define GEN10_3DSTATE_WM_LegacyDepthBufferClearEnable_bits 1 +#define GEN9_3DSTATE_WM_LegacyDepthBufferClearEnable_bits 1 +#define GEN8_3DSTATE_WM_LegacyDepthBufferClearEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_LegacyDepthBufferClearEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_LegacyDepthBufferClearEnable_start 62 +#define GEN10_3DSTATE_WM_LegacyDepthBufferClearEnable_start 62 +#define GEN9_3DSTATE_WM_LegacyDepthBufferClearEnable_start 62 +#define GEN8_3DSTATE_WM_LegacyDepthBufferClearEnable_start 62 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_LegacyDepthBufferClearEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 62; + case 10: return 62; + case 9: return 62; + case 8: return 62; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Legacy Depth Buffer Resolve Enable */ + + +#define GEN11_3DSTATE_WM_LegacyDepthBufferResolveEnable_bits 1 +#define GEN10_3DSTATE_WM_LegacyDepthBufferResolveEnable_bits 1 +#define GEN9_3DSTATE_WM_LegacyDepthBufferResolveEnable_bits 1 +#define GEN8_3DSTATE_WM_LegacyDepthBufferResolveEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_LegacyDepthBufferResolveEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_LegacyDepthBufferResolveEnable_start 60 +#define GEN10_3DSTATE_WM_LegacyDepthBufferResolveEnable_start 60 +#define GEN9_3DSTATE_WM_LegacyDepthBufferResolveEnable_start 60 +#define GEN8_3DSTATE_WM_LegacyDepthBufferResolveEnable_start 60 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_LegacyDepthBufferResolveEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 60; + case 10: return 60; + case 9: return 60; + case 8: return 60; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Legacy Diamond Line Rasterization */ + + +#define GEN11_3DSTATE_WM_LegacyDiamondLineRasterization_bits 1 +#define GEN10_3DSTATE_WM_LegacyDiamondLineRasterization_bits 1 +#define GEN9_3DSTATE_WM_LegacyDiamondLineRasterization_bits 1 +#define GEN8_3DSTATE_WM_LegacyDiamondLineRasterization_bits 1 +#define GEN75_3DSTATE_WM_LegacyDiamondLineRasterization_bits 1 +#define GEN7_3DSTATE_WM_LegacyDiamondLineRasterization_bits 1 +#define GEN6_3DSTATE_WM_LegacyDiamondLineRasterization_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_LegacyDiamondLineRasterization_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_LegacyDiamondLineRasterization_start 58 +#define GEN10_3DSTATE_WM_LegacyDiamondLineRasterization_start 58 +#define GEN9_3DSTATE_WM_LegacyDiamondLineRasterization_start 58 +#define GEN8_3DSTATE_WM_LegacyDiamondLineRasterization_start 58 +#define GEN75_3DSTATE_WM_LegacyDiamondLineRasterization_start 58 +#define GEN7_3DSTATE_WM_LegacyDiamondLineRasterization_start 58 +#define GEN6_3DSTATE_WM_LegacyDiamondLineRasterization_start 183 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_LegacyDiamondLineRasterization_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 58; + case 10: return 58; + case 9: return 58; + case 8: return 58; + case 7: + if (devinfo->is_haswell) { + return 58; + } else { + return 58; + } + case 6: return 183; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Legacy Hierarchical Depth Buffer Resolve Enable */ + + +#define GEN11_3DSTATE_WM_LegacyHierarchicalDepthBufferResolveEnable_bits 1 +#define GEN10_3DSTATE_WM_LegacyHierarchicalDepthBufferResolveEnable_bits 1 +#define GEN9_3DSTATE_WM_LegacyHierarchicalDepthBufferResolveEnable_bits 1 +#define GEN8_3DSTATE_WM_LegacyHierarchicalDepthBufferResolveEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_LegacyHierarchicalDepthBufferResolveEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_LegacyHierarchicalDepthBufferResolveEnable_start 59 +#define GEN10_3DSTATE_WM_LegacyHierarchicalDepthBufferResolveEnable_start 59 +#define GEN9_3DSTATE_WM_LegacyHierarchicalDepthBufferResolveEnable_start 59 +#define GEN8_3DSTATE_WM_LegacyHierarchicalDepthBufferResolveEnable_start 59 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_LegacyHierarchicalDepthBufferResolveEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 59; + case 10: return 59; + case 9: return 59; + case 8: return 59; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Line Antialiasing Region Width */ + + +#define GEN11_3DSTATE_WM_LineAntialiasingRegionWidth_bits 2 +#define GEN10_3DSTATE_WM_LineAntialiasingRegionWidth_bits 2 +#define GEN9_3DSTATE_WM_LineAntialiasingRegionWidth_bits 2 +#define GEN8_3DSTATE_WM_LineAntialiasingRegionWidth_bits 2 +#define GEN75_3DSTATE_WM_LineAntialiasingRegionWidth_bits 2 +#define GEN7_3DSTATE_WM_LineAntialiasingRegionWidth_bits 2 +#define GEN6_3DSTATE_WM_LineAntialiasingRegionWidth_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_LineAntialiasingRegionWidth_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_LineAntialiasingRegionWidth_start 38 +#define GEN10_3DSTATE_WM_LineAntialiasingRegionWidth_start 38 +#define GEN9_3DSTATE_WM_LineAntialiasingRegionWidth_start 38 +#define GEN8_3DSTATE_WM_LineAntialiasingRegionWidth_start 38 +#define GEN75_3DSTATE_WM_LineAntialiasingRegionWidth_start 38 +#define GEN7_3DSTATE_WM_LineAntialiasingRegionWidth_start 38 +#define GEN6_3DSTATE_WM_LineAntialiasingRegionWidth_start 174 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_LineAntialiasingRegionWidth_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 38; + case 10: return 38; + case 9: return 38; + case 8: return 38; + case 7: + if (devinfo->is_haswell) { + return 38; + } else { + return 38; + } + case 6: return 174; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Line End Cap Antialiasing Region Width */ + + +#define GEN11_3DSTATE_WM_LineEndCapAntialiasingRegionWidth_bits 2 +#define GEN10_3DSTATE_WM_LineEndCapAntialiasingRegionWidth_bits 2 +#define GEN9_3DSTATE_WM_LineEndCapAntialiasingRegionWidth_bits 2 +#define GEN8_3DSTATE_WM_LineEndCapAntialiasingRegionWidth_bits 2 +#define GEN75_3DSTATE_WM_LineEndCapAntialiasingRegionWidth_bits 2 +#define GEN7_3DSTATE_WM_LineEndCapAntialiasingRegionWidth_bits 2 +#define GEN6_3DSTATE_WM_LineEndCapAntialiasingRegionWidth_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_LineEndCapAntialiasingRegionWidth_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_LineEndCapAntialiasingRegionWidth_start 40 +#define GEN10_3DSTATE_WM_LineEndCapAntialiasingRegionWidth_start 40 +#define GEN9_3DSTATE_WM_LineEndCapAntialiasingRegionWidth_start 40 +#define GEN8_3DSTATE_WM_LineEndCapAntialiasingRegionWidth_start 40 +#define GEN75_3DSTATE_WM_LineEndCapAntialiasingRegionWidth_start 40 +#define GEN7_3DSTATE_WM_LineEndCapAntialiasingRegionWidth_start 40 +#define GEN6_3DSTATE_WM_LineEndCapAntialiasingRegionWidth_start 176 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_LineEndCapAntialiasingRegionWidth_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 40; + case 10: return 40; + case 9: return 40; + case 8: return 40; + case 7: + if (devinfo->is_haswell) { + return 40; + } else { + return 40; + } + case 6: return 176; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Line Stipple Enable */ + + +#define GEN11_3DSTATE_WM_LineStippleEnable_bits 1 +#define GEN10_3DSTATE_WM_LineStippleEnable_bits 1 +#define GEN9_3DSTATE_WM_LineStippleEnable_bits 1 +#define GEN8_3DSTATE_WM_LineStippleEnable_bits 1 +#define GEN75_3DSTATE_WM_LineStippleEnable_bits 1 +#define GEN7_3DSTATE_WM_LineStippleEnable_bits 1 +#define GEN6_3DSTATE_WM_LineStippleEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_LineStippleEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_LineStippleEnable_start 35 +#define GEN10_3DSTATE_WM_LineStippleEnable_start 35 +#define GEN9_3DSTATE_WM_LineStippleEnable_start 35 +#define GEN8_3DSTATE_WM_LineStippleEnable_start 35 +#define GEN75_3DSTATE_WM_LineStippleEnable_start 35 +#define GEN7_3DSTATE_WM_LineStippleEnable_start 35 +#define GEN6_3DSTATE_WM_LineStippleEnable_start 171 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_LineStippleEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 35; + case 10: return 35; + case 9: return 35; + case 8: return 35; + case 7: + if (devinfo->is_haswell) { + return 35; + } else { + return 35; + } + case 6: return 171; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::MaskStack Exception Enable */ + + +#define GEN6_3DSTATE_WM_MaskStackExceptionEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_MaskStackExceptionEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_WM_MaskStackExceptionEnable_start 75 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_MaskStackExceptionEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 75; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Maximum Number of Threads */ + + +#define GEN6_3DSTATE_WM_MaximumNumberofThreads_bits 7 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_MaximumNumberofThreads_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 7; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_WM_MaximumNumberofThreads_start 185 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_MaximumNumberofThreads_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 185; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Multisample Dispatch Mode */ + + +#define GEN75_3DSTATE_WM_MultisampleDispatchMode_bits 1 +#define GEN7_3DSTATE_WM_MultisampleDispatchMode_bits 1 +#define GEN6_3DSTATE_WM_MultisampleDispatchMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_MultisampleDispatchMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_WM_MultisampleDispatchMode_start 95 +#define GEN7_3DSTATE_WM_MultisampleDispatchMode_start 95 +#define GEN6_3DSTATE_WM_MultisampleDispatchMode_start 192 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_MultisampleDispatchMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 95; + } else { + return 95; + } + case 6: return 192; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Multisample Rasterization Mode */ + + +#define GEN75_3DSTATE_WM_MultisampleRasterizationMode_bits 2 +#define GEN7_3DSTATE_WM_MultisampleRasterizationMode_bits 2 +#define GEN6_3DSTATE_WM_MultisampleRasterizationMode_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_MultisampleRasterizationMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_WM_MultisampleRasterizationMode_start 32 +#define GEN7_3DSTATE_WM_MultisampleRasterizationMode_start 32 +#define GEN6_3DSTATE_WM_MultisampleRasterizationMode_start 193 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_MultisampleRasterizationMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 193; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Number of SF Output Attributes */ + + +#define GEN6_3DSTATE_WM_NumberofSFOutputAttributes_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_NumberofSFOutputAttributes_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 6; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_WM_NumberofSFOutputAttributes_start 212 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_NumberofSFOutputAttributes_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 212; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::PS UAV-only */ + + +#define GEN75_3DSTATE_WM_PSUAVonly_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_PSUAVonly_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_WM_PSUAVonly_start 94 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_PSUAVonly_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 94; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Per Thread Scratch Space */ + + +#define GEN6_3DSTATE_WM_PerThreadScratchSpace_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_PerThreadScratchSpace_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_WM_PerThreadScratchSpace_start 96 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_PerThreadScratchSpace_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 96; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Pixel Shader Computed Depth */ + + +#define GEN6_3DSTATE_WM_PixelShaderComputedDepth_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_PixelShaderComputedDepth_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_WM_PixelShaderComputedDepth_start 181 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_PixelShaderComputedDepth_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 181; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Pixel Shader Computed Depth Mode */ + + +#define GEN75_3DSTATE_WM_PixelShaderComputedDepthMode_bits 2 +#define GEN7_3DSTATE_WM_PixelShaderComputedDepthMode_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_PixelShaderComputedDepthMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_WM_PixelShaderComputedDepthMode_start 55 +#define GEN7_3DSTATE_WM_PixelShaderComputedDepthMode_start 55 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_PixelShaderComputedDepthMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 55; + } else { + return 55; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Pixel Shader Kills Pixel */ + + +#define GEN75_3DSTATE_WM_PixelShaderKillsPixel_bits 1 +#define GEN7_3DSTATE_WM_PixelShaderKillsPixel_bits 1 +#define GEN6_3DSTATE_WM_PixelShaderKillsPixel_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_PixelShaderKillsPixel_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_WM_PixelShaderKillsPixel_start 57 +#define GEN7_3DSTATE_WM_PixelShaderKillsPixel_start 57 +#define GEN6_3DSTATE_WM_PixelShaderKillsPixel_start 182 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_PixelShaderKillsPixel_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 57; + } else { + return 57; + } + case 6: return 182; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Pixel Shader Uses Input Coverage Mask */ + + +#define GEN75_3DSTATE_WM_PixelShaderUsesInputCoverageMask_bits 1 +#define GEN7_3DSTATE_WM_PixelShaderUsesInputCoverageMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_PixelShaderUsesInputCoverageMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_WM_PixelShaderUsesInputCoverageMask_start 42 +#define GEN7_3DSTATE_WM_PixelShaderUsesInputCoverageMask_start 42 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_PixelShaderUsesInputCoverageMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 42; + } else { + return 42; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Pixel Shader Uses Source Depth */ + + +#define GEN75_3DSTATE_WM_PixelShaderUsesSourceDepth_bits 1 +#define GEN7_3DSTATE_WM_PixelShaderUsesSourceDepth_bits 1 +#define GEN6_3DSTATE_WM_PixelShaderUsesSourceDepth_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_PixelShaderUsesSourceDepth_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_WM_PixelShaderUsesSourceDepth_start 52 +#define GEN7_3DSTATE_WM_PixelShaderUsesSourceDepth_start 52 +#define GEN6_3DSTATE_WM_PixelShaderUsesSourceDepth_start 180 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_PixelShaderUsesSourceDepth_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 52; + } else { + return 52; + } + case 6: return 180; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Pixel Shader Uses Source W */ + + +#define GEN75_3DSTATE_WM_PixelShaderUsesSourceW_bits 1 +#define GEN7_3DSTATE_WM_PixelShaderUsesSourceW_bits 1 +#define GEN6_3DSTATE_WM_PixelShaderUsesSourceW_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_PixelShaderUsesSourceW_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_WM_PixelShaderUsesSourceW_start 51 +#define GEN7_3DSTATE_WM_PixelShaderUsesSourceW_start 51 +#define GEN6_3DSTATE_WM_PixelShaderUsesSourceW_start 168 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_PixelShaderUsesSourceW_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 51; + } else { + return 51; + } + case 6: return 168; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Point Rasterization Rule */ + + +#define GEN11_3DSTATE_WM_PointRasterizationRule_bits 1 +#define GEN10_3DSTATE_WM_PointRasterizationRule_bits 1 +#define GEN9_3DSTATE_WM_PointRasterizationRule_bits 1 +#define GEN8_3DSTATE_WM_PointRasterizationRule_bits 1 +#define GEN75_3DSTATE_WM_PointRasterizationRule_bits 1 +#define GEN7_3DSTATE_WM_PointRasterizationRule_bits 1 +#define GEN6_3DSTATE_WM_PointRasterizationRule_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_PointRasterizationRule_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_PointRasterizationRule_start 34 +#define GEN10_3DSTATE_WM_PointRasterizationRule_start 34 +#define GEN9_3DSTATE_WM_PointRasterizationRule_start 34 +#define GEN8_3DSTATE_WM_PointRasterizationRule_start 34 +#define GEN75_3DSTATE_WM_PointRasterizationRule_start 34 +#define GEN7_3DSTATE_WM_PointRasterizationRule_start 34 +#define GEN6_3DSTATE_WM_PointRasterizationRule_start 201 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_PointRasterizationRule_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 34; + case 10: return 34; + case 9: return 34; + case 8: return 34; + case 7: + if (devinfo->is_haswell) { + return 34; + } else { + return 34; + } + case 6: return 201; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Polygon Stipple Enable */ + + +#define GEN11_3DSTATE_WM_PolygonStippleEnable_bits 1 +#define GEN10_3DSTATE_WM_PolygonStippleEnable_bits 1 +#define GEN9_3DSTATE_WM_PolygonStippleEnable_bits 1 +#define GEN8_3DSTATE_WM_PolygonStippleEnable_bits 1 +#define GEN75_3DSTATE_WM_PolygonStippleEnable_bits 1 +#define GEN7_3DSTATE_WM_PolygonStippleEnable_bits 1 +#define GEN6_3DSTATE_WM_PolygonStippleEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_PolygonStippleEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_PolygonStippleEnable_start 36 +#define GEN10_3DSTATE_WM_PolygonStippleEnable_start 36 +#define GEN9_3DSTATE_WM_PolygonStippleEnable_start 36 +#define GEN8_3DSTATE_WM_PolygonStippleEnable_start 36 +#define GEN75_3DSTATE_WM_PolygonStippleEnable_start 36 +#define GEN7_3DSTATE_WM_PolygonStippleEnable_start 36 +#define GEN6_3DSTATE_WM_PolygonStippleEnable_start 173 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_PolygonStippleEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 36; + case 10: return 36; + case 9: return 36; + case 8: return 36; + case 7: + if (devinfo->is_haswell) { + return 36; + } else { + return 36; + } + case 6: return 173; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Position XY Offset Select */ + + +#define GEN6_3DSTATE_WM_PositionXYOffsetSelect_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_PositionXYOffsetSelect_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_WM_PositionXYOffsetSelect_start 210 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_PositionXYOffsetSelect_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 210; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Position ZW Interpolation Mode */ + + +#define GEN11_3DSTATE_WM_PositionZWInterpolationMode_bits 2 +#define GEN10_3DSTATE_WM_PositionZWInterpolationMode_bits 2 +#define GEN9_3DSTATE_WM_PositionZWInterpolationMode_bits 2 +#define GEN8_3DSTATE_WM_PositionZWInterpolationMode_bits 2 +#define GEN75_3DSTATE_WM_PositionZWInterpolationMode_bits 2 +#define GEN7_3DSTATE_WM_PositionZWInterpolationMode_bits 2 +#define GEN6_3DSTATE_WM_PositionZWInterpolationMode_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_PositionZWInterpolationMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_PositionZWInterpolationMode_start 49 +#define GEN10_3DSTATE_WM_PositionZWInterpolationMode_start 49 +#define GEN9_3DSTATE_WM_PositionZWInterpolationMode_start 49 +#define GEN8_3DSTATE_WM_PositionZWInterpolationMode_start 49 +#define GEN75_3DSTATE_WM_PositionZWInterpolationMode_start 49 +#define GEN7_3DSTATE_WM_PositionZWInterpolationMode_start 49 +#define GEN6_3DSTATE_WM_PositionZWInterpolationMode_start 208 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_PositionZWInterpolationMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 49; + case 10: return 49; + case 9: return 49; + case 8: return 49; + case 7: + if (devinfo->is_haswell) { + return 49; + } else { + return 49; + } + case 6: return 208; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::RT Independent Rasterization Enable */ + + +#define GEN75_3DSTATE_WM_RTIndependentRasterizationEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_RTIndependentRasterizationEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_WM_RTIndependentRasterizationEnable_start 37 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_RTIndependentRasterizationEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 37; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Sampler Count */ + + +#define GEN6_3DSTATE_WM_SamplerCount_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_SamplerCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_WM_SamplerCount_start 91 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_SamplerCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 91; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Scratch Space Base Pointer */ + + +#define GEN6_3DSTATE_WM_ScratchSpaceBasePointer_bits 22 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_ScratchSpaceBasePointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 22; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_WM_ScratchSpaceBasePointer_start 106 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_ScratchSpaceBasePointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 106; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Single Program Flow */ + + +#define GEN6_3DSTATE_WM_SingleProgramFlow_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_SingleProgramFlow_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_WM_SingleProgramFlow_start 95 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_SingleProgramFlow_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 95; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Software Exception Enable */ + + +#define GEN6_3DSTATE_WM_SoftwareExceptionEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_SoftwareExceptionEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_WM_SoftwareExceptionEnable_start 71 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_SoftwareExceptionEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 71; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Statistics Enable */ + + +#define GEN11_3DSTATE_WM_StatisticsEnable_bits 1 +#define GEN10_3DSTATE_WM_StatisticsEnable_bits 1 +#define GEN9_3DSTATE_WM_StatisticsEnable_bits 1 +#define GEN8_3DSTATE_WM_StatisticsEnable_bits 1 +#define GEN75_3DSTATE_WM_StatisticsEnable_bits 1 +#define GEN7_3DSTATE_WM_StatisticsEnable_bits 1 +#define GEN6_3DSTATE_WM_StatisticsEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_StatisticsEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_StatisticsEnable_start 63 +#define GEN10_3DSTATE_WM_StatisticsEnable_start 63 +#define GEN9_3DSTATE_WM_StatisticsEnable_start 63 +#define GEN8_3DSTATE_WM_StatisticsEnable_start 63 +#define GEN75_3DSTATE_WM_StatisticsEnable_start 63 +#define GEN7_3DSTATE_WM_StatisticsEnable_start 63 +#define GEN6_3DSTATE_WM_StatisticsEnable_start 159 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_StatisticsEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 63; + case 10: return 63; + case 9: return 63; + case 8: return 63; + case 7: + if (devinfo->is_haswell) { + return 63; + } else { + return 63; + } + case 6: return 159; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Thread Dispatch Enable */ + + +#define GEN75_3DSTATE_WM_ThreadDispatchEnable_bits 1 +#define GEN7_3DSTATE_WM_ThreadDispatchEnable_bits 1 +#define GEN6_3DSTATE_WM_ThreadDispatchEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_ThreadDispatchEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_3DSTATE_WM_ThreadDispatchEnable_start 61 +#define GEN7_3DSTATE_WM_ThreadDispatchEnable_start 61 +#define GEN6_3DSTATE_WM_ThreadDispatchEnable_start 179 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_ThreadDispatchEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 61; + } else { + return 61; + } + case 6: return 179; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Thread Priority */ + + +#define GEN6_3DSTATE_WM_ThreadPriority_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_ThreadPriority_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_WM_ThreadPriority_start 81 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_ThreadPriority_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 81; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::Vector Mask Enable */ + + +#define GEN6_3DSTATE_WM_VectorMaskEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_VectorMaskEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_WM_VectorMaskEnable_start 94 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_VectorMaskEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 94; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM::oMask Present to RenderTarget */ + + +#define GEN6_3DSTATE_WM_oMaskPresenttoRenderTarget_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_oMaskPresenttoRenderTarget_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_3DSTATE_WM_oMaskPresenttoRenderTarget_start 169 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_oMaskPresenttoRenderTarget_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 169; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_CHROMAKEY */ + + +#define GEN11_3DSTATE_WM_CHROMAKEY_length 2 +#define GEN10_3DSTATE_WM_CHROMAKEY_length 2 +#define GEN9_3DSTATE_WM_CHROMAKEY_length 2 +#define GEN8_3DSTATE_WM_CHROMAKEY_length 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_CHROMAKEY_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_CHROMAKEY::3D Command Opcode */ + + +#define GEN11_3DSTATE_WM_CHROMAKEY_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_WM_CHROMAKEY_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_WM_CHROMAKEY_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_WM_CHROMAKEY_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_CHROMAKEY_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_CHROMAKEY_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_WM_CHROMAKEY_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_WM_CHROMAKEY_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_WM_CHROMAKEY_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_CHROMAKEY_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_CHROMAKEY::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_WM_CHROMAKEY_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_WM_CHROMAKEY_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_WM_CHROMAKEY_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_WM_CHROMAKEY_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_CHROMAKEY_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_CHROMAKEY_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_WM_CHROMAKEY_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_WM_CHROMAKEY_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_WM_CHROMAKEY_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_CHROMAKEY_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_CHROMAKEY::ChromaKey Kill Enable */ + + +#define GEN11_3DSTATE_WM_CHROMAKEY_ChromaKeyKillEnable_bits 1 +#define GEN10_3DSTATE_WM_CHROMAKEY_ChromaKeyKillEnable_bits 1 +#define GEN9_3DSTATE_WM_CHROMAKEY_ChromaKeyKillEnable_bits 1 +#define GEN8_3DSTATE_WM_CHROMAKEY_ChromaKeyKillEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_CHROMAKEY_ChromaKeyKillEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_CHROMAKEY_ChromaKeyKillEnable_start 63 +#define GEN10_3DSTATE_WM_CHROMAKEY_ChromaKeyKillEnable_start 63 +#define GEN9_3DSTATE_WM_CHROMAKEY_ChromaKeyKillEnable_start 63 +#define GEN8_3DSTATE_WM_CHROMAKEY_ChromaKeyKillEnable_start 63 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_CHROMAKEY_ChromaKeyKillEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 63; + case 10: return 63; + case 9: return 63; + case 8: return 63; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_CHROMAKEY::Command SubType */ + + +#define GEN11_3DSTATE_WM_CHROMAKEY_CommandSubType_bits 2 +#define GEN10_3DSTATE_WM_CHROMAKEY_CommandSubType_bits 2 +#define GEN9_3DSTATE_WM_CHROMAKEY_CommandSubType_bits 2 +#define GEN8_3DSTATE_WM_CHROMAKEY_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_CHROMAKEY_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_CHROMAKEY_CommandSubType_start 27 +#define GEN10_3DSTATE_WM_CHROMAKEY_CommandSubType_start 27 +#define GEN9_3DSTATE_WM_CHROMAKEY_CommandSubType_start 27 +#define GEN8_3DSTATE_WM_CHROMAKEY_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_CHROMAKEY_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_CHROMAKEY::Command Type */ + + +#define GEN11_3DSTATE_WM_CHROMAKEY_CommandType_bits 3 +#define GEN10_3DSTATE_WM_CHROMAKEY_CommandType_bits 3 +#define GEN9_3DSTATE_WM_CHROMAKEY_CommandType_bits 3 +#define GEN8_3DSTATE_WM_CHROMAKEY_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_CHROMAKEY_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_CHROMAKEY_CommandType_start 29 +#define GEN10_3DSTATE_WM_CHROMAKEY_CommandType_start 29 +#define GEN9_3DSTATE_WM_CHROMAKEY_CommandType_start 29 +#define GEN8_3DSTATE_WM_CHROMAKEY_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_CHROMAKEY_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_CHROMAKEY::DWord Length */ + + +#define GEN11_3DSTATE_WM_CHROMAKEY_DWordLength_bits 8 +#define GEN10_3DSTATE_WM_CHROMAKEY_DWordLength_bits 8 +#define GEN9_3DSTATE_WM_CHROMAKEY_DWordLength_bits 8 +#define GEN8_3DSTATE_WM_CHROMAKEY_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_CHROMAKEY_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_CHROMAKEY_DWordLength_start 0 +#define GEN10_3DSTATE_WM_CHROMAKEY_DWordLength_start 0 +#define GEN9_3DSTATE_WM_CHROMAKEY_DWordLength_start 0 +#define GEN8_3DSTATE_WM_CHROMAKEY_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_CHROMAKEY_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_DEPTH_STENCIL */ + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_length 4 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_length 4 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_length 4 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_length 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_DEPTH_STENCIL::3D Command Opcode */ + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_DEPTH_STENCIL::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_DEPTH_STENCIL::Backface Stencil Fail Op */ + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilFailOp_bits 3 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilFailOp_bits 3 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilFailOp_bits 3 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilFailOp_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilFailOp_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilFailOp_start 49 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilFailOp_start 49 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilFailOp_start 49 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilFailOp_start 49 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilFailOp_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 49; + case 10: return 49; + case 9: return 49; + case 8: return 49; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_DEPTH_STENCIL::Backface Stencil Pass Depth Fail Op */ + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthFailOp_bits 3 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthFailOp_bits 3 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthFailOp_bits 3 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthFailOp_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthFailOp_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthFailOp_start 46 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthFailOp_start 46 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthFailOp_start 46 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthFailOp_start 46 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthFailOp_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 46; + case 10: return 46; + case 9: return 46; + case 8: return 46; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_DEPTH_STENCIL::Backface Stencil Pass Depth Pass Op */ + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthPassOp_bits 3 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthPassOp_bits 3 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthPassOp_bits 3 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthPassOp_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthPassOp_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthPassOp_start 43 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthPassOp_start 43 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthPassOp_start 43 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthPassOp_start 43 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilPassDepthPassOp_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 43; + case 10: return 43; + case 9: return 43; + case 8: return 43; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_DEPTH_STENCIL::Backface Stencil Reference Value */ + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilReferenceValue_bits 8 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilReferenceValue_bits 8 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilReferenceValue_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilReferenceValue_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilReferenceValue_start 96 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilReferenceValue_start 96 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilReferenceValue_start 96 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilReferenceValue_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 96; + case 10: return 96; + case 9: return 96; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_DEPTH_STENCIL::Backface Stencil Test Function */ + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestFunction_bits 3 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestFunction_bits 3 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestFunction_bits 3 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestFunction_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestFunction_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestFunction_start 52 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestFunction_start 52 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestFunction_start 52 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestFunction_start 52 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestFunction_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 52; + case 10: return 52; + case 9: return 52; + case 8: return 52; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_DEPTH_STENCIL::Backface Stencil Test Mask */ + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestMask_bits 8 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestMask_bits 8 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestMask_bits 8 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestMask_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestMask_start 72 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestMask_start 72 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestMask_start 72 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestMask_start 72 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilTestMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 72; + case 10: return 72; + case 9: return 72; + case 8: return 72; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_DEPTH_STENCIL::Backface Stencil Write Mask */ + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilWriteMask_bits 8 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilWriteMask_bits 8 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilWriteMask_bits 8 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilWriteMask_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilWriteMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilWriteMask_start 64 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilWriteMask_start 64 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilWriteMask_start 64 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilWriteMask_start 64 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_BackfaceStencilWriteMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_DEPTH_STENCIL::Command SubType */ + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_CommandSubType_bits 2 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_CommandSubType_bits 2 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_CommandSubType_bits 2 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_CommandSubType_start 27 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_CommandSubType_start 27 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_CommandSubType_start 27 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_DEPTH_STENCIL::Command Type */ + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_CommandType_bits 3 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_CommandType_bits 3 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_CommandType_bits 3 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_CommandType_start 29 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_CommandType_start 29 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_CommandType_start 29 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_DEPTH_STENCIL::DWord Length */ + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_DWordLength_bits 8 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_DWordLength_bits 8 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_DWordLength_bits 8 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_DWordLength_start 0 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_DWordLength_start 0 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_DWordLength_start 0 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_DEPTH_STENCIL::Depth Buffer Write Enable */ + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_DepthBufferWriteEnable_bits 1 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_DepthBufferWriteEnable_bits 1 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_DepthBufferWriteEnable_bits 1 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_DepthBufferWriteEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_DepthBufferWriteEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_DepthBufferWriteEnable_start 32 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_DepthBufferWriteEnable_start 32 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_DepthBufferWriteEnable_start 32 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_DepthBufferWriteEnable_start 32 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_DepthBufferWriteEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_DEPTH_STENCIL::Depth Test Enable */ + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_DepthTestEnable_bits 1 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_DepthTestEnable_bits 1 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_DepthTestEnable_bits 1 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_DepthTestEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_DepthTestEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_DepthTestEnable_start 33 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_DepthTestEnable_start 33 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_DepthTestEnable_start 33 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_DepthTestEnable_start 33 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_DepthTestEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 33; + case 10: return 33; + case 9: return 33; + case 8: return 33; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_DEPTH_STENCIL::Depth Test Function */ + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_DepthTestFunction_bits 3 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_DepthTestFunction_bits 3 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_DepthTestFunction_bits 3 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_DepthTestFunction_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_DepthTestFunction_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_DepthTestFunction_start 37 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_DepthTestFunction_start 37 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_DepthTestFunction_start 37 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_DepthTestFunction_start 37 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_DepthTestFunction_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 37; + case 10: return 37; + case 9: return 37; + case 8: return 37; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_DEPTH_STENCIL::Double Sided Stencil Enable */ + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_DoubleSidedStencilEnable_bits 1 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_DoubleSidedStencilEnable_bits 1 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_DoubleSidedStencilEnable_bits 1 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_DoubleSidedStencilEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_DoubleSidedStencilEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_DoubleSidedStencilEnable_start 36 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_DoubleSidedStencilEnable_start 36 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_DoubleSidedStencilEnable_start 36 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_DoubleSidedStencilEnable_start 36 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_DoubleSidedStencilEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 36; + case 10: return 36; + case 9: return 36; + case 8: return 36; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_DEPTH_STENCIL::Stencil Buffer Write Enable */ + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_StencilBufferWriteEnable_bits 1 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_StencilBufferWriteEnable_bits 1 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_StencilBufferWriteEnable_bits 1 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_StencilBufferWriteEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_StencilBufferWriteEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_StencilBufferWriteEnable_start 34 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_StencilBufferWriteEnable_start 34 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_StencilBufferWriteEnable_start 34 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_StencilBufferWriteEnable_start 34 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_StencilBufferWriteEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 34; + case 10: return 34; + case 9: return 34; + case 8: return 34; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_DEPTH_STENCIL::Stencil Fail Op */ + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_StencilFailOp_bits 3 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_StencilFailOp_bits 3 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_StencilFailOp_bits 3 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_StencilFailOp_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_StencilFailOp_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_StencilFailOp_start 61 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_StencilFailOp_start 61 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_StencilFailOp_start 61 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_StencilFailOp_start 61 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_StencilFailOp_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 61; + case 10: return 61; + case 9: return 61; + case 8: return 61; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_DEPTH_STENCIL::Stencil Pass Depth Fail Op */ + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthFailOp_bits 3 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthFailOp_bits 3 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthFailOp_bits 3 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthFailOp_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthFailOp_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthFailOp_start 58 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthFailOp_start 58 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthFailOp_start 58 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthFailOp_start 58 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthFailOp_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 58; + case 10: return 58; + case 9: return 58; + case 8: return 58; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_DEPTH_STENCIL::Stencil Pass Depth Pass Op */ + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthPassOp_bits 3 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthPassOp_bits 3 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthPassOp_bits 3 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthPassOp_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthPassOp_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthPassOp_start 55 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthPassOp_start 55 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthPassOp_start 55 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthPassOp_start 55 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_StencilPassDepthPassOp_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 55; + case 10: return 55; + case 9: return 55; + case 8: return 55; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_DEPTH_STENCIL::Stencil Reference Value */ + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_StencilReferenceValue_bits 8 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_StencilReferenceValue_bits 8 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_StencilReferenceValue_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_StencilReferenceValue_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_StencilReferenceValue_start 104 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_StencilReferenceValue_start 104 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_StencilReferenceValue_start 104 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_StencilReferenceValue_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 104; + case 10: return 104; + case 9: return 104; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_DEPTH_STENCIL::Stencil Test Enable */ + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_StencilTestEnable_bits 1 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_StencilTestEnable_bits 1 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_StencilTestEnable_bits 1 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_StencilTestEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_StencilTestEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_StencilTestEnable_start 35 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_StencilTestEnable_start 35 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_StencilTestEnable_start 35 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_StencilTestEnable_start 35 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_StencilTestEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 35; + case 10: return 35; + case 9: return 35; + case 8: return 35; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_DEPTH_STENCIL::Stencil Test Function */ + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_StencilTestFunction_bits 3 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_StencilTestFunction_bits 3 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_StencilTestFunction_bits 3 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_StencilTestFunction_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_StencilTestFunction_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_StencilTestFunction_start 40 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_StencilTestFunction_start 40 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_StencilTestFunction_start 40 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_StencilTestFunction_start 40 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_StencilTestFunction_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 40; + case 10: return 40; + case 9: return 40; + case 8: return 40; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_DEPTH_STENCIL::Stencil Test Mask */ + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_StencilTestMask_bits 8 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_StencilTestMask_bits 8 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_StencilTestMask_bits 8 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_StencilTestMask_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_StencilTestMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_StencilTestMask_start 88 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_StencilTestMask_start 88 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_StencilTestMask_start 88 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_StencilTestMask_start 88 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_StencilTestMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 88; + case 10: return 88; + case 9: return 88; + case 8: return 88; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_DEPTH_STENCIL::Stencil Write Mask */ + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_StencilWriteMask_bits 8 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_StencilWriteMask_bits 8 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_StencilWriteMask_bits 8 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_StencilWriteMask_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_StencilWriteMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_DEPTH_STENCIL_StencilWriteMask_start 80 +#define GEN10_3DSTATE_WM_DEPTH_STENCIL_StencilWriteMask_start 80 +#define GEN9_3DSTATE_WM_DEPTH_STENCIL_StencilWriteMask_start 80 +#define GEN8_3DSTATE_WM_DEPTH_STENCIL_StencilWriteMask_start 80 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_DEPTH_STENCIL_StencilWriteMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 80; + case 10: return 80; + case 9: return 80; + case 8: return 80; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_HZ_OP */ + + +#define GEN11_3DSTATE_WM_HZ_OP_length 5 +#define GEN10_3DSTATE_WM_HZ_OP_length 5 +#define GEN9_3DSTATE_WM_HZ_OP_length 5 +#define GEN8_3DSTATE_WM_HZ_OP_length 5 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_HZ_OP::3D Command Opcode */ + + +#define GEN11_3DSTATE_WM_HZ_OP_3DCommandOpcode_bits 3 +#define GEN10_3DSTATE_WM_HZ_OP_3DCommandOpcode_bits 3 +#define GEN9_3DSTATE_WM_HZ_OP_3DCommandOpcode_bits 3 +#define GEN8_3DSTATE_WM_HZ_OP_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_HZ_OP_3DCommandOpcode_start 24 +#define GEN10_3DSTATE_WM_HZ_OP_3DCommandOpcode_start 24 +#define GEN9_3DSTATE_WM_HZ_OP_3DCommandOpcode_start 24 +#define GEN8_3DSTATE_WM_HZ_OP_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_HZ_OP::3D Command Sub Opcode */ + + +#define GEN11_3DSTATE_WM_HZ_OP_3DCommandSubOpcode_bits 8 +#define GEN10_3DSTATE_WM_HZ_OP_3DCommandSubOpcode_bits 8 +#define GEN9_3DSTATE_WM_HZ_OP_3DCommandSubOpcode_bits 8 +#define GEN8_3DSTATE_WM_HZ_OP_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_HZ_OP_3DCommandSubOpcode_start 16 +#define GEN10_3DSTATE_WM_HZ_OP_3DCommandSubOpcode_start 16 +#define GEN9_3DSTATE_WM_HZ_OP_3DCommandSubOpcode_start 16 +#define GEN8_3DSTATE_WM_HZ_OP_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_HZ_OP::Clear Rectangle X Max */ + + +#define GEN11_3DSTATE_WM_HZ_OP_ClearRectangleXMax_bits 16 +#define GEN10_3DSTATE_WM_HZ_OP_ClearRectangleXMax_bits 16 +#define GEN9_3DSTATE_WM_HZ_OP_ClearRectangleXMax_bits 16 +#define GEN8_3DSTATE_WM_HZ_OP_ClearRectangleXMax_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_ClearRectangleXMax_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_HZ_OP_ClearRectangleXMax_start 96 +#define GEN10_3DSTATE_WM_HZ_OP_ClearRectangleXMax_start 96 +#define GEN9_3DSTATE_WM_HZ_OP_ClearRectangleXMax_start 96 +#define GEN8_3DSTATE_WM_HZ_OP_ClearRectangleXMax_start 96 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_ClearRectangleXMax_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 96; + case 10: return 96; + case 9: return 96; + case 8: return 96; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_HZ_OP::Clear Rectangle X Min */ + + +#define GEN11_3DSTATE_WM_HZ_OP_ClearRectangleXMin_bits 16 +#define GEN10_3DSTATE_WM_HZ_OP_ClearRectangleXMin_bits 16 +#define GEN9_3DSTATE_WM_HZ_OP_ClearRectangleXMin_bits 16 +#define GEN8_3DSTATE_WM_HZ_OP_ClearRectangleXMin_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_ClearRectangleXMin_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_HZ_OP_ClearRectangleXMin_start 64 +#define GEN10_3DSTATE_WM_HZ_OP_ClearRectangleXMin_start 64 +#define GEN9_3DSTATE_WM_HZ_OP_ClearRectangleXMin_start 64 +#define GEN8_3DSTATE_WM_HZ_OP_ClearRectangleXMin_start 64 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_ClearRectangleXMin_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_HZ_OP::Clear Rectangle Y Max */ + + +#define GEN11_3DSTATE_WM_HZ_OP_ClearRectangleYMax_bits 16 +#define GEN10_3DSTATE_WM_HZ_OP_ClearRectangleYMax_bits 16 +#define GEN9_3DSTATE_WM_HZ_OP_ClearRectangleYMax_bits 16 +#define GEN8_3DSTATE_WM_HZ_OP_ClearRectangleYMax_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_ClearRectangleYMax_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_HZ_OP_ClearRectangleYMax_start 112 +#define GEN10_3DSTATE_WM_HZ_OP_ClearRectangleYMax_start 112 +#define GEN9_3DSTATE_WM_HZ_OP_ClearRectangleYMax_start 112 +#define GEN8_3DSTATE_WM_HZ_OP_ClearRectangleYMax_start 112 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_ClearRectangleYMax_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 112; + case 10: return 112; + case 9: return 112; + case 8: return 112; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_HZ_OP::Clear Rectangle Y Min */ + + +#define GEN11_3DSTATE_WM_HZ_OP_ClearRectangleYMin_bits 16 +#define GEN10_3DSTATE_WM_HZ_OP_ClearRectangleYMin_bits 16 +#define GEN9_3DSTATE_WM_HZ_OP_ClearRectangleYMin_bits 16 +#define GEN8_3DSTATE_WM_HZ_OP_ClearRectangleYMin_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_ClearRectangleYMin_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_HZ_OP_ClearRectangleYMin_start 80 +#define GEN10_3DSTATE_WM_HZ_OP_ClearRectangleYMin_start 80 +#define GEN9_3DSTATE_WM_HZ_OP_ClearRectangleYMin_start 80 +#define GEN8_3DSTATE_WM_HZ_OP_ClearRectangleYMin_start 80 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_ClearRectangleYMin_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 80; + case 10: return 80; + case 9: return 80; + case 8: return 80; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_HZ_OP::Command SubType */ + + +#define GEN11_3DSTATE_WM_HZ_OP_CommandSubType_bits 2 +#define GEN10_3DSTATE_WM_HZ_OP_CommandSubType_bits 2 +#define GEN9_3DSTATE_WM_HZ_OP_CommandSubType_bits 2 +#define GEN8_3DSTATE_WM_HZ_OP_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_HZ_OP_CommandSubType_start 27 +#define GEN10_3DSTATE_WM_HZ_OP_CommandSubType_start 27 +#define GEN9_3DSTATE_WM_HZ_OP_CommandSubType_start 27 +#define GEN8_3DSTATE_WM_HZ_OP_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_HZ_OP::Command Type */ + + +#define GEN11_3DSTATE_WM_HZ_OP_CommandType_bits 3 +#define GEN10_3DSTATE_WM_HZ_OP_CommandType_bits 3 +#define GEN9_3DSTATE_WM_HZ_OP_CommandType_bits 3 +#define GEN8_3DSTATE_WM_HZ_OP_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_HZ_OP_CommandType_start 29 +#define GEN10_3DSTATE_WM_HZ_OP_CommandType_start 29 +#define GEN9_3DSTATE_WM_HZ_OP_CommandType_start 29 +#define GEN8_3DSTATE_WM_HZ_OP_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_HZ_OP::DWord Length */ + + +#define GEN11_3DSTATE_WM_HZ_OP_DWordLength_bits 8 +#define GEN10_3DSTATE_WM_HZ_OP_DWordLength_bits 8 +#define GEN9_3DSTATE_WM_HZ_OP_DWordLength_bits 8 +#define GEN8_3DSTATE_WM_HZ_OP_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_HZ_OP_DWordLength_start 0 +#define GEN10_3DSTATE_WM_HZ_OP_DWordLength_start 0 +#define GEN9_3DSTATE_WM_HZ_OP_DWordLength_start 0 +#define GEN8_3DSTATE_WM_HZ_OP_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_HZ_OP::Depth Buffer Clear Enable */ + + +#define GEN11_3DSTATE_WM_HZ_OP_DepthBufferClearEnable_bits 1 +#define GEN10_3DSTATE_WM_HZ_OP_DepthBufferClearEnable_bits 1 +#define GEN9_3DSTATE_WM_HZ_OP_DepthBufferClearEnable_bits 1 +#define GEN8_3DSTATE_WM_HZ_OP_DepthBufferClearEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_DepthBufferClearEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_HZ_OP_DepthBufferClearEnable_start 62 +#define GEN10_3DSTATE_WM_HZ_OP_DepthBufferClearEnable_start 62 +#define GEN9_3DSTATE_WM_HZ_OP_DepthBufferClearEnable_start 62 +#define GEN8_3DSTATE_WM_HZ_OP_DepthBufferClearEnable_start 62 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_DepthBufferClearEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 62; + case 10: return 62; + case 9: return 62; + case 8: return 62; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_HZ_OP::Depth Buffer Resolve Enable */ + + +#define GEN11_3DSTATE_WM_HZ_OP_DepthBufferResolveEnable_bits 1 +#define GEN10_3DSTATE_WM_HZ_OP_DepthBufferResolveEnable_bits 1 +#define GEN9_3DSTATE_WM_HZ_OP_DepthBufferResolveEnable_bits 1 +#define GEN8_3DSTATE_WM_HZ_OP_DepthBufferResolveEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_DepthBufferResolveEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_HZ_OP_DepthBufferResolveEnable_start 60 +#define GEN10_3DSTATE_WM_HZ_OP_DepthBufferResolveEnable_start 60 +#define GEN9_3DSTATE_WM_HZ_OP_DepthBufferResolveEnable_start 60 +#define GEN8_3DSTATE_WM_HZ_OP_DepthBufferResolveEnable_start 60 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_DepthBufferResolveEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 60; + case 10: return 60; + case 9: return 60; + case 8: return 60; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_HZ_OP::Full Surface Depth and Stencil Clear */ + + +#define GEN11_3DSTATE_WM_HZ_OP_FullSurfaceDepthandStencilClear_bits 1 +#define GEN10_3DSTATE_WM_HZ_OP_FullSurfaceDepthandStencilClear_bits 1 +#define GEN9_3DSTATE_WM_HZ_OP_FullSurfaceDepthandStencilClear_bits 1 +#define GEN8_3DSTATE_WM_HZ_OP_FullSurfaceDepthandStencilClear_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_FullSurfaceDepthandStencilClear_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_HZ_OP_FullSurfaceDepthandStencilClear_start 57 +#define GEN10_3DSTATE_WM_HZ_OP_FullSurfaceDepthandStencilClear_start 57 +#define GEN9_3DSTATE_WM_HZ_OP_FullSurfaceDepthandStencilClear_start 57 +#define GEN8_3DSTATE_WM_HZ_OP_FullSurfaceDepthandStencilClear_start 57 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_FullSurfaceDepthandStencilClear_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 57; + case 10: return 57; + case 9: return 57; + case 8: return 57; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_HZ_OP::Hierarchical Depth Buffer Resolve Enable */ + + +#define GEN11_3DSTATE_WM_HZ_OP_HierarchicalDepthBufferResolveEnable_bits 1 +#define GEN10_3DSTATE_WM_HZ_OP_HierarchicalDepthBufferResolveEnable_bits 1 +#define GEN9_3DSTATE_WM_HZ_OP_HierarchicalDepthBufferResolveEnable_bits 1 +#define GEN8_3DSTATE_WM_HZ_OP_HierarchicalDepthBufferResolveEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_HierarchicalDepthBufferResolveEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_HZ_OP_HierarchicalDepthBufferResolveEnable_start 59 +#define GEN10_3DSTATE_WM_HZ_OP_HierarchicalDepthBufferResolveEnable_start 59 +#define GEN9_3DSTATE_WM_HZ_OP_HierarchicalDepthBufferResolveEnable_start 59 +#define GEN8_3DSTATE_WM_HZ_OP_HierarchicalDepthBufferResolveEnable_start 59 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_HierarchicalDepthBufferResolveEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 59; + case 10: return 59; + case 9: return 59; + case 8: return 59; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_HZ_OP::Number of Multisamples */ + + +#define GEN11_3DSTATE_WM_HZ_OP_NumberofMultisamples_bits 3 +#define GEN10_3DSTATE_WM_HZ_OP_NumberofMultisamples_bits 3 +#define GEN9_3DSTATE_WM_HZ_OP_NumberofMultisamples_bits 3 +#define GEN8_3DSTATE_WM_HZ_OP_NumberofMultisamples_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_NumberofMultisamples_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_HZ_OP_NumberofMultisamples_start 45 +#define GEN10_3DSTATE_WM_HZ_OP_NumberofMultisamples_start 45 +#define GEN9_3DSTATE_WM_HZ_OP_NumberofMultisamples_start 45 +#define GEN8_3DSTATE_WM_HZ_OP_NumberofMultisamples_start 45 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_NumberofMultisamples_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 45; + case 10: return 45; + case 9: return 45; + case 8: return 45; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_HZ_OP::Pixel Position Offset Enable */ + + +#define GEN11_3DSTATE_WM_HZ_OP_PixelPositionOffsetEnable_bits 1 +#define GEN10_3DSTATE_WM_HZ_OP_PixelPositionOffsetEnable_bits 1 +#define GEN9_3DSTATE_WM_HZ_OP_PixelPositionOffsetEnable_bits 1 +#define GEN8_3DSTATE_WM_HZ_OP_PixelPositionOffsetEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_PixelPositionOffsetEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_HZ_OP_PixelPositionOffsetEnable_start 58 +#define GEN10_3DSTATE_WM_HZ_OP_PixelPositionOffsetEnable_start 58 +#define GEN9_3DSTATE_WM_HZ_OP_PixelPositionOffsetEnable_start 58 +#define GEN8_3DSTATE_WM_HZ_OP_PixelPositionOffsetEnable_start 58 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_PixelPositionOffsetEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 58; + case 10: return 58; + case 9: return 58; + case 8: return 58; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_HZ_OP::Sample Mask */ + + +#define GEN11_3DSTATE_WM_HZ_OP_SampleMask_bits 16 +#define GEN10_3DSTATE_WM_HZ_OP_SampleMask_bits 16 +#define GEN9_3DSTATE_WM_HZ_OP_SampleMask_bits 16 +#define GEN8_3DSTATE_WM_HZ_OP_SampleMask_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_SampleMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_HZ_OP_SampleMask_start 128 +#define GEN10_3DSTATE_WM_HZ_OP_SampleMask_start 128 +#define GEN9_3DSTATE_WM_HZ_OP_SampleMask_start 128 +#define GEN8_3DSTATE_WM_HZ_OP_SampleMask_start 128 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_SampleMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 128; + case 10: return 128; + case 9: return 128; + case 8: return 128; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_HZ_OP::Scissor Rectangle Enable */ + + +#define GEN11_3DSTATE_WM_HZ_OP_ScissorRectangleEnable_bits 1 +#define GEN10_3DSTATE_WM_HZ_OP_ScissorRectangleEnable_bits 1 +#define GEN9_3DSTATE_WM_HZ_OP_ScissorRectangleEnable_bits 1 +#define GEN8_3DSTATE_WM_HZ_OP_ScissorRectangleEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_ScissorRectangleEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_HZ_OP_ScissorRectangleEnable_start 61 +#define GEN10_3DSTATE_WM_HZ_OP_ScissorRectangleEnable_start 61 +#define GEN9_3DSTATE_WM_HZ_OP_ScissorRectangleEnable_start 61 +#define GEN8_3DSTATE_WM_HZ_OP_ScissorRectangleEnable_start 61 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_ScissorRectangleEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 61; + case 10: return 61; + case 9: return 61; + case 8: return 61; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_HZ_OP::Stencil Buffer Clear Enable */ + + +#define GEN11_3DSTATE_WM_HZ_OP_StencilBufferClearEnable_bits 1 +#define GEN10_3DSTATE_WM_HZ_OP_StencilBufferClearEnable_bits 1 +#define GEN9_3DSTATE_WM_HZ_OP_StencilBufferClearEnable_bits 1 +#define GEN8_3DSTATE_WM_HZ_OP_StencilBufferClearEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_StencilBufferClearEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_HZ_OP_StencilBufferClearEnable_start 63 +#define GEN10_3DSTATE_WM_HZ_OP_StencilBufferClearEnable_start 63 +#define GEN9_3DSTATE_WM_HZ_OP_StencilBufferClearEnable_start 63 +#define GEN8_3DSTATE_WM_HZ_OP_StencilBufferClearEnable_start 63 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_StencilBufferClearEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 63; + case 10: return 63; + case 9: return 63; + case 8: return 63; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* 3DSTATE_WM_HZ_OP::Stencil Clear Value */ + + +#define GEN11_3DSTATE_WM_HZ_OP_StencilClearValue_bits 8 +#define GEN10_3DSTATE_WM_HZ_OP_StencilClearValue_bits 8 +#define GEN9_3DSTATE_WM_HZ_OP_StencilClearValue_bits 8 +#define GEN8_3DSTATE_WM_HZ_OP_StencilClearValue_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_StencilClearValue_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_3DSTATE_WM_HZ_OP_StencilClearValue_start 48 +#define GEN10_3DSTATE_WM_HZ_OP_StencilClearValue_start 48 +#define GEN9_3DSTATE_WM_HZ_OP_StencilClearValue_start 48 +#define GEN8_3DSTATE_WM_HZ_OP_StencilClearValue_start 48 + +static inline uint32_t ATTRIBUTE_PURE +_3DSTATE_WM_HZ_OP_StencilClearValue_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 48; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* ACTHD_UDW */ + + +#define GEN9_ACTHD_UDW_length 1 +#define GEN8_ACTHD_UDW_length 1 + +static inline uint32_t ATTRIBUTE_PURE +ACTHD_UDW_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* ACTHD_UDW::Head Pointer Upper DWORD */ + + +#define GEN9_ACTHD_UDW_HeadPointerUpperDWORD_bits 16 +#define GEN8_ACTHD_UDW_HeadPointerUpperDWORD_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +ACTHD_UDW_HeadPointerUpperDWORD_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_ACTHD_UDW_HeadPointerUpperDWORD_start 0 +#define GEN8_ACTHD_UDW_HeadPointerUpperDWORD_start 0 + +static inline uint32_t ATTRIBUTE_PURE +ACTHD_UDW_HeadPointerUpperDWORD_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BCS_ACTHD_UDW */ + + +#define GEN9_BCS_ACTHD_UDW_length 1 +#define GEN8_BCS_ACTHD_UDW_length 1 + +static inline uint32_t ATTRIBUTE_PURE +BCS_ACTHD_UDW_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BCS_ACTHD_UDW::Head Pointer Upper DWORD */ + + +#define GEN9_BCS_ACTHD_UDW_HeadPointerUpperDWORD_bits 16 +#define GEN8_BCS_ACTHD_UDW_HeadPointerUpperDWORD_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +BCS_ACTHD_UDW_HeadPointerUpperDWORD_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_BCS_ACTHD_UDW_HeadPointerUpperDWORD_start 0 +#define GEN8_BCS_ACTHD_UDW_HeadPointerUpperDWORD_start 0 + +static inline uint32_t ATTRIBUTE_PURE +BCS_ACTHD_UDW_HeadPointerUpperDWORD_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BCS_FAULT_REG */ + + +#define GEN75_BCS_FAULT_REG_length 1 +#define GEN7_BCS_FAULT_REG_length 1 +#define GEN6_BCS_FAULT_REG_length 1 + +static inline uint32_t ATTRIBUTE_PURE +BCS_FAULT_REG_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BCS_FAULT_REG::Fault Type */ + + +#define GEN75_BCS_FAULT_REG_FaultType_bits 2 +#define GEN7_BCS_FAULT_REG_FaultType_bits 2 +#define GEN6_BCS_FAULT_REG_FaultType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +BCS_FAULT_REG_FaultType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_BCS_FAULT_REG_FaultType_start 1 +#define GEN7_BCS_FAULT_REG_FaultType_start 1 +#define GEN6_BCS_FAULT_REG_FaultType_start 1 + +static inline uint32_t ATTRIBUTE_PURE +BCS_FAULT_REG_FaultType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BCS_FAULT_REG::GTTSEL */ + + +#define GEN75_BCS_FAULT_REG_GTTSEL_bits 1 +#define GEN7_BCS_FAULT_REG_GTTSEL_bits 1 +#define GEN6_BCS_FAULT_REG_GTTSEL_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +BCS_FAULT_REG_GTTSEL_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_BCS_FAULT_REG_GTTSEL_start 11 +#define GEN7_BCS_FAULT_REG_GTTSEL_start 11 +#define GEN6_BCS_FAULT_REG_GTTSEL_start 11 + +static inline uint32_t ATTRIBUTE_PURE +BCS_FAULT_REG_GTTSEL_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 11; + } else { + return 11; + } + case 6: return 11; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BCS_FAULT_REG::SRCID of Fault */ + + +#define GEN75_BCS_FAULT_REG_SRCIDofFault_bits 8 +#define GEN7_BCS_FAULT_REG_SRCIDofFault_bits 8 +#define GEN6_BCS_FAULT_REG_SRCIDofFault_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +BCS_FAULT_REG_SRCIDofFault_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_BCS_FAULT_REG_SRCIDofFault_start 3 +#define GEN7_BCS_FAULT_REG_SRCIDofFault_start 3 +#define GEN6_BCS_FAULT_REG_SRCIDofFault_start 3 + +static inline uint32_t ATTRIBUTE_PURE +BCS_FAULT_REG_SRCIDofFault_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BCS_FAULT_REG::Valid Bit */ + + +#define GEN75_BCS_FAULT_REG_ValidBit_bits 1 +#define GEN7_BCS_FAULT_REG_ValidBit_bits 1 +#define GEN6_BCS_FAULT_REG_ValidBit_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +BCS_FAULT_REG_ValidBit_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_BCS_FAULT_REG_ValidBit_start 0 +#define GEN7_BCS_FAULT_REG_ValidBit_start 0 +#define GEN6_BCS_FAULT_REG_ValidBit_start 0 + +static inline uint32_t ATTRIBUTE_PURE +BCS_FAULT_REG_ValidBit_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BCS_FAULT_REG::Virtual Address of Fault */ + + +#define GEN75_BCS_FAULT_REG_VirtualAddressofFault_bits 20 +#define GEN7_BCS_FAULT_REG_VirtualAddressofFault_bits 20 +#define GEN6_BCS_FAULT_REG_VirtualAddressofFault_bits 20 + +static inline uint32_t ATTRIBUTE_PURE +BCS_FAULT_REG_VirtualAddressofFault_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 20; + } else { + return 20; + } + case 6: return 20; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_BCS_FAULT_REG_VirtualAddressofFault_start 12 +#define GEN7_BCS_FAULT_REG_VirtualAddressofFault_start 12 +#define GEN6_BCS_FAULT_REG_VirtualAddressofFault_start 12 + +static inline uint32_t ATTRIBUTE_PURE +BCS_FAULT_REG_VirtualAddressofFault_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 12; + } else { + return 12; + } + case 6: return 12; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BCS_INSTDONE */ + + +#define GEN11_BCS_INSTDONE_length 1 +#define GEN10_BCS_INSTDONE_length 1 +#define GEN9_BCS_INSTDONE_length 1 +#define GEN8_BCS_INSTDONE_length 1 +#define GEN75_BCS_INSTDONE_length 1 +#define GEN7_BCS_INSTDONE_length 1 +#define GEN6_BCS_INSTDONE_length 1 + +static inline uint32_t ATTRIBUTE_PURE +BCS_INSTDONE_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BCS_INSTDONE::BCS Done */ + + +#define GEN11_BCS_INSTDONE_BCSDone_bits 1 +#define GEN10_BCS_INSTDONE_BCSDone_bits 1 +#define GEN9_BCS_INSTDONE_BCSDone_bits 1 +#define GEN8_BCS_INSTDONE_BCSDone_bits 1 +#define GEN75_BCS_INSTDONE_BCSDone_bits 1 +#define GEN7_BCS_INSTDONE_BCSDone_bits 1 +#define GEN6_BCS_INSTDONE_BCSDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +BCS_INSTDONE_BCSDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_BCS_INSTDONE_BCSDone_start 3 +#define GEN10_BCS_INSTDONE_BCSDone_start 3 +#define GEN9_BCS_INSTDONE_BCSDone_start 3 +#define GEN8_BCS_INSTDONE_BCSDone_start 3 +#define GEN75_BCS_INSTDONE_BCSDone_start 3 +#define GEN7_BCS_INSTDONE_BCSDone_start 3 +#define GEN6_BCS_INSTDONE_BCSDone_start 3 + +static inline uint32_t ATTRIBUTE_PURE +BCS_INSTDONE_BCSDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BCS_INSTDONE::Blitter IDLE */ + + +#define GEN11_BCS_INSTDONE_BlitterIDLE_bits 1 +#define GEN10_BCS_INSTDONE_BlitterIDLE_bits 1 +#define GEN9_BCS_INSTDONE_BlitterIDLE_bits 1 +#define GEN8_BCS_INSTDONE_BlitterIDLE_bits 1 +#define GEN75_BCS_INSTDONE_BlitterIDLE_bits 1 +#define GEN7_BCS_INSTDONE_BlitterIDLE_bits 1 +#define GEN6_BCS_INSTDONE_BlitterIDLE_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +BCS_INSTDONE_BlitterIDLE_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_BCS_INSTDONE_BlitterIDLE_start 1 +#define GEN10_BCS_INSTDONE_BlitterIDLE_start 1 +#define GEN9_BCS_INSTDONE_BlitterIDLE_start 1 +#define GEN8_BCS_INSTDONE_BlitterIDLE_start 1 +#define GEN75_BCS_INSTDONE_BlitterIDLE_start 1 +#define GEN7_BCS_INSTDONE_BlitterIDLE_start 1 +#define GEN6_BCS_INSTDONE_BlitterIDLE_start 1 + +static inline uint32_t ATTRIBUTE_PURE +BCS_INSTDONE_BlitterIDLE_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BCS_INSTDONE::GAB IDLE */ + + +#define GEN11_BCS_INSTDONE_GABIDLE_bits 1 +#define GEN10_BCS_INSTDONE_GABIDLE_bits 1 +#define GEN9_BCS_INSTDONE_GABIDLE_bits 1 +#define GEN8_BCS_INSTDONE_GABIDLE_bits 1 +#define GEN75_BCS_INSTDONE_GABIDLE_bits 1 +#define GEN7_BCS_INSTDONE_GABIDLE_bits 1 +#define GEN6_BCS_INSTDONE_GABIDLE_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +BCS_INSTDONE_GABIDLE_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_BCS_INSTDONE_GABIDLE_start 2 +#define GEN10_BCS_INSTDONE_GABIDLE_start 2 +#define GEN9_BCS_INSTDONE_GABIDLE_start 2 +#define GEN8_BCS_INSTDONE_GABIDLE_start 2 +#define GEN75_BCS_INSTDONE_GABIDLE_start 2 +#define GEN7_BCS_INSTDONE_GABIDLE_start 2 +#define GEN6_BCS_INSTDONE_GABIDLE_start 2 + +static inline uint32_t ATTRIBUTE_PURE +BCS_INSTDONE_GABIDLE_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BCS_INSTDONE::Ring Enable */ + + +#define GEN11_BCS_INSTDONE_RingEnable_bits 1 +#define GEN10_BCS_INSTDONE_RingEnable_bits 1 +#define GEN9_BCS_INSTDONE_RingEnable_bits 1 +#define GEN8_BCS_INSTDONE_RingEnable_bits 1 +#define GEN75_BCS_INSTDONE_RingEnable_bits 1 +#define GEN7_BCS_INSTDONE_RingEnable_bits 1 +#define GEN6_BCS_INSTDONE_RingEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +BCS_INSTDONE_RingEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_BCS_INSTDONE_RingEnable_start 0 +#define GEN10_BCS_INSTDONE_RingEnable_start 0 +#define GEN9_BCS_INSTDONE_RingEnable_start 0 +#define GEN8_BCS_INSTDONE_RingEnable_start 0 +#define GEN75_BCS_INSTDONE_RingEnable_start 0 +#define GEN7_BCS_INSTDONE_RingEnable_start 0 +#define GEN6_BCS_INSTDONE_RingEnable_start 0 + +static inline uint32_t ATTRIBUTE_PURE +BCS_INSTDONE_RingEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BCS_RING_BUFFER_CTL */ + + +#define GEN9_BCS_RING_BUFFER_CTL_length 1 +#define GEN8_BCS_RING_BUFFER_CTL_length 1 +#define GEN75_BCS_RING_BUFFER_CTL_length 1 +#define GEN7_BCS_RING_BUFFER_CTL_length 1 +#define GEN6_BCS_RING_BUFFER_CTL_length 1 + +static inline uint32_t ATTRIBUTE_PURE +BCS_RING_BUFFER_CTL_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BCS_RING_BUFFER_CTL::Automatic Report Head Pointer */ + + +#define GEN9_BCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 +#define GEN8_BCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 +#define GEN75_BCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 +#define GEN7_BCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 +#define GEN6_BCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +BCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_BCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 +#define GEN8_BCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 +#define GEN75_BCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 +#define GEN7_BCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 +#define GEN6_BCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 + +static inline uint32_t ATTRIBUTE_PURE +BCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BCS_RING_BUFFER_CTL::Buffer Length (in pages - 1) */ + + +#define GEN9_BCS_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 +#define GEN8_BCS_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 +#define GEN75_BCS_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 +#define GEN7_BCS_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 +#define GEN6_BCS_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +BCS_RING_BUFFER_CTL_BufferLengthinpages1_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 9; + } + case 6: return 9; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_BCS_RING_BUFFER_CTL_BufferLengthinpages1_start 12 +#define GEN8_BCS_RING_BUFFER_CTL_BufferLengthinpages1_start 12 +#define GEN75_BCS_RING_BUFFER_CTL_BufferLengthinpages1_start 12 +#define GEN7_BCS_RING_BUFFER_CTL_BufferLengthinpages1_start 12 +#define GEN6_BCS_RING_BUFFER_CTL_BufferLengthinpages1_start 12 + +static inline uint32_t ATTRIBUTE_PURE +BCS_RING_BUFFER_CTL_BufferLengthinpages1_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 12; + case 8: return 12; + case 7: + if (devinfo->is_haswell) { + return 12; + } else { + return 12; + } + case 6: return 12; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BCS_RING_BUFFER_CTL::Disable Register Accesses */ + + +#define GEN9_BCS_RING_BUFFER_CTL_DisableRegisterAccesses_bits 1 +#define GEN8_BCS_RING_BUFFER_CTL_DisableRegisterAccesses_bits 1 +#define GEN75_BCS_RING_BUFFER_CTL_DisableRegisterAccesses_bits 1 +#define GEN7_BCS_RING_BUFFER_CTL_DisableRegisterAccesses_bits 1 +#define GEN6_BCS_RING_BUFFER_CTL_DisableRegisterAccesses_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +BCS_RING_BUFFER_CTL_DisableRegisterAccesses_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_BCS_RING_BUFFER_CTL_DisableRegisterAccesses_start 8 +#define GEN8_BCS_RING_BUFFER_CTL_DisableRegisterAccesses_start 8 +#define GEN75_BCS_RING_BUFFER_CTL_DisableRegisterAccesses_start 8 +#define GEN7_BCS_RING_BUFFER_CTL_DisableRegisterAccesses_start 8 +#define GEN6_BCS_RING_BUFFER_CTL_DisableRegisterAccesses_start 8 + +static inline uint32_t ATTRIBUTE_PURE +BCS_RING_BUFFER_CTL_DisableRegisterAccesses_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BCS_RING_BUFFER_CTL::RBWait */ + + +#define GEN9_BCS_RING_BUFFER_CTL_RBWait_bits 1 +#define GEN8_BCS_RING_BUFFER_CTL_RBWait_bits 1 +#define GEN75_BCS_RING_BUFFER_CTL_RBWait_bits 1 +#define GEN7_BCS_RING_BUFFER_CTL_RBWait_bits 1 +#define GEN6_BCS_RING_BUFFER_CTL_RBWait_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +BCS_RING_BUFFER_CTL_RBWait_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_BCS_RING_BUFFER_CTL_RBWait_start 11 +#define GEN8_BCS_RING_BUFFER_CTL_RBWait_start 11 +#define GEN75_BCS_RING_BUFFER_CTL_RBWait_start 11 +#define GEN7_BCS_RING_BUFFER_CTL_RBWait_start 11 +#define GEN6_BCS_RING_BUFFER_CTL_RBWait_start 11 + +static inline uint32_t ATTRIBUTE_PURE +BCS_RING_BUFFER_CTL_RBWait_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 11; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 11; + } else { + return 11; + } + case 6: return 11; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BCS_RING_BUFFER_CTL::Ring Buffer Enable */ + + +#define GEN9_BCS_RING_BUFFER_CTL_RingBufferEnable_bits 1 +#define GEN8_BCS_RING_BUFFER_CTL_RingBufferEnable_bits 1 +#define GEN75_BCS_RING_BUFFER_CTL_RingBufferEnable_bits 1 +#define GEN7_BCS_RING_BUFFER_CTL_RingBufferEnable_bits 1 +#define GEN6_BCS_RING_BUFFER_CTL_RingBufferEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +BCS_RING_BUFFER_CTL_RingBufferEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_BCS_RING_BUFFER_CTL_RingBufferEnable_start 0 +#define GEN8_BCS_RING_BUFFER_CTL_RingBufferEnable_start 0 +#define GEN75_BCS_RING_BUFFER_CTL_RingBufferEnable_start 0 +#define GEN7_BCS_RING_BUFFER_CTL_RingBufferEnable_start 0 +#define GEN6_BCS_RING_BUFFER_CTL_RingBufferEnable_start 0 + +static inline uint32_t ATTRIBUTE_PURE +BCS_RING_BUFFER_CTL_RingBufferEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BCS_RING_BUFFER_CTL::Semaphore Wait */ + + +#define GEN9_BCS_RING_BUFFER_CTL_SemaphoreWait_bits 1 +#define GEN8_BCS_RING_BUFFER_CTL_SemaphoreWait_bits 1 +#define GEN75_BCS_RING_BUFFER_CTL_SemaphoreWait_bits 1 +#define GEN7_BCS_RING_BUFFER_CTL_SemaphoreWait_bits 1 +#define GEN6_BCS_RING_BUFFER_CTL_SemaphoreWait_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +BCS_RING_BUFFER_CTL_SemaphoreWait_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_BCS_RING_BUFFER_CTL_SemaphoreWait_start 10 +#define GEN8_BCS_RING_BUFFER_CTL_SemaphoreWait_start 10 +#define GEN75_BCS_RING_BUFFER_CTL_SemaphoreWait_start 10 +#define GEN7_BCS_RING_BUFFER_CTL_SemaphoreWait_start 10 +#define GEN6_BCS_RING_BUFFER_CTL_SemaphoreWait_start 10 + +static inline uint32_t ATTRIBUTE_PURE +BCS_RING_BUFFER_CTL_SemaphoreWait_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 10; + case 8: return 10; + case 7: + if (devinfo->is_haswell) { + return 10; + } else { + return 10; + } + case 6: return 10; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BINDING_TABLE_EDIT_ENTRY */ + + +#define GEN11_BINDING_TABLE_EDIT_ENTRY_length 1 +#define GEN10_BINDING_TABLE_EDIT_ENTRY_length 1 +#define GEN9_BINDING_TABLE_EDIT_ENTRY_length 1 +#define GEN8_BINDING_TABLE_EDIT_ENTRY_length 1 +#define GEN75_BINDING_TABLE_EDIT_ENTRY_length 1 + +static inline uint32_t ATTRIBUTE_PURE +BINDING_TABLE_EDIT_ENTRY_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BINDING_TABLE_EDIT_ENTRY::Binding Table Index */ + + +#define GEN11_BINDING_TABLE_EDIT_ENTRY_BindingTableIndex_bits 8 +#define GEN10_BINDING_TABLE_EDIT_ENTRY_BindingTableIndex_bits 8 +#define GEN9_BINDING_TABLE_EDIT_ENTRY_BindingTableIndex_bits 8 +#define GEN8_BINDING_TABLE_EDIT_ENTRY_BindingTableIndex_bits 8 +#define GEN75_BINDING_TABLE_EDIT_ENTRY_BindingTableIndex_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +BINDING_TABLE_EDIT_ENTRY_BindingTableIndex_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_BINDING_TABLE_EDIT_ENTRY_BindingTableIndex_start 16 +#define GEN10_BINDING_TABLE_EDIT_ENTRY_BindingTableIndex_start 16 +#define GEN9_BINDING_TABLE_EDIT_ENTRY_BindingTableIndex_start 16 +#define GEN8_BINDING_TABLE_EDIT_ENTRY_BindingTableIndex_start 16 +#define GEN75_BINDING_TABLE_EDIT_ENTRY_BindingTableIndex_start 16 + +static inline uint32_t ATTRIBUTE_PURE +BINDING_TABLE_EDIT_ENTRY_BindingTableIndex_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BINDING_TABLE_EDIT_ENTRY::Surface State Pointer */ + + +#define GEN11_BINDING_TABLE_EDIT_ENTRY_SurfaceStatePointer_bits 16 +#define GEN10_BINDING_TABLE_EDIT_ENTRY_SurfaceStatePointer_bits 16 +#define GEN9_BINDING_TABLE_EDIT_ENTRY_SurfaceStatePointer_bits 16 +#define GEN8_BINDING_TABLE_EDIT_ENTRY_SurfaceStatePointer_bits 16 +#define GEN75_BINDING_TABLE_EDIT_ENTRY_SurfaceStatePointer_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +BINDING_TABLE_EDIT_ENTRY_SurfaceStatePointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_BINDING_TABLE_EDIT_ENTRY_SurfaceStatePointer_start 0 +#define GEN10_BINDING_TABLE_EDIT_ENTRY_SurfaceStatePointer_start 0 +#define GEN9_BINDING_TABLE_EDIT_ENTRY_SurfaceStatePointer_start 0 +#define GEN8_BINDING_TABLE_EDIT_ENTRY_SurfaceStatePointer_start 0 +#define GEN75_BINDING_TABLE_EDIT_ENTRY_SurfaceStatePointer_start 0 + +static inline uint32_t ATTRIBUTE_PURE +BINDING_TABLE_EDIT_ENTRY_SurfaceStatePointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BINDING_TABLE_STATE */ + + +#define GEN11_BINDING_TABLE_STATE_length 1 +#define GEN10_BINDING_TABLE_STATE_length 1 +#define GEN9_BINDING_TABLE_STATE_length 1 +#define GEN8_BINDING_TABLE_STATE_length 1 +#define GEN75_BINDING_TABLE_STATE_length 1 +#define GEN7_BINDING_TABLE_STATE_length 1 +#define GEN6_BINDING_TABLE_STATE_length 1 + +static inline uint32_t ATTRIBUTE_PURE +BINDING_TABLE_STATE_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BINDING_TABLE_STATE::Surface State Pointer */ + + +#define GEN11_BINDING_TABLE_STATE_SurfaceStatePointer_bits 26 +#define GEN10_BINDING_TABLE_STATE_SurfaceStatePointer_bits 26 +#define GEN9_BINDING_TABLE_STATE_SurfaceStatePointer_bits 26 +#define GEN8_BINDING_TABLE_STATE_SurfaceStatePointer_bits 26 +#define GEN75_BINDING_TABLE_STATE_SurfaceStatePointer_bits 27 +#define GEN7_BINDING_TABLE_STATE_SurfaceStatePointer_bits 27 +#define GEN6_BINDING_TABLE_STATE_SurfaceStatePointer_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +BINDING_TABLE_STATE_SurfaceStatePointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 26; + case 10: return 26; + case 9: return 26; + case 8: return 26; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_BINDING_TABLE_STATE_SurfaceStatePointer_start 6 +#define GEN10_BINDING_TABLE_STATE_SurfaceStatePointer_start 6 +#define GEN9_BINDING_TABLE_STATE_SurfaceStatePointer_start 6 +#define GEN8_BINDING_TABLE_STATE_SurfaceStatePointer_start 6 +#define GEN75_BINDING_TABLE_STATE_SurfaceStatePointer_start 5 +#define GEN7_BINDING_TABLE_STATE_SurfaceStatePointer_start 5 +#define GEN6_BINDING_TABLE_STATE_SurfaceStatePointer_start 5 + +static inline uint32_t ATTRIBUTE_PURE +BINDING_TABLE_STATE_SurfaceStatePointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 5; + } + case 6: return 5; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BLEND_STATE */ + + +#define GEN11_BLEND_STATE_length 1 +#define GEN10_BLEND_STATE_length 1 +#define GEN9_BLEND_STATE_length 1 +#define GEN8_BLEND_STATE_length 1 +#define GEN75_BLEND_STATE_length 0 +#define GEN7_BLEND_STATE_length 0 +#define GEN6_BLEND_STATE_length 0 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BLEND_STATE::Alpha Test Enable */ + + +#define GEN11_BLEND_STATE_AlphaTestEnable_bits 1 +#define GEN10_BLEND_STATE_AlphaTestEnable_bits 1 +#define GEN9_BLEND_STATE_AlphaTestEnable_bits 1 +#define GEN8_BLEND_STATE_AlphaTestEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_AlphaTestEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_BLEND_STATE_AlphaTestEnable_start 27 +#define GEN10_BLEND_STATE_AlphaTestEnable_start 27 +#define GEN9_BLEND_STATE_AlphaTestEnable_start 27 +#define GEN8_BLEND_STATE_AlphaTestEnable_start 27 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_AlphaTestEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BLEND_STATE::Alpha Test Function */ + + +#define GEN11_BLEND_STATE_AlphaTestFunction_bits 3 +#define GEN10_BLEND_STATE_AlphaTestFunction_bits 3 +#define GEN9_BLEND_STATE_AlphaTestFunction_bits 3 +#define GEN8_BLEND_STATE_AlphaTestFunction_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_AlphaTestFunction_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_BLEND_STATE_AlphaTestFunction_start 24 +#define GEN10_BLEND_STATE_AlphaTestFunction_start 24 +#define GEN9_BLEND_STATE_AlphaTestFunction_start 24 +#define GEN8_BLEND_STATE_AlphaTestFunction_start 24 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_AlphaTestFunction_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BLEND_STATE::Alpha To Coverage Dither Enable */ + + +#define GEN11_BLEND_STATE_AlphaToCoverageDitherEnable_bits 1 +#define GEN10_BLEND_STATE_AlphaToCoverageDitherEnable_bits 1 +#define GEN9_BLEND_STATE_AlphaToCoverageDitherEnable_bits 1 +#define GEN8_BLEND_STATE_AlphaToCoverageDitherEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_AlphaToCoverageDitherEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_BLEND_STATE_AlphaToCoverageDitherEnable_start 28 +#define GEN10_BLEND_STATE_AlphaToCoverageDitherEnable_start 28 +#define GEN9_BLEND_STATE_AlphaToCoverageDitherEnable_start 28 +#define GEN8_BLEND_STATE_AlphaToCoverageDitherEnable_start 28 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_AlphaToCoverageDitherEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 28; + case 10: return 28; + case 9: return 28; + case 8: return 28; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BLEND_STATE::Alpha To Coverage Enable */ + + +#define GEN11_BLEND_STATE_AlphaToCoverageEnable_bits 1 +#define GEN10_BLEND_STATE_AlphaToCoverageEnable_bits 1 +#define GEN9_BLEND_STATE_AlphaToCoverageEnable_bits 1 +#define GEN8_BLEND_STATE_AlphaToCoverageEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_AlphaToCoverageEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_BLEND_STATE_AlphaToCoverageEnable_start 31 +#define GEN10_BLEND_STATE_AlphaToCoverageEnable_start 31 +#define GEN9_BLEND_STATE_AlphaToCoverageEnable_start 31 +#define GEN8_BLEND_STATE_AlphaToCoverageEnable_start 31 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_AlphaToCoverageEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 31; + case 10: return 31; + case 9: return 31; + case 8: return 31; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BLEND_STATE::Alpha To One Enable */ + + +#define GEN11_BLEND_STATE_AlphaToOneEnable_bits 1 +#define GEN10_BLEND_STATE_AlphaToOneEnable_bits 1 +#define GEN9_BLEND_STATE_AlphaToOneEnable_bits 1 +#define GEN8_BLEND_STATE_AlphaToOneEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_AlphaToOneEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_BLEND_STATE_AlphaToOneEnable_start 29 +#define GEN10_BLEND_STATE_AlphaToOneEnable_start 29 +#define GEN9_BLEND_STATE_AlphaToOneEnable_start 29 +#define GEN8_BLEND_STATE_AlphaToOneEnable_start 29 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_AlphaToOneEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BLEND_STATE::Color Dither Enable */ + + +#define GEN11_BLEND_STATE_ColorDitherEnable_bits 1 +#define GEN10_BLEND_STATE_ColorDitherEnable_bits 1 +#define GEN9_BLEND_STATE_ColorDitherEnable_bits 1 +#define GEN8_BLEND_STATE_ColorDitherEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ColorDitherEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_BLEND_STATE_ColorDitherEnable_start 23 +#define GEN10_BLEND_STATE_ColorDitherEnable_start 23 +#define GEN9_BLEND_STATE_ColorDitherEnable_start 23 +#define GEN8_BLEND_STATE_ColorDitherEnable_start 23 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ColorDitherEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BLEND_STATE::Entry */ + + +#define GEN11_BLEND_STATE_Entry_bits 64 +#define GEN10_BLEND_STATE_Entry_bits 64 +#define GEN9_BLEND_STATE_Entry_bits 64 +#define GEN8_BLEND_STATE_Entry_bits 64 +#define GEN75_BLEND_STATE_Entry_bits 64 +#define GEN7_BLEND_STATE_Entry_bits 64 +#define GEN6_BLEND_STATE_Entry_bits 64 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_Entry_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 64; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_BLEND_STATE_Entry_start 0 +#define GEN10_BLEND_STATE_Entry_start 0 +#define GEN9_BLEND_STATE_Entry_start 0 +#define GEN8_BLEND_STATE_Entry_start 0 +#define GEN75_BLEND_STATE_Entry_start 0 +#define GEN7_BLEND_STATE_Entry_start 0 +#define GEN6_BLEND_STATE_Entry_start 0 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_Entry_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BLEND_STATE::Independent Alpha Blend Enable */ + + +#define GEN11_BLEND_STATE_IndependentAlphaBlendEnable_bits 1 +#define GEN10_BLEND_STATE_IndependentAlphaBlendEnable_bits 1 +#define GEN9_BLEND_STATE_IndependentAlphaBlendEnable_bits 1 +#define GEN8_BLEND_STATE_IndependentAlphaBlendEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_IndependentAlphaBlendEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_BLEND_STATE_IndependentAlphaBlendEnable_start 30 +#define GEN10_BLEND_STATE_IndependentAlphaBlendEnable_start 30 +#define GEN9_BLEND_STATE_IndependentAlphaBlendEnable_start 30 +#define GEN8_BLEND_STATE_IndependentAlphaBlendEnable_start 30 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_IndependentAlphaBlendEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 30; + case 10: return 30; + case 9: return 30; + case 8: return 30; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BLEND_STATE::X Dither Offset */ + + +#define GEN11_BLEND_STATE_XDitherOffset_bits 2 +#define GEN10_BLEND_STATE_XDitherOffset_bits 2 +#define GEN9_BLEND_STATE_XDitherOffset_bits 2 +#define GEN8_BLEND_STATE_XDitherOffset_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_XDitherOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_BLEND_STATE_XDitherOffset_start 21 +#define GEN10_BLEND_STATE_XDitherOffset_start 21 +#define GEN9_BLEND_STATE_XDitherOffset_start 21 +#define GEN8_BLEND_STATE_XDitherOffset_start 21 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_XDitherOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 21; + case 10: return 21; + case 9: return 21; + case 8: return 21; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BLEND_STATE::Y Dither Offset */ + + +#define GEN11_BLEND_STATE_YDitherOffset_bits 2 +#define GEN10_BLEND_STATE_YDitherOffset_bits 2 +#define GEN9_BLEND_STATE_YDitherOffset_bits 2 +#define GEN8_BLEND_STATE_YDitherOffset_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_YDitherOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_BLEND_STATE_YDitherOffset_start 19 +#define GEN10_BLEND_STATE_YDitherOffset_start 19 +#define GEN9_BLEND_STATE_YDitherOffset_start 19 +#define GEN8_BLEND_STATE_YDitherOffset_start 19 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_YDitherOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 19; + case 10: return 19; + case 9: return 19; + case 8: return 19; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BLEND_STATE_ENTRY */ + + +#define GEN11_BLEND_STATE_ENTRY_length 2 +#define GEN10_BLEND_STATE_ENTRY_length 2 +#define GEN9_BLEND_STATE_ENTRY_length 2 +#define GEN8_BLEND_STATE_ENTRY_length 2 +#define GEN75_BLEND_STATE_ENTRY_length 2 +#define GEN7_BLEND_STATE_ENTRY_length 2 +#define GEN6_BLEND_STATE_ENTRY_length 2 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BLEND_STATE_ENTRY::Alpha Blend Function */ + + +#define GEN11_BLEND_STATE_ENTRY_AlphaBlendFunction_bits 3 +#define GEN10_BLEND_STATE_ENTRY_AlphaBlendFunction_bits 3 +#define GEN9_BLEND_STATE_ENTRY_AlphaBlendFunction_bits 3 +#define GEN8_BLEND_STATE_ENTRY_AlphaBlendFunction_bits 3 +#define GEN75_BLEND_STATE_ENTRY_AlphaBlendFunction_bits 3 +#define GEN7_BLEND_STATE_ENTRY_AlphaBlendFunction_bits 3 +#define GEN6_BLEND_STATE_ENTRY_AlphaBlendFunction_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_AlphaBlendFunction_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_BLEND_STATE_ENTRY_AlphaBlendFunction_start 5 +#define GEN10_BLEND_STATE_ENTRY_AlphaBlendFunction_start 5 +#define GEN9_BLEND_STATE_ENTRY_AlphaBlendFunction_start 5 +#define GEN8_BLEND_STATE_ENTRY_AlphaBlendFunction_start 5 +#define GEN75_BLEND_STATE_ENTRY_AlphaBlendFunction_start 26 +#define GEN7_BLEND_STATE_ENTRY_AlphaBlendFunction_start 26 +#define GEN6_BLEND_STATE_ENTRY_AlphaBlendFunction_start 26 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_AlphaBlendFunction_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 26; + } else { + return 26; + } + case 6: return 26; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BLEND_STATE_ENTRY::Alpha Test Enable */ + + +#define GEN75_BLEND_STATE_ENTRY_AlphaTestEnable_bits 1 +#define GEN7_BLEND_STATE_ENTRY_AlphaTestEnable_bits 1 +#define GEN6_BLEND_STATE_ENTRY_AlphaTestEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_AlphaTestEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_BLEND_STATE_ENTRY_AlphaTestEnable_start 48 +#define GEN7_BLEND_STATE_ENTRY_AlphaTestEnable_start 48 +#define GEN6_BLEND_STATE_ENTRY_AlphaTestEnable_start 48 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_AlphaTestEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 48; + } else { + return 48; + } + case 6: return 48; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BLEND_STATE_ENTRY::Alpha Test Function */ + + +#define GEN75_BLEND_STATE_ENTRY_AlphaTestFunction_bits 3 +#define GEN7_BLEND_STATE_ENTRY_AlphaTestFunction_bits 3 +#define GEN6_BLEND_STATE_ENTRY_AlphaTestFunction_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_AlphaTestFunction_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_BLEND_STATE_ENTRY_AlphaTestFunction_start 45 +#define GEN7_BLEND_STATE_ENTRY_AlphaTestFunction_start 45 +#define GEN6_BLEND_STATE_ENTRY_AlphaTestFunction_start 45 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_AlphaTestFunction_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 45; + } else { + return 45; + } + case 6: return 45; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BLEND_STATE_ENTRY::AlphaToCoverage Dither Enable */ + + +#define GEN75_BLEND_STATE_ENTRY_AlphaToCoverageDitherEnable_bits 1 +#define GEN7_BLEND_STATE_ENTRY_AlphaToCoverageDitherEnable_bits 1 +#define GEN6_BLEND_STATE_ENTRY_AlphaToCoverageDitherEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_AlphaToCoverageDitherEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_BLEND_STATE_ENTRY_AlphaToCoverageDitherEnable_start 61 +#define GEN7_BLEND_STATE_ENTRY_AlphaToCoverageDitherEnable_start 61 +#define GEN6_BLEND_STATE_ENTRY_AlphaToCoverageDitherEnable_start 61 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_AlphaToCoverageDitherEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 61; + } else { + return 61; + } + case 6: return 61; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BLEND_STATE_ENTRY::AlphaToCoverage Enable */ + + +#define GEN75_BLEND_STATE_ENTRY_AlphaToCoverageEnable_bits 1 +#define GEN7_BLEND_STATE_ENTRY_AlphaToCoverageEnable_bits 1 +#define GEN6_BLEND_STATE_ENTRY_AlphaToCoverageEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_AlphaToCoverageEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_BLEND_STATE_ENTRY_AlphaToCoverageEnable_start 63 +#define GEN7_BLEND_STATE_ENTRY_AlphaToCoverageEnable_start 63 +#define GEN6_BLEND_STATE_ENTRY_AlphaToCoverageEnable_start 63 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_AlphaToCoverageEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 63; + } else { + return 63; + } + case 6: return 63; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BLEND_STATE_ENTRY::AlphaToOne Enable */ + + +#define GEN75_BLEND_STATE_ENTRY_AlphaToOneEnable_bits 1 +#define GEN7_BLEND_STATE_ENTRY_AlphaToOneEnable_bits 1 +#define GEN6_BLEND_STATE_ENTRY_AlphaToOneEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_AlphaToOneEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_BLEND_STATE_ENTRY_AlphaToOneEnable_start 62 +#define GEN7_BLEND_STATE_ENTRY_AlphaToOneEnable_start 62 +#define GEN6_BLEND_STATE_ENTRY_AlphaToOneEnable_start 62 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_AlphaToOneEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 62; + } else { + return 62; + } + case 6: return 62; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BLEND_STATE_ENTRY::Color Blend Function */ + + +#define GEN11_BLEND_STATE_ENTRY_ColorBlendFunction_bits 3 +#define GEN10_BLEND_STATE_ENTRY_ColorBlendFunction_bits 3 +#define GEN9_BLEND_STATE_ENTRY_ColorBlendFunction_bits 3 +#define GEN8_BLEND_STATE_ENTRY_ColorBlendFunction_bits 3 +#define GEN75_BLEND_STATE_ENTRY_ColorBlendFunction_bits 3 +#define GEN7_BLEND_STATE_ENTRY_ColorBlendFunction_bits 3 +#define GEN6_BLEND_STATE_ENTRY_ColorBlendFunction_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_ColorBlendFunction_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_BLEND_STATE_ENTRY_ColorBlendFunction_start 18 +#define GEN10_BLEND_STATE_ENTRY_ColorBlendFunction_start 18 +#define GEN9_BLEND_STATE_ENTRY_ColorBlendFunction_start 18 +#define GEN8_BLEND_STATE_ENTRY_ColorBlendFunction_start 18 +#define GEN75_BLEND_STATE_ENTRY_ColorBlendFunction_start 11 +#define GEN7_BLEND_STATE_ENTRY_ColorBlendFunction_start 11 +#define GEN6_BLEND_STATE_ENTRY_ColorBlendFunction_start 11 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_ColorBlendFunction_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 18; + case 10: return 18; + case 9: return 18; + case 8: return 18; + case 7: + if (devinfo->is_haswell) { + return 11; + } else { + return 11; + } + case 6: return 11; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BLEND_STATE_ENTRY::Color Buffer Blend Enable */ + + +#define GEN11_BLEND_STATE_ENTRY_ColorBufferBlendEnable_bits 1 +#define GEN10_BLEND_STATE_ENTRY_ColorBufferBlendEnable_bits 1 +#define GEN9_BLEND_STATE_ENTRY_ColorBufferBlendEnable_bits 1 +#define GEN8_BLEND_STATE_ENTRY_ColorBufferBlendEnable_bits 1 +#define GEN75_BLEND_STATE_ENTRY_ColorBufferBlendEnable_bits 1 +#define GEN7_BLEND_STATE_ENTRY_ColorBufferBlendEnable_bits 1 +#define GEN6_BLEND_STATE_ENTRY_ColorBufferBlendEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_ColorBufferBlendEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_BLEND_STATE_ENTRY_ColorBufferBlendEnable_start 31 +#define GEN10_BLEND_STATE_ENTRY_ColorBufferBlendEnable_start 31 +#define GEN9_BLEND_STATE_ENTRY_ColorBufferBlendEnable_start 31 +#define GEN8_BLEND_STATE_ENTRY_ColorBufferBlendEnable_start 31 +#define GEN75_BLEND_STATE_ENTRY_ColorBufferBlendEnable_start 31 +#define GEN7_BLEND_STATE_ENTRY_ColorBufferBlendEnable_start 31 +#define GEN6_BLEND_STATE_ENTRY_ColorBufferBlendEnable_start 31 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_ColorBufferBlendEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 31; + case 10: return 31; + case 9: return 31; + case 8: return 31; + case 7: + if (devinfo->is_haswell) { + return 31; + } else { + return 31; + } + case 6: return 31; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BLEND_STATE_ENTRY::Color Clamp Range */ + + +#define GEN11_BLEND_STATE_ENTRY_ColorClampRange_bits 2 +#define GEN10_BLEND_STATE_ENTRY_ColorClampRange_bits 2 +#define GEN9_BLEND_STATE_ENTRY_ColorClampRange_bits 2 +#define GEN8_BLEND_STATE_ENTRY_ColorClampRange_bits 2 +#define GEN75_BLEND_STATE_ENTRY_ColorClampRange_bits 2 +#define GEN7_BLEND_STATE_ENTRY_ColorClampRange_bits 2 +#define GEN6_BLEND_STATE_ENTRY_ColorClampRange_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_ColorClampRange_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_BLEND_STATE_ENTRY_ColorClampRange_start 34 +#define GEN10_BLEND_STATE_ENTRY_ColorClampRange_start 34 +#define GEN9_BLEND_STATE_ENTRY_ColorClampRange_start 34 +#define GEN8_BLEND_STATE_ENTRY_ColorClampRange_start 34 +#define GEN75_BLEND_STATE_ENTRY_ColorClampRange_start 34 +#define GEN7_BLEND_STATE_ENTRY_ColorClampRange_start 34 +#define GEN6_BLEND_STATE_ENTRY_ColorClampRange_start 34 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_ColorClampRange_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 34; + case 10: return 34; + case 9: return 34; + case 8: return 34; + case 7: + if (devinfo->is_haswell) { + return 34; + } else { + return 34; + } + case 6: return 34; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BLEND_STATE_ENTRY::Color Dither Enable */ + + +#define GEN75_BLEND_STATE_ENTRY_ColorDitherEnable_bits 1 +#define GEN7_BLEND_STATE_ENTRY_ColorDitherEnable_bits 1 +#define GEN6_BLEND_STATE_ENTRY_ColorDitherEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_ColorDitherEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_BLEND_STATE_ENTRY_ColorDitherEnable_start 44 +#define GEN7_BLEND_STATE_ENTRY_ColorDitherEnable_start 44 +#define GEN6_BLEND_STATE_ENTRY_ColorDitherEnable_start 44 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_ColorDitherEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 44; + } else { + return 44; + } + case 6: return 44; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BLEND_STATE_ENTRY::Destination Alpha Blend Factor */ + + +#define GEN11_BLEND_STATE_ENTRY_DestinationAlphaBlendFactor_bits 5 +#define GEN10_BLEND_STATE_ENTRY_DestinationAlphaBlendFactor_bits 5 +#define GEN9_BLEND_STATE_ENTRY_DestinationAlphaBlendFactor_bits 5 +#define GEN8_BLEND_STATE_ENTRY_DestinationAlphaBlendFactor_bits 5 +#define GEN75_BLEND_STATE_ENTRY_DestinationAlphaBlendFactor_bits 5 +#define GEN7_BLEND_STATE_ENTRY_DestinationAlphaBlendFactor_bits 5 +#define GEN6_BLEND_STATE_ENTRY_DestinationAlphaBlendFactor_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_DestinationAlphaBlendFactor_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 5; + } + case 6: return 5; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_BLEND_STATE_ENTRY_DestinationAlphaBlendFactor_start 8 +#define GEN10_BLEND_STATE_ENTRY_DestinationAlphaBlendFactor_start 8 +#define GEN9_BLEND_STATE_ENTRY_DestinationAlphaBlendFactor_start 8 +#define GEN8_BLEND_STATE_ENTRY_DestinationAlphaBlendFactor_start 8 +#define GEN75_BLEND_STATE_ENTRY_DestinationAlphaBlendFactor_start 15 +#define GEN7_BLEND_STATE_ENTRY_DestinationAlphaBlendFactor_start 15 +#define GEN6_BLEND_STATE_ENTRY_DestinationAlphaBlendFactor_start 15 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_DestinationAlphaBlendFactor_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 15; + } else { + return 15; + } + case 6: return 15; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BLEND_STATE_ENTRY::Destination Blend Factor */ + + +#define GEN11_BLEND_STATE_ENTRY_DestinationBlendFactor_bits 5 +#define GEN10_BLEND_STATE_ENTRY_DestinationBlendFactor_bits 5 +#define GEN9_BLEND_STATE_ENTRY_DestinationBlendFactor_bits 5 +#define GEN8_BLEND_STATE_ENTRY_DestinationBlendFactor_bits 5 +#define GEN75_BLEND_STATE_ENTRY_DestinationBlendFactor_bits 5 +#define GEN7_BLEND_STATE_ENTRY_DestinationBlendFactor_bits 5 +#define GEN6_BLEND_STATE_ENTRY_DestinationBlendFactor_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_DestinationBlendFactor_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 5; + } + case 6: return 5; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_BLEND_STATE_ENTRY_DestinationBlendFactor_start 21 +#define GEN10_BLEND_STATE_ENTRY_DestinationBlendFactor_start 21 +#define GEN9_BLEND_STATE_ENTRY_DestinationBlendFactor_start 21 +#define GEN8_BLEND_STATE_ENTRY_DestinationBlendFactor_start 21 +#define GEN75_BLEND_STATE_ENTRY_DestinationBlendFactor_start 0 +#define GEN7_BLEND_STATE_ENTRY_DestinationBlendFactor_start 0 +#define GEN6_BLEND_STATE_ENTRY_DestinationBlendFactor_start 0 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_DestinationBlendFactor_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 21; + case 10: return 21; + case 9: return 21; + case 8: return 21; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BLEND_STATE_ENTRY::Independent Alpha Blend Enable */ + + +#define GEN75_BLEND_STATE_ENTRY_IndependentAlphaBlendEnable_bits 1 +#define GEN7_BLEND_STATE_ENTRY_IndependentAlphaBlendEnable_bits 1 +#define GEN6_BLEND_STATE_ENTRY_IndependentAlphaBlendEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_IndependentAlphaBlendEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_BLEND_STATE_ENTRY_IndependentAlphaBlendEnable_start 30 +#define GEN7_BLEND_STATE_ENTRY_IndependentAlphaBlendEnable_start 30 +#define GEN6_BLEND_STATE_ENTRY_IndependentAlphaBlendEnable_start 30 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_IndependentAlphaBlendEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 30; + } else { + return 30; + } + case 6: return 30; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BLEND_STATE_ENTRY::Logic Op Enable */ + + +#define GEN11_BLEND_STATE_ENTRY_LogicOpEnable_bits 1 +#define GEN10_BLEND_STATE_ENTRY_LogicOpEnable_bits 1 +#define GEN9_BLEND_STATE_ENTRY_LogicOpEnable_bits 1 +#define GEN8_BLEND_STATE_ENTRY_LogicOpEnable_bits 1 +#define GEN75_BLEND_STATE_ENTRY_LogicOpEnable_bits 1 +#define GEN7_BLEND_STATE_ENTRY_LogicOpEnable_bits 1 +#define GEN6_BLEND_STATE_ENTRY_LogicOpEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_LogicOpEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_BLEND_STATE_ENTRY_LogicOpEnable_start 63 +#define GEN10_BLEND_STATE_ENTRY_LogicOpEnable_start 63 +#define GEN9_BLEND_STATE_ENTRY_LogicOpEnable_start 63 +#define GEN8_BLEND_STATE_ENTRY_LogicOpEnable_start 63 +#define GEN75_BLEND_STATE_ENTRY_LogicOpEnable_start 54 +#define GEN7_BLEND_STATE_ENTRY_LogicOpEnable_start 54 +#define GEN6_BLEND_STATE_ENTRY_LogicOpEnable_start 54 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_LogicOpEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 63; + case 10: return 63; + case 9: return 63; + case 8: return 63; + case 7: + if (devinfo->is_haswell) { + return 54; + } else { + return 54; + } + case 6: return 54; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BLEND_STATE_ENTRY::Logic Op Function */ + + +#define GEN11_BLEND_STATE_ENTRY_LogicOpFunction_bits 4 +#define GEN10_BLEND_STATE_ENTRY_LogicOpFunction_bits 4 +#define GEN9_BLEND_STATE_ENTRY_LogicOpFunction_bits 4 +#define GEN8_BLEND_STATE_ENTRY_LogicOpFunction_bits 4 +#define GEN75_BLEND_STATE_ENTRY_LogicOpFunction_bits 4 +#define GEN7_BLEND_STATE_ENTRY_LogicOpFunction_bits 4 +#define GEN6_BLEND_STATE_ENTRY_LogicOpFunction_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_LogicOpFunction_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_BLEND_STATE_ENTRY_LogicOpFunction_start 59 +#define GEN10_BLEND_STATE_ENTRY_LogicOpFunction_start 59 +#define GEN9_BLEND_STATE_ENTRY_LogicOpFunction_start 59 +#define GEN8_BLEND_STATE_ENTRY_LogicOpFunction_start 59 +#define GEN75_BLEND_STATE_ENTRY_LogicOpFunction_start 50 +#define GEN7_BLEND_STATE_ENTRY_LogicOpFunction_start 50 +#define GEN6_BLEND_STATE_ENTRY_LogicOpFunction_start 50 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_LogicOpFunction_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 59; + case 10: return 59; + case 9: return 59; + case 8: return 59; + case 7: + if (devinfo->is_haswell) { + return 50; + } else { + return 50; + } + case 6: return 50; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BLEND_STATE_ENTRY::Post-Blend Color Clamp Enable */ + + +#define GEN11_BLEND_STATE_ENTRY_PostBlendColorClampEnable_bits 1 +#define GEN10_BLEND_STATE_ENTRY_PostBlendColorClampEnable_bits 1 +#define GEN9_BLEND_STATE_ENTRY_PostBlendColorClampEnable_bits 1 +#define GEN8_BLEND_STATE_ENTRY_PostBlendColorClampEnable_bits 1 +#define GEN75_BLEND_STATE_ENTRY_PostBlendColorClampEnable_bits 1 +#define GEN7_BLEND_STATE_ENTRY_PostBlendColorClampEnable_bits 1 +#define GEN6_BLEND_STATE_ENTRY_PostBlendColorClampEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_PostBlendColorClampEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_BLEND_STATE_ENTRY_PostBlendColorClampEnable_start 32 +#define GEN10_BLEND_STATE_ENTRY_PostBlendColorClampEnable_start 32 +#define GEN9_BLEND_STATE_ENTRY_PostBlendColorClampEnable_start 32 +#define GEN8_BLEND_STATE_ENTRY_PostBlendColorClampEnable_start 32 +#define GEN75_BLEND_STATE_ENTRY_PostBlendColorClampEnable_start 32 +#define GEN7_BLEND_STATE_ENTRY_PostBlendColorClampEnable_start 32 +#define GEN6_BLEND_STATE_ENTRY_PostBlendColorClampEnable_start 32 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_PostBlendColorClampEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BLEND_STATE_ENTRY::Pre-Blend Color Clamp Enable */ + + +#define GEN11_BLEND_STATE_ENTRY_PreBlendColorClampEnable_bits 1 +#define GEN10_BLEND_STATE_ENTRY_PreBlendColorClampEnable_bits 1 +#define GEN9_BLEND_STATE_ENTRY_PreBlendColorClampEnable_bits 1 +#define GEN8_BLEND_STATE_ENTRY_PreBlendColorClampEnable_bits 1 +#define GEN75_BLEND_STATE_ENTRY_PreBlendColorClampEnable_bits 1 +#define GEN7_BLEND_STATE_ENTRY_PreBlendColorClampEnable_bits 1 +#define GEN6_BLEND_STATE_ENTRY_PreBlendColorClampEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_PreBlendColorClampEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_BLEND_STATE_ENTRY_PreBlendColorClampEnable_start 33 +#define GEN10_BLEND_STATE_ENTRY_PreBlendColorClampEnable_start 33 +#define GEN9_BLEND_STATE_ENTRY_PreBlendColorClampEnable_start 33 +#define GEN8_BLEND_STATE_ENTRY_PreBlendColorClampEnable_start 33 +#define GEN75_BLEND_STATE_ENTRY_PreBlendColorClampEnable_start 33 +#define GEN7_BLEND_STATE_ENTRY_PreBlendColorClampEnable_start 33 +#define GEN6_BLEND_STATE_ENTRY_PreBlendColorClampEnable_start 33 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_PreBlendColorClampEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 33; + case 10: return 33; + case 9: return 33; + case 8: return 33; + case 7: + if (devinfo->is_haswell) { + return 33; + } else { + return 33; + } + case 6: return 33; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BLEND_STATE_ENTRY::Pre-Blend Source Only Clamp Enable */ + + +#define GEN11_BLEND_STATE_ENTRY_PreBlendSourceOnlyClampEnable_bits 1 +#define GEN10_BLEND_STATE_ENTRY_PreBlendSourceOnlyClampEnable_bits 1 +#define GEN9_BLEND_STATE_ENTRY_PreBlendSourceOnlyClampEnable_bits 1 +#define GEN8_BLEND_STATE_ENTRY_PreBlendSourceOnlyClampEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_PreBlendSourceOnlyClampEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_BLEND_STATE_ENTRY_PreBlendSourceOnlyClampEnable_start 36 +#define GEN10_BLEND_STATE_ENTRY_PreBlendSourceOnlyClampEnable_start 36 +#define GEN9_BLEND_STATE_ENTRY_PreBlendSourceOnlyClampEnable_start 36 +#define GEN8_BLEND_STATE_ENTRY_PreBlendSourceOnlyClampEnable_start 36 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_PreBlendSourceOnlyClampEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 36; + case 10: return 36; + case 9: return 36; + case 8: return 36; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BLEND_STATE_ENTRY::Source Alpha Blend Factor */ + + +#define GEN11_BLEND_STATE_ENTRY_SourceAlphaBlendFactor_bits 5 +#define GEN10_BLEND_STATE_ENTRY_SourceAlphaBlendFactor_bits 5 +#define GEN9_BLEND_STATE_ENTRY_SourceAlphaBlendFactor_bits 5 +#define GEN8_BLEND_STATE_ENTRY_SourceAlphaBlendFactor_bits 5 +#define GEN75_BLEND_STATE_ENTRY_SourceAlphaBlendFactor_bits 5 +#define GEN7_BLEND_STATE_ENTRY_SourceAlphaBlendFactor_bits 5 +#define GEN6_BLEND_STATE_ENTRY_SourceAlphaBlendFactor_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_SourceAlphaBlendFactor_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 5; + } + case 6: return 5; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_BLEND_STATE_ENTRY_SourceAlphaBlendFactor_start 13 +#define GEN10_BLEND_STATE_ENTRY_SourceAlphaBlendFactor_start 13 +#define GEN9_BLEND_STATE_ENTRY_SourceAlphaBlendFactor_start 13 +#define GEN8_BLEND_STATE_ENTRY_SourceAlphaBlendFactor_start 13 +#define GEN75_BLEND_STATE_ENTRY_SourceAlphaBlendFactor_start 20 +#define GEN7_BLEND_STATE_ENTRY_SourceAlphaBlendFactor_start 20 +#define GEN6_BLEND_STATE_ENTRY_SourceAlphaBlendFactor_start 20 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_SourceAlphaBlendFactor_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 13; + case 10: return 13; + case 9: return 13; + case 8: return 13; + case 7: + if (devinfo->is_haswell) { + return 20; + } else { + return 20; + } + case 6: return 20; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BLEND_STATE_ENTRY::Source Blend Factor */ + + +#define GEN11_BLEND_STATE_ENTRY_SourceBlendFactor_bits 5 +#define GEN10_BLEND_STATE_ENTRY_SourceBlendFactor_bits 5 +#define GEN9_BLEND_STATE_ENTRY_SourceBlendFactor_bits 5 +#define GEN8_BLEND_STATE_ENTRY_SourceBlendFactor_bits 5 +#define GEN75_BLEND_STATE_ENTRY_SourceBlendFactor_bits 5 +#define GEN7_BLEND_STATE_ENTRY_SourceBlendFactor_bits 5 +#define GEN6_BLEND_STATE_ENTRY_SourceBlendFactor_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_SourceBlendFactor_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 5; + } + case 6: return 5; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_BLEND_STATE_ENTRY_SourceBlendFactor_start 26 +#define GEN10_BLEND_STATE_ENTRY_SourceBlendFactor_start 26 +#define GEN9_BLEND_STATE_ENTRY_SourceBlendFactor_start 26 +#define GEN8_BLEND_STATE_ENTRY_SourceBlendFactor_start 26 +#define GEN75_BLEND_STATE_ENTRY_SourceBlendFactor_start 5 +#define GEN7_BLEND_STATE_ENTRY_SourceBlendFactor_start 5 +#define GEN6_BLEND_STATE_ENTRY_SourceBlendFactor_start 5 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_SourceBlendFactor_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 26; + case 10: return 26; + case 9: return 26; + case 8: return 26; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 5; + } + case 6: return 5; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BLEND_STATE_ENTRY::Write Disable Alpha */ + + +#define GEN11_BLEND_STATE_ENTRY_WriteDisableAlpha_bits 1 +#define GEN10_BLEND_STATE_ENTRY_WriteDisableAlpha_bits 1 +#define GEN9_BLEND_STATE_ENTRY_WriteDisableAlpha_bits 1 +#define GEN8_BLEND_STATE_ENTRY_WriteDisableAlpha_bits 1 +#define GEN75_BLEND_STATE_ENTRY_WriteDisableAlpha_bits 1 +#define GEN7_BLEND_STATE_ENTRY_WriteDisableAlpha_bits 1 +#define GEN6_BLEND_STATE_ENTRY_WriteDisableAlpha_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_WriteDisableAlpha_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_BLEND_STATE_ENTRY_WriteDisableAlpha_start 3 +#define GEN10_BLEND_STATE_ENTRY_WriteDisableAlpha_start 3 +#define GEN9_BLEND_STATE_ENTRY_WriteDisableAlpha_start 3 +#define GEN8_BLEND_STATE_ENTRY_WriteDisableAlpha_start 3 +#define GEN75_BLEND_STATE_ENTRY_WriteDisableAlpha_start 59 +#define GEN7_BLEND_STATE_ENTRY_WriteDisableAlpha_start 59 +#define GEN6_BLEND_STATE_ENTRY_WriteDisableAlpha_start 59 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_WriteDisableAlpha_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 59; + } else { + return 59; + } + case 6: return 59; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BLEND_STATE_ENTRY::Write Disable Blue */ + + +#define GEN11_BLEND_STATE_ENTRY_WriteDisableBlue_bits 1 +#define GEN10_BLEND_STATE_ENTRY_WriteDisableBlue_bits 1 +#define GEN9_BLEND_STATE_ENTRY_WriteDisableBlue_bits 1 +#define GEN8_BLEND_STATE_ENTRY_WriteDisableBlue_bits 1 +#define GEN75_BLEND_STATE_ENTRY_WriteDisableBlue_bits 1 +#define GEN7_BLEND_STATE_ENTRY_WriteDisableBlue_bits 1 +#define GEN6_BLEND_STATE_ENTRY_WriteDisableBlue_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_WriteDisableBlue_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_BLEND_STATE_ENTRY_WriteDisableBlue_start 0 +#define GEN10_BLEND_STATE_ENTRY_WriteDisableBlue_start 0 +#define GEN9_BLEND_STATE_ENTRY_WriteDisableBlue_start 0 +#define GEN8_BLEND_STATE_ENTRY_WriteDisableBlue_start 0 +#define GEN75_BLEND_STATE_ENTRY_WriteDisableBlue_start 56 +#define GEN7_BLEND_STATE_ENTRY_WriteDisableBlue_start 56 +#define GEN6_BLEND_STATE_ENTRY_WriteDisableBlue_start 56 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_WriteDisableBlue_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 56; + } else { + return 56; + } + case 6: return 56; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BLEND_STATE_ENTRY::Write Disable Green */ + + +#define GEN11_BLEND_STATE_ENTRY_WriteDisableGreen_bits 1 +#define GEN10_BLEND_STATE_ENTRY_WriteDisableGreen_bits 1 +#define GEN9_BLEND_STATE_ENTRY_WriteDisableGreen_bits 1 +#define GEN8_BLEND_STATE_ENTRY_WriteDisableGreen_bits 1 +#define GEN75_BLEND_STATE_ENTRY_WriteDisableGreen_bits 1 +#define GEN7_BLEND_STATE_ENTRY_WriteDisableGreen_bits 1 +#define GEN6_BLEND_STATE_ENTRY_WriteDisableGreen_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_WriteDisableGreen_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_BLEND_STATE_ENTRY_WriteDisableGreen_start 1 +#define GEN10_BLEND_STATE_ENTRY_WriteDisableGreen_start 1 +#define GEN9_BLEND_STATE_ENTRY_WriteDisableGreen_start 1 +#define GEN8_BLEND_STATE_ENTRY_WriteDisableGreen_start 1 +#define GEN75_BLEND_STATE_ENTRY_WriteDisableGreen_start 57 +#define GEN7_BLEND_STATE_ENTRY_WriteDisableGreen_start 57 +#define GEN6_BLEND_STATE_ENTRY_WriteDisableGreen_start 57 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_WriteDisableGreen_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 57; + } else { + return 57; + } + case 6: return 57; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BLEND_STATE_ENTRY::Write Disable Red */ + + +#define GEN11_BLEND_STATE_ENTRY_WriteDisableRed_bits 1 +#define GEN10_BLEND_STATE_ENTRY_WriteDisableRed_bits 1 +#define GEN9_BLEND_STATE_ENTRY_WriteDisableRed_bits 1 +#define GEN8_BLEND_STATE_ENTRY_WriteDisableRed_bits 1 +#define GEN75_BLEND_STATE_ENTRY_WriteDisableRed_bits 1 +#define GEN7_BLEND_STATE_ENTRY_WriteDisableRed_bits 1 +#define GEN6_BLEND_STATE_ENTRY_WriteDisableRed_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_WriteDisableRed_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_BLEND_STATE_ENTRY_WriteDisableRed_start 2 +#define GEN10_BLEND_STATE_ENTRY_WriteDisableRed_start 2 +#define GEN9_BLEND_STATE_ENTRY_WriteDisableRed_start 2 +#define GEN8_BLEND_STATE_ENTRY_WriteDisableRed_start 2 +#define GEN75_BLEND_STATE_ENTRY_WriteDisableRed_start 58 +#define GEN7_BLEND_STATE_ENTRY_WriteDisableRed_start 58 +#define GEN6_BLEND_STATE_ENTRY_WriteDisableRed_start 58 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_WriteDisableRed_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 58; + } else { + return 58; + } + case 6: return 58; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BLEND_STATE_ENTRY::X Dither Offset */ + + +#define GEN75_BLEND_STATE_ENTRY_XDitherOffset_bits 2 +#define GEN7_BLEND_STATE_ENTRY_XDitherOffset_bits 2 +#define GEN6_BLEND_STATE_ENTRY_XDitherOffset_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_XDitherOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_BLEND_STATE_ENTRY_XDitherOffset_start 42 +#define GEN7_BLEND_STATE_ENTRY_XDitherOffset_start 42 +#define GEN6_BLEND_STATE_ENTRY_XDitherOffset_start 42 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_XDitherOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 42; + } else { + return 42; + } + case 6: return 42; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* BLEND_STATE_ENTRY::Y Dither Offset */ + + +#define GEN75_BLEND_STATE_ENTRY_YDitherOffset_bits 2 +#define GEN7_BLEND_STATE_ENTRY_YDitherOffset_bits 2 +#define GEN6_BLEND_STATE_ENTRY_YDitherOffset_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_YDitherOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_BLEND_STATE_ENTRY_YDitherOffset_start 40 +#define GEN7_BLEND_STATE_ENTRY_YDitherOffset_start 40 +#define GEN6_BLEND_STATE_ENTRY_YDitherOffset_start 40 + +static inline uint32_t ATTRIBUTE_PURE +BLEND_STATE_ENTRY_YDitherOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 40; + } else { + return 40; + } + case 6: return 40; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_0 */ + + +#define GEN11_CACHE_MODE_0_length 1 +#define GEN10_CACHE_MODE_0_length 1 +#define GEN9_CACHE_MODE_0_length 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_0::Disable clock gating in the pixel backend */ + + +#define GEN11_CACHE_MODE_0_Disableclockgatinginthepixelbackend_bits 1 +#define GEN10_CACHE_MODE_0_Disableclockgatinginthepixelbackend_bits 1 +#define GEN9_CACHE_MODE_0_Disableclockgatinginthepixelbackend_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_Disableclockgatinginthepixelbackend_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_0_Disableclockgatinginthepixelbackend_start 1 +#define GEN10_CACHE_MODE_0_Disableclockgatinginthepixelbackend_start 1 +#define GEN9_CACHE_MODE_0_Disableclockgatinginthepixelbackend_start 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_Disableclockgatinginthepixelbackend_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_0::Disable clock gating in the pixel backend Mask */ + + +#define GEN11_CACHE_MODE_0_DisableclockgatinginthepixelbackendMask_bits 1 +#define GEN10_CACHE_MODE_0_DisableclockgatinginthepixelbackendMask_bits 1 +#define GEN9_CACHE_MODE_0_DisableclockgatinginthepixelbackendMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_DisableclockgatinginthepixelbackendMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_0_DisableclockgatinginthepixelbackendMask_start 17 +#define GEN10_CACHE_MODE_0_DisableclockgatinginthepixelbackendMask_start 17 +#define GEN9_CACHE_MODE_0_DisableclockgatinginthepixelbackendMask_start 17 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_DisableclockgatinginthepixelbackendMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 17; + case 10: return 17; + case 9: return 17; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_0::Hierarchical Z RAW Stall Optimization Disable */ + + +#define GEN11_CACHE_MODE_0_HierarchicalZRAWStallOptimizationDisable_bits 1 +#define GEN10_CACHE_MODE_0_HierarchicalZRAWStallOptimizationDisable_bits 1 +#define GEN9_CACHE_MODE_0_HierarchicalZRAWStallOptimizationDisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_HierarchicalZRAWStallOptimizationDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_0_HierarchicalZRAWStallOptimizationDisable_start 2 +#define GEN10_CACHE_MODE_0_HierarchicalZRAWStallOptimizationDisable_start 2 +#define GEN9_CACHE_MODE_0_HierarchicalZRAWStallOptimizationDisable_start 2 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_HierarchicalZRAWStallOptimizationDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_0::Hierarchical Z RAW Stall Optimization Disable Mask */ + + +#define GEN11_CACHE_MODE_0_HierarchicalZRAWStallOptimizationDisableMask_bits 1 +#define GEN10_CACHE_MODE_0_HierarchicalZRAWStallOptimizationDisableMask_bits 1 +#define GEN9_CACHE_MODE_0_HierarchicalZRAWStallOptimizationDisableMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_HierarchicalZRAWStallOptimizationDisableMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_0_HierarchicalZRAWStallOptimizationDisableMask_start 18 +#define GEN10_CACHE_MODE_0_HierarchicalZRAWStallOptimizationDisableMask_start 18 +#define GEN9_CACHE_MODE_0_HierarchicalZRAWStallOptimizationDisableMask_start 18 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_HierarchicalZRAWStallOptimizationDisableMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 18; + case 10: return 18; + case 9: return 18; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_0::MSAA Compression Plane Number Threshold for eLLC */ + + +#define GEN11_CACHE_MODE_0_MSAACompressionPlaneNumberThresholdforeLLC_bits 3 +#define GEN10_CACHE_MODE_0_MSAACompressionPlaneNumberThresholdforeLLC_bits 3 +#define GEN9_CACHE_MODE_0_MSAACompressionPlaneNumberThresholdforeLLC_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_MSAACompressionPlaneNumberThresholdforeLLC_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_0_MSAACompressionPlaneNumberThresholdforeLLC_start 12 +#define GEN10_CACHE_MODE_0_MSAACompressionPlaneNumberThresholdforeLLC_start 12 +#define GEN9_CACHE_MODE_0_MSAACompressionPlaneNumberThresholdforeLLC_start 12 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_MSAACompressionPlaneNumberThresholdforeLLC_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 12; + case 10: return 12; + case 9: return 12; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_0::MSAA Compression Plane Number Threshold for eLLC Mask */ + + +#define GEN11_CACHE_MODE_0_MSAACompressionPlaneNumberThresholdforeLLCMask_bits 3 +#define GEN10_CACHE_MODE_0_MSAACompressionPlaneNumberThresholdforeLLCMask_bits 3 +#define GEN9_CACHE_MODE_0_MSAACompressionPlaneNumberThresholdforeLLCMask_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_MSAACompressionPlaneNumberThresholdforeLLCMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_0_MSAACompressionPlaneNumberThresholdforeLLCMask_start 28 +#define GEN10_CACHE_MODE_0_MSAACompressionPlaneNumberThresholdforeLLCMask_start 28 +#define GEN9_CACHE_MODE_0_MSAACompressionPlaneNumberThresholdforeLLCMask_start 28 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_MSAACompressionPlaneNumberThresholdforeLLCMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 28; + case 10: return 28; + case 9: return 28; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_0::Null tile fix disable */ + + +#define GEN11_CACHE_MODE_0_Nulltilefixdisable_bits 1 +#define GEN10_CACHE_MODE_0_Nulltilefixdisable_bits 1 +#define GEN9_CACHE_MODE_0_Nulltilefixdisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_Nulltilefixdisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_0_Nulltilefixdisable_start 0 +#define GEN10_CACHE_MODE_0_Nulltilefixdisable_start 0 +#define GEN9_CACHE_MODE_0_Nulltilefixdisable_start 0 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_Nulltilefixdisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_0::Null tile fix disable Mask */ + + +#define GEN11_CACHE_MODE_0_NulltilefixdisableMask_bits 1 +#define GEN10_CACHE_MODE_0_NulltilefixdisableMask_bits 1 +#define GEN9_CACHE_MODE_0_NulltilefixdisableMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_NulltilefixdisableMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_0_NulltilefixdisableMask_start 16 +#define GEN10_CACHE_MODE_0_NulltilefixdisableMask_start 16 +#define GEN9_CACHE_MODE_0_NulltilefixdisableMask_start 16 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_NulltilefixdisableMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_0::RCC Eviction Policy */ + + +#define GEN11_CACHE_MODE_0_RCCEvictionPolicy_bits 1 +#define GEN10_CACHE_MODE_0_RCCEvictionPolicy_bits 1 +#define GEN9_CACHE_MODE_0_RCCEvictionPolicy_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_RCCEvictionPolicy_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_0_RCCEvictionPolicy_start 4 +#define GEN10_CACHE_MODE_0_RCCEvictionPolicy_start 4 +#define GEN9_CACHE_MODE_0_RCCEvictionPolicy_start 4 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_RCCEvictionPolicy_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_0::RCC Eviction Policy Mask */ + + +#define GEN11_CACHE_MODE_0_RCCEvictionPolicyMask_bits 1 +#define GEN10_CACHE_MODE_0_RCCEvictionPolicyMask_bits 1 +#define GEN9_CACHE_MODE_0_RCCEvictionPolicyMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_RCCEvictionPolicyMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_0_RCCEvictionPolicyMask_start 20 +#define GEN10_CACHE_MODE_0_RCCEvictionPolicyMask_start 20 +#define GEN9_CACHE_MODE_0_RCCEvictionPolicyMask_start 20 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_RCCEvictionPolicyMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 20; + case 10: return 20; + case 9: return 20; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_0::STC PMA Optimization Enable */ + + +#define GEN11_CACHE_MODE_0_STCPMAOptimizationEnable_bits 1 +#define GEN10_CACHE_MODE_0_STCPMAOptimizationEnable_bits 1 +#define GEN9_CACHE_MODE_0_STCPMAOptimizationEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_STCPMAOptimizationEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_0_STCPMAOptimizationEnable_start 5 +#define GEN10_CACHE_MODE_0_STCPMAOptimizationEnable_start 5 +#define GEN9_CACHE_MODE_0_STCPMAOptimizationEnable_start 5 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_STCPMAOptimizationEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_0::STC PMA Optimization Enable Mask */ + + +#define GEN11_CACHE_MODE_0_STCPMAOptimizationEnableMask_bits 1 +#define GEN10_CACHE_MODE_0_STCPMAOptimizationEnableMask_bits 1 +#define GEN9_CACHE_MODE_0_STCPMAOptimizationEnableMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_STCPMAOptimizationEnableMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_0_STCPMAOptimizationEnableMask_start 21 +#define GEN10_CACHE_MODE_0_STCPMAOptimizationEnableMask_start 21 +#define GEN9_CACHE_MODE_0_STCPMAOptimizationEnableMask_start 21 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_STCPMAOptimizationEnableMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 21; + case 10: return 21; + case 9: return 21; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_0::Sampler L2 Disable */ + + +#define GEN11_CACHE_MODE_0_SamplerL2Disable_bits 1 +#define GEN10_CACHE_MODE_0_SamplerL2Disable_bits 1 +#define GEN9_CACHE_MODE_0_SamplerL2Disable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_SamplerL2Disable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_0_SamplerL2Disable_start 15 +#define GEN10_CACHE_MODE_0_SamplerL2Disable_start 15 +#define GEN9_CACHE_MODE_0_SamplerL2Disable_start 15 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_SamplerL2Disable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 15; + case 10: return 15; + case 9: return 15; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_0::Sampler L2 Disable Mask */ + + +#define GEN11_CACHE_MODE_0_SamplerL2DisableMask_bits 1 +#define GEN10_CACHE_MODE_0_SamplerL2DisableMask_bits 1 +#define GEN9_CACHE_MODE_0_SamplerL2DisableMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_SamplerL2DisableMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_0_SamplerL2DisableMask_start 31 +#define GEN10_CACHE_MODE_0_SamplerL2DisableMask_start 31 +#define GEN9_CACHE_MODE_0_SamplerL2DisableMask_start 31 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_SamplerL2DisableMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 31; + case 10: return 31; + case 9: return 31; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_0::Sampler L2 Request Arbitration */ + + +#define GEN11_CACHE_MODE_0_SamplerL2RequestArbitration_bits 2 +#define GEN10_CACHE_MODE_0_SamplerL2RequestArbitration_bits 2 +#define GEN9_CACHE_MODE_0_SamplerL2RequestArbitration_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_SamplerL2RequestArbitration_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_0_SamplerL2RequestArbitration_start 6 +#define GEN10_CACHE_MODE_0_SamplerL2RequestArbitration_start 6 +#define GEN9_CACHE_MODE_0_SamplerL2RequestArbitration_start 6 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_SamplerL2RequestArbitration_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_0::Sampler L2 Request Arbitration Mask */ + + +#define GEN11_CACHE_MODE_0_SamplerL2RequestArbitrationMask_bits 2 +#define GEN10_CACHE_MODE_0_SamplerL2RequestArbitrationMask_bits 2 +#define GEN9_CACHE_MODE_0_SamplerL2RequestArbitrationMask_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_SamplerL2RequestArbitrationMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_0_SamplerL2RequestArbitrationMask_start 22 +#define GEN10_CACHE_MODE_0_SamplerL2RequestArbitrationMask_start 22 +#define GEN9_CACHE_MODE_0_SamplerL2RequestArbitrationMask_start 22 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_SamplerL2RequestArbitrationMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 22; + case 10: return 22; + case 9: return 22; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_0::Sampler L2 TLB Prefetch Enable */ + + +#define GEN11_CACHE_MODE_0_SamplerL2TLBPrefetchEnable_bits 1 +#define GEN10_CACHE_MODE_0_SamplerL2TLBPrefetchEnable_bits 1 +#define GEN9_CACHE_MODE_0_SamplerL2TLBPrefetchEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_SamplerL2TLBPrefetchEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_0_SamplerL2TLBPrefetchEnable_start 9 +#define GEN10_CACHE_MODE_0_SamplerL2TLBPrefetchEnable_start 9 +#define GEN9_CACHE_MODE_0_SamplerL2TLBPrefetchEnable_start 9 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_SamplerL2TLBPrefetchEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 9; + case 10: return 9; + case 9: return 9; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_0::Sampler L2 TLB Prefetch Enable Mask */ + + +#define GEN11_CACHE_MODE_0_SamplerL2TLBPrefetchEnableMask_bits 1 +#define GEN10_CACHE_MODE_0_SamplerL2TLBPrefetchEnableMask_bits 1 +#define GEN9_CACHE_MODE_0_SamplerL2TLBPrefetchEnableMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_SamplerL2TLBPrefetchEnableMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_0_SamplerL2TLBPrefetchEnableMask_start 25 +#define GEN10_CACHE_MODE_0_SamplerL2TLBPrefetchEnableMask_start 25 +#define GEN9_CACHE_MODE_0_SamplerL2TLBPrefetchEnableMask_start 25 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_SamplerL2TLBPrefetchEnableMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 25; + case 10: return 25; + case 9: return 25; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_0::Sampler Set Remapping for 3D Disable */ + + +#define GEN11_CACHE_MODE_0_SamplerSetRemappingfor3DDisable_bits 1 +#define GEN10_CACHE_MODE_0_SamplerSetRemappingfor3DDisable_bits 1 +#define GEN9_CACHE_MODE_0_SamplerSetRemappingfor3DDisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_SamplerSetRemappingfor3DDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_0_SamplerSetRemappingfor3DDisable_start 11 +#define GEN10_CACHE_MODE_0_SamplerSetRemappingfor3DDisable_start 11 +#define GEN9_CACHE_MODE_0_SamplerSetRemappingfor3DDisable_start 11 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_SamplerSetRemappingfor3DDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_0::Sampler Set Remapping for 3D Disable Mask */ + + +#define GEN11_CACHE_MODE_0_SamplerSetRemappingfor3DDisableMask_bits 1 +#define GEN10_CACHE_MODE_0_SamplerSetRemappingfor3DDisableMask_bits 1 +#define GEN9_CACHE_MODE_0_SamplerSetRemappingfor3DDisableMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_SamplerSetRemappingfor3DDisableMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_0_SamplerSetRemappingfor3DDisableMask_start 27 +#define GEN10_CACHE_MODE_0_SamplerSetRemappingfor3DDisableMask_start 27 +#define GEN9_CACHE_MODE_0_SamplerSetRemappingfor3DDisableMask_start 27 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_0_SamplerSetRemappingfor3DDisableMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_1 */ + + +#define GEN11_CACHE_MODE_1_length 1 +#define GEN10_CACHE_MODE_1_length 1 +#define GEN9_CACHE_MODE_1_length 1 +#define GEN8_CACHE_MODE_1_length 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_1::4X4 RCPFE-STC Optimization Disable */ + + +#define GEN9_CACHE_MODE_1_4X4RCPFESTCOptimizationDisable_bits 1 +#define GEN8_CACHE_MODE_1_4X4RCPFESTCOptimizationDisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_4X4RCPFESTCOptimizationDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_CACHE_MODE_1_4X4RCPFESTCOptimizationDisable_start 6 +#define GEN8_CACHE_MODE_1_4X4RCPFESTCOptimizationDisable_start 6 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_4X4RCPFESTCOptimizationDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_1::4X4 RCPFE-STC Optimization Disable Mask */ + + +#define GEN9_CACHE_MODE_1_4X4RCPFESTCOptimizationDisableMask_bits 1 +#define GEN8_CACHE_MODE_1_4X4RCPFESTCOptimizationDisableMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_4X4RCPFESTCOptimizationDisableMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_CACHE_MODE_1_4X4RCPFESTCOptimizationDisableMask_start 22 +#define GEN8_CACHE_MODE_1_4X4RCPFESTCOptimizationDisableMask_start 22 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_4X4RCPFESTCOptimizationDisableMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 22; + case 8: return 22; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_1::Blend Optimization Fix Disable */ + + +#define GEN11_CACHE_MODE_1_BlendOptimizationFixDisable_bits 1 +#define GEN10_CACHE_MODE_1_BlendOptimizationFixDisable_bits 1 +#define GEN9_CACHE_MODE_1_BlendOptimizationFixDisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_BlendOptimizationFixDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_1_BlendOptimizationFixDisable_start 14 +#define GEN10_CACHE_MODE_1_BlendOptimizationFixDisable_start 14 +#define GEN9_CACHE_MODE_1_BlendOptimizationFixDisable_start 14 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_BlendOptimizationFixDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 14; + case 10: return 14; + case 9: return 14; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_1::Blend Optimization Fix Disable Mask */ + + +#define GEN11_CACHE_MODE_1_BlendOptimizationFixDisableMask_bits 1 +#define GEN10_CACHE_MODE_1_BlendOptimizationFixDisableMask_bits 1 +#define GEN9_CACHE_MODE_1_BlendOptimizationFixDisableMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_BlendOptimizationFixDisableMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_1_BlendOptimizationFixDisableMask_start 30 +#define GEN10_CACHE_MODE_1_BlendOptimizationFixDisableMask_start 30 +#define GEN9_CACHE_MODE_1_BlendOptimizationFixDisableMask_start 30 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_BlendOptimizationFixDisableMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 30; + case 10: return 30; + case 9: return 30; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_1::Color Compression Disable */ + + +#define GEN11_CACHE_MODE_1_ColorCompressionDisable_bits 1 +#define GEN10_CACHE_MODE_1_ColorCompressionDisable_bits 1 +#define GEN9_CACHE_MODE_1_ColorCompressionDisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_ColorCompressionDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_1_ColorCompressionDisable_start 15 +#define GEN10_CACHE_MODE_1_ColorCompressionDisable_start 15 +#define GEN9_CACHE_MODE_1_ColorCompressionDisable_start 15 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_ColorCompressionDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 15; + case 10: return 15; + case 9: return 15; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_1::Color Compression Disable Mask */ + + +#define GEN11_CACHE_MODE_1_ColorCompressionDisableMask_bits 1 +#define GEN10_CACHE_MODE_1_ColorCompressionDisableMask_bits 1 +#define GEN9_CACHE_MODE_1_ColorCompressionDisableMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_ColorCompressionDisableMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_1_ColorCompressionDisableMask_start 31 +#define GEN10_CACHE_MODE_1_ColorCompressionDisableMask_start 31 +#define GEN9_CACHE_MODE_1_ColorCompressionDisableMask_start 31 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_ColorCompressionDisableMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 31; + case 10: return 31; + case 9: return 31; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_1::Depth Read Hit Write-Only Optimization Disable */ + + +#define GEN9_CACHE_MODE_1_DepthReadHitWriteOnlyOptimizationDisable_bits 1 +#define GEN8_CACHE_MODE_1_DepthReadHitWriteOnlyOptimizationDisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_DepthReadHitWriteOnlyOptimizationDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_CACHE_MODE_1_DepthReadHitWriteOnlyOptimizationDisable_start 3 +#define GEN8_CACHE_MODE_1_DepthReadHitWriteOnlyOptimizationDisable_start 3 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_DepthReadHitWriteOnlyOptimizationDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_1::Depth Read Hit Write-Only Optimization Disable Mask */ + + +#define GEN9_CACHE_MODE_1_DepthReadHitWriteOnlyOptimizationDisableMask_bits 1 +#define GEN8_CACHE_MODE_1_DepthReadHitWriteOnlyOptimizationDisableMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_DepthReadHitWriteOnlyOptimizationDisableMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_CACHE_MODE_1_DepthReadHitWriteOnlyOptimizationDisableMask_start 19 +#define GEN8_CACHE_MODE_1_DepthReadHitWriteOnlyOptimizationDisableMask_start 19 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_DepthReadHitWriteOnlyOptimizationDisableMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 19; + case 8: return 19; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_1::Float Blend Optimization Enable */ + + +#define GEN9_CACHE_MODE_1_FloatBlendOptimizationEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_FloatBlendOptimizationEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_CACHE_MODE_1_FloatBlendOptimizationEnable_start 4 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_FloatBlendOptimizationEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_1::Float Blend Optimization Enable Mask */ + + +#define GEN9_CACHE_MODE_1_FloatBlendOptimizationEnableMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_FloatBlendOptimizationEnableMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_CACHE_MODE_1_FloatBlendOptimizationEnableMask_start 20 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_FloatBlendOptimizationEnableMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 20; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_1::HIZ Eviction Policy */ + + +#define GEN9_CACHE_MODE_1_HIZEvictionPolicy_bits 1 +#define GEN8_CACHE_MODE_1_HIZEvictionPolicy_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_HIZEvictionPolicy_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_CACHE_MODE_1_HIZEvictionPolicy_start 12 +#define GEN8_CACHE_MODE_1_HIZEvictionPolicy_start 12 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_HIZEvictionPolicy_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 12; + case 8: return 12; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_1::HIZ Eviction Policy Mask */ + + +#define GEN9_CACHE_MODE_1_HIZEvictionPolicyMask_bits 1 +#define GEN8_CACHE_MODE_1_HIZEvictionPolicyMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_HIZEvictionPolicyMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_CACHE_MODE_1_HIZEvictionPolicyMask_start 28 +#define GEN8_CACHE_MODE_1_HIZEvictionPolicyMask_start 28 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_HIZEvictionPolicyMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 28; + case 8: return 28; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_1::MCS Cache Disable */ + + +#define GEN11_CACHE_MODE_1_MCSCacheDisable_bits 1 +#define GEN10_CACHE_MODE_1_MCSCacheDisable_bits 1 +#define GEN9_CACHE_MODE_1_MCSCacheDisable_bits 1 +#define GEN8_CACHE_MODE_1_MCSCacheDisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_MCSCacheDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_1_MCSCacheDisable_start 5 +#define GEN10_CACHE_MODE_1_MCSCacheDisable_start 5 +#define GEN9_CACHE_MODE_1_MCSCacheDisable_start 5 +#define GEN8_CACHE_MODE_1_MCSCacheDisable_start 5 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_MCSCacheDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_1::MCS Cache Disable Mask */ + + +#define GEN11_CACHE_MODE_1_MCSCacheDisableMask_bits 1 +#define GEN10_CACHE_MODE_1_MCSCacheDisableMask_bits 1 +#define GEN9_CACHE_MODE_1_MCSCacheDisableMask_bits 1 +#define GEN8_CACHE_MODE_1_MCSCacheDisableMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_MCSCacheDisableMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_1_MCSCacheDisableMask_start 21 +#define GEN10_CACHE_MODE_1_MCSCacheDisableMask_start 21 +#define GEN9_CACHE_MODE_1_MCSCacheDisableMask_start 21 +#define GEN8_CACHE_MODE_1_MCSCacheDisableMask_start 21 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_MCSCacheDisableMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 21; + case 10: return 21; + case 9: return 21; + case 8: return 21; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_1::MSC RAW Hazard Avoidance Bit */ + + +#define GEN11_CACHE_MODE_1_MSCRAWHazardAvoidanceBit_bits 1 +#define GEN10_CACHE_MODE_1_MSCRAWHazardAvoidanceBit_bits 1 +#define GEN9_CACHE_MODE_1_MSCRAWHazardAvoidanceBit_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_MSCRAWHazardAvoidanceBit_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_1_MSCRAWHazardAvoidanceBit_start 9 +#define GEN10_CACHE_MODE_1_MSCRAWHazardAvoidanceBit_start 9 +#define GEN9_CACHE_MODE_1_MSCRAWHazardAvoidanceBit_start 9 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_MSCRAWHazardAvoidanceBit_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 9; + case 10: return 9; + case 9: return 9; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_1::MSC RAW Hazard Avoidance Bit Mask */ + + +#define GEN11_CACHE_MODE_1_MSCRAWHazardAvoidanceBitMask_bits 1 +#define GEN10_CACHE_MODE_1_MSCRAWHazardAvoidanceBitMask_bits 1 +#define GEN9_CACHE_MODE_1_MSCRAWHazardAvoidanceBitMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_MSCRAWHazardAvoidanceBitMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_1_MSCRAWHazardAvoidanceBitMask_start 25 +#define GEN10_CACHE_MODE_1_MSCRAWHazardAvoidanceBitMask_start 25 +#define GEN9_CACHE_MODE_1_MSCRAWHazardAvoidanceBitMask_start 25 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_MSCRAWHazardAvoidanceBitMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 25; + case 10: return 25; + case 9: return 25; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_1::MSC Resolve Optimization Disable */ + + +#define GEN8_CACHE_MODE_1_MSCResolveOptimizationDisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_MSCResolveOptimizationDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_CACHE_MODE_1_MSCResolveOptimizationDisable_start 14 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_MSCResolveOptimizationDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 14; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_1::MSC Resolve Optimization Disable Mask */ + + +#define GEN8_CACHE_MODE_1_MSCResolveOptimizationDisableMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_MSCResolveOptimizationDisableMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_CACHE_MODE_1_MSCResolveOptimizationDisableMask_start 30 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_MSCResolveOptimizationDisableMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 30; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_1::NP Early Z Fails Disable */ + + +#define GEN11_CACHE_MODE_1_NPEarlyZFailsDisable_bits 1 +#define GEN10_CACHE_MODE_1_NPEarlyZFailsDisable_bits 1 +#define GEN9_CACHE_MODE_1_NPEarlyZFailsDisable_bits 1 +#define GEN8_CACHE_MODE_1_NPEarlyZFailsDisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_NPEarlyZFailsDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_1_NPEarlyZFailsDisable_start 13 +#define GEN10_CACHE_MODE_1_NPEarlyZFailsDisable_start 13 +#define GEN9_CACHE_MODE_1_NPEarlyZFailsDisable_start 13 +#define GEN8_CACHE_MODE_1_NPEarlyZFailsDisable_start 13 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_NPEarlyZFailsDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 13; + case 10: return 13; + case 9: return 13; + case 8: return 13; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_1::NP Early Z Fails Disable Mask */ + + +#define GEN11_CACHE_MODE_1_NPEarlyZFailsDisableMask_bits 1 +#define GEN10_CACHE_MODE_1_NPEarlyZFailsDisableMask_bits 1 +#define GEN9_CACHE_MODE_1_NPEarlyZFailsDisableMask_bits 1 +#define GEN8_CACHE_MODE_1_NPEarlyZFailsDisableMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_NPEarlyZFailsDisableMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_1_NPEarlyZFailsDisableMask_start 29 +#define GEN10_CACHE_MODE_1_NPEarlyZFailsDisableMask_start 29 +#define GEN9_CACHE_MODE_1_NPEarlyZFailsDisableMask_start 29 +#define GEN8_CACHE_MODE_1_NPEarlyZFailsDisableMask_start 29 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_NPEarlyZFailsDisableMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_1::NP PMA Fix Enable */ + + +#define GEN9_CACHE_MODE_1_NPPMAFixEnable_bits 1 +#define GEN8_CACHE_MODE_1_NPPMAFixEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_NPPMAFixEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_CACHE_MODE_1_NPPMAFixEnable_start 11 +#define GEN8_CACHE_MODE_1_NPPMAFixEnable_start 11 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_NPPMAFixEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 11; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_1::NP PMA Fix Enable Mask */ + + +#define GEN9_CACHE_MODE_1_NPPMAFixEnableMask_bits 1 +#define GEN8_CACHE_MODE_1_NPPMAFixEnableMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_NPPMAFixEnableMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_CACHE_MODE_1_NPPMAFixEnableMask_start 27 +#define GEN8_CACHE_MODE_1_NPPMAFixEnableMask_start 27 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_NPPMAFixEnableMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_1::Partial Resolve Disable In VC */ + + +#define GEN11_CACHE_MODE_1_PartialResolveDisableInVC_bits 1 +#define GEN10_CACHE_MODE_1_PartialResolveDisableInVC_bits 1 +#define GEN9_CACHE_MODE_1_PartialResolveDisableInVC_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_PartialResolveDisableInVC_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_1_PartialResolveDisableInVC_start 1 +#define GEN10_CACHE_MODE_1_PartialResolveDisableInVC_start 1 +#define GEN9_CACHE_MODE_1_PartialResolveDisableInVC_start 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_PartialResolveDisableInVC_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_1::Partial Resolve Disable In VC Mask */ + + +#define GEN11_CACHE_MODE_1_PartialResolveDisableInVCMask_bits 1 +#define GEN10_CACHE_MODE_1_PartialResolveDisableInVCMask_bits 1 +#define GEN9_CACHE_MODE_1_PartialResolveDisableInVCMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_PartialResolveDisableInVCMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_1_PartialResolveDisableInVCMask_start 17 +#define GEN10_CACHE_MODE_1_PartialResolveDisableInVCMask_start 17 +#define GEN9_CACHE_MODE_1_PartialResolveDisableInVCMask_start 17 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_PartialResolveDisableInVCMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 17; + case 10: return 17; + case 9: return 17; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_1::RCZ PMA Promoted 2 Not-Promoted Allocation stall optimization Disable */ + + +#define GEN11_CACHE_MODE_1_RCZPMAPromoted2NotPromotedAllocationstalloptimizationDisable_bits 1 +#define GEN10_CACHE_MODE_1_RCZPMAPromoted2NotPromotedAllocationstalloptimizationDisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_RCZPMAPromoted2NotPromotedAllocationstalloptimizationDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_1_RCZPMAPromoted2NotPromotedAllocationstalloptimizationDisable_start 3 +#define GEN10_CACHE_MODE_1_RCZPMAPromoted2NotPromotedAllocationstalloptimizationDisable_start 3 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_RCZPMAPromoted2NotPromotedAllocationstalloptimizationDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_1::RCZ PMA Promoted 2 Not-Promoted Allocation stall optimization Disable Mask */ + + +#define GEN11_CACHE_MODE_1_RCZPMAPromoted2NotPromotedAllocationstalloptimizationDisableMask_bits 1 +#define GEN10_CACHE_MODE_1_RCZPMAPromoted2NotPromotedAllocationstalloptimizationDisableMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_RCZPMAPromoted2NotPromotedAllocationstalloptimizationDisableMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_1_RCZPMAPromoted2NotPromotedAllocationstalloptimizationDisableMask_start 19 +#define GEN10_CACHE_MODE_1_RCZPMAPromoted2NotPromotedAllocationstalloptimizationDisableMask_start 19 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_RCZPMAPromoted2NotPromotedAllocationstalloptimizationDisableMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 19; + case 10: return 19; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_1::RCZ Read after expansion control fix 2 */ + + +#define GEN9_CACHE_MODE_1_RCZReadafterexpansioncontrolfix2_bits 1 +#define GEN8_CACHE_MODE_1_RCZReadafterexpansioncontrolfix2_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_RCZReadafterexpansioncontrolfix2_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_CACHE_MODE_1_RCZReadafterexpansioncontrolfix2_start 2 +#define GEN8_CACHE_MODE_1_RCZReadafterexpansioncontrolfix2_start 2 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_RCZReadafterexpansioncontrolfix2_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_1::RCZ Read after expansion control fix 2 Mask */ + + +#define GEN9_CACHE_MODE_1_RCZReadafterexpansioncontrolfix2Mask_bits 1 +#define GEN8_CACHE_MODE_1_RCZReadafterexpansioncontrolfix2Mask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_RCZReadafterexpansioncontrolfix2Mask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_CACHE_MODE_1_RCZReadafterexpansioncontrolfix2Mask_start 18 +#define GEN8_CACHE_MODE_1_RCZReadafterexpansioncontrolfix2Mask_start 18 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_RCZReadafterexpansioncontrolfix2Mask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 18; + case 8: return 18; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_1::Sampler Cache Set XOR selection */ + + +#define GEN9_CACHE_MODE_1_SamplerCacheSetXORselection_bits 2 +#define GEN8_CACHE_MODE_1_SamplerCacheSetXORselection_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_SamplerCacheSetXORselection_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_CACHE_MODE_1_SamplerCacheSetXORselection_start 7 +#define GEN8_CACHE_MODE_1_SamplerCacheSetXORselection_start 7 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_SamplerCacheSetXORselection_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_1::Sampler Cache Set XOR selection Mask */ + + +#define GEN9_CACHE_MODE_1_SamplerCacheSetXORselectionMask_bits 2 +#define GEN8_CACHE_MODE_1_SamplerCacheSetXORselectionMask_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_SamplerCacheSetXORselectionMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_CACHE_MODE_1_SamplerCacheSetXORselectionMask_start 23 +#define GEN8_CACHE_MODE_1_SamplerCacheSetXORselectionMask_start 23 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_1_SamplerCacheSetXORselectionMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_SS */ + + +#define GEN11_CACHE_MODE_SS_length 1 +#define GEN10_CACHE_MODE_SS_length 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_SS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_SS::Float Blend Optimization Enable */ + + +#define GEN11_CACHE_MODE_SS_FloatBlendOptimizationEnable_bits 1 +#define GEN10_CACHE_MODE_SS_FloatBlendOptimizationEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_SS_FloatBlendOptimizationEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_SS_FloatBlendOptimizationEnable_start 4 +#define GEN10_CACHE_MODE_SS_FloatBlendOptimizationEnable_start 4 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_SS_FloatBlendOptimizationEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_SS::Float Blend Optimization Enable Mask */ + + +#define GEN11_CACHE_MODE_SS_FloatBlendOptimizationEnableMask_bits 1 +#define GEN10_CACHE_MODE_SS_FloatBlendOptimizationEnableMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_SS_FloatBlendOptimizationEnableMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_SS_FloatBlendOptimizationEnableMask_start 20 +#define GEN10_CACHE_MODE_SS_FloatBlendOptimizationEnableMask_start 20 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_SS_FloatBlendOptimizationEnableMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 20; + case 10: return 20; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_SS::Instruction Level 1 Cache Disable */ + + +#define GEN11_CACHE_MODE_SS_InstructionLevel1CacheDisable_bits 1 +#define GEN10_CACHE_MODE_SS_InstructionLevel1CacheDisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_SS_InstructionLevel1CacheDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_SS_InstructionLevel1CacheDisable_start 0 +#define GEN10_CACHE_MODE_SS_InstructionLevel1CacheDisable_start 0 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_SS_InstructionLevel1CacheDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_SS::Instruction Level 1 Cache Disable Mask */ + + +#define GEN11_CACHE_MODE_SS_InstructionLevel1CacheDisableMask_bits 1 +#define GEN10_CACHE_MODE_SS_InstructionLevel1CacheDisableMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_SS_InstructionLevel1CacheDisableMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_SS_InstructionLevel1CacheDisableMask_start 16 +#define GEN10_CACHE_MODE_SS_InstructionLevel1CacheDisableMask_start 16 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_SS_InstructionLevel1CacheDisableMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_SS::Instruction Level 1 Cache and In-Flight Queue Disable */ + + +#define GEN11_CACHE_MODE_SS_InstructionLevel1CacheandInFlightQueueDisable_bits 1 +#define GEN10_CACHE_MODE_SS_InstructionLevel1CacheandInFlightQueueDisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_SS_InstructionLevel1CacheandInFlightQueueDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_SS_InstructionLevel1CacheandInFlightQueueDisable_start 1 +#define GEN10_CACHE_MODE_SS_InstructionLevel1CacheandInFlightQueueDisable_start 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_SS_InstructionLevel1CacheandInFlightQueueDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_SS::Instruction Level 1 Cache and In-Flight Queue Disable Mask */ + + +#define GEN11_CACHE_MODE_SS_InstructionLevel1CacheandInFlightQueueDisableMask_bits 1 +#define GEN10_CACHE_MODE_SS_InstructionLevel1CacheandInFlightQueueDisableMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_SS_InstructionLevel1CacheandInFlightQueueDisableMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_SS_InstructionLevel1CacheandInFlightQueueDisableMask_start 17 +#define GEN10_CACHE_MODE_SS_InstructionLevel1CacheandInFlightQueueDisableMask_start 17 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_SS_InstructionLevel1CacheandInFlightQueueDisableMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 17; + case 10: return 17; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_SS::Per Sample Blend Opt Disable */ + + +#define GEN11_CACHE_MODE_SS_PerSampleBlendOptDisable_bits 1 +#define GEN10_CACHE_MODE_SS_PerSampleBlendOptDisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_SS_PerSampleBlendOptDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_SS_PerSampleBlendOptDisable_start 11 +#define GEN10_CACHE_MODE_SS_PerSampleBlendOptDisable_start 11 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_SS_PerSampleBlendOptDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CACHE_MODE_SS::Per Sample Blend Opt Disable Mask */ + + +#define GEN11_CACHE_MODE_SS_PerSampleBlendOptDisableMask_bits 1 +#define GEN10_CACHE_MODE_SS_PerSampleBlendOptDisableMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_SS_PerSampleBlendOptDisableMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CACHE_MODE_SS_PerSampleBlendOptDisableMask_start 27 +#define GEN10_CACHE_MODE_SS_PerSampleBlendOptDisableMask_start 27 + +static inline uint32_t ATTRIBUTE_PURE +CACHE_MODE_SS_PerSampleBlendOptDisableMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CC_VIEWPORT */ + + +#define GEN11_CC_VIEWPORT_length 2 +#define GEN10_CC_VIEWPORT_length 2 +#define GEN9_CC_VIEWPORT_length 2 +#define GEN8_CC_VIEWPORT_length 2 +#define GEN75_CC_VIEWPORT_length 2 +#define GEN7_CC_VIEWPORT_length 2 +#define GEN6_CC_VIEWPORT_length 2 +#define GEN5_CC_VIEWPORT_length 2 +#define GEN45_CC_VIEWPORT_length 2 +#define GEN4_CC_VIEWPORT_length 2 + +static inline uint32_t ATTRIBUTE_PURE +CC_VIEWPORT_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CC_VIEWPORT::Maximum Depth */ + + +#define GEN11_CC_VIEWPORT_MaximumDepth_bits 32 +#define GEN10_CC_VIEWPORT_MaximumDepth_bits 32 +#define GEN9_CC_VIEWPORT_MaximumDepth_bits 32 +#define GEN8_CC_VIEWPORT_MaximumDepth_bits 32 +#define GEN75_CC_VIEWPORT_MaximumDepth_bits 32 +#define GEN7_CC_VIEWPORT_MaximumDepth_bits 32 +#define GEN6_CC_VIEWPORT_MaximumDepth_bits 32 +#define GEN5_CC_VIEWPORT_MaximumDepth_bits 32 +#define GEN45_CC_VIEWPORT_MaximumDepth_bits 32 +#define GEN4_CC_VIEWPORT_MaximumDepth_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +CC_VIEWPORT_MaximumDepth_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CC_VIEWPORT_MaximumDepth_start 32 +#define GEN10_CC_VIEWPORT_MaximumDepth_start 32 +#define GEN9_CC_VIEWPORT_MaximumDepth_start 32 +#define GEN8_CC_VIEWPORT_MaximumDepth_start 32 +#define GEN75_CC_VIEWPORT_MaximumDepth_start 32 +#define GEN7_CC_VIEWPORT_MaximumDepth_start 32 +#define GEN6_CC_VIEWPORT_MaximumDepth_start 32 +#define GEN5_CC_VIEWPORT_MaximumDepth_start 32 +#define GEN45_CC_VIEWPORT_MaximumDepth_start 32 +#define GEN4_CC_VIEWPORT_MaximumDepth_start 32 + +static inline uint32_t ATTRIBUTE_PURE +CC_VIEWPORT_MaximumDepth_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CC_VIEWPORT::Minimum Depth */ + + +#define GEN11_CC_VIEWPORT_MinimumDepth_bits 32 +#define GEN10_CC_VIEWPORT_MinimumDepth_bits 32 +#define GEN9_CC_VIEWPORT_MinimumDepth_bits 32 +#define GEN8_CC_VIEWPORT_MinimumDepth_bits 32 +#define GEN75_CC_VIEWPORT_MinimumDepth_bits 32 +#define GEN7_CC_VIEWPORT_MinimumDepth_bits 32 +#define GEN6_CC_VIEWPORT_MinimumDepth_bits 32 +#define GEN5_CC_VIEWPORT_MinimumDepth_bits 32 +#define GEN45_CC_VIEWPORT_MinimumDepth_bits 32 +#define GEN4_CC_VIEWPORT_MinimumDepth_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +CC_VIEWPORT_MinimumDepth_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CC_VIEWPORT_MinimumDepth_start 0 +#define GEN10_CC_VIEWPORT_MinimumDepth_start 0 +#define GEN9_CC_VIEWPORT_MinimumDepth_start 0 +#define GEN8_CC_VIEWPORT_MinimumDepth_start 0 +#define GEN75_CC_VIEWPORT_MinimumDepth_start 0 +#define GEN7_CC_VIEWPORT_MinimumDepth_start 0 +#define GEN6_CC_VIEWPORT_MinimumDepth_start 0 +#define GEN5_CC_VIEWPORT_MinimumDepth_start 0 +#define GEN45_CC_VIEWPORT_MinimumDepth_start 0 +#define GEN4_CC_VIEWPORT_MinimumDepth_start 0 + +static inline uint32_t ATTRIBUTE_PURE +CC_VIEWPORT_MinimumDepth_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CHICKEN3 */ + + +#define GEN75_CHICKEN3_length 1 + +static inline uint32_t ATTRIBUTE_PURE +CHICKEN3_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CHICKEN3::L3 Atomic Disable */ + + +#define GEN75_CHICKEN3_L3AtomicDisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CHICKEN3_L3AtomicDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_CHICKEN3_L3AtomicDisable_start 6 + +static inline uint32_t ATTRIBUTE_PURE +CHICKEN3_L3AtomicDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CHICKEN3::L3 Atomic Disable Mask */ + + +#define GEN75_CHICKEN3_L3AtomicDisableMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CHICKEN3_L3AtomicDisableMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_CHICKEN3_L3AtomicDisableMask_start 22 + +static inline uint32_t ATTRIBUTE_PURE +CHICKEN3_L3AtomicDisableMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 22; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLEAR_COLOR */ + + +#define GEN11_CLEAR_COLOR_length 8 +#define GEN10_CLEAR_COLOR_length 8 + +static inline uint32_t ATTRIBUTE_PURE +CLEAR_COLOR_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLEAR_COLOR::Converted Clear Value Hi/Low */ + + +#define GEN11_CLEAR_COLOR_ConvertedClearValueHiLow_bits 64 + +static inline uint32_t ATTRIBUTE_PURE +CLEAR_COLOR_ConvertedClearValueHiLow_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CLEAR_COLOR_ConvertedClearValueHiLow_start 128 + +static inline uint32_t ATTRIBUTE_PURE +CLEAR_COLOR_ConvertedClearValueHiLow_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 128; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLEAR_COLOR::Raw Clear Color Alpha */ + + +#define GEN11_CLEAR_COLOR_RawClearColorAlpha_bits 32 +#define GEN10_CLEAR_COLOR_RawClearColorAlpha_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +CLEAR_COLOR_RawClearColorAlpha_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CLEAR_COLOR_RawClearColorAlpha_start 96 +#define GEN10_CLEAR_COLOR_RawClearColorAlpha_start 96 + +static inline uint32_t ATTRIBUTE_PURE +CLEAR_COLOR_RawClearColorAlpha_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 96; + case 10: return 96; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLEAR_COLOR::Raw Clear Color Blue */ + + +#define GEN11_CLEAR_COLOR_RawClearColorBlue_bits 32 +#define GEN10_CLEAR_COLOR_RawClearColorBlue_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +CLEAR_COLOR_RawClearColorBlue_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CLEAR_COLOR_RawClearColorBlue_start 64 +#define GEN10_CLEAR_COLOR_RawClearColorBlue_start 64 + +static inline uint32_t ATTRIBUTE_PURE +CLEAR_COLOR_RawClearColorBlue_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLEAR_COLOR::Raw Clear Color Green */ + + +#define GEN11_CLEAR_COLOR_RawClearColorGreen_bits 32 +#define GEN10_CLEAR_COLOR_RawClearColorGreen_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +CLEAR_COLOR_RawClearColorGreen_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CLEAR_COLOR_RawClearColorGreen_start 32 +#define GEN10_CLEAR_COLOR_RawClearColorGreen_start 32 + +static inline uint32_t ATTRIBUTE_PURE +CLEAR_COLOR_RawClearColorGreen_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLEAR_COLOR::Raw Clear Color Red */ + + +#define GEN11_CLEAR_COLOR_RawClearColorRed_bits 32 +#define GEN10_CLEAR_COLOR_RawClearColorRed_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +CLEAR_COLOR_RawClearColorRed_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CLEAR_COLOR_RawClearColorRed_start 0 +#define GEN10_CLEAR_COLOR_RawClearColorRed_start 0 + +static inline uint32_t ATTRIBUTE_PURE +CLEAR_COLOR_RawClearColorRed_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_STATE */ + + +#define GEN5_CLIP_STATE_length 11 +#define GEN45_CLIP_STATE_length 11 +#define GEN4_CLIP_STATE_length 11 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 11; + case 4: + if (devinfo->is_g4x) { + return 11; + } else { + return 11; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_STATE::API Mode */ + + +#define GEN5_CLIP_STATE_APIMode_bits 1 +#define GEN45_CLIP_STATE_APIMode_bits 1 +#define GEN4_CLIP_STATE_APIMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_APIMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CLIP_STATE_APIMode_start 190 +#define GEN45_CLIP_STATE_APIMode_start 190 +#define GEN4_CLIP_STATE_APIMode_start 190 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_APIMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 190; + case 4: + if (devinfo->is_g4x) { + return 190; + } else { + return 190; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_STATE::Binding Table Entry Count */ + + +#define GEN5_CLIP_STATE_BindingTableEntryCount_bits 8 +#define GEN45_CLIP_STATE_BindingTableEntryCount_bits 8 +#define GEN4_CLIP_STATE_BindingTableEntryCount_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_BindingTableEntryCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CLIP_STATE_BindingTableEntryCount_start 50 +#define GEN45_CLIP_STATE_BindingTableEntryCount_start 50 +#define GEN4_CLIP_STATE_BindingTableEntryCount_start 50 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_BindingTableEntryCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 50; + case 4: + if (devinfo->is_g4x) { + return 50; + } else { + return 50; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_STATE::Clip Mode */ + + +#define GEN5_CLIP_STATE_ClipMode_bits 3 +#define GEN45_CLIP_STATE_ClipMode_bits 3 +#define GEN4_CLIP_STATE_ClipMode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_ClipMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CLIP_STATE_ClipMode_start 173 +#define GEN45_CLIP_STATE_ClipMode_start 173 +#define GEN4_CLIP_STATE_ClipMode_start 173 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_ClipMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 173; + case 4: + if (devinfo->is_g4x) { + return 173; + } else { + return 173; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_STATE::Clipper Statistics Enable */ + + +#define GEN45_CLIP_STATE_ClipperStatisticsEnable_bits 1 +#define GEN4_CLIP_STATE_ClipperStatisticsEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_ClipperStatisticsEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN45_CLIP_STATE_ClipperStatisticsEnable_start 138 +#define GEN4_CLIP_STATE_ClipperStatisticsEnable_start 138 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_ClipperStatisticsEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 138; + } else { + return 138; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_STATE::Clipper Viewport State Pointer */ + + +#define GEN5_CLIP_STATE_ClipperViewportStatePointer_bits 27 +#define GEN45_CLIP_STATE_ClipperViewportStatePointer_bits 27 +#define GEN4_CLIP_STATE_ClipperViewportStatePointer_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_ClipperViewportStatePointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CLIP_STATE_ClipperViewportStatePointer_start 197 +#define GEN45_CLIP_STATE_ClipperViewportStatePointer_start 197 +#define GEN4_CLIP_STATE_ClipperViewportStatePointer_start 197 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_ClipperViewportStatePointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 197; + case 4: + if (devinfo->is_g4x) { + return 197; + } else { + return 197; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_STATE::Constant URB Entry Read Length */ + + +#define GEN5_CLIP_STATE_ConstantURBEntryReadLength_bits 6 +#define GEN45_CLIP_STATE_ConstantURBEntryReadLength_bits 6 +#define GEN4_CLIP_STATE_ConstantURBEntryReadLength_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_ConstantURBEntryReadLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CLIP_STATE_ConstantURBEntryReadLength_start 121 +#define GEN45_CLIP_STATE_ConstantURBEntryReadLength_start 121 +#define GEN4_CLIP_STATE_ConstantURBEntryReadLength_start 121 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_ConstantURBEntryReadLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 121; + case 4: + if (devinfo->is_g4x) { + return 121; + } else { + return 121; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_STATE::Constant URB Entry Read Offset */ + + +#define GEN5_CLIP_STATE_ConstantURBEntryReadOffset_bits 6 +#define GEN45_CLIP_STATE_ConstantURBEntryReadOffset_bits 6 +#define GEN4_CLIP_STATE_ConstantURBEntryReadOffset_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_ConstantURBEntryReadOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CLIP_STATE_ConstantURBEntryReadOffset_start 114 +#define GEN45_CLIP_STATE_ConstantURBEntryReadOffset_start 114 +#define GEN4_CLIP_STATE_ConstantURBEntryReadOffset_start 114 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_ConstantURBEntryReadOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 114; + case 4: + if (devinfo->is_g4x) { + return 114; + } else { + return 114; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_STATE::Dispatch GRF Start Register For URB Data */ + + +#define GEN5_CLIP_STATE_DispatchGRFStartRegisterForURBData_bits 4 +#define GEN45_CLIP_STATE_DispatchGRFStartRegisterForURBData_bits 4 +#define GEN4_CLIP_STATE_DispatchGRFStartRegisterForURBData_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_DispatchGRFStartRegisterForURBData_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 4; + case 4: + if (devinfo->is_g4x) { + return 4; + } else { + return 4; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CLIP_STATE_DispatchGRFStartRegisterForURBData_start 96 +#define GEN45_CLIP_STATE_DispatchGRFStartRegisterForURBData_start 96 +#define GEN4_CLIP_STATE_DispatchGRFStartRegisterForURBData_start 96 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_DispatchGRFStartRegisterForURBData_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 96; + case 4: + if (devinfo->is_g4x) { + return 96; + } else { + return 96; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_STATE::Floating Point Mode */ + + +#define GEN5_CLIP_STATE_FloatingPointMode_bits 1 +#define GEN45_CLIP_STATE_FloatingPointMode_bits 1 +#define GEN4_CLIP_STATE_FloatingPointMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_FloatingPointMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CLIP_STATE_FloatingPointMode_start 48 +#define GEN45_CLIP_STATE_FloatingPointMode_start 48 +#define GEN4_CLIP_STATE_FloatingPointMode_start 48 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_FloatingPointMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 48; + case 4: + if (devinfo->is_g4x) { + return 48; + } else { + return 48; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_STATE::GRF Register Count */ + + +#define GEN5_CLIP_STATE_GRFRegisterCount_bits 3 +#define GEN45_CLIP_STATE_GRFRegisterCount_bits 3 +#define GEN4_CLIP_STATE_GRFRegisterCount_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_GRFRegisterCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CLIP_STATE_GRFRegisterCount_start 1 +#define GEN45_CLIP_STATE_GRFRegisterCount_start 1 +#define GEN4_CLIP_STATE_GRFRegisterCount_start 1 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_GRFRegisterCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_STATE::GS Output Object Statistics Enable */ + + +#define GEN45_CLIP_STATE_GSOutputObjectStatisticsEnable_bits 1 +#define GEN4_CLIP_STATE_GSOutputObjectStatisticsEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_GSOutputObjectStatisticsEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN45_CLIP_STATE_GSOutputObjectStatisticsEnable_start 138 +#define GEN4_CLIP_STATE_GSOutputObjectStatisticsEnable_start 138 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_GSOutputObjectStatisticsEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 138; + } else { + return 138; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_STATE::Guardband ClipTest Enable */ + + +#define GEN5_CLIP_STATE_GuardbandClipTestEnable_bits 1 +#define GEN45_CLIP_STATE_GuardbandClipTestEnable_bits 1 +#define GEN4_CLIP_STATE_GuardbandClipTestEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_GuardbandClipTestEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CLIP_STATE_GuardbandClipTestEnable_start 186 +#define GEN45_CLIP_STATE_GuardbandClipTestEnable_start 186 +#define GEN4_CLIP_STATE_GuardbandClipTestEnable_start 186 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_GuardbandClipTestEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 186; + case 4: + if (devinfo->is_g4x) { + return 186; + } else { + return 186; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_STATE::Illegal Opcode Exception Enable */ + + +#define GEN5_CLIP_STATE_IllegalOpcodeExceptionEnable_bits 1 +#define GEN45_CLIP_STATE_IllegalOpcodeExceptionEnable_bits 1 +#define GEN4_CLIP_STATE_IllegalOpcodeExceptionEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_IllegalOpcodeExceptionEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CLIP_STATE_IllegalOpcodeExceptionEnable_start 45 +#define GEN45_CLIP_STATE_IllegalOpcodeExceptionEnable_start 45 +#define GEN4_CLIP_STATE_IllegalOpcodeExceptionEnable_start 45 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_IllegalOpcodeExceptionEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 45; + case 4: + if (devinfo->is_g4x) { + return 45; + } else { + return 45; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_STATE::Kernel Start Pointer */ + + +#define GEN5_CLIP_STATE_KernelStartPointer_bits 26 +#define GEN45_CLIP_STATE_KernelStartPointer_bits 26 +#define GEN4_CLIP_STATE_KernelStartPointer_bits 26 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_KernelStartPointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 26; + case 4: + if (devinfo->is_g4x) { + return 26; + } else { + return 26; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CLIP_STATE_KernelStartPointer_start 6 +#define GEN45_CLIP_STATE_KernelStartPointer_start 6 +#define GEN4_CLIP_STATE_KernelStartPointer_start 6 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_KernelStartPointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_STATE::Mask Stack Exception Enable */ + + +#define GEN5_CLIP_STATE_MaskStackExceptionEnable_bits 1 +#define GEN45_CLIP_STATE_MaskStackExceptionEnable_bits 1 +#define GEN4_CLIP_STATE_MaskStackExceptionEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_MaskStackExceptionEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CLIP_STATE_MaskStackExceptionEnable_start 43 +#define GEN45_CLIP_STATE_MaskStackExceptionEnable_start 43 +#define GEN4_CLIP_STATE_MaskStackExceptionEnable_start 43 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_MaskStackExceptionEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 43; + case 4: + if (devinfo->is_g4x) { + return 43; + } else { + return 43; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_STATE::Maximum Number of Threads */ + + +#define GEN5_CLIP_STATE_MaximumNumberofThreads_bits 6 +#define GEN45_CLIP_STATE_MaximumNumberofThreads_bits 6 +#define GEN4_CLIP_STATE_MaximumNumberofThreads_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_MaximumNumberofThreads_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CLIP_STATE_MaximumNumberofThreads_start 153 +#define GEN45_CLIP_STATE_MaximumNumberofThreads_start 153 +#define GEN4_CLIP_STATE_MaximumNumberofThreads_start 153 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_MaximumNumberofThreads_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 153; + case 4: + if (devinfo->is_g4x) { + return 153; + } else { + return 153; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_STATE::Negative W ClipTest Enable */ + + +#define GEN5_CLIP_STATE_NegativeWClipTestEnable_bits 1 +#define GEN45_CLIP_STATE_NegativeWClipTestEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_NegativeWClipTestEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CLIP_STATE_NegativeWClipTestEnable_start 185 +#define GEN45_CLIP_STATE_NegativeWClipTestEnable_start 185 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_NegativeWClipTestEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 185; + case 4: + if (devinfo->is_g4x) { + return 185; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_STATE::Number of URB Entries */ + + +#define GEN5_CLIP_STATE_NumberofURBEntries_bits 8 +#define GEN45_CLIP_STATE_NumberofURBEntries_bits 8 +#define GEN4_CLIP_STATE_NumberofURBEntries_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_NumberofURBEntries_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CLIP_STATE_NumberofURBEntries_start 139 +#define GEN45_CLIP_STATE_NumberofURBEntries_start 139 +#define GEN4_CLIP_STATE_NumberofURBEntries_start 139 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_NumberofURBEntries_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 139; + case 4: + if (devinfo->is_g4x) { + return 139; + } else { + return 139; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_STATE::Per-Thread Scratch Space */ + + +#define GEN5_CLIP_STATE_PerThreadScratchSpace_bits 4 +#define GEN45_CLIP_STATE_PerThreadScratchSpace_bits 4 +#define GEN4_CLIP_STATE_PerThreadScratchSpace_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_PerThreadScratchSpace_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 4; + case 4: + if (devinfo->is_g4x) { + return 4; + } else { + return 4; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CLIP_STATE_PerThreadScratchSpace_start 64 +#define GEN45_CLIP_STATE_PerThreadScratchSpace_start 64 +#define GEN4_CLIP_STATE_PerThreadScratchSpace_start 64 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_PerThreadScratchSpace_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 64; + case 4: + if (devinfo->is_g4x) { + return 64; + } else { + return 64; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_STATE::Scratch Space Base Pointer */ + + +#define GEN5_CLIP_STATE_ScratchSpaceBasePointer_bits 22 +#define GEN45_CLIP_STATE_ScratchSpaceBasePointer_bits 22 +#define GEN4_CLIP_STATE_ScratchSpaceBasePointer_bits 22 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_ScratchSpaceBasePointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 22; + case 4: + if (devinfo->is_g4x) { + return 22; + } else { + return 22; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CLIP_STATE_ScratchSpaceBasePointer_start 74 +#define GEN45_CLIP_STATE_ScratchSpaceBasePointer_start 74 +#define GEN4_CLIP_STATE_ScratchSpaceBasePointer_start 74 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_ScratchSpaceBasePointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 74; + case 4: + if (devinfo->is_g4x) { + return 74; + } else { + return 74; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_STATE::Screen Space Viewport X Max */ + + +#define GEN5_CLIP_STATE_ScreenSpaceViewportXMax_bits 32 +#define GEN45_CLIP_STATE_ScreenSpaceViewportXMax_bits 32 +#define GEN4_CLIP_STATE_ScreenSpaceViewportXMax_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_ScreenSpaceViewportXMax_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CLIP_STATE_ScreenSpaceViewportXMax_start 256 +#define GEN45_CLIP_STATE_ScreenSpaceViewportXMax_start 256 +#define GEN4_CLIP_STATE_ScreenSpaceViewportXMax_start 256 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_ScreenSpaceViewportXMax_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 256; + case 4: + if (devinfo->is_g4x) { + return 256; + } else { + return 256; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_STATE::Screen Space Viewport X Min */ + + +#define GEN5_CLIP_STATE_ScreenSpaceViewportXMin_bits 32 +#define GEN45_CLIP_STATE_ScreenSpaceViewportXMin_bits 32 +#define GEN4_CLIP_STATE_ScreenSpaceViewportXMin_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_ScreenSpaceViewportXMin_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CLIP_STATE_ScreenSpaceViewportXMin_start 224 +#define GEN45_CLIP_STATE_ScreenSpaceViewportXMin_start 224 +#define GEN4_CLIP_STATE_ScreenSpaceViewportXMin_start 224 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_ScreenSpaceViewportXMin_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 224; + case 4: + if (devinfo->is_g4x) { + return 224; + } else { + return 224; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_STATE::Screen Space Viewport Y Max */ + + +#define GEN5_CLIP_STATE_ScreenSpaceViewportYMax_bits 32 +#define GEN45_CLIP_STATE_ScreenSpaceViewportYMax_bits 32 +#define GEN4_CLIP_STATE_ScreenSpaceViewportYMax_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_ScreenSpaceViewportYMax_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CLIP_STATE_ScreenSpaceViewportYMax_start 320 +#define GEN45_CLIP_STATE_ScreenSpaceViewportYMax_start 320 +#define GEN4_CLIP_STATE_ScreenSpaceViewportYMax_start 320 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_ScreenSpaceViewportYMax_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 320; + case 4: + if (devinfo->is_g4x) { + return 320; + } else { + return 320; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_STATE::Screen Space Viewport Y Min */ + + +#define GEN5_CLIP_STATE_ScreenSpaceViewportYMin_bits 32 +#define GEN45_CLIP_STATE_ScreenSpaceViewportYMin_bits 32 +#define GEN4_CLIP_STATE_ScreenSpaceViewportYMin_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_ScreenSpaceViewportYMin_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CLIP_STATE_ScreenSpaceViewportYMin_start 288 +#define GEN45_CLIP_STATE_ScreenSpaceViewportYMin_start 288 +#define GEN4_CLIP_STATE_ScreenSpaceViewportYMin_start 288 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_ScreenSpaceViewportYMin_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 288; + case 4: + if (devinfo->is_g4x) { + return 288; + } else { + return 288; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_STATE::Single Program Flow */ + + +#define GEN5_CLIP_STATE_SingleProgramFlow_bits 1 +#define GEN45_CLIP_STATE_SingleProgramFlow_bits 1 +#define GEN4_CLIP_STATE_SingleProgramFlow_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_SingleProgramFlow_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CLIP_STATE_SingleProgramFlow_start 63 +#define GEN45_CLIP_STATE_SingleProgramFlow_start 63 +#define GEN4_CLIP_STATE_SingleProgramFlow_start 63 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_SingleProgramFlow_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 63; + case 4: + if (devinfo->is_g4x) { + return 63; + } else { + return 63; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_STATE::Software Exception Enable */ + + +#define GEN5_CLIP_STATE_SoftwareExceptionEnable_bits 1 +#define GEN45_CLIP_STATE_SoftwareExceptionEnable_bits 1 +#define GEN4_CLIP_STATE_SoftwareExceptionEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_SoftwareExceptionEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CLIP_STATE_SoftwareExceptionEnable_start 39 +#define GEN45_CLIP_STATE_SoftwareExceptionEnable_start 39 +#define GEN4_CLIP_STATE_SoftwareExceptionEnable_start 39 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_SoftwareExceptionEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 39; + case 4: + if (devinfo->is_g4x) { + return 39; + } else { + return 39; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_STATE::Thread Priority */ + + +#define GEN5_CLIP_STATE_ThreadPriority_bits 1 +#define GEN45_CLIP_STATE_ThreadPriority_bits 1 +#define GEN4_CLIP_STATE_ThreadPriority_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_ThreadPriority_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CLIP_STATE_ThreadPriority_start 49 +#define GEN45_CLIP_STATE_ThreadPriority_start 49 +#define GEN4_CLIP_STATE_ThreadPriority_start 49 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_ThreadPriority_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 49; + case 4: + if (devinfo->is_g4x) { + return 49; + } else { + return 49; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_STATE::URB Entry Allocation Size */ + + +#define GEN5_CLIP_STATE_URBEntryAllocationSize_bits 5 +#define GEN45_CLIP_STATE_URBEntryAllocationSize_bits 5 +#define GEN4_CLIP_STATE_URBEntryAllocationSize_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_URBEntryAllocationSize_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 5; + case 4: + if (devinfo->is_g4x) { + return 5; + } else { + return 5; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CLIP_STATE_URBEntryAllocationSize_start 147 +#define GEN45_CLIP_STATE_URBEntryAllocationSize_start 147 +#define GEN4_CLIP_STATE_URBEntryAllocationSize_start 147 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_URBEntryAllocationSize_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 147; + case 4: + if (devinfo->is_g4x) { + return 147; + } else { + return 147; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_STATE::UserClipDistance ClipTest Enable Bitmask */ + + +#define GEN5_CLIP_STATE_UserClipDistanceClipTestEnableBitmask_bits 8 +#define GEN45_CLIP_STATE_UserClipDistanceClipTestEnableBitmask_bits 8 +#define GEN4_CLIP_STATE_UserClipDistanceClipTestEnableBitmask_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_UserClipDistanceClipTestEnableBitmask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CLIP_STATE_UserClipDistanceClipTestEnableBitmask_start 176 +#define GEN45_CLIP_STATE_UserClipDistanceClipTestEnableBitmask_start 176 +#define GEN4_CLIP_STATE_UserClipDistanceClipTestEnableBitmask_start 176 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_UserClipDistanceClipTestEnableBitmask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 176; + case 4: + if (devinfo->is_g4x) { + return 176; + } else { + return 176; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_STATE::UserClipFlags MustClip Enable */ + + +#define GEN5_CLIP_STATE_UserClipFlagsMustClipEnable_bits 1 +#define GEN45_CLIP_STATE_UserClipFlagsMustClipEnable_bits 1 +#define GEN4_CLIP_STATE_UserClipFlagsMustClipEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_UserClipFlagsMustClipEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CLIP_STATE_UserClipFlagsMustClipEnable_start 184 +#define GEN45_CLIP_STATE_UserClipFlagsMustClipEnable_start 184 +#define GEN4_CLIP_STATE_UserClipFlagsMustClipEnable_start 184 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_UserClipFlagsMustClipEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 184; + case 4: + if (devinfo->is_g4x) { + return 184; + } else { + return 184; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_STATE::Vertex Position Space */ + + +#define GEN5_CLIP_STATE_VertexPositionSpace_bits 1 +#define GEN45_CLIP_STATE_VertexPositionSpace_bits 1 +#define GEN4_CLIP_STATE_VertexPositionSpace_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_VertexPositionSpace_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CLIP_STATE_VertexPositionSpace_start 189 +#define GEN45_CLIP_STATE_VertexPositionSpace_start 189 +#define GEN4_CLIP_STATE_VertexPositionSpace_start 189 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_VertexPositionSpace_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 189; + case 4: + if (devinfo->is_g4x) { + return 189; + } else { + return 189; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_STATE::Vertex URB Entry Read Length */ + + +#define GEN5_CLIP_STATE_VertexURBEntryReadLength_bits 6 +#define GEN45_CLIP_STATE_VertexURBEntryReadLength_bits 6 +#define GEN4_CLIP_STATE_VertexURBEntryReadLength_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_VertexURBEntryReadLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CLIP_STATE_VertexURBEntryReadLength_start 107 +#define GEN45_CLIP_STATE_VertexURBEntryReadLength_start 107 +#define GEN4_CLIP_STATE_VertexURBEntryReadLength_start 107 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_VertexURBEntryReadLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 107; + case 4: + if (devinfo->is_g4x) { + return 107; + } else { + return 107; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_STATE::Vertex URB Entry Read Offset */ + + +#define GEN5_CLIP_STATE_VertexURBEntryReadOffset_bits 6 +#define GEN45_CLIP_STATE_VertexURBEntryReadOffset_bits 6 +#define GEN4_CLIP_STATE_VertexURBEntryReadOffset_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_VertexURBEntryReadOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CLIP_STATE_VertexURBEntryReadOffset_start 100 +#define GEN45_CLIP_STATE_VertexURBEntryReadOffset_start 100 +#define GEN4_CLIP_STATE_VertexURBEntryReadOffset_start 100 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_VertexURBEntryReadOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 100; + case 4: + if (devinfo->is_g4x) { + return 100; + } else { + return 100; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_STATE::Viewport XY ClipTest Enable */ + + +#define GEN5_CLIP_STATE_ViewportXYClipTestEnable_bits 1 +#define GEN45_CLIP_STATE_ViewportXYClipTestEnable_bits 1 +#define GEN4_CLIP_STATE_ViewportXYClipTestEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_ViewportXYClipTestEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CLIP_STATE_ViewportXYClipTestEnable_start 188 +#define GEN45_CLIP_STATE_ViewportXYClipTestEnable_start 188 +#define GEN4_CLIP_STATE_ViewportXYClipTestEnable_start 188 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_ViewportXYClipTestEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 188; + case 4: + if (devinfo->is_g4x) { + return 188; + } else { + return 188; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_STATE::Viewport Z ClipTest Enable */ + + +#define GEN5_CLIP_STATE_ViewportZClipTestEnable_bits 1 +#define GEN45_CLIP_STATE_ViewportZClipTestEnable_bits 1 +#define GEN4_CLIP_STATE_ViewportZClipTestEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_ViewportZClipTestEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CLIP_STATE_ViewportZClipTestEnable_start 187 +#define GEN45_CLIP_STATE_ViewportZClipTestEnable_start 187 +#define GEN4_CLIP_STATE_ViewportZClipTestEnable_start 187 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_STATE_ViewportZClipTestEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 187; + case 4: + if (devinfo->is_g4x) { + return 187; + } else { + return 187; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_VIEWPORT */ + + +#define GEN6_CLIP_VIEWPORT_length 4 +#define GEN5_CLIP_VIEWPORT_length 4 +#define GEN45_CLIP_VIEWPORT_length 4 +#define GEN4_CLIP_VIEWPORT_length 4 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_VIEWPORT_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 4; + case 5: return 4; + case 4: + if (devinfo->is_g4x) { + return 4; + } else { + return 4; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_VIEWPORT::XMax Clip Guardband */ + + +#define GEN6_CLIP_VIEWPORT_XMaxClipGuardband_bits 32 +#define GEN5_CLIP_VIEWPORT_XMaxClipGuardband_bits 32 +#define GEN45_CLIP_VIEWPORT_XMaxClipGuardband_bits 32 +#define GEN4_CLIP_VIEWPORT_XMaxClipGuardband_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_VIEWPORT_XMaxClipGuardband_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_CLIP_VIEWPORT_XMaxClipGuardband_start 32 +#define GEN5_CLIP_VIEWPORT_XMaxClipGuardband_start 32 +#define GEN45_CLIP_VIEWPORT_XMaxClipGuardband_start 32 +#define GEN4_CLIP_VIEWPORT_XMaxClipGuardband_start 32 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_VIEWPORT_XMaxClipGuardband_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_VIEWPORT::XMin Clip Guardband */ + + +#define GEN6_CLIP_VIEWPORT_XMinClipGuardband_bits 32 +#define GEN5_CLIP_VIEWPORT_XMinClipGuardband_bits 32 +#define GEN45_CLIP_VIEWPORT_XMinClipGuardband_bits 32 +#define GEN4_CLIP_VIEWPORT_XMinClipGuardband_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_VIEWPORT_XMinClipGuardband_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_CLIP_VIEWPORT_XMinClipGuardband_start 0 +#define GEN5_CLIP_VIEWPORT_XMinClipGuardband_start 0 +#define GEN45_CLIP_VIEWPORT_XMinClipGuardband_start 0 +#define GEN4_CLIP_VIEWPORT_XMinClipGuardband_start 0 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_VIEWPORT_XMinClipGuardband_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_VIEWPORT::YMax Clip Guardband */ + + +#define GEN6_CLIP_VIEWPORT_YMaxClipGuardband_bits 32 +#define GEN5_CLIP_VIEWPORT_YMaxClipGuardband_bits 32 +#define GEN45_CLIP_VIEWPORT_YMaxClipGuardband_bits 32 +#define GEN4_CLIP_VIEWPORT_YMaxClipGuardband_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_VIEWPORT_YMaxClipGuardband_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_CLIP_VIEWPORT_YMaxClipGuardband_start 96 +#define GEN5_CLIP_VIEWPORT_YMaxClipGuardband_start 96 +#define GEN45_CLIP_VIEWPORT_YMaxClipGuardband_start 96 +#define GEN4_CLIP_VIEWPORT_YMaxClipGuardband_start 96 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_VIEWPORT_YMaxClipGuardband_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 96; + case 5: return 96; + case 4: + if (devinfo->is_g4x) { + return 96; + } else { + return 96; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CLIP_VIEWPORT::YMin Clip Guardband */ + + +#define GEN6_CLIP_VIEWPORT_YMinClipGuardband_bits 32 +#define GEN5_CLIP_VIEWPORT_YMinClipGuardband_bits 32 +#define GEN45_CLIP_VIEWPORT_YMinClipGuardband_bits 32 +#define GEN4_CLIP_VIEWPORT_YMinClipGuardband_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_VIEWPORT_YMinClipGuardband_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_CLIP_VIEWPORT_YMinClipGuardband_start 64 +#define GEN5_CLIP_VIEWPORT_YMinClipGuardband_start 64 +#define GEN45_CLIP_VIEWPORT_YMinClipGuardband_start 64 +#define GEN4_CLIP_VIEWPORT_YMinClipGuardband_start 64 + +static inline uint32_t ATTRIBUTE_PURE +CLIP_VIEWPORT_YMinClipGuardband_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 64; + case 5: return 64; + case 4: + if (devinfo->is_g4x) { + return 64; + } else { + return 64; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CL_INVOCATION_COUNT */ + + +#define GEN11_CL_INVOCATION_COUNT_length 2 +#define GEN10_CL_INVOCATION_COUNT_length 2 +#define GEN9_CL_INVOCATION_COUNT_length 2 +#define GEN8_CL_INVOCATION_COUNT_length 2 +#define GEN75_CL_INVOCATION_COUNT_length 2 +#define GEN7_CL_INVOCATION_COUNT_length 2 + +static inline uint32_t ATTRIBUTE_PURE +CL_INVOCATION_COUNT_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CL_INVOCATION_COUNT::CL Invocation Count Report */ + + +#define GEN11_CL_INVOCATION_COUNT_CLInvocationCountReport_bits 64 +#define GEN10_CL_INVOCATION_COUNT_CLInvocationCountReport_bits 64 +#define GEN9_CL_INVOCATION_COUNT_CLInvocationCountReport_bits 64 +#define GEN8_CL_INVOCATION_COUNT_CLInvocationCountReport_bits 64 +#define GEN75_CL_INVOCATION_COUNT_CLInvocationCountReport_bits 64 +#define GEN7_CL_INVOCATION_COUNT_CLInvocationCountReport_bits 64 + +static inline uint32_t ATTRIBUTE_PURE +CL_INVOCATION_COUNT_CLInvocationCountReport_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CL_INVOCATION_COUNT_CLInvocationCountReport_start 0 +#define GEN10_CL_INVOCATION_COUNT_CLInvocationCountReport_start 0 +#define GEN9_CL_INVOCATION_COUNT_CLInvocationCountReport_start 0 +#define GEN8_CL_INVOCATION_COUNT_CLInvocationCountReport_start 0 +#define GEN75_CL_INVOCATION_COUNT_CLInvocationCountReport_start 0 +#define GEN7_CL_INVOCATION_COUNT_CLInvocationCountReport_start 0 + +static inline uint32_t ATTRIBUTE_PURE +CL_INVOCATION_COUNT_CLInvocationCountReport_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CL_PRIMITIVES_COUNT */ + + +#define GEN11_CL_PRIMITIVES_COUNT_length 2 +#define GEN10_CL_PRIMITIVES_COUNT_length 2 +#define GEN9_CL_PRIMITIVES_COUNT_length 2 +#define GEN8_CL_PRIMITIVES_COUNT_length 2 +#define GEN75_CL_PRIMITIVES_COUNT_length 2 +#define GEN7_CL_PRIMITIVES_COUNT_length 2 + +static inline uint32_t ATTRIBUTE_PURE +CL_PRIMITIVES_COUNT_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CL_PRIMITIVES_COUNT::CL Primitives Count Report */ + + +#define GEN11_CL_PRIMITIVES_COUNT_CLPrimitivesCountReport_bits 64 +#define GEN10_CL_PRIMITIVES_COUNT_CLPrimitivesCountReport_bits 64 +#define GEN9_CL_PRIMITIVES_COUNT_CLPrimitivesCountReport_bits 64 +#define GEN8_CL_PRIMITIVES_COUNT_CLPrimitivesCountReport_bits 64 +#define GEN75_CL_PRIMITIVES_COUNT_CLPrimitivesCountReport_bits 64 +#define GEN7_CL_PRIMITIVES_COUNT_CLPrimitivesCountReport_bits 64 + +static inline uint32_t ATTRIBUTE_PURE +CL_PRIMITIVES_COUNT_CLPrimitivesCountReport_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CL_PRIMITIVES_COUNT_CLPrimitivesCountReport_start 0 +#define GEN10_CL_PRIMITIVES_COUNT_CLPrimitivesCountReport_start 0 +#define GEN9_CL_PRIMITIVES_COUNT_CLPrimitivesCountReport_start 0 +#define GEN8_CL_PRIMITIVES_COUNT_CLPrimitivesCountReport_start 0 +#define GEN75_CL_PRIMITIVES_COUNT_CLPrimitivesCountReport_start 0 +#define GEN7_CL_PRIMITIVES_COUNT_CLPrimitivesCountReport_start 0 + +static inline uint32_t ATTRIBUTE_PURE +CL_PRIMITIVES_COUNT_CLPrimitivesCountReport_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE */ + + +#define GEN11_COLOR_CALC_STATE_length 6 +#define GEN10_COLOR_CALC_STATE_length 6 +#define GEN9_COLOR_CALC_STATE_length 6 +#define GEN8_COLOR_CALC_STATE_length 6 +#define GEN75_COLOR_CALC_STATE_length 6 +#define GEN7_COLOR_CALC_STATE_length 6 +#define GEN6_COLOR_CALC_STATE_length 6 +#define GEN5_COLOR_CALC_STATE_length 8 +#define GEN45_COLOR_CALC_STATE_length 8 +#define GEN4_COLOR_CALC_STATE_length 8 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 6; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Alpha Blend Function */ + + +#define GEN5_COLOR_CALC_STATE_AlphaBlendFunction_bits 3 +#define GEN45_COLOR_CALC_STATE_AlphaBlendFunction_bits 3 +#define GEN4_COLOR_CALC_STATE_AlphaBlendFunction_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_AlphaBlendFunction_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_COLOR_CALC_STATE_AlphaBlendFunction_start 172 +#define GEN45_COLOR_CALC_STATE_AlphaBlendFunction_start 172 +#define GEN4_COLOR_CALC_STATE_AlphaBlendFunction_start 172 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_AlphaBlendFunction_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 172; + case 4: + if (devinfo->is_g4x) { + return 172; + } else { + return 172; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Alpha Reference Value As FLOAT32 */ + + +#define GEN11_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_bits 32 +#define GEN10_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_bits 32 +#define GEN9_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_bits 32 +#define GEN8_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_bits 32 +#define GEN75_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_bits 32 +#define GEN7_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_bits 32 +#define GEN6_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_bits 32 +#define GEN5_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_bits 32 +#define GEN45_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_bits 32 +#define GEN4_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_start 32 +#define GEN10_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_start 32 +#define GEN9_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_start 32 +#define GEN8_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_start 32 +#define GEN75_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_start 32 +#define GEN7_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_start 32 +#define GEN6_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_start 32 +#define GEN5_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_start 224 +#define GEN45_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_start 224 +#define GEN4_COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_start 224 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_AlphaReferenceValueAsFLOAT32_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 224; + case 4: + if (devinfo->is_g4x) { + return 224; + } else { + return 224; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Alpha Reference Value As UNORM8 */ + + +#define GEN11_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_bits 32 +#define GEN10_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_bits 32 +#define GEN9_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_bits 32 +#define GEN8_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_bits 32 +#define GEN75_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_bits 32 +#define GEN7_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_bits 32 +#define GEN6_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_bits 32 +#define GEN5_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_bits 32 +#define GEN45_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_bits 32 +#define GEN4_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_start 32 +#define GEN10_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_start 32 +#define GEN9_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_start 32 +#define GEN8_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_start 32 +#define GEN75_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_start 32 +#define GEN7_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_start 32 +#define GEN6_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_start 32 +#define GEN5_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_start 224 +#define GEN45_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_start 224 +#define GEN4_COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_start 224 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_AlphaReferenceValueAsUNORM8_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 224; + case 4: + if (devinfo->is_g4x) { + return 224; + } else { + return 224; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Alpha Test Enable */ + + +#define GEN5_COLOR_CALC_STATE_AlphaTestEnable_bits 1 +#define GEN45_COLOR_CALC_STATE_AlphaTestEnable_bits 1 +#define GEN4_COLOR_CALC_STATE_AlphaTestEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_AlphaTestEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_COLOR_CALC_STATE_AlphaTestEnable_start 107 +#define GEN45_COLOR_CALC_STATE_AlphaTestEnable_start 107 +#define GEN4_COLOR_CALC_STATE_AlphaTestEnable_start 107 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_AlphaTestEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 107; + case 4: + if (devinfo->is_g4x) { + return 107; + } else { + return 107; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Alpha Test Format */ + + +#define GEN11_COLOR_CALC_STATE_AlphaTestFormat_bits 1 +#define GEN10_COLOR_CALC_STATE_AlphaTestFormat_bits 1 +#define GEN9_COLOR_CALC_STATE_AlphaTestFormat_bits 1 +#define GEN8_COLOR_CALC_STATE_AlphaTestFormat_bits 1 +#define GEN75_COLOR_CALC_STATE_AlphaTestFormat_bits 1 +#define GEN7_COLOR_CALC_STATE_AlphaTestFormat_bits 1 +#define GEN6_COLOR_CALC_STATE_AlphaTestFormat_bits 1 +#define GEN5_COLOR_CALC_STATE_AlphaTestFormat_bits 1 +#define GEN45_COLOR_CALC_STATE_AlphaTestFormat_bits 1 +#define GEN4_COLOR_CALC_STATE_AlphaTestFormat_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_AlphaTestFormat_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_COLOR_CALC_STATE_AlphaTestFormat_start 0 +#define GEN10_COLOR_CALC_STATE_AlphaTestFormat_start 0 +#define GEN9_COLOR_CALC_STATE_AlphaTestFormat_start 0 +#define GEN8_COLOR_CALC_STATE_AlphaTestFormat_start 0 +#define GEN75_COLOR_CALC_STATE_AlphaTestFormat_start 0 +#define GEN7_COLOR_CALC_STATE_AlphaTestFormat_start 0 +#define GEN6_COLOR_CALC_STATE_AlphaTestFormat_start 0 +#define GEN5_COLOR_CALC_STATE_AlphaTestFormat_start 111 +#define GEN45_COLOR_CALC_STATE_AlphaTestFormat_start 111 +#define GEN4_COLOR_CALC_STATE_AlphaTestFormat_start 111 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_AlphaTestFormat_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 111; + case 4: + if (devinfo->is_g4x) { + return 111; + } else { + return 111; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Alpha Test Function */ + + +#define GEN5_COLOR_CALC_STATE_AlphaTestFunction_bits 3 +#define GEN45_COLOR_CALC_STATE_AlphaTestFunction_bits 3 +#define GEN4_COLOR_CALC_STATE_AlphaTestFunction_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_AlphaTestFunction_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_COLOR_CALC_STATE_AlphaTestFunction_start 104 +#define GEN45_COLOR_CALC_STATE_AlphaTestFunction_start 104 +#define GEN4_COLOR_CALC_STATE_AlphaTestFunction_start 104 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_AlphaTestFunction_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 104; + case 4: + if (devinfo->is_g4x) { + return 104; + } else { + return 104; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Backface Stencil Fail Op */ + + +#define GEN5_COLOR_CALC_STATE_BackfaceStencilFailOp_bits 3 +#define GEN45_COLOR_CALC_STATE_BackfaceStencilFailOp_bits 3 +#define GEN4_COLOR_CALC_STATE_BackfaceStencilFailOp_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_BackfaceStencilFailOp_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_COLOR_CALC_STATE_BackfaceStencilFailOp_start 9 +#define GEN45_COLOR_CALC_STATE_BackfaceStencilFailOp_start 9 +#define GEN4_COLOR_CALC_STATE_BackfaceStencilFailOp_start 9 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_BackfaceStencilFailOp_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 9; + case 4: + if (devinfo->is_g4x) { + return 9; + } else { + return 9; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Backface Stencil Pass Depth Fail Op */ + + +#define GEN5_COLOR_CALC_STATE_BackfaceStencilPassDepthFailOp_bits 3 +#define GEN45_COLOR_CALC_STATE_BackfaceStencilPassDepthFailOp_bits 3 +#define GEN4_COLOR_CALC_STATE_BackfaceStencilPassDepthFailOp_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_BackfaceStencilPassDepthFailOp_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_COLOR_CALC_STATE_BackfaceStencilPassDepthFailOp_start 6 +#define GEN45_COLOR_CALC_STATE_BackfaceStencilPassDepthFailOp_start 6 +#define GEN4_COLOR_CALC_STATE_BackfaceStencilPassDepthFailOp_start 6 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_BackfaceStencilPassDepthFailOp_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Backface Stencil Pass Depth Pass Op */ + + +#define GEN5_COLOR_CALC_STATE_BackfaceStencilPassDepthPassOp_bits 3 +#define GEN45_COLOR_CALC_STATE_BackfaceStencilPassDepthPassOp_bits 3 +#define GEN4_COLOR_CALC_STATE_BackfaceStencilPassDepthPassOp_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_BackfaceStencilPassDepthPassOp_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_COLOR_CALC_STATE_BackfaceStencilPassDepthPassOp_start 3 +#define GEN45_COLOR_CALC_STATE_BackfaceStencilPassDepthPassOp_start 3 +#define GEN4_COLOR_CALC_STATE_BackfaceStencilPassDepthPassOp_start 3 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_BackfaceStencilPassDepthPassOp_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Backface Stencil Reference Value */ + + +#define GEN8_COLOR_CALC_STATE_BackfaceStencilReferenceValue_bits 8 +#define GEN75_COLOR_CALC_STATE_BackfaceStencilReferenceValue_bits 8 +#define GEN7_COLOR_CALC_STATE_BackfaceStencilReferenceValue_bits 8 +#define GEN6_COLOR_CALC_STATE_BackfaceStencilReferenceValue_bits 8 +#define GEN5_COLOR_CALC_STATE_BackfaceStencilReferenceValue_bits 8 +#define GEN45_COLOR_CALC_STATE_BackfaceStencilReferenceValue_bits 8 +#define GEN4_COLOR_CALC_STATE_BackfaceStencilReferenceValue_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_BackfaceStencilReferenceValue_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_COLOR_CALC_STATE_BackfaceStencilReferenceValue_start 16 +#define GEN75_COLOR_CALC_STATE_BackfaceStencilReferenceValue_start 16 +#define GEN7_COLOR_CALC_STATE_BackfaceStencilReferenceValue_start 16 +#define GEN6_COLOR_CALC_STATE_BackfaceStencilReferenceValue_start 16 +#define GEN5_COLOR_CALC_STATE_BackfaceStencilReferenceValue_start 32 +#define GEN45_COLOR_CALC_STATE_BackfaceStencilReferenceValue_start 32 +#define GEN4_COLOR_CALC_STATE_BackfaceStencilReferenceValue_start 32 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_BackfaceStencilReferenceValue_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Backface Stencil Test Function */ + + +#define GEN5_COLOR_CALC_STATE_BackfaceStencilTestFunction_bits 3 +#define GEN45_COLOR_CALC_STATE_BackfaceStencilTestFunction_bits 3 +#define GEN4_COLOR_CALC_STATE_BackfaceStencilTestFunction_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_BackfaceStencilTestFunction_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_COLOR_CALC_STATE_BackfaceStencilTestFunction_start 12 +#define GEN45_COLOR_CALC_STATE_BackfaceStencilTestFunction_start 12 +#define GEN4_COLOR_CALC_STATE_BackfaceStencilTestFunction_start 12 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_BackfaceStencilTestFunction_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 12; + case 4: + if (devinfo->is_g4x) { + return 12; + } else { + return 12; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Backface Stencil Test Mask */ + + +#define GEN5_COLOR_CALC_STATE_BackfaceStencilTestMask_bits 8 +#define GEN45_COLOR_CALC_STATE_BackfaceStencilTestMask_bits 8 +#define GEN4_COLOR_CALC_STATE_BackfaceStencilTestMask_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_BackfaceStencilTestMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_COLOR_CALC_STATE_BackfaceStencilTestMask_start 88 +#define GEN45_COLOR_CALC_STATE_BackfaceStencilTestMask_start 88 +#define GEN4_COLOR_CALC_STATE_BackfaceStencilTestMask_start 88 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_BackfaceStencilTestMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 88; + case 4: + if (devinfo->is_g4x) { + return 88; + } else { + return 88; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Backface Stencil Write Mask */ + + +#define GEN5_COLOR_CALC_STATE_BackfaceStencilWriteMask_bits 8 +#define GEN45_COLOR_CALC_STATE_BackfaceStencilWriteMask_bits 8 +#define GEN4_COLOR_CALC_STATE_BackfaceStencilWriteMask_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_BackfaceStencilWriteMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_COLOR_CALC_STATE_BackfaceStencilWriteMask_start 80 +#define GEN45_COLOR_CALC_STATE_BackfaceStencilWriteMask_start 80 +#define GEN4_COLOR_CALC_STATE_BackfaceStencilWriteMask_start 80 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_BackfaceStencilWriteMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 80; + case 4: + if (devinfo->is_g4x) { + return 80; + } else { + return 80; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Blend Constant Color Alpha */ + + +#define GEN11_COLOR_CALC_STATE_BlendConstantColorAlpha_bits 32 +#define GEN10_COLOR_CALC_STATE_BlendConstantColorAlpha_bits 32 +#define GEN9_COLOR_CALC_STATE_BlendConstantColorAlpha_bits 32 +#define GEN8_COLOR_CALC_STATE_BlendConstantColorAlpha_bits 32 +#define GEN75_COLOR_CALC_STATE_BlendConstantColorAlpha_bits 32 +#define GEN7_COLOR_CALC_STATE_BlendConstantColorAlpha_bits 32 +#define GEN6_COLOR_CALC_STATE_BlendConstantColorAlpha_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_BlendConstantColorAlpha_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_COLOR_CALC_STATE_BlendConstantColorAlpha_start 160 +#define GEN10_COLOR_CALC_STATE_BlendConstantColorAlpha_start 160 +#define GEN9_COLOR_CALC_STATE_BlendConstantColorAlpha_start 160 +#define GEN8_COLOR_CALC_STATE_BlendConstantColorAlpha_start 160 +#define GEN75_COLOR_CALC_STATE_BlendConstantColorAlpha_start 160 +#define GEN7_COLOR_CALC_STATE_BlendConstantColorAlpha_start 160 +#define GEN6_COLOR_CALC_STATE_BlendConstantColorAlpha_start 160 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_BlendConstantColorAlpha_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 160; + case 10: return 160; + case 9: return 160; + case 8: return 160; + case 7: + if (devinfo->is_haswell) { + return 160; + } else { + return 160; + } + case 6: return 160; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Blend Constant Color Blue */ + + +#define GEN11_COLOR_CALC_STATE_BlendConstantColorBlue_bits 32 +#define GEN10_COLOR_CALC_STATE_BlendConstantColorBlue_bits 32 +#define GEN9_COLOR_CALC_STATE_BlendConstantColorBlue_bits 32 +#define GEN8_COLOR_CALC_STATE_BlendConstantColorBlue_bits 32 +#define GEN75_COLOR_CALC_STATE_BlendConstantColorBlue_bits 32 +#define GEN7_COLOR_CALC_STATE_BlendConstantColorBlue_bits 32 +#define GEN6_COLOR_CALC_STATE_BlendConstantColorBlue_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_BlendConstantColorBlue_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_COLOR_CALC_STATE_BlendConstantColorBlue_start 128 +#define GEN10_COLOR_CALC_STATE_BlendConstantColorBlue_start 128 +#define GEN9_COLOR_CALC_STATE_BlendConstantColorBlue_start 128 +#define GEN8_COLOR_CALC_STATE_BlendConstantColorBlue_start 128 +#define GEN75_COLOR_CALC_STATE_BlendConstantColorBlue_start 128 +#define GEN7_COLOR_CALC_STATE_BlendConstantColorBlue_start 128 +#define GEN6_COLOR_CALC_STATE_BlendConstantColorBlue_start 128 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_BlendConstantColorBlue_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 128; + case 10: return 128; + case 9: return 128; + case 8: return 128; + case 7: + if (devinfo->is_haswell) { + return 128; + } else { + return 128; + } + case 6: return 128; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Blend Constant Color Green */ + + +#define GEN11_COLOR_CALC_STATE_BlendConstantColorGreen_bits 32 +#define GEN10_COLOR_CALC_STATE_BlendConstantColorGreen_bits 32 +#define GEN9_COLOR_CALC_STATE_BlendConstantColorGreen_bits 32 +#define GEN8_COLOR_CALC_STATE_BlendConstantColorGreen_bits 32 +#define GEN75_COLOR_CALC_STATE_BlendConstantColorGreen_bits 32 +#define GEN7_COLOR_CALC_STATE_BlendConstantColorGreen_bits 32 +#define GEN6_COLOR_CALC_STATE_BlendConstantColorGreen_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_BlendConstantColorGreen_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_COLOR_CALC_STATE_BlendConstantColorGreen_start 96 +#define GEN10_COLOR_CALC_STATE_BlendConstantColorGreen_start 96 +#define GEN9_COLOR_CALC_STATE_BlendConstantColorGreen_start 96 +#define GEN8_COLOR_CALC_STATE_BlendConstantColorGreen_start 96 +#define GEN75_COLOR_CALC_STATE_BlendConstantColorGreen_start 96 +#define GEN7_COLOR_CALC_STATE_BlendConstantColorGreen_start 96 +#define GEN6_COLOR_CALC_STATE_BlendConstantColorGreen_start 96 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_BlendConstantColorGreen_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 96; + case 10: return 96; + case 9: return 96; + case 8: return 96; + case 7: + if (devinfo->is_haswell) { + return 96; + } else { + return 96; + } + case 6: return 96; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Blend Constant Color Red */ + + +#define GEN11_COLOR_CALC_STATE_BlendConstantColorRed_bits 32 +#define GEN10_COLOR_CALC_STATE_BlendConstantColorRed_bits 32 +#define GEN9_COLOR_CALC_STATE_BlendConstantColorRed_bits 32 +#define GEN8_COLOR_CALC_STATE_BlendConstantColorRed_bits 32 +#define GEN75_COLOR_CALC_STATE_BlendConstantColorRed_bits 32 +#define GEN7_COLOR_CALC_STATE_BlendConstantColorRed_bits 32 +#define GEN6_COLOR_CALC_STATE_BlendConstantColorRed_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_BlendConstantColorRed_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_COLOR_CALC_STATE_BlendConstantColorRed_start 64 +#define GEN10_COLOR_CALC_STATE_BlendConstantColorRed_start 64 +#define GEN9_COLOR_CALC_STATE_BlendConstantColorRed_start 64 +#define GEN8_COLOR_CALC_STATE_BlendConstantColorRed_start 64 +#define GEN75_COLOR_CALC_STATE_BlendConstantColorRed_start 64 +#define GEN7_COLOR_CALC_STATE_BlendConstantColorRed_start 64 +#define GEN6_COLOR_CALC_STATE_BlendConstantColorRed_start 64 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_BlendConstantColorRed_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 64; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::CC Viewport State Pointer */ + + +#define GEN5_COLOR_CALC_STATE_CCViewportStatePointer_bits 27 +#define GEN45_COLOR_CALC_STATE_CCViewportStatePointer_bits 27 +#define GEN4_COLOR_CALC_STATE_CCViewportStatePointer_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_CCViewportStatePointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_COLOR_CALC_STATE_CCViewportStatePointer_start 133 +#define GEN45_COLOR_CALC_STATE_CCViewportStatePointer_start 133 +#define GEN4_COLOR_CALC_STATE_CCViewportStatePointer_start 133 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_CCViewportStatePointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 133; + case 4: + if (devinfo->is_g4x) { + return 133; + } else { + return 133; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Color Blend Function */ + + +#define GEN5_COLOR_CALC_STATE_ColorBlendFunction_bits 3 +#define GEN45_COLOR_CALC_STATE_ColorBlendFunction_bits 3 +#define GEN4_COLOR_CALC_STATE_ColorBlendFunction_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_ColorBlendFunction_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_COLOR_CALC_STATE_ColorBlendFunction_start 221 +#define GEN45_COLOR_CALC_STATE_ColorBlendFunction_start 221 +#define GEN4_COLOR_CALC_STATE_ColorBlendFunction_start 221 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_ColorBlendFunction_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 221; + case 4: + if (devinfo->is_g4x) { + return 221; + } else { + return 221; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Color Buffer Blend Enable */ + + +#define GEN5_COLOR_CALC_STATE_ColorBufferBlendEnable_bits 1 +#define GEN45_COLOR_CALC_STATE_ColorBufferBlendEnable_bits 1 +#define GEN4_COLOR_CALC_STATE_ColorBufferBlendEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_ColorBufferBlendEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_COLOR_CALC_STATE_ColorBufferBlendEnable_start 108 +#define GEN45_COLOR_CALC_STATE_ColorBufferBlendEnable_start 108 +#define GEN4_COLOR_CALC_STATE_ColorBufferBlendEnable_start 108 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_ColorBufferBlendEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 108; + case 4: + if (devinfo->is_g4x) { + return 108; + } else { + return 108; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Color Clamp Range */ + + +#define GEN5_COLOR_CALC_STATE_ColorClampRange_bits 2 +#define GEN45_COLOR_CALC_STATE_ColorClampRange_bits 2 +#define GEN4_COLOR_CALC_STATE_ColorClampRange_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_ColorClampRange_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_COLOR_CALC_STATE_ColorClampRange_start 194 +#define GEN45_COLOR_CALC_STATE_ColorClampRange_start 194 +#define GEN4_COLOR_CALC_STATE_ColorClampRange_start 194 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_ColorClampRange_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 194; + case 4: + if (devinfo->is_g4x) { + return 194; + } else { + return 194; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Color Dither Enable */ + + +#define GEN5_COLOR_CALC_STATE_ColorDitherEnable_bits 1 +#define GEN45_COLOR_CALC_STATE_ColorDitherEnable_bits 1 +#define GEN4_COLOR_CALC_STATE_ColorDitherEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_ColorDitherEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_COLOR_CALC_STATE_ColorDitherEnable_start 191 +#define GEN45_COLOR_CALC_STATE_ColorDitherEnable_start 191 +#define GEN4_COLOR_CALC_STATE_ColorDitherEnable_start 191 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_ColorDitherEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 191; + case 4: + if (devinfo->is_g4x) { + return 191; + } else { + return 191; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Depth Buffer Write Enable */ + + +#define GEN5_COLOR_CALC_STATE_DepthBufferWriteEnable_bits 1 +#define GEN45_COLOR_CALC_STATE_DepthBufferWriteEnable_bits 1 +#define GEN4_COLOR_CALC_STATE_DepthBufferWriteEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_DepthBufferWriteEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_COLOR_CALC_STATE_DepthBufferWriteEnable_start 75 +#define GEN45_COLOR_CALC_STATE_DepthBufferWriteEnable_start 75 +#define GEN4_COLOR_CALC_STATE_DepthBufferWriteEnable_start 75 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_DepthBufferWriteEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 75; + case 4: + if (devinfo->is_g4x) { + return 75; + } else { + return 75; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Depth Test Enable */ + + +#define GEN5_COLOR_CALC_STATE_DepthTestEnable_bits 1 +#define GEN45_COLOR_CALC_STATE_DepthTestEnable_bits 1 +#define GEN4_COLOR_CALC_STATE_DepthTestEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_DepthTestEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_COLOR_CALC_STATE_DepthTestEnable_start 79 +#define GEN45_COLOR_CALC_STATE_DepthTestEnable_start 79 +#define GEN4_COLOR_CALC_STATE_DepthTestEnable_start 79 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_DepthTestEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 79; + case 4: + if (devinfo->is_g4x) { + return 79; + } else { + return 79; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Depth Test Function */ + + +#define GEN5_COLOR_CALC_STATE_DepthTestFunction_bits 3 +#define GEN45_COLOR_CALC_STATE_DepthTestFunction_bits 3 +#define GEN4_COLOR_CALC_STATE_DepthTestFunction_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_DepthTestFunction_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_COLOR_CALC_STATE_DepthTestFunction_start 76 +#define GEN45_COLOR_CALC_STATE_DepthTestFunction_start 76 +#define GEN4_COLOR_CALC_STATE_DepthTestFunction_start 76 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_DepthTestFunction_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 76; + case 4: + if (devinfo->is_g4x) { + return 76; + } else { + return 76; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Destination Alpha Blend Factor */ + + +#define GEN5_COLOR_CALC_STATE_DestinationAlphaBlendFactor_bits 5 +#define GEN45_COLOR_CALC_STATE_DestinationAlphaBlendFactor_bits 5 +#define GEN4_COLOR_CALC_STATE_DestinationAlphaBlendFactor_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_DestinationAlphaBlendFactor_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 5; + case 4: + if (devinfo->is_g4x) { + return 5; + } else { + return 5; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_COLOR_CALC_STATE_DestinationAlphaBlendFactor_start 162 +#define GEN45_COLOR_CALC_STATE_DestinationAlphaBlendFactor_start 162 +#define GEN4_COLOR_CALC_STATE_DestinationAlphaBlendFactor_start 162 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_DestinationAlphaBlendFactor_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 162; + case 4: + if (devinfo->is_g4x) { + return 162; + } else { + return 162; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Destination Blend Factor */ + + +#define GEN5_COLOR_CALC_STATE_DestinationBlendFactor_bits 5 +#define GEN45_COLOR_CALC_STATE_DestinationBlendFactor_bits 5 +#define GEN4_COLOR_CALC_STATE_DestinationBlendFactor_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_DestinationBlendFactor_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 5; + case 4: + if (devinfo->is_g4x) { + return 5; + } else { + return 5; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_COLOR_CALC_STATE_DestinationBlendFactor_start 211 +#define GEN45_COLOR_CALC_STATE_DestinationBlendFactor_start 211 +#define GEN4_COLOR_CALC_STATE_DestinationBlendFactor_start 211 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_DestinationBlendFactor_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 211; + case 4: + if (devinfo->is_g4x) { + return 211; + } else { + return 211; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Double Sided Stencil Enable */ + + +#define GEN5_COLOR_CALC_STATE_DoubleSidedStencilEnable_bits 1 +#define GEN45_COLOR_CALC_STATE_DoubleSidedStencilEnable_bits 1 +#define GEN4_COLOR_CALC_STATE_DoubleSidedStencilEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_DoubleSidedStencilEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_COLOR_CALC_STATE_DoubleSidedStencilEnable_start 15 +#define GEN45_COLOR_CALC_STATE_DoubleSidedStencilEnable_start 15 +#define GEN4_COLOR_CALC_STATE_DoubleSidedStencilEnable_start 15 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_DoubleSidedStencilEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 15; + case 4: + if (devinfo->is_g4x) { + return 15; + } else { + return 15; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Independent Alpha Blend Enable */ + + +#define GEN5_COLOR_CALC_STATE_IndependentAlphaBlendEnable_bits 1 +#define GEN45_COLOR_CALC_STATE_IndependentAlphaBlendEnable_bits 1 +#define GEN4_COLOR_CALC_STATE_IndependentAlphaBlendEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_IndependentAlphaBlendEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_COLOR_CALC_STATE_IndependentAlphaBlendEnable_start 109 +#define GEN45_COLOR_CALC_STATE_IndependentAlphaBlendEnable_start 109 +#define GEN4_COLOR_CALC_STATE_IndependentAlphaBlendEnable_start 109 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_IndependentAlphaBlendEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 109; + case 4: + if (devinfo->is_g4x) { + return 109; + } else { + return 109; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Logic Op Enable */ + + +#define GEN5_COLOR_CALC_STATE_LogicOpEnable_bits 1 +#define GEN45_COLOR_CALC_STATE_LogicOpEnable_bits 1 +#define GEN4_COLOR_CALC_STATE_LogicOpEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_LogicOpEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_COLOR_CALC_STATE_LogicOpEnable_start 64 +#define GEN45_COLOR_CALC_STATE_LogicOpEnable_start 64 +#define GEN4_COLOR_CALC_STATE_LogicOpEnable_start 64 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_LogicOpEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 64; + case 4: + if (devinfo->is_g4x) { + return 64; + } else { + return 64; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Logic Op Function */ + + +#define GEN5_COLOR_CALC_STATE_LogicOpFunction_bits 4 +#define GEN45_COLOR_CALC_STATE_LogicOpFunction_bits 4 +#define GEN4_COLOR_CALC_STATE_LogicOpFunction_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_LogicOpFunction_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 4; + case 4: + if (devinfo->is_g4x) { + return 4; + } else { + return 4; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_COLOR_CALC_STATE_LogicOpFunction_start 176 +#define GEN45_COLOR_CALC_STATE_LogicOpFunction_start 176 +#define GEN4_COLOR_CALC_STATE_LogicOpFunction_start 176 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_LogicOpFunction_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 176; + case 4: + if (devinfo->is_g4x) { + return 176; + } else { + return 176; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Post-Blend Color Clamp Enable */ + + +#define GEN5_COLOR_CALC_STATE_PostBlendColorClampEnable_bits 1 +#define GEN45_COLOR_CALC_STATE_PostBlendColorClampEnable_bits 1 +#define GEN4_COLOR_CALC_STATE_PostBlendColorClampEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_PostBlendColorClampEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_COLOR_CALC_STATE_PostBlendColorClampEnable_start 192 +#define GEN45_COLOR_CALC_STATE_PostBlendColorClampEnable_start 192 +#define GEN4_COLOR_CALC_STATE_PostBlendColorClampEnable_start 192 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_PostBlendColorClampEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 192; + case 4: + if (devinfo->is_g4x) { + return 192; + } else { + return 192; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Pre-Blend Color Clamp Enable */ + + +#define GEN5_COLOR_CALC_STATE_PreBlendColorClampEnable_bits 1 +#define GEN45_COLOR_CALC_STATE_PreBlendColorClampEnable_bits 1 +#define GEN4_COLOR_CALC_STATE_PreBlendColorClampEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_PreBlendColorClampEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_COLOR_CALC_STATE_PreBlendColorClampEnable_start 193 +#define GEN45_COLOR_CALC_STATE_PreBlendColorClampEnable_start 193 +#define GEN4_COLOR_CALC_STATE_PreBlendColorClampEnable_start 193 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_PreBlendColorClampEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 193; + case 4: + if (devinfo->is_g4x) { + return 193; + } else { + return 193; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Round Disable Function Disable */ + + +#define GEN11_COLOR_CALC_STATE_RoundDisableFunctionDisable_bits 1 +#define GEN10_COLOR_CALC_STATE_RoundDisableFunctionDisable_bits 1 +#define GEN9_COLOR_CALC_STATE_RoundDisableFunctionDisable_bits 1 +#define GEN8_COLOR_CALC_STATE_RoundDisableFunctionDisable_bits 1 +#define GEN75_COLOR_CALC_STATE_RoundDisableFunctionDisable_bits 1 +#define GEN7_COLOR_CALC_STATE_RoundDisableFunctionDisable_bits 1 +#define GEN6_COLOR_CALC_STATE_RoundDisableFunctionDisable_bits 1 +#define GEN5_COLOR_CALC_STATE_RoundDisableFunctionDisable_bits 1 +#define GEN45_COLOR_CALC_STATE_RoundDisableFunctionDisable_bits 1 +#define GEN4_COLOR_CALC_STATE_RoundDisableFunctionDisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_RoundDisableFunctionDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_COLOR_CALC_STATE_RoundDisableFunctionDisable_start 15 +#define GEN10_COLOR_CALC_STATE_RoundDisableFunctionDisable_start 15 +#define GEN9_COLOR_CALC_STATE_RoundDisableFunctionDisable_start 15 +#define GEN8_COLOR_CALC_STATE_RoundDisableFunctionDisable_start 15 +#define GEN75_COLOR_CALC_STATE_RoundDisableFunctionDisable_start 15 +#define GEN7_COLOR_CALC_STATE_RoundDisableFunctionDisable_start 15 +#define GEN6_COLOR_CALC_STATE_RoundDisableFunctionDisable_start 15 +#define GEN5_COLOR_CALC_STATE_RoundDisableFunctionDisable_start 190 +#define GEN45_COLOR_CALC_STATE_RoundDisableFunctionDisable_start 190 +#define GEN4_COLOR_CALC_STATE_RoundDisableFunctionDisable_start 190 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_RoundDisableFunctionDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 15; + case 10: return 15; + case 9: return 15; + case 8: return 15; + case 7: + if (devinfo->is_haswell) { + return 15; + } else { + return 15; + } + case 6: return 15; + case 5: return 190; + case 4: + if (devinfo->is_g4x) { + return 190; + } else { + return 190; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Source Alpha Blend Factor */ + + +#define GEN5_COLOR_CALC_STATE_SourceAlphaBlendFactor_bits 5 +#define GEN45_COLOR_CALC_STATE_SourceAlphaBlendFactor_bits 5 +#define GEN4_COLOR_CALC_STATE_SourceAlphaBlendFactor_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_SourceAlphaBlendFactor_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 5; + case 4: + if (devinfo->is_g4x) { + return 5; + } else { + return 5; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_COLOR_CALC_STATE_SourceAlphaBlendFactor_start 167 +#define GEN45_COLOR_CALC_STATE_SourceAlphaBlendFactor_start 167 +#define GEN4_COLOR_CALC_STATE_SourceAlphaBlendFactor_start 167 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_SourceAlphaBlendFactor_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 167; + case 4: + if (devinfo->is_g4x) { + return 167; + } else { + return 167; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Source Blend Factor */ + + +#define GEN5_COLOR_CALC_STATE_SourceBlendFactor_bits 5 +#define GEN45_COLOR_CALC_STATE_SourceBlendFactor_bits 5 +#define GEN4_COLOR_CALC_STATE_SourceBlendFactor_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_SourceBlendFactor_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 5; + case 4: + if (devinfo->is_g4x) { + return 5; + } else { + return 5; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_COLOR_CALC_STATE_SourceBlendFactor_start 216 +#define GEN45_COLOR_CALC_STATE_SourceBlendFactor_start 216 +#define GEN4_COLOR_CALC_STATE_SourceBlendFactor_start 216 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_SourceBlendFactor_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 216; + case 4: + if (devinfo->is_g4x) { + return 216; + } else { + return 216; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Statistics Enable */ + + +#define GEN5_COLOR_CALC_STATE_StatisticsEnable_bits 1 +#define GEN45_COLOR_CALC_STATE_StatisticsEnable_bits 1 +#define GEN4_COLOR_CALC_STATE_StatisticsEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_StatisticsEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_COLOR_CALC_STATE_StatisticsEnable_start 175 +#define GEN45_COLOR_CALC_STATE_StatisticsEnable_start 175 +#define GEN4_COLOR_CALC_STATE_StatisticsEnable_start 175 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_StatisticsEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 175; + case 4: + if (devinfo->is_g4x) { + return 175; + } else { + return 175; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Stencil Buffer Write Enable */ + + +#define GEN5_COLOR_CALC_STATE_StencilBufferWriteEnable_bits 1 +#define GEN45_COLOR_CALC_STATE_StencilBufferWriteEnable_bits 1 +#define GEN4_COLOR_CALC_STATE_StencilBufferWriteEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_StencilBufferWriteEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_COLOR_CALC_STATE_StencilBufferWriteEnable_start 18 +#define GEN45_COLOR_CALC_STATE_StencilBufferWriteEnable_start 18 +#define GEN4_COLOR_CALC_STATE_StencilBufferWriteEnable_start 18 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_StencilBufferWriteEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 18; + case 4: + if (devinfo->is_g4x) { + return 18; + } else { + return 18; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Stencil Fail Op */ + + +#define GEN5_COLOR_CALC_STATE_StencilFailOp_bits 3 +#define GEN45_COLOR_CALC_STATE_StencilFailOp_bits 3 +#define GEN4_COLOR_CALC_STATE_StencilFailOp_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_StencilFailOp_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_COLOR_CALC_STATE_StencilFailOp_start 25 +#define GEN45_COLOR_CALC_STATE_StencilFailOp_start 25 +#define GEN4_COLOR_CALC_STATE_StencilFailOp_start 25 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_StencilFailOp_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 25; + case 4: + if (devinfo->is_g4x) { + return 25; + } else { + return 25; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Stencil Pass Depth Fail Op */ + + +#define GEN5_COLOR_CALC_STATE_StencilPassDepthFailOp_bits 3 +#define GEN45_COLOR_CALC_STATE_StencilPassDepthFailOp_bits 3 +#define GEN4_COLOR_CALC_STATE_StencilPassDepthFailOp_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_StencilPassDepthFailOp_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_COLOR_CALC_STATE_StencilPassDepthFailOp_start 22 +#define GEN45_COLOR_CALC_STATE_StencilPassDepthFailOp_start 22 +#define GEN4_COLOR_CALC_STATE_StencilPassDepthFailOp_start 22 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_StencilPassDepthFailOp_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 22; + case 4: + if (devinfo->is_g4x) { + return 22; + } else { + return 22; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Stencil Pass Depth Pass Op */ + + +#define GEN5_COLOR_CALC_STATE_StencilPassDepthPassOp_bits 3 +#define GEN45_COLOR_CALC_STATE_StencilPassDepthPassOp_bits 3 +#define GEN4_COLOR_CALC_STATE_StencilPassDepthPassOp_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_StencilPassDepthPassOp_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_COLOR_CALC_STATE_StencilPassDepthPassOp_start 19 +#define GEN45_COLOR_CALC_STATE_StencilPassDepthPassOp_start 19 +#define GEN4_COLOR_CALC_STATE_StencilPassDepthPassOp_start 19 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_StencilPassDepthPassOp_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 19; + case 4: + if (devinfo->is_g4x) { + return 19; + } else { + return 19; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Stencil Reference Value */ + + +#define GEN8_COLOR_CALC_STATE_StencilReferenceValue_bits 8 +#define GEN75_COLOR_CALC_STATE_StencilReferenceValue_bits 8 +#define GEN7_COLOR_CALC_STATE_StencilReferenceValue_bits 8 +#define GEN6_COLOR_CALC_STATE_StencilReferenceValue_bits 8 +#define GEN5_COLOR_CALC_STATE_StencilReferenceValue_bits 8 +#define GEN45_COLOR_CALC_STATE_StencilReferenceValue_bits 8 +#define GEN4_COLOR_CALC_STATE_StencilReferenceValue_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_StencilReferenceValue_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_COLOR_CALC_STATE_StencilReferenceValue_start 24 +#define GEN75_COLOR_CALC_STATE_StencilReferenceValue_start 24 +#define GEN7_COLOR_CALC_STATE_StencilReferenceValue_start 24 +#define GEN6_COLOR_CALC_STATE_StencilReferenceValue_start 24 +#define GEN5_COLOR_CALC_STATE_StencilReferenceValue_start 56 +#define GEN45_COLOR_CALC_STATE_StencilReferenceValue_start 56 +#define GEN4_COLOR_CALC_STATE_StencilReferenceValue_start 56 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_StencilReferenceValue_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 56; + case 4: + if (devinfo->is_g4x) { + return 56; + } else { + return 56; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Stencil Test Enable */ + + +#define GEN5_COLOR_CALC_STATE_StencilTestEnable_bits 1 +#define GEN45_COLOR_CALC_STATE_StencilTestEnable_bits 1 +#define GEN4_COLOR_CALC_STATE_StencilTestEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_StencilTestEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_COLOR_CALC_STATE_StencilTestEnable_start 31 +#define GEN45_COLOR_CALC_STATE_StencilTestEnable_start 31 +#define GEN4_COLOR_CALC_STATE_StencilTestEnable_start 31 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_StencilTestEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 31; + case 4: + if (devinfo->is_g4x) { + return 31; + } else { + return 31; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Stencil Test Function */ + + +#define GEN5_COLOR_CALC_STATE_StencilTestFunction_bits 3 +#define GEN45_COLOR_CALC_STATE_StencilTestFunction_bits 3 +#define GEN4_COLOR_CALC_STATE_StencilTestFunction_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_StencilTestFunction_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_COLOR_CALC_STATE_StencilTestFunction_start 28 +#define GEN45_COLOR_CALC_STATE_StencilTestFunction_start 28 +#define GEN4_COLOR_CALC_STATE_StencilTestFunction_start 28 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_StencilTestFunction_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 28; + case 4: + if (devinfo->is_g4x) { + return 28; + } else { + return 28; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Stencil Test Mask */ + + +#define GEN5_COLOR_CALC_STATE_StencilTestMask_bits 8 +#define GEN45_COLOR_CALC_STATE_StencilTestMask_bits 8 +#define GEN4_COLOR_CALC_STATE_StencilTestMask_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_StencilTestMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_COLOR_CALC_STATE_StencilTestMask_start 48 +#define GEN45_COLOR_CALC_STATE_StencilTestMask_start 48 +#define GEN4_COLOR_CALC_STATE_StencilTestMask_start 48 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_StencilTestMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 48; + case 4: + if (devinfo->is_g4x) { + return 48; + } else { + return 48; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Stencil Write Mask */ + + +#define GEN5_COLOR_CALC_STATE_StencilWriteMask_bits 8 +#define GEN45_COLOR_CALC_STATE_StencilWriteMask_bits 8 +#define GEN4_COLOR_CALC_STATE_StencilWriteMask_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_StencilWriteMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_COLOR_CALC_STATE_StencilWriteMask_start 40 +#define GEN45_COLOR_CALC_STATE_StencilWriteMask_start 40 +#define GEN4_COLOR_CALC_STATE_StencilWriteMask_start 40 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_StencilWriteMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 40; + case 4: + if (devinfo->is_g4x) { + return 40; + } else { + return 40; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::X Dither Offset */ + + +#define GEN5_COLOR_CALC_STATE_XDitherOffset_bits 2 +#define GEN45_COLOR_CALC_STATE_XDitherOffset_bits 2 +#define GEN4_COLOR_CALC_STATE_XDitherOffset_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_XDitherOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_COLOR_CALC_STATE_XDitherOffset_start 209 +#define GEN45_COLOR_CALC_STATE_XDitherOffset_start 209 +#define GEN4_COLOR_CALC_STATE_XDitherOffset_start 209 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_XDitherOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 209; + case 4: + if (devinfo->is_g4x) { + return 209; + } else { + return 209; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* COLOR_CALC_STATE::Y Dither Offset */ + + +#define GEN5_COLOR_CALC_STATE_YDitherOffset_bits 2 +#define GEN45_COLOR_CALC_STATE_YDitherOffset_bits 2 +#define GEN4_COLOR_CALC_STATE_YDitherOffset_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_YDitherOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_COLOR_CALC_STATE_YDitherOffset_start 207 +#define GEN45_COLOR_CALC_STATE_YDitherOffset_start 207 +#define GEN4_COLOR_CALC_STATE_YDitherOffset_start 207 + +static inline uint32_t ATTRIBUTE_PURE +COLOR_CALC_STATE_YDitherOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 207; + case 4: + if (devinfo->is_g4x) { + return 207; + } else { + return 207; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CONSTANT_BUFFER */ + + +#define GEN5_CONSTANT_BUFFER_length 2 +#define GEN45_CONSTANT_BUFFER_length 2 +#define GEN4_CONSTANT_BUFFER_length 2 + +static inline uint32_t ATTRIBUTE_PURE +CONSTANT_BUFFER_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CONSTANT_BUFFER::3D Command Opcode */ + + +#define GEN5_CONSTANT_BUFFER_3DCommandOpcode_bits 3 +#define GEN45_CONSTANT_BUFFER_3DCommandOpcode_bits 3 +#define GEN4_CONSTANT_BUFFER_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +CONSTANT_BUFFER_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CONSTANT_BUFFER_3DCommandOpcode_start 24 +#define GEN45_CONSTANT_BUFFER_3DCommandOpcode_start 24 +#define GEN4_CONSTANT_BUFFER_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +CONSTANT_BUFFER_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 24; + case 4: + if (devinfo->is_g4x) { + return 24; + } else { + return 24; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CONSTANT_BUFFER::3D Command Sub Opcode */ + + +#define GEN5_CONSTANT_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN45_CONSTANT_BUFFER_3DCommandSubOpcode_bits 8 +#define GEN4_CONSTANT_BUFFER_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +CONSTANT_BUFFER_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CONSTANT_BUFFER_3DCommandSubOpcode_start 16 +#define GEN45_CONSTANT_BUFFER_3DCommandSubOpcode_start 16 +#define GEN4_CONSTANT_BUFFER_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +CONSTANT_BUFFER_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CONSTANT_BUFFER::Buffer Length */ + + +#define GEN5_CONSTANT_BUFFER_BufferLength_bits 6 +#define GEN45_CONSTANT_BUFFER_BufferLength_bits 6 +#define GEN4_CONSTANT_BUFFER_BufferLength_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +CONSTANT_BUFFER_BufferLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CONSTANT_BUFFER_BufferLength_start 32 +#define GEN45_CONSTANT_BUFFER_BufferLength_start 32 +#define GEN4_CONSTANT_BUFFER_BufferLength_start 32 + +static inline uint32_t ATTRIBUTE_PURE +CONSTANT_BUFFER_BufferLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CONSTANT_BUFFER::Buffer Starting Address */ + + +#define GEN5_CONSTANT_BUFFER_BufferStartingAddress_bits 26 +#define GEN45_CONSTANT_BUFFER_BufferStartingAddress_bits 26 +#define GEN4_CONSTANT_BUFFER_BufferStartingAddress_bits 26 + +static inline uint32_t ATTRIBUTE_PURE +CONSTANT_BUFFER_BufferStartingAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 26; + case 4: + if (devinfo->is_g4x) { + return 26; + } else { + return 26; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CONSTANT_BUFFER_BufferStartingAddress_start 38 +#define GEN45_CONSTANT_BUFFER_BufferStartingAddress_start 38 +#define GEN4_CONSTANT_BUFFER_BufferStartingAddress_start 38 + +static inline uint32_t ATTRIBUTE_PURE +CONSTANT_BUFFER_BufferStartingAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 38; + case 4: + if (devinfo->is_g4x) { + return 38; + } else { + return 38; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CONSTANT_BUFFER::Command SubType */ + + +#define GEN5_CONSTANT_BUFFER_CommandSubType_bits 2 +#define GEN45_CONSTANT_BUFFER_CommandSubType_bits 2 +#define GEN4_CONSTANT_BUFFER_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +CONSTANT_BUFFER_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CONSTANT_BUFFER_CommandSubType_start 27 +#define GEN45_CONSTANT_BUFFER_CommandSubType_start 27 +#define GEN4_CONSTANT_BUFFER_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +CONSTANT_BUFFER_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CONSTANT_BUFFER::Command Type */ + + +#define GEN5_CONSTANT_BUFFER_CommandType_bits 3 +#define GEN45_CONSTANT_BUFFER_CommandType_bits 3 +#define GEN4_CONSTANT_BUFFER_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +CONSTANT_BUFFER_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CONSTANT_BUFFER_CommandType_start 29 +#define GEN45_CONSTANT_BUFFER_CommandType_start 29 +#define GEN4_CONSTANT_BUFFER_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +CONSTANT_BUFFER_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 29; + case 4: + if (devinfo->is_g4x) { + return 29; + } else { + return 29; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CONSTANT_BUFFER::DWord Length */ + + +#define GEN5_CONSTANT_BUFFER_DWordLength_bits 8 +#define GEN45_CONSTANT_BUFFER_DWordLength_bits 8 +#define GEN4_CONSTANT_BUFFER_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +CONSTANT_BUFFER_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CONSTANT_BUFFER_DWordLength_start 0 +#define GEN45_CONSTANT_BUFFER_DWordLength_start 0 +#define GEN4_CONSTANT_BUFFER_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +CONSTANT_BUFFER_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CONSTANT_BUFFER::Valid */ + + +#define GEN5_CONSTANT_BUFFER_Valid_bits 1 +#define GEN45_CONSTANT_BUFFER_Valid_bits 1 +#define GEN4_CONSTANT_BUFFER_Valid_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CONSTANT_BUFFER_Valid_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CONSTANT_BUFFER_Valid_start 8 +#define GEN45_CONSTANT_BUFFER_Valid_start 8 +#define GEN4_CONSTANT_BUFFER_Valid_start 8 + +static inline uint32_t ATTRIBUTE_PURE +CONSTANT_BUFFER_Valid_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CS_CHICKEN1 */ + + +#define GEN11_CS_CHICKEN1_length 1 +#define GEN10_CS_CHICKEN1_length 1 +#define GEN9_CS_CHICKEN1_length 1 + +static inline uint32_t ATTRIBUTE_PURE +CS_CHICKEN1_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CS_CHICKEN1::Replay Mode */ + + +#define GEN11_CS_CHICKEN1_ReplayMode_bits 1 +#define GEN10_CS_CHICKEN1_ReplayMode_bits 1 +#define GEN9_CS_CHICKEN1_ReplayMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CS_CHICKEN1_ReplayMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CS_CHICKEN1_ReplayMode_start 0 +#define GEN10_CS_CHICKEN1_ReplayMode_start 0 +#define GEN9_CS_CHICKEN1_ReplayMode_start 0 + +static inline uint32_t ATTRIBUTE_PURE +CS_CHICKEN1_ReplayMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CS_CHICKEN1::Replay Mode Mask */ + + +#define GEN11_CS_CHICKEN1_ReplayModeMask_bits 1 +#define GEN10_CS_CHICKEN1_ReplayModeMask_bits 1 +#define GEN9_CS_CHICKEN1_ReplayModeMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CS_CHICKEN1_ReplayModeMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CS_CHICKEN1_ReplayModeMask_start 16 +#define GEN10_CS_CHICKEN1_ReplayModeMask_start 16 +#define GEN9_CS_CHICKEN1_ReplayModeMask_start 16 + +static inline uint32_t ATTRIBUTE_PURE +CS_CHICKEN1_ReplayModeMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CS_DEBUG_MODE2 */ + + +#define GEN11_CS_DEBUG_MODE2_length 1 +#define GEN10_CS_DEBUG_MODE2_length 1 +#define GEN9_CS_DEBUG_MODE2_length 1 + +static inline uint32_t ATTRIBUTE_PURE +CS_DEBUG_MODE2_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CS_DEBUG_MODE2::3D Rendering Instruction Disable */ + + +#define GEN11_CS_DEBUG_MODE2_3DRenderingInstructionDisable_bits 1 +#define GEN10_CS_DEBUG_MODE2_3DRenderingInstructionDisable_bits 1 +#define GEN9_CS_DEBUG_MODE2_3DRenderingInstructionDisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CS_DEBUG_MODE2_3DRenderingInstructionDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CS_DEBUG_MODE2_3DRenderingInstructionDisable_start 0 +#define GEN10_CS_DEBUG_MODE2_3DRenderingInstructionDisable_start 0 +#define GEN9_CS_DEBUG_MODE2_3DRenderingInstructionDisable_start 0 + +static inline uint32_t ATTRIBUTE_PURE +CS_DEBUG_MODE2_3DRenderingInstructionDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CS_DEBUG_MODE2::3D Rendering Instruction Disable Mask */ + + +#define GEN11_CS_DEBUG_MODE2_3DRenderingInstructionDisableMask_bits 1 +#define GEN10_CS_DEBUG_MODE2_3DRenderingInstructionDisableMask_bits 1 +#define GEN9_CS_DEBUG_MODE2_3DRenderingInstructionDisableMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CS_DEBUG_MODE2_3DRenderingInstructionDisableMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CS_DEBUG_MODE2_3DRenderingInstructionDisableMask_start 16 +#define GEN10_CS_DEBUG_MODE2_3DRenderingInstructionDisableMask_start 16 +#define GEN9_CS_DEBUG_MODE2_3DRenderingInstructionDisableMask_start 16 + +static inline uint32_t ATTRIBUTE_PURE +CS_DEBUG_MODE2_3DRenderingInstructionDisableMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CS_DEBUG_MODE2::CONSTANT_BUFFER Address Offset Disable */ + + +#define GEN11_CS_DEBUG_MODE2_CONSTANT_BUFFERAddressOffsetDisable_bits 1 +#define GEN10_CS_DEBUG_MODE2_CONSTANT_BUFFERAddressOffsetDisable_bits 1 +#define GEN9_CS_DEBUG_MODE2_CONSTANT_BUFFERAddressOffsetDisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CS_DEBUG_MODE2_CONSTANT_BUFFERAddressOffsetDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CS_DEBUG_MODE2_CONSTANT_BUFFERAddressOffsetDisable_start 4 +#define GEN10_CS_DEBUG_MODE2_CONSTANT_BUFFERAddressOffsetDisable_start 4 +#define GEN9_CS_DEBUG_MODE2_CONSTANT_BUFFERAddressOffsetDisable_start 4 + +static inline uint32_t ATTRIBUTE_PURE +CS_DEBUG_MODE2_CONSTANT_BUFFERAddressOffsetDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CS_DEBUG_MODE2::CONSTANT_BUFFER Address Offset Disable Mask */ + + +#define GEN11_CS_DEBUG_MODE2_CONSTANT_BUFFERAddressOffsetDisableMask_bits 1 +#define GEN10_CS_DEBUG_MODE2_CONSTANT_BUFFERAddressOffsetDisableMask_bits 1 +#define GEN9_CS_DEBUG_MODE2_CONSTANT_BUFFERAddressOffsetDisableMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CS_DEBUG_MODE2_CONSTANT_BUFFERAddressOffsetDisableMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CS_DEBUG_MODE2_CONSTANT_BUFFERAddressOffsetDisableMask_start 20 +#define GEN10_CS_DEBUG_MODE2_CONSTANT_BUFFERAddressOffsetDisableMask_start 20 +#define GEN9_CS_DEBUG_MODE2_CONSTANT_BUFFERAddressOffsetDisableMask_start 20 + +static inline uint32_t ATTRIBUTE_PURE +CS_DEBUG_MODE2_CONSTANT_BUFFERAddressOffsetDisableMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 20; + case 10: return 20; + case 9: return 20; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CS_DEBUG_MODE2::Media Instruction Disable */ + + +#define GEN11_CS_DEBUG_MODE2_MediaInstructionDisable_bits 1 +#define GEN10_CS_DEBUG_MODE2_MediaInstructionDisable_bits 1 +#define GEN9_CS_DEBUG_MODE2_MediaInstructionDisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CS_DEBUG_MODE2_MediaInstructionDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CS_DEBUG_MODE2_MediaInstructionDisable_start 1 +#define GEN10_CS_DEBUG_MODE2_MediaInstructionDisable_start 1 +#define GEN9_CS_DEBUG_MODE2_MediaInstructionDisable_start 1 + +static inline uint32_t ATTRIBUTE_PURE +CS_DEBUG_MODE2_MediaInstructionDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CS_DEBUG_MODE2::Media Instruction Disable Mask */ + + +#define GEN11_CS_DEBUG_MODE2_MediaInstructionDisableMask_bits 1 +#define GEN10_CS_DEBUG_MODE2_MediaInstructionDisableMask_bits 1 +#define GEN9_CS_DEBUG_MODE2_MediaInstructionDisableMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +CS_DEBUG_MODE2_MediaInstructionDisableMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CS_DEBUG_MODE2_MediaInstructionDisableMask_start 17 +#define GEN10_CS_DEBUG_MODE2_MediaInstructionDisableMask_start 17 +#define GEN9_CS_DEBUG_MODE2_MediaInstructionDisableMask_start 17 + +static inline uint32_t ATTRIBUTE_PURE +CS_DEBUG_MODE2_MediaInstructionDisableMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 17; + case 10: return 17; + case 9: return 17; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CS_INVOCATION_COUNT */ + + +#define GEN11_CS_INVOCATION_COUNT_length 2 +#define GEN10_CS_INVOCATION_COUNT_length 2 +#define GEN9_CS_INVOCATION_COUNT_length 2 +#define GEN8_CS_INVOCATION_COUNT_length 2 +#define GEN75_CS_INVOCATION_COUNT_length 2 +#define GEN7_CS_INVOCATION_COUNT_length 2 + +static inline uint32_t ATTRIBUTE_PURE +CS_INVOCATION_COUNT_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CS_INVOCATION_COUNT::CS Invocation Count Report */ + + +#define GEN11_CS_INVOCATION_COUNT_CSInvocationCountReport_bits 64 +#define GEN10_CS_INVOCATION_COUNT_CSInvocationCountReport_bits 64 +#define GEN9_CS_INVOCATION_COUNT_CSInvocationCountReport_bits 64 +#define GEN8_CS_INVOCATION_COUNT_CSInvocationCountReport_bits 64 +#define GEN75_CS_INVOCATION_COUNT_CSInvocationCountReport_bits 64 +#define GEN7_CS_INVOCATION_COUNT_CSInvocationCountReport_bits 64 + +static inline uint32_t ATTRIBUTE_PURE +CS_INVOCATION_COUNT_CSInvocationCountReport_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_CS_INVOCATION_COUNT_CSInvocationCountReport_start 0 +#define GEN10_CS_INVOCATION_COUNT_CSInvocationCountReport_start 0 +#define GEN9_CS_INVOCATION_COUNT_CSInvocationCountReport_start 0 +#define GEN8_CS_INVOCATION_COUNT_CSInvocationCountReport_start 0 +#define GEN75_CS_INVOCATION_COUNT_CSInvocationCountReport_start 0 +#define GEN7_CS_INVOCATION_COUNT_CSInvocationCountReport_start 0 + +static inline uint32_t ATTRIBUTE_PURE +CS_INVOCATION_COUNT_CSInvocationCountReport_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CS_URB_STATE */ + + +#define GEN5_CS_URB_STATE_length 2 +#define GEN45_CS_URB_STATE_length 2 +#define GEN4_CS_URB_STATE_length 2 + +static inline uint32_t ATTRIBUTE_PURE +CS_URB_STATE_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CS_URB_STATE::3D Command Opcode */ + + +#define GEN5_CS_URB_STATE_3DCommandOpcode_bits 3 +#define GEN45_CS_URB_STATE_3DCommandOpcode_bits 3 +#define GEN4_CS_URB_STATE_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +CS_URB_STATE_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CS_URB_STATE_3DCommandOpcode_start 24 +#define GEN45_CS_URB_STATE_3DCommandOpcode_start 24 +#define GEN4_CS_URB_STATE_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +CS_URB_STATE_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 24; + case 4: + if (devinfo->is_g4x) { + return 24; + } else { + return 24; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CS_URB_STATE::3D Command Sub Opcode */ + + +#define GEN5_CS_URB_STATE_3DCommandSubOpcode_bits 8 +#define GEN45_CS_URB_STATE_3DCommandSubOpcode_bits 8 +#define GEN4_CS_URB_STATE_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +CS_URB_STATE_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CS_URB_STATE_3DCommandSubOpcode_start 16 +#define GEN45_CS_URB_STATE_3DCommandSubOpcode_start 16 +#define GEN4_CS_URB_STATE_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +CS_URB_STATE_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CS_URB_STATE::Command SubType */ + + +#define GEN5_CS_URB_STATE_CommandSubType_bits 2 +#define GEN45_CS_URB_STATE_CommandSubType_bits 2 +#define GEN4_CS_URB_STATE_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +CS_URB_STATE_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CS_URB_STATE_CommandSubType_start 27 +#define GEN45_CS_URB_STATE_CommandSubType_start 27 +#define GEN4_CS_URB_STATE_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +CS_URB_STATE_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CS_URB_STATE::Command Type */ + + +#define GEN5_CS_URB_STATE_CommandType_bits 3 +#define GEN45_CS_URB_STATE_CommandType_bits 3 +#define GEN4_CS_URB_STATE_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +CS_URB_STATE_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CS_URB_STATE_CommandType_start 29 +#define GEN45_CS_URB_STATE_CommandType_start 29 +#define GEN4_CS_URB_STATE_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +CS_URB_STATE_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 29; + case 4: + if (devinfo->is_g4x) { + return 29; + } else { + return 29; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CS_URB_STATE::DWord Length */ + + +#define GEN5_CS_URB_STATE_DWordLength_bits 8 +#define GEN45_CS_URB_STATE_DWordLength_bits 8 +#define GEN4_CS_URB_STATE_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +CS_URB_STATE_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CS_URB_STATE_DWordLength_start 0 +#define GEN45_CS_URB_STATE_DWordLength_start 0 +#define GEN4_CS_URB_STATE_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +CS_URB_STATE_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CS_URB_STATE::Number of URB Entries */ + + +#define GEN5_CS_URB_STATE_NumberofURBEntries_bits 3 +#define GEN45_CS_URB_STATE_NumberofURBEntries_bits 3 +#define GEN4_CS_URB_STATE_NumberofURBEntries_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +CS_URB_STATE_NumberofURBEntries_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CS_URB_STATE_NumberofURBEntries_start 32 +#define GEN45_CS_URB_STATE_NumberofURBEntries_start 32 +#define GEN4_CS_URB_STATE_NumberofURBEntries_start 32 + +static inline uint32_t ATTRIBUTE_PURE +CS_URB_STATE_NumberofURBEntries_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* CS_URB_STATE::URB Entry Allocation Size */ + + +#define GEN5_CS_URB_STATE_URBEntryAllocationSize_bits 5 +#define GEN45_CS_URB_STATE_URBEntryAllocationSize_bits 5 +#define GEN4_CS_URB_STATE_URBEntryAllocationSize_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +CS_URB_STATE_URBEntryAllocationSize_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 5; + case 4: + if (devinfo->is_g4x) { + return 5; + } else { + return 5; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_CS_URB_STATE_URBEntryAllocationSize_start 36 +#define GEN45_CS_URB_STATE_URBEntryAllocationSize_start 36 +#define GEN4_CS_URB_STATE_URBEntryAllocationSize_start 36 + +static inline uint32_t ATTRIBUTE_PURE +CS_URB_STATE_URBEntryAllocationSize_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 36; + case 4: + if (devinfo->is_g4x) { + return 36; + } else { + return 36; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* DEPTH_STENCIL_STATE */ + + +#define GEN75_DEPTH_STENCIL_STATE_length 3 +#define GEN7_DEPTH_STENCIL_STATE_length 3 +#define GEN6_DEPTH_STENCIL_STATE_length 3 + +static inline uint32_t ATTRIBUTE_PURE +DEPTH_STENCIL_STATE_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* DEPTH_STENCIL_STATE::Backface Stencil Fail Op */ + + +#define GEN75_DEPTH_STENCIL_STATE_BackfaceStencilFailOp_bits 3 +#define GEN7_DEPTH_STENCIL_STATE_BackfaceStencilFailOp_bits 3 +#define GEN6_DEPTH_STENCIL_STATE_BackfaceStencilFailOp_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +DEPTH_STENCIL_STATE_BackfaceStencilFailOp_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_DEPTH_STENCIL_STATE_BackfaceStencilFailOp_start 9 +#define GEN7_DEPTH_STENCIL_STATE_BackfaceStencilFailOp_start 9 +#define GEN6_DEPTH_STENCIL_STATE_BackfaceStencilFailOp_start 9 + +static inline uint32_t ATTRIBUTE_PURE +DEPTH_STENCIL_STATE_BackfaceStencilFailOp_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 9; + } + case 6: return 9; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* DEPTH_STENCIL_STATE::Backface Stencil Pass Depth Fail Op */ + + +#define GEN75_DEPTH_STENCIL_STATE_BackfaceStencilPassDepthFailOp_bits 3 +#define GEN7_DEPTH_STENCIL_STATE_BackfaceStencilPassDepthFailOp_bits 3 +#define GEN6_DEPTH_STENCIL_STATE_BackfaceStencilPassDepthFailOp_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +DEPTH_STENCIL_STATE_BackfaceStencilPassDepthFailOp_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_DEPTH_STENCIL_STATE_BackfaceStencilPassDepthFailOp_start 6 +#define GEN7_DEPTH_STENCIL_STATE_BackfaceStencilPassDepthFailOp_start 6 +#define GEN6_DEPTH_STENCIL_STATE_BackfaceStencilPassDepthFailOp_start 6 + +static inline uint32_t ATTRIBUTE_PURE +DEPTH_STENCIL_STATE_BackfaceStencilPassDepthFailOp_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 6; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* DEPTH_STENCIL_STATE::Backface Stencil Pass Depth Pass Op */ + + +#define GEN75_DEPTH_STENCIL_STATE_BackfaceStencilPassDepthPassOp_bits 3 +#define GEN7_DEPTH_STENCIL_STATE_BackfaceStencilPassDepthPassOp_bits 3 +#define GEN6_DEPTH_STENCIL_STATE_BackfaceStencilPassDepthPassOp_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +DEPTH_STENCIL_STATE_BackfaceStencilPassDepthPassOp_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_DEPTH_STENCIL_STATE_BackfaceStencilPassDepthPassOp_start 3 +#define GEN7_DEPTH_STENCIL_STATE_BackfaceStencilPassDepthPassOp_start 3 +#define GEN6_DEPTH_STENCIL_STATE_BackfaceStencilPassDepthPassOp_start 3 + +static inline uint32_t ATTRIBUTE_PURE +DEPTH_STENCIL_STATE_BackfaceStencilPassDepthPassOp_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* DEPTH_STENCIL_STATE::Backface Stencil Test Function */ + + +#define GEN75_DEPTH_STENCIL_STATE_BackfaceStencilTestFunction_bits 3 +#define GEN7_DEPTH_STENCIL_STATE_BackfaceStencilTestFunction_bits 3 +#define GEN6_DEPTH_STENCIL_STATE_BackfaceStencilTestFunction_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +DEPTH_STENCIL_STATE_BackfaceStencilTestFunction_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_DEPTH_STENCIL_STATE_BackfaceStencilTestFunction_start 12 +#define GEN7_DEPTH_STENCIL_STATE_BackfaceStencilTestFunction_start 12 +#define GEN6_DEPTH_STENCIL_STATE_BackfaceStencilTestFunction_start 12 + +static inline uint32_t ATTRIBUTE_PURE +DEPTH_STENCIL_STATE_BackfaceStencilTestFunction_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 12; + } else { + return 12; + } + case 6: return 12; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* DEPTH_STENCIL_STATE::Backface Stencil Test Mask */ + + +#define GEN75_DEPTH_STENCIL_STATE_BackfaceStencilTestMask_bits 8 +#define GEN7_DEPTH_STENCIL_STATE_BackfaceStencilTestMask_bits 8 +#define GEN6_DEPTH_STENCIL_STATE_BackfaceStencilTestMask_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +DEPTH_STENCIL_STATE_BackfaceStencilTestMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_DEPTH_STENCIL_STATE_BackfaceStencilTestMask_start 40 +#define GEN7_DEPTH_STENCIL_STATE_BackfaceStencilTestMask_start 40 +#define GEN6_DEPTH_STENCIL_STATE_BackfaceStencilTestMask_start 40 + +static inline uint32_t ATTRIBUTE_PURE +DEPTH_STENCIL_STATE_BackfaceStencilTestMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 40; + } else { + return 40; + } + case 6: return 40; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* DEPTH_STENCIL_STATE::Backface Stencil Write Mask */ + + +#define GEN75_DEPTH_STENCIL_STATE_BackfaceStencilWriteMask_bits 8 +#define GEN7_DEPTH_STENCIL_STATE_BackfaceStencilWriteMask_bits 8 +#define GEN6_DEPTH_STENCIL_STATE_BackfaceStencilWriteMask_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +DEPTH_STENCIL_STATE_BackfaceStencilWriteMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_DEPTH_STENCIL_STATE_BackfaceStencilWriteMask_start 32 +#define GEN7_DEPTH_STENCIL_STATE_BackfaceStencilWriteMask_start 32 +#define GEN6_DEPTH_STENCIL_STATE_BackfaceStencilWriteMask_start 32 + +static inline uint32_t ATTRIBUTE_PURE +DEPTH_STENCIL_STATE_BackfaceStencilWriteMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* DEPTH_STENCIL_STATE::Depth Buffer Write Enable */ + + +#define GEN75_DEPTH_STENCIL_STATE_DepthBufferWriteEnable_bits 1 +#define GEN7_DEPTH_STENCIL_STATE_DepthBufferWriteEnable_bits 1 +#define GEN6_DEPTH_STENCIL_STATE_DepthBufferWriteEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +DEPTH_STENCIL_STATE_DepthBufferWriteEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_DEPTH_STENCIL_STATE_DepthBufferWriteEnable_start 90 +#define GEN7_DEPTH_STENCIL_STATE_DepthBufferWriteEnable_start 90 +#define GEN6_DEPTH_STENCIL_STATE_DepthBufferWriteEnable_start 90 + +static inline uint32_t ATTRIBUTE_PURE +DEPTH_STENCIL_STATE_DepthBufferWriteEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 90; + } else { + return 90; + } + case 6: return 90; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* DEPTH_STENCIL_STATE::Depth Test Enable */ + + +#define GEN75_DEPTH_STENCIL_STATE_DepthTestEnable_bits 1 +#define GEN7_DEPTH_STENCIL_STATE_DepthTestEnable_bits 1 +#define GEN6_DEPTH_STENCIL_STATE_DepthTestEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +DEPTH_STENCIL_STATE_DepthTestEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_DEPTH_STENCIL_STATE_DepthTestEnable_start 95 +#define GEN7_DEPTH_STENCIL_STATE_DepthTestEnable_start 95 +#define GEN6_DEPTH_STENCIL_STATE_DepthTestEnable_start 95 + +static inline uint32_t ATTRIBUTE_PURE +DEPTH_STENCIL_STATE_DepthTestEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 95; + } else { + return 95; + } + case 6: return 95; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* DEPTH_STENCIL_STATE::Depth Test Function */ + + +#define GEN75_DEPTH_STENCIL_STATE_DepthTestFunction_bits 3 +#define GEN7_DEPTH_STENCIL_STATE_DepthTestFunction_bits 3 +#define GEN6_DEPTH_STENCIL_STATE_DepthTestFunction_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +DEPTH_STENCIL_STATE_DepthTestFunction_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_DEPTH_STENCIL_STATE_DepthTestFunction_start 91 +#define GEN7_DEPTH_STENCIL_STATE_DepthTestFunction_start 91 +#define GEN6_DEPTH_STENCIL_STATE_DepthTestFunction_start 91 + +static inline uint32_t ATTRIBUTE_PURE +DEPTH_STENCIL_STATE_DepthTestFunction_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 91; + } else { + return 91; + } + case 6: return 91; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* DEPTH_STENCIL_STATE::Double Sided Stencil Enable */ + + +#define GEN75_DEPTH_STENCIL_STATE_DoubleSidedStencilEnable_bits 1 +#define GEN7_DEPTH_STENCIL_STATE_DoubleSidedStencilEnable_bits 1 +#define GEN6_DEPTH_STENCIL_STATE_DoubleSidedStencilEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +DEPTH_STENCIL_STATE_DoubleSidedStencilEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_DEPTH_STENCIL_STATE_DoubleSidedStencilEnable_start 15 +#define GEN7_DEPTH_STENCIL_STATE_DoubleSidedStencilEnable_start 15 +#define GEN6_DEPTH_STENCIL_STATE_DoubleSidedStencilEnable_start 15 + +static inline uint32_t ATTRIBUTE_PURE +DEPTH_STENCIL_STATE_DoubleSidedStencilEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 15; + } else { + return 15; + } + case 6: return 15; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* DEPTH_STENCIL_STATE::Stencil Buffer Write Enable */ + + +#define GEN75_DEPTH_STENCIL_STATE_StencilBufferWriteEnable_bits 1 +#define GEN7_DEPTH_STENCIL_STATE_StencilBufferWriteEnable_bits 1 +#define GEN6_DEPTH_STENCIL_STATE_StencilBufferWriteEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +DEPTH_STENCIL_STATE_StencilBufferWriteEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_DEPTH_STENCIL_STATE_StencilBufferWriteEnable_start 18 +#define GEN7_DEPTH_STENCIL_STATE_StencilBufferWriteEnable_start 18 +#define GEN6_DEPTH_STENCIL_STATE_StencilBufferWriteEnable_start 18 + +static inline uint32_t ATTRIBUTE_PURE +DEPTH_STENCIL_STATE_StencilBufferWriteEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 18; + } else { + return 18; + } + case 6: return 18; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* DEPTH_STENCIL_STATE::Stencil Fail Op */ + + +#define GEN75_DEPTH_STENCIL_STATE_StencilFailOp_bits 3 +#define GEN7_DEPTH_STENCIL_STATE_StencilFailOp_bits 3 +#define GEN6_DEPTH_STENCIL_STATE_StencilFailOp_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +DEPTH_STENCIL_STATE_StencilFailOp_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_DEPTH_STENCIL_STATE_StencilFailOp_start 25 +#define GEN7_DEPTH_STENCIL_STATE_StencilFailOp_start 25 +#define GEN6_DEPTH_STENCIL_STATE_StencilFailOp_start 25 + +static inline uint32_t ATTRIBUTE_PURE +DEPTH_STENCIL_STATE_StencilFailOp_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 25; + } else { + return 25; + } + case 6: return 25; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* DEPTH_STENCIL_STATE::Stencil Pass Depth Fail Op */ + + +#define GEN75_DEPTH_STENCIL_STATE_StencilPassDepthFailOp_bits 3 +#define GEN7_DEPTH_STENCIL_STATE_StencilPassDepthFailOp_bits 3 +#define GEN6_DEPTH_STENCIL_STATE_StencilPassDepthFailOp_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +DEPTH_STENCIL_STATE_StencilPassDepthFailOp_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_DEPTH_STENCIL_STATE_StencilPassDepthFailOp_start 22 +#define GEN7_DEPTH_STENCIL_STATE_StencilPassDepthFailOp_start 22 +#define GEN6_DEPTH_STENCIL_STATE_StencilPassDepthFailOp_start 22 + +static inline uint32_t ATTRIBUTE_PURE +DEPTH_STENCIL_STATE_StencilPassDepthFailOp_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 22; + } else { + return 22; + } + case 6: return 22; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* DEPTH_STENCIL_STATE::Stencil Pass Depth Pass Op */ + + +#define GEN75_DEPTH_STENCIL_STATE_StencilPassDepthPassOp_bits 3 +#define GEN7_DEPTH_STENCIL_STATE_StencilPassDepthPassOp_bits 3 +#define GEN6_DEPTH_STENCIL_STATE_StencilPassDepthPassOp_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +DEPTH_STENCIL_STATE_StencilPassDepthPassOp_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_DEPTH_STENCIL_STATE_StencilPassDepthPassOp_start 19 +#define GEN7_DEPTH_STENCIL_STATE_StencilPassDepthPassOp_start 19 +#define GEN6_DEPTH_STENCIL_STATE_StencilPassDepthPassOp_start 19 + +static inline uint32_t ATTRIBUTE_PURE +DEPTH_STENCIL_STATE_StencilPassDepthPassOp_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 19; + } else { + return 19; + } + case 6: return 19; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* DEPTH_STENCIL_STATE::Stencil Test Enable */ + + +#define GEN75_DEPTH_STENCIL_STATE_StencilTestEnable_bits 1 +#define GEN7_DEPTH_STENCIL_STATE_StencilTestEnable_bits 1 +#define GEN6_DEPTH_STENCIL_STATE_StencilTestEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +DEPTH_STENCIL_STATE_StencilTestEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_DEPTH_STENCIL_STATE_StencilTestEnable_start 31 +#define GEN7_DEPTH_STENCIL_STATE_StencilTestEnable_start 31 +#define GEN6_DEPTH_STENCIL_STATE_StencilTestEnable_start 31 + +static inline uint32_t ATTRIBUTE_PURE +DEPTH_STENCIL_STATE_StencilTestEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 31; + } else { + return 31; + } + case 6: return 31; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* DEPTH_STENCIL_STATE::Stencil Test Function */ + + +#define GEN75_DEPTH_STENCIL_STATE_StencilTestFunction_bits 3 +#define GEN7_DEPTH_STENCIL_STATE_StencilTestFunction_bits 3 +#define GEN6_DEPTH_STENCIL_STATE_StencilTestFunction_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +DEPTH_STENCIL_STATE_StencilTestFunction_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_DEPTH_STENCIL_STATE_StencilTestFunction_start 28 +#define GEN7_DEPTH_STENCIL_STATE_StencilTestFunction_start 28 +#define GEN6_DEPTH_STENCIL_STATE_StencilTestFunction_start 28 + +static inline uint32_t ATTRIBUTE_PURE +DEPTH_STENCIL_STATE_StencilTestFunction_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 28; + } else { + return 28; + } + case 6: return 28; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* DEPTH_STENCIL_STATE::Stencil Test Mask */ + + +#define GEN75_DEPTH_STENCIL_STATE_StencilTestMask_bits 8 +#define GEN7_DEPTH_STENCIL_STATE_StencilTestMask_bits 8 +#define GEN6_DEPTH_STENCIL_STATE_StencilTestMask_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +DEPTH_STENCIL_STATE_StencilTestMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_DEPTH_STENCIL_STATE_StencilTestMask_start 56 +#define GEN7_DEPTH_STENCIL_STATE_StencilTestMask_start 56 +#define GEN6_DEPTH_STENCIL_STATE_StencilTestMask_start 56 + +static inline uint32_t ATTRIBUTE_PURE +DEPTH_STENCIL_STATE_StencilTestMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 56; + } else { + return 56; + } + case 6: return 56; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* DEPTH_STENCIL_STATE::Stencil Write Mask */ + + +#define GEN75_DEPTH_STENCIL_STATE_StencilWriteMask_bits 8 +#define GEN7_DEPTH_STENCIL_STATE_StencilWriteMask_bits 8 +#define GEN6_DEPTH_STENCIL_STATE_StencilWriteMask_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +DEPTH_STENCIL_STATE_StencilWriteMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_DEPTH_STENCIL_STATE_StencilWriteMask_start 48 +#define GEN7_DEPTH_STENCIL_STATE_StencilWriteMask_start 48 +#define GEN6_DEPTH_STENCIL_STATE_StencilWriteMask_start 48 + +static inline uint32_t ATTRIBUTE_PURE +DEPTH_STENCIL_STATE_StencilWriteMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 48; + } else { + return 48; + } + case 6: return 48; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* DS_INVOCATION_COUNT */ + + +#define GEN11_DS_INVOCATION_COUNT_length 2 +#define GEN10_DS_INVOCATION_COUNT_length 2 +#define GEN9_DS_INVOCATION_COUNT_length 2 +#define GEN8_DS_INVOCATION_COUNT_length 2 +#define GEN75_DS_INVOCATION_COUNT_length 2 +#define GEN7_DS_INVOCATION_COUNT_length 2 + +static inline uint32_t ATTRIBUTE_PURE +DS_INVOCATION_COUNT_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* DS_INVOCATION_COUNT::DS Invocation Count Report */ + + +#define GEN11_DS_INVOCATION_COUNT_DSInvocationCountReport_bits 64 +#define GEN10_DS_INVOCATION_COUNT_DSInvocationCountReport_bits 64 +#define GEN9_DS_INVOCATION_COUNT_DSInvocationCountReport_bits 64 +#define GEN8_DS_INVOCATION_COUNT_DSInvocationCountReport_bits 64 +#define GEN75_DS_INVOCATION_COUNT_DSInvocationCountReport_bits 64 +#define GEN7_DS_INVOCATION_COUNT_DSInvocationCountReport_bits 64 + +static inline uint32_t ATTRIBUTE_PURE +DS_INVOCATION_COUNT_DSInvocationCountReport_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_DS_INVOCATION_COUNT_DSInvocationCountReport_start 0 +#define GEN10_DS_INVOCATION_COUNT_DSInvocationCountReport_start 0 +#define GEN9_DS_INVOCATION_COUNT_DSInvocationCountReport_start 0 +#define GEN8_DS_INVOCATION_COUNT_DSInvocationCountReport_start 0 +#define GEN75_DS_INVOCATION_COUNT_DSInvocationCountReport_start 0 +#define GEN7_DS_INVOCATION_COUNT_DSInvocationCountReport_start 0 + +static inline uint32_t ATTRIBUTE_PURE +DS_INVOCATION_COUNT_DSInvocationCountReport_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* ERR_INT */ + + +#define GEN75_ERR_INT_length 1 +#define GEN7_ERR_INT_length 1 + +static inline uint32_t ATTRIBUTE_PURE +ERR_INT_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* ERR_INT::Cursor A GTT Fault Status */ + + +#define GEN75_ERR_INT_CursorAGTTFaultStatus_bits 1 +#define GEN7_ERR_INT_CursorAGTTFaultStatus_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +ERR_INT_CursorAGTTFaultStatus_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_ERR_INT_CursorAGTTFaultStatus_start 4 +#define GEN7_ERR_INT_CursorAGTTFaultStatus_start 4 + +static inline uint32_t ATTRIBUTE_PURE +ERR_INT_CursorAGTTFaultStatus_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* ERR_INT::Cursor B GTT Fault Status */ + + +#define GEN75_ERR_INT_CursorBGTTFaultStatus_bits 1 +#define GEN7_ERR_INT_CursorBGTTFaultStatus_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +ERR_INT_CursorBGTTFaultStatus_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_ERR_INT_CursorBGTTFaultStatus_start 5 +#define GEN7_ERR_INT_CursorBGTTFaultStatus_start 5 + +static inline uint32_t ATTRIBUTE_PURE +ERR_INT_CursorBGTTFaultStatus_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 5; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* ERR_INT::Invalid GTT page table entry */ + + +#define GEN75_ERR_INT_InvalidGTTpagetableentry_bits 1 +#define GEN7_ERR_INT_InvalidGTTpagetableentry_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +ERR_INT_InvalidGTTpagetableentry_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_ERR_INT_InvalidGTTpagetableentry_start 7 +#define GEN7_ERR_INT_InvalidGTTpagetableentry_start 7 + +static inline uint32_t ATTRIBUTE_PURE +ERR_INT_InvalidGTTpagetableentry_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 7; + } else { + return 7; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* ERR_INT::Invalid page table entry data */ + + +#define GEN75_ERR_INT_Invalidpagetableentrydata_bits 1 +#define GEN7_ERR_INT_Invalidpagetableentrydata_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +ERR_INT_Invalidpagetableentrydata_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_ERR_INT_Invalidpagetableentrydata_start 6 +#define GEN7_ERR_INT_Invalidpagetableentrydata_start 6 + +static inline uint32_t ATTRIBUTE_PURE +ERR_INT_Invalidpagetableentrydata_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* ERR_INT::Primary A GTT Fault Status */ + + +#define GEN75_ERR_INT_PrimaryAGTTFaultStatus_bits 1 +#define GEN7_ERR_INT_PrimaryAGTTFaultStatus_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +ERR_INT_PrimaryAGTTFaultStatus_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_ERR_INT_PrimaryAGTTFaultStatus_start 0 +#define GEN7_ERR_INT_PrimaryAGTTFaultStatus_start 0 + +static inline uint32_t ATTRIBUTE_PURE +ERR_INT_PrimaryAGTTFaultStatus_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* ERR_INT::Primary B GTT Fault Status */ + + +#define GEN75_ERR_INT_PrimaryBGTTFaultStatus_bits 1 +#define GEN7_ERR_INT_PrimaryBGTTFaultStatus_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +ERR_INT_PrimaryBGTTFaultStatus_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_ERR_INT_PrimaryBGTTFaultStatus_start 1 +#define GEN7_ERR_INT_PrimaryBGTTFaultStatus_start 1 + +static inline uint32_t ATTRIBUTE_PURE +ERR_INT_PrimaryBGTTFaultStatus_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* ERR_INT::Sprite A GTT Fault Status */ + + +#define GEN75_ERR_INT_SpriteAGTTFaultStatus_bits 1 +#define GEN7_ERR_INT_SpriteAGTTFaultStatus_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +ERR_INT_SpriteAGTTFaultStatus_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_ERR_INT_SpriteAGTTFaultStatus_start 2 +#define GEN7_ERR_INT_SpriteAGTTFaultStatus_start 2 + +static inline uint32_t ATTRIBUTE_PURE +ERR_INT_SpriteAGTTFaultStatus_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* ERR_INT::Sprite B GTT Fault Status */ + + +#define GEN75_ERR_INT_SpriteBGTTFaultStatus_bits 1 +#define GEN7_ERR_INT_SpriteBGTTFaultStatus_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +ERR_INT_SpriteBGTTFaultStatus_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_ERR_INT_SpriteBGTTFaultStatus_start 3 +#define GEN7_ERR_INT_SpriteBGTTFaultStatus_start 3 + +static inline uint32_t ATTRIBUTE_PURE +ERR_INT_SpriteBGTTFaultStatus_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR */ + + +#define GEN11_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_length 1 +#define GEN10_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_length 1 +#define GEN9_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_length 1 + +static inline uint32_t ATTRIBUTE_PURE +EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR::End Of Thread */ + + +#define GEN11_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_EndOfThread_bits 1 +#define GEN10_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_EndOfThread_bits 1 +#define GEN9_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_EndOfThread_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_EndOfThread_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_EndOfThread_start 5 +#define GEN10_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_EndOfThread_start 5 +#define GEN9_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_EndOfThread_start 5 + +static inline uint32_t ATTRIBUTE_PURE +EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_EndOfThread_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR::Extended Message Length */ + + +#define GEN11_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_ExtendedMessageLength_bits 4 +#define GEN10_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_ExtendedMessageLength_bits 4 +#define GEN9_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_ExtendedMessageLength_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_ExtendedMessageLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_ExtendedMessageLength_start 6 +#define GEN10_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_ExtendedMessageLength_start 6 +#define GEN9_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_ExtendedMessageLength_start 6 + +static inline uint32_t ATTRIBUTE_PURE +EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_ExtendedMessageLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR::Target Function ID */ + + +#define GEN11_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_TargetFunctionID_bits 4 +#define GEN10_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_TargetFunctionID_bits 4 +#define GEN9_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_TargetFunctionID_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_TargetFunctionID_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_TargetFunctionID_start 0 +#define GEN10_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_TargetFunctionID_start 0 +#define GEN9_EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_TargetFunctionID_start 0 + +static inline uint32_t ATTRIBUTE_PURE +EXECUTION_UNIT_EXTENDED_MESSAGE_DESCRIPTOR_TargetFunctionID_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* FAULT_REG */ + + +#define GEN9_FAULT_REG_length 1 +#define GEN8_FAULT_REG_length 1 + +static inline uint32_t ATTRIBUTE_PURE +FAULT_REG_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* FAULT_REG::Engine ID */ + + +#define GEN9_FAULT_REG_EngineID_bits 3 +#define GEN8_FAULT_REG_EngineID_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +FAULT_REG_EngineID_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_FAULT_REG_EngineID_start 12 +#define GEN8_FAULT_REG_EngineID_start 12 + +static inline uint32_t ATTRIBUTE_PURE +FAULT_REG_EngineID_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 12; + case 8: return 12; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* FAULT_REG::Fault Type */ + + +#define GEN9_FAULT_REG_FaultType_bits 2 +#define GEN8_FAULT_REG_FaultType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +FAULT_REG_FaultType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_FAULT_REG_FaultType_start 1 +#define GEN8_FAULT_REG_FaultType_start 1 + +static inline uint32_t ATTRIBUTE_PURE +FAULT_REG_FaultType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* FAULT_REG::GTTSEL */ + + +#define GEN9_FAULT_REG_GTTSEL_bits 1 +#define GEN8_FAULT_REG_GTTSEL_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +FAULT_REG_GTTSEL_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_FAULT_REG_GTTSEL_start 11 +#define GEN8_FAULT_REG_GTTSEL_start 11 + +static inline uint32_t ATTRIBUTE_PURE +FAULT_REG_GTTSEL_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 11; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* FAULT_REG::SRCID of Fault */ + + +#define GEN9_FAULT_REG_SRCIDofFault_bits 8 +#define GEN8_FAULT_REG_SRCIDofFault_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +FAULT_REG_SRCIDofFault_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_FAULT_REG_SRCIDofFault_start 3 +#define GEN8_FAULT_REG_SRCIDofFault_start 3 + +static inline uint32_t ATTRIBUTE_PURE +FAULT_REG_SRCIDofFault_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* FAULT_REG::Valid Bit */ + + +#define GEN9_FAULT_REG_ValidBit_bits 1 +#define GEN8_FAULT_REG_ValidBit_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +FAULT_REG_ValidBit_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_FAULT_REG_ValidBit_start 0 +#define GEN8_FAULT_REG_ValidBit_start 0 + +static inline uint32_t ATTRIBUTE_PURE +FAULT_REG_ValidBit_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* FILTER_COEFFICIENT */ + + +#define GEN11_FILTER_COEFFICIENT_length 1 +#define GEN10_FILTER_COEFFICIENT_length 1 +#define GEN9_FILTER_COEFFICIENT_length 1 +#define GEN8_FILTER_COEFFICIENT_length 1 + +static inline uint32_t ATTRIBUTE_PURE +FILTER_COEFFICIENT_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* FILTER_COEFFICIENT::Filter Coefficient */ + + +#define GEN11_FILTER_COEFFICIENT_FilterCoefficient_bits 8 +#define GEN10_FILTER_COEFFICIENT_FilterCoefficient_bits 8 +#define GEN9_FILTER_COEFFICIENT_FilterCoefficient_bits 8 +#define GEN8_FILTER_COEFFICIENT_FilterCoefficient_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +FILTER_COEFFICIENT_FilterCoefficient_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_FILTER_COEFFICIENT_FilterCoefficient_start 0 +#define GEN10_FILTER_COEFFICIENT_FilterCoefficient_start 0 +#define GEN9_FILTER_COEFFICIENT_FilterCoefficient_start 0 +#define GEN8_FILTER_COEFFICIENT_FilterCoefficient_start 0 + +static inline uint32_t ATTRIBUTE_PURE +FILTER_COEFFICIENT_FilterCoefficient_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GATHER_CONSTANT_ENTRY */ + + +#define GEN11_GATHER_CONSTANT_ENTRY_length 1 +#define GEN10_GATHER_CONSTANT_ENTRY_length 1 +#define GEN9_GATHER_CONSTANT_ENTRY_length 1 +#define GEN8_GATHER_CONSTANT_ENTRY_length 1 +#define GEN75_GATHER_CONSTANT_ENTRY_length 1 + +static inline uint32_t ATTRIBUTE_PURE +GATHER_CONSTANT_ENTRY_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GATHER_CONSTANT_ENTRY::Binding Table Index Offset */ + + +#define GEN11_GATHER_CONSTANT_ENTRY_BindingTableIndexOffset_bits 4 +#define GEN10_GATHER_CONSTANT_ENTRY_BindingTableIndexOffset_bits 4 +#define GEN9_GATHER_CONSTANT_ENTRY_BindingTableIndexOffset_bits 4 +#define GEN8_GATHER_CONSTANT_ENTRY_BindingTableIndexOffset_bits 4 +#define GEN75_GATHER_CONSTANT_ENTRY_BindingTableIndexOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +GATHER_CONSTANT_ENTRY_BindingTableIndexOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_GATHER_CONSTANT_ENTRY_BindingTableIndexOffset_start 0 +#define GEN10_GATHER_CONSTANT_ENTRY_BindingTableIndexOffset_start 0 +#define GEN9_GATHER_CONSTANT_ENTRY_BindingTableIndexOffset_start 0 +#define GEN8_GATHER_CONSTANT_ENTRY_BindingTableIndexOffset_start 0 +#define GEN75_GATHER_CONSTANT_ENTRY_BindingTableIndexOffset_start 0 + +static inline uint32_t ATTRIBUTE_PURE +GATHER_CONSTANT_ENTRY_BindingTableIndexOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GATHER_CONSTANT_ENTRY::Channel Mask */ + + +#define GEN11_GATHER_CONSTANT_ENTRY_ChannelMask_bits 4 +#define GEN10_GATHER_CONSTANT_ENTRY_ChannelMask_bits 4 +#define GEN9_GATHER_CONSTANT_ENTRY_ChannelMask_bits 4 +#define GEN8_GATHER_CONSTANT_ENTRY_ChannelMask_bits 4 +#define GEN75_GATHER_CONSTANT_ENTRY_ChannelMask_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +GATHER_CONSTANT_ENTRY_ChannelMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_GATHER_CONSTANT_ENTRY_ChannelMask_start 4 +#define GEN10_GATHER_CONSTANT_ENTRY_ChannelMask_start 4 +#define GEN9_GATHER_CONSTANT_ENTRY_ChannelMask_start 4 +#define GEN8_GATHER_CONSTANT_ENTRY_ChannelMask_start 4 +#define GEN75_GATHER_CONSTANT_ENTRY_ChannelMask_start 4 + +static inline uint32_t ATTRIBUTE_PURE +GATHER_CONSTANT_ENTRY_ChannelMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GATHER_CONSTANT_ENTRY::Constant Buffer Offset */ + + +#define GEN11_GATHER_CONSTANT_ENTRY_ConstantBufferOffset_bits 8 +#define GEN10_GATHER_CONSTANT_ENTRY_ConstantBufferOffset_bits 8 +#define GEN9_GATHER_CONSTANT_ENTRY_ConstantBufferOffset_bits 8 +#define GEN8_GATHER_CONSTANT_ENTRY_ConstantBufferOffset_bits 8 +#define GEN75_GATHER_CONSTANT_ENTRY_ConstantBufferOffset_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +GATHER_CONSTANT_ENTRY_ConstantBufferOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_GATHER_CONSTANT_ENTRY_ConstantBufferOffset_start 8 +#define GEN10_GATHER_CONSTANT_ENTRY_ConstantBufferOffset_start 8 +#define GEN9_GATHER_CONSTANT_ENTRY_ConstantBufferOffset_start 8 +#define GEN8_GATHER_CONSTANT_ENTRY_ConstantBufferOffset_start 8 +#define GEN75_GATHER_CONSTANT_ENTRY_ConstantBufferOffset_start 8 + +static inline uint32_t ATTRIBUTE_PURE +GATHER_CONSTANT_ENTRY_ConstantBufferOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GFX_ARB_ERROR_RPT */ + + +#define GEN9_GFX_ARB_ERROR_RPT_length 1 +#define GEN8_GFX_ARB_ERROR_RPT_length 1 +#define GEN75_GFX_ARB_ERROR_RPT_length 1 +#define GEN7_GFX_ARB_ERROR_RPT_length 1 +#define GEN6_GFX_ARB_ERROR_RPT_length 1 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GFX_ARB_ERROR_RPT::Context Page Fault Error */ + + +#define GEN75_GFX_ARB_ERROR_RPT_ContextPageFaultError_bits 1 +#define GEN7_GFX_ARB_ERROR_RPT_ContextPageFaultError_bits 1 +#define GEN6_GFX_ARB_ERROR_RPT_ContextPageFaultError_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_ContextPageFaultError_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_GFX_ARB_ERROR_RPT_ContextPageFaultError_start 1 +#define GEN7_GFX_ARB_ERROR_RPT_ContextPageFaultError_start 1 +#define GEN6_GFX_ARB_ERROR_RPT_ContextPageFaultError_start 1 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_ContextPageFaultError_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GFX_ARB_ERROR_RPT::Context Page VTD Translation Error */ + + +#define GEN75_GFX_ARB_ERROR_RPT_ContextPageVTDTranslationError_bits 1 +#define GEN7_GFX_ARB_ERROR_RPT_ContextPageVTDTranslationError_bits 1 +#define GEN6_GFX_ARB_ERROR_RPT_ContextPageVTDTranslationError_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_ContextPageVTDTranslationError_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_GFX_ARB_ERROR_RPT_ContextPageVTDTranslationError_start 5 +#define GEN7_GFX_ARB_ERROR_RPT_ContextPageVTDTranslationError_start 5 +#define GEN6_GFX_ARB_ERROR_RPT_ContextPageVTDTranslationError_start 5 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_ContextPageVTDTranslationError_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 5; + } + case 6: return 5; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GFX_ARB_ERROR_RPT::Context Was Not Marked As Present When Doing DMA */ + + +#define GEN9_GFX_ARB_ERROR_RPT_ContextWasNotMarkedAsPresentWhenDoingDMA_bits 1 +#define GEN8_GFX_ARB_ERROR_RPT_ContextWasNotMarkedAsPresentWhenDoingDMA_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_ContextWasNotMarkedAsPresentWhenDoingDMA_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_GFX_ARB_ERROR_RPT_ContextWasNotMarkedAsPresentWhenDoingDMA_start 15 +#define GEN8_GFX_ARB_ERROR_RPT_ContextWasNotMarkedAsPresentWhenDoingDMA_start 15 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_ContextWasNotMarkedAsPresentWhenDoingDMA_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 15; + case 8: return 15; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GFX_ARB_ERROR_RPT::GuC VTd translation Page Fault 2nd level (Undefined doorbell) */ + + +#define GEN9_GFX_ARB_ERROR_RPT_GuCVTdtranslationPageFault2ndlevelUndefineddoorbell_bits 1 +#define GEN8_GFX_ARB_ERROR_RPT_GuCVTdtranslationPageFault2ndlevelUndefineddoorbell_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_GuCVTdtranslationPageFault2ndlevelUndefineddoorbell_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_GFX_ARB_ERROR_RPT_GuCVTdtranslationPageFault2ndlevelUndefineddoorbell_start 9 +#define GEN8_GFX_ARB_ERROR_RPT_GuCVTdtranslationPageFault2ndlevelUndefineddoorbell_start 9 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_GuCVTdtranslationPageFault2ndlevelUndefineddoorbell_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GFX_ARB_ERROR_RPT::Hardware Status Page Fault Error */ + + +#define GEN75_GFX_ARB_ERROR_RPT_HardwareStatusPageFaultError_bits 1 +#define GEN7_GFX_ARB_ERROR_RPT_HardwareStatusPageFaultError_bits 1 +#define GEN6_GFX_ARB_ERROR_RPT_HardwareStatusPageFaultError_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_HardwareStatusPageFaultError_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_GFX_ARB_ERROR_RPT_HardwareStatusPageFaultError_start 3 +#define GEN7_GFX_ARB_ERROR_RPT_HardwareStatusPageFaultError_start 3 +#define GEN6_GFX_ARB_ERROR_RPT_HardwareStatusPageFaultError_start 3 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_HardwareStatusPageFaultError_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GFX_ARB_ERROR_RPT::Hardware Status Page VTD Translation Error */ + + +#define GEN75_GFX_ARB_ERROR_RPT_HardwareStatusPageVTDTranslationError_bits 1 +#define GEN7_GFX_ARB_ERROR_RPT_HardwareStatusPageVTDTranslationError_bits 1 +#define GEN6_GFX_ARB_ERROR_RPT_HardwareStatusPageVTDTranslationError_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_HardwareStatusPageVTDTranslationError_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_GFX_ARB_ERROR_RPT_HardwareStatusPageVTDTranslationError_start 7 +#define GEN7_GFX_ARB_ERROR_RPT_HardwareStatusPageVTDTranslationError_start 7 +#define GEN6_GFX_ARB_ERROR_RPT_HardwareStatusPageVTDTranslationError_start 7 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_HardwareStatusPageVTDTranslationError_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 7; + } else { + return 7; + } + case 6: return 7; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GFX_ARB_ERROR_RPT::Invalid Page Directory Entry Error */ + + +#define GEN9_GFX_ARB_ERROR_RPT_InvalidPageDirectoryEntryError_bits 1 +#define GEN8_GFX_ARB_ERROR_RPT_InvalidPageDirectoryEntryError_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_InvalidPageDirectoryEntryError_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_GFX_ARB_ERROR_RPT_InvalidPageDirectoryEntryError_start 2 +#define GEN8_GFX_ARB_ERROR_RPT_InvalidPageDirectoryEntryError_start 2 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_InvalidPageDirectoryEntryError_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GFX_ARB_ERROR_RPT::Invalid Page Directory entry error */ + + +#define GEN75_GFX_ARB_ERROR_RPT_InvalidPageDirectoryentryerror_bits 1 +#define GEN7_GFX_ARB_ERROR_RPT_InvalidPageDirectoryentryerror_bits 1 +#define GEN6_GFX_ARB_ERROR_RPT_InvalidPageDirectoryentryerror_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_InvalidPageDirectoryentryerror_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_GFX_ARB_ERROR_RPT_InvalidPageDirectoryentryerror_start 2 +#define GEN7_GFX_ARB_ERROR_RPT_InvalidPageDirectoryentryerror_start 2 +#define GEN6_GFX_ARB_ERROR_RPT_InvalidPageDirectoryentryerror_start 2 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_InvalidPageDirectoryentryerror_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GFX_ARB_ERROR_RPT::Non WB memory type for Advanced Context */ + + +#define GEN9_GFX_ARB_ERROR_RPT_NonWBmemorytypeforAdvancedContext_bits 1 +#define GEN8_GFX_ARB_ERROR_RPT_NonWBmemorytypeforAdvancedContext_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_NonWBmemorytypeforAdvancedContext_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_GFX_ARB_ERROR_RPT_NonWBmemorytypeforAdvancedContext_start 10 +#define GEN8_GFX_ARB_ERROR_RPT_NonWBmemorytypeforAdvancedContext_start 10 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_NonWBmemorytypeforAdvancedContext_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 10; + case 8: return 10; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GFX_ARB_ERROR_RPT::PASID Boundary Violation */ + + +#define GEN9_GFX_ARB_ERROR_RPT_PASIDBoundaryViolation_bits 1 +#define GEN8_GFX_ARB_ERROR_RPT_PASIDBoundaryViolation_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_PASIDBoundaryViolation_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_GFX_ARB_ERROR_RPT_PASIDBoundaryViolation_start 12 +#define GEN8_GFX_ARB_ERROR_RPT_PASIDBoundaryViolation_start 12 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_PASIDBoundaryViolation_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 12; + case 8: return 12; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GFX_ARB_ERROR_RPT::PASID Not Enabled */ + + +#define GEN9_GFX_ARB_ERROR_RPT_PASIDNotEnabled_bits 1 +#define GEN8_GFX_ARB_ERROR_RPT_PASIDNotEnabled_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_PASIDNotEnabled_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_GFX_ARB_ERROR_RPT_PASIDNotEnabled_start 11 +#define GEN8_GFX_ARB_ERROR_RPT_PASIDNotEnabled_start 11 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_PASIDNotEnabled_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 11; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GFX_ARB_ERROR_RPT::PASID Not Valid */ + + +#define GEN9_GFX_ARB_ERROR_RPT_PASIDNotValid_bits 1 +#define GEN8_GFX_ARB_ERROR_RPT_PASIDNotValid_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_PASIDNotValid_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_GFX_ARB_ERROR_RPT_PASIDNotValid_start 13 +#define GEN8_GFX_ARB_ERROR_RPT_PASIDNotValid_start 13 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_PASIDNotValid_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 13; + case 8: return 13; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GFX_ARB_ERROR_RPT::PASID Was Zero For Untranslated Request */ + + +#define GEN9_GFX_ARB_ERROR_RPT_PASIDWasZeroForUntranslatedRequest_bits 1 +#define GEN8_GFX_ARB_ERROR_RPT_PASIDWasZeroForUntranslatedRequest_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_PASIDWasZeroForUntranslatedRequest_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_GFX_ARB_ERROR_RPT_PASIDWasZeroForUntranslatedRequest_start 14 +#define GEN8_GFX_ARB_ERROR_RPT_PASIDWasZeroForUntranslatedRequest_start 14 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_PASIDWasZeroForUntranslatedRequest_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 14; + case 8: return 14; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GFX_ARB_ERROR_RPT::Page Directory Entry VTD Translation Error */ + + +#define GEN9_GFX_ARB_ERROR_RPT_PageDirectoryEntryVTDTranslationError_bits 1 +#define GEN8_GFX_ARB_ERROR_RPT_PageDirectoryEntryVTDTranslationError_bits 1 +#define GEN75_GFX_ARB_ERROR_RPT_PageDirectoryEntryVTDTranslationError_bits 1 +#define GEN7_GFX_ARB_ERROR_RPT_PageDirectoryEntryVTDTranslationError_bits 1 +#define GEN6_GFX_ARB_ERROR_RPT_PageDirectoryEntryVTDTranslationError_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_PageDirectoryEntryVTDTranslationError_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_GFX_ARB_ERROR_RPT_PageDirectoryEntryVTDTranslationError_start 6 +#define GEN8_GFX_ARB_ERROR_RPT_PageDirectoryEntryVTDTranslationError_start 6 +#define GEN75_GFX_ARB_ERROR_RPT_PageDirectoryEntryVTDTranslationError_start 6 +#define GEN7_GFX_ARB_ERROR_RPT_PageDirectoryEntryVTDTranslationError_start 6 +#define GEN6_GFX_ARB_ERROR_RPT_PageDirectoryEntryVTDTranslationError_start 6 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_PageDirectoryEntryVTDTranslationError_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 6; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GFX_ARB_ERROR_RPT::Pending Page Faults */ + + +#define GEN75_GFX_ARB_ERROR_RPT_PendingPageFaults_bits 7 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_PendingPageFaults_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 7; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_GFX_ARB_ERROR_RPT_PendingPageFaults_start 9 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_PendingPageFaults_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GFX_ARB_ERROR_RPT::ROSTRM PAVP Invalid Physical Address */ + + +#define GEN9_GFX_ARB_ERROR_RPT_ROSTRMPAVPInvalidPhysicalAddress_bits 1 +#define GEN8_GFX_ARB_ERROR_RPT_ROSTRMPAVPInvalidPhysicalAddress_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_ROSTRMPAVPInvalidPhysicalAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_GFX_ARB_ERROR_RPT_ROSTRMPAVPInvalidPhysicalAddress_start 3 +#define GEN8_GFX_ARB_ERROR_RPT_ROSTRMPAVPInvalidPhysicalAddress_start 3 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_ROSTRMPAVPInvalidPhysicalAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GFX_ARB_ERROR_RPT::RSTRM PAVP Read Invalid */ + + +#define GEN9_GFX_ARB_ERROR_RPT_RSTRMPAVPReadInvalid_bits 1 +#define GEN8_GFX_ARB_ERROR_RPT_RSTRMPAVPReadInvalid_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_RSTRMPAVPReadInvalid_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_GFX_ARB_ERROR_RPT_RSTRMPAVPReadInvalid_start 1 +#define GEN8_GFX_ARB_ERROR_RPT_RSTRMPAVPReadInvalid_start 1 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_RSTRMPAVPReadInvalid_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GFX_ARB_ERROR_RPT::TLB Page Fault Error */ + + +#define GEN9_GFX_ARB_ERROR_RPT_TLBPageFaultError_bits 1 +#define GEN8_GFX_ARB_ERROR_RPT_TLBPageFaultError_bits 1 +#define GEN75_GFX_ARB_ERROR_RPT_TLBPageFaultError_bits 1 +#define GEN7_GFX_ARB_ERROR_RPT_TLBPageFaultError_bits 1 +#define GEN6_GFX_ARB_ERROR_RPT_TLBPageFaultError_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_TLBPageFaultError_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_GFX_ARB_ERROR_RPT_TLBPageFaultError_start 0 +#define GEN8_GFX_ARB_ERROR_RPT_TLBPageFaultError_start 0 +#define GEN75_GFX_ARB_ERROR_RPT_TLBPageFaultError_start 0 +#define GEN7_GFX_ARB_ERROR_RPT_TLBPageFaultError_start 0 +#define GEN6_GFX_ARB_ERROR_RPT_TLBPageFaultError_start 0 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_TLBPageFaultError_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GFX_ARB_ERROR_RPT::TLB Page VTD Translation Error */ + + +#define GEN9_GFX_ARB_ERROR_RPT_TLBPageVTDTranslationError_bits 1 +#define GEN8_GFX_ARB_ERROR_RPT_TLBPageVTDTranslationError_bits 1 +#define GEN75_GFX_ARB_ERROR_RPT_TLBPageVTDTranslationError_bits 1 +#define GEN7_GFX_ARB_ERROR_RPT_TLBPageVTDTranslationError_bits 1 +#define GEN6_GFX_ARB_ERROR_RPT_TLBPageVTDTranslationError_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_TLBPageVTDTranslationError_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_GFX_ARB_ERROR_RPT_TLBPageVTDTranslationError_start 4 +#define GEN8_GFX_ARB_ERROR_RPT_TLBPageVTDTranslationError_start 4 +#define GEN75_GFX_ARB_ERROR_RPT_TLBPageVTDTranslationError_start 4 +#define GEN7_GFX_ARB_ERROR_RPT_TLBPageVTDTranslationError_start 4 +#define GEN6_GFX_ARB_ERROR_RPT_TLBPageVTDTranslationError_start 4 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_TLBPageVTDTranslationError_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GFX_ARB_ERROR_RPT::Unloaded PD Error */ + + +#define GEN9_GFX_ARB_ERROR_RPT_UnloadedPDError_bits 1 +#define GEN8_GFX_ARB_ERROR_RPT_UnloadedPDError_bits 1 +#define GEN75_GFX_ARB_ERROR_RPT_UnloadedPDError_bits 1 +#define GEN7_GFX_ARB_ERROR_RPT_UnloadedPDError_bits 1 +#define GEN6_GFX_ARB_ERROR_RPT_UnloadedPDError_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_UnloadedPDError_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_GFX_ARB_ERROR_RPT_UnloadedPDError_start 8 +#define GEN8_GFX_ARB_ERROR_RPT_UnloadedPDError_start 8 +#define GEN75_GFX_ARB_ERROR_RPT_UnloadedPDError_start 8 +#define GEN7_GFX_ARB_ERROR_RPT_UnloadedPDError_start 8 +#define GEN6_GFX_ARB_ERROR_RPT_UnloadedPDError_start 8 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_UnloadedPDError_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GFX_ARB_ERROR_RPT::WRDP PAVP Invalid */ + + +#define GEN9_GFX_ARB_ERROR_RPT_WRDPPAVPInvalid_bits 1 +#define GEN8_GFX_ARB_ERROR_RPT_WRDPPAVPInvalid_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_WRDPPAVPInvalid_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_GFX_ARB_ERROR_RPT_WRDPPAVPInvalid_start 5 +#define GEN8_GFX_ARB_ERROR_RPT_WRDPPAVPInvalid_start 5 + +static inline uint32_t ATTRIBUTE_PURE +GFX_ARB_ERROR_RPT_WRDPPAVPInvalid_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_CSR_BASE_ADDRESS */ + + +#define GEN9_GPGPU_CSR_BASE_ADDRESS_length 3 +#define GEN8_GPGPU_CSR_BASE_ADDRESS_length 3 +#define GEN75_GPGPU_CSR_BASE_ADDRESS_length 2 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_CSR_BASE_ADDRESS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_CSR_BASE_ADDRESS::3D Command Opcode */ + + +#define GEN9_GPGPU_CSR_BASE_ADDRESS_3DCommandOpcode_bits 3 +#define GEN8_GPGPU_CSR_BASE_ADDRESS_3DCommandOpcode_bits 3 +#define GEN75_GPGPU_CSR_BASE_ADDRESS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_CSR_BASE_ADDRESS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_GPGPU_CSR_BASE_ADDRESS_3DCommandOpcode_start 24 +#define GEN8_GPGPU_CSR_BASE_ADDRESS_3DCommandOpcode_start 24 +#define GEN75_GPGPU_CSR_BASE_ADDRESS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_CSR_BASE_ADDRESS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_CSR_BASE_ADDRESS::3D Command Sub Opcode */ + + +#define GEN9_GPGPU_CSR_BASE_ADDRESS_3DCommandSubOpcode_bits 8 +#define GEN8_GPGPU_CSR_BASE_ADDRESS_3DCommandSubOpcode_bits 8 +#define GEN75_GPGPU_CSR_BASE_ADDRESS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_CSR_BASE_ADDRESS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_GPGPU_CSR_BASE_ADDRESS_3DCommandSubOpcode_start 16 +#define GEN8_GPGPU_CSR_BASE_ADDRESS_3DCommandSubOpcode_start 16 +#define GEN75_GPGPU_CSR_BASE_ADDRESS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_CSR_BASE_ADDRESS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_CSR_BASE_ADDRESS::Command SubType */ + + +#define GEN9_GPGPU_CSR_BASE_ADDRESS_CommandSubType_bits 2 +#define GEN8_GPGPU_CSR_BASE_ADDRESS_CommandSubType_bits 2 +#define GEN75_GPGPU_CSR_BASE_ADDRESS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_CSR_BASE_ADDRESS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_GPGPU_CSR_BASE_ADDRESS_CommandSubType_start 27 +#define GEN8_GPGPU_CSR_BASE_ADDRESS_CommandSubType_start 27 +#define GEN75_GPGPU_CSR_BASE_ADDRESS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_CSR_BASE_ADDRESS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_CSR_BASE_ADDRESS::Command Type */ + + +#define GEN9_GPGPU_CSR_BASE_ADDRESS_CommandType_bits 3 +#define GEN8_GPGPU_CSR_BASE_ADDRESS_CommandType_bits 3 +#define GEN75_GPGPU_CSR_BASE_ADDRESS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_CSR_BASE_ADDRESS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_GPGPU_CSR_BASE_ADDRESS_CommandType_start 29 +#define GEN8_GPGPU_CSR_BASE_ADDRESS_CommandType_start 29 +#define GEN75_GPGPU_CSR_BASE_ADDRESS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_CSR_BASE_ADDRESS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_CSR_BASE_ADDRESS::DWord Length */ + + +#define GEN9_GPGPU_CSR_BASE_ADDRESS_DWordLength_bits 8 +#define GEN8_GPGPU_CSR_BASE_ADDRESS_DWordLength_bits 8 +#define GEN75_GPGPU_CSR_BASE_ADDRESS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_CSR_BASE_ADDRESS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_GPGPU_CSR_BASE_ADDRESS_DWordLength_start 0 +#define GEN8_GPGPU_CSR_BASE_ADDRESS_DWordLength_start 0 +#define GEN75_GPGPU_CSR_BASE_ADDRESS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_CSR_BASE_ADDRESS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_CSR_BASE_ADDRESS::GPGPU CSR Base Address */ + + +#define GEN9_GPGPU_CSR_BASE_ADDRESS_GPGPUCSRBaseAddress_bits 52 +#define GEN8_GPGPU_CSR_BASE_ADDRESS_GPGPUCSRBaseAddress_bits 52 +#define GEN75_GPGPU_CSR_BASE_ADDRESS_GPGPUCSRBaseAddress_bits 20 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_CSR_BASE_ADDRESS_GPGPUCSRBaseAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 52; + case 8: return 52; + case 7: + if (devinfo->is_haswell) { + return 20; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_GPGPU_CSR_BASE_ADDRESS_GPGPUCSRBaseAddress_start 44 +#define GEN8_GPGPU_CSR_BASE_ADDRESS_GPGPUCSRBaseAddress_start 44 +#define GEN75_GPGPU_CSR_BASE_ADDRESS_GPGPUCSRBaseAddress_start 44 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_CSR_BASE_ADDRESS_GPGPUCSRBaseAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 44; + case 8: return 44; + case 7: + if (devinfo->is_haswell) { + return 44; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_OBJECT */ + + +#define GEN75_GPGPU_OBJECT_length 8 +#define GEN7_GPGPU_OBJECT_length 8 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_OBJECT_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_OBJECT::Command Type */ + + +#define GEN75_GPGPU_OBJECT_CommandType_bits 3 +#define GEN7_GPGPU_OBJECT_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_OBJECT_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_GPGPU_OBJECT_CommandType_start 29 +#define GEN7_GPGPU_OBJECT_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_OBJECT_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_OBJECT::DWord Length */ + + +#define GEN75_GPGPU_OBJECT_DWordLength_bits 8 +#define GEN7_GPGPU_OBJECT_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_OBJECT_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_GPGPU_OBJECT_DWordLength_start 0 +#define GEN7_GPGPU_OBJECT_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_OBJECT_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_OBJECT::End of Thread Group */ + + +#define GEN75_GPGPU_OBJECT_EndofThreadGroup_bits 1 +#define GEN7_GPGPU_OBJECT_EndofThreadGroup_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_OBJECT_EndofThreadGroup_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_GPGPU_OBJECT_EndofThreadGroup_start 88 +#define GEN7_GPGPU_OBJECT_EndofThreadGroup_start 88 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_OBJECT_EndofThreadGroup_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 88; + } else { + return 88; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_OBJECT::Execution Mask */ + + +#define GEN75_GPGPU_OBJECT_ExecutionMask_bits 32 +#define GEN7_GPGPU_OBJECT_ExecutionMask_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_OBJECT_ExecutionMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_GPGPU_OBJECT_ExecutionMask_start 224 +#define GEN7_GPGPU_OBJECT_ExecutionMask_start 224 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_OBJECT_ExecutionMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 224; + } else { + return 224; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_OBJECT::Half-Slice Destination Select */ + + +#define GEN75_GPGPU_OBJECT_HalfSliceDestinationSelect_bits 2 +#define GEN7_GPGPU_OBJECT_HalfSliceDestinationSelect_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_OBJECT_HalfSliceDestinationSelect_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_GPGPU_OBJECT_HalfSliceDestinationSelect_start 81 +#define GEN7_GPGPU_OBJECT_HalfSliceDestinationSelect_start 81 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_OBJECT_HalfSliceDestinationSelect_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 81; + } else { + return 81; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_OBJECT::Indirect Data Length */ + + +#define GEN75_GPGPU_OBJECT_IndirectDataLength_bits 17 +#define GEN7_GPGPU_OBJECT_IndirectDataLength_bits 17 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_OBJECT_IndirectDataLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 17; + } else { + return 17; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_GPGPU_OBJECT_IndirectDataLength_start 64 +#define GEN7_GPGPU_OBJECT_IndirectDataLength_start 64 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_OBJECT_IndirectDataLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_OBJECT::Indirect Data Start Address */ + + +#define GEN75_GPGPU_OBJECT_IndirectDataStartAddress_bits 32 +#define GEN7_GPGPU_OBJECT_IndirectDataStartAddress_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_OBJECT_IndirectDataStartAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_GPGPU_OBJECT_IndirectDataStartAddress_start 96 +#define GEN7_GPGPU_OBJECT_IndirectDataStartAddress_start 96 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_OBJECT_IndirectDataStartAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 96; + } else { + return 96; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_OBJECT::Interface Descriptor Offset */ + + +#define GEN75_GPGPU_OBJECT_InterfaceDescriptorOffset_bits 6 +#define GEN7_GPGPU_OBJECT_InterfaceDescriptorOffset_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_OBJECT_InterfaceDescriptorOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 5; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_GPGPU_OBJECT_InterfaceDescriptorOffset_start 32 +#define GEN7_GPGPU_OBJECT_InterfaceDescriptorOffset_start 32 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_OBJECT_InterfaceDescriptorOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_OBJECT::Media Command Opcode */ + + +#define GEN75_GPGPU_OBJECT_MediaCommandOpcode_bits 3 +#define GEN7_GPGPU_OBJECT_MediaCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_OBJECT_MediaCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_GPGPU_OBJECT_MediaCommandOpcode_start 24 +#define GEN7_GPGPU_OBJECT_MediaCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_OBJECT_MediaCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_OBJECT::Pipeline */ + + +#define GEN75_GPGPU_OBJECT_Pipeline_bits 2 +#define GEN7_GPGPU_OBJECT_Pipeline_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_OBJECT_Pipeline_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_GPGPU_OBJECT_Pipeline_start 27 +#define GEN7_GPGPU_OBJECT_Pipeline_start 27 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_OBJECT_Pipeline_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_OBJECT::Predicate Enable */ + + +#define GEN75_GPGPU_OBJECT_PredicateEnable_bits 1 +#define GEN7_GPGPU_OBJECT_PredicateEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_OBJECT_PredicateEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_GPGPU_OBJECT_PredicateEnable_start 8 +#define GEN7_GPGPU_OBJECT_PredicateEnable_start 8 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_OBJECT_PredicateEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_OBJECT::Shared Local Memory Fixed Offset */ + + +#define GEN75_GPGPU_OBJECT_SharedLocalMemoryFixedOffset_bits 1 +#define GEN7_GPGPU_OBJECT_SharedLocalMemoryFixedOffset_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_OBJECT_SharedLocalMemoryFixedOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_GPGPU_OBJECT_SharedLocalMemoryFixedOffset_start 39 +#define GEN7_GPGPU_OBJECT_SharedLocalMemoryFixedOffset_start 39 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_OBJECT_SharedLocalMemoryFixedOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 39; + } else { + return 39; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_OBJECT::Shared Local Memory Offset */ + + +#define GEN75_GPGPU_OBJECT_SharedLocalMemoryOffset_bits 4 +#define GEN7_GPGPU_OBJECT_SharedLocalMemoryOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_OBJECT_SharedLocalMemoryOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_GPGPU_OBJECT_SharedLocalMemoryOffset_start 92 +#define GEN7_GPGPU_OBJECT_SharedLocalMemoryOffset_start 92 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_OBJECT_SharedLocalMemoryOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 92; + } else { + return 92; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_OBJECT::Slice Destination Select */ + + +#define GEN75_GPGPU_OBJECT_SliceDestinationSelect_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_OBJECT_SliceDestinationSelect_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_GPGPU_OBJECT_SliceDestinationSelect_start 83 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_OBJECT_SliceDestinationSelect_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 83; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_OBJECT::SubOpcode */ + + +#define GEN75_GPGPU_OBJECT_SubOpcode_bits 8 +#define GEN7_GPGPU_OBJECT_SubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_OBJECT_SubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_GPGPU_OBJECT_SubOpcode_start 16 +#define GEN7_GPGPU_OBJECT_SubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_OBJECT_SubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_OBJECT::Thread Group ID X */ + + +#define GEN75_GPGPU_OBJECT_ThreadGroupIDX_bits 32 +#define GEN7_GPGPU_OBJECT_ThreadGroupIDX_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_OBJECT_ThreadGroupIDX_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_GPGPU_OBJECT_ThreadGroupIDX_start 128 +#define GEN7_GPGPU_OBJECT_ThreadGroupIDX_start 128 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_OBJECT_ThreadGroupIDX_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 128; + } else { + return 128; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_OBJECT::Thread Group ID Y */ + + +#define GEN75_GPGPU_OBJECT_ThreadGroupIDY_bits 32 +#define GEN7_GPGPU_OBJECT_ThreadGroupIDY_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_OBJECT_ThreadGroupIDY_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_GPGPU_OBJECT_ThreadGroupIDY_start 160 +#define GEN7_GPGPU_OBJECT_ThreadGroupIDY_start 160 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_OBJECT_ThreadGroupIDY_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 160; + } else { + return 160; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_OBJECT::Thread Group ID Z */ + + +#define GEN75_GPGPU_OBJECT_ThreadGroupIDZ_bits 32 +#define GEN7_GPGPU_OBJECT_ThreadGroupIDZ_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_OBJECT_ThreadGroupIDZ_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_GPGPU_OBJECT_ThreadGroupIDZ_start 192 +#define GEN7_GPGPU_OBJECT_ThreadGroupIDZ_start 192 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_OBJECT_ThreadGroupIDZ_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 192; + } else { + return 192; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_WALKER */ + + +#define GEN11_GPGPU_WALKER_length 15 +#define GEN10_GPGPU_WALKER_length 15 +#define GEN9_GPGPU_WALKER_length 15 +#define GEN8_GPGPU_WALKER_length 15 +#define GEN75_GPGPU_WALKER_length 11 +#define GEN7_GPGPU_WALKER_length 11 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 15; + case 10: return 15; + case 9: return 15; + case 8: return 15; + case 7: + if (devinfo->is_haswell) { + return 11; + } else { + return 11; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_WALKER::Bottom Execution Mask */ + + +#define GEN11_GPGPU_WALKER_BottomExecutionMask_bits 32 +#define GEN10_GPGPU_WALKER_BottomExecutionMask_bits 32 +#define GEN9_GPGPU_WALKER_BottomExecutionMask_bits 32 +#define GEN8_GPGPU_WALKER_BottomExecutionMask_bits 32 +#define GEN75_GPGPU_WALKER_BottomExecutionMask_bits 32 +#define GEN7_GPGPU_WALKER_BottomExecutionMask_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_BottomExecutionMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_GPGPU_WALKER_BottomExecutionMask_start 448 +#define GEN10_GPGPU_WALKER_BottomExecutionMask_start 448 +#define GEN9_GPGPU_WALKER_BottomExecutionMask_start 448 +#define GEN8_GPGPU_WALKER_BottomExecutionMask_start 448 +#define GEN75_GPGPU_WALKER_BottomExecutionMask_start 320 +#define GEN7_GPGPU_WALKER_BottomExecutionMask_start 320 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_BottomExecutionMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 448; + case 10: return 448; + case 9: return 448; + case 8: return 448; + case 7: + if (devinfo->is_haswell) { + return 320; + } else { + return 320; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_WALKER::Command Type */ + + +#define GEN11_GPGPU_WALKER_CommandType_bits 3 +#define GEN10_GPGPU_WALKER_CommandType_bits 3 +#define GEN9_GPGPU_WALKER_CommandType_bits 3 +#define GEN8_GPGPU_WALKER_CommandType_bits 3 +#define GEN75_GPGPU_WALKER_CommandType_bits 3 +#define GEN7_GPGPU_WALKER_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_GPGPU_WALKER_CommandType_start 29 +#define GEN10_GPGPU_WALKER_CommandType_start 29 +#define GEN9_GPGPU_WALKER_CommandType_start 29 +#define GEN8_GPGPU_WALKER_CommandType_start 29 +#define GEN75_GPGPU_WALKER_CommandType_start 29 +#define GEN7_GPGPU_WALKER_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_WALKER::DWord Length */ + + +#define GEN11_GPGPU_WALKER_DWordLength_bits 8 +#define GEN10_GPGPU_WALKER_DWordLength_bits 8 +#define GEN9_GPGPU_WALKER_DWordLength_bits 8 +#define GEN8_GPGPU_WALKER_DWordLength_bits 8 +#define GEN75_GPGPU_WALKER_DWordLength_bits 8 +#define GEN7_GPGPU_WALKER_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_GPGPU_WALKER_DWordLength_start 0 +#define GEN10_GPGPU_WALKER_DWordLength_start 0 +#define GEN9_GPGPU_WALKER_DWordLength_start 0 +#define GEN8_GPGPU_WALKER_DWordLength_start 0 +#define GEN75_GPGPU_WALKER_DWordLength_start 0 +#define GEN7_GPGPU_WALKER_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_WALKER::Indirect Data Length */ + + +#define GEN11_GPGPU_WALKER_IndirectDataLength_bits 17 +#define GEN10_GPGPU_WALKER_IndirectDataLength_bits 17 +#define GEN9_GPGPU_WALKER_IndirectDataLength_bits 17 +#define GEN8_GPGPU_WALKER_IndirectDataLength_bits 17 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_IndirectDataLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 17; + case 10: return 17; + case 9: return 17; + case 8: return 17; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_GPGPU_WALKER_IndirectDataLength_start 64 +#define GEN10_GPGPU_WALKER_IndirectDataLength_start 64 +#define GEN9_GPGPU_WALKER_IndirectDataLength_start 64 +#define GEN8_GPGPU_WALKER_IndirectDataLength_start 64 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_IndirectDataLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_WALKER::Indirect Data Start Address */ + + +#define GEN11_GPGPU_WALKER_IndirectDataStartAddress_bits 26 +#define GEN10_GPGPU_WALKER_IndirectDataStartAddress_bits 26 +#define GEN9_GPGPU_WALKER_IndirectDataStartAddress_bits 26 +#define GEN8_GPGPU_WALKER_IndirectDataStartAddress_bits 26 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_IndirectDataStartAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 26; + case 10: return 26; + case 9: return 26; + case 8: return 26; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_GPGPU_WALKER_IndirectDataStartAddress_start 102 +#define GEN10_GPGPU_WALKER_IndirectDataStartAddress_start 102 +#define GEN9_GPGPU_WALKER_IndirectDataStartAddress_start 102 +#define GEN8_GPGPU_WALKER_IndirectDataStartAddress_start 102 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_IndirectDataStartAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 102; + case 10: return 102; + case 9: return 102; + case 8: return 102; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_WALKER::Indirect Parameter Enable */ + + +#define GEN11_GPGPU_WALKER_IndirectParameterEnable_bits 1 +#define GEN10_GPGPU_WALKER_IndirectParameterEnable_bits 1 +#define GEN9_GPGPU_WALKER_IndirectParameterEnable_bits 1 +#define GEN8_GPGPU_WALKER_IndirectParameterEnable_bits 1 +#define GEN75_GPGPU_WALKER_IndirectParameterEnable_bits 1 +#define GEN7_GPGPU_WALKER_IndirectParameterEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_IndirectParameterEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_GPGPU_WALKER_IndirectParameterEnable_start 10 +#define GEN10_GPGPU_WALKER_IndirectParameterEnable_start 10 +#define GEN9_GPGPU_WALKER_IndirectParameterEnable_start 10 +#define GEN8_GPGPU_WALKER_IndirectParameterEnable_start 10 +#define GEN75_GPGPU_WALKER_IndirectParameterEnable_start 10 +#define GEN7_GPGPU_WALKER_IndirectParameterEnable_start 10 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_IndirectParameterEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 10; + case 10: return 10; + case 9: return 10; + case 8: return 10; + case 7: + if (devinfo->is_haswell) { + return 10; + } else { + return 10; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_WALKER::Interface Descriptor Offset */ + + +#define GEN11_GPGPU_WALKER_InterfaceDescriptorOffset_bits 6 +#define GEN10_GPGPU_WALKER_InterfaceDescriptorOffset_bits 6 +#define GEN9_GPGPU_WALKER_InterfaceDescriptorOffset_bits 6 +#define GEN8_GPGPU_WALKER_InterfaceDescriptorOffset_bits 6 +#define GEN75_GPGPU_WALKER_InterfaceDescriptorOffset_bits 6 +#define GEN7_GPGPU_WALKER_InterfaceDescriptorOffset_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_InterfaceDescriptorOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 5; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_GPGPU_WALKER_InterfaceDescriptorOffset_start 32 +#define GEN10_GPGPU_WALKER_InterfaceDescriptorOffset_start 32 +#define GEN9_GPGPU_WALKER_InterfaceDescriptorOffset_start 32 +#define GEN8_GPGPU_WALKER_InterfaceDescriptorOffset_start 32 +#define GEN75_GPGPU_WALKER_InterfaceDescriptorOffset_start 32 +#define GEN7_GPGPU_WALKER_InterfaceDescriptorOffset_start 32 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_InterfaceDescriptorOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_WALKER::Media Command Opcode */ + + +#define GEN11_GPGPU_WALKER_MediaCommandOpcode_bits 3 +#define GEN10_GPGPU_WALKER_MediaCommandOpcode_bits 3 +#define GEN9_GPGPU_WALKER_MediaCommandOpcode_bits 3 +#define GEN8_GPGPU_WALKER_MediaCommandOpcode_bits 3 +#define GEN75_GPGPU_WALKER_MediaCommandOpcode_bits 3 +#define GEN7_GPGPU_WALKER_MediaCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_MediaCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_GPGPU_WALKER_MediaCommandOpcode_start 24 +#define GEN10_GPGPU_WALKER_MediaCommandOpcode_start 24 +#define GEN9_GPGPU_WALKER_MediaCommandOpcode_start 24 +#define GEN8_GPGPU_WALKER_MediaCommandOpcode_start 24 +#define GEN75_GPGPU_WALKER_MediaCommandOpcode_start 24 +#define GEN7_GPGPU_WALKER_MediaCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_MediaCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_WALKER::Pipeline */ + + +#define GEN11_GPGPU_WALKER_Pipeline_bits 2 +#define GEN10_GPGPU_WALKER_Pipeline_bits 2 +#define GEN9_GPGPU_WALKER_Pipeline_bits 2 +#define GEN8_GPGPU_WALKER_Pipeline_bits 2 +#define GEN75_GPGPU_WALKER_Pipeline_bits 2 +#define GEN7_GPGPU_WALKER_Pipeline_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_Pipeline_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_GPGPU_WALKER_Pipeline_start 27 +#define GEN10_GPGPU_WALKER_Pipeline_start 27 +#define GEN9_GPGPU_WALKER_Pipeline_start 27 +#define GEN8_GPGPU_WALKER_Pipeline_start 27 +#define GEN75_GPGPU_WALKER_Pipeline_start 27 +#define GEN7_GPGPU_WALKER_Pipeline_start 27 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_Pipeline_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_WALKER::Predicate Enable */ + + +#define GEN11_GPGPU_WALKER_PredicateEnable_bits 1 +#define GEN10_GPGPU_WALKER_PredicateEnable_bits 1 +#define GEN9_GPGPU_WALKER_PredicateEnable_bits 1 +#define GEN8_GPGPU_WALKER_PredicateEnable_bits 1 +#define GEN75_GPGPU_WALKER_PredicateEnable_bits 1 +#define GEN7_GPGPU_WALKER_PredicateEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_PredicateEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_GPGPU_WALKER_PredicateEnable_start 8 +#define GEN10_GPGPU_WALKER_PredicateEnable_start 8 +#define GEN9_GPGPU_WALKER_PredicateEnable_start 8 +#define GEN8_GPGPU_WALKER_PredicateEnable_start 8 +#define GEN75_GPGPU_WALKER_PredicateEnable_start 8 +#define GEN7_GPGPU_WALKER_PredicateEnable_start 8 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_PredicateEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_WALKER::Right Execution Mask */ + + +#define GEN11_GPGPU_WALKER_RightExecutionMask_bits 32 +#define GEN10_GPGPU_WALKER_RightExecutionMask_bits 32 +#define GEN9_GPGPU_WALKER_RightExecutionMask_bits 32 +#define GEN8_GPGPU_WALKER_RightExecutionMask_bits 32 +#define GEN75_GPGPU_WALKER_RightExecutionMask_bits 32 +#define GEN7_GPGPU_WALKER_RightExecutionMask_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_RightExecutionMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_GPGPU_WALKER_RightExecutionMask_start 416 +#define GEN10_GPGPU_WALKER_RightExecutionMask_start 416 +#define GEN9_GPGPU_WALKER_RightExecutionMask_start 416 +#define GEN8_GPGPU_WALKER_RightExecutionMask_start 416 +#define GEN75_GPGPU_WALKER_RightExecutionMask_start 288 +#define GEN7_GPGPU_WALKER_RightExecutionMask_start 288 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_RightExecutionMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 416; + case 10: return 416; + case 9: return 416; + case 8: return 416; + case 7: + if (devinfo->is_haswell) { + return 288; + } else { + return 288; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_WALKER::SIMD Size */ + + +#define GEN11_GPGPU_WALKER_SIMDSize_bits 2 +#define GEN10_GPGPU_WALKER_SIMDSize_bits 2 +#define GEN9_GPGPU_WALKER_SIMDSize_bits 2 +#define GEN8_GPGPU_WALKER_SIMDSize_bits 2 +#define GEN75_GPGPU_WALKER_SIMDSize_bits 2 +#define GEN7_GPGPU_WALKER_SIMDSize_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_SIMDSize_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_GPGPU_WALKER_SIMDSize_start 158 +#define GEN10_GPGPU_WALKER_SIMDSize_start 158 +#define GEN9_GPGPU_WALKER_SIMDSize_start 158 +#define GEN8_GPGPU_WALKER_SIMDSize_start 158 +#define GEN75_GPGPU_WALKER_SIMDSize_start 94 +#define GEN7_GPGPU_WALKER_SIMDSize_start 94 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_SIMDSize_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 158; + case 10: return 158; + case 9: return 158; + case 8: return 158; + case 7: + if (devinfo->is_haswell) { + return 94; + } else { + return 94; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_WALKER::SubOpcode */ + + +#define GEN11_GPGPU_WALKER_SubOpcode_bits 8 +#define GEN10_GPGPU_WALKER_SubOpcode_bits 8 +#define GEN9_GPGPU_WALKER_SubOpcode_bits 8 +#define GEN8_GPGPU_WALKER_SubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_SubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_GPGPU_WALKER_SubOpcode_start 16 +#define GEN10_GPGPU_WALKER_SubOpcode_start 16 +#define GEN9_GPGPU_WALKER_SubOpcode_start 16 +#define GEN8_GPGPU_WALKER_SubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_SubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_WALKER::SubOpcode A */ + + +#define GEN75_GPGPU_WALKER_SubOpcodeA_bits 8 +#define GEN7_GPGPU_WALKER_SubOpcodeA_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_SubOpcodeA_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_GPGPU_WALKER_SubOpcodeA_start 16 +#define GEN7_GPGPU_WALKER_SubOpcodeA_start 16 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_SubOpcodeA_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_WALKER::Thread Depth Counter Maximum */ + + +#define GEN11_GPGPU_WALKER_ThreadDepthCounterMaximum_bits 6 +#define GEN10_GPGPU_WALKER_ThreadDepthCounterMaximum_bits 6 +#define GEN9_GPGPU_WALKER_ThreadDepthCounterMaximum_bits 6 +#define GEN8_GPGPU_WALKER_ThreadDepthCounterMaximum_bits 6 +#define GEN75_GPGPU_WALKER_ThreadDepthCounterMaximum_bits 6 +#define GEN7_GPGPU_WALKER_ThreadDepthCounterMaximum_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_ThreadDepthCounterMaximum_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_GPGPU_WALKER_ThreadDepthCounterMaximum_start 144 +#define GEN10_GPGPU_WALKER_ThreadDepthCounterMaximum_start 144 +#define GEN9_GPGPU_WALKER_ThreadDepthCounterMaximum_start 144 +#define GEN8_GPGPU_WALKER_ThreadDepthCounterMaximum_start 144 +#define GEN75_GPGPU_WALKER_ThreadDepthCounterMaximum_start 80 +#define GEN7_GPGPU_WALKER_ThreadDepthCounterMaximum_start 80 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_ThreadDepthCounterMaximum_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 144; + case 10: return 144; + case 9: return 144; + case 8: return 144; + case 7: + if (devinfo->is_haswell) { + return 80; + } else { + return 80; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_WALKER::Thread Group ID Starting X */ + + +#define GEN11_GPGPU_WALKER_ThreadGroupIDStartingX_bits 32 +#define GEN10_GPGPU_WALKER_ThreadGroupIDStartingX_bits 32 +#define GEN9_GPGPU_WALKER_ThreadGroupIDStartingX_bits 32 +#define GEN8_GPGPU_WALKER_ThreadGroupIDStartingX_bits 32 +#define GEN75_GPGPU_WALKER_ThreadGroupIDStartingX_bits 32 +#define GEN7_GPGPU_WALKER_ThreadGroupIDStartingX_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_ThreadGroupIDStartingX_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_GPGPU_WALKER_ThreadGroupIDStartingX_start 160 +#define GEN10_GPGPU_WALKER_ThreadGroupIDStartingX_start 160 +#define GEN9_GPGPU_WALKER_ThreadGroupIDStartingX_start 160 +#define GEN8_GPGPU_WALKER_ThreadGroupIDStartingX_start 160 +#define GEN75_GPGPU_WALKER_ThreadGroupIDStartingX_start 96 +#define GEN7_GPGPU_WALKER_ThreadGroupIDStartingX_start 96 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_ThreadGroupIDStartingX_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 160; + case 10: return 160; + case 9: return 160; + case 8: return 160; + case 7: + if (devinfo->is_haswell) { + return 96; + } else { + return 96; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_WALKER::Thread Group ID Starting Y */ + + +#define GEN11_GPGPU_WALKER_ThreadGroupIDStartingY_bits 32 +#define GEN10_GPGPU_WALKER_ThreadGroupIDStartingY_bits 32 +#define GEN9_GPGPU_WALKER_ThreadGroupIDStartingY_bits 32 +#define GEN8_GPGPU_WALKER_ThreadGroupIDStartingY_bits 32 +#define GEN75_GPGPU_WALKER_ThreadGroupIDStartingY_bits 32 +#define GEN7_GPGPU_WALKER_ThreadGroupIDStartingY_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_ThreadGroupIDStartingY_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_GPGPU_WALKER_ThreadGroupIDStartingY_start 256 +#define GEN10_GPGPU_WALKER_ThreadGroupIDStartingY_start 256 +#define GEN9_GPGPU_WALKER_ThreadGroupIDStartingY_start 256 +#define GEN8_GPGPU_WALKER_ThreadGroupIDStartingY_start 256 +#define GEN75_GPGPU_WALKER_ThreadGroupIDStartingY_start 160 +#define GEN7_GPGPU_WALKER_ThreadGroupIDStartingY_start 160 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_ThreadGroupIDStartingY_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 256; + case 10: return 256; + case 9: return 256; + case 8: return 256; + case 7: + if (devinfo->is_haswell) { + return 160; + } else { + return 160; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_WALKER::Thread Group ID Starting Z */ + + +#define GEN75_GPGPU_WALKER_ThreadGroupIDStartingZ_bits 32 +#define GEN7_GPGPU_WALKER_ThreadGroupIDStartingZ_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_ThreadGroupIDStartingZ_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_GPGPU_WALKER_ThreadGroupIDStartingZ_start 224 +#define GEN7_GPGPU_WALKER_ThreadGroupIDStartingZ_start 224 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_ThreadGroupIDStartingZ_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 224; + } else { + return 224; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_WALKER::Thread Group ID Starting/Resume Z */ + + +#define GEN11_GPGPU_WALKER_ThreadGroupIDStartingResumeZ_bits 32 +#define GEN10_GPGPU_WALKER_ThreadGroupIDStartingResumeZ_bits 32 +#define GEN9_GPGPU_WALKER_ThreadGroupIDStartingResumeZ_bits 32 +#define GEN8_GPGPU_WALKER_ThreadGroupIDStartingResumeZ_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_ThreadGroupIDStartingResumeZ_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_GPGPU_WALKER_ThreadGroupIDStartingResumeZ_start 352 +#define GEN10_GPGPU_WALKER_ThreadGroupIDStartingResumeZ_start 352 +#define GEN9_GPGPU_WALKER_ThreadGroupIDStartingResumeZ_start 352 +#define GEN8_GPGPU_WALKER_ThreadGroupIDStartingResumeZ_start 352 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_ThreadGroupIDStartingResumeZ_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 352; + case 10: return 352; + case 9: return 352; + case 8: return 352; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_WALKER::Thread Group ID X Dimension */ + + +#define GEN11_GPGPU_WALKER_ThreadGroupIDXDimension_bits 32 +#define GEN10_GPGPU_WALKER_ThreadGroupIDXDimension_bits 32 +#define GEN9_GPGPU_WALKER_ThreadGroupIDXDimension_bits 32 +#define GEN8_GPGPU_WALKER_ThreadGroupIDXDimension_bits 32 +#define GEN75_GPGPU_WALKER_ThreadGroupIDXDimension_bits 32 +#define GEN7_GPGPU_WALKER_ThreadGroupIDXDimension_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_ThreadGroupIDXDimension_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_GPGPU_WALKER_ThreadGroupIDXDimension_start 224 +#define GEN10_GPGPU_WALKER_ThreadGroupIDXDimension_start 224 +#define GEN9_GPGPU_WALKER_ThreadGroupIDXDimension_start 224 +#define GEN8_GPGPU_WALKER_ThreadGroupIDXDimension_start 224 +#define GEN75_GPGPU_WALKER_ThreadGroupIDXDimension_start 128 +#define GEN7_GPGPU_WALKER_ThreadGroupIDXDimension_start 128 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_ThreadGroupIDXDimension_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 224; + case 10: return 224; + case 9: return 224; + case 8: return 224; + case 7: + if (devinfo->is_haswell) { + return 128; + } else { + return 128; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_WALKER::Thread Group ID Y Dimension */ + + +#define GEN11_GPGPU_WALKER_ThreadGroupIDYDimension_bits 32 +#define GEN10_GPGPU_WALKER_ThreadGroupIDYDimension_bits 32 +#define GEN9_GPGPU_WALKER_ThreadGroupIDYDimension_bits 32 +#define GEN8_GPGPU_WALKER_ThreadGroupIDYDimension_bits 32 +#define GEN75_GPGPU_WALKER_ThreadGroupIDYDimension_bits 32 +#define GEN7_GPGPU_WALKER_ThreadGroupIDYDimension_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_ThreadGroupIDYDimension_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_GPGPU_WALKER_ThreadGroupIDYDimension_start 320 +#define GEN10_GPGPU_WALKER_ThreadGroupIDYDimension_start 320 +#define GEN9_GPGPU_WALKER_ThreadGroupIDYDimension_start 320 +#define GEN8_GPGPU_WALKER_ThreadGroupIDYDimension_start 320 +#define GEN75_GPGPU_WALKER_ThreadGroupIDYDimension_start 192 +#define GEN7_GPGPU_WALKER_ThreadGroupIDYDimension_start 192 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_ThreadGroupIDYDimension_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 320; + case 10: return 320; + case 9: return 320; + case 8: return 320; + case 7: + if (devinfo->is_haswell) { + return 192; + } else { + return 192; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_WALKER::Thread Group ID Z Dimension */ + + +#define GEN11_GPGPU_WALKER_ThreadGroupIDZDimension_bits 32 +#define GEN10_GPGPU_WALKER_ThreadGroupIDZDimension_bits 32 +#define GEN9_GPGPU_WALKER_ThreadGroupIDZDimension_bits 32 +#define GEN8_GPGPU_WALKER_ThreadGroupIDZDimension_bits 32 +#define GEN75_GPGPU_WALKER_ThreadGroupIDZDimension_bits 32 +#define GEN7_GPGPU_WALKER_ThreadGroupIDZDimension_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_ThreadGroupIDZDimension_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_GPGPU_WALKER_ThreadGroupIDZDimension_start 384 +#define GEN10_GPGPU_WALKER_ThreadGroupIDZDimension_start 384 +#define GEN9_GPGPU_WALKER_ThreadGroupIDZDimension_start 384 +#define GEN8_GPGPU_WALKER_ThreadGroupIDZDimension_start 384 +#define GEN75_GPGPU_WALKER_ThreadGroupIDZDimension_start 256 +#define GEN7_GPGPU_WALKER_ThreadGroupIDZDimension_start 256 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_ThreadGroupIDZDimension_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 384; + case 10: return 384; + case 9: return 384; + case 8: return 384; + case 7: + if (devinfo->is_haswell) { + return 256; + } else { + return 256; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_WALKER::Thread Height Counter Maximum */ + + +#define GEN11_GPGPU_WALKER_ThreadHeightCounterMaximum_bits 6 +#define GEN10_GPGPU_WALKER_ThreadHeightCounterMaximum_bits 6 +#define GEN9_GPGPU_WALKER_ThreadHeightCounterMaximum_bits 6 +#define GEN8_GPGPU_WALKER_ThreadHeightCounterMaximum_bits 6 +#define GEN75_GPGPU_WALKER_ThreadHeightCounterMaximum_bits 6 +#define GEN7_GPGPU_WALKER_ThreadHeightCounterMaximum_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_ThreadHeightCounterMaximum_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_GPGPU_WALKER_ThreadHeightCounterMaximum_start 136 +#define GEN10_GPGPU_WALKER_ThreadHeightCounterMaximum_start 136 +#define GEN9_GPGPU_WALKER_ThreadHeightCounterMaximum_start 136 +#define GEN8_GPGPU_WALKER_ThreadHeightCounterMaximum_start 136 +#define GEN75_GPGPU_WALKER_ThreadHeightCounterMaximum_start 72 +#define GEN7_GPGPU_WALKER_ThreadHeightCounterMaximum_start 72 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_ThreadHeightCounterMaximum_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 136; + case 10: return 136; + case 9: return 136; + case 8: return 136; + case 7: + if (devinfo->is_haswell) { + return 72; + } else { + return 72; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GPGPU_WALKER::Thread Width Counter Maximum */ + + +#define GEN11_GPGPU_WALKER_ThreadWidthCounterMaximum_bits 6 +#define GEN10_GPGPU_WALKER_ThreadWidthCounterMaximum_bits 6 +#define GEN9_GPGPU_WALKER_ThreadWidthCounterMaximum_bits 6 +#define GEN8_GPGPU_WALKER_ThreadWidthCounterMaximum_bits 6 +#define GEN75_GPGPU_WALKER_ThreadWidthCounterMaximum_bits 6 +#define GEN7_GPGPU_WALKER_ThreadWidthCounterMaximum_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_ThreadWidthCounterMaximum_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_GPGPU_WALKER_ThreadWidthCounterMaximum_start 128 +#define GEN10_GPGPU_WALKER_ThreadWidthCounterMaximum_start 128 +#define GEN9_GPGPU_WALKER_ThreadWidthCounterMaximum_start 128 +#define GEN8_GPGPU_WALKER_ThreadWidthCounterMaximum_start 128 +#define GEN75_GPGPU_WALKER_ThreadWidthCounterMaximum_start 64 +#define GEN7_GPGPU_WALKER_ThreadWidthCounterMaximum_start 64 + +static inline uint32_t ATTRIBUTE_PURE +GPGPU_WALKER_ThreadWidthCounterMaximum_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 128; + case 10: return 128; + case 9: return 128; + case 8: return 128; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GS_INVOCATION_COUNT */ + + +#define GEN11_GS_INVOCATION_COUNT_length 2 +#define GEN10_GS_INVOCATION_COUNT_length 2 +#define GEN9_GS_INVOCATION_COUNT_length 2 +#define GEN8_GS_INVOCATION_COUNT_length 2 +#define GEN75_GS_INVOCATION_COUNT_length 2 +#define GEN7_GS_INVOCATION_COUNT_length 2 + +static inline uint32_t ATTRIBUTE_PURE +GS_INVOCATION_COUNT_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GS_INVOCATION_COUNT::GS Invocation Count Report */ + + +#define GEN11_GS_INVOCATION_COUNT_GSInvocationCountReport_bits 64 +#define GEN10_GS_INVOCATION_COUNT_GSInvocationCountReport_bits 64 +#define GEN9_GS_INVOCATION_COUNT_GSInvocationCountReport_bits 64 +#define GEN8_GS_INVOCATION_COUNT_GSInvocationCountReport_bits 64 +#define GEN75_GS_INVOCATION_COUNT_GSInvocationCountReport_bits 64 +#define GEN7_GS_INVOCATION_COUNT_GSInvocationCountReport_bits 64 + +static inline uint32_t ATTRIBUTE_PURE +GS_INVOCATION_COUNT_GSInvocationCountReport_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_GS_INVOCATION_COUNT_GSInvocationCountReport_start 0 +#define GEN10_GS_INVOCATION_COUNT_GSInvocationCountReport_start 0 +#define GEN9_GS_INVOCATION_COUNT_GSInvocationCountReport_start 0 +#define GEN8_GS_INVOCATION_COUNT_GSInvocationCountReport_start 0 +#define GEN75_GS_INVOCATION_COUNT_GSInvocationCountReport_start 0 +#define GEN7_GS_INVOCATION_COUNT_GSInvocationCountReport_start 0 + +static inline uint32_t ATTRIBUTE_PURE +GS_INVOCATION_COUNT_GSInvocationCountReport_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GS_PRIMITIVES_COUNT */ + + +#define GEN11_GS_PRIMITIVES_COUNT_length 2 +#define GEN10_GS_PRIMITIVES_COUNT_length 2 +#define GEN9_GS_PRIMITIVES_COUNT_length 2 +#define GEN8_GS_PRIMITIVES_COUNT_length 2 +#define GEN75_GS_PRIMITIVES_COUNT_length 2 +#define GEN7_GS_PRIMITIVES_COUNT_length 2 + +static inline uint32_t ATTRIBUTE_PURE +GS_PRIMITIVES_COUNT_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GS_PRIMITIVES_COUNT::GS Primitives Count Report */ + + +#define GEN11_GS_PRIMITIVES_COUNT_GSPrimitivesCountReport_bits 64 +#define GEN10_GS_PRIMITIVES_COUNT_GSPrimitivesCountReport_bits 64 +#define GEN9_GS_PRIMITIVES_COUNT_GSPrimitivesCountReport_bits 64 +#define GEN8_GS_PRIMITIVES_COUNT_GSPrimitivesCountReport_bits 64 +#define GEN75_GS_PRIMITIVES_COUNT_GSPrimitivesCountReport_bits 64 +#define GEN7_GS_PRIMITIVES_COUNT_GSPrimitivesCountReport_bits 64 + +static inline uint32_t ATTRIBUTE_PURE +GS_PRIMITIVES_COUNT_GSPrimitivesCountReport_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_GS_PRIMITIVES_COUNT_GSPrimitivesCountReport_start 0 +#define GEN10_GS_PRIMITIVES_COUNT_GSPrimitivesCountReport_start 0 +#define GEN9_GS_PRIMITIVES_COUNT_GSPrimitivesCountReport_start 0 +#define GEN8_GS_PRIMITIVES_COUNT_GSPrimitivesCountReport_start 0 +#define GEN75_GS_PRIMITIVES_COUNT_GSPrimitivesCountReport_start 0 +#define GEN7_GS_PRIMITIVES_COUNT_GSPrimitivesCountReport_start 0 + +static inline uint32_t ATTRIBUTE_PURE +GS_PRIMITIVES_COUNT_GSPrimitivesCountReport_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GS_STATE */ + + +#define GEN5_GS_STATE_length 7 +#define GEN45_GS_STATE_length 7 +#define GEN4_GS_STATE_length 7 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 7; + case 4: + if (devinfo->is_g4x) { + return 7; + } else { + return 7; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GS_STATE::Binding Table Entry Count */ + + +#define GEN5_GS_STATE_BindingTableEntryCount_bits 8 +#define GEN45_GS_STATE_BindingTableEntryCount_bits 8 +#define GEN4_GS_STATE_BindingTableEntryCount_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_BindingTableEntryCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_GS_STATE_BindingTableEntryCount_start 50 +#define GEN45_GS_STATE_BindingTableEntryCount_start 50 +#define GEN4_GS_STATE_BindingTableEntryCount_start 50 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_BindingTableEntryCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 50; + case 4: + if (devinfo->is_g4x) { + return 50; + } else { + return 50; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GS_STATE::Constant URB Entry Read Length */ + + +#define GEN5_GS_STATE_ConstantURBEntryReadLength_bits 6 +#define GEN45_GS_STATE_ConstantURBEntryReadLength_bits 6 +#define GEN4_GS_STATE_ConstantURBEntryReadLength_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_ConstantURBEntryReadLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_GS_STATE_ConstantURBEntryReadLength_start 121 +#define GEN45_GS_STATE_ConstantURBEntryReadLength_start 121 +#define GEN4_GS_STATE_ConstantURBEntryReadLength_start 121 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_ConstantURBEntryReadLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 121; + case 4: + if (devinfo->is_g4x) { + return 121; + } else { + return 121; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GS_STATE::Constant URB Entry Read Offset */ + + +#define GEN5_GS_STATE_ConstantURBEntryReadOffset_bits 6 +#define GEN45_GS_STATE_ConstantURBEntryReadOffset_bits 6 +#define GEN4_GS_STATE_ConstantURBEntryReadOffset_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_ConstantURBEntryReadOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_GS_STATE_ConstantURBEntryReadOffset_start 114 +#define GEN45_GS_STATE_ConstantURBEntryReadOffset_start 114 +#define GEN4_GS_STATE_ConstantURBEntryReadOffset_start 114 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_ConstantURBEntryReadOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 114; + case 4: + if (devinfo->is_g4x) { + return 114; + } else { + return 114; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GS_STATE::Discard Adjacency */ + + +#define GEN45_GS_STATE_DiscardAdjacency_bits 1 +#define GEN4_GS_STATE_DiscardAdjacency_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_DiscardAdjacency_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN45_GS_STATE_DiscardAdjacency_start 221 +#define GEN4_GS_STATE_DiscardAdjacency_start 221 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_DiscardAdjacency_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 221; + } else { + return 221; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GS_STATE::Dispatch GRF Start Register For URB Data */ + + +#define GEN5_GS_STATE_DispatchGRFStartRegisterForURBData_bits 4 +#define GEN45_GS_STATE_DispatchGRFStartRegisterForURBData_bits 4 +#define GEN4_GS_STATE_DispatchGRFStartRegisterForURBData_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_DispatchGRFStartRegisterForURBData_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 4; + case 4: + if (devinfo->is_g4x) { + return 4; + } else { + return 4; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_GS_STATE_DispatchGRFStartRegisterForURBData_start 96 +#define GEN45_GS_STATE_DispatchGRFStartRegisterForURBData_start 96 +#define GEN4_GS_STATE_DispatchGRFStartRegisterForURBData_start 96 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_DispatchGRFStartRegisterForURBData_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 96; + case 4: + if (devinfo->is_g4x) { + return 96; + } else { + return 96; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GS_STATE::Floating Point Mode */ + + +#define GEN5_GS_STATE_FloatingPointMode_bits 1 +#define GEN45_GS_STATE_FloatingPointMode_bits 1 +#define GEN4_GS_STATE_FloatingPointMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_FloatingPointMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_GS_STATE_FloatingPointMode_start 48 +#define GEN45_GS_STATE_FloatingPointMode_start 48 +#define GEN4_GS_STATE_FloatingPointMode_start 48 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_FloatingPointMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 48; + case 4: + if (devinfo->is_g4x) { + return 48; + } else { + return 48; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GS_STATE::GRF Register Count */ + + +#define GEN5_GS_STATE_GRFRegisterCount_bits 3 +#define GEN45_GS_STATE_GRFRegisterCount_bits 3 +#define GEN4_GS_STATE_GRFRegisterCount_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_GRFRegisterCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_GS_STATE_GRFRegisterCount_start 1 +#define GEN45_GS_STATE_GRFRegisterCount_start 1 +#define GEN4_GS_STATE_GRFRegisterCount_start 1 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_GRFRegisterCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GS_STATE::GS Statistics Enable */ + + +#define GEN5_GS_STATE_GSStatisticsEnable_bits 1 +#define GEN45_GS_STATE_GSStatisticsEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_GSStatisticsEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_GS_STATE_GSStatisticsEnable_start 138 +#define GEN45_GS_STATE_GSStatisticsEnable_start 138 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_GSStatisticsEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 138; + case 4: + if (devinfo->is_g4x) { + return 138; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GS_STATE::Illegal Opcode Exception Enable */ + + +#define GEN5_GS_STATE_IllegalOpcodeExceptionEnable_bits 1 +#define GEN45_GS_STATE_IllegalOpcodeExceptionEnable_bits 1 +#define GEN4_GS_STATE_IllegalOpcodeExceptionEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_IllegalOpcodeExceptionEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_GS_STATE_IllegalOpcodeExceptionEnable_start 45 +#define GEN45_GS_STATE_IllegalOpcodeExceptionEnable_start 45 +#define GEN4_GS_STATE_IllegalOpcodeExceptionEnable_start 45 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_IllegalOpcodeExceptionEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 45; + case 4: + if (devinfo->is_g4x) { + return 45; + } else { + return 45; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GS_STATE::Kernel Start Pointer */ + + +#define GEN5_GS_STATE_KernelStartPointer_bits 26 +#define GEN45_GS_STATE_KernelStartPointer_bits 26 +#define GEN4_GS_STATE_KernelStartPointer_bits 26 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_KernelStartPointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 26; + case 4: + if (devinfo->is_g4x) { + return 26; + } else { + return 26; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_GS_STATE_KernelStartPointer_start 6 +#define GEN45_GS_STATE_KernelStartPointer_start 6 +#define GEN4_GS_STATE_KernelStartPointer_start 6 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_KernelStartPointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GS_STATE::Mask Stack Exception Enable */ + + +#define GEN5_GS_STATE_MaskStackExceptionEnable_bits 1 +#define GEN45_GS_STATE_MaskStackExceptionEnable_bits 1 +#define GEN4_GS_STATE_MaskStackExceptionEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_MaskStackExceptionEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_GS_STATE_MaskStackExceptionEnable_start 43 +#define GEN45_GS_STATE_MaskStackExceptionEnable_start 43 +#define GEN4_GS_STATE_MaskStackExceptionEnable_start 43 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_MaskStackExceptionEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 43; + case 4: + if (devinfo->is_g4x) { + return 43; + } else { + return 43; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GS_STATE::Maximum Number of Threads */ + + +#define GEN5_GS_STATE_MaximumNumberofThreads_bits 6 +#define GEN45_GS_STATE_MaximumNumberofThreads_bits 6 +#define GEN4_GS_STATE_MaximumNumberofThreads_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_MaximumNumberofThreads_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_GS_STATE_MaximumNumberofThreads_start 153 +#define GEN45_GS_STATE_MaximumNumberofThreads_start 153 +#define GEN4_GS_STATE_MaximumNumberofThreads_start 153 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_MaximumNumberofThreads_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 153; + case 4: + if (devinfo->is_g4x) { + return 153; + } else { + return 153; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GS_STATE::Maximum VPIndex */ + + +#define GEN5_GS_STATE_MaximumVPIndex_bits 4 +#define GEN45_GS_STATE_MaximumVPIndex_bits 4 +#define GEN4_GS_STATE_MaximumVPIndex_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_MaximumVPIndex_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 4; + case 4: + if (devinfo->is_g4x) { + return 4; + } else { + return 4; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_GS_STATE_MaximumVPIndex_start 192 +#define GEN45_GS_STATE_MaximumVPIndex_start 192 +#define GEN4_GS_STATE_MaximumVPIndex_start 192 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_MaximumVPIndex_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 192; + case 4: + if (devinfo->is_g4x) { + return 192; + } else { + return 192; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GS_STATE::Number of URB Entries */ + + +#define GEN5_GS_STATE_NumberofURBEntries_bits 8 +#define GEN45_GS_STATE_NumberofURBEntries_bits 8 +#define GEN4_GS_STATE_NumberofURBEntries_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_NumberofURBEntries_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_GS_STATE_NumberofURBEntries_start 139 +#define GEN45_GS_STATE_NumberofURBEntries_start 139 +#define GEN4_GS_STATE_NumberofURBEntries_start 139 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_NumberofURBEntries_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 139; + case 4: + if (devinfo->is_g4x) { + return 139; + } else { + return 139; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GS_STATE::Per-Thread Scratch Space */ + + +#define GEN5_GS_STATE_PerThreadScratchSpace_bits 4 +#define GEN45_GS_STATE_PerThreadScratchSpace_bits 4 +#define GEN4_GS_STATE_PerThreadScratchSpace_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_PerThreadScratchSpace_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 4; + case 4: + if (devinfo->is_g4x) { + return 4; + } else { + return 4; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_GS_STATE_PerThreadScratchSpace_start 64 +#define GEN45_GS_STATE_PerThreadScratchSpace_start 64 +#define GEN4_GS_STATE_PerThreadScratchSpace_start 64 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_PerThreadScratchSpace_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 64; + case 4: + if (devinfo->is_g4x) { + return 64; + } else { + return 64; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GS_STATE::Rendering Enable */ + + +#define GEN45_GS_STATE_RenderingEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_RenderingEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN45_GS_STATE_RenderingEnable_start 136 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_RenderingEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 136; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GS_STATE::Rendering Enabled */ + + +#define GEN5_GS_STATE_RenderingEnabled_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_RenderingEnabled_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_GS_STATE_RenderingEnabled_start 136 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_RenderingEnabled_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 136; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GS_STATE::Reorder Enable */ + + +#define GEN5_GS_STATE_ReorderEnable_bits 1 +#define GEN45_GS_STATE_ReorderEnable_bits 1 +#define GEN4_GS_STATE_ReorderEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_ReorderEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_GS_STATE_ReorderEnable_start 222 +#define GEN45_GS_STATE_ReorderEnable_start 222 +#define GEN4_GS_STATE_ReorderEnable_start 222 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_ReorderEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 222; + case 4: + if (devinfo->is_g4x) { + return 222; + } else { + return 222; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GS_STATE::SO Statistics Enable */ + + +#define GEN5_GS_STATE_SOStatisticsEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_SOStatisticsEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_GS_STATE_SOStatisticsEnable_start 137 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_SOStatisticsEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 137; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GS_STATE::Sampler Count */ + + +#define GEN5_GS_STATE_SamplerCount_bits 3 +#define GEN45_GS_STATE_SamplerCount_bits 3 +#define GEN4_GS_STATE_SamplerCount_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_SamplerCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_GS_STATE_SamplerCount_start 160 +#define GEN45_GS_STATE_SamplerCount_start 160 +#define GEN4_GS_STATE_SamplerCount_start 160 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_SamplerCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 160; + case 4: + if (devinfo->is_g4x) { + return 160; + } else { + return 160; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GS_STATE::Sampler State Pointer */ + + +#define GEN5_GS_STATE_SamplerStatePointer_bits 27 +#define GEN45_GS_STATE_SamplerStatePointer_bits 27 +#define GEN4_GS_STATE_SamplerStatePointer_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_SamplerStatePointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_GS_STATE_SamplerStatePointer_start 165 +#define GEN45_GS_STATE_SamplerStatePointer_start 165 +#define GEN4_GS_STATE_SamplerStatePointer_start 165 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_SamplerStatePointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 165; + case 4: + if (devinfo->is_g4x) { + return 165; + } else { + return 165; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GS_STATE::Scratch Space Base Pointer */ + + +#define GEN5_GS_STATE_ScratchSpaceBasePointer_bits 22 +#define GEN45_GS_STATE_ScratchSpaceBasePointer_bits 22 +#define GEN4_GS_STATE_ScratchSpaceBasePointer_bits 22 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_ScratchSpaceBasePointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 22; + case 4: + if (devinfo->is_g4x) { + return 22; + } else { + return 22; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_GS_STATE_ScratchSpaceBasePointer_start 74 +#define GEN45_GS_STATE_ScratchSpaceBasePointer_start 74 +#define GEN4_GS_STATE_ScratchSpaceBasePointer_start 74 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_ScratchSpaceBasePointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 74; + case 4: + if (devinfo->is_g4x) { + return 74; + } else { + return 74; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GS_STATE::Single Program Flow */ + + +#define GEN5_GS_STATE_SingleProgramFlow_bits 1 +#define GEN45_GS_STATE_SingleProgramFlow_bits 1 +#define GEN4_GS_STATE_SingleProgramFlow_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_SingleProgramFlow_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_GS_STATE_SingleProgramFlow_start 63 +#define GEN45_GS_STATE_SingleProgramFlow_start 63 +#define GEN4_GS_STATE_SingleProgramFlow_start 63 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_SingleProgramFlow_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 63; + case 4: + if (devinfo->is_g4x) { + return 63; + } else { + return 63; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GS_STATE::Software Exception Enable */ + + +#define GEN5_GS_STATE_SoftwareExceptionEnable_bits 1 +#define GEN45_GS_STATE_SoftwareExceptionEnable_bits 1 +#define GEN4_GS_STATE_SoftwareExceptionEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_SoftwareExceptionEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_GS_STATE_SoftwareExceptionEnable_start 39 +#define GEN45_GS_STATE_SoftwareExceptionEnable_start 39 +#define GEN4_GS_STATE_SoftwareExceptionEnable_start 39 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_SoftwareExceptionEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 39; + case 4: + if (devinfo->is_g4x) { + return 39; + } else { + return 39; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GS_STATE::URB Entry Allocation Size */ + + +#define GEN5_GS_STATE_URBEntryAllocationSize_bits 5 +#define GEN45_GS_STATE_URBEntryAllocationSize_bits 5 +#define GEN4_GS_STATE_URBEntryAllocationSize_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_URBEntryAllocationSize_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 5; + case 4: + if (devinfo->is_g4x) { + return 5; + } else { + return 5; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_GS_STATE_URBEntryAllocationSize_start 147 +#define GEN45_GS_STATE_URBEntryAllocationSize_start 147 +#define GEN4_GS_STATE_URBEntryAllocationSize_start 147 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_URBEntryAllocationSize_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 147; + case 4: + if (devinfo->is_g4x) { + return 147; + } else { + return 147; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GS_STATE::Vertex URB Entry Read Length */ + + +#define GEN5_GS_STATE_VertexURBEntryReadLength_bits 6 +#define GEN45_GS_STATE_VertexURBEntryReadLength_bits 6 +#define GEN4_GS_STATE_VertexURBEntryReadLength_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_VertexURBEntryReadLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_GS_STATE_VertexURBEntryReadLength_start 107 +#define GEN45_GS_STATE_VertexURBEntryReadLength_start 107 +#define GEN4_GS_STATE_VertexURBEntryReadLength_start 107 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_VertexURBEntryReadLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 107; + case 4: + if (devinfo->is_g4x) { + return 107; + } else { + return 107; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* GS_STATE::Vertex URB Entry Read Offset */ + + +#define GEN5_GS_STATE_VertexURBEntryReadOffset_bits 6 +#define GEN45_GS_STATE_VertexURBEntryReadOffset_bits 6 +#define GEN4_GS_STATE_VertexURBEntryReadOffset_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_VertexURBEntryReadOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_GS_STATE_VertexURBEntryReadOffset_start 100 +#define GEN45_GS_STATE_VertexURBEntryReadOffset_start 100 +#define GEN4_GS_STATE_VertexURBEntryReadOffset_start 100 + +static inline uint32_t ATTRIBUTE_PURE +GS_STATE_VertexURBEntryReadOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 100; + case 4: + if (devinfo->is_g4x) { + return 100; + } else { + return 100; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* HALF_SLICE_CHICKEN7 */ + + +#define GEN11_HALF_SLICE_CHICKEN7_length 1 + +static inline uint32_t ATTRIBUTE_PURE +HALF_SLICE_CHICKEN7_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* HALF_SLICE_CHICKEN7::Enabled Texel Offset Precision Fix */ + + +#define GEN11_HALF_SLICE_CHICKEN7_EnabledTexelOffsetPrecisionFix_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +HALF_SLICE_CHICKEN7_EnabledTexelOffsetPrecisionFix_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_HALF_SLICE_CHICKEN7_EnabledTexelOffsetPrecisionFix_start 1 + +static inline uint32_t ATTRIBUTE_PURE +HALF_SLICE_CHICKEN7_EnabledTexelOffsetPrecisionFix_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* HALF_SLICE_CHICKEN7::Enabled Texel Offset Precision Fix Mask */ + + +#define GEN11_HALF_SLICE_CHICKEN7_EnabledTexelOffsetPrecisionFixMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +HALF_SLICE_CHICKEN7_EnabledTexelOffsetPrecisionFixMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_HALF_SLICE_CHICKEN7_EnabledTexelOffsetPrecisionFixMask_start 17 + +static inline uint32_t ATTRIBUTE_PURE +HALF_SLICE_CHICKEN7_EnabledTexelOffsetPrecisionFixMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 17; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* HS_INVOCATION_COUNT */ + + +#define GEN11_HS_INVOCATION_COUNT_length 2 +#define GEN10_HS_INVOCATION_COUNT_length 2 +#define GEN9_HS_INVOCATION_COUNT_length 2 +#define GEN8_HS_INVOCATION_COUNT_length 2 +#define GEN75_HS_INVOCATION_COUNT_length 2 +#define GEN7_HS_INVOCATION_COUNT_length 2 + +static inline uint32_t ATTRIBUTE_PURE +HS_INVOCATION_COUNT_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* HS_INVOCATION_COUNT::HS Invocation Count Report */ + + +#define GEN11_HS_INVOCATION_COUNT_HSInvocationCountReport_bits 64 +#define GEN10_HS_INVOCATION_COUNT_HSInvocationCountReport_bits 64 +#define GEN9_HS_INVOCATION_COUNT_HSInvocationCountReport_bits 64 +#define GEN8_HS_INVOCATION_COUNT_HSInvocationCountReport_bits 64 +#define GEN75_HS_INVOCATION_COUNT_HSInvocationCountReport_bits 64 +#define GEN7_HS_INVOCATION_COUNT_HSInvocationCountReport_bits 64 + +static inline uint32_t ATTRIBUTE_PURE +HS_INVOCATION_COUNT_HSInvocationCountReport_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_HS_INVOCATION_COUNT_HSInvocationCountReport_start 0 +#define GEN10_HS_INVOCATION_COUNT_HSInvocationCountReport_start 0 +#define GEN9_HS_INVOCATION_COUNT_HSInvocationCountReport_start 0 +#define GEN8_HS_INVOCATION_COUNT_HSInvocationCountReport_start 0 +#define GEN75_HS_INVOCATION_COUNT_HSInvocationCountReport_start 0 +#define GEN7_HS_INVOCATION_COUNT_HSInvocationCountReport_start 0 + +static inline uint32_t ATTRIBUTE_PURE +HS_INVOCATION_COUNT_HSInvocationCountReport_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* IA_PRIMITIVES_COUNT */ + + +#define GEN11_IA_PRIMITIVES_COUNT_length 2 +#define GEN10_IA_PRIMITIVES_COUNT_length 2 +#define GEN9_IA_PRIMITIVES_COUNT_length 2 +#define GEN8_IA_PRIMITIVES_COUNT_length 2 +#define GEN75_IA_PRIMITIVES_COUNT_length 2 +#define GEN7_IA_PRIMITIVES_COUNT_length 2 + +static inline uint32_t ATTRIBUTE_PURE +IA_PRIMITIVES_COUNT_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* IA_PRIMITIVES_COUNT::IA Primitives Count Report */ + + +#define GEN11_IA_PRIMITIVES_COUNT_IAPrimitivesCountReport_bits 64 +#define GEN10_IA_PRIMITIVES_COUNT_IAPrimitivesCountReport_bits 64 +#define GEN9_IA_PRIMITIVES_COUNT_IAPrimitivesCountReport_bits 64 +#define GEN8_IA_PRIMITIVES_COUNT_IAPrimitivesCountReport_bits 64 +#define GEN75_IA_PRIMITIVES_COUNT_IAPrimitivesCountReport_bits 64 +#define GEN7_IA_PRIMITIVES_COUNT_IAPrimitivesCountReport_bits 64 + +static inline uint32_t ATTRIBUTE_PURE +IA_PRIMITIVES_COUNT_IAPrimitivesCountReport_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_IA_PRIMITIVES_COUNT_IAPrimitivesCountReport_start 0 +#define GEN10_IA_PRIMITIVES_COUNT_IAPrimitivesCountReport_start 0 +#define GEN9_IA_PRIMITIVES_COUNT_IAPrimitivesCountReport_start 0 +#define GEN8_IA_PRIMITIVES_COUNT_IAPrimitivesCountReport_start 0 +#define GEN75_IA_PRIMITIVES_COUNT_IAPrimitivesCountReport_start 0 +#define GEN7_IA_PRIMITIVES_COUNT_IAPrimitivesCountReport_start 0 + +static inline uint32_t ATTRIBUTE_PURE +IA_PRIMITIVES_COUNT_IAPrimitivesCountReport_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* IA_VERTICES_COUNT */ + + +#define GEN11_IA_VERTICES_COUNT_length 2 +#define GEN10_IA_VERTICES_COUNT_length 2 +#define GEN9_IA_VERTICES_COUNT_length 2 +#define GEN8_IA_VERTICES_COUNT_length 2 +#define GEN75_IA_VERTICES_COUNT_length 2 +#define GEN7_IA_VERTICES_COUNT_length 2 + +static inline uint32_t ATTRIBUTE_PURE +IA_VERTICES_COUNT_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* IA_VERTICES_COUNT::IA Vertices Count Report */ + + +#define GEN11_IA_VERTICES_COUNT_IAVerticesCountReport_bits 64 +#define GEN10_IA_VERTICES_COUNT_IAVerticesCountReport_bits 64 +#define GEN9_IA_VERTICES_COUNT_IAVerticesCountReport_bits 64 +#define GEN8_IA_VERTICES_COUNT_IAVerticesCountReport_bits 64 +#define GEN75_IA_VERTICES_COUNT_IAVerticesCountReport_bits 64 +#define GEN7_IA_VERTICES_COUNT_IAVerticesCountReport_bits 64 + +static inline uint32_t ATTRIBUTE_PURE +IA_VERTICES_COUNT_IAVerticesCountReport_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_IA_VERTICES_COUNT_IAVerticesCountReport_start 0 +#define GEN10_IA_VERTICES_COUNT_IAVerticesCountReport_start 0 +#define GEN9_IA_VERTICES_COUNT_IAVerticesCountReport_start 0 +#define GEN8_IA_VERTICES_COUNT_IAVerticesCountReport_start 0 +#define GEN75_IA_VERTICES_COUNT_IAVerticesCountReport_start 0 +#define GEN7_IA_VERTICES_COUNT_IAVerticesCountReport_start 0 + +static inline uint32_t ATTRIBUTE_PURE +IA_VERTICES_COUNT_IAVerticesCountReport_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1 */ + + +#define GEN11_INSTDONE_1_length 1 +#define GEN10_INSTDONE_1_length 1 +#define GEN9_INSTDONE_1_length 1 +#define GEN8_INSTDONE_1_length 1 +#define GEN75_INSTDONE_1_length 1 +#define GEN7_INSTDONE_1_length 1 +#define GEN6_INSTDONE_1_length 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::AVS Done */ + + +#define GEN6_INSTDONE_1_AVSDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_AVSDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_1_AVSDone_start 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_AVSDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::CL Done */ + + +#define GEN11_INSTDONE_1_CLDone_bits 1 +#define GEN10_INSTDONE_1_CLDone_bits 1 +#define GEN9_INSTDONE_1_CLDone_bits 1 +#define GEN8_INSTDONE_1_CLDone_bits 1 +#define GEN75_INSTDONE_1_CLDone_bits 1 +#define GEN7_INSTDONE_1_CLDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_CLDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INSTDONE_1_CLDone_start 8 +#define GEN10_INSTDONE_1_CLDone_start 8 +#define GEN9_INSTDONE_1_CLDone_start 8 +#define GEN8_INSTDONE_1_CLDone_start 8 +#define GEN75_INSTDONE_1_CLDone_start 8 +#define GEN7_INSTDONE_1_CLDone_start 8 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_CLDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::CS Done */ + + +#define GEN11_INSTDONE_1_CSDone_bits 1 +#define GEN10_INSTDONE_1_CSDone_bits 1 +#define GEN9_INSTDONE_1_CSDone_bits 1 +#define GEN8_INSTDONE_1_CSDone_bits 1 +#define GEN75_INSTDONE_1_CSDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_CSDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INSTDONE_1_CSDone_start 21 +#define GEN10_INSTDONE_1_CSDone_start 21 +#define GEN9_INSTDONE_1_CSDone_start 21 +#define GEN8_INSTDONE_1_CSDone_start 21 +#define GEN75_INSTDONE_1_CSDone_start 21 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_CSDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 21; + case 10: return 21; + case 9: return 21; + case 8: return 21; + case 7: + if (devinfo->is_haswell) { + return 21; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::DS Done */ + + +#define GEN11_INSTDONE_1_DSDone_bits 1 +#define GEN10_INSTDONE_1_DSDone_bits 1 +#define GEN9_INSTDONE_1_DSDone_bits 1 +#define GEN8_INSTDONE_1_DSDone_bits 1 +#define GEN75_INSTDONE_1_DSDone_bits 1 +#define GEN7_INSTDONE_1_DSDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_DSDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INSTDONE_1_DSDone_start 5 +#define GEN10_INSTDONE_1_DSDone_start 5 +#define GEN9_INSTDONE_1_DSDone_start 5 +#define GEN8_INSTDONE_1_DSDone_start 5 +#define GEN75_INSTDONE_1_DSDone_start 5 +#define GEN7_INSTDONE_1_DSDone_start 5 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_DSDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 5; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::EU00 Done */ + + +#define GEN6_INSTDONE_1_EU00Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_EU00Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_1_EU00Done_start 16 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_EU00Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::EU01 Done */ + + +#define GEN6_INSTDONE_1_EU01Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_EU01Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_1_EU01Done_start 17 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_EU01Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 17; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::EU02 Done */ + + +#define GEN6_INSTDONE_1_EU02Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_EU02Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_1_EU02Done_start 18 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_EU02Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 18; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::EU10 Done */ + + +#define GEN6_INSTDONE_1_EU10Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_EU10Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_1_EU10Done_start 20 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_EU10Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 20; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::EU11 Done */ + + +#define GEN6_INSTDONE_1_EU11Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_EU11Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_1_EU11Done_start 21 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_EU11Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 21; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::EU12 Done */ + + +#define GEN6_INSTDONE_1_EU12Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_EU12Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_1_EU12Done_start 22 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_EU12Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 22; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::EU20 Done */ + + +#define GEN6_INSTDONE_1_EU20Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_EU20Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_1_EU20Done_start 24 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_EU20Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 24; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::EU21 Done */ + + +#define GEN6_INSTDONE_1_EU21Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_EU21Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_1_EU21Done_start 25 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_EU21Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 25; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::EU22 Done */ + + +#define GEN6_INSTDONE_1_EU22Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_EU22Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_1_EU22Done_start 26 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_EU22Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 26; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::EU30 Done */ + + +#define GEN6_INSTDONE_1_EU30Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_EU30Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_1_EU30Done_start 28 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_EU30Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 28; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::EU31 Done */ + + +#define GEN6_INSTDONE_1_EU31Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_EU31Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_1_EU31Done_start 29 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_EU31Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::EU32 Done */ + + +#define GEN6_INSTDONE_1_EU32Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_EU32Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_1_EU32Done_start 30 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_EU32Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 30; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::GAFM Done */ + + +#define GEN11_INSTDONE_1_GAFMDone_bits 1 +#define GEN10_INSTDONE_1_GAFMDone_bits 1 +#define GEN9_INSTDONE_1_GAFMDone_bits 1 +#define GEN8_INSTDONE_1_GAFMDone_bits 1 +#define GEN75_INSTDONE_1_GAFMDone_bits 1 +#define GEN7_INSTDONE_1_GAFMDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_GAFMDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INSTDONE_1_GAFMDone_start 18 +#define GEN10_INSTDONE_1_GAFMDone_start 18 +#define GEN9_INSTDONE_1_GAFMDone_start 18 +#define GEN8_INSTDONE_1_GAFMDone_start 18 +#define GEN75_INSTDONE_1_GAFMDone_start 18 +#define GEN7_INSTDONE_1_GAFMDone_start 18 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_GAFMDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 18; + case 10: return 18; + case 9: return 18; + case 8: return 18; + case 7: + if (devinfo->is_haswell) { + return 18; + } else { + return 18; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::GAFS Done */ + + +#define GEN11_INSTDONE_1_GAFSDone_bits 1 +#define GEN10_INSTDONE_1_GAFSDone_bits 1 +#define GEN9_INSTDONE_1_GAFSDone_bits 1 +#define GEN8_INSTDONE_1_GAFSDone_bits 1 +#define GEN75_INSTDONE_1_GAFSDone_bits 1 +#define GEN7_INSTDONE_1_GAFSDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_GAFSDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INSTDONE_1_GAFSDone_start 15 +#define GEN10_INSTDONE_1_GAFSDone_start 15 +#define GEN9_INSTDONE_1_GAFSDone_start 15 +#define GEN8_INSTDONE_1_GAFSDone_start 15 +#define GEN75_INSTDONE_1_GAFSDone_start 15 +#define GEN7_INSTDONE_1_GAFSDone_start 15 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_GAFSDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 15; + case 10: return 15; + case 9: return 15; + case 8: return 15; + case 7: + if (devinfo->is_haswell) { + return 15; + } else { + return 15; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::GAM Done */ + + +#define GEN11_INSTDONE_1_GAMDone_bits 1 +#define GEN10_INSTDONE_1_GAMDone_bits 1 +#define GEN9_INSTDONE_1_GAMDone_bits 1 +#define GEN8_INSTDONE_1_GAMDone_bits 1 +#define GEN75_INSTDONE_1_GAMDone_bits 1 +#define GEN7_INSTDONE_1_GAMDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_GAMDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INSTDONE_1_GAMDone_start 19 +#define GEN10_INSTDONE_1_GAMDone_start 19 +#define GEN9_INSTDONE_1_GAMDone_start 19 +#define GEN8_INSTDONE_1_GAMDone_start 19 +#define GEN75_INSTDONE_1_GAMDone_start 19 +#define GEN7_INSTDONE_1_GAMDone_start 19 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_GAMDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 19; + case 10: return 19; + case 9: return 19; + case 8: return 19; + case 7: + if (devinfo->is_haswell) { + return 19; + } else { + return 19; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::GS Done */ + + +#define GEN11_INSTDONE_1_GSDone_bits 1 +#define GEN10_INSTDONE_1_GSDone_bits 1 +#define GEN9_INSTDONE_1_GSDone_bits 1 +#define GEN8_INSTDONE_1_GSDone_bits 1 +#define GEN75_INSTDONE_1_GSDone_bits 1 +#define GEN7_INSTDONE_1_GSDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_GSDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INSTDONE_1_GSDone_start 6 +#define GEN10_INSTDONE_1_GSDone_start 6 +#define GEN9_INSTDONE_1_GSDone_start 6 +#define GEN8_INSTDONE_1_GSDone_start 6 +#define GEN75_INSTDONE_1_GSDone_start 6 +#define GEN7_INSTDONE_1_GSDone_start 6 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_GSDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::GW Done */ + + +#define GEN6_INSTDONE_1_GWDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_GWDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_1_GWDone_start 3 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_GWDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::HIZ Done */ + + +#define GEN6_INSTDONE_1_HIZDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_HIZDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_1_HIZDone_start 2 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_HIZDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::HS Done */ + + +#define GEN11_INSTDONE_1_HSDone_bits 1 +#define GEN10_INSTDONE_1_HSDone_bits 1 +#define GEN9_INSTDONE_1_HSDone_bits 1 +#define GEN8_INSTDONE_1_HSDone_bits 1 +#define GEN75_INSTDONE_1_HSDone_bits 1 +#define GEN7_INSTDONE_1_HSDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_HSDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INSTDONE_1_HSDone_start 3 +#define GEN10_INSTDONE_1_HSDone_start 3 +#define GEN9_INSTDONE_1_HSDone_start 3 +#define GEN8_INSTDONE_1_HSDone_start 3 +#define GEN75_INSTDONE_1_HSDone_start 3 +#define GEN7_INSTDONE_1_HSDone_start 3 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_HSDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::IC0 Done */ + + +#define GEN6_INSTDONE_1_IC0Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_IC0Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_1_IC0Done_start 12 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_IC0Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 12; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::IC1 Done */ + + +#define GEN6_INSTDONE_1_IC1Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_IC1Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_1_IC1Done_start 13 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_IC1Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 13; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::IC2 Done */ + + +#define GEN6_INSTDONE_1_IC2Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_IC2Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_1_IC2Done_start 14 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_IC2Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 14; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::IC3 Done */ + + +#define GEN6_INSTDONE_1_IC3Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_IC3Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_1_IC3Done_start 15 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_IC3Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 15; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::IEF Done */ + + +#define GEN6_INSTDONE_1_IEFDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_IEFDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_1_IEFDone_start 8 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_IEFDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::ISC1/0 Done */ + + +#define GEN6_INSTDONE_1_ISC10Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_ISC10Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_1_ISC10Done_start 11 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_ISC10Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 11; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::ISC2/3 Done */ + + +#define GEN6_INSTDONE_1_ISC23Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_ISC23Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_1_ISC23Done_start 10 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_ISC23Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 10; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::MA0 Done */ + + +#define GEN6_INSTDONE_1_MA0Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_MA0Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_1_MA0Done_start 19 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_MA0Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 19; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::MA1 Done */ + + +#define GEN6_INSTDONE_1_MA1Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_MA1Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_1_MA1Done_start 23 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_MA1Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 23; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::MA2 Done */ + + +#define GEN6_INSTDONE_1_MA2Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_MA2Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_1_MA2Done_start 27 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_MA2Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::MA3 Done */ + + +#define GEN6_INSTDONE_1_MA3Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_MA3Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_1_MA3Done_start 31 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_MA3Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 31; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::PRB0 Ring Enable */ + + +#define GEN11_INSTDONE_1_PRB0RingEnable_bits 1 +#define GEN10_INSTDONE_1_PRB0RingEnable_bits 1 +#define GEN9_INSTDONE_1_PRB0RingEnable_bits 1 +#define GEN8_INSTDONE_1_PRB0RingEnable_bits 1 +#define GEN75_INSTDONE_1_PRB0RingEnable_bits 1 +#define GEN7_INSTDONE_1_PRB0RingEnable_bits 1 +#define GEN6_INSTDONE_1_PRB0RingEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_PRB0RingEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INSTDONE_1_PRB0RingEnable_start 0 +#define GEN10_INSTDONE_1_PRB0RingEnable_start 0 +#define GEN9_INSTDONE_1_PRB0RingEnable_start 0 +#define GEN8_INSTDONE_1_PRB0RingEnable_start 0 +#define GEN75_INSTDONE_1_PRB0RingEnable_start 0 +#define GEN7_INSTDONE_1_PRB0RingEnable_start 0 +#define GEN6_INSTDONE_1_PRB0RingEnable_start 0 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_PRB0RingEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::RCCFBC CS Done */ + + +#define GEN11_INSTDONE_1_RCCFBCCSDone_bits 1 +#define GEN10_INSTDONE_1_RCCFBCCSDone_bits 1 +#define GEN9_INSTDONE_1_RCCFBCCSDone_bits 1 +#define GEN8_INSTDONE_1_RCCFBCCSDone_bits 1 +#define GEN75_INSTDONE_1_RCCFBCCSDone_bits 1 +#define GEN7_INSTDONE_1_RCCFBCCSDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_RCCFBCCSDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INSTDONE_1_RCCFBCCSDone_start 23 +#define GEN10_INSTDONE_1_RCCFBCCSDone_start 23 +#define GEN9_INSTDONE_1_RCCFBCCSDone_start 23 +#define GEN8_INSTDONE_1_RCCFBCCSDone_start 23 +#define GEN75_INSTDONE_1_RCCFBCCSDone_start 23 +#define GEN7_INSTDONE_1_RCCFBCCSDone_start 23 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_RCCFBCCSDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 23; + } else { + return 23; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::RS Done */ + + +#define GEN11_INSTDONE_1_RSDone_bits 1 +#define GEN10_INSTDONE_1_RSDone_bits 1 +#define GEN9_INSTDONE_1_RSDone_bits 1 +#define GEN8_INSTDONE_1_RSDone_bits 1 +#define GEN75_INSTDONE_1_RSDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_RSDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INSTDONE_1_RSDone_start 20 +#define GEN10_INSTDONE_1_RSDone_start 20 +#define GEN9_INSTDONE_1_RSDone_start 20 +#define GEN8_INSTDONE_1_RSDone_start 20 +#define GEN75_INSTDONE_1_RSDone_start 20 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_RSDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 20; + case 10: return 20; + case 9: return 20; + case 8: return 20; + case 7: + if (devinfo->is_haswell) { + return 20; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::SDE Done */ + + +#define GEN11_INSTDONE_1_SDEDone_bits 1 +#define GEN10_INSTDONE_1_SDEDone_bits 1 +#define GEN9_INSTDONE_1_SDEDone_bits 1 +#define GEN8_INSTDONE_1_SDEDone_bits 1 +#define GEN75_INSTDONE_1_SDEDone_bits 1 +#define GEN7_INSTDONE_1_SDEDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_SDEDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INSTDONE_1_SDEDone_start 22 +#define GEN10_INSTDONE_1_SDEDone_start 22 +#define GEN9_INSTDONE_1_SDEDone_start 22 +#define GEN8_INSTDONE_1_SDEDone_start 22 +#define GEN75_INSTDONE_1_SDEDone_start 22 +#define GEN7_INSTDONE_1_SDEDone_start 22 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_SDEDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 22; + case 10: return 22; + case 9: return 22; + case 8: return 22; + case 7: + if (devinfo->is_haswell) { + return 22; + } else { + return 22; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::SF Done */ + + +#define GEN11_INSTDONE_1_SFDone_bits 1 +#define GEN10_INSTDONE_1_SFDone_bits 1 +#define GEN9_INSTDONE_1_SFDone_bits 1 +#define GEN8_INSTDONE_1_SFDone_bits 1 +#define GEN75_INSTDONE_1_SFDone_bits 1 +#define GEN7_INSTDONE_1_SFDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_SFDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INSTDONE_1_SFDone_start 9 +#define GEN10_INSTDONE_1_SFDone_start 9 +#define GEN9_INSTDONE_1_SFDone_start 9 +#define GEN8_INSTDONE_1_SFDone_start 9 +#define GEN75_INSTDONE_1_SFDone_start 9 +#define GEN7_INSTDONE_1_SFDone_start 9 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_SFDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 9; + case 10: return 9; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 9; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::SOL Done */ + + +#define GEN11_INSTDONE_1_SOLDone_bits 1 +#define GEN10_INSTDONE_1_SOLDone_bits 1 +#define GEN9_INSTDONE_1_SOLDone_bits 1 +#define GEN8_INSTDONE_1_SOLDone_bits 1 +#define GEN75_INSTDONE_1_SOLDone_bits 1 +#define GEN7_INSTDONE_1_SOLDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_SOLDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INSTDONE_1_SOLDone_start 7 +#define GEN10_INSTDONE_1_SOLDone_start 7 +#define GEN9_INSTDONE_1_SOLDone_start 7 +#define GEN8_INSTDONE_1_SOLDone_start 7 +#define GEN75_INSTDONE_1_SOLDone_start 7 +#define GEN7_INSTDONE_1_SOLDone_start 7 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_SOLDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 7; + } else { + return 7; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::SVG Done */ + + +#define GEN11_INSTDONE_1_SVGDone_bits 1 +#define GEN10_INSTDONE_1_SVGDone_bits 1 +#define GEN9_INSTDONE_1_SVGDone_bits 1 +#define GEN8_INSTDONE_1_SVGDone_bits 1 +#define GEN75_INSTDONE_1_SVGDone_bits 1 +#define GEN7_INSTDONE_1_SVGDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_SVGDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INSTDONE_1_SVGDone_start 14 +#define GEN10_INSTDONE_1_SVGDone_start 14 +#define GEN9_INSTDONE_1_SVGDone_start 14 +#define GEN8_INSTDONE_1_SVGDone_start 14 +#define GEN75_INSTDONE_1_SVGDone_start 14 +#define GEN7_INSTDONE_1_SVGDone_start 14 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_SVGDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 14; + case 10: return 14; + case 9: return 14; + case 8: return 14; + case 7: + if (devinfo->is_haswell) { + return 14; + } else { + return 14; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::TD Done */ + + +#define GEN6_INSTDONE_1_TDDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_TDDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_1_TDDone_start 6 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_TDDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 6; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::TDG Done */ + + +#define GEN10_INSTDONE_1_TDGDone_bits 1 +#define GEN9_INSTDONE_1_TDGDone_bits 1 +#define GEN8_INSTDONE_1_TDGDone_bits 1 +#define GEN75_INSTDONE_1_TDGDone_bits 1 +#define GEN7_INSTDONE_1_TDGDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_TDGDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_INSTDONE_1_TDGDone_start 12 +#define GEN9_INSTDONE_1_TDGDone_start 12 +#define GEN8_INSTDONE_1_TDGDone_start 12 +#define GEN75_INSTDONE_1_TDGDone_start 12 +#define GEN7_INSTDONE_1_TDGDone_start 12 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_TDGDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 12; + case 9: return 12; + case 8: return 12; + case 7: + if (devinfo->is_haswell) { + return 12; + } else { + return 12; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::TDG0 Done */ + + +#define GEN11_INSTDONE_1_TDG0Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_TDG0Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INSTDONE_1_TDG0Done_start 12 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_TDG0Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 12; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::TDG1 Done */ + + +#define GEN11_INSTDONE_1_TDG1Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_TDG1Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INSTDONE_1_TDG1Done_start 11 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_TDG1Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::TE Done */ + + +#define GEN11_INSTDONE_1_TEDone_bits 1 +#define GEN10_INSTDONE_1_TEDone_bits 1 +#define GEN9_INSTDONE_1_TEDone_bits 1 +#define GEN8_INSTDONE_1_TEDone_bits 1 +#define GEN75_INSTDONE_1_TEDone_bits 1 +#define GEN7_INSTDONE_1_TEDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_TEDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INSTDONE_1_TEDone_start 4 +#define GEN10_INSTDONE_1_TEDone_start 4 +#define GEN9_INSTDONE_1_TEDone_start 4 +#define GEN8_INSTDONE_1_TEDone_start 4 +#define GEN75_INSTDONE_1_TEDone_start 4 +#define GEN7_INSTDONE_1_TEDone_start 4 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_TEDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::TS Done */ + + +#define GEN6_INSTDONE_1_TSDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_TSDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_1_TSDone_start 4 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_TSDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::TSG Done */ + + +#define GEN10_INSTDONE_1_TSGDone_bits 1 +#define GEN9_INSTDONE_1_TSGDone_bits 1 +#define GEN8_INSTDONE_1_TSGDone_bits 1 +#define GEN75_INSTDONE_1_TSGDone_bits 1 +#define GEN7_INSTDONE_1_TSGDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_TSGDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_INSTDONE_1_TSGDone_start 17 +#define GEN9_INSTDONE_1_TSGDone_start 17 +#define GEN8_INSTDONE_1_TSGDone_start 17 +#define GEN75_INSTDONE_1_TSGDone_start 17 +#define GEN7_INSTDONE_1_TSGDone_start 17 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_TSGDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 17; + case 9: return 17; + case 8: return 17; + case 7: + if (devinfo->is_haswell) { + return 17; + } else { + return 17; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::TSG0 Done */ + + +#define GEN11_INSTDONE_1_TSG0Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_TSG0Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INSTDONE_1_TSG0Done_start 17 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_TSG0Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 17; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::TSG1 Done */ + + +#define GEN11_INSTDONE_1_TSG1Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_TSG1Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INSTDONE_1_TSG1Done_start 24 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_TSG1Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::URBM Done */ + + +#define GEN11_INSTDONE_1_URBMDone_bits 1 +#define GEN10_INSTDONE_1_URBMDone_bits 1 +#define GEN9_INSTDONE_1_URBMDone_bits 1 +#define GEN8_INSTDONE_1_URBMDone_bits 1 +#define GEN75_INSTDONE_1_URBMDone_bits 1 +#define GEN7_INSTDONE_1_URBMDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_URBMDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INSTDONE_1_URBMDone_start 13 +#define GEN10_INSTDONE_1_URBMDone_start 13 +#define GEN9_INSTDONE_1_URBMDone_start 13 +#define GEN8_INSTDONE_1_URBMDone_start 13 +#define GEN75_INSTDONE_1_URBMDone_start 13 +#define GEN7_INSTDONE_1_URBMDone_start 13 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_URBMDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 13; + case 10: return 13; + case 9: return 13; + case 8: return 13; + case 7: + if (devinfo->is_haswell) { + return 13; + } else { + return 13; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::VFE Done */ + + +#define GEN11_INSTDONE_1_VFEDone_bits 1 +#define GEN10_INSTDONE_1_VFEDone_bits 1 +#define GEN9_INSTDONE_1_VFEDone_bits 1 +#define GEN8_INSTDONE_1_VFEDone_bits 1 +#define GEN75_INSTDONE_1_VFEDone_bits 1 +#define GEN7_INSTDONE_1_VFEDone_bits 1 +#define GEN6_INSTDONE_1_VFEDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_VFEDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INSTDONE_1_VFEDone_start 16 +#define GEN10_INSTDONE_1_VFEDone_start 16 +#define GEN9_INSTDONE_1_VFEDone_start 16 +#define GEN8_INSTDONE_1_VFEDone_start 16 +#define GEN75_INSTDONE_1_VFEDone_start 16 +#define GEN7_INSTDONE_1_VFEDone_start 16 +#define GEN6_INSTDONE_1_VFEDone_start 7 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_VFEDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 7; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::VFG Done */ + + +#define GEN11_INSTDONE_1_VFGDone_bits 1 +#define GEN10_INSTDONE_1_VFGDone_bits 1 +#define GEN9_INSTDONE_1_VFGDone_bits 1 +#define GEN8_INSTDONE_1_VFGDone_bits 1 +#define GEN75_INSTDONE_1_VFGDone_bits 1 +#define GEN7_INSTDONE_1_VFGDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_VFGDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INSTDONE_1_VFGDone_start 1 +#define GEN10_INSTDONE_1_VFGDone_start 1 +#define GEN9_INSTDONE_1_VFGDone_start 1 +#define GEN8_INSTDONE_1_VFGDone_start 1 +#define GEN75_INSTDONE_1_VFGDone_start 1 +#define GEN7_INSTDONE_1_VFGDone_start 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_VFGDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::VS Done */ + + +#define GEN11_INSTDONE_1_VSDone_bits 1 +#define GEN10_INSTDONE_1_VSDone_bits 1 +#define GEN9_INSTDONE_1_VSDone_bits 1 +#define GEN8_INSTDONE_1_VSDone_bits 1 +#define GEN75_INSTDONE_1_VSDone_bits 1 +#define GEN7_INSTDONE_1_VSDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_VSDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INSTDONE_1_VSDone_start 2 +#define GEN10_INSTDONE_1_VSDone_start 2 +#define GEN9_INSTDONE_1_VSDone_start 2 +#define GEN8_INSTDONE_1_VSDone_start 2 +#define GEN75_INSTDONE_1_VSDone_start 2 +#define GEN7_INSTDONE_1_VSDone_start 2 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_VSDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_1::VSC Done */ + + +#define GEN6_INSTDONE_1_VSCDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_VSCDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_1_VSCDone_start 9 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_1_VSCDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 9; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_2 */ + + +#define GEN6_INSTDONE_2_length 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_2::CL Done */ + + +#define GEN6_INSTDONE_2_CLDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_CLDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_2_CLDone_start 3 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_CLDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_2::CS Done */ + + +#define GEN6_INSTDONE_2_CSDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_CSDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_2_CSDone_start 30 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_CSDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 30; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_2::DAP Done */ + + +#define GEN6_INSTDONE_2_DAPDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_DAPDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_2_DAPDone_start 19 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_DAPDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 19; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_2::DG Done */ + + +#define GEN6_INSTDONE_2_DGDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_DGDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_2_DGDone_start 9 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_DGDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 9; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_2::DM Done */ + + +#define GEN6_INSTDONE_2_DMDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_DMDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_2_DMDone_start 11 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_DMDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 11; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_2::FL Done */ + + +#define GEN6_INSTDONE_2_FLDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_FLDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_2_FLDone_start 13 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_FLDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 13; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_2::FT Done */ + + +#define GEN6_INSTDONE_2_FTDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_FTDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_2_FTDone_start 10 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_FTDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 10; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_2::GAM Done */ + + +#define GEN6_INSTDONE_2_GAMDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_GAMDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_2_GAMDone_start 31 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_GAMDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 31; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_2::GS Done */ + + +#define GEN6_INSTDONE_2_GSDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_GSDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_2_GSDone_start 2 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_GSDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_2::ISC Done */ + + +#define GEN6_INSTDONE_2_ISCDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_ISCDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_2_ISCDone_start 25 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_ISCDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 25; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_2::IZ Done */ + + +#define GEN6_INSTDONE_2_IZDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_IZDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_2_IZDone_start 17 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_IZDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 17; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_2::MT Done */ + + +#define GEN6_INSTDONE_2_MTDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_MTDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_2_MTDone_start 24 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_MTDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 24; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_2::PL Done */ + + +#define GEN6_INSTDONE_2_PLDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_PLDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_2_PLDone_start 6 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_PLDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 6; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_2::PSD Done */ + + +#define GEN6_INSTDONE_2_PSDDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_PSDDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_2_PSDDone_start 18 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_PSDDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 18; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_2::QC Done */ + + +#define GEN6_INSTDONE_2_QCDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_QCDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_2_QCDone_start 14 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_QCDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 14; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_2::RCC Done */ + + +#define GEN6_INSTDONE_2_RCCDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_RCCDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_2_RCCDone_start 27 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_RCCDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_2::RCPBE Done */ + + +#define GEN6_INSTDONE_2_RCPBEDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_RCPBEDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_2_RCPBEDone_start 22 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_RCPBEDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 22; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_2::RCPFE Done */ + + +#define GEN6_INSTDONE_2_RCPFEDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_RCPFEDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_2_RCPFEDone_start 23 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_RCPFEDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 23; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_2::RCZ Done */ + + +#define GEN6_INSTDONE_2_RCZDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_RCZDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_2_RCZDone_start 20 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_RCZDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 20; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_2::SC Done */ + + +#define GEN6_INSTDONE_2_SCDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_SCDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_2_SCDone_start 12 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_SCDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 12; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_2::SF Done */ + + +#define GEN6_INSTDONE_2_SFDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_SFDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_2_SFDone_start 4 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_SFDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_2::SI Done */ + + +#define GEN6_INSTDONE_2_SIDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_SIDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_2_SIDone_start 8 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_SIDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_2::SO Done */ + + +#define GEN6_INSTDONE_2_SODone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_SODone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_2_SODone_start 7 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_SODone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 7; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_2::SVG Done */ + + +#define GEN6_INSTDONE_2_SVGDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_SVGDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_2_SVGDone_start 26 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_SVGDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 26; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_2::SVRW Done */ + + +#define GEN6_INSTDONE_2_SVRWDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_SVRWDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_2_SVRWDone_start 28 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_SVRWDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 28; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_2::SVSM Done */ + + +#define GEN6_INSTDONE_2_SVSMDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_SVSMDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_2_SVSMDone_start 15 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_SVSMDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 15; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_2::VDI Done */ + + +#define GEN6_INSTDONE_2_VDIDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_VDIDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_2_VDIDone_start 21 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_VDIDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 21; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_2::VF Done */ + + +#define GEN6_INSTDONE_2_VFDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_VFDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_2_VFDone_start 0 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_VFDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_2::VME Done */ + + +#define GEN6_INSTDONE_2_VMEDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_VMEDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_2_VMEDone_start 5 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_VMEDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 5; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_2::VS0 Done */ + + +#define GEN6_INSTDONE_2_VS0Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_VS0Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_2_VS0Done_start 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_VS0Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_2::WMBE Done */ + + +#define GEN6_INSTDONE_2_WMBEDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_WMBEDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_2_WMBEDone_start 29 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_WMBEDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTDONE_2::WMFE Done */ + + +#define GEN6_INSTDONE_2_WMFEDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_WMFEDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INSTDONE_2_WMFEDone_start 16 + +static inline uint32_t ATTRIBUTE_PURE +INSTDONE_2_WMFEDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTPM */ + + +#define GEN8_INSTPM_length 1 +#define GEN75_INSTPM_length 1 +#define GEN7_INSTPM_length 1 +#define GEN6_INSTPM_length 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTPM_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTPM::3D Rendering Instruction Disable */ + + +#define GEN8_INSTPM_3DRenderingInstructionDisable_bits 1 +#define GEN75_INSTPM_3DRenderingInstructionDisable_bits 1 +#define GEN7_INSTPM_3DRenderingInstructionDisable_bits 1 +#define GEN6_INSTPM_3DRenderingInstructionDisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTPM_3DRenderingInstructionDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_INSTPM_3DRenderingInstructionDisable_start 2 +#define GEN75_INSTPM_3DRenderingInstructionDisable_start 2 +#define GEN7_INSTPM_3DRenderingInstructionDisable_start 2 +#define GEN6_INSTPM_3DRenderingInstructionDisable_start 2 + +static inline uint32_t ATTRIBUTE_PURE +INSTPM_3DRenderingInstructionDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTPM::3D Rendering Instruction Disable Mask */ + + +#define GEN8_INSTPM_3DRenderingInstructionDisableMask_bits 1 +#define GEN75_INSTPM_3DRenderingInstructionDisableMask_bits 1 +#define GEN7_INSTPM_3DRenderingInstructionDisableMask_bits 1 +#define GEN6_INSTPM_3DRenderingInstructionDisableMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTPM_3DRenderingInstructionDisableMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_INSTPM_3DRenderingInstructionDisableMask_start 18 +#define GEN75_INSTPM_3DRenderingInstructionDisableMask_start 18 +#define GEN7_INSTPM_3DRenderingInstructionDisableMask_start 18 +#define GEN6_INSTPM_3DRenderingInstructionDisableMask_start 18 + +static inline uint32_t ATTRIBUTE_PURE +INSTPM_3DRenderingInstructionDisableMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 18; + case 7: + if (devinfo->is_haswell) { + return 18; + } else { + return 18; + } + case 6: return 18; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTPM::3D State Instruction Disable */ + + +#define GEN8_INSTPM_3DStateInstructionDisable_bits 1 +#define GEN75_INSTPM_3DStateInstructionDisable_bits 1 +#define GEN7_INSTPM_3DStateInstructionDisable_bits 1 +#define GEN6_INSTPM_3DStateInstructionDisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTPM_3DStateInstructionDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_INSTPM_3DStateInstructionDisable_start 1 +#define GEN75_INSTPM_3DStateInstructionDisable_start 1 +#define GEN7_INSTPM_3DStateInstructionDisable_start 1 +#define GEN6_INSTPM_3DStateInstructionDisable_start 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTPM_3DStateInstructionDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTPM::3D State Instruction Disable Mask */ + + +#define GEN8_INSTPM_3DStateInstructionDisableMask_bits 1 +#define GEN75_INSTPM_3DStateInstructionDisableMask_bits 1 +#define GEN7_INSTPM_3DStateInstructionDisableMask_bits 1 +#define GEN6_INSTPM_3DStateInstructionDisableMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTPM_3DStateInstructionDisableMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_INSTPM_3DStateInstructionDisableMask_start 17 +#define GEN75_INSTPM_3DStateInstructionDisableMask_start 17 +#define GEN7_INSTPM_3DStateInstructionDisableMask_start 17 +#define GEN6_INSTPM_3DStateInstructionDisableMask_start 17 + +static inline uint32_t ATTRIBUTE_PURE +INSTPM_3DStateInstructionDisableMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 17; + case 7: + if (devinfo->is_haswell) { + return 17; + } else { + return 17; + } + case 6: return 17; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTPM::CONSTANT_BUFFER Address Offset Disable */ + + +#define GEN8_INSTPM_CONSTANT_BUFFERAddressOffsetDisable_bits 1 +#define GEN75_INSTPM_CONSTANT_BUFFERAddressOffsetDisable_bits 1 +#define GEN7_INSTPM_CONSTANT_BUFFERAddressOffsetDisable_bits 1 +#define GEN6_INSTPM_CONSTANT_BUFFERAddressOffsetDisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTPM_CONSTANT_BUFFERAddressOffsetDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_INSTPM_CONSTANT_BUFFERAddressOffsetDisable_start 6 +#define GEN75_INSTPM_CONSTANT_BUFFERAddressOffsetDisable_start 6 +#define GEN7_INSTPM_CONSTANT_BUFFERAddressOffsetDisable_start 6 +#define GEN6_INSTPM_CONSTANT_BUFFERAddressOffsetDisable_start 6 + +static inline uint32_t ATTRIBUTE_PURE +INSTPM_CONSTANT_BUFFERAddressOffsetDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 6; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTPM::CONSTANT_BUFFER Address Offset Disable Mask */ + + +#define GEN8_INSTPM_CONSTANT_BUFFERAddressOffsetDisableMask_bits 1 +#define GEN75_INSTPM_CONSTANT_BUFFERAddressOffsetDisableMask_bits 1 +#define GEN7_INSTPM_CONSTANT_BUFFERAddressOffsetDisableMask_bits 1 +#define GEN6_INSTPM_CONSTANT_BUFFERAddressOffsetDisableMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTPM_CONSTANT_BUFFERAddressOffsetDisableMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_INSTPM_CONSTANT_BUFFERAddressOffsetDisableMask_start 22 +#define GEN75_INSTPM_CONSTANT_BUFFERAddressOffsetDisableMask_start 22 +#define GEN7_INSTPM_CONSTANT_BUFFERAddressOffsetDisableMask_start 22 +#define GEN6_INSTPM_CONSTANT_BUFFERAddressOffsetDisableMask_start 22 + +static inline uint32_t ATTRIBUTE_PURE +INSTPM_CONSTANT_BUFFERAddressOffsetDisableMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 22; + case 7: + if (devinfo->is_haswell) { + return 22; + } else { + return 22; + } + case 6: return 22; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTPM::Media Instruction Disable */ + + +#define GEN8_INSTPM_MediaInstructionDisable_bits 1 +#define GEN75_INSTPM_MediaInstructionDisable_bits 1 +#define GEN7_INSTPM_MediaInstructionDisable_bits 1 +#define GEN6_INSTPM_MediaInstructionDisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTPM_MediaInstructionDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_INSTPM_MediaInstructionDisable_start 3 +#define GEN75_INSTPM_MediaInstructionDisable_start 3 +#define GEN7_INSTPM_MediaInstructionDisable_start 3 +#define GEN6_INSTPM_MediaInstructionDisable_start 3 + +static inline uint32_t ATTRIBUTE_PURE +INSTPM_MediaInstructionDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INSTPM::Media Instruction Disable Mask */ + + +#define GEN8_INSTPM_MediaInstructionDisableMask_bits 1 +#define GEN75_INSTPM_MediaInstructionDisableMask_bits 1 +#define GEN7_INSTPM_MediaInstructionDisableMask_bits 1 +#define GEN6_INSTPM_MediaInstructionDisableMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INSTPM_MediaInstructionDisableMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_INSTPM_MediaInstructionDisableMask_start 19 +#define GEN75_INSTPM_MediaInstructionDisableMask_start 19 +#define GEN7_INSTPM_MediaInstructionDisableMask_start 19 +#define GEN6_INSTPM_MediaInstructionDisableMask_start 19 + +static inline uint32_t ATTRIBUTE_PURE +INSTPM_MediaInstructionDisableMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 19; + case 7: + if (devinfo->is_haswell) { + return 19; + } else { + return 19; + } + case 6: return 19; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INTERFACE_DESCRIPTOR_DATA */ + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_length 8 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_length 8 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_length 8 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_length 8 +#define GEN75_INTERFACE_DESCRIPTOR_DATA_length 8 +#define GEN7_INTERFACE_DESCRIPTOR_DATA_length 8 +#define GEN6_INTERFACE_DESCRIPTOR_DATA_length 8 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INTERFACE_DESCRIPTOR_DATA::Barrier Enable */ + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_BarrierEnable_bits 1 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_BarrierEnable_bits 1 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_BarrierEnable_bits 1 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_BarrierEnable_bits 1 +#define GEN75_INTERFACE_DESCRIPTOR_DATA_BarrierEnable_bits 1 +#define GEN7_INTERFACE_DESCRIPTOR_DATA_BarrierEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_BarrierEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_BarrierEnable_start 213 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_BarrierEnable_start 213 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_BarrierEnable_start 213 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_BarrierEnable_start 213 +#define GEN75_INTERFACE_DESCRIPTOR_DATA_BarrierEnable_start 181 +#define GEN7_INTERFACE_DESCRIPTOR_DATA_BarrierEnable_start 181 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_BarrierEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 213; + case 10: return 213; + case 9: return 213; + case 8: return 213; + case 7: + if (devinfo->is_haswell) { + return 181; + } else { + return 181; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INTERFACE_DESCRIPTOR_DATA::Barrier ID */ + + +#define GEN6_INTERFACE_DESCRIPTOR_DATA_BarrierID_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_BarrierID_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INTERFACE_DESCRIPTOR_DATA_BarrierID_start 160 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_BarrierID_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 160; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INTERFACE_DESCRIPTOR_DATA::Barrier Return Byte */ + + +#define GEN6_INTERFACE_DESCRIPTOR_DATA_BarrierReturnByte_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_BarrierReturnByte_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INTERFACE_DESCRIPTOR_DATA_BarrierReturnByte_start 168 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_BarrierReturnByte_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 168; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INTERFACE_DESCRIPTOR_DATA::Barrier Return GRF Offset */ + + +#define GEN6_INTERFACE_DESCRIPTOR_DATA_BarrierReturnGRFOffset_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_BarrierReturnGRFOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_INTERFACE_DESCRIPTOR_DATA_BarrierReturnGRFOffset_start 184 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_BarrierReturnGRFOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 184; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INTERFACE_DESCRIPTOR_DATA::Binding Table Entry Count */ + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_BindingTableEntryCount_bits 5 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_BindingTableEntryCount_bits 5 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_BindingTableEntryCount_bits 5 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_BindingTableEntryCount_bits 5 +#define GEN75_INTERFACE_DESCRIPTOR_DATA_BindingTableEntryCount_bits 5 +#define GEN7_INTERFACE_DESCRIPTOR_DATA_BindingTableEntryCount_bits 5 +#define GEN6_INTERFACE_DESCRIPTOR_DATA_BindingTableEntryCount_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_BindingTableEntryCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 5; + } + case 6: return 5; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_BindingTableEntryCount_start 128 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_BindingTableEntryCount_start 128 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_BindingTableEntryCount_start 128 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_BindingTableEntryCount_start 128 +#define GEN75_INTERFACE_DESCRIPTOR_DATA_BindingTableEntryCount_start 96 +#define GEN7_INTERFACE_DESCRIPTOR_DATA_BindingTableEntryCount_start 96 +#define GEN6_INTERFACE_DESCRIPTOR_DATA_BindingTableEntryCount_start 96 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_BindingTableEntryCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 128; + case 10: return 128; + case 9: return 128; + case 8: return 128; + case 7: + if (devinfo->is_haswell) { + return 96; + } else { + return 96; + } + case 6: return 96; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INTERFACE_DESCRIPTOR_DATA::Binding Table Pointer */ + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_BindingTablePointer_bits 11 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_BindingTablePointer_bits 11 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_BindingTablePointer_bits 11 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_BindingTablePointer_bits 11 +#define GEN75_INTERFACE_DESCRIPTOR_DATA_BindingTablePointer_bits 11 +#define GEN7_INTERFACE_DESCRIPTOR_DATA_BindingTablePointer_bits 11 +#define GEN6_INTERFACE_DESCRIPTOR_DATA_BindingTablePointer_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_BindingTablePointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 11; + } else { + return 11; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_BindingTablePointer_start 133 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_BindingTablePointer_start 133 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_BindingTablePointer_start 133 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_BindingTablePointer_start 133 +#define GEN75_INTERFACE_DESCRIPTOR_DATA_BindingTablePointer_start 101 +#define GEN7_INTERFACE_DESCRIPTOR_DATA_BindingTablePointer_start 101 +#define GEN6_INTERFACE_DESCRIPTOR_DATA_BindingTablePointer_start 101 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_BindingTablePointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 133; + case 10: return 133; + case 9: return 133; + case 8: return 133; + case 7: + if (devinfo->is_haswell) { + return 101; + } else { + return 101; + } + case 6: return 101; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INTERFACE_DESCRIPTOR_DATA::Constant URB Entry Read Length */ + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadLength_bits 16 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadLength_bits 16 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadLength_bits 16 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadLength_bits 16 +#define GEN75_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadLength_bits 16 +#define GEN7_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadLength_bits 16 +#define GEN6_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadLength_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadLength_start 176 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadLength_start 176 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadLength_start 176 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadLength_start 176 +#define GEN75_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadLength_start 144 +#define GEN7_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadLength_start 144 +#define GEN6_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadLength_start 144 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 176; + case 10: return 176; + case 9: return 176; + case 8: return 176; + case 7: + if (devinfo->is_haswell) { + return 144; + } else { + return 144; + } + case 6: return 144; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INTERFACE_DESCRIPTOR_DATA::Constant URB Entry Read Offset */ + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadOffset_bits 16 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadOffset_bits 16 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadOffset_bits 16 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadOffset_bits 16 +#define GEN7_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadOffset_bits 16 +#define GEN6_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadOffset_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadOffset_start 160 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadOffset_start 160 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadOffset_start 160 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadOffset_start 160 +#define GEN7_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadOffset_start 128 +#define GEN6_INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadOffset_start 128 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_ConstantURBEntryReadOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 160; + case 10: return 160; + case 9: return 160; + case 8: return 160; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 128; + } + case 6: return 128; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INTERFACE_DESCRIPTOR_DATA::Cross-Thread Constant Data Read Length */ + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_CrossThreadConstantDataReadLength_bits 8 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_CrossThreadConstantDataReadLength_bits 8 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_CrossThreadConstantDataReadLength_bits 8 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_CrossThreadConstantDataReadLength_bits 8 +#define GEN75_INTERFACE_DESCRIPTOR_DATA_CrossThreadConstantDataReadLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_CrossThreadConstantDataReadLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_CrossThreadConstantDataReadLength_start 224 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_CrossThreadConstantDataReadLength_start 224 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_CrossThreadConstantDataReadLength_start 224 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_CrossThreadConstantDataReadLength_start 224 +#define GEN75_INTERFACE_DESCRIPTOR_DATA_CrossThreadConstantDataReadLength_start 192 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_CrossThreadConstantDataReadLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 224; + case 10: return 224; + case 9: return 224; + case 8: return 224; + case 7: + if (devinfo->is_haswell) { + return 192; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INTERFACE_DESCRIPTOR_DATA::Denorm Mode */ + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_DenormMode_bits 1 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_DenormMode_bits 1 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_DenormMode_bits 1 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_DenormMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_DenormMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_DenormMode_start 83 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_DenormMode_start 83 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_DenormMode_start 83 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_DenormMode_start 83 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_DenormMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 83; + case 10: return 83; + case 9: return 83; + case 8: return 83; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INTERFACE_DESCRIPTOR_DATA::Floating Point Mode */ + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_FloatingPointMode_bits 1 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_FloatingPointMode_bits 1 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_FloatingPointMode_bits 1 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_FloatingPointMode_bits 1 +#define GEN75_INTERFACE_DESCRIPTOR_DATA_FloatingPointMode_bits 1 +#define GEN7_INTERFACE_DESCRIPTOR_DATA_FloatingPointMode_bits 1 +#define GEN6_INTERFACE_DESCRIPTOR_DATA_FloatingPointMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_FloatingPointMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_FloatingPointMode_start 80 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_FloatingPointMode_start 80 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_FloatingPointMode_start 80 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_FloatingPointMode_start 80 +#define GEN75_INTERFACE_DESCRIPTOR_DATA_FloatingPointMode_start 48 +#define GEN7_INTERFACE_DESCRIPTOR_DATA_FloatingPointMode_start 48 +#define GEN6_INTERFACE_DESCRIPTOR_DATA_FloatingPointMode_start 48 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_FloatingPointMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 80; + case 10: return 80; + case 9: return 80; + case 8: return 80; + case 7: + if (devinfo->is_haswell) { + return 48; + } else { + return 48; + } + case 6: return 48; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INTERFACE_DESCRIPTOR_DATA::Global Barrier Enable */ + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_GlobalBarrierEnable_bits 1 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_GlobalBarrierEnable_bits 1 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_GlobalBarrierEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_GlobalBarrierEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_GlobalBarrierEnable_start 207 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_GlobalBarrierEnable_start 207 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_GlobalBarrierEnable_start 207 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_GlobalBarrierEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 207; + case 10: return 207; + case 9: return 207; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INTERFACE_DESCRIPTOR_DATA::Illegal Opcode Exception Enable */ + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_IllegalOpcodeExceptionEnable_bits 1 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_IllegalOpcodeExceptionEnable_bits 1 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_IllegalOpcodeExceptionEnable_bits 1 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_IllegalOpcodeExceptionEnable_bits 1 +#define GEN75_INTERFACE_DESCRIPTOR_DATA_IllegalOpcodeExceptionEnable_bits 1 +#define GEN7_INTERFACE_DESCRIPTOR_DATA_IllegalOpcodeExceptionEnable_bits 1 +#define GEN6_INTERFACE_DESCRIPTOR_DATA_IllegalOpcodeExceptionEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_IllegalOpcodeExceptionEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_IllegalOpcodeExceptionEnable_start 77 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_IllegalOpcodeExceptionEnable_start 77 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_IllegalOpcodeExceptionEnable_start 77 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_IllegalOpcodeExceptionEnable_start 77 +#define GEN75_INTERFACE_DESCRIPTOR_DATA_IllegalOpcodeExceptionEnable_start 45 +#define GEN7_INTERFACE_DESCRIPTOR_DATA_IllegalOpcodeExceptionEnable_start 45 +#define GEN6_INTERFACE_DESCRIPTOR_DATA_IllegalOpcodeExceptionEnable_start 45 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_IllegalOpcodeExceptionEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 77; + case 10: return 77; + case 9: return 77; + case 8: return 77; + case 7: + if (devinfo->is_haswell) { + return 45; + } else { + return 45; + } + case 6: return 45; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INTERFACE_DESCRIPTOR_DATA::Kernel Start Pointer */ + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_KernelStartPointer_bits 42 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_KernelStartPointer_bits 42 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_KernelStartPointer_bits 42 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_KernelStartPointer_bits 42 +#define GEN75_INTERFACE_DESCRIPTOR_DATA_KernelStartPointer_bits 26 +#define GEN7_INTERFACE_DESCRIPTOR_DATA_KernelStartPointer_bits 26 +#define GEN6_INTERFACE_DESCRIPTOR_DATA_KernelStartPointer_bits 26 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_KernelStartPointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 42; + case 10: return 42; + case 9: return 42; + case 8: return 42; + case 7: + if (devinfo->is_haswell) { + return 26; + } else { + return 26; + } + case 6: return 26; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_KernelStartPointer_start 6 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_KernelStartPointer_start 6 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_KernelStartPointer_start 6 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_KernelStartPointer_start 6 +#define GEN75_INTERFACE_DESCRIPTOR_DATA_KernelStartPointer_start 6 +#define GEN7_INTERFACE_DESCRIPTOR_DATA_KernelStartPointer_start 6 +#define GEN6_INTERFACE_DESCRIPTOR_DATA_KernelStartPointer_start 6 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_KernelStartPointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 6; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INTERFACE_DESCRIPTOR_DATA::Mask Stack Exception Enable */ + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_MaskStackExceptionEnable_bits 1 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_MaskStackExceptionEnable_bits 1 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_MaskStackExceptionEnable_bits 1 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_MaskStackExceptionEnable_bits 1 +#define GEN75_INTERFACE_DESCRIPTOR_DATA_MaskStackExceptionEnable_bits 1 +#define GEN7_INTERFACE_DESCRIPTOR_DATA_MaskStackExceptionEnable_bits 1 +#define GEN6_INTERFACE_DESCRIPTOR_DATA_MaskStackExceptionEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_MaskStackExceptionEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_MaskStackExceptionEnable_start 75 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_MaskStackExceptionEnable_start 75 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_MaskStackExceptionEnable_start 75 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_MaskStackExceptionEnable_start 75 +#define GEN75_INTERFACE_DESCRIPTOR_DATA_MaskStackExceptionEnable_start 43 +#define GEN7_INTERFACE_DESCRIPTOR_DATA_MaskStackExceptionEnable_start 43 +#define GEN6_INTERFACE_DESCRIPTOR_DATA_MaskStackExceptionEnable_start 43 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_MaskStackExceptionEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 75; + case 10: return 75; + case 9: return 75; + case 8: return 75; + case 7: + if (devinfo->is_haswell) { + return 43; + } else { + return 43; + } + case 6: return 43; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INTERFACE_DESCRIPTOR_DATA::Number of Threads in GPGPU Thread Group */ + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_NumberofThreadsinGPGPUThreadGroup_bits 10 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_NumberofThreadsinGPGPUThreadGroup_bits 10 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_NumberofThreadsinGPGPUThreadGroup_bits 10 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_NumberofThreadsinGPGPUThreadGroup_bits 10 +#define GEN75_INTERFACE_DESCRIPTOR_DATA_NumberofThreadsinGPGPUThreadGroup_bits 8 +#define GEN7_INTERFACE_DESCRIPTOR_DATA_NumberofThreadsinGPGPUThreadGroup_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_NumberofThreadsinGPGPUThreadGroup_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 10; + case 10: return 10; + case 9: return 10; + case 8: return 10; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_NumberofThreadsinGPGPUThreadGroup_start 192 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_NumberofThreadsinGPGPUThreadGroup_start 192 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_NumberofThreadsinGPGPUThreadGroup_start 192 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_NumberofThreadsinGPGPUThreadGroup_start 192 +#define GEN75_INTERFACE_DESCRIPTOR_DATA_NumberofThreadsinGPGPUThreadGroup_start 160 +#define GEN7_INTERFACE_DESCRIPTOR_DATA_NumberofThreadsinGPGPUThreadGroup_start 160 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_NumberofThreadsinGPGPUThreadGroup_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 192; + case 10: return 192; + case 9: return 192; + case 8: return 192; + case 7: + if (devinfo->is_haswell) { + return 160; + } else { + return 160; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INTERFACE_DESCRIPTOR_DATA::Rounding Mode */ + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_RoundingMode_bits 2 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_RoundingMode_bits 2 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_RoundingMode_bits 2 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_RoundingMode_bits 2 +#define GEN75_INTERFACE_DESCRIPTOR_DATA_RoundingMode_bits 2 +#define GEN7_INTERFACE_DESCRIPTOR_DATA_RoundingMode_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_RoundingMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_RoundingMode_start 214 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_RoundingMode_start 214 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_RoundingMode_start 214 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_RoundingMode_start 214 +#define GEN75_INTERFACE_DESCRIPTOR_DATA_RoundingMode_start 182 +#define GEN7_INTERFACE_DESCRIPTOR_DATA_RoundingMode_start 182 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_RoundingMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 214; + case 10: return 214; + case 9: return 214; + case 8: return 214; + case 7: + if (devinfo->is_haswell) { + return 182; + } else { + return 182; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INTERFACE_DESCRIPTOR_DATA::Sampler Count */ + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_SamplerCount_bits 3 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_SamplerCount_bits 3 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_SamplerCount_bits 3 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_SamplerCount_bits 3 +#define GEN75_INTERFACE_DESCRIPTOR_DATA_SamplerCount_bits 3 +#define GEN7_INTERFACE_DESCRIPTOR_DATA_SamplerCount_bits 3 +#define GEN6_INTERFACE_DESCRIPTOR_DATA_SamplerCount_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_SamplerCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_SamplerCount_start 98 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_SamplerCount_start 98 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_SamplerCount_start 98 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_SamplerCount_start 98 +#define GEN75_INTERFACE_DESCRIPTOR_DATA_SamplerCount_start 66 +#define GEN7_INTERFACE_DESCRIPTOR_DATA_SamplerCount_start 66 +#define GEN6_INTERFACE_DESCRIPTOR_DATA_SamplerCount_start 66 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_SamplerCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 98; + case 10: return 98; + case 9: return 98; + case 8: return 98; + case 7: + if (devinfo->is_haswell) { + return 66; + } else { + return 66; + } + case 6: return 66; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INTERFACE_DESCRIPTOR_DATA::Sampler State Pointer */ + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_SamplerStatePointer_bits 27 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_SamplerStatePointer_bits 27 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_SamplerStatePointer_bits 27 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_SamplerStatePointer_bits 27 +#define GEN75_INTERFACE_DESCRIPTOR_DATA_SamplerStatePointer_bits 27 +#define GEN7_INTERFACE_DESCRIPTOR_DATA_SamplerStatePointer_bits 27 +#define GEN6_INTERFACE_DESCRIPTOR_DATA_SamplerStatePointer_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_SamplerStatePointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_SamplerStatePointer_start 101 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_SamplerStatePointer_start 101 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_SamplerStatePointer_start 101 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_SamplerStatePointer_start 101 +#define GEN75_INTERFACE_DESCRIPTOR_DATA_SamplerStatePointer_start 69 +#define GEN7_INTERFACE_DESCRIPTOR_DATA_SamplerStatePointer_start 69 +#define GEN6_INTERFACE_DESCRIPTOR_DATA_SamplerStatePointer_start 69 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_SamplerStatePointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 101; + case 10: return 101; + case 9: return 101; + case 8: return 101; + case 7: + if (devinfo->is_haswell) { + return 69; + } else { + return 69; + } + case 6: return 69; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INTERFACE_DESCRIPTOR_DATA::Shared Local Memory Size */ + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_SharedLocalMemorySize_bits 5 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_SharedLocalMemorySize_bits 5 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_SharedLocalMemorySize_bits 5 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_SharedLocalMemorySize_bits 5 +#define GEN75_INTERFACE_DESCRIPTOR_DATA_SharedLocalMemorySize_bits 5 +#define GEN7_INTERFACE_DESCRIPTOR_DATA_SharedLocalMemorySize_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_SharedLocalMemorySize_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 5; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_SharedLocalMemorySize_start 208 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_SharedLocalMemorySize_start 208 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_SharedLocalMemorySize_start 208 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_SharedLocalMemorySize_start 208 +#define GEN75_INTERFACE_DESCRIPTOR_DATA_SharedLocalMemorySize_start 176 +#define GEN7_INTERFACE_DESCRIPTOR_DATA_SharedLocalMemorySize_start 176 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_SharedLocalMemorySize_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 208; + case 10: return 208; + case 9: return 208; + case 8: return 208; + case 7: + if (devinfo->is_haswell) { + return 176; + } else { + return 176; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INTERFACE_DESCRIPTOR_DATA::Single Program Flow */ + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_SingleProgramFlow_bits 1 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_SingleProgramFlow_bits 1 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_SingleProgramFlow_bits 1 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_SingleProgramFlow_bits 1 +#define GEN75_INTERFACE_DESCRIPTOR_DATA_SingleProgramFlow_bits 1 +#define GEN7_INTERFACE_DESCRIPTOR_DATA_SingleProgramFlow_bits 1 +#define GEN6_INTERFACE_DESCRIPTOR_DATA_SingleProgramFlow_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_SingleProgramFlow_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_SingleProgramFlow_start 82 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_SingleProgramFlow_start 82 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_SingleProgramFlow_start 82 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_SingleProgramFlow_start 82 +#define GEN75_INTERFACE_DESCRIPTOR_DATA_SingleProgramFlow_start 50 +#define GEN7_INTERFACE_DESCRIPTOR_DATA_SingleProgramFlow_start 50 +#define GEN6_INTERFACE_DESCRIPTOR_DATA_SingleProgramFlow_start 50 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_SingleProgramFlow_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 82; + case 10: return 82; + case 9: return 82; + case 8: return 82; + case 7: + if (devinfo->is_haswell) { + return 50; + } else { + return 50; + } + case 6: return 50; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INTERFACE_DESCRIPTOR_DATA::Software Exception Enable */ + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_SoftwareExceptionEnable_bits 1 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_SoftwareExceptionEnable_bits 1 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_SoftwareExceptionEnable_bits 1 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_SoftwareExceptionEnable_bits 1 +#define GEN75_INTERFACE_DESCRIPTOR_DATA_SoftwareExceptionEnable_bits 1 +#define GEN7_INTERFACE_DESCRIPTOR_DATA_SoftwareExceptionEnable_bits 1 +#define GEN6_INTERFACE_DESCRIPTOR_DATA_SoftwareExceptionEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_SoftwareExceptionEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_SoftwareExceptionEnable_start 71 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_SoftwareExceptionEnable_start 71 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_SoftwareExceptionEnable_start 71 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_SoftwareExceptionEnable_start 71 +#define GEN75_INTERFACE_DESCRIPTOR_DATA_SoftwareExceptionEnable_start 39 +#define GEN7_INTERFACE_DESCRIPTOR_DATA_SoftwareExceptionEnable_start 39 +#define GEN6_INTERFACE_DESCRIPTOR_DATA_SoftwareExceptionEnable_start 39 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_SoftwareExceptionEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 71; + case 10: return 71; + case 9: return 71; + case 8: return 71; + case 7: + if (devinfo->is_haswell) { + return 39; + } else { + return 39; + } + case 6: return 39; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INTERFACE_DESCRIPTOR_DATA::Thread Preemption disable */ + + +#define GEN10_INTERFACE_DESCRIPTOR_DATA_ThreadPreemptiondisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_ThreadPreemptiondisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_INTERFACE_DESCRIPTOR_DATA_ThreadPreemptiondisable_start 84 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_ThreadPreemptiondisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 84; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* INTERFACE_DESCRIPTOR_DATA::Thread Priority */ + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_ThreadPriority_bits 1 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_ThreadPriority_bits 1 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_ThreadPriority_bits 1 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_ThreadPriority_bits 1 +#define GEN75_INTERFACE_DESCRIPTOR_DATA_ThreadPriority_bits 1 +#define GEN7_INTERFACE_DESCRIPTOR_DATA_ThreadPriority_bits 1 +#define GEN6_INTERFACE_DESCRIPTOR_DATA_ThreadPriority_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_ThreadPriority_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_INTERFACE_DESCRIPTOR_DATA_ThreadPriority_start 81 +#define GEN10_INTERFACE_DESCRIPTOR_DATA_ThreadPriority_start 81 +#define GEN9_INTERFACE_DESCRIPTOR_DATA_ThreadPriority_start 81 +#define GEN8_INTERFACE_DESCRIPTOR_DATA_ThreadPriority_start 81 +#define GEN75_INTERFACE_DESCRIPTOR_DATA_ThreadPriority_start 49 +#define GEN7_INTERFACE_DESCRIPTOR_DATA_ThreadPriority_start 49 +#define GEN6_INTERFACE_DESCRIPTOR_DATA_ThreadPriority_start 49 + +static inline uint32_t ATTRIBUTE_PURE +INTERFACE_DESCRIPTOR_DATA_ThreadPriority_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 81; + case 10: return 81; + case 9: return 81; + case 8: return 81; + case 7: + if (devinfo->is_haswell) { + return 49; + } else { + return 49; + } + case 6: return 49; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* L3CNTLREG */ + + +#define GEN11_L3CNTLREG_length 1 +#define GEN10_L3CNTLREG_length 1 +#define GEN9_L3CNTLREG_length 1 +#define GEN8_L3CNTLREG_length 1 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* L3CNTLREG::All Allocation */ + + +#define GEN11_L3CNTLREG_AllAllocation_bits 7 +#define GEN10_L3CNTLREG_AllAllocation_bits 7 +#define GEN9_L3CNTLREG_AllAllocation_bits 7 +#define GEN8_L3CNTLREG_AllAllocation_bits 7 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG_AllAllocation_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_L3CNTLREG_AllAllocation_start 25 +#define GEN10_L3CNTLREG_AllAllocation_start 25 +#define GEN9_L3CNTLREG_AllAllocation_start 25 +#define GEN8_L3CNTLREG_AllAllocation_start 25 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG_AllAllocation_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 25; + case 10: return 25; + case 9: return 25; + case 8: return 25; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* L3CNTLREG::DC Allocation */ + + +#define GEN11_L3CNTLREG_DCAllocation_bits 7 +#define GEN10_L3CNTLREG_DCAllocation_bits 7 +#define GEN9_L3CNTLREG_DCAllocation_bits 7 +#define GEN8_L3CNTLREG_DCAllocation_bits 7 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG_DCAllocation_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_L3CNTLREG_DCAllocation_start 18 +#define GEN10_L3CNTLREG_DCAllocation_start 18 +#define GEN9_L3CNTLREG_DCAllocation_start 18 +#define GEN8_L3CNTLREG_DCAllocation_start 18 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG_DCAllocation_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 18; + case 10: return 18; + case 9: return 18; + case 8: return 18; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* L3CNTLREG::Error Detection Behavior Control */ + + +#define GEN11_L3CNTLREG_ErrorDetectionBehaviorControl_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG_ErrorDetectionBehaviorControl_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_L3CNTLREG_ErrorDetectionBehaviorControl_start 9 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG_ErrorDetectionBehaviorControl_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 9; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* L3CNTLREG::RO Allocation */ + + +#define GEN11_L3CNTLREG_ROAllocation_bits 7 +#define GEN10_L3CNTLREG_ROAllocation_bits 7 +#define GEN9_L3CNTLREG_ROAllocation_bits 7 +#define GEN8_L3CNTLREG_ROAllocation_bits 7 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG_ROAllocation_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_L3CNTLREG_ROAllocation_start 11 +#define GEN10_L3CNTLREG_ROAllocation_start 11 +#define GEN9_L3CNTLREG_ROAllocation_start 11 +#define GEN8_L3CNTLREG_ROAllocation_start 11 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG_ROAllocation_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* L3CNTLREG::SLM Enable */ + + +#define GEN11_L3CNTLREG_SLMEnable_bits 1 +#define GEN10_L3CNTLREG_SLMEnable_bits 1 +#define GEN9_L3CNTLREG_SLMEnable_bits 1 +#define GEN8_L3CNTLREG_SLMEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG_SLMEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_L3CNTLREG_SLMEnable_start 0 +#define GEN10_L3CNTLREG_SLMEnable_start 0 +#define GEN9_L3CNTLREG_SLMEnable_start 0 +#define GEN8_L3CNTLREG_SLMEnable_start 0 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG_SLMEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* L3CNTLREG::URB Allocation */ + + +#define GEN11_L3CNTLREG_URBAllocation_bits 7 +#define GEN10_L3CNTLREG_URBAllocation_bits 7 +#define GEN9_L3CNTLREG_URBAllocation_bits 7 +#define GEN8_L3CNTLREG_URBAllocation_bits 7 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG_URBAllocation_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_L3CNTLREG_URBAllocation_start 1 +#define GEN10_L3CNTLREG_URBAllocation_start 1 +#define GEN9_L3CNTLREG_URBAllocation_start 1 +#define GEN8_L3CNTLREG_URBAllocation_start 1 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG_URBAllocation_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* L3CNTLREG::Use Full Ways */ + + +#define GEN11_L3CNTLREG_UseFullWays_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG_UseFullWays_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_L3CNTLREG_UseFullWays_start 10 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG_UseFullWays_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 10; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* L3CNTLREG2 */ + + +#define GEN75_L3CNTLREG2_length 1 +#define GEN7_L3CNTLREG2_length 1 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG2_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* L3CNTLREG2::ALL Allocation */ + + +#define GEN7_L3CNTLREG2_ALLAllocation_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG2_ALLAllocation_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 6; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN7_L3CNTLREG2_ALLAllocation_start 8 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG2_ALLAllocation_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* L3CNTLREG2::DC Allocation */ + + +#define GEN75_L3CNTLREG2_DCAllocation_bits 6 +#define GEN7_L3CNTLREG2_DCAllocation_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG2_DCAllocation_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_L3CNTLREG2_DCAllocation_start 21 +#define GEN7_L3CNTLREG2_DCAllocation_start 21 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG2_DCAllocation_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 21; + } else { + return 21; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* L3CNTLREG2::DC Low Bandwidth */ + + +#define GEN75_L3CNTLREG2_DCLowBandwidth_bits 1 +#define GEN7_L3CNTLREG2_DCLowBandwidth_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG2_DCLowBandwidth_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_L3CNTLREG2_DCLowBandwidth_start 27 +#define GEN7_L3CNTLREG2_DCLowBandwidth_start 27 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG2_DCLowBandwidth_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* L3CNTLREG2::RO Allocation */ + + +#define GEN75_L3CNTLREG2_ROAllocation_bits 6 +#define GEN7_L3CNTLREG2_ROAllocation_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG2_ROAllocation_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_L3CNTLREG2_ROAllocation_start 14 +#define GEN7_L3CNTLREG2_ROAllocation_start 14 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG2_ROAllocation_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 14; + } else { + return 14; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* L3CNTLREG2::RO Low Bandwidth */ + + +#define GEN75_L3CNTLREG2_ROLowBandwidth_bits 1 +#define GEN7_L3CNTLREG2_ROLowBandwidth_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG2_ROLowBandwidth_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_L3CNTLREG2_ROLowBandwidth_start 20 +#define GEN7_L3CNTLREG2_ROLowBandwidth_start 20 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG2_ROLowBandwidth_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 20; + } else { + return 20; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* L3CNTLREG2::SLM Enable */ + + +#define GEN75_L3CNTLREG2_SLMEnable_bits 1 +#define GEN7_L3CNTLREG2_SLMEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG2_SLMEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_L3CNTLREG2_SLMEnable_start 0 +#define GEN7_L3CNTLREG2_SLMEnable_start 0 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG2_SLMEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* L3CNTLREG2::URB Allocation */ + + +#define GEN75_L3CNTLREG2_URBAllocation_bits 6 +#define GEN7_L3CNTLREG2_URBAllocation_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG2_URBAllocation_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_L3CNTLREG2_URBAllocation_start 1 +#define GEN7_L3CNTLREG2_URBAllocation_start 1 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG2_URBAllocation_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* L3CNTLREG2::URB Low Bandwidth */ + + +#define GEN75_L3CNTLREG2_URBLowBandwidth_bits 1 +#define GEN7_L3CNTLREG2_URBLowBandwidth_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG2_URBLowBandwidth_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_L3CNTLREG2_URBLowBandwidth_start 7 +#define GEN7_L3CNTLREG2_URBLowBandwidth_start 7 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG2_URBLowBandwidth_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 7; + } else { + return 7; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* L3CNTLREG3 */ + + +#define GEN75_L3CNTLREG3_length 1 +#define GEN7_L3CNTLREG3_length 1 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG3_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* L3CNTLREG3::C Allocation */ + + +#define GEN75_L3CNTLREG3_CAllocation_bits 6 +#define GEN7_L3CNTLREG3_CAllocation_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG3_CAllocation_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_L3CNTLREG3_CAllocation_start 8 +#define GEN7_L3CNTLREG3_CAllocation_start 8 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG3_CAllocation_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* L3CNTLREG3::C Low Bandwidth */ + + +#define GEN75_L3CNTLREG3_CLowBandwidth_bits 1 +#define GEN7_L3CNTLREG3_CLowBandwidth_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG3_CLowBandwidth_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_L3CNTLREG3_CLowBandwidth_start 14 +#define GEN7_L3CNTLREG3_CLowBandwidth_start 14 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG3_CLowBandwidth_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 14; + } else { + return 14; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* L3CNTLREG3::IS Allocation */ + + +#define GEN75_L3CNTLREG3_ISAllocation_bits 6 +#define GEN7_L3CNTLREG3_ISAllocation_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG3_ISAllocation_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_L3CNTLREG3_ISAllocation_start 1 +#define GEN7_L3CNTLREG3_ISAllocation_start 1 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG3_ISAllocation_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* L3CNTLREG3::IS Low Bandwidth */ + + +#define GEN75_L3CNTLREG3_ISLowBandwidth_bits 1 +#define GEN7_L3CNTLREG3_ISLowBandwidth_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG3_ISLowBandwidth_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_L3CNTLREG3_ISLowBandwidth_start 7 +#define GEN7_L3CNTLREG3_ISLowBandwidth_start 7 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG3_ISLowBandwidth_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 7; + } else { + return 7; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* L3CNTLREG3::T Allocation */ + + +#define GEN75_L3CNTLREG3_TAllocation_bits 6 +#define GEN7_L3CNTLREG3_TAllocation_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG3_TAllocation_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_L3CNTLREG3_TAllocation_start 15 +#define GEN7_L3CNTLREG3_TAllocation_start 15 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG3_TAllocation_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 15; + } else { + return 15; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* L3CNTLREG3::T Low Bandwidth */ + + +#define GEN75_L3CNTLREG3_TLowBandwidth_bits 1 +#define GEN7_L3CNTLREG3_TLowBandwidth_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG3_TLowBandwidth_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_L3CNTLREG3_TLowBandwidth_start 21 +#define GEN7_L3CNTLREG3_TLowBandwidth_start 21 + +static inline uint32_t ATTRIBUTE_PURE +L3CNTLREG3_TLowBandwidth_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 21; + } else { + return 21; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* L3SQCREG1 */ + + +#define GEN75_L3SQCREG1_length 1 +#define GEN7_L3SQCREG1_length 1 + +static inline uint32_t ATTRIBUTE_PURE +L3SQCREG1_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* L3SQCREG1::Convert C_UC */ + + +#define GEN75_L3SQCREG1_ConvertC_UC_bits 1 +#define GEN7_L3SQCREG1_ConvertC_UC_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +L3SQCREG1_ConvertC_UC_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_L3SQCREG1_ConvertC_UC_start 26 +#define GEN7_L3SQCREG1_ConvertC_UC_start 26 + +static inline uint32_t ATTRIBUTE_PURE +L3SQCREG1_ConvertC_UC_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 26; + } else { + return 26; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* L3SQCREG1::Convert DC_UC */ + + +#define GEN75_L3SQCREG1_ConvertDC_UC_bits 1 +#define GEN7_L3SQCREG1_ConvertDC_UC_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +L3SQCREG1_ConvertDC_UC_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_L3SQCREG1_ConvertDC_UC_start 24 +#define GEN7_L3SQCREG1_ConvertDC_UC_start 24 + +static inline uint32_t ATTRIBUTE_PURE +L3SQCREG1_ConvertDC_UC_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* L3SQCREG1::Convert IS_UC */ + + +#define GEN75_L3SQCREG1_ConvertIS_UC_bits 1 +#define GEN7_L3SQCREG1_ConvertIS_UC_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +L3SQCREG1_ConvertIS_UC_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_L3SQCREG1_ConvertIS_UC_start 25 +#define GEN7_L3SQCREG1_ConvertIS_UC_start 25 + +static inline uint32_t ATTRIBUTE_PURE +L3SQCREG1_ConvertIS_UC_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 25; + } else { + return 25; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* L3SQCREG1::Convert T_UC */ + + +#define GEN75_L3SQCREG1_ConvertT_UC_bits 1 +#define GEN7_L3SQCREG1_ConvertT_UC_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +L3SQCREG1_ConvertT_UC_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_L3SQCREG1_ConvertT_UC_start 27 +#define GEN7_L3SQCREG1_ConvertT_UC_start 27 + +static inline uint32_t ATTRIBUTE_PURE +L3SQCREG1_ConvertT_UC_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_CURBE_LOAD */ + + +#define GEN11_MEDIA_CURBE_LOAD_length 4 +#define GEN10_MEDIA_CURBE_LOAD_length 4 +#define GEN9_MEDIA_CURBE_LOAD_length 4 +#define GEN8_MEDIA_CURBE_LOAD_length 4 +#define GEN75_MEDIA_CURBE_LOAD_length 4 +#define GEN7_MEDIA_CURBE_LOAD_length 4 +#define GEN6_MEDIA_CURBE_LOAD_length 4 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_CURBE_LOAD_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_CURBE_LOAD::CURBE Data Start Address */ + + +#define GEN11_MEDIA_CURBE_LOAD_CURBEDataStartAddress_bits 32 +#define GEN10_MEDIA_CURBE_LOAD_CURBEDataStartAddress_bits 32 +#define GEN9_MEDIA_CURBE_LOAD_CURBEDataStartAddress_bits 32 +#define GEN8_MEDIA_CURBE_LOAD_CURBEDataStartAddress_bits 32 +#define GEN75_MEDIA_CURBE_LOAD_CURBEDataStartAddress_bits 32 +#define GEN7_MEDIA_CURBE_LOAD_CURBEDataStartAddress_bits 32 +#define GEN6_MEDIA_CURBE_LOAD_CURBEDataStartAddress_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_CURBE_LOAD_CURBEDataStartAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_CURBE_LOAD_CURBEDataStartAddress_start 96 +#define GEN10_MEDIA_CURBE_LOAD_CURBEDataStartAddress_start 96 +#define GEN9_MEDIA_CURBE_LOAD_CURBEDataStartAddress_start 96 +#define GEN8_MEDIA_CURBE_LOAD_CURBEDataStartAddress_start 96 +#define GEN75_MEDIA_CURBE_LOAD_CURBEDataStartAddress_start 96 +#define GEN7_MEDIA_CURBE_LOAD_CURBEDataStartAddress_start 96 +#define GEN6_MEDIA_CURBE_LOAD_CURBEDataStartAddress_start 96 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_CURBE_LOAD_CURBEDataStartAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 96; + case 10: return 96; + case 9: return 96; + case 8: return 96; + case 7: + if (devinfo->is_haswell) { + return 96; + } else { + return 96; + } + case 6: return 96; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_CURBE_LOAD::CURBE Total Data Length */ + + +#define GEN11_MEDIA_CURBE_LOAD_CURBETotalDataLength_bits 17 +#define GEN10_MEDIA_CURBE_LOAD_CURBETotalDataLength_bits 17 +#define GEN9_MEDIA_CURBE_LOAD_CURBETotalDataLength_bits 17 +#define GEN8_MEDIA_CURBE_LOAD_CURBETotalDataLength_bits 17 +#define GEN75_MEDIA_CURBE_LOAD_CURBETotalDataLength_bits 17 +#define GEN7_MEDIA_CURBE_LOAD_CURBETotalDataLength_bits 17 +#define GEN6_MEDIA_CURBE_LOAD_CURBETotalDataLength_bits 17 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_CURBE_LOAD_CURBETotalDataLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 17; + case 10: return 17; + case 9: return 17; + case 8: return 17; + case 7: + if (devinfo->is_haswell) { + return 17; + } else { + return 17; + } + case 6: return 17; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_CURBE_LOAD_CURBETotalDataLength_start 64 +#define GEN10_MEDIA_CURBE_LOAD_CURBETotalDataLength_start 64 +#define GEN9_MEDIA_CURBE_LOAD_CURBETotalDataLength_start 64 +#define GEN8_MEDIA_CURBE_LOAD_CURBETotalDataLength_start 64 +#define GEN75_MEDIA_CURBE_LOAD_CURBETotalDataLength_start 64 +#define GEN7_MEDIA_CURBE_LOAD_CURBETotalDataLength_start 64 +#define GEN6_MEDIA_CURBE_LOAD_CURBETotalDataLength_start 64 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_CURBE_LOAD_CURBETotalDataLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 64; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_CURBE_LOAD::Command Type */ + + +#define GEN11_MEDIA_CURBE_LOAD_CommandType_bits 3 +#define GEN10_MEDIA_CURBE_LOAD_CommandType_bits 3 +#define GEN9_MEDIA_CURBE_LOAD_CommandType_bits 3 +#define GEN8_MEDIA_CURBE_LOAD_CommandType_bits 3 +#define GEN75_MEDIA_CURBE_LOAD_CommandType_bits 3 +#define GEN7_MEDIA_CURBE_LOAD_CommandType_bits 3 +#define GEN6_MEDIA_CURBE_LOAD_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_CURBE_LOAD_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_CURBE_LOAD_CommandType_start 29 +#define GEN10_MEDIA_CURBE_LOAD_CommandType_start 29 +#define GEN9_MEDIA_CURBE_LOAD_CommandType_start 29 +#define GEN8_MEDIA_CURBE_LOAD_CommandType_start 29 +#define GEN75_MEDIA_CURBE_LOAD_CommandType_start 29 +#define GEN7_MEDIA_CURBE_LOAD_CommandType_start 29 +#define GEN6_MEDIA_CURBE_LOAD_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_CURBE_LOAD_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_CURBE_LOAD::DWord Length */ + + +#define GEN11_MEDIA_CURBE_LOAD_DWordLength_bits 16 +#define GEN10_MEDIA_CURBE_LOAD_DWordLength_bits 16 +#define GEN9_MEDIA_CURBE_LOAD_DWordLength_bits 16 +#define GEN8_MEDIA_CURBE_LOAD_DWordLength_bits 16 +#define GEN75_MEDIA_CURBE_LOAD_DWordLength_bits 16 +#define GEN7_MEDIA_CURBE_LOAD_DWordLength_bits 16 +#define GEN6_MEDIA_CURBE_LOAD_DWordLength_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_CURBE_LOAD_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_CURBE_LOAD_DWordLength_start 0 +#define GEN10_MEDIA_CURBE_LOAD_DWordLength_start 0 +#define GEN9_MEDIA_CURBE_LOAD_DWordLength_start 0 +#define GEN8_MEDIA_CURBE_LOAD_DWordLength_start 0 +#define GEN75_MEDIA_CURBE_LOAD_DWordLength_start 0 +#define GEN7_MEDIA_CURBE_LOAD_DWordLength_start 0 +#define GEN6_MEDIA_CURBE_LOAD_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_CURBE_LOAD_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_CURBE_LOAD::Media Command Opcode */ + + +#define GEN11_MEDIA_CURBE_LOAD_MediaCommandOpcode_bits 3 +#define GEN10_MEDIA_CURBE_LOAD_MediaCommandOpcode_bits 3 +#define GEN9_MEDIA_CURBE_LOAD_MediaCommandOpcode_bits 3 +#define GEN8_MEDIA_CURBE_LOAD_MediaCommandOpcode_bits 3 +#define GEN75_MEDIA_CURBE_LOAD_MediaCommandOpcode_bits 3 +#define GEN7_MEDIA_CURBE_LOAD_MediaCommandOpcode_bits 3 +#define GEN6_MEDIA_CURBE_LOAD_MediaCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_CURBE_LOAD_MediaCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_CURBE_LOAD_MediaCommandOpcode_start 24 +#define GEN10_MEDIA_CURBE_LOAD_MediaCommandOpcode_start 24 +#define GEN9_MEDIA_CURBE_LOAD_MediaCommandOpcode_start 24 +#define GEN8_MEDIA_CURBE_LOAD_MediaCommandOpcode_start 24 +#define GEN75_MEDIA_CURBE_LOAD_MediaCommandOpcode_start 24 +#define GEN7_MEDIA_CURBE_LOAD_MediaCommandOpcode_start 24 +#define GEN6_MEDIA_CURBE_LOAD_MediaCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_CURBE_LOAD_MediaCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_CURBE_LOAD::Pipeline */ + + +#define GEN11_MEDIA_CURBE_LOAD_Pipeline_bits 2 +#define GEN10_MEDIA_CURBE_LOAD_Pipeline_bits 2 +#define GEN9_MEDIA_CURBE_LOAD_Pipeline_bits 2 +#define GEN8_MEDIA_CURBE_LOAD_Pipeline_bits 2 +#define GEN75_MEDIA_CURBE_LOAD_Pipeline_bits 2 +#define GEN7_MEDIA_CURBE_LOAD_Pipeline_bits 2 +#define GEN6_MEDIA_CURBE_LOAD_Pipeline_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_CURBE_LOAD_Pipeline_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_CURBE_LOAD_Pipeline_start 27 +#define GEN10_MEDIA_CURBE_LOAD_Pipeline_start 27 +#define GEN9_MEDIA_CURBE_LOAD_Pipeline_start 27 +#define GEN8_MEDIA_CURBE_LOAD_Pipeline_start 27 +#define GEN75_MEDIA_CURBE_LOAD_Pipeline_start 27 +#define GEN7_MEDIA_CURBE_LOAD_Pipeline_start 27 +#define GEN6_MEDIA_CURBE_LOAD_Pipeline_start 27 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_CURBE_LOAD_Pipeline_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_CURBE_LOAD::SubOpcode */ + + +#define GEN11_MEDIA_CURBE_LOAD_SubOpcode_bits 8 +#define GEN10_MEDIA_CURBE_LOAD_SubOpcode_bits 8 +#define GEN9_MEDIA_CURBE_LOAD_SubOpcode_bits 8 +#define GEN8_MEDIA_CURBE_LOAD_SubOpcode_bits 8 +#define GEN75_MEDIA_CURBE_LOAD_SubOpcode_bits 8 +#define GEN7_MEDIA_CURBE_LOAD_SubOpcode_bits 8 +#define GEN6_MEDIA_CURBE_LOAD_SubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_CURBE_LOAD_SubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_CURBE_LOAD_SubOpcode_start 16 +#define GEN10_MEDIA_CURBE_LOAD_SubOpcode_start 16 +#define GEN9_MEDIA_CURBE_LOAD_SubOpcode_start 16 +#define GEN8_MEDIA_CURBE_LOAD_SubOpcode_start 16 +#define GEN75_MEDIA_CURBE_LOAD_SubOpcode_start 16 +#define GEN7_MEDIA_CURBE_LOAD_SubOpcode_start 16 +#define GEN6_MEDIA_CURBE_LOAD_SubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_CURBE_LOAD_SubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_GATEWAY_STATE */ + + +#define GEN6_MEDIA_GATEWAY_STATE_length 2 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_GATEWAY_STATE_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_GATEWAY_STATE::Barrier.Byte */ + + +#define GEN6_MEDIA_GATEWAY_STATE_BarrierByte_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_GATEWAY_STATE_BarrierByte_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_MEDIA_GATEWAY_STATE_BarrierByte_start 40 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_GATEWAY_STATE_BarrierByte_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 40; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_GATEWAY_STATE::Barrier.ThreadCount */ + + +#define GEN6_MEDIA_GATEWAY_STATE_BarrierThreadCount_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_GATEWAY_STATE_BarrierThreadCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_MEDIA_GATEWAY_STATE_BarrierThreadCount_start 32 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_GATEWAY_STATE_BarrierThreadCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_GATEWAY_STATE::BarrierID */ + + +#define GEN6_MEDIA_GATEWAY_STATE_BarrierID_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_GATEWAY_STATE_BarrierID_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_MEDIA_GATEWAY_STATE_BarrierID_start 48 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_GATEWAY_STATE_BarrierID_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 48; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_GATEWAY_STATE::Command Type */ + + +#define GEN6_MEDIA_GATEWAY_STATE_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_GATEWAY_STATE_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_MEDIA_GATEWAY_STATE_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_GATEWAY_STATE_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_GATEWAY_STATE::DWord Length */ + + +#define GEN6_MEDIA_GATEWAY_STATE_DWordLength_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_GATEWAY_STATE_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_MEDIA_GATEWAY_STATE_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_GATEWAY_STATE_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_GATEWAY_STATE::Media Command Opcode */ + + +#define GEN6_MEDIA_GATEWAY_STATE_MediaCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_GATEWAY_STATE_MediaCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_MEDIA_GATEWAY_STATE_MediaCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_GATEWAY_STATE_MediaCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 24; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_GATEWAY_STATE::Pipeline */ + + +#define GEN6_MEDIA_GATEWAY_STATE_Pipeline_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_GATEWAY_STATE_Pipeline_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_MEDIA_GATEWAY_STATE_Pipeline_start 27 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_GATEWAY_STATE_Pipeline_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_GATEWAY_STATE::SubOpcode */ + + +#define GEN6_MEDIA_GATEWAY_STATE_SubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_GATEWAY_STATE_SubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_MEDIA_GATEWAY_STATE_SubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_GATEWAY_STATE_SubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_INTERFACE_DESCRIPTOR_LOAD */ + + +#define GEN11_MEDIA_INTERFACE_DESCRIPTOR_LOAD_length 4 +#define GEN10_MEDIA_INTERFACE_DESCRIPTOR_LOAD_length 4 +#define GEN9_MEDIA_INTERFACE_DESCRIPTOR_LOAD_length 4 +#define GEN8_MEDIA_INTERFACE_DESCRIPTOR_LOAD_length 4 +#define GEN75_MEDIA_INTERFACE_DESCRIPTOR_LOAD_length 4 +#define GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD_length 4 +#define GEN6_MEDIA_INTERFACE_DESCRIPTOR_LOAD_length 4 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_INTERFACE_DESCRIPTOR_LOAD_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_INTERFACE_DESCRIPTOR_LOAD::Command Type */ + + +#define GEN11_MEDIA_INTERFACE_DESCRIPTOR_LOAD_CommandType_bits 3 +#define GEN10_MEDIA_INTERFACE_DESCRIPTOR_LOAD_CommandType_bits 3 +#define GEN9_MEDIA_INTERFACE_DESCRIPTOR_LOAD_CommandType_bits 3 +#define GEN8_MEDIA_INTERFACE_DESCRIPTOR_LOAD_CommandType_bits 3 +#define GEN75_MEDIA_INTERFACE_DESCRIPTOR_LOAD_CommandType_bits 3 +#define GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD_CommandType_bits 3 +#define GEN6_MEDIA_INTERFACE_DESCRIPTOR_LOAD_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_INTERFACE_DESCRIPTOR_LOAD_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_INTERFACE_DESCRIPTOR_LOAD_CommandType_start 29 +#define GEN10_MEDIA_INTERFACE_DESCRIPTOR_LOAD_CommandType_start 29 +#define GEN9_MEDIA_INTERFACE_DESCRIPTOR_LOAD_CommandType_start 29 +#define GEN8_MEDIA_INTERFACE_DESCRIPTOR_LOAD_CommandType_start 29 +#define GEN75_MEDIA_INTERFACE_DESCRIPTOR_LOAD_CommandType_start 29 +#define GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD_CommandType_start 29 +#define GEN6_MEDIA_INTERFACE_DESCRIPTOR_LOAD_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_INTERFACE_DESCRIPTOR_LOAD_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_INTERFACE_DESCRIPTOR_LOAD::DWord Length */ + + +#define GEN11_MEDIA_INTERFACE_DESCRIPTOR_LOAD_DWordLength_bits 16 +#define GEN10_MEDIA_INTERFACE_DESCRIPTOR_LOAD_DWordLength_bits 16 +#define GEN9_MEDIA_INTERFACE_DESCRIPTOR_LOAD_DWordLength_bits 16 +#define GEN8_MEDIA_INTERFACE_DESCRIPTOR_LOAD_DWordLength_bits 16 +#define GEN75_MEDIA_INTERFACE_DESCRIPTOR_LOAD_DWordLength_bits 16 +#define GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD_DWordLength_bits 16 +#define GEN6_MEDIA_INTERFACE_DESCRIPTOR_LOAD_DWordLength_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_INTERFACE_DESCRIPTOR_LOAD_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_INTERFACE_DESCRIPTOR_LOAD_DWordLength_start 0 +#define GEN10_MEDIA_INTERFACE_DESCRIPTOR_LOAD_DWordLength_start 0 +#define GEN9_MEDIA_INTERFACE_DESCRIPTOR_LOAD_DWordLength_start 0 +#define GEN8_MEDIA_INTERFACE_DESCRIPTOR_LOAD_DWordLength_start 0 +#define GEN75_MEDIA_INTERFACE_DESCRIPTOR_LOAD_DWordLength_start 0 +#define GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD_DWordLength_start 0 +#define GEN6_MEDIA_INTERFACE_DESCRIPTOR_LOAD_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_INTERFACE_DESCRIPTOR_LOAD_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_INTERFACE_DESCRIPTOR_LOAD::Interface Descriptor Data Start Address */ + + +#define GEN11_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorDataStartAddress_bits 32 +#define GEN10_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorDataStartAddress_bits 32 +#define GEN9_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorDataStartAddress_bits 32 +#define GEN8_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorDataStartAddress_bits 32 +#define GEN75_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorDataStartAddress_bits 32 +#define GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorDataStartAddress_bits 32 +#define GEN6_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorDataStartAddress_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorDataStartAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorDataStartAddress_start 96 +#define GEN10_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorDataStartAddress_start 96 +#define GEN9_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorDataStartAddress_start 96 +#define GEN8_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorDataStartAddress_start 96 +#define GEN75_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorDataStartAddress_start 96 +#define GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorDataStartAddress_start 96 +#define GEN6_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorDataStartAddress_start 96 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorDataStartAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 96; + case 10: return 96; + case 9: return 96; + case 8: return 96; + case 7: + if (devinfo->is_haswell) { + return 96; + } else { + return 96; + } + case 6: return 96; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_INTERFACE_DESCRIPTOR_LOAD::Interface Descriptor Total Length */ + + +#define GEN11_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorTotalLength_bits 17 +#define GEN10_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorTotalLength_bits 17 +#define GEN9_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorTotalLength_bits 17 +#define GEN8_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorTotalLength_bits 17 +#define GEN75_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorTotalLength_bits 17 +#define GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorTotalLength_bits 17 +#define GEN6_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorTotalLength_bits 17 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorTotalLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 17; + case 10: return 17; + case 9: return 17; + case 8: return 17; + case 7: + if (devinfo->is_haswell) { + return 17; + } else { + return 17; + } + case 6: return 17; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorTotalLength_start 64 +#define GEN10_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorTotalLength_start 64 +#define GEN9_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorTotalLength_start 64 +#define GEN8_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorTotalLength_start 64 +#define GEN75_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorTotalLength_start 64 +#define GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorTotalLength_start 64 +#define GEN6_MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorTotalLength_start 64 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_INTERFACE_DESCRIPTOR_LOAD_InterfaceDescriptorTotalLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 64; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_INTERFACE_DESCRIPTOR_LOAD::Media Command Opcode */ + + +#define GEN11_MEDIA_INTERFACE_DESCRIPTOR_LOAD_MediaCommandOpcode_bits 3 +#define GEN10_MEDIA_INTERFACE_DESCRIPTOR_LOAD_MediaCommandOpcode_bits 3 +#define GEN9_MEDIA_INTERFACE_DESCRIPTOR_LOAD_MediaCommandOpcode_bits 3 +#define GEN8_MEDIA_INTERFACE_DESCRIPTOR_LOAD_MediaCommandOpcode_bits 3 +#define GEN75_MEDIA_INTERFACE_DESCRIPTOR_LOAD_MediaCommandOpcode_bits 3 +#define GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD_MediaCommandOpcode_bits 3 +#define GEN6_MEDIA_INTERFACE_DESCRIPTOR_LOAD_MediaCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_INTERFACE_DESCRIPTOR_LOAD_MediaCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_INTERFACE_DESCRIPTOR_LOAD_MediaCommandOpcode_start 24 +#define GEN10_MEDIA_INTERFACE_DESCRIPTOR_LOAD_MediaCommandOpcode_start 24 +#define GEN9_MEDIA_INTERFACE_DESCRIPTOR_LOAD_MediaCommandOpcode_start 24 +#define GEN8_MEDIA_INTERFACE_DESCRIPTOR_LOAD_MediaCommandOpcode_start 24 +#define GEN75_MEDIA_INTERFACE_DESCRIPTOR_LOAD_MediaCommandOpcode_start 24 +#define GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD_MediaCommandOpcode_start 24 +#define GEN6_MEDIA_INTERFACE_DESCRIPTOR_LOAD_MediaCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_INTERFACE_DESCRIPTOR_LOAD_MediaCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_INTERFACE_DESCRIPTOR_LOAD::Pipeline */ + + +#define GEN11_MEDIA_INTERFACE_DESCRIPTOR_LOAD_Pipeline_bits 2 +#define GEN10_MEDIA_INTERFACE_DESCRIPTOR_LOAD_Pipeline_bits 2 +#define GEN9_MEDIA_INTERFACE_DESCRIPTOR_LOAD_Pipeline_bits 2 +#define GEN8_MEDIA_INTERFACE_DESCRIPTOR_LOAD_Pipeline_bits 2 +#define GEN75_MEDIA_INTERFACE_DESCRIPTOR_LOAD_Pipeline_bits 2 +#define GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD_Pipeline_bits 2 +#define GEN6_MEDIA_INTERFACE_DESCRIPTOR_LOAD_Pipeline_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_INTERFACE_DESCRIPTOR_LOAD_Pipeline_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_INTERFACE_DESCRIPTOR_LOAD_Pipeline_start 27 +#define GEN10_MEDIA_INTERFACE_DESCRIPTOR_LOAD_Pipeline_start 27 +#define GEN9_MEDIA_INTERFACE_DESCRIPTOR_LOAD_Pipeline_start 27 +#define GEN8_MEDIA_INTERFACE_DESCRIPTOR_LOAD_Pipeline_start 27 +#define GEN75_MEDIA_INTERFACE_DESCRIPTOR_LOAD_Pipeline_start 27 +#define GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD_Pipeline_start 27 +#define GEN6_MEDIA_INTERFACE_DESCRIPTOR_LOAD_Pipeline_start 27 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_INTERFACE_DESCRIPTOR_LOAD_Pipeline_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_INTERFACE_DESCRIPTOR_LOAD::SubOpcode */ + + +#define GEN11_MEDIA_INTERFACE_DESCRIPTOR_LOAD_SubOpcode_bits 8 +#define GEN10_MEDIA_INTERFACE_DESCRIPTOR_LOAD_SubOpcode_bits 8 +#define GEN9_MEDIA_INTERFACE_DESCRIPTOR_LOAD_SubOpcode_bits 8 +#define GEN8_MEDIA_INTERFACE_DESCRIPTOR_LOAD_SubOpcode_bits 8 +#define GEN75_MEDIA_INTERFACE_DESCRIPTOR_LOAD_SubOpcode_bits 8 +#define GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD_SubOpcode_bits 8 +#define GEN6_MEDIA_INTERFACE_DESCRIPTOR_LOAD_SubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_INTERFACE_DESCRIPTOR_LOAD_SubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_INTERFACE_DESCRIPTOR_LOAD_SubOpcode_start 16 +#define GEN10_MEDIA_INTERFACE_DESCRIPTOR_LOAD_SubOpcode_start 16 +#define GEN9_MEDIA_INTERFACE_DESCRIPTOR_LOAD_SubOpcode_start 16 +#define GEN8_MEDIA_INTERFACE_DESCRIPTOR_LOAD_SubOpcode_start 16 +#define GEN75_MEDIA_INTERFACE_DESCRIPTOR_LOAD_SubOpcode_start 16 +#define GEN7_MEDIA_INTERFACE_DESCRIPTOR_LOAD_SubOpcode_start 16 +#define GEN6_MEDIA_INTERFACE_DESCRIPTOR_LOAD_SubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_INTERFACE_DESCRIPTOR_LOAD_SubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT */ + + + + + +/* MEDIA_OBJECT::Block Color */ + + +#define GEN11_MEDIA_OBJECT_BlockColor_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_BlockColor_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_BlockColor_start 176 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_BlockColor_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 176; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT::Children Present */ + + +#define GEN11_MEDIA_OBJECT_ChildrenPresent_bits 1 +#define GEN10_MEDIA_OBJECT_ChildrenPresent_bits 1 +#define GEN9_MEDIA_OBJECT_ChildrenPresent_bits 1 +#define GEN8_MEDIA_OBJECT_ChildrenPresent_bits 1 +#define GEN75_MEDIA_OBJECT_ChildrenPresent_bits 1 +#define GEN7_MEDIA_OBJECT_ChildrenPresent_bits 1 +#define GEN6_MEDIA_OBJECT_ChildrenPresent_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_ChildrenPresent_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_ChildrenPresent_start 95 +#define GEN10_MEDIA_OBJECT_ChildrenPresent_start 95 +#define GEN9_MEDIA_OBJECT_ChildrenPresent_start 95 +#define GEN8_MEDIA_OBJECT_ChildrenPresent_start 95 +#define GEN75_MEDIA_OBJECT_ChildrenPresent_start 95 +#define GEN7_MEDIA_OBJECT_ChildrenPresent_start 95 +#define GEN6_MEDIA_OBJECT_ChildrenPresent_start 95 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_ChildrenPresent_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 95; + case 10: return 95; + case 9: return 95; + case 8: return 95; + case 7: + if (devinfo->is_haswell) { + return 95; + } else { + return 95; + } + case 6: return 95; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT::Command Type */ + + +#define GEN11_MEDIA_OBJECT_CommandType_bits 3 +#define GEN10_MEDIA_OBJECT_CommandType_bits 3 +#define GEN9_MEDIA_OBJECT_CommandType_bits 3 +#define GEN8_MEDIA_OBJECT_CommandType_bits 3 +#define GEN75_MEDIA_OBJECT_CommandType_bits 3 +#define GEN7_MEDIA_OBJECT_CommandType_bits 3 +#define GEN6_MEDIA_OBJECT_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_CommandType_start 29 +#define GEN10_MEDIA_OBJECT_CommandType_start 29 +#define GEN9_MEDIA_OBJECT_CommandType_start 29 +#define GEN8_MEDIA_OBJECT_CommandType_start 29 +#define GEN75_MEDIA_OBJECT_CommandType_start 29 +#define GEN7_MEDIA_OBJECT_CommandType_start 29 +#define GEN6_MEDIA_OBJECT_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT::DWord Length */ + + +#define GEN11_MEDIA_OBJECT_DWordLength_bits 15 +#define GEN10_MEDIA_OBJECT_DWordLength_bits 15 +#define GEN9_MEDIA_OBJECT_DWordLength_bits 16 +#define GEN8_MEDIA_OBJECT_DWordLength_bits 16 +#define GEN75_MEDIA_OBJECT_DWordLength_bits 16 +#define GEN7_MEDIA_OBJECT_DWordLength_bits 16 +#define GEN6_MEDIA_OBJECT_DWordLength_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 15; + case 10: return 15; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_DWordLength_start 0 +#define GEN10_MEDIA_OBJECT_DWordLength_start 0 +#define GEN9_MEDIA_OBJECT_DWordLength_start 0 +#define GEN8_MEDIA_OBJECT_DWordLength_start 0 +#define GEN75_MEDIA_OBJECT_DWordLength_start 0 +#define GEN7_MEDIA_OBJECT_DWordLength_start 0 +#define GEN6_MEDIA_OBJECT_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT::Force Destination */ + + +#define GEN11_MEDIA_OBJECT_ForceDestination_bits 1 +#define GEN10_MEDIA_OBJECT_ForceDestination_bits 1 +#define GEN9_MEDIA_OBJECT_ForceDestination_bits 1 +#define GEN8_MEDIA_OBJECT_ForceDestination_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_ForceDestination_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_ForceDestination_start 86 +#define GEN10_MEDIA_OBJECT_ForceDestination_start 86 +#define GEN9_MEDIA_OBJECT_ForceDestination_start 86 +#define GEN8_MEDIA_OBJECT_ForceDestination_start 86 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_ForceDestination_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 86; + case 10: return 86; + case 9: return 86; + case 8: return 86; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT::Half-Slice Destination Select */ + + +#define GEN75_MEDIA_OBJECT_HalfSliceDestinationSelect_bits 2 +#define GEN7_MEDIA_OBJECT_HalfSliceDestinationSelect_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_HalfSliceDestinationSelect_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_MEDIA_OBJECT_HalfSliceDestinationSelect_start 81 +#define GEN7_MEDIA_OBJECT_HalfSliceDestinationSelect_start 81 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_HalfSliceDestinationSelect_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 81; + } else { + return 81; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT::Indirect Data Length */ + + +#define GEN11_MEDIA_OBJECT_IndirectDataLength_bits 17 +#define GEN10_MEDIA_OBJECT_IndirectDataLength_bits 17 +#define GEN9_MEDIA_OBJECT_IndirectDataLength_bits 17 +#define GEN8_MEDIA_OBJECT_IndirectDataLength_bits 17 +#define GEN75_MEDIA_OBJECT_IndirectDataLength_bits 17 +#define GEN7_MEDIA_OBJECT_IndirectDataLength_bits 17 +#define GEN6_MEDIA_OBJECT_IndirectDataLength_bits 17 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_IndirectDataLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 17; + case 10: return 17; + case 9: return 17; + case 8: return 17; + case 7: + if (devinfo->is_haswell) { + return 17; + } else { + return 17; + } + case 6: return 17; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_IndirectDataLength_start 64 +#define GEN10_MEDIA_OBJECT_IndirectDataLength_start 64 +#define GEN9_MEDIA_OBJECT_IndirectDataLength_start 64 +#define GEN8_MEDIA_OBJECT_IndirectDataLength_start 64 +#define GEN75_MEDIA_OBJECT_IndirectDataLength_start 64 +#define GEN7_MEDIA_OBJECT_IndirectDataLength_start 64 +#define GEN6_MEDIA_OBJECT_IndirectDataLength_start 64 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_IndirectDataLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 64; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT::Indirect Data Start Address */ + + +#define GEN11_MEDIA_OBJECT_IndirectDataStartAddress_bits 32 +#define GEN10_MEDIA_OBJECT_IndirectDataStartAddress_bits 32 +#define GEN9_MEDIA_OBJECT_IndirectDataStartAddress_bits 32 +#define GEN8_MEDIA_OBJECT_IndirectDataStartAddress_bits 32 +#define GEN75_MEDIA_OBJECT_IndirectDataStartAddress_bits 32 +#define GEN7_MEDIA_OBJECT_IndirectDataStartAddress_bits 32 +#define GEN6_MEDIA_OBJECT_IndirectDataStartAddress_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_IndirectDataStartAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_IndirectDataStartAddress_start 96 +#define GEN10_MEDIA_OBJECT_IndirectDataStartAddress_start 96 +#define GEN9_MEDIA_OBJECT_IndirectDataStartAddress_start 96 +#define GEN8_MEDIA_OBJECT_IndirectDataStartAddress_start 96 +#define GEN75_MEDIA_OBJECT_IndirectDataStartAddress_start 96 +#define GEN7_MEDIA_OBJECT_IndirectDataStartAddress_start 96 +#define GEN6_MEDIA_OBJECT_IndirectDataStartAddress_start 96 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_IndirectDataStartAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 96; + case 10: return 96; + case 9: return 96; + case 8: return 96; + case 7: + if (devinfo->is_haswell) { + return 96; + } else { + return 96; + } + case 6: return 96; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT::Inline Data */ + + +#define GEN11_MEDIA_OBJECT_InlineData_bits 32 +#define GEN10_MEDIA_OBJECT_InlineData_bits 32 +#define GEN9_MEDIA_OBJECT_InlineData_bits 32 +#define GEN8_MEDIA_OBJECT_InlineData_bits 32 +#define GEN75_MEDIA_OBJECT_InlineData_bits 32 +#define GEN7_MEDIA_OBJECT_InlineData_bits 32 +#define GEN6_MEDIA_OBJECT_InlineData_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_InlineData_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_InlineData_start 0 +#define GEN10_MEDIA_OBJECT_InlineData_start 0 +#define GEN9_MEDIA_OBJECT_InlineData_start 0 +#define GEN8_MEDIA_OBJECT_InlineData_start 0 +#define GEN75_MEDIA_OBJECT_InlineData_start 0 +#define GEN7_MEDIA_OBJECT_InlineData_start 0 +#define GEN6_MEDIA_OBJECT_InlineData_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_InlineData_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT::Interface Descriptor Offset */ + + +#define GEN11_MEDIA_OBJECT_InterfaceDescriptorOffset_bits 6 +#define GEN10_MEDIA_OBJECT_InterfaceDescriptorOffset_bits 6 +#define GEN9_MEDIA_OBJECT_InterfaceDescriptorOffset_bits 6 +#define GEN8_MEDIA_OBJECT_InterfaceDescriptorOffset_bits 6 +#define GEN75_MEDIA_OBJECT_InterfaceDescriptorOffset_bits 6 +#define GEN7_MEDIA_OBJECT_InterfaceDescriptorOffset_bits 5 +#define GEN6_MEDIA_OBJECT_InterfaceDescriptorOffset_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_InterfaceDescriptorOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 5; + } + case 6: return 5; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_InterfaceDescriptorOffset_start 32 +#define GEN10_MEDIA_OBJECT_InterfaceDescriptorOffset_start 32 +#define GEN9_MEDIA_OBJECT_InterfaceDescriptorOffset_start 32 +#define GEN8_MEDIA_OBJECT_InterfaceDescriptorOffset_start 32 +#define GEN75_MEDIA_OBJECT_InterfaceDescriptorOffset_start 32 +#define GEN7_MEDIA_OBJECT_InterfaceDescriptorOffset_start 32 +#define GEN6_MEDIA_OBJECT_InterfaceDescriptorOffset_start 32 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_InterfaceDescriptorOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT::Media Command Opcode */ + + +#define GEN11_MEDIA_OBJECT_MediaCommandOpcode_bits 3 +#define GEN10_MEDIA_OBJECT_MediaCommandOpcode_bits 3 +#define GEN9_MEDIA_OBJECT_MediaCommandOpcode_bits 3 +#define GEN8_MEDIA_OBJECT_MediaCommandOpcode_bits 3 +#define GEN75_MEDIA_OBJECT_MediaCommandOpcode_bits 3 +#define GEN7_MEDIA_OBJECT_MediaCommandOpcode_bits 3 +#define GEN6_MEDIA_OBJECT_MediaCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_MediaCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_MediaCommandOpcode_start 24 +#define GEN10_MEDIA_OBJECT_MediaCommandOpcode_start 24 +#define GEN9_MEDIA_OBJECT_MediaCommandOpcode_start 24 +#define GEN8_MEDIA_OBJECT_MediaCommandOpcode_start 24 +#define GEN75_MEDIA_OBJECT_MediaCommandOpcode_start 24 +#define GEN7_MEDIA_OBJECT_MediaCommandOpcode_start 24 +#define GEN6_MEDIA_OBJECT_MediaCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_MediaCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT::Media Command Pipeline */ + + +#define GEN11_MEDIA_OBJECT_MediaCommandPipeline_bits 2 +#define GEN10_MEDIA_OBJECT_MediaCommandPipeline_bits 2 +#define GEN9_MEDIA_OBJECT_MediaCommandPipeline_bits 2 +#define GEN8_MEDIA_OBJECT_MediaCommandPipeline_bits 2 +#define GEN75_MEDIA_OBJECT_MediaCommandPipeline_bits 2 +#define GEN7_MEDIA_OBJECT_MediaCommandPipeline_bits 2 +#define GEN6_MEDIA_OBJECT_MediaCommandPipeline_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_MediaCommandPipeline_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_MediaCommandPipeline_start 27 +#define GEN10_MEDIA_OBJECT_MediaCommandPipeline_start 27 +#define GEN9_MEDIA_OBJECT_MediaCommandPipeline_start 27 +#define GEN8_MEDIA_OBJECT_MediaCommandPipeline_start 27 +#define GEN75_MEDIA_OBJECT_MediaCommandPipeline_start 27 +#define GEN7_MEDIA_OBJECT_MediaCommandPipeline_start 27 +#define GEN6_MEDIA_OBJECT_MediaCommandPipeline_start 27 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_MediaCommandPipeline_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT::Media Command Sub-Opcode */ + + +#define GEN11_MEDIA_OBJECT_MediaCommandSubOpcode_bits 8 +#define GEN10_MEDIA_OBJECT_MediaCommandSubOpcode_bits 8 +#define GEN9_MEDIA_OBJECT_MediaCommandSubOpcode_bits 8 +#define GEN8_MEDIA_OBJECT_MediaCommandSubOpcode_bits 8 +#define GEN75_MEDIA_OBJECT_MediaCommandSubOpcode_bits 8 +#define GEN7_MEDIA_OBJECT_MediaCommandSubOpcode_bits 8 +#define GEN6_MEDIA_OBJECT_MediaCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_MediaCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_MediaCommandSubOpcode_start 16 +#define GEN10_MEDIA_OBJECT_MediaCommandSubOpcode_start 16 +#define GEN9_MEDIA_OBJECT_MediaCommandSubOpcode_start 16 +#define GEN8_MEDIA_OBJECT_MediaCommandSubOpcode_start 16 +#define GEN75_MEDIA_OBJECT_MediaCommandSubOpcode_start 16 +#define GEN7_MEDIA_OBJECT_MediaCommandSubOpcode_start 16 +#define GEN6_MEDIA_OBJECT_MediaCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_MediaCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT::Scoreboard Color */ + + +#define GEN10_MEDIA_OBJECT_ScoreboardColor_bits 4 +#define GEN9_MEDIA_OBJECT_ScoreboardColor_bits 4 +#define GEN8_MEDIA_OBJECT_ScoreboardColor_bits 4 +#define GEN75_MEDIA_OBJECT_ScoreboardColor_bits 4 +#define GEN7_MEDIA_OBJECT_ScoreboardColor_bits 4 +#define GEN6_MEDIA_OBJECT_ScoreboardColor_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_ScoreboardColor_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MEDIA_OBJECT_ScoreboardColor_start 176 +#define GEN9_MEDIA_OBJECT_ScoreboardColor_start 176 +#define GEN8_MEDIA_OBJECT_ScoreboardColor_start 176 +#define GEN75_MEDIA_OBJECT_ScoreboardColor_start 176 +#define GEN7_MEDIA_OBJECT_ScoreboardColor_start 176 +#define GEN6_MEDIA_OBJECT_ScoreboardColor_start 176 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_ScoreboardColor_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 176; + case 9: return 176; + case 8: return 176; + case 7: + if (devinfo->is_haswell) { + return 176; + } else { + return 176; + } + case 6: return 176; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT::Scoreboard Mask */ + + +#define GEN10_MEDIA_OBJECT_ScoreboardMask_bits 8 +#define GEN9_MEDIA_OBJECT_ScoreboardMask_bits 8 +#define GEN8_MEDIA_OBJECT_ScoreboardMask_bits 8 +#define GEN75_MEDIA_OBJECT_ScoreboardMask_bits 8 +#define GEN7_MEDIA_OBJECT_ScoreboardMask_bits 8 +#define GEN6_MEDIA_OBJECT_ScoreboardMask_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_ScoreboardMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MEDIA_OBJECT_ScoreboardMask_start 160 +#define GEN9_MEDIA_OBJECT_ScoreboardMask_start 160 +#define GEN8_MEDIA_OBJECT_ScoreboardMask_start 160 +#define GEN75_MEDIA_OBJECT_ScoreboardMask_start 160 +#define GEN7_MEDIA_OBJECT_ScoreboardMask_start 160 +#define GEN6_MEDIA_OBJECT_ScoreboardMask_start 160 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_ScoreboardMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 160; + case 9: return 160; + case 8: return 160; + case 7: + if (devinfo->is_haswell) { + return 160; + } else { + return 160; + } + case 6: return 160; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT::Scoreboard X */ + + +#define GEN10_MEDIA_OBJECT_ScoreboardX_bits 9 +#define GEN9_MEDIA_OBJECT_ScoreboardX_bits 9 +#define GEN8_MEDIA_OBJECT_ScoreboardX_bits 9 +#define GEN75_MEDIA_OBJECT_ScoreboardX_bits 9 +#define GEN7_MEDIA_OBJECT_ScoreboardX_bits 9 +#define GEN6_MEDIA_OBJECT_ScoreboardX_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_ScoreboardX_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 9; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 9; + } + case 6: return 9; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MEDIA_OBJECT_ScoreboardX_start 128 +#define GEN9_MEDIA_OBJECT_ScoreboardX_start 128 +#define GEN8_MEDIA_OBJECT_ScoreboardX_start 128 +#define GEN75_MEDIA_OBJECT_ScoreboardX_start 128 +#define GEN7_MEDIA_OBJECT_ScoreboardX_start 128 +#define GEN6_MEDIA_OBJECT_ScoreboardX_start 128 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_ScoreboardX_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 128; + case 9: return 128; + case 8: return 128; + case 7: + if (devinfo->is_haswell) { + return 128; + } else { + return 128; + } + case 6: return 128; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT::Scoredboard Y */ + + +#define GEN10_MEDIA_OBJECT_ScoredboardY_bits 9 +#define GEN9_MEDIA_OBJECT_ScoredboardY_bits 9 +#define GEN8_MEDIA_OBJECT_ScoredboardY_bits 9 +#define GEN75_MEDIA_OBJECT_ScoredboardY_bits 9 +#define GEN7_MEDIA_OBJECT_ScoredboardY_bits 9 +#define GEN6_MEDIA_OBJECT_ScoredboardY_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_ScoredboardY_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 9; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 9; + } + case 6: return 9; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MEDIA_OBJECT_ScoredboardY_start 144 +#define GEN9_MEDIA_OBJECT_ScoredboardY_start 144 +#define GEN8_MEDIA_OBJECT_ScoredboardY_start 144 +#define GEN75_MEDIA_OBJECT_ScoredboardY_start 144 +#define GEN7_MEDIA_OBJECT_ScoredboardY_start 144 +#define GEN6_MEDIA_OBJECT_ScoredboardY_start 144 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_ScoredboardY_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 144; + case 9: return 144; + case 8: return 144; + case 7: + if (devinfo->is_haswell) { + return 144; + } else { + return 144; + } + case 6: return 144; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT::Slice Destination Select */ + + +#define GEN11_MEDIA_OBJECT_SliceDestinationSelect_bits 2 +#define GEN10_MEDIA_OBJECT_SliceDestinationSelect_bits 2 +#define GEN9_MEDIA_OBJECT_SliceDestinationSelect_bits 2 +#define GEN8_MEDIA_OBJECT_SliceDestinationSelect_bits 2 +#define GEN75_MEDIA_OBJECT_SliceDestinationSelect_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_SliceDestinationSelect_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_SliceDestinationSelect_start 83 +#define GEN10_MEDIA_OBJECT_SliceDestinationSelect_start 83 +#define GEN9_MEDIA_OBJECT_SliceDestinationSelect_start 83 +#define GEN8_MEDIA_OBJECT_SliceDestinationSelect_start 83 +#define GEN75_MEDIA_OBJECT_SliceDestinationSelect_start 83 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_SliceDestinationSelect_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 83; + case 10: return 83; + case 9: return 83; + case 8: return 83; + case 7: + if (devinfo->is_haswell) { + return 83; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT::Slice Destination Select MSBs */ + + +#define GEN11_MEDIA_OBJECT_SliceDestinationSelectMSBs_bits 2 +#define GEN10_MEDIA_OBJECT_SliceDestinationSelectMSBs_bits 2 +#define GEN9_MEDIA_OBJECT_SliceDestinationSelectMSBs_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_SliceDestinationSelectMSBs_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_SliceDestinationSelectMSBs_start 89 +#define GEN10_MEDIA_OBJECT_SliceDestinationSelectMSBs_start 89 +#define GEN9_MEDIA_OBJECT_SliceDestinationSelectMSBs_start 89 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_SliceDestinationSelectMSBs_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 89; + case 10: return 89; + case 9: return 89; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT::SubSlice Destination Select */ + + +#define GEN11_MEDIA_OBJECT_SubSliceDestinationSelect_bits 2 +#define GEN10_MEDIA_OBJECT_SubSliceDestinationSelect_bits 2 +#define GEN9_MEDIA_OBJECT_SubSliceDestinationSelect_bits 2 +#define GEN8_MEDIA_OBJECT_SubSliceDestinationSelect_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_SubSliceDestinationSelect_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_SubSliceDestinationSelect_start 81 +#define GEN10_MEDIA_OBJECT_SubSliceDestinationSelect_start 81 +#define GEN9_MEDIA_OBJECT_SubSliceDestinationSelect_start 81 +#define GEN8_MEDIA_OBJECT_SubSliceDestinationSelect_start 81 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_SubSliceDestinationSelect_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 81; + case 10: return 81; + case 9: return 81; + case 8: return 81; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT::Thread Synchronization */ + + +#define GEN11_MEDIA_OBJECT_ThreadSynchronization_bits 1 +#define GEN10_MEDIA_OBJECT_ThreadSynchronization_bits 1 +#define GEN9_MEDIA_OBJECT_ThreadSynchronization_bits 1 +#define GEN8_MEDIA_OBJECT_ThreadSynchronization_bits 1 +#define GEN75_MEDIA_OBJECT_ThreadSynchronization_bits 1 +#define GEN7_MEDIA_OBJECT_ThreadSynchronization_bits 1 +#define GEN6_MEDIA_OBJECT_ThreadSynchronization_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_ThreadSynchronization_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_ThreadSynchronization_start 88 +#define GEN10_MEDIA_OBJECT_ThreadSynchronization_start 88 +#define GEN9_MEDIA_OBJECT_ThreadSynchronization_start 88 +#define GEN8_MEDIA_OBJECT_ThreadSynchronization_start 88 +#define GEN75_MEDIA_OBJECT_ThreadSynchronization_start 88 +#define GEN7_MEDIA_OBJECT_ThreadSynchronization_start 88 +#define GEN6_MEDIA_OBJECT_ThreadSynchronization_start 88 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_ThreadSynchronization_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 88; + case 10: return 88; + case 9: return 88; + case 8: return 88; + case 7: + if (devinfo->is_haswell) { + return 88; + } else { + return 88; + } + case 6: return 88; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT::Use Scoreboard */ + + +#define GEN10_MEDIA_OBJECT_UseScoreboard_bits 1 +#define GEN9_MEDIA_OBJECT_UseScoreboard_bits 1 +#define GEN8_MEDIA_OBJECT_UseScoreboard_bits 1 +#define GEN75_MEDIA_OBJECT_UseScoreboard_bits 1 +#define GEN7_MEDIA_OBJECT_UseScoreboard_bits 1 +#define GEN6_MEDIA_OBJECT_UseScoreboard_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_UseScoreboard_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MEDIA_OBJECT_UseScoreboard_start 85 +#define GEN9_MEDIA_OBJECT_UseScoreboard_start 85 +#define GEN8_MEDIA_OBJECT_UseScoreboard_start 85 +#define GEN75_MEDIA_OBJECT_UseScoreboard_start 85 +#define GEN7_MEDIA_OBJECT_UseScoreboard_start 85 +#define GEN6_MEDIA_OBJECT_UseScoreboard_start 85 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_UseScoreboard_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 85; + case 9: return 85; + case 8: return 85; + case 7: + if (devinfo->is_haswell) { + return 85; + } else { + return 85; + } + case 6: return 85; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT::X Position */ + + +#define GEN11_MEDIA_OBJECT_XPosition_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_XPosition_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 9; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_XPosition_start 128 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_XPosition_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 128; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT::Y Position */ + + +#define GEN11_MEDIA_OBJECT_YPosition_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_YPosition_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 9; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_YPosition_start 144 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_YPosition_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 144; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_GRPID */ + + + + + +/* MEDIA_OBJECT_GRPID::Block Color */ + + +#define GEN11_MEDIA_OBJECT_GRPID_BlockColor_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_BlockColor_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_GRPID_BlockColor_start 176 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_BlockColor_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 176; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_GRPID::Command Type */ + + +#define GEN11_MEDIA_OBJECT_GRPID_CommandType_bits 3 +#define GEN10_MEDIA_OBJECT_GRPID_CommandType_bits 3 +#define GEN9_MEDIA_OBJECT_GRPID_CommandType_bits 3 +#define GEN8_MEDIA_OBJECT_GRPID_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_GRPID_CommandType_start 29 +#define GEN10_MEDIA_OBJECT_GRPID_CommandType_start 29 +#define GEN9_MEDIA_OBJECT_GRPID_CommandType_start 29 +#define GEN8_MEDIA_OBJECT_GRPID_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_GRPID::DWord Length */ + + +#define GEN11_MEDIA_OBJECT_GRPID_DWordLength_bits 16 +#define GEN10_MEDIA_OBJECT_GRPID_DWordLength_bits 16 +#define GEN9_MEDIA_OBJECT_GRPID_DWordLength_bits 16 +#define GEN8_MEDIA_OBJECT_GRPID_DWordLength_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_GRPID_DWordLength_start 0 +#define GEN10_MEDIA_OBJECT_GRPID_DWordLength_start 0 +#define GEN9_MEDIA_OBJECT_GRPID_DWordLength_start 0 +#define GEN8_MEDIA_OBJECT_GRPID_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_GRPID::End of Thread Group */ + + +#define GEN11_MEDIA_OBJECT_GRPID_EndofThreadGroup_bits 1 +#define GEN10_MEDIA_OBJECT_GRPID_EndofThreadGroup_bits 1 +#define GEN9_MEDIA_OBJECT_GRPID_EndofThreadGroup_bits 1 +#define GEN8_MEDIA_OBJECT_GRPID_EndofThreadGroup_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_EndofThreadGroup_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_GRPID_EndofThreadGroup_start 87 +#define GEN10_MEDIA_OBJECT_GRPID_EndofThreadGroup_start 87 +#define GEN9_MEDIA_OBJECT_GRPID_EndofThreadGroup_start 87 +#define GEN8_MEDIA_OBJECT_GRPID_EndofThreadGroup_start 87 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_EndofThreadGroup_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 87; + case 10: return 87; + case 9: return 87; + case 8: return 87; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_GRPID::Force Destination */ + + +#define GEN9_MEDIA_OBJECT_GRPID_ForceDestination_bits 1 +#define GEN8_MEDIA_OBJECT_GRPID_ForceDestination_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_ForceDestination_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_MEDIA_OBJECT_GRPID_ForceDestination_start 86 +#define GEN8_MEDIA_OBJECT_GRPID_ForceDestination_start 86 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_ForceDestination_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 86; + case 8: return 86; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_GRPID::GroupID */ + + +#define GEN11_MEDIA_OBJECT_GRPID_GroupID_bits 32 +#define GEN10_MEDIA_OBJECT_GRPID_GroupID_bits 32 +#define GEN9_MEDIA_OBJECT_GRPID_GroupID_bits 32 +#define GEN8_MEDIA_OBJECT_GRPID_GroupID_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_GroupID_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_GRPID_GroupID_start 192 +#define GEN10_MEDIA_OBJECT_GRPID_GroupID_start 192 +#define GEN9_MEDIA_OBJECT_GRPID_GroupID_start 192 +#define GEN8_MEDIA_OBJECT_GRPID_GroupID_start 192 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_GroupID_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 192; + case 10: return 192; + case 9: return 192; + case 8: return 192; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_GRPID::Indirect Data Length */ + + +#define GEN11_MEDIA_OBJECT_GRPID_IndirectDataLength_bits 17 +#define GEN10_MEDIA_OBJECT_GRPID_IndirectDataLength_bits 17 +#define GEN9_MEDIA_OBJECT_GRPID_IndirectDataLength_bits 17 +#define GEN8_MEDIA_OBJECT_GRPID_IndirectDataLength_bits 17 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_IndirectDataLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 17; + case 10: return 17; + case 9: return 17; + case 8: return 17; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_GRPID_IndirectDataLength_start 64 +#define GEN10_MEDIA_OBJECT_GRPID_IndirectDataLength_start 64 +#define GEN9_MEDIA_OBJECT_GRPID_IndirectDataLength_start 64 +#define GEN8_MEDIA_OBJECT_GRPID_IndirectDataLength_start 64 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_IndirectDataLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_GRPID::Indirect Data Start Address */ + + +#define GEN11_MEDIA_OBJECT_GRPID_IndirectDataStartAddress_bits 32 +#define GEN10_MEDIA_OBJECT_GRPID_IndirectDataStartAddress_bits 32 +#define GEN9_MEDIA_OBJECT_GRPID_IndirectDataStartAddress_bits 32 +#define GEN8_MEDIA_OBJECT_GRPID_IndirectDataStartAddress_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_IndirectDataStartAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_GRPID_IndirectDataStartAddress_start 96 +#define GEN10_MEDIA_OBJECT_GRPID_IndirectDataStartAddress_start 96 +#define GEN9_MEDIA_OBJECT_GRPID_IndirectDataStartAddress_start 96 +#define GEN8_MEDIA_OBJECT_GRPID_IndirectDataStartAddress_start 96 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_IndirectDataStartAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 96; + case 10: return 96; + case 9: return 96; + case 8: return 96; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_GRPID::Inline Data */ + + +#define GEN11_MEDIA_OBJECT_GRPID_InlineData_bits 32 +#define GEN10_MEDIA_OBJECT_GRPID_InlineData_bits 32 +#define GEN9_MEDIA_OBJECT_GRPID_InlineData_bits 32 +#define GEN8_MEDIA_OBJECT_GRPID_InlineData_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_InlineData_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_GRPID_InlineData_start 0 +#define GEN10_MEDIA_OBJECT_GRPID_InlineData_start 0 +#define GEN9_MEDIA_OBJECT_GRPID_InlineData_start 0 +#define GEN8_MEDIA_OBJECT_GRPID_InlineData_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_InlineData_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_GRPID::Interface Descriptor Offset */ + + +#define GEN11_MEDIA_OBJECT_GRPID_InterfaceDescriptorOffset_bits 6 +#define GEN10_MEDIA_OBJECT_GRPID_InterfaceDescriptorOffset_bits 6 +#define GEN9_MEDIA_OBJECT_GRPID_InterfaceDescriptorOffset_bits 6 +#define GEN8_MEDIA_OBJECT_GRPID_InterfaceDescriptorOffset_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_InterfaceDescriptorOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_GRPID_InterfaceDescriptorOffset_start 32 +#define GEN10_MEDIA_OBJECT_GRPID_InterfaceDescriptorOffset_start 32 +#define GEN9_MEDIA_OBJECT_GRPID_InterfaceDescriptorOffset_start 32 +#define GEN8_MEDIA_OBJECT_GRPID_InterfaceDescriptorOffset_start 32 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_InterfaceDescriptorOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_GRPID::Media Command Opcode */ + + +#define GEN11_MEDIA_OBJECT_GRPID_MediaCommandOpcode_bits 3 +#define GEN10_MEDIA_OBJECT_GRPID_MediaCommandOpcode_bits 3 +#define GEN9_MEDIA_OBJECT_GRPID_MediaCommandOpcode_bits 3 +#define GEN8_MEDIA_OBJECT_GRPID_MediaCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_MediaCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_GRPID_MediaCommandOpcode_start 24 +#define GEN10_MEDIA_OBJECT_GRPID_MediaCommandOpcode_start 24 +#define GEN9_MEDIA_OBJECT_GRPID_MediaCommandOpcode_start 24 +#define GEN8_MEDIA_OBJECT_GRPID_MediaCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_MediaCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_GRPID::Media Command Pipeline */ + + +#define GEN11_MEDIA_OBJECT_GRPID_MediaCommandPipeline_bits 2 +#define GEN10_MEDIA_OBJECT_GRPID_MediaCommandPipeline_bits 2 +#define GEN9_MEDIA_OBJECT_GRPID_MediaCommandPipeline_bits 2 +#define GEN8_MEDIA_OBJECT_GRPID_MediaCommandPipeline_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_MediaCommandPipeline_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_GRPID_MediaCommandPipeline_start 27 +#define GEN10_MEDIA_OBJECT_GRPID_MediaCommandPipeline_start 27 +#define GEN9_MEDIA_OBJECT_GRPID_MediaCommandPipeline_start 27 +#define GEN8_MEDIA_OBJECT_GRPID_MediaCommandPipeline_start 27 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_MediaCommandPipeline_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_GRPID::Media Command Sub-Opcode */ + + +#define GEN11_MEDIA_OBJECT_GRPID_MediaCommandSubOpcode_bits 8 +#define GEN10_MEDIA_OBJECT_GRPID_MediaCommandSubOpcode_bits 8 +#define GEN9_MEDIA_OBJECT_GRPID_MediaCommandSubOpcode_bits 8 +#define GEN8_MEDIA_OBJECT_GRPID_MediaCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_MediaCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_GRPID_MediaCommandSubOpcode_start 16 +#define GEN10_MEDIA_OBJECT_GRPID_MediaCommandSubOpcode_start 16 +#define GEN9_MEDIA_OBJECT_GRPID_MediaCommandSubOpcode_start 16 +#define GEN8_MEDIA_OBJECT_GRPID_MediaCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_MediaCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_GRPID::Scoreboard Color */ + + +#define GEN10_MEDIA_OBJECT_GRPID_ScoreboardColor_bits 4 +#define GEN9_MEDIA_OBJECT_GRPID_ScoreboardColor_bits 4 +#define GEN8_MEDIA_OBJECT_GRPID_ScoreboardColor_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_ScoreboardColor_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MEDIA_OBJECT_GRPID_ScoreboardColor_start 176 +#define GEN9_MEDIA_OBJECT_GRPID_ScoreboardColor_start 176 +#define GEN8_MEDIA_OBJECT_GRPID_ScoreboardColor_start 176 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_ScoreboardColor_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 176; + case 9: return 176; + case 8: return 176; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_GRPID::Scoreboard Mask */ + + +#define GEN10_MEDIA_OBJECT_GRPID_ScoreboardMask_bits 8 +#define GEN9_MEDIA_OBJECT_GRPID_ScoreboardMask_bits 8 +#define GEN8_MEDIA_OBJECT_GRPID_ScoreboardMask_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_ScoreboardMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MEDIA_OBJECT_GRPID_ScoreboardMask_start 160 +#define GEN9_MEDIA_OBJECT_GRPID_ScoreboardMask_start 160 +#define GEN8_MEDIA_OBJECT_GRPID_ScoreboardMask_start 160 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_ScoreboardMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 160; + case 9: return 160; + case 8: return 160; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_GRPID::Scoreboard X */ + + +#define GEN10_MEDIA_OBJECT_GRPID_ScoreboardX_bits 9 +#define GEN9_MEDIA_OBJECT_GRPID_ScoreboardX_bits 9 +#define GEN8_MEDIA_OBJECT_GRPID_ScoreboardX_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_ScoreboardX_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 9; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MEDIA_OBJECT_GRPID_ScoreboardX_start 128 +#define GEN9_MEDIA_OBJECT_GRPID_ScoreboardX_start 128 +#define GEN8_MEDIA_OBJECT_GRPID_ScoreboardX_start 128 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_ScoreboardX_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 128; + case 9: return 128; + case 8: return 128; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_GRPID::Scoreboard Y */ + + +#define GEN10_MEDIA_OBJECT_GRPID_ScoreboardY_bits 9 +#define GEN9_MEDIA_OBJECT_GRPID_ScoreboardY_bits 9 +#define GEN8_MEDIA_OBJECT_GRPID_ScoreboardY_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_ScoreboardY_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 9; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MEDIA_OBJECT_GRPID_ScoreboardY_start 144 +#define GEN9_MEDIA_OBJECT_GRPID_ScoreboardY_start 144 +#define GEN8_MEDIA_OBJECT_GRPID_ScoreboardY_start 144 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_ScoreboardY_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 144; + case 9: return 144; + case 8: return 144; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_GRPID::Slice Destination Select */ + + +#define GEN9_MEDIA_OBJECT_GRPID_SliceDestinationSelect_bits 2 +#define GEN8_MEDIA_OBJECT_GRPID_SliceDestinationSelect_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_SliceDestinationSelect_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_MEDIA_OBJECT_GRPID_SliceDestinationSelect_start 83 +#define GEN8_MEDIA_OBJECT_GRPID_SliceDestinationSelect_start 83 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_SliceDestinationSelect_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 83; + case 8: return 83; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_GRPID::Slice Destination Select MSB */ + + +#define GEN9_MEDIA_OBJECT_GRPID_SliceDestinationSelectMSB_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_SliceDestinationSelectMSB_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_MEDIA_OBJECT_GRPID_SliceDestinationSelectMSB_start 88 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_SliceDestinationSelectMSB_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 88; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_GRPID::SubSlice Destination Select */ + + +#define GEN9_MEDIA_OBJECT_GRPID_SubSliceDestinationSelect_bits 2 +#define GEN8_MEDIA_OBJECT_GRPID_SubSliceDestinationSelect_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_SubSliceDestinationSelect_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_MEDIA_OBJECT_GRPID_SubSliceDestinationSelect_start 81 +#define GEN8_MEDIA_OBJECT_GRPID_SubSliceDestinationSelect_start 81 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_SubSliceDestinationSelect_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 81; + case 8: return 81; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_GRPID::Use Scoreboard */ + + +#define GEN10_MEDIA_OBJECT_GRPID_UseScoreboard_bits 1 +#define GEN9_MEDIA_OBJECT_GRPID_UseScoreboard_bits 1 +#define GEN8_MEDIA_OBJECT_GRPID_UseScoreboard_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_UseScoreboard_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MEDIA_OBJECT_GRPID_UseScoreboard_start 85 +#define GEN9_MEDIA_OBJECT_GRPID_UseScoreboard_start 85 +#define GEN8_MEDIA_OBJECT_GRPID_UseScoreboard_start 85 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_UseScoreboard_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 85; + case 9: return 85; + case 8: return 85; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_GRPID::X Position */ + + +#define GEN11_MEDIA_OBJECT_GRPID_XPosition_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_XPosition_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 9; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_GRPID_XPosition_start 128 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_XPosition_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 128; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_GRPID::Y Position */ + + +#define GEN11_MEDIA_OBJECT_GRPID_YPosition_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_YPosition_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 9; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_GRPID_YPosition_start 144 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_GRPID_YPosition_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 144; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_PRT */ + + +#define GEN11_MEDIA_OBJECT_PRT_length 16 +#define GEN10_MEDIA_OBJECT_PRT_length 16 +#define GEN9_MEDIA_OBJECT_PRT_length 16 +#define GEN8_MEDIA_OBJECT_PRT_length 16 +#define GEN75_MEDIA_OBJECT_PRT_length 16 +#define GEN7_MEDIA_OBJECT_PRT_length 16 +#define GEN6_MEDIA_OBJECT_PRT_length 16 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_PRT_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_PRT::Children Present */ + + +#define GEN11_MEDIA_OBJECT_PRT_ChildrenPresent_bits 1 +#define GEN10_MEDIA_OBJECT_PRT_ChildrenPresent_bits 1 +#define GEN9_MEDIA_OBJECT_PRT_ChildrenPresent_bits 1 +#define GEN8_MEDIA_OBJECT_PRT_ChildrenPresent_bits 1 +#define GEN75_MEDIA_OBJECT_PRT_ChildrenPresent_bits 1 +#define GEN7_MEDIA_OBJECT_PRT_ChildrenPresent_bits 1 +#define GEN6_MEDIA_OBJECT_PRT_ChildrenPresent_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_PRT_ChildrenPresent_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_PRT_ChildrenPresent_start 95 +#define GEN10_MEDIA_OBJECT_PRT_ChildrenPresent_start 95 +#define GEN9_MEDIA_OBJECT_PRT_ChildrenPresent_start 95 +#define GEN8_MEDIA_OBJECT_PRT_ChildrenPresent_start 95 +#define GEN75_MEDIA_OBJECT_PRT_ChildrenPresent_start 95 +#define GEN7_MEDIA_OBJECT_PRT_ChildrenPresent_start 95 +#define GEN6_MEDIA_OBJECT_PRT_ChildrenPresent_start 95 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_PRT_ChildrenPresent_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 95; + case 10: return 95; + case 9: return 95; + case 8: return 95; + case 7: + if (devinfo->is_haswell) { + return 95; + } else { + return 95; + } + case 6: return 95; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_PRT::Command Type */ + + +#define GEN11_MEDIA_OBJECT_PRT_CommandType_bits 3 +#define GEN10_MEDIA_OBJECT_PRT_CommandType_bits 3 +#define GEN9_MEDIA_OBJECT_PRT_CommandType_bits 3 +#define GEN8_MEDIA_OBJECT_PRT_CommandType_bits 3 +#define GEN75_MEDIA_OBJECT_PRT_CommandType_bits 3 +#define GEN7_MEDIA_OBJECT_PRT_CommandType_bits 3 +#define GEN6_MEDIA_OBJECT_PRT_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_PRT_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_PRT_CommandType_start 29 +#define GEN10_MEDIA_OBJECT_PRT_CommandType_start 29 +#define GEN9_MEDIA_OBJECT_PRT_CommandType_start 29 +#define GEN8_MEDIA_OBJECT_PRT_CommandType_start 29 +#define GEN75_MEDIA_OBJECT_PRT_CommandType_start 29 +#define GEN7_MEDIA_OBJECT_PRT_CommandType_start 29 +#define GEN6_MEDIA_OBJECT_PRT_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_PRT_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_PRT::DWord Length */ + + +#define GEN11_MEDIA_OBJECT_PRT_DWordLength_bits 15 +#define GEN10_MEDIA_OBJECT_PRT_DWordLength_bits 15 +#define GEN9_MEDIA_OBJECT_PRT_DWordLength_bits 16 +#define GEN8_MEDIA_OBJECT_PRT_DWordLength_bits 16 +#define GEN75_MEDIA_OBJECT_PRT_DWordLength_bits 16 +#define GEN7_MEDIA_OBJECT_PRT_DWordLength_bits 16 +#define GEN6_MEDIA_OBJECT_PRT_DWordLength_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_PRT_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 15; + case 10: return 15; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_PRT_DWordLength_start 0 +#define GEN10_MEDIA_OBJECT_PRT_DWordLength_start 0 +#define GEN9_MEDIA_OBJECT_PRT_DWordLength_start 0 +#define GEN8_MEDIA_OBJECT_PRT_DWordLength_start 0 +#define GEN75_MEDIA_OBJECT_PRT_DWordLength_start 0 +#define GEN7_MEDIA_OBJECT_PRT_DWordLength_start 0 +#define GEN6_MEDIA_OBJECT_PRT_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_PRT_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_PRT::Inline Data */ + + +#define GEN11_MEDIA_OBJECT_PRT_InlineData_bits 32 +#define GEN10_MEDIA_OBJECT_PRT_InlineData_bits 32 +#define GEN9_MEDIA_OBJECT_PRT_InlineData_bits 32 +#define GEN8_MEDIA_OBJECT_PRT_InlineData_bits 32 +#define GEN75_MEDIA_OBJECT_PRT_InlineData_bits 32 +#define GEN7_MEDIA_OBJECT_PRT_InlineData_bits 32 +#define GEN6_MEDIA_OBJECT_PRT_InlineData_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_PRT_InlineData_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_PRT_InlineData_start 0 +#define GEN10_MEDIA_OBJECT_PRT_InlineData_start 0 +#define GEN9_MEDIA_OBJECT_PRT_InlineData_start 0 +#define GEN8_MEDIA_OBJECT_PRT_InlineData_start 0 +#define GEN75_MEDIA_OBJECT_PRT_InlineData_start 0 +#define GEN7_MEDIA_OBJECT_PRT_InlineData_start 0 +#define GEN6_MEDIA_OBJECT_PRT_InlineData_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_PRT_InlineData_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_PRT::Interface Descriptor Offset */ + + +#define GEN11_MEDIA_OBJECT_PRT_InterfaceDescriptorOffset_bits 6 +#define GEN10_MEDIA_OBJECT_PRT_InterfaceDescriptorOffset_bits 6 +#define GEN9_MEDIA_OBJECT_PRT_InterfaceDescriptorOffset_bits 6 +#define GEN8_MEDIA_OBJECT_PRT_InterfaceDescriptorOffset_bits 6 +#define GEN75_MEDIA_OBJECT_PRT_InterfaceDescriptorOffset_bits 6 +#define GEN7_MEDIA_OBJECT_PRT_InterfaceDescriptorOffset_bits 5 +#define GEN6_MEDIA_OBJECT_PRT_InterfaceDescriptorOffset_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_PRT_InterfaceDescriptorOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 5; + } + case 6: return 5; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_PRT_InterfaceDescriptorOffset_start 32 +#define GEN10_MEDIA_OBJECT_PRT_InterfaceDescriptorOffset_start 32 +#define GEN9_MEDIA_OBJECT_PRT_InterfaceDescriptorOffset_start 32 +#define GEN8_MEDIA_OBJECT_PRT_InterfaceDescriptorOffset_start 32 +#define GEN75_MEDIA_OBJECT_PRT_InterfaceDescriptorOffset_start 32 +#define GEN7_MEDIA_OBJECT_PRT_InterfaceDescriptorOffset_start 32 +#define GEN6_MEDIA_OBJECT_PRT_InterfaceDescriptorOffset_start 32 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_PRT_InterfaceDescriptorOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_PRT::Media Command Opcode */ + + +#define GEN11_MEDIA_OBJECT_PRT_MediaCommandOpcode_bits 3 +#define GEN10_MEDIA_OBJECT_PRT_MediaCommandOpcode_bits 3 +#define GEN9_MEDIA_OBJECT_PRT_MediaCommandOpcode_bits 3 +#define GEN8_MEDIA_OBJECT_PRT_MediaCommandOpcode_bits 3 +#define GEN75_MEDIA_OBJECT_PRT_MediaCommandOpcode_bits 3 +#define GEN7_MEDIA_OBJECT_PRT_MediaCommandOpcode_bits 3 +#define GEN6_MEDIA_OBJECT_PRT_MediaCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_PRT_MediaCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_PRT_MediaCommandOpcode_start 24 +#define GEN10_MEDIA_OBJECT_PRT_MediaCommandOpcode_start 24 +#define GEN9_MEDIA_OBJECT_PRT_MediaCommandOpcode_start 24 +#define GEN8_MEDIA_OBJECT_PRT_MediaCommandOpcode_start 24 +#define GEN75_MEDIA_OBJECT_PRT_MediaCommandOpcode_start 24 +#define GEN7_MEDIA_OBJECT_PRT_MediaCommandOpcode_start 24 +#define GEN6_MEDIA_OBJECT_PRT_MediaCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_PRT_MediaCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_PRT::PRT_Fence Needed */ + + +#define GEN11_MEDIA_OBJECT_PRT_PRT_FenceNeeded_bits 1 +#define GEN10_MEDIA_OBJECT_PRT_PRT_FenceNeeded_bits 1 +#define GEN9_MEDIA_OBJECT_PRT_PRT_FenceNeeded_bits 1 +#define GEN8_MEDIA_OBJECT_PRT_PRT_FenceNeeded_bits 1 +#define GEN75_MEDIA_OBJECT_PRT_PRT_FenceNeeded_bits 1 +#define GEN7_MEDIA_OBJECT_PRT_PRT_FenceNeeded_bits 1 +#define GEN6_MEDIA_OBJECT_PRT_PRT_FenceNeeded_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_PRT_PRT_FenceNeeded_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_PRT_PRT_FenceNeeded_start 87 +#define GEN10_MEDIA_OBJECT_PRT_PRT_FenceNeeded_start 87 +#define GEN9_MEDIA_OBJECT_PRT_PRT_FenceNeeded_start 87 +#define GEN8_MEDIA_OBJECT_PRT_PRT_FenceNeeded_start 87 +#define GEN75_MEDIA_OBJECT_PRT_PRT_FenceNeeded_start 87 +#define GEN7_MEDIA_OBJECT_PRT_PRT_FenceNeeded_start 87 +#define GEN6_MEDIA_OBJECT_PRT_PRT_FenceNeeded_start 87 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_PRT_PRT_FenceNeeded_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 87; + case 10: return 87; + case 9: return 87; + case 8: return 87; + case 7: + if (devinfo->is_haswell) { + return 87; + } else { + return 87; + } + case 6: return 87; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_PRT::PRT_FenceType */ + + +#define GEN11_MEDIA_OBJECT_PRT_PRT_FenceType_bits 1 +#define GEN10_MEDIA_OBJECT_PRT_PRT_FenceType_bits 1 +#define GEN9_MEDIA_OBJECT_PRT_PRT_FenceType_bits 1 +#define GEN8_MEDIA_OBJECT_PRT_PRT_FenceType_bits 1 +#define GEN75_MEDIA_OBJECT_PRT_PRT_FenceType_bits 1 +#define GEN7_MEDIA_OBJECT_PRT_PRT_FenceType_bits 1 +#define GEN6_MEDIA_OBJECT_PRT_PRT_FenceType_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_PRT_PRT_FenceType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_PRT_PRT_FenceType_start 86 +#define GEN10_MEDIA_OBJECT_PRT_PRT_FenceType_start 86 +#define GEN9_MEDIA_OBJECT_PRT_PRT_FenceType_start 86 +#define GEN8_MEDIA_OBJECT_PRT_PRT_FenceType_start 86 +#define GEN75_MEDIA_OBJECT_PRT_PRT_FenceType_start 86 +#define GEN7_MEDIA_OBJECT_PRT_PRT_FenceType_start 86 +#define GEN6_MEDIA_OBJECT_PRT_PRT_FenceType_start 86 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_PRT_PRT_FenceType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 86; + case 10: return 86; + case 9: return 86; + case 8: return 86; + case 7: + if (devinfo->is_haswell) { + return 86; + } else { + return 86; + } + case 6: return 86; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_PRT::Pipeline */ + + +#define GEN11_MEDIA_OBJECT_PRT_Pipeline_bits 2 +#define GEN10_MEDIA_OBJECT_PRT_Pipeline_bits 2 +#define GEN9_MEDIA_OBJECT_PRT_Pipeline_bits 2 +#define GEN8_MEDIA_OBJECT_PRT_Pipeline_bits 2 +#define GEN75_MEDIA_OBJECT_PRT_Pipeline_bits 2 +#define GEN7_MEDIA_OBJECT_PRT_Pipeline_bits 2 +#define GEN6_MEDIA_OBJECT_PRT_Pipeline_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_PRT_Pipeline_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_PRT_Pipeline_start 27 +#define GEN10_MEDIA_OBJECT_PRT_Pipeline_start 27 +#define GEN9_MEDIA_OBJECT_PRT_Pipeline_start 27 +#define GEN8_MEDIA_OBJECT_PRT_Pipeline_start 27 +#define GEN75_MEDIA_OBJECT_PRT_Pipeline_start 27 +#define GEN7_MEDIA_OBJECT_PRT_Pipeline_start 27 +#define GEN6_MEDIA_OBJECT_PRT_Pipeline_start 27 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_PRT_Pipeline_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_PRT::SubOpcode */ + + +#define GEN11_MEDIA_OBJECT_PRT_SubOpcode_bits 8 +#define GEN10_MEDIA_OBJECT_PRT_SubOpcode_bits 8 +#define GEN9_MEDIA_OBJECT_PRT_SubOpcode_bits 8 +#define GEN8_MEDIA_OBJECT_PRT_SubOpcode_bits 8 +#define GEN75_MEDIA_OBJECT_PRT_SubOpcode_bits 8 +#define GEN7_MEDIA_OBJECT_PRT_SubOpcode_bits 8 +#define GEN6_MEDIA_OBJECT_PRT_SubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_PRT_SubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_PRT_SubOpcode_start 16 +#define GEN10_MEDIA_OBJECT_PRT_SubOpcode_start 16 +#define GEN9_MEDIA_OBJECT_PRT_SubOpcode_start 16 +#define GEN8_MEDIA_OBJECT_PRT_SubOpcode_start 16 +#define GEN75_MEDIA_OBJECT_PRT_SubOpcode_start 16 +#define GEN7_MEDIA_OBJECT_PRT_SubOpcode_start 16 +#define GEN6_MEDIA_OBJECT_PRT_SubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_PRT_SubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER */ + + + + + +/* MEDIA_OBJECT_WALKER::Block Resolution X */ + + +#define GEN11_MEDIA_OBJECT_WALKER_BlockResolutionX_bits 11 +#define GEN10_MEDIA_OBJECT_WALKER_BlockResolutionX_bits 11 +#define GEN9_MEDIA_OBJECT_WALKER_BlockResolutionX_bits 11 +#define GEN8_MEDIA_OBJECT_WALKER_BlockResolutionX_bits 9 +#define GEN75_MEDIA_OBJECT_WALKER_BlockResolutionX_bits 9 +#define GEN7_MEDIA_OBJECT_WALKER_BlockResolutionX_bits 9 +#define GEN6_MEDIA_OBJECT_WALKER_BlockResolutionX_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_BlockResolutionX_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 9; + } + case 6: return 9; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_WALKER_BlockResolutionX_start 256 +#define GEN10_MEDIA_OBJECT_WALKER_BlockResolutionX_start 256 +#define GEN9_MEDIA_OBJECT_WALKER_BlockResolutionX_start 256 +#define GEN8_MEDIA_OBJECT_WALKER_BlockResolutionX_start 256 +#define GEN75_MEDIA_OBJECT_WALKER_BlockResolutionX_start 256 +#define GEN7_MEDIA_OBJECT_WALKER_BlockResolutionX_start 256 +#define GEN6_MEDIA_OBJECT_WALKER_BlockResolutionX_start 256 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_BlockResolutionX_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 256; + case 10: return 256; + case 9: return 256; + case 8: return 256; + case 7: + if (devinfo->is_haswell) { + return 256; + } else { + return 256; + } + case 6: return 256; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Block Resolution Y */ + + +#define GEN11_MEDIA_OBJECT_WALKER_BlockResolutionY_bits 11 +#define GEN10_MEDIA_OBJECT_WALKER_BlockResolutionY_bits 11 +#define GEN9_MEDIA_OBJECT_WALKER_BlockResolutionY_bits 11 +#define GEN8_MEDIA_OBJECT_WALKER_BlockResolutionY_bits 9 +#define GEN75_MEDIA_OBJECT_WALKER_BlockResolutionY_bits 9 +#define GEN7_MEDIA_OBJECT_WALKER_BlockResolutionY_bits 9 +#define GEN6_MEDIA_OBJECT_WALKER_BlockResolutionY_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_BlockResolutionY_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 9; + } + case 6: return 9; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_WALKER_BlockResolutionY_start 272 +#define GEN10_MEDIA_OBJECT_WALKER_BlockResolutionY_start 272 +#define GEN9_MEDIA_OBJECT_WALKER_BlockResolutionY_start 272 +#define GEN8_MEDIA_OBJECT_WALKER_BlockResolutionY_start 272 +#define GEN75_MEDIA_OBJECT_WALKER_BlockResolutionY_start 272 +#define GEN7_MEDIA_OBJECT_WALKER_BlockResolutionY_start 272 +#define GEN6_MEDIA_OBJECT_WALKER_BlockResolutionY_start 272 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_BlockResolutionY_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 272; + case 10: return 272; + case 9: return 272; + case 8: return 272; + case 7: + if (devinfo->is_haswell) { + return 272; + } else { + return 272; + } + case 6: return 272; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Children Present */ + + +#define GEN8_MEDIA_OBJECT_WALKER_ChildrenPresent_bits 1 +#define GEN75_MEDIA_OBJECT_WALKER_ChildrenPresent_bits 1 +#define GEN7_MEDIA_OBJECT_WALKER_ChildrenPresent_bits 1 +#define GEN6_MEDIA_OBJECT_WALKER_ChildrenPresent_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_ChildrenPresent_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_MEDIA_OBJECT_WALKER_ChildrenPresent_start 95 +#define GEN75_MEDIA_OBJECT_WALKER_ChildrenPresent_start 95 +#define GEN7_MEDIA_OBJECT_WALKER_ChildrenPresent_start 95 +#define GEN6_MEDIA_OBJECT_WALKER_ChildrenPresent_start 95 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_ChildrenPresent_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 95; + case 7: + if (devinfo->is_haswell) { + return 95; + } else { + return 95; + } + case 6: return 95; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Color Count Minus One */ + + +#define GEN11_MEDIA_OBJECT_WALKER_ColorCountMinusOne_bits 8 +#define GEN10_MEDIA_OBJECT_WALKER_ColorCountMinusOne_bits 4 +#define GEN9_MEDIA_OBJECT_WALKER_ColorCountMinusOne_bits 4 +#define GEN8_MEDIA_OBJECT_WALKER_ColorCountMinusOne_bits 4 +#define GEN75_MEDIA_OBJECT_WALKER_ColorCountMinusOne_bits 4 +#define GEN7_MEDIA_OBJECT_WALKER_ColorCountMinusOne_bits 4 +#define GEN6_MEDIA_OBJECT_WALKER_ColorCountMinusOne_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_ColorCountMinusOne_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_WALKER_ColorCountMinusOne_start 216 +#define GEN10_MEDIA_OBJECT_WALKER_ColorCountMinusOne_start 216 +#define GEN9_MEDIA_OBJECT_WALKER_ColorCountMinusOne_start 216 +#define GEN8_MEDIA_OBJECT_WALKER_ColorCountMinusOne_start 216 +#define GEN75_MEDIA_OBJECT_WALKER_ColorCountMinusOne_start 216 +#define GEN7_MEDIA_OBJECT_WALKER_ColorCountMinusOne_start 216 +#define GEN6_MEDIA_OBJECT_WALKER_ColorCountMinusOne_start 216 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_ColorCountMinusOne_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 216; + case 10: return 216; + case 9: return 216; + case 8: return 216; + case 7: + if (devinfo->is_haswell) { + return 216; + } else { + return 216; + } + case 6: return 216; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Command Type */ + + +#define GEN11_MEDIA_OBJECT_WALKER_CommandType_bits 3 +#define GEN10_MEDIA_OBJECT_WALKER_CommandType_bits 3 +#define GEN9_MEDIA_OBJECT_WALKER_CommandType_bits 3 +#define GEN8_MEDIA_OBJECT_WALKER_CommandType_bits 3 +#define GEN75_MEDIA_OBJECT_WALKER_CommandType_bits 3 +#define GEN7_MEDIA_OBJECT_WALKER_CommandType_bits 3 +#define GEN6_MEDIA_OBJECT_WALKER_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_WALKER_CommandType_start 29 +#define GEN10_MEDIA_OBJECT_WALKER_CommandType_start 29 +#define GEN9_MEDIA_OBJECT_WALKER_CommandType_start 29 +#define GEN8_MEDIA_OBJECT_WALKER_CommandType_start 29 +#define GEN75_MEDIA_OBJECT_WALKER_CommandType_start 29 +#define GEN7_MEDIA_OBJECT_WALKER_CommandType_start 29 +#define GEN6_MEDIA_OBJECT_WALKER_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::DWord Length */ + + +#define GEN11_MEDIA_OBJECT_WALKER_DWordLength_bits 15 +#define GEN10_MEDIA_OBJECT_WALKER_DWordLength_bits 15 +#define GEN9_MEDIA_OBJECT_WALKER_DWordLength_bits 16 +#define GEN8_MEDIA_OBJECT_WALKER_DWordLength_bits 16 +#define GEN75_MEDIA_OBJECT_WALKER_DWordLength_bits 16 +#define GEN7_MEDIA_OBJECT_WALKER_DWordLength_bits 16 +#define GEN6_MEDIA_OBJECT_WALKER_DWordLength_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 15; + case 10: return 15; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_WALKER_DWordLength_start 0 +#define GEN10_MEDIA_OBJECT_WALKER_DWordLength_start 0 +#define GEN9_MEDIA_OBJECT_WALKER_DWordLength_start 0 +#define GEN8_MEDIA_OBJECT_WALKER_DWordLength_start 0 +#define GEN75_MEDIA_OBJECT_WALKER_DWordLength_start 0 +#define GEN7_MEDIA_OBJECT_WALKER_DWordLength_start 0 +#define GEN6_MEDIA_OBJECT_WALKER_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Dual Mode */ + + +#define GEN75_MEDIA_OBJECT_WALKER_DualMode_bits 1 +#define GEN7_MEDIA_OBJECT_WALKER_DualMode_bits 1 +#define GEN6_MEDIA_OBJECT_WALKER_DualMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_DualMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_MEDIA_OBJECT_WALKER_DualMode_start 223 +#define GEN7_MEDIA_OBJECT_WALKER_DualMode_start 223 +#define GEN6_MEDIA_OBJECT_WALKER_DualMode_start 223 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_DualMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 223; + } else { + return 223; + } + case 6: return 223; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Global Inner Loop Unit X */ + + +#define GEN11_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitX_bits 12 +#define GEN10_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitX_bits 12 +#define GEN9_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitX_bits 12 +#define GEN8_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitX_bits 10 +#define GEN75_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitX_bits 10 +#define GEN7_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitX_bits 10 +#define GEN6_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitX_bits 10 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitX_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 12; + case 10: return 12; + case 9: return 12; + case 8: return 10; + case 7: + if (devinfo->is_haswell) { + return 10; + } else { + return 10; + } + case 6: return 10; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitX_start 512 +#define GEN10_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitX_start 512 +#define GEN9_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitX_start 512 +#define GEN8_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitX_start 512 +#define GEN75_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitX_start 512 +#define GEN7_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitX_start 512 +#define GEN6_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitX_start 512 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitX_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 512; + case 10: return 512; + case 9: return 512; + case 8: return 512; + case 7: + if (devinfo->is_haswell) { + return 512; + } else { + return 512; + } + case 6: return 512; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Global Inner Loop Unit Y */ + + +#define GEN11_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitY_bits 12 +#define GEN10_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitY_bits 12 +#define GEN9_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitY_bits 12 +#define GEN8_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitY_bits 10 +#define GEN75_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitY_bits 10 +#define GEN7_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitY_bits 10 +#define GEN6_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitY_bits 10 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitY_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 12; + case 10: return 12; + case 9: return 12; + case 8: return 10; + case 7: + if (devinfo->is_haswell) { + return 10; + } else { + return 10; + } + case 6: return 10; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitY_start 528 +#define GEN10_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitY_start 528 +#define GEN9_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitY_start 528 +#define GEN8_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitY_start 528 +#define GEN75_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitY_start 528 +#define GEN7_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitY_start 528 +#define GEN6_MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitY_start 528 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_GlobalInnerLoopUnitY_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 528; + case 10: return 528; + case 9: return 528; + case 8: return 528; + case 7: + if (devinfo->is_haswell) { + return 528; + } else { + return 528; + } + case 6: return 528; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Global Loop Exec Count */ + + +#define GEN11_MEDIA_OBJECT_WALKER_GlobalLoopExecCount_bits 12 +#define GEN10_MEDIA_OBJECT_WALKER_GlobalLoopExecCount_bits 12 +#define GEN9_MEDIA_OBJECT_WALKER_GlobalLoopExecCount_bits 12 +#define GEN8_MEDIA_OBJECT_WALKER_GlobalLoopExecCount_bits 10 +#define GEN75_MEDIA_OBJECT_WALKER_GlobalLoopExecCount_bits 10 +#define GEN7_MEDIA_OBJECT_WALKER_GlobalLoopExecCount_bits 10 +#define GEN6_MEDIA_OBJECT_WALKER_GlobalLoopExecCount_bits 10 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_GlobalLoopExecCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 12; + case 10: return 12; + case 9: return 12; + case 8: return 10; + case 7: + if (devinfo->is_haswell) { + return 10; + } else { + return 10; + } + case 6: return 10; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_WALKER_GlobalLoopExecCount_start 240 +#define GEN10_MEDIA_OBJECT_WALKER_GlobalLoopExecCount_start 240 +#define GEN9_MEDIA_OBJECT_WALKER_GlobalLoopExecCount_start 240 +#define GEN8_MEDIA_OBJECT_WALKER_GlobalLoopExecCount_start 240 +#define GEN75_MEDIA_OBJECT_WALKER_GlobalLoopExecCount_start 240 +#define GEN7_MEDIA_OBJECT_WALKER_GlobalLoopExecCount_start 240 +#define GEN6_MEDIA_OBJECT_WALKER_GlobalLoopExecCount_start 240 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_GlobalLoopExecCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 240; + case 10: return 240; + case 9: return 240; + case 8: return 240; + case 7: + if (devinfo->is_haswell) { + return 240; + } else { + return 240; + } + case 6: return 240; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Global Outer Loop Stride X */ + + +#define GEN11_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideX_bits 12 +#define GEN10_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideX_bits 12 +#define GEN9_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideX_bits 12 +#define GEN8_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideX_bits 10 +#define GEN75_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideX_bits 10 +#define GEN7_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideX_bits 10 +#define GEN6_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideX_bits 10 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideX_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 12; + case 10: return 12; + case 9: return 12; + case 8: return 10; + case 7: + if (devinfo->is_haswell) { + return 10; + } else { + return 10; + } + case 6: return 10; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideX_start 480 +#define GEN10_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideX_start 480 +#define GEN9_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideX_start 480 +#define GEN8_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideX_start 480 +#define GEN75_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideX_start 480 +#define GEN7_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideX_start 480 +#define GEN6_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideX_start 480 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideX_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 480; + case 10: return 480; + case 9: return 480; + case 8: return 480; + case 7: + if (devinfo->is_haswell) { + return 480; + } else { + return 480; + } + case 6: return 480; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Global Outer Loop Stride Y */ + + +#define GEN11_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideY_bits 12 +#define GEN10_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideY_bits 12 +#define GEN9_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideY_bits 12 +#define GEN8_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideY_bits 10 +#define GEN75_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideY_bits 10 +#define GEN7_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideY_bits 10 +#define GEN6_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideY_bits 10 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideY_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 12; + case 10: return 12; + case 9: return 12; + case 8: return 10; + case 7: + if (devinfo->is_haswell) { + return 10; + } else { + return 10; + } + case 6: return 10; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideY_start 496 +#define GEN10_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideY_start 496 +#define GEN9_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideY_start 496 +#define GEN8_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideY_start 496 +#define GEN75_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideY_start 496 +#define GEN7_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideY_start 496 +#define GEN6_MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideY_start 496 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_GlobalOuterLoopStrideY_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 496; + case 10: return 496; + case 9: return 496; + case 8: return 496; + case 7: + if (devinfo->is_haswell) { + return 496; + } else { + return 496; + } + case 6: return 496; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Global Resolution X */ + + +#define GEN11_MEDIA_OBJECT_WALKER_GlobalResolutionX_bits 11 +#define GEN10_MEDIA_OBJECT_WALKER_GlobalResolutionX_bits 11 +#define GEN9_MEDIA_OBJECT_WALKER_GlobalResolutionX_bits 11 +#define GEN8_MEDIA_OBJECT_WALKER_GlobalResolutionX_bits 9 +#define GEN75_MEDIA_OBJECT_WALKER_GlobalResolutionX_bits 9 +#define GEN7_MEDIA_OBJECT_WALKER_GlobalResolutionX_bits 9 +#define GEN6_MEDIA_OBJECT_WALKER_GlobalResolutionX_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_GlobalResolutionX_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 9; + } + case 6: return 9; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_WALKER_GlobalResolutionX_start 416 +#define GEN10_MEDIA_OBJECT_WALKER_GlobalResolutionX_start 416 +#define GEN9_MEDIA_OBJECT_WALKER_GlobalResolutionX_start 416 +#define GEN8_MEDIA_OBJECT_WALKER_GlobalResolutionX_start 416 +#define GEN75_MEDIA_OBJECT_WALKER_GlobalResolutionX_start 416 +#define GEN7_MEDIA_OBJECT_WALKER_GlobalResolutionX_start 416 +#define GEN6_MEDIA_OBJECT_WALKER_GlobalResolutionX_start 416 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_GlobalResolutionX_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 416; + case 10: return 416; + case 9: return 416; + case 8: return 416; + case 7: + if (devinfo->is_haswell) { + return 416; + } else { + return 416; + } + case 6: return 416; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Global Resolution Y */ + + +#define GEN11_MEDIA_OBJECT_WALKER_GlobalResolutionY_bits 11 +#define GEN10_MEDIA_OBJECT_WALKER_GlobalResolutionY_bits 11 +#define GEN9_MEDIA_OBJECT_WALKER_GlobalResolutionY_bits 11 +#define GEN8_MEDIA_OBJECT_WALKER_GlobalResolutionY_bits 9 +#define GEN75_MEDIA_OBJECT_WALKER_GlobalResolutionY_bits 9 +#define GEN7_MEDIA_OBJECT_WALKER_GlobalResolutionY_bits 9 +#define GEN6_MEDIA_OBJECT_WALKER_GlobalResolutionY_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_GlobalResolutionY_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 9; + } + case 6: return 9; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_WALKER_GlobalResolutionY_start 432 +#define GEN10_MEDIA_OBJECT_WALKER_GlobalResolutionY_start 432 +#define GEN9_MEDIA_OBJECT_WALKER_GlobalResolutionY_start 432 +#define GEN8_MEDIA_OBJECT_WALKER_GlobalResolutionY_start 432 +#define GEN75_MEDIA_OBJECT_WALKER_GlobalResolutionY_start 432 +#define GEN7_MEDIA_OBJECT_WALKER_GlobalResolutionY_start 432 +#define GEN6_MEDIA_OBJECT_WALKER_GlobalResolutionY_start 432 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_GlobalResolutionY_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 432; + case 10: return 432; + case 9: return 432; + case 8: return 432; + case 7: + if (devinfo->is_haswell) { + return 432; + } else { + return 432; + } + case 6: return 432; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Global Start X */ + + +#define GEN11_MEDIA_OBJECT_WALKER_GlobalStartX_bits 12 +#define GEN10_MEDIA_OBJECT_WALKER_GlobalStartX_bits 12 +#define GEN9_MEDIA_OBJECT_WALKER_GlobalStartX_bits 12 +#define GEN8_MEDIA_OBJECT_WALKER_GlobalStartX_bits 10 +#define GEN75_MEDIA_OBJECT_WALKER_GlobalStartX_bits 10 +#define GEN7_MEDIA_OBJECT_WALKER_GlobalStartX_bits 10 +#define GEN6_MEDIA_OBJECT_WALKER_GlobalStartX_bits 10 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_GlobalStartX_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 12; + case 10: return 12; + case 9: return 12; + case 8: return 10; + case 7: + if (devinfo->is_haswell) { + return 10; + } else { + return 10; + } + case 6: return 10; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_WALKER_GlobalStartX_start 448 +#define GEN10_MEDIA_OBJECT_WALKER_GlobalStartX_start 448 +#define GEN9_MEDIA_OBJECT_WALKER_GlobalStartX_start 448 +#define GEN8_MEDIA_OBJECT_WALKER_GlobalStartX_start 448 +#define GEN75_MEDIA_OBJECT_WALKER_GlobalStartX_start 448 +#define GEN7_MEDIA_OBJECT_WALKER_GlobalStartX_start 448 +#define GEN6_MEDIA_OBJECT_WALKER_GlobalStartX_start 448 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_GlobalStartX_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 448; + case 10: return 448; + case 9: return 448; + case 8: return 448; + case 7: + if (devinfo->is_haswell) { + return 448; + } else { + return 448; + } + case 6: return 448; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Global Start Y */ + + +#define GEN11_MEDIA_OBJECT_WALKER_GlobalStartY_bits 12 +#define GEN10_MEDIA_OBJECT_WALKER_GlobalStartY_bits 12 +#define GEN9_MEDIA_OBJECT_WALKER_GlobalStartY_bits 12 +#define GEN8_MEDIA_OBJECT_WALKER_GlobalStartY_bits 10 +#define GEN75_MEDIA_OBJECT_WALKER_GlobalStartY_bits 10 +#define GEN7_MEDIA_OBJECT_WALKER_GlobalStartY_bits 10 +#define GEN6_MEDIA_OBJECT_WALKER_GlobalStartY_bits 10 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_GlobalStartY_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 12; + case 10: return 12; + case 9: return 12; + case 8: return 10; + case 7: + if (devinfo->is_haswell) { + return 10; + } else { + return 10; + } + case 6: return 10; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_WALKER_GlobalStartY_start 464 +#define GEN10_MEDIA_OBJECT_WALKER_GlobalStartY_start 464 +#define GEN9_MEDIA_OBJECT_WALKER_GlobalStartY_start 464 +#define GEN8_MEDIA_OBJECT_WALKER_GlobalStartY_start 464 +#define GEN75_MEDIA_OBJECT_WALKER_GlobalStartY_start 464 +#define GEN7_MEDIA_OBJECT_WALKER_GlobalStartY_start 464 +#define GEN6_MEDIA_OBJECT_WALKER_GlobalStartY_start 464 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_GlobalStartY_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 464; + case 10: return 464; + case 9: return 464; + case 8: return 464; + case 7: + if (devinfo->is_haswell) { + return 464; + } else { + return 464; + } + case 6: return 464; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Group ID Loop Select */ + + +#define GEN11_MEDIA_OBJECT_WALKER_GroupIDLoopSelect_bits 24 +#define GEN10_MEDIA_OBJECT_WALKER_GroupIDLoopSelect_bits 24 +#define GEN9_MEDIA_OBJECT_WALKER_GroupIDLoopSelect_bits 24 +#define GEN8_MEDIA_OBJECT_WALKER_GroupIDLoopSelect_bits 24 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_GroupIDLoopSelect_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_WALKER_GroupIDLoopSelect_start 168 +#define GEN10_MEDIA_OBJECT_WALKER_GroupIDLoopSelect_start 168 +#define GEN9_MEDIA_OBJECT_WALKER_GroupIDLoopSelect_start 168 +#define GEN8_MEDIA_OBJECT_WALKER_GroupIDLoopSelect_start 168 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_GroupIDLoopSelect_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 168; + case 10: return 168; + case 9: return 168; + case 8: return 168; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Indirect Data Length */ + + +#define GEN11_MEDIA_OBJECT_WALKER_IndirectDataLength_bits 17 +#define GEN10_MEDIA_OBJECT_WALKER_IndirectDataLength_bits 17 +#define GEN9_MEDIA_OBJECT_WALKER_IndirectDataLength_bits 17 +#define GEN8_MEDIA_OBJECT_WALKER_IndirectDataLength_bits 17 +#define GEN75_MEDIA_OBJECT_WALKER_IndirectDataLength_bits 17 +#define GEN7_MEDIA_OBJECT_WALKER_IndirectDataLength_bits 17 +#define GEN6_MEDIA_OBJECT_WALKER_IndirectDataLength_bits 17 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_IndirectDataLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 17; + case 10: return 17; + case 9: return 17; + case 8: return 17; + case 7: + if (devinfo->is_haswell) { + return 17; + } else { + return 17; + } + case 6: return 17; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_WALKER_IndirectDataLength_start 64 +#define GEN10_MEDIA_OBJECT_WALKER_IndirectDataLength_start 64 +#define GEN9_MEDIA_OBJECT_WALKER_IndirectDataLength_start 64 +#define GEN8_MEDIA_OBJECT_WALKER_IndirectDataLength_start 64 +#define GEN75_MEDIA_OBJECT_WALKER_IndirectDataLength_start 64 +#define GEN7_MEDIA_OBJECT_WALKER_IndirectDataLength_start 64 +#define GEN6_MEDIA_OBJECT_WALKER_IndirectDataLength_start 64 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_IndirectDataLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 64; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Indirect Data Start Address */ + + +#define GEN11_MEDIA_OBJECT_WALKER_IndirectDataStartAddress_bits 32 +#define GEN10_MEDIA_OBJECT_WALKER_IndirectDataStartAddress_bits 32 +#define GEN9_MEDIA_OBJECT_WALKER_IndirectDataStartAddress_bits 32 +#define GEN8_MEDIA_OBJECT_WALKER_IndirectDataStartAddress_bits 32 +#define GEN75_MEDIA_OBJECT_WALKER_IndirectDataStartAddress_bits 32 +#define GEN7_MEDIA_OBJECT_WALKER_IndirectDataStartAddress_bits 32 +#define GEN6_MEDIA_OBJECT_WALKER_IndirectDataStartAddress_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_IndirectDataStartAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_WALKER_IndirectDataStartAddress_start 96 +#define GEN10_MEDIA_OBJECT_WALKER_IndirectDataStartAddress_start 96 +#define GEN9_MEDIA_OBJECT_WALKER_IndirectDataStartAddress_start 96 +#define GEN8_MEDIA_OBJECT_WALKER_IndirectDataStartAddress_start 96 +#define GEN75_MEDIA_OBJECT_WALKER_IndirectDataStartAddress_start 96 +#define GEN7_MEDIA_OBJECT_WALKER_IndirectDataStartAddress_start 96 +#define GEN6_MEDIA_OBJECT_WALKER_IndirectDataStartAddress_start 96 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_IndirectDataStartAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 96; + case 10: return 96; + case 9: return 96; + case 8: return 96; + case 7: + if (devinfo->is_haswell) { + return 96; + } else { + return 96; + } + case 6: return 96; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Inline Data */ + + +#define GEN11_MEDIA_OBJECT_WALKER_InlineData_bits 32 +#define GEN10_MEDIA_OBJECT_WALKER_InlineData_bits 32 +#define GEN9_MEDIA_OBJECT_WALKER_InlineData_bits 32 +#define GEN8_MEDIA_OBJECT_WALKER_InlineData_bits 32 +#define GEN75_MEDIA_OBJECT_WALKER_InlineData_bits 32 +#define GEN7_MEDIA_OBJECT_WALKER_InlineData_bits 32 +#define GEN6_MEDIA_OBJECT_WALKER_InlineData_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_InlineData_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_WALKER_InlineData_start 0 +#define GEN10_MEDIA_OBJECT_WALKER_InlineData_start 0 +#define GEN9_MEDIA_OBJECT_WALKER_InlineData_start 0 +#define GEN8_MEDIA_OBJECT_WALKER_InlineData_start 0 +#define GEN75_MEDIA_OBJECT_WALKER_InlineData_start 0 +#define GEN7_MEDIA_OBJECT_WALKER_InlineData_start 0 +#define GEN6_MEDIA_OBJECT_WALKER_InlineData_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_InlineData_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Interface Descriptor Offset */ + + +#define GEN11_MEDIA_OBJECT_WALKER_InterfaceDescriptorOffset_bits 6 +#define GEN10_MEDIA_OBJECT_WALKER_InterfaceDescriptorOffset_bits 6 +#define GEN9_MEDIA_OBJECT_WALKER_InterfaceDescriptorOffset_bits 6 +#define GEN8_MEDIA_OBJECT_WALKER_InterfaceDescriptorOffset_bits 6 +#define GEN75_MEDIA_OBJECT_WALKER_InterfaceDescriptorOffset_bits 6 +#define GEN7_MEDIA_OBJECT_WALKER_InterfaceDescriptorOffset_bits 5 +#define GEN6_MEDIA_OBJECT_WALKER_InterfaceDescriptorOffset_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_InterfaceDescriptorOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 5; + } + case 6: return 5; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_WALKER_InterfaceDescriptorOffset_start 32 +#define GEN10_MEDIA_OBJECT_WALKER_InterfaceDescriptorOffset_start 32 +#define GEN9_MEDIA_OBJECT_WALKER_InterfaceDescriptorOffset_start 32 +#define GEN8_MEDIA_OBJECT_WALKER_InterfaceDescriptorOffset_start 32 +#define GEN75_MEDIA_OBJECT_WALKER_InterfaceDescriptorOffset_start 32 +#define GEN7_MEDIA_OBJECT_WALKER_InterfaceDescriptorOffset_start 32 +#define GEN6_MEDIA_OBJECT_WALKER_InterfaceDescriptorOffset_start 32 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_InterfaceDescriptorOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Local End X */ + + +#define GEN7_MEDIA_OBJECT_WALKER_LocalEndX_bits 9 +#define GEN6_MEDIA_OBJECT_WALKER_LocalEndX_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_LocalEndX_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 9; + } + case 6: return 9; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN7_MEDIA_OBJECT_WALKER_LocalEndX_start 320 +#define GEN6_MEDIA_OBJECT_WALKER_LocalEndX_start 320 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_LocalEndX_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 320; + } + case 6: return 320; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Local End Y */ + + +#define GEN7_MEDIA_OBJECT_WALKER_LocalEndY_bits 9 +#define GEN6_MEDIA_OBJECT_WALKER_LocalEndY_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_LocalEndY_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 9; + } + case 6: return 9; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN7_MEDIA_OBJECT_WALKER_LocalEndY_start 336 +#define GEN6_MEDIA_OBJECT_WALKER_LocalEndY_start 336 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_LocalEndY_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 336; + } + case 6: return 336; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Local Inner Loop Unit X */ + + +#define GEN11_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitX_bits 12 +#define GEN10_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitX_bits 12 +#define GEN9_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitX_bits 12 +#define GEN8_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitX_bits 10 +#define GEN75_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitX_bits 10 +#define GEN7_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitX_bits 10 +#define GEN6_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitX_bits 10 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_LocalInnerLoopUnitX_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 12; + case 10: return 12; + case 9: return 12; + case 8: return 10; + case 7: + if (devinfo->is_haswell) { + return 10; + } else { + return 10; + } + case 6: return 10; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitX_start 384 +#define GEN10_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitX_start 384 +#define GEN9_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitX_start 384 +#define GEN8_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitX_start 384 +#define GEN75_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitX_start 384 +#define GEN7_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitX_start 384 +#define GEN6_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitX_start 384 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_LocalInnerLoopUnitX_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 384; + case 10: return 384; + case 9: return 384; + case 8: return 384; + case 7: + if (devinfo->is_haswell) { + return 384; + } else { + return 384; + } + case 6: return 384; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Local Inner Loop Unit Y */ + + +#define GEN11_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitY_bits 12 +#define GEN10_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitY_bits 12 +#define GEN9_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitY_bits 12 +#define GEN8_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitY_bits 10 +#define GEN75_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitY_bits 10 +#define GEN7_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitY_bits 10 +#define GEN6_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitY_bits 10 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_LocalInnerLoopUnitY_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 12; + case 10: return 12; + case 9: return 12; + case 8: return 10; + case 7: + if (devinfo->is_haswell) { + return 10; + } else { + return 10; + } + case 6: return 10; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitY_start 400 +#define GEN10_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitY_start 400 +#define GEN9_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitY_start 400 +#define GEN8_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitY_start 400 +#define GEN75_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitY_start 400 +#define GEN7_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitY_start 400 +#define GEN6_MEDIA_OBJECT_WALKER_LocalInnerLoopUnitY_start 400 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_LocalInnerLoopUnitY_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 400; + case 10: return 400; + case 9: return 400; + case 8: return 400; + case 7: + if (devinfo->is_haswell) { + return 400; + } else { + return 400; + } + case 6: return 400; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Local Loop Exec Count */ + + +#define GEN11_MEDIA_OBJECT_WALKER_LocalLoopExecCount_bits 12 +#define GEN10_MEDIA_OBJECT_WALKER_LocalLoopExecCount_bits 12 +#define GEN9_MEDIA_OBJECT_WALKER_LocalLoopExecCount_bits 12 +#define GEN8_MEDIA_OBJECT_WALKER_LocalLoopExecCount_bits 10 +#define GEN75_MEDIA_OBJECT_WALKER_LocalLoopExecCount_bits 10 +#define GEN7_MEDIA_OBJECT_WALKER_LocalLoopExecCount_bits 10 +#define GEN6_MEDIA_OBJECT_WALKER_LocalLoopExecCount_bits 10 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_LocalLoopExecCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 12; + case 10: return 12; + case 9: return 12; + case 8: return 10; + case 7: + if (devinfo->is_haswell) { + return 10; + } else { + return 10; + } + case 6: return 10; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_WALKER_LocalLoopExecCount_start 224 +#define GEN10_MEDIA_OBJECT_WALKER_LocalLoopExecCount_start 224 +#define GEN9_MEDIA_OBJECT_WALKER_LocalLoopExecCount_start 224 +#define GEN8_MEDIA_OBJECT_WALKER_LocalLoopExecCount_start 224 +#define GEN75_MEDIA_OBJECT_WALKER_LocalLoopExecCount_start 224 +#define GEN7_MEDIA_OBJECT_WALKER_LocalLoopExecCount_start 224 +#define GEN6_MEDIA_OBJECT_WALKER_LocalLoopExecCount_start 224 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_LocalLoopExecCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 224; + case 10: return 224; + case 9: return 224; + case 8: return 224; + case 7: + if (devinfo->is_haswell) { + return 224; + } else { + return 224; + } + case 6: return 224; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Local Mid-Loop Unit Y */ + + +#define GEN11_MEDIA_OBJECT_WALKER_LocalMidLoopUnitY_bits 2 +#define GEN10_MEDIA_OBJECT_WALKER_LocalMidLoopUnitY_bits 2 +#define GEN9_MEDIA_OBJECT_WALKER_LocalMidLoopUnitY_bits 2 +#define GEN8_MEDIA_OBJECT_WALKER_LocalMidLoopUnitY_bits 2 +#define GEN75_MEDIA_OBJECT_WALKER_LocalMidLoopUnitY_bits 2 +#define GEN7_MEDIA_OBJECT_WALKER_LocalMidLoopUnitY_bits 2 +#define GEN6_MEDIA_OBJECT_WALKER_LocalMidLoopUnitY_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_LocalMidLoopUnitY_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_WALKER_LocalMidLoopUnitY_start 204 +#define GEN10_MEDIA_OBJECT_WALKER_LocalMidLoopUnitY_start 204 +#define GEN9_MEDIA_OBJECT_WALKER_LocalMidLoopUnitY_start 204 +#define GEN8_MEDIA_OBJECT_WALKER_LocalMidLoopUnitY_start 204 +#define GEN75_MEDIA_OBJECT_WALKER_LocalMidLoopUnitY_start 204 +#define GEN7_MEDIA_OBJECT_WALKER_LocalMidLoopUnitY_start 204 +#define GEN6_MEDIA_OBJECT_WALKER_LocalMidLoopUnitY_start 204 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_LocalMidLoopUnitY_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 204; + case 10: return 204; + case 9: return 204; + case 8: return 204; + case 7: + if (devinfo->is_haswell) { + return 204; + } else { + return 204; + } + case 6: return 204; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Local Outer Loop Stride X */ + + +#define GEN11_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideX_bits 12 +#define GEN10_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideX_bits 12 +#define GEN9_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideX_bits 12 +#define GEN8_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideX_bits 10 +#define GEN75_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideX_bits 10 +#define GEN7_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideX_bits 10 +#define GEN6_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideX_bits 10 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_LocalOuterLoopStrideX_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 12; + case 10: return 12; + case 9: return 12; + case 8: return 10; + case 7: + if (devinfo->is_haswell) { + return 10; + } else { + return 10; + } + case 6: return 10; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideX_start 352 +#define GEN10_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideX_start 352 +#define GEN9_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideX_start 352 +#define GEN8_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideX_start 352 +#define GEN75_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideX_start 352 +#define GEN7_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideX_start 352 +#define GEN6_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideX_start 352 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_LocalOuterLoopStrideX_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 352; + case 10: return 352; + case 9: return 352; + case 8: return 352; + case 7: + if (devinfo->is_haswell) { + return 352; + } else { + return 352; + } + case 6: return 352; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Local Outer Loop Stride Y */ + + +#define GEN11_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideY_bits 12 +#define GEN10_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideY_bits 12 +#define GEN9_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideY_bits 12 +#define GEN8_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideY_bits 10 +#define GEN75_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideY_bits 10 +#define GEN7_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideY_bits 10 +#define GEN6_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideY_bits 10 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_LocalOuterLoopStrideY_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 12; + case 10: return 12; + case 9: return 12; + case 8: return 10; + case 7: + if (devinfo->is_haswell) { + return 10; + } else { + return 10; + } + case 6: return 10; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideY_start 368 +#define GEN10_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideY_start 368 +#define GEN9_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideY_start 368 +#define GEN8_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideY_start 368 +#define GEN75_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideY_start 368 +#define GEN7_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideY_start 368 +#define GEN6_MEDIA_OBJECT_WALKER_LocalOuterLoopStrideY_start 368 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_LocalOuterLoopStrideY_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 368; + case 10: return 368; + case 9: return 368; + case 8: return 368; + case 7: + if (devinfo->is_haswell) { + return 368; + } else { + return 368; + } + case 6: return 368; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Local Start X */ + + +#define GEN11_MEDIA_OBJECT_WALKER_LocalStartX_bits 11 +#define GEN10_MEDIA_OBJECT_WALKER_LocalStartX_bits 11 +#define GEN9_MEDIA_OBJECT_WALKER_LocalStartX_bits 11 +#define GEN8_MEDIA_OBJECT_WALKER_LocalStartX_bits 9 +#define GEN75_MEDIA_OBJECT_WALKER_LocalStartX_bits 9 +#define GEN7_MEDIA_OBJECT_WALKER_LocalStartX_bits 9 +#define GEN6_MEDIA_OBJECT_WALKER_LocalStartX_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_LocalStartX_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 9; + } + case 6: return 9; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_WALKER_LocalStartX_start 288 +#define GEN10_MEDIA_OBJECT_WALKER_LocalStartX_start 288 +#define GEN9_MEDIA_OBJECT_WALKER_LocalStartX_start 288 +#define GEN8_MEDIA_OBJECT_WALKER_LocalStartX_start 288 +#define GEN75_MEDIA_OBJECT_WALKER_LocalStartX_start 288 +#define GEN7_MEDIA_OBJECT_WALKER_LocalStartX_start 288 +#define GEN6_MEDIA_OBJECT_WALKER_LocalStartX_start 288 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_LocalStartX_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 288; + case 10: return 288; + case 9: return 288; + case 8: return 288; + case 7: + if (devinfo->is_haswell) { + return 288; + } else { + return 288; + } + case 6: return 288; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Local Start Y */ + + +#define GEN11_MEDIA_OBJECT_WALKER_LocalStartY_bits 11 +#define GEN10_MEDIA_OBJECT_WALKER_LocalStartY_bits 11 +#define GEN9_MEDIA_OBJECT_WALKER_LocalStartY_bits 11 +#define GEN8_MEDIA_OBJECT_WALKER_LocalStartY_bits 9 +#define GEN75_MEDIA_OBJECT_WALKER_LocalStartY_bits 9 +#define GEN7_MEDIA_OBJECT_WALKER_LocalStartY_bits 9 +#define GEN6_MEDIA_OBJECT_WALKER_LocalStartY_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_LocalStartY_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 9; + } + case 6: return 9; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_WALKER_LocalStartY_start 304 +#define GEN10_MEDIA_OBJECT_WALKER_LocalStartY_start 304 +#define GEN9_MEDIA_OBJECT_WALKER_LocalStartY_start 304 +#define GEN8_MEDIA_OBJECT_WALKER_LocalStartY_start 304 +#define GEN75_MEDIA_OBJECT_WALKER_LocalStartY_start 304 +#define GEN7_MEDIA_OBJECT_WALKER_LocalStartY_start 304 +#define GEN6_MEDIA_OBJECT_WALKER_LocalStartY_start 304 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_LocalStartY_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 304; + case 10: return 304; + case 9: return 304; + case 8: return 304; + case 7: + if (devinfo->is_haswell) { + return 304; + } else { + return 304; + } + case 6: return 304; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Masked Dispatch */ + + +#define GEN11_MEDIA_OBJECT_WALKER_MaskedDispatch_bits 2 +#define GEN10_MEDIA_OBJECT_WALKER_MaskedDispatch_bits 2 +#define GEN9_MEDIA_OBJECT_WALKER_MaskedDispatch_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_MaskedDispatch_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_WALKER_MaskedDispatch_start 86 +#define GEN10_MEDIA_OBJECT_WALKER_MaskedDispatch_start 86 +#define GEN9_MEDIA_OBJECT_WALKER_MaskedDispatch_start 86 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_MaskedDispatch_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 86; + case 10: return 86; + case 9: return 86; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Media Command Opcode */ + + +#define GEN11_MEDIA_OBJECT_WALKER_MediaCommandOpcode_bits 3 +#define GEN10_MEDIA_OBJECT_WALKER_MediaCommandOpcode_bits 3 +#define GEN9_MEDIA_OBJECT_WALKER_MediaCommandOpcode_bits 3 +#define GEN8_MEDIA_OBJECT_WALKER_MediaCommandOpcode_bits 3 +#define GEN75_MEDIA_OBJECT_WALKER_MediaCommandOpcode_bits 3 +#define GEN7_MEDIA_OBJECT_WALKER_MediaCommandOpcode_bits 3 +#define GEN6_MEDIA_OBJECT_WALKER_MediaCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_MediaCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_WALKER_MediaCommandOpcode_start 24 +#define GEN10_MEDIA_OBJECT_WALKER_MediaCommandOpcode_start 24 +#define GEN9_MEDIA_OBJECT_WALKER_MediaCommandOpcode_start 24 +#define GEN8_MEDIA_OBJECT_WALKER_MediaCommandOpcode_start 24 +#define GEN75_MEDIA_OBJECT_WALKER_MediaCommandOpcode_start 24 +#define GEN7_MEDIA_OBJECT_WALKER_MediaCommandOpcode_start 24 +#define GEN6_MEDIA_OBJECT_WALKER_MediaCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_MediaCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Mid-Loop Unit X */ + + +#define GEN11_MEDIA_OBJECT_WALKER_MidLoopUnitX_bits 2 +#define GEN10_MEDIA_OBJECT_WALKER_MidLoopUnitX_bits 2 +#define GEN9_MEDIA_OBJECT_WALKER_MidLoopUnitX_bits 2 +#define GEN8_MEDIA_OBJECT_WALKER_MidLoopUnitX_bits 2 +#define GEN75_MEDIA_OBJECT_WALKER_MidLoopUnitX_bits 2 +#define GEN7_MEDIA_OBJECT_WALKER_MidLoopUnitX_bits 2 +#define GEN6_MEDIA_OBJECT_WALKER_MidLoopUnitX_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_MidLoopUnitX_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_WALKER_MidLoopUnitX_start 200 +#define GEN10_MEDIA_OBJECT_WALKER_MidLoopUnitX_start 200 +#define GEN9_MEDIA_OBJECT_WALKER_MidLoopUnitX_start 200 +#define GEN8_MEDIA_OBJECT_WALKER_MidLoopUnitX_start 200 +#define GEN75_MEDIA_OBJECT_WALKER_MidLoopUnitX_start 200 +#define GEN7_MEDIA_OBJECT_WALKER_MidLoopUnitX_start 200 +#define GEN6_MEDIA_OBJECT_WALKER_MidLoopUnitX_start 200 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_MidLoopUnitX_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 200; + case 10: return 200; + case 9: return 200; + case 8: return 200; + case 7: + if (devinfo->is_haswell) { + return 200; + } else { + return 200; + } + case 6: return 200; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Middle Loop Extra Steps */ + + +#define GEN11_MEDIA_OBJECT_WALKER_MiddleLoopExtraSteps_bits 5 +#define GEN10_MEDIA_OBJECT_WALKER_MiddleLoopExtraSteps_bits 5 +#define GEN9_MEDIA_OBJECT_WALKER_MiddleLoopExtraSteps_bits 5 +#define GEN8_MEDIA_OBJECT_WALKER_MiddleLoopExtraSteps_bits 5 +#define GEN75_MEDIA_OBJECT_WALKER_MiddleLoopExtraSteps_bits 5 +#define GEN7_MEDIA_OBJECT_WALKER_MiddleLoopExtraSteps_bits 5 +#define GEN6_MEDIA_OBJECT_WALKER_MiddleLoopExtraSteps_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_MiddleLoopExtraSteps_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 5; + } + case 6: return 5; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_WALKER_MiddleLoopExtraSteps_start 208 +#define GEN10_MEDIA_OBJECT_WALKER_MiddleLoopExtraSteps_start 208 +#define GEN9_MEDIA_OBJECT_WALKER_MiddleLoopExtraSteps_start 208 +#define GEN8_MEDIA_OBJECT_WALKER_MiddleLoopExtraSteps_start 208 +#define GEN75_MEDIA_OBJECT_WALKER_MiddleLoopExtraSteps_start 208 +#define GEN7_MEDIA_OBJECT_WALKER_MiddleLoopExtraSteps_start 208 +#define GEN6_MEDIA_OBJECT_WALKER_MiddleLoopExtraSteps_start 208 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_MiddleLoopExtraSteps_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 208; + case 10: return 208; + case 9: return 208; + case 8: return 208; + case 7: + if (devinfo->is_haswell) { + return 208; + } else { + return 208; + } + case 6: return 208; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Pipeline */ + + +#define GEN11_MEDIA_OBJECT_WALKER_Pipeline_bits 2 +#define GEN10_MEDIA_OBJECT_WALKER_Pipeline_bits 2 +#define GEN9_MEDIA_OBJECT_WALKER_Pipeline_bits 2 +#define GEN8_MEDIA_OBJECT_WALKER_Pipeline_bits 2 +#define GEN75_MEDIA_OBJECT_WALKER_Pipeline_bits 2 +#define GEN7_MEDIA_OBJECT_WALKER_Pipeline_bits 2 +#define GEN6_MEDIA_OBJECT_WALKER_Pipeline_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_Pipeline_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_WALKER_Pipeline_start 27 +#define GEN10_MEDIA_OBJECT_WALKER_Pipeline_start 27 +#define GEN9_MEDIA_OBJECT_WALKER_Pipeline_start 27 +#define GEN8_MEDIA_OBJECT_WALKER_Pipeline_start 27 +#define GEN75_MEDIA_OBJECT_WALKER_Pipeline_start 27 +#define GEN7_MEDIA_OBJECT_WALKER_Pipeline_start 27 +#define GEN6_MEDIA_OBJECT_WALKER_Pipeline_start 27 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_Pipeline_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Quad Mode */ + + +#define GEN75_MEDIA_OBJECT_WALKER_QuadMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_QuadMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_MEDIA_OBJECT_WALKER_QuadMode_start 221 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_QuadMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 221; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Repel */ + + +#define GEN75_MEDIA_OBJECT_WALKER_Repel_bits 1 +#define GEN7_MEDIA_OBJECT_WALKER_Repel_bits 1 +#define GEN6_MEDIA_OBJECT_WALKER_Repel_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_Repel_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_MEDIA_OBJECT_WALKER_Repel_start 222 +#define GEN7_MEDIA_OBJECT_WALKER_Repel_start 222 +#define GEN6_MEDIA_OBJECT_WALKER_Repel_start 222 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_Repel_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 222; + } else { + return 222; + } + case 6: return 222; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Scoreboard Mask */ + + +#define GEN10_MEDIA_OBJECT_WALKER_ScoreboardMask_bits 8 +#define GEN9_MEDIA_OBJECT_WALKER_ScoreboardMask_bits 8 +#define GEN8_MEDIA_OBJECT_WALKER_ScoreboardMask_bits 8 +#define GEN75_MEDIA_OBJECT_WALKER_ScoreboardMask_bits 8 +#define GEN7_MEDIA_OBJECT_WALKER_ScoreboardMask_bits 8 +#define GEN6_MEDIA_OBJECT_WALKER_ScoreboardMask_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_ScoreboardMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MEDIA_OBJECT_WALKER_ScoreboardMask_start 160 +#define GEN9_MEDIA_OBJECT_WALKER_ScoreboardMask_start 160 +#define GEN8_MEDIA_OBJECT_WALKER_ScoreboardMask_start 160 +#define GEN75_MEDIA_OBJECT_WALKER_ScoreboardMask_start 160 +#define GEN7_MEDIA_OBJECT_WALKER_ScoreboardMask_start 160 +#define GEN6_MEDIA_OBJECT_WALKER_ScoreboardMask_start 160 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_ScoreboardMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 160; + case 9: return 160; + case 8: return 160; + case 7: + if (devinfo->is_haswell) { + return 160; + } else { + return 160; + } + case 6: return 160; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::SubOpcode */ + + +#define GEN11_MEDIA_OBJECT_WALKER_SubOpcode_bits 8 +#define GEN10_MEDIA_OBJECT_WALKER_SubOpcode_bits 8 +#define GEN9_MEDIA_OBJECT_WALKER_SubOpcode_bits 8 +#define GEN8_MEDIA_OBJECT_WALKER_SubOpcode_bits 8 +#define GEN75_MEDIA_OBJECT_WALKER_SubOpcode_bits 8 +#define GEN7_MEDIA_OBJECT_WALKER_SubOpcode_bits 8 +#define GEN6_MEDIA_OBJECT_WALKER_SubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_SubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_WALKER_SubOpcode_start 16 +#define GEN10_MEDIA_OBJECT_WALKER_SubOpcode_start 16 +#define GEN9_MEDIA_OBJECT_WALKER_SubOpcode_start 16 +#define GEN8_MEDIA_OBJECT_WALKER_SubOpcode_start 16 +#define GEN75_MEDIA_OBJECT_WALKER_SubOpcode_start 16 +#define GEN7_MEDIA_OBJECT_WALKER_SubOpcode_start 16 +#define GEN6_MEDIA_OBJECT_WALKER_SubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_SubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Thread Synchronization */ + + +#define GEN11_MEDIA_OBJECT_WALKER_ThreadSynchronization_bits 1 +#define GEN10_MEDIA_OBJECT_WALKER_ThreadSynchronization_bits 1 +#define GEN9_MEDIA_OBJECT_WALKER_ThreadSynchronization_bits 1 +#define GEN8_MEDIA_OBJECT_WALKER_ThreadSynchronization_bits 1 +#define GEN75_MEDIA_OBJECT_WALKER_ThreadSynchronization_bits 1 +#define GEN7_MEDIA_OBJECT_WALKER_ThreadSynchronization_bits 1 +#define GEN6_MEDIA_OBJECT_WALKER_ThreadSynchronization_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_ThreadSynchronization_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_OBJECT_WALKER_ThreadSynchronization_start 88 +#define GEN10_MEDIA_OBJECT_WALKER_ThreadSynchronization_start 88 +#define GEN9_MEDIA_OBJECT_WALKER_ThreadSynchronization_start 88 +#define GEN8_MEDIA_OBJECT_WALKER_ThreadSynchronization_start 88 +#define GEN75_MEDIA_OBJECT_WALKER_ThreadSynchronization_start 88 +#define GEN7_MEDIA_OBJECT_WALKER_ThreadSynchronization_start 88 +#define GEN6_MEDIA_OBJECT_WALKER_ThreadSynchronization_start 88 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_ThreadSynchronization_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 88; + case 10: return 88; + case 9: return 88; + case 8: return 88; + case 7: + if (devinfo->is_haswell) { + return 88; + } else { + return 88; + } + case 6: return 88; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_OBJECT_WALKER::Use Scoreboard */ + + +#define GEN10_MEDIA_OBJECT_WALKER_UseScoreboard_bits 1 +#define GEN9_MEDIA_OBJECT_WALKER_UseScoreboard_bits 1 +#define GEN8_MEDIA_OBJECT_WALKER_UseScoreboard_bits 1 +#define GEN75_MEDIA_OBJECT_WALKER_UseScoreboard_bits 1 +#define GEN7_MEDIA_OBJECT_WALKER_UseScoreboard_bits 1 +#define GEN6_MEDIA_OBJECT_WALKER_UseScoreboard_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_UseScoreboard_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MEDIA_OBJECT_WALKER_UseScoreboard_start 85 +#define GEN9_MEDIA_OBJECT_WALKER_UseScoreboard_start 85 +#define GEN8_MEDIA_OBJECT_WALKER_UseScoreboard_start 85 +#define GEN75_MEDIA_OBJECT_WALKER_UseScoreboard_start 85 +#define GEN7_MEDIA_OBJECT_WALKER_UseScoreboard_start 85 +#define GEN6_MEDIA_OBJECT_WALKER_UseScoreboard_start 85 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_OBJECT_WALKER_UseScoreboard_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 85; + case 9: return 85; + case 8: return 85; + case 7: + if (devinfo->is_haswell) { + return 85; + } else { + return 85; + } + case 6: return 85; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_STATE_FLUSH */ + + +#define GEN11_MEDIA_STATE_FLUSH_length 2 +#define GEN10_MEDIA_STATE_FLUSH_length 2 +#define GEN9_MEDIA_STATE_FLUSH_length 2 +#define GEN8_MEDIA_STATE_FLUSH_length 2 +#define GEN75_MEDIA_STATE_FLUSH_length 2 +#define GEN7_MEDIA_STATE_FLUSH_length 2 +#define GEN6_MEDIA_STATE_FLUSH_length 2 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_STATE_FLUSH_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_STATE_FLUSH::Barrier Mask */ + + +#define GEN6_MEDIA_STATE_FLUSH_BarrierMask_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_STATE_FLUSH_BarrierMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_MEDIA_STATE_FLUSH_BarrierMask_start 32 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_STATE_FLUSH_BarrierMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_STATE_FLUSH::Command Type */ + + +#define GEN11_MEDIA_STATE_FLUSH_CommandType_bits 3 +#define GEN10_MEDIA_STATE_FLUSH_CommandType_bits 3 +#define GEN9_MEDIA_STATE_FLUSH_CommandType_bits 3 +#define GEN8_MEDIA_STATE_FLUSH_CommandType_bits 3 +#define GEN75_MEDIA_STATE_FLUSH_CommandType_bits 3 +#define GEN7_MEDIA_STATE_FLUSH_CommandType_bits 3 +#define GEN6_MEDIA_STATE_FLUSH_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_STATE_FLUSH_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_STATE_FLUSH_CommandType_start 29 +#define GEN10_MEDIA_STATE_FLUSH_CommandType_start 29 +#define GEN9_MEDIA_STATE_FLUSH_CommandType_start 29 +#define GEN8_MEDIA_STATE_FLUSH_CommandType_start 29 +#define GEN75_MEDIA_STATE_FLUSH_CommandType_start 29 +#define GEN7_MEDIA_STATE_FLUSH_CommandType_start 29 +#define GEN6_MEDIA_STATE_FLUSH_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_STATE_FLUSH_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_STATE_FLUSH::DWord Length */ + + +#define GEN11_MEDIA_STATE_FLUSH_DWordLength_bits 16 +#define GEN10_MEDIA_STATE_FLUSH_DWordLength_bits 16 +#define GEN9_MEDIA_STATE_FLUSH_DWordLength_bits 16 +#define GEN8_MEDIA_STATE_FLUSH_DWordLength_bits 16 +#define GEN75_MEDIA_STATE_FLUSH_DWordLength_bits 16 +#define GEN7_MEDIA_STATE_FLUSH_DWordLength_bits 16 +#define GEN6_MEDIA_STATE_FLUSH_DWordLength_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_STATE_FLUSH_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_STATE_FLUSH_DWordLength_start 0 +#define GEN10_MEDIA_STATE_FLUSH_DWordLength_start 0 +#define GEN9_MEDIA_STATE_FLUSH_DWordLength_start 0 +#define GEN8_MEDIA_STATE_FLUSH_DWordLength_start 0 +#define GEN75_MEDIA_STATE_FLUSH_DWordLength_start 0 +#define GEN7_MEDIA_STATE_FLUSH_DWordLength_start 0 +#define GEN6_MEDIA_STATE_FLUSH_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_STATE_FLUSH_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_STATE_FLUSH::Disable Preemption */ + + +#define GEN75_MEDIA_STATE_FLUSH_DisablePreemption_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_STATE_FLUSH_DisablePreemption_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_MEDIA_STATE_FLUSH_DisablePreemption_start 40 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_STATE_FLUSH_DisablePreemption_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 40; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_STATE_FLUSH::Flush to GO */ + + +#define GEN11_MEDIA_STATE_FLUSH_FlushtoGO_bits 1 +#define GEN10_MEDIA_STATE_FLUSH_FlushtoGO_bits 1 +#define GEN9_MEDIA_STATE_FLUSH_FlushtoGO_bits 1 +#define GEN8_MEDIA_STATE_FLUSH_FlushtoGO_bits 1 +#define GEN75_MEDIA_STATE_FLUSH_FlushtoGO_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_STATE_FLUSH_FlushtoGO_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_STATE_FLUSH_FlushtoGO_start 39 +#define GEN10_MEDIA_STATE_FLUSH_FlushtoGO_start 39 +#define GEN9_MEDIA_STATE_FLUSH_FlushtoGO_start 39 +#define GEN8_MEDIA_STATE_FLUSH_FlushtoGO_start 39 +#define GEN75_MEDIA_STATE_FLUSH_FlushtoGO_start 39 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_STATE_FLUSH_FlushtoGO_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 39; + case 10: return 39; + case 9: return 39; + case 8: return 39; + case 7: + if (devinfo->is_haswell) { + return 39; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_STATE_FLUSH::Interface Descriptor Offset */ + + +#define GEN11_MEDIA_STATE_FLUSH_InterfaceDescriptorOffset_bits 6 +#define GEN10_MEDIA_STATE_FLUSH_InterfaceDescriptorOffset_bits 6 +#define GEN9_MEDIA_STATE_FLUSH_InterfaceDescriptorOffset_bits 6 +#define GEN8_MEDIA_STATE_FLUSH_InterfaceDescriptorOffset_bits 6 +#define GEN75_MEDIA_STATE_FLUSH_InterfaceDescriptorOffset_bits 6 +#define GEN7_MEDIA_STATE_FLUSH_InterfaceDescriptorOffset_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_STATE_FLUSH_InterfaceDescriptorOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_STATE_FLUSH_InterfaceDescriptorOffset_start 32 +#define GEN10_MEDIA_STATE_FLUSH_InterfaceDescriptorOffset_start 32 +#define GEN9_MEDIA_STATE_FLUSH_InterfaceDescriptorOffset_start 32 +#define GEN8_MEDIA_STATE_FLUSH_InterfaceDescriptorOffset_start 32 +#define GEN75_MEDIA_STATE_FLUSH_InterfaceDescriptorOffset_start 32 +#define GEN7_MEDIA_STATE_FLUSH_InterfaceDescriptorOffset_start 32 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_STATE_FLUSH_InterfaceDescriptorOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_STATE_FLUSH::Media Command Opcode */ + + +#define GEN11_MEDIA_STATE_FLUSH_MediaCommandOpcode_bits 3 +#define GEN10_MEDIA_STATE_FLUSH_MediaCommandOpcode_bits 3 +#define GEN9_MEDIA_STATE_FLUSH_MediaCommandOpcode_bits 3 +#define GEN8_MEDIA_STATE_FLUSH_MediaCommandOpcode_bits 3 +#define GEN75_MEDIA_STATE_FLUSH_MediaCommandOpcode_bits 3 +#define GEN7_MEDIA_STATE_FLUSH_MediaCommandOpcode_bits 3 +#define GEN6_MEDIA_STATE_FLUSH_MediaCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_STATE_FLUSH_MediaCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_STATE_FLUSH_MediaCommandOpcode_start 24 +#define GEN10_MEDIA_STATE_FLUSH_MediaCommandOpcode_start 24 +#define GEN9_MEDIA_STATE_FLUSH_MediaCommandOpcode_start 24 +#define GEN8_MEDIA_STATE_FLUSH_MediaCommandOpcode_start 24 +#define GEN75_MEDIA_STATE_FLUSH_MediaCommandOpcode_start 24 +#define GEN7_MEDIA_STATE_FLUSH_MediaCommandOpcode_start 24 +#define GEN6_MEDIA_STATE_FLUSH_MediaCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_STATE_FLUSH_MediaCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_STATE_FLUSH::Pipeline */ + + +#define GEN11_MEDIA_STATE_FLUSH_Pipeline_bits 2 +#define GEN10_MEDIA_STATE_FLUSH_Pipeline_bits 2 +#define GEN9_MEDIA_STATE_FLUSH_Pipeline_bits 2 +#define GEN8_MEDIA_STATE_FLUSH_Pipeline_bits 2 +#define GEN75_MEDIA_STATE_FLUSH_Pipeline_bits 2 +#define GEN7_MEDIA_STATE_FLUSH_Pipeline_bits 2 +#define GEN6_MEDIA_STATE_FLUSH_Pipeline_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_STATE_FLUSH_Pipeline_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_STATE_FLUSH_Pipeline_start 27 +#define GEN10_MEDIA_STATE_FLUSH_Pipeline_start 27 +#define GEN9_MEDIA_STATE_FLUSH_Pipeline_start 27 +#define GEN8_MEDIA_STATE_FLUSH_Pipeline_start 27 +#define GEN75_MEDIA_STATE_FLUSH_Pipeline_start 27 +#define GEN7_MEDIA_STATE_FLUSH_Pipeline_start 27 +#define GEN6_MEDIA_STATE_FLUSH_Pipeline_start 27 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_STATE_FLUSH_Pipeline_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_STATE_FLUSH::SubOpcode */ + + +#define GEN11_MEDIA_STATE_FLUSH_SubOpcode_bits 8 +#define GEN10_MEDIA_STATE_FLUSH_SubOpcode_bits 8 +#define GEN9_MEDIA_STATE_FLUSH_SubOpcode_bits 8 +#define GEN8_MEDIA_STATE_FLUSH_SubOpcode_bits 8 +#define GEN75_MEDIA_STATE_FLUSH_SubOpcode_bits 8 +#define GEN7_MEDIA_STATE_FLUSH_SubOpcode_bits 8 +#define GEN6_MEDIA_STATE_FLUSH_SubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_STATE_FLUSH_SubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_STATE_FLUSH_SubOpcode_start 16 +#define GEN10_MEDIA_STATE_FLUSH_SubOpcode_start 16 +#define GEN9_MEDIA_STATE_FLUSH_SubOpcode_start 16 +#define GEN8_MEDIA_STATE_FLUSH_SubOpcode_start 16 +#define GEN75_MEDIA_STATE_FLUSH_SubOpcode_start 16 +#define GEN7_MEDIA_STATE_FLUSH_SubOpcode_start 16 +#define GEN6_MEDIA_STATE_FLUSH_SubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_STATE_FLUSH_SubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_STATE_FLUSH::Thread Count WaterMark */ + + +#define GEN6_MEDIA_STATE_FLUSH_ThreadCountWaterMark_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_STATE_FLUSH_ThreadCountWaterMark_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_MEDIA_STATE_FLUSH_ThreadCountWaterMark_start 48 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_STATE_FLUSH_ThreadCountWaterMark_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 48; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_STATE_FLUSH::Watermark Required */ + + +#define GEN10_MEDIA_STATE_FLUSH_WatermarkRequired_bits 1 +#define GEN9_MEDIA_STATE_FLUSH_WatermarkRequired_bits 1 +#define GEN8_MEDIA_STATE_FLUSH_WatermarkRequired_bits 1 +#define GEN75_MEDIA_STATE_FLUSH_WatermarkRequired_bits 1 +#define GEN7_MEDIA_STATE_FLUSH_WatermarkRequired_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_STATE_FLUSH_WatermarkRequired_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MEDIA_STATE_FLUSH_WatermarkRequired_start 38 +#define GEN9_MEDIA_STATE_FLUSH_WatermarkRequired_start 38 +#define GEN8_MEDIA_STATE_FLUSH_WatermarkRequired_start 38 +#define GEN75_MEDIA_STATE_FLUSH_WatermarkRequired_start 38 +#define GEN7_MEDIA_STATE_FLUSH_WatermarkRequired_start 38 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_STATE_FLUSH_WatermarkRequired_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 38; + case 9: return 38; + case 8: return 38; + case 7: + if (devinfo->is_haswell) { + return 38; + } else { + return 38; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE */ + + +#define GEN11_MEDIA_VFE_STATE_length 9 +#define GEN10_MEDIA_VFE_STATE_length 9 +#define GEN9_MEDIA_VFE_STATE_length 9 +#define GEN8_MEDIA_VFE_STATE_length 9 +#define GEN75_MEDIA_VFE_STATE_length 8 +#define GEN7_MEDIA_VFE_STATE_length 8 +#define GEN6_MEDIA_VFE_STATE_length 8 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 9; + case 10: return 9; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::Bypass Gateway Control */ + + +#define GEN8_MEDIA_VFE_STATE_BypassGatewayControl_bits 1 +#define GEN75_MEDIA_VFE_STATE_BypassGatewayControl_bits 1 +#define GEN7_MEDIA_VFE_STATE_BypassGatewayControl_bits 1 +#define GEN6_MEDIA_VFE_STATE_BypassGatewayControl_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_BypassGatewayControl_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_MEDIA_VFE_STATE_BypassGatewayControl_start 102 +#define GEN75_MEDIA_VFE_STATE_BypassGatewayControl_start 70 +#define GEN7_MEDIA_VFE_STATE_BypassGatewayControl_start 70 +#define GEN6_MEDIA_VFE_STATE_BypassGatewayControl_start 70 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_BypassGatewayControl_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 102; + case 7: + if (devinfo->is_haswell) { + return 70; + } else { + return 70; + } + case 6: return 70; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::CURBE Allocation Size */ + + +#define GEN11_MEDIA_VFE_STATE_CURBEAllocationSize_bits 16 +#define GEN10_MEDIA_VFE_STATE_CURBEAllocationSize_bits 16 +#define GEN9_MEDIA_VFE_STATE_CURBEAllocationSize_bits 16 +#define GEN8_MEDIA_VFE_STATE_CURBEAllocationSize_bits 16 +#define GEN75_MEDIA_VFE_STATE_CURBEAllocationSize_bits 16 +#define GEN7_MEDIA_VFE_STATE_CURBEAllocationSize_bits 16 +#define GEN6_MEDIA_VFE_STATE_CURBEAllocationSize_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_CURBEAllocationSize_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_VFE_STATE_CURBEAllocationSize_start 160 +#define GEN10_MEDIA_VFE_STATE_CURBEAllocationSize_start 160 +#define GEN9_MEDIA_VFE_STATE_CURBEAllocationSize_start 160 +#define GEN8_MEDIA_VFE_STATE_CURBEAllocationSize_start 160 +#define GEN75_MEDIA_VFE_STATE_CURBEAllocationSize_start 128 +#define GEN7_MEDIA_VFE_STATE_CURBEAllocationSize_start 128 +#define GEN6_MEDIA_VFE_STATE_CURBEAllocationSize_start 128 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_CURBEAllocationSize_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 160; + case 10: return 160; + case 9: return 160; + case 8: return 160; + case 7: + if (devinfo->is_haswell) { + return 128; + } else { + return 128; + } + case 6: return 128; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::Command Type */ + + +#define GEN11_MEDIA_VFE_STATE_CommandType_bits 3 +#define GEN10_MEDIA_VFE_STATE_CommandType_bits 3 +#define GEN9_MEDIA_VFE_STATE_CommandType_bits 3 +#define GEN8_MEDIA_VFE_STATE_CommandType_bits 3 +#define GEN75_MEDIA_VFE_STATE_CommandType_bits 3 +#define GEN7_MEDIA_VFE_STATE_CommandType_bits 3 +#define GEN6_MEDIA_VFE_STATE_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_VFE_STATE_CommandType_start 29 +#define GEN10_MEDIA_VFE_STATE_CommandType_start 29 +#define GEN9_MEDIA_VFE_STATE_CommandType_start 29 +#define GEN8_MEDIA_VFE_STATE_CommandType_start 29 +#define GEN75_MEDIA_VFE_STATE_CommandType_start 29 +#define GEN7_MEDIA_VFE_STATE_CommandType_start 29 +#define GEN6_MEDIA_VFE_STATE_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::DWord Length */ + + +#define GEN11_MEDIA_VFE_STATE_DWordLength_bits 16 +#define GEN10_MEDIA_VFE_STATE_DWordLength_bits 16 +#define GEN9_MEDIA_VFE_STATE_DWordLength_bits 16 +#define GEN8_MEDIA_VFE_STATE_DWordLength_bits 16 +#define GEN75_MEDIA_VFE_STATE_DWordLength_bits 16 +#define GEN7_MEDIA_VFE_STATE_DWordLength_bits 16 +#define GEN6_MEDIA_VFE_STATE_DWordLength_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_VFE_STATE_DWordLength_start 0 +#define GEN10_MEDIA_VFE_STATE_DWordLength_start 0 +#define GEN9_MEDIA_VFE_STATE_DWordLength_start 0 +#define GEN8_MEDIA_VFE_STATE_DWordLength_start 0 +#define GEN75_MEDIA_VFE_STATE_DWordLength_start 0 +#define GEN7_MEDIA_VFE_STATE_DWordLength_start 0 +#define GEN6_MEDIA_VFE_STATE_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::Dispatch Load Balance */ + + +#define GEN11_MEDIA_VFE_STATE_DispatchLoadBalance_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_DispatchLoadBalance_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_VFE_STATE_DispatchLoadBalance_start 98 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_DispatchLoadBalance_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 98; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::Fast Preempt */ + + +#define GEN6_MEDIA_VFE_STATE_FastPreempt_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_FastPreempt_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_MEDIA_VFE_STATE_FastPreempt_start 69 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_FastPreempt_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 69; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::GPGPU Mode */ + + +#define GEN75_MEDIA_VFE_STATE_GPGPUMode_bits 1 +#define GEN7_MEDIA_VFE_STATE_GPGPUMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_GPGPUMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_MEDIA_VFE_STATE_GPGPUMode_start 66 +#define GEN7_MEDIA_VFE_STATE_GPGPUMode_start 66 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_GPGPUMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 66; + } else { + return 66; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::Gateway MMIO Access Control */ + + +#define GEN7_MEDIA_VFE_STATE_GatewayMMIOAccessControl_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_GatewayMMIOAccessControl_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN7_MEDIA_VFE_STATE_GatewayMMIOAccessControl_start 67 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_GatewayMMIOAccessControl_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 67; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::Half-Slice Disable */ + + +#define GEN75_MEDIA_VFE_STATE_HalfSliceDisable_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_HalfSliceDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_MEDIA_VFE_STATE_HalfSliceDisable_start 96 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_HalfSliceDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 96; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::Maximum Number of Dual-Subslices */ + + +#define GEN11_MEDIA_VFE_STATE_MaximumNumberofDualSubslices_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_MaximumNumberofDualSubslices_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_VFE_STATE_MaximumNumberofDualSubslices_start 128 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_MaximumNumberofDualSubslices_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 128; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::Maximum Number of Threads */ + + +#define GEN11_MEDIA_VFE_STATE_MaximumNumberofThreads_bits 16 +#define GEN10_MEDIA_VFE_STATE_MaximumNumberofThreads_bits 16 +#define GEN9_MEDIA_VFE_STATE_MaximumNumberofThreads_bits 16 +#define GEN8_MEDIA_VFE_STATE_MaximumNumberofThreads_bits 16 +#define GEN75_MEDIA_VFE_STATE_MaximumNumberofThreads_bits 16 +#define GEN7_MEDIA_VFE_STATE_MaximumNumberofThreads_bits 16 +#define GEN6_MEDIA_VFE_STATE_MaximumNumberofThreads_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_MaximumNumberofThreads_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_VFE_STATE_MaximumNumberofThreads_start 112 +#define GEN10_MEDIA_VFE_STATE_MaximumNumberofThreads_start 112 +#define GEN9_MEDIA_VFE_STATE_MaximumNumberofThreads_start 112 +#define GEN8_MEDIA_VFE_STATE_MaximumNumberofThreads_start 112 +#define GEN75_MEDIA_VFE_STATE_MaximumNumberofThreads_start 80 +#define GEN7_MEDIA_VFE_STATE_MaximumNumberofThreads_start 80 +#define GEN6_MEDIA_VFE_STATE_MaximumNumberofThreads_start 80 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_MaximumNumberofThreads_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 112; + case 10: return 112; + case 9: return 112; + case 8: return 112; + case 7: + if (devinfo->is_haswell) { + return 80; + } else { + return 80; + } + case 6: return 80; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::Media Command Opcode */ + + +#define GEN11_MEDIA_VFE_STATE_MediaCommandOpcode_bits 3 +#define GEN10_MEDIA_VFE_STATE_MediaCommandOpcode_bits 3 +#define GEN9_MEDIA_VFE_STATE_MediaCommandOpcode_bits 3 +#define GEN8_MEDIA_VFE_STATE_MediaCommandOpcode_bits 3 +#define GEN75_MEDIA_VFE_STATE_MediaCommandOpcode_bits 3 +#define GEN7_MEDIA_VFE_STATE_MediaCommandOpcode_bits 3 +#define GEN6_MEDIA_VFE_STATE_MediaCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_MediaCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_VFE_STATE_MediaCommandOpcode_start 24 +#define GEN10_MEDIA_VFE_STATE_MediaCommandOpcode_start 24 +#define GEN9_MEDIA_VFE_STATE_MediaCommandOpcode_start 24 +#define GEN8_MEDIA_VFE_STATE_MediaCommandOpcode_start 24 +#define GEN75_MEDIA_VFE_STATE_MediaCommandOpcode_start 24 +#define GEN7_MEDIA_VFE_STATE_MediaCommandOpcode_start 24 +#define GEN6_MEDIA_VFE_STATE_MediaCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_MediaCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::Number of Media Objects per Pre-Emption Checkpoint */ + + +#define GEN10_MEDIA_VFE_STATE_NumberofMediaObjectsperPreEmptionCheckpoint_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_NumberofMediaObjectsperPreEmptionCheckpoint_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 8; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MEDIA_VFE_STATE_NumberofMediaObjectsperPreEmptionCheckpoint_start 200 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_NumberofMediaObjectsperPreEmptionCheckpoint_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 200; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::Number of URB Entries */ + + +#define GEN11_MEDIA_VFE_STATE_NumberofURBEntries_bits 8 +#define GEN10_MEDIA_VFE_STATE_NumberofURBEntries_bits 8 +#define GEN9_MEDIA_VFE_STATE_NumberofURBEntries_bits 8 +#define GEN8_MEDIA_VFE_STATE_NumberofURBEntries_bits 8 +#define GEN75_MEDIA_VFE_STATE_NumberofURBEntries_bits 8 +#define GEN7_MEDIA_VFE_STATE_NumberofURBEntries_bits 8 +#define GEN6_MEDIA_VFE_STATE_NumberofURBEntries_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_NumberofURBEntries_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_VFE_STATE_NumberofURBEntries_start 104 +#define GEN10_MEDIA_VFE_STATE_NumberofURBEntries_start 104 +#define GEN9_MEDIA_VFE_STATE_NumberofURBEntries_start 104 +#define GEN8_MEDIA_VFE_STATE_NumberofURBEntries_start 104 +#define GEN75_MEDIA_VFE_STATE_NumberofURBEntries_start 72 +#define GEN7_MEDIA_VFE_STATE_NumberofURBEntries_start 72 +#define GEN6_MEDIA_VFE_STATE_NumberofURBEntries_start 72 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_NumberofURBEntries_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 104; + case 10: return 104; + case 9: return 104; + case 8: return 104; + case 7: + if (devinfo->is_haswell) { + return 72; + } else { + return 72; + } + case 6: return 72; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::Per Thread Scratch Space */ + + +#define GEN11_MEDIA_VFE_STATE_PerThreadScratchSpace_bits 4 +#define GEN10_MEDIA_VFE_STATE_PerThreadScratchSpace_bits 4 +#define GEN9_MEDIA_VFE_STATE_PerThreadScratchSpace_bits 4 +#define GEN8_MEDIA_VFE_STATE_PerThreadScratchSpace_bits 4 +#define GEN75_MEDIA_VFE_STATE_PerThreadScratchSpace_bits 4 +#define GEN7_MEDIA_VFE_STATE_PerThreadScratchSpace_bits 4 +#define GEN6_MEDIA_VFE_STATE_PerThreadScratchSpace_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_PerThreadScratchSpace_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_VFE_STATE_PerThreadScratchSpace_start 32 +#define GEN10_MEDIA_VFE_STATE_PerThreadScratchSpace_start 32 +#define GEN9_MEDIA_VFE_STATE_PerThreadScratchSpace_start 32 +#define GEN8_MEDIA_VFE_STATE_PerThreadScratchSpace_start 32 +#define GEN75_MEDIA_VFE_STATE_PerThreadScratchSpace_start 32 +#define GEN7_MEDIA_VFE_STATE_PerThreadScratchSpace_start 32 +#define GEN6_MEDIA_VFE_STATE_PerThreadScratchSpace_start 32 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_PerThreadScratchSpace_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::Pipeline */ + + +#define GEN11_MEDIA_VFE_STATE_Pipeline_bits 2 +#define GEN10_MEDIA_VFE_STATE_Pipeline_bits 2 +#define GEN9_MEDIA_VFE_STATE_Pipeline_bits 2 +#define GEN8_MEDIA_VFE_STATE_Pipeline_bits 2 +#define GEN75_MEDIA_VFE_STATE_Pipeline_bits 2 +#define GEN7_MEDIA_VFE_STATE_Pipeline_bits 2 +#define GEN6_MEDIA_VFE_STATE_Pipeline_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_Pipeline_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_VFE_STATE_Pipeline_start 27 +#define GEN10_MEDIA_VFE_STATE_Pipeline_start 27 +#define GEN9_MEDIA_VFE_STATE_Pipeline_start 27 +#define GEN8_MEDIA_VFE_STATE_Pipeline_start 27 +#define GEN75_MEDIA_VFE_STATE_Pipeline_start 27 +#define GEN7_MEDIA_VFE_STATE_Pipeline_start 27 +#define GEN6_MEDIA_VFE_STATE_Pipeline_start 27 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_Pipeline_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::Reset Gateway Timer */ + + +#define GEN10_MEDIA_VFE_STATE_ResetGatewayTimer_bits 1 +#define GEN9_MEDIA_VFE_STATE_ResetGatewayTimer_bits 1 +#define GEN8_MEDIA_VFE_STATE_ResetGatewayTimer_bits 1 +#define GEN75_MEDIA_VFE_STATE_ResetGatewayTimer_bits 1 +#define GEN7_MEDIA_VFE_STATE_ResetGatewayTimer_bits 1 +#define GEN6_MEDIA_VFE_STATE_ResetGatewayTimer_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_ResetGatewayTimer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MEDIA_VFE_STATE_ResetGatewayTimer_start 103 +#define GEN9_MEDIA_VFE_STATE_ResetGatewayTimer_start 103 +#define GEN8_MEDIA_VFE_STATE_ResetGatewayTimer_start 103 +#define GEN75_MEDIA_VFE_STATE_ResetGatewayTimer_start 71 +#define GEN7_MEDIA_VFE_STATE_ResetGatewayTimer_start 71 +#define GEN6_MEDIA_VFE_STATE_ResetGatewayTimer_start 71 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_ResetGatewayTimer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 103; + case 9: return 103; + case 8: return 103; + case 7: + if (devinfo->is_haswell) { + return 71; + } else { + return 71; + } + case 6: return 71; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::SLM Bank Selection Policy */ + + +#define GEN10_MEDIA_VFE_STATE_SLMBankSelectionPolicy_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_SLMBankSelectionPolicy_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MEDIA_VFE_STATE_SLMBankSelectionPolicy_start 99 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_SLMBankSelectionPolicy_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 99; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::Scoreboard 0 Delta X */ + + +#define GEN10_MEDIA_VFE_STATE_Scoreboard0DeltaX_bits 4 +#define GEN9_MEDIA_VFE_STATE_Scoreboard0DeltaX_bits 4 +#define GEN8_MEDIA_VFE_STATE_Scoreboard0DeltaX_bits 4 +#define GEN75_MEDIA_VFE_STATE_Scoreboard0DeltaX_bits 4 +#define GEN7_MEDIA_VFE_STATE_Scoreboard0DeltaX_bits 4 +#define GEN6_MEDIA_VFE_STATE_Scoreboard0DeltaX_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_Scoreboard0DeltaX_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MEDIA_VFE_STATE_Scoreboard0DeltaX_start 224 +#define GEN9_MEDIA_VFE_STATE_Scoreboard0DeltaX_start 224 +#define GEN8_MEDIA_VFE_STATE_Scoreboard0DeltaX_start 224 +#define GEN75_MEDIA_VFE_STATE_Scoreboard0DeltaX_start 192 +#define GEN7_MEDIA_VFE_STATE_Scoreboard0DeltaX_start 192 +#define GEN6_MEDIA_VFE_STATE_Scoreboard0DeltaX_start 192 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_Scoreboard0DeltaX_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 224; + case 9: return 224; + case 8: return 224; + case 7: + if (devinfo->is_haswell) { + return 192; + } else { + return 192; + } + case 6: return 192; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::Scoreboard 0 Delta Y */ + + +#define GEN10_MEDIA_VFE_STATE_Scoreboard0DeltaY_bits 4 +#define GEN9_MEDIA_VFE_STATE_Scoreboard0DeltaY_bits 4 +#define GEN8_MEDIA_VFE_STATE_Scoreboard0DeltaY_bits 4 +#define GEN75_MEDIA_VFE_STATE_Scoreboard0DeltaY_bits 4 +#define GEN7_MEDIA_VFE_STATE_Scoreboard0DeltaY_bits 4 +#define GEN6_MEDIA_VFE_STATE_Scoreboard0DeltaY_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_Scoreboard0DeltaY_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MEDIA_VFE_STATE_Scoreboard0DeltaY_start 228 +#define GEN9_MEDIA_VFE_STATE_Scoreboard0DeltaY_start 228 +#define GEN8_MEDIA_VFE_STATE_Scoreboard0DeltaY_start 228 +#define GEN75_MEDIA_VFE_STATE_Scoreboard0DeltaY_start 196 +#define GEN7_MEDIA_VFE_STATE_Scoreboard0DeltaY_start 196 +#define GEN6_MEDIA_VFE_STATE_Scoreboard0DeltaY_start 196 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_Scoreboard0DeltaY_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 228; + case 9: return 228; + case 8: return 228; + case 7: + if (devinfo->is_haswell) { + return 196; + } else { + return 196; + } + case 6: return 196; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::Scoreboard 1 Delta X */ + + +#define GEN10_MEDIA_VFE_STATE_Scoreboard1DeltaX_bits 4 +#define GEN9_MEDIA_VFE_STATE_Scoreboard1DeltaX_bits 4 +#define GEN8_MEDIA_VFE_STATE_Scoreboard1DeltaX_bits 4 +#define GEN75_MEDIA_VFE_STATE_Scoreboard1DeltaX_bits 4 +#define GEN7_MEDIA_VFE_STATE_Scoreboard1DeltaX_bits 4 +#define GEN6_MEDIA_VFE_STATE_Scoreboard1DeltaX_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_Scoreboard1DeltaX_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MEDIA_VFE_STATE_Scoreboard1DeltaX_start 232 +#define GEN9_MEDIA_VFE_STATE_Scoreboard1DeltaX_start 232 +#define GEN8_MEDIA_VFE_STATE_Scoreboard1DeltaX_start 232 +#define GEN75_MEDIA_VFE_STATE_Scoreboard1DeltaX_start 200 +#define GEN7_MEDIA_VFE_STATE_Scoreboard1DeltaX_start 200 +#define GEN6_MEDIA_VFE_STATE_Scoreboard1DeltaX_start 200 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_Scoreboard1DeltaX_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 232; + case 9: return 232; + case 8: return 232; + case 7: + if (devinfo->is_haswell) { + return 200; + } else { + return 200; + } + case 6: return 200; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::Scoreboard 1 Delta Y */ + + +#define GEN10_MEDIA_VFE_STATE_Scoreboard1DeltaY_bits 4 +#define GEN9_MEDIA_VFE_STATE_Scoreboard1DeltaY_bits 4 +#define GEN8_MEDIA_VFE_STATE_Scoreboard1DeltaY_bits 4 +#define GEN75_MEDIA_VFE_STATE_Scoreboard1DeltaY_bits 4 +#define GEN7_MEDIA_VFE_STATE_Scoreboard1DeltaY_bits 4 +#define GEN6_MEDIA_VFE_STATE_Scoreboard1DeltaY_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_Scoreboard1DeltaY_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MEDIA_VFE_STATE_Scoreboard1DeltaY_start 236 +#define GEN9_MEDIA_VFE_STATE_Scoreboard1DeltaY_start 236 +#define GEN8_MEDIA_VFE_STATE_Scoreboard1DeltaY_start 236 +#define GEN75_MEDIA_VFE_STATE_Scoreboard1DeltaY_start 204 +#define GEN7_MEDIA_VFE_STATE_Scoreboard1DeltaY_start 204 +#define GEN6_MEDIA_VFE_STATE_Scoreboard1DeltaY_start 204 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_Scoreboard1DeltaY_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 236; + case 9: return 236; + case 8: return 236; + case 7: + if (devinfo->is_haswell) { + return 204; + } else { + return 204; + } + case 6: return 204; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::Scoreboard 2 Delta X */ + + +#define GEN10_MEDIA_VFE_STATE_Scoreboard2DeltaX_bits 4 +#define GEN9_MEDIA_VFE_STATE_Scoreboard2DeltaX_bits 4 +#define GEN8_MEDIA_VFE_STATE_Scoreboard2DeltaX_bits 4 +#define GEN75_MEDIA_VFE_STATE_Scoreboard2DeltaX_bits 4 +#define GEN7_MEDIA_VFE_STATE_Scoreboard2DeltaX_bits 4 +#define GEN6_MEDIA_VFE_STATE_Scoreboard2DeltaX_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_Scoreboard2DeltaX_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MEDIA_VFE_STATE_Scoreboard2DeltaX_start 240 +#define GEN9_MEDIA_VFE_STATE_Scoreboard2DeltaX_start 240 +#define GEN8_MEDIA_VFE_STATE_Scoreboard2DeltaX_start 240 +#define GEN75_MEDIA_VFE_STATE_Scoreboard2DeltaX_start 208 +#define GEN7_MEDIA_VFE_STATE_Scoreboard2DeltaX_start 208 +#define GEN6_MEDIA_VFE_STATE_Scoreboard2DeltaX_start 208 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_Scoreboard2DeltaX_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 240; + case 9: return 240; + case 8: return 240; + case 7: + if (devinfo->is_haswell) { + return 208; + } else { + return 208; + } + case 6: return 208; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::Scoreboard 2 Delta Y */ + + +#define GEN10_MEDIA_VFE_STATE_Scoreboard2DeltaY_bits 4 +#define GEN9_MEDIA_VFE_STATE_Scoreboard2DeltaY_bits 4 +#define GEN8_MEDIA_VFE_STATE_Scoreboard2DeltaY_bits 4 +#define GEN75_MEDIA_VFE_STATE_Scoreboard2DeltaY_bits 4 +#define GEN7_MEDIA_VFE_STATE_Scoreboard2DeltaY_bits 4 +#define GEN6_MEDIA_VFE_STATE_Scoreboard2DeltaY_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_Scoreboard2DeltaY_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MEDIA_VFE_STATE_Scoreboard2DeltaY_start 244 +#define GEN9_MEDIA_VFE_STATE_Scoreboard2DeltaY_start 244 +#define GEN8_MEDIA_VFE_STATE_Scoreboard2DeltaY_start 244 +#define GEN75_MEDIA_VFE_STATE_Scoreboard2DeltaY_start 212 +#define GEN7_MEDIA_VFE_STATE_Scoreboard2DeltaY_start 212 +#define GEN6_MEDIA_VFE_STATE_Scoreboard2DeltaY_start 212 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_Scoreboard2DeltaY_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 244; + case 9: return 244; + case 8: return 244; + case 7: + if (devinfo->is_haswell) { + return 212; + } else { + return 212; + } + case 6: return 212; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::Scoreboard 3 Delta X */ + + +#define GEN10_MEDIA_VFE_STATE_Scoreboard3DeltaX_bits 4 +#define GEN9_MEDIA_VFE_STATE_Scoreboard3DeltaX_bits 4 +#define GEN8_MEDIA_VFE_STATE_Scoreboard3DeltaX_bits 4 +#define GEN75_MEDIA_VFE_STATE_Scoreboard3DeltaX_bits 4 +#define GEN7_MEDIA_VFE_STATE_Scoreboard3DeltaX_bits 4 +#define GEN6_MEDIA_VFE_STATE_Scoreboard3DeltaX_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_Scoreboard3DeltaX_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MEDIA_VFE_STATE_Scoreboard3DeltaX_start 248 +#define GEN9_MEDIA_VFE_STATE_Scoreboard3DeltaX_start 248 +#define GEN8_MEDIA_VFE_STATE_Scoreboard3DeltaX_start 248 +#define GEN75_MEDIA_VFE_STATE_Scoreboard3DeltaX_start 216 +#define GEN7_MEDIA_VFE_STATE_Scoreboard3DeltaX_start 216 +#define GEN6_MEDIA_VFE_STATE_Scoreboard3DeltaX_start 216 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_Scoreboard3DeltaX_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 248; + case 9: return 248; + case 8: return 248; + case 7: + if (devinfo->is_haswell) { + return 216; + } else { + return 216; + } + case 6: return 216; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::Scoreboard 3 Delta Y */ + + +#define GEN10_MEDIA_VFE_STATE_Scoreboard3DeltaY_bits 4 +#define GEN9_MEDIA_VFE_STATE_Scoreboard3DeltaY_bits 4 +#define GEN8_MEDIA_VFE_STATE_Scoreboard3DeltaY_bits 4 +#define GEN75_MEDIA_VFE_STATE_Scoreboard3DeltaY_bits 4 +#define GEN7_MEDIA_VFE_STATE_Scoreboard3DeltaY_bits 4 +#define GEN6_MEDIA_VFE_STATE_Scoreboard3DeltaY_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_Scoreboard3DeltaY_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MEDIA_VFE_STATE_Scoreboard3DeltaY_start 252 +#define GEN9_MEDIA_VFE_STATE_Scoreboard3DeltaY_start 252 +#define GEN8_MEDIA_VFE_STATE_Scoreboard3DeltaY_start 252 +#define GEN75_MEDIA_VFE_STATE_Scoreboard3DeltaY_start 220 +#define GEN7_MEDIA_VFE_STATE_Scoreboard3DeltaY_start 220 +#define GEN6_MEDIA_VFE_STATE_Scoreboard3DeltaY_start 220 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_Scoreboard3DeltaY_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 252; + case 9: return 252; + case 8: return 252; + case 7: + if (devinfo->is_haswell) { + return 220; + } else { + return 220; + } + case 6: return 220; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::Scoreboard 4 Delta X */ + + +#define GEN10_MEDIA_VFE_STATE_Scoreboard4DeltaX_bits 4 +#define GEN9_MEDIA_VFE_STATE_Scoreboard4DeltaX_bits 4 +#define GEN8_MEDIA_VFE_STATE_Scoreboard4DeltaX_bits 4 +#define GEN75_MEDIA_VFE_STATE_Scoreboard4DeltaX_bits 4 +#define GEN7_MEDIA_VFE_STATE_Scoreboard4DeltaX_bits 4 +#define GEN6_MEDIA_VFE_STATE_Scoreboard4DeltaX_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_Scoreboard4DeltaX_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MEDIA_VFE_STATE_Scoreboard4DeltaX_start 256 +#define GEN9_MEDIA_VFE_STATE_Scoreboard4DeltaX_start 256 +#define GEN8_MEDIA_VFE_STATE_Scoreboard4DeltaX_start 256 +#define GEN75_MEDIA_VFE_STATE_Scoreboard4DeltaX_start 224 +#define GEN7_MEDIA_VFE_STATE_Scoreboard4DeltaX_start 224 +#define GEN6_MEDIA_VFE_STATE_Scoreboard4DeltaX_start 224 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_Scoreboard4DeltaX_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 256; + case 9: return 256; + case 8: return 256; + case 7: + if (devinfo->is_haswell) { + return 224; + } else { + return 224; + } + case 6: return 224; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::Scoreboard 4 Delta Y */ + + +#define GEN10_MEDIA_VFE_STATE_Scoreboard4DeltaY_bits 4 +#define GEN9_MEDIA_VFE_STATE_Scoreboard4DeltaY_bits 4 +#define GEN8_MEDIA_VFE_STATE_Scoreboard4DeltaY_bits 4 +#define GEN75_MEDIA_VFE_STATE_Scoreboard4DeltaY_bits 4 +#define GEN7_MEDIA_VFE_STATE_Scoreboard4DeltaY_bits 4 +#define GEN6_MEDIA_VFE_STATE_Scoreboard4DeltaY_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_Scoreboard4DeltaY_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MEDIA_VFE_STATE_Scoreboard4DeltaY_start 260 +#define GEN9_MEDIA_VFE_STATE_Scoreboard4DeltaY_start 260 +#define GEN8_MEDIA_VFE_STATE_Scoreboard4DeltaY_start 260 +#define GEN75_MEDIA_VFE_STATE_Scoreboard4DeltaY_start 228 +#define GEN7_MEDIA_VFE_STATE_Scoreboard4DeltaY_start 228 +#define GEN6_MEDIA_VFE_STATE_Scoreboard4DeltaY_start 228 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_Scoreboard4DeltaY_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 260; + case 9: return 260; + case 8: return 260; + case 7: + if (devinfo->is_haswell) { + return 228; + } else { + return 228; + } + case 6: return 228; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::Scoreboard 5 Delta X */ + + +#define GEN10_MEDIA_VFE_STATE_Scoreboard5DeltaX_bits 4 +#define GEN9_MEDIA_VFE_STATE_Scoreboard5DeltaX_bits 4 +#define GEN8_MEDIA_VFE_STATE_Scoreboard5DeltaX_bits 4 +#define GEN75_MEDIA_VFE_STATE_Scoreboard5DeltaX_bits 4 +#define GEN7_MEDIA_VFE_STATE_Scoreboard5DeltaX_bits 4 +#define GEN6_MEDIA_VFE_STATE_Scoreboard5DeltaX_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_Scoreboard5DeltaX_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MEDIA_VFE_STATE_Scoreboard5DeltaX_start 264 +#define GEN9_MEDIA_VFE_STATE_Scoreboard5DeltaX_start 264 +#define GEN8_MEDIA_VFE_STATE_Scoreboard5DeltaX_start 264 +#define GEN75_MEDIA_VFE_STATE_Scoreboard5DeltaX_start 232 +#define GEN7_MEDIA_VFE_STATE_Scoreboard5DeltaX_start 232 +#define GEN6_MEDIA_VFE_STATE_Scoreboard5DeltaX_start 232 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_Scoreboard5DeltaX_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 264; + case 9: return 264; + case 8: return 264; + case 7: + if (devinfo->is_haswell) { + return 232; + } else { + return 232; + } + case 6: return 232; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::Scoreboard 5 Delta Y */ + + +#define GEN10_MEDIA_VFE_STATE_Scoreboard5DeltaY_bits 4 +#define GEN9_MEDIA_VFE_STATE_Scoreboard5DeltaY_bits 4 +#define GEN8_MEDIA_VFE_STATE_Scoreboard5DeltaY_bits 4 +#define GEN75_MEDIA_VFE_STATE_Scoreboard5DeltaY_bits 4 +#define GEN7_MEDIA_VFE_STATE_Scoreboard5DeltaY_bits 4 +#define GEN6_MEDIA_VFE_STATE_Scoreboard5DeltaY_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_Scoreboard5DeltaY_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MEDIA_VFE_STATE_Scoreboard5DeltaY_start 268 +#define GEN9_MEDIA_VFE_STATE_Scoreboard5DeltaY_start 268 +#define GEN8_MEDIA_VFE_STATE_Scoreboard5DeltaY_start 268 +#define GEN75_MEDIA_VFE_STATE_Scoreboard5DeltaY_start 236 +#define GEN7_MEDIA_VFE_STATE_Scoreboard5DeltaY_start 236 +#define GEN6_MEDIA_VFE_STATE_Scoreboard5DeltaY_start 236 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_Scoreboard5DeltaY_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 268; + case 9: return 268; + case 8: return 268; + case 7: + if (devinfo->is_haswell) { + return 236; + } else { + return 236; + } + case 6: return 236; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::Scoreboard 6 Delta X */ + + +#define GEN10_MEDIA_VFE_STATE_Scoreboard6DeltaX_bits 4 +#define GEN9_MEDIA_VFE_STATE_Scoreboard6DeltaX_bits 4 +#define GEN8_MEDIA_VFE_STATE_Scoreboard6DeltaX_bits 4 +#define GEN75_MEDIA_VFE_STATE_Scoreboard6DeltaX_bits 4 +#define GEN7_MEDIA_VFE_STATE_Scoreboard6DeltaX_bits 4 +#define GEN6_MEDIA_VFE_STATE_Scoreboard6DeltaX_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_Scoreboard6DeltaX_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MEDIA_VFE_STATE_Scoreboard6DeltaX_start 272 +#define GEN9_MEDIA_VFE_STATE_Scoreboard6DeltaX_start 272 +#define GEN8_MEDIA_VFE_STATE_Scoreboard6DeltaX_start 272 +#define GEN75_MEDIA_VFE_STATE_Scoreboard6DeltaX_start 240 +#define GEN7_MEDIA_VFE_STATE_Scoreboard6DeltaX_start 240 +#define GEN6_MEDIA_VFE_STATE_Scoreboard6DeltaX_start 240 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_Scoreboard6DeltaX_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 272; + case 9: return 272; + case 8: return 272; + case 7: + if (devinfo->is_haswell) { + return 240; + } else { + return 240; + } + case 6: return 240; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::Scoreboard 6 Delta Y */ + + +#define GEN10_MEDIA_VFE_STATE_Scoreboard6DeltaY_bits 4 +#define GEN9_MEDIA_VFE_STATE_Scoreboard6DeltaY_bits 4 +#define GEN8_MEDIA_VFE_STATE_Scoreboard6DeltaY_bits 4 +#define GEN75_MEDIA_VFE_STATE_Scoreboard6DeltaY_bits 4 +#define GEN7_MEDIA_VFE_STATE_Scoreboard6DeltaY_bits 4 +#define GEN6_MEDIA_VFE_STATE_Scoreboard6DeltaY_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_Scoreboard6DeltaY_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MEDIA_VFE_STATE_Scoreboard6DeltaY_start 276 +#define GEN9_MEDIA_VFE_STATE_Scoreboard6DeltaY_start 276 +#define GEN8_MEDIA_VFE_STATE_Scoreboard6DeltaY_start 276 +#define GEN75_MEDIA_VFE_STATE_Scoreboard6DeltaY_start 244 +#define GEN7_MEDIA_VFE_STATE_Scoreboard6DeltaY_start 244 +#define GEN6_MEDIA_VFE_STATE_Scoreboard6DeltaY_start 244 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_Scoreboard6DeltaY_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 276; + case 9: return 276; + case 8: return 276; + case 7: + if (devinfo->is_haswell) { + return 244; + } else { + return 244; + } + case 6: return 244; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::Scoreboard 7 Delta X */ + + +#define GEN10_MEDIA_VFE_STATE_Scoreboard7DeltaX_bits 4 +#define GEN9_MEDIA_VFE_STATE_Scoreboard7DeltaX_bits 4 +#define GEN8_MEDIA_VFE_STATE_Scoreboard7DeltaX_bits 4 +#define GEN75_MEDIA_VFE_STATE_Scoreboard7DeltaX_bits 4 +#define GEN7_MEDIA_VFE_STATE_Scoreboard7DeltaX_bits 4 +#define GEN6_MEDIA_VFE_STATE_Scoreboard7DeltaX_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_Scoreboard7DeltaX_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MEDIA_VFE_STATE_Scoreboard7DeltaX_start 280 +#define GEN9_MEDIA_VFE_STATE_Scoreboard7DeltaX_start 280 +#define GEN8_MEDIA_VFE_STATE_Scoreboard7DeltaX_start 280 +#define GEN75_MEDIA_VFE_STATE_Scoreboard7DeltaX_start 248 +#define GEN7_MEDIA_VFE_STATE_Scoreboard7DeltaX_start 248 +#define GEN6_MEDIA_VFE_STATE_Scoreboard7DeltaX_start 248 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_Scoreboard7DeltaX_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 280; + case 9: return 280; + case 8: return 280; + case 7: + if (devinfo->is_haswell) { + return 248; + } else { + return 248; + } + case 6: return 248; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::Scoreboard 7 Delta Y */ + + +#define GEN10_MEDIA_VFE_STATE_Scoreboard7DeltaY_bits 4 +#define GEN9_MEDIA_VFE_STATE_Scoreboard7DeltaY_bits 4 +#define GEN8_MEDIA_VFE_STATE_Scoreboard7DeltaY_bits 4 +#define GEN75_MEDIA_VFE_STATE_Scoreboard7DeltaY_bits 4 +#define GEN7_MEDIA_VFE_STATE_Scoreboard7DeltaY_bits 4 +#define GEN6_MEDIA_VFE_STATE_Scoreboard7DeltaY_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_Scoreboard7DeltaY_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MEDIA_VFE_STATE_Scoreboard7DeltaY_start 284 +#define GEN9_MEDIA_VFE_STATE_Scoreboard7DeltaY_start 284 +#define GEN8_MEDIA_VFE_STATE_Scoreboard7DeltaY_start 284 +#define GEN75_MEDIA_VFE_STATE_Scoreboard7DeltaY_start 252 +#define GEN7_MEDIA_VFE_STATE_Scoreboard7DeltaY_start 252 +#define GEN6_MEDIA_VFE_STATE_Scoreboard7DeltaY_start 252 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_Scoreboard7DeltaY_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 284; + case 9: return 284; + case 8: return 284; + case 7: + if (devinfo->is_haswell) { + return 252; + } else { + return 252; + } + case 6: return 252; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::Scoreboard Enable */ + + +#define GEN10_MEDIA_VFE_STATE_ScoreboardEnable_bits 1 +#define GEN9_MEDIA_VFE_STATE_ScoreboardEnable_bits 1 +#define GEN8_MEDIA_VFE_STATE_ScoreboardEnable_bits 1 +#define GEN75_MEDIA_VFE_STATE_ScoreboardEnable_bits 1 +#define GEN7_MEDIA_VFE_STATE_ScoreboardEnable_bits 1 +#define GEN6_MEDIA_VFE_STATE_ScoreboardEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_ScoreboardEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MEDIA_VFE_STATE_ScoreboardEnable_start 223 +#define GEN9_MEDIA_VFE_STATE_ScoreboardEnable_start 223 +#define GEN8_MEDIA_VFE_STATE_ScoreboardEnable_start 223 +#define GEN75_MEDIA_VFE_STATE_ScoreboardEnable_start 191 +#define GEN7_MEDIA_VFE_STATE_ScoreboardEnable_start 191 +#define GEN6_MEDIA_VFE_STATE_ScoreboardEnable_start 191 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_ScoreboardEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 223; + case 9: return 223; + case 8: return 223; + case 7: + if (devinfo->is_haswell) { + return 191; + } else { + return 191; + } + case 6: return 191; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::Scoreboard Mask */ + + +#define GEN10_MEDIA_VFE_STATE_ScoreboardMask_bits 8 +#define GEN9_MEDIA_VFE_STATE_ScoreboardMask_bits 8 +#define GEN8_MEDIA_VFE_STATE_ScoreboardMask_bits 8 +#define GEN75_MEDIA_VFE_STATE_ScoreboardMask_bits 8 +#define GEN7_MEDIA_VFE_STATE_ScoreboardMask_bits 8 +#define GEN6_MEDIA_VFE_STATE_ScoreboardMask_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_ScoreboardMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MEDIA_VFE_STATE_ScoreboardMask_start 192 +#define GEN9_MEDIA_VFE_STATE_ScoreboardMask_start 192 +#define GEN8_MEDIA_VFE_STATE_ScoreboardMask_start 192 +#define GEN75_MEDIA_VFE_STATE_ScoreboardMask_start 160 +#define GEN7_MEDIA_VFE_STATE_ScoreboardMask_start 160 +#define GEN6_MEDIA_VFE_STATE_ScoreboardMask_start 160 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_ScoreboardMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 192; + case 9: return 192; + case 8: return 192; + case 7: + if (devinfo->is_haswell) { + return 160; + } else { + return 160; + } + case 6: return 160; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::Scoreboard Type */ + + +#define GEN10_MEDIA_VFE_STATE_ScoreboardType_bits 1 +#define GEN9_MEDIA_VFE_STATE_ScoreboardType_bits 1 +#define GEN8_MEDIA_VFE_STATE_ScoreboardType_bits 1 +#define GEN75_MEDIA_VFE_STATE_ScoreboardType_bits 1 +#define GEN7_MEDIA_VFE_STATE_ScoreboardType_bits 1 +#define GEN6_MEDIA_VFE_STATE_ScoreboardType_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_ScoreboardType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MEDIA_VFE_STATE_ScoreboardType_start 222 +#define GEN9_MEDIA_VFE_STATE_ScoreboardType_start 222 +#define GEN8_MEDIA_VFE_STATE_ScoreboardType_start 222 +#define GEN75_MEDIA_VFE_STATE_ScoreboardType_start 190 +#define GEN7_MEDIA_VFE_STATE_ScoreboardType_start 190 +#define GEN6_MEDIA_VFE_STATE_ScoreboardType_start 190 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_ScoreboardType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 222; + case 9: return 222; + case 8: return 222; + case 7: + if (devinfo->is_haswell) { + return 190; + } else { + return 190; + } + case 6: return 190; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::Scratch Space Base Pointer */ + + +#define GEN11_MEDIA_VFE_STATE_ScratchSpaceBasePointer_bits 38 +#define GEN10_MEDIA_VFE_STATE_ScratchSpaceBasePointer_bits 38 +#define GEN9_MEDIA_VFE_STATE_ScratchSpaceBasePointer_bits 38 +#define GEN8_MEDIA_VFE_STATE_ScratchSpaceBasePointer_bits 38 +#define GEN75_MEDIA_VFE_STATE_ScratchSpaceBasePointer_bits 22 +#define GEN7_MEDIA_VFE_STATE_ScratchSpaceBasePointer_bits 22 +#define GEN6_MEDIA_VFE_STATE_ScratchSpaceBasePointer_bits 22 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_ScratchSpaceBasePointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 38; + case 10: return 38; + case 9: return 38; + case 8: return 38; + case 7: + if (devinfo->is_haswell) { + return 22; + } else { + return 22; + } + case 6: return 22; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_VFE_STATE_ScratchSpaceBasePointer_start 42 +#define GEN10_MEDIA_VFE_STATE_ScratchSpaceBasePointer_start 42 +#define GEN9_MEDIA_VFE_STATE_ScratchSpaceBasePointer_start 42 +#define GEN8_MEDIA_VFE_STATE_ScratchSpaceBasePointer_start 42 +#define GEN75_MEDIA_VFE_STATE_ScratchSpaceBasePointer_start 42 +#define GEN7_MEDIA_VFE_STATE_ScratchSpaceBasePointer_start 42 +#define GEN6_MEDIA_VFE_STATE_ScratchSpaceBasePointer_start 42 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_ScratchSpaceBasePointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 42; + case 10: return 42; + case 9: return 42; + case 8: return 42; + case 7: + if (devinfo->is_haswell) { + return 42; + } else { + return 42; + } + case 6: return 42; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::Slice Disable */ + + +#define GEN10_MEDIA_VFE_STATE_SliceDisable_bits 2 +#define GEN9_MEDIA_VFE_STATE_SliceDisable_bits 2 +#define GEN8_MEDIA_VFE_STATE_SliceDisable_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_SliceDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MEDIA_VFE_STATE_SliceDisable_start 128 +#define GEN9_MEDIA_VFE_STATE_SliceDisable_start 128 +#define GEN8_MEDIA_VFE_STATE_SliceDisable_start 128 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_SliceDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 128; + case 9: return 128; + case 8: return 128; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::Stack Size */ + + +#define GEN11_MEDIA_VFE_STATE_StackSize_bits 4 +#define GEN10_MEDIA_VFE_STATE_StackSize_bits 4 +#define GEN9_MEDIA_VFE_STATE_StackSize_bits 4 +#define GEN8_MEDIA_VFE_STATE_StackSize_bits 4 +#define GEN75_MEDIA_VFE_STATE_StackSize_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_StackSize_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_VFE_STATE_StackSize_start 36 +#define GEN10_MEDIA_VFE_STATE_StackSize_start 36 +#define GEN9_MEDIA_VFE_STATE_StackSize_start 36 +#define GEN8_MEDIA_VFE_STATE_StackSize_start 36 +#define GEN75_MEDIA_VFE_STATE_StackSize_start 36 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_StackSize_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 36; + case 10: return 36; + case 9: return 36; + case 8: return 36; + case 7: + if (devinfo->is_haswell) { + return 36; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::SubOpcode */ + + +#define GEN11_MEDIA_VFE_STATE_SubOpcode_bits 8 +#define GEN10_MEDIA_VFE_STATE_SubOpcode_bits 8 +#define GEN9_MEDIA_VFE_STATE_SubOpcode_bits 8 +#define GEN8_MEDIA_VFE_STATE_SubOpcode_bits 8 +#define GEN75_MEDIA_VFE_STATE_SubOpcode_bits 8 +#define GEN7_MEDIA_VFE_STATE_SubOpcode_bits 8 +#define GEN6_MEDIA_VFE_STATE_SubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_SubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_VFE_STATE_SubOpcode_start 16 +#define GEN10_MEDIA_VFE_STATE_SubOpcode_start 16 +#define GEN9_MEDIA_VFE_STATE_SubOpcode_start 16 +#define GEN8_MEDIA_VFE_STATE_SubOpcode_start 16 +#define GEN75_MEDIA_VFE_STATE_SubOpcode_start 16 +#define GEN7_MEDIA_VFE_STATE_SubOpcode_start 16 +#define GEN6_MEDIA_VFE_STATE_SubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_SubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::Thread Dispatch Selection Policy */ + + +#define GEN10_MEDIA_VFE_STATE_ThreadDispatchSelectionPolicy_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_ThreadDispatchSelectionPolicy_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 2; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MEDIA_VFE_STATE_ThreadDispatchSelectionPolicy_start 100 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_ThreadDispatchSelectionPolicy_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 100; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEDIA_VFE_STATE::URB Entry Allocation Size */ + + +#define GEN11_MEDIA_VFE_STATE_URBEntryAllocationSize_bits 16 +#define GEN10_MEDIA_VFE_STATE_URBEntryAllocationSize_bits 16 +#define GEN9_MEDIA_VFE_STATE_URBEntryAllocationSize_bits 16 +#define GEN8_MEDIA_VFE_STATE_URBEntryAllocationSize_bits 16 +#define GEN75_MEDIA_VFE_STATE_URBEntryAllocationSize_bits 16 +#define GEN7_MEDIA_VFE_STATE_URBEntryAllocationSize_bits 16 +#define GEN6_MEDIA_VFE_STATE_URBEntryAllocationSize_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_URBEntryAllocationSize_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MEDIA_VFE_STATE_URBEntryAllocationSize_start 176 +#define GEN10_MEDIA_VFE_STATE_URBEntryAllocationSize_start 176 +#define GEN9_MEDIA_VFE_STATE_URBEntryAllocationSize_start 176 +#define GEN8_MEDIA_VFE_STATE_URBEntryAllocationSize_start 176 +#define GEN75_MEDIA_VFE_STATE_URBEntryAllocationSize_start 144 +#define GEN7_MEDIA_VFE_STATE_URBEntryAllocationSize_start 144 +#define GEN6_MEDIA_VFE_STATE_URBEntryAllocationSize_start 144 + +static inline uint32_t ATTRIBUTE_PURE +MEDIA_VFE_STATE_URBEntryAllocationSize_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 176; + case 10: return 176; + case 9: return 176; + case 8: return 176; + case 7: + if (devinfo->is_haswell) { + return 144; + } else { + return 144; + } + case 6: return 144; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEMORY_OBJECT_CONTROL_STATE */ + + +#define GEN8_MEMORY_OBJECT_CONTROL_STATE_length 1 +#define GEN75_MEMORY_OBJECT_CONTROL_STATE_length 1 +#define GEN7_MEMORY_OBJECT_CONTROL_STATE_length 1 +#define GEN6_MEMORY_OBJECT_CONTROL_STATE_length 1 +#define GEN5_MEMORY_OBJECT_CONTROL_STATE_length 1 + +static inline uint32_t ATTRIBUTE_PURE +MEMORY_OBJECT_CONTROL_STATE_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEMORY_OBJECT_CONTROL_STATE::Age for QUADLRU */ + + +#define GEN8_MEMORY_OBJECT_CONTROL_STATE_AgeforQUADLRU_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +MEMORY_OBJECT_CONTROL_STATE_AgeforQUADLRU_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_MEMORY_OBJECT_CONTROL_STATE_AgeforQUADLRU_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MEMORY_OBJECT_CONTROL_STATE_AgeforQUADLRU_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEMORY_OBJECT_CONTROL_STATE::Cacheability Control */ + + +#define GEN6_MEMORY_OBJECT_CONTROL_STATE_CacheabilityControl_bits 2 +#define GEN5_MEMORY_OBJECT_CONTROL_STATE_CacheabilityControl_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +MEMORY_OBJECT_CONTROL_STATE_CacheabilityControl_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 2; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_MEMORY_OBJECT_CONTROL_STATE_CacheabilityControl_start 0 +#define GEN5_MEMORY_OBJECT_CONTROL_STATE_CacheabilityControl_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MEMORY_OBJECT_CONTROL_STATE_CacheabilityControl_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEMORY_OBJECT_CONTROL_STATE::Encrypted Data */ + + +#define GEN5_MEMORY_OBJECT_CONTROL_STATE_EncryptedData_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MEMORY_OBJECT_CONTROL_STATE_EncryptedData_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_MEMORY_OBJECT_CONTROL_STATE_EncryptedData_start 3 + +static inline uint32_t ATTRIBUTE_PURE +MEMORY_OBJECT_CONTROL_STATE_EncryptedData_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEMORY_OBJECT_CONTROL_STATE::Graphics Data Type (GFDT) */ + + +#define GEN7_MEMORY_OBJECT_CONTROL_STATE_GraphicsDataTypeGFDT_bits 1 +#define GEN6_MEMORY_OBJECT_CONTROL_STATE_GraphicsDataTypeGFDT_bits 1 +#define GEN5_MEMORY_OBJECT_CONTROL_STATE_GraphicsDataTypeGFDT_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MEMORY_OBJECT_CONTROL_STATE_GraphicsDataTypeGFDT_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN7_MEMORY_OBJECT_CONTROL_STATE_GraphicsDataTypeGFDT_start 2 +#define GEN6_MEMORY_OBJECT_CONTROL_STATE_GraphicsDataTypeGFDT_start 2 +#define GEN5_MEMORY_OBJECT_CONTROL_STATE_GraphicsDataTypeGFDT_start 2 + +static inline uint32_t ATTRIBUTE_PURE +MEMORY_OBJECT_CONTROL_STATE_GraphicsDataTypeGFDT_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 2; + } + case 6: return 2; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEMORY_OBJECT_CONTROL_STATE::L3 Cacheability Control (L3CC) */ + + +#define GEN75_MEMORY_OBJECT_CONTROL_STATE_L3CacheabilityControlL3CC_bits 1 +#define GEN7_MEMORY_OBJECT_CONTROL_STATE_L3CacheabilityControlL3CC_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MEMORY_OBJECT_CONTROL_STATE_L3CacheabilityControlL3CC_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_MEMORY_OBJECT_CONTROL_STATE_L3CacheabilityControlL3CC_start 0 +#define GEN7_MEMORY_OBJECT_CONTROL_STATE_L3CacheabilityControlL3CC_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MEMORY_OBJECT_CONTROL_STATE_L3CacheabilityControlL3CC_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEMORY_OBJECT_CONTROL_STATE::LLC Cacheability Control (LLCCC) */ + + +#define GEN7_MEMORY_OBJECT_CONTROL_STATE_LLCCacheabilityControlLLCCC_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MEMORY_OBJECT_CONTROL_STATE_LLCCacheabilityControlLLCCC_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN7_MEMORY_OBJECT_CONTROL_STATE_LLCCacheabilityControlLLCCC_start 1 + +static inline uint32_t ATTRIBUTE_PURE +MEMORY_OBJECT_CONTROL_STATE_LLCCacheabilityControlLLCCC_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEMORY_OBJECT_CONTROL_STATE::LLC/eLLC Cacheability Control (LLCCC) */ + + +#define GEN75_MEMORY_OBJECT_CONTROL_STATE_LLCeLLCCacheabilityControlLLCCC_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +MEMORY_OBJECT_CONTROL_STATE_LLCeLLCCacheabilityControlLLCCC_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_MEMORY_OBJECT_CONTROL_STATE_LLCeLLCCacheabilityControlLLCCC_start 1 + +static inline uint32_t ATTRIBUTE_PURE +MEMORY_OBJECT_CONTROL_STATE_LLCeLLCCacheabilityControlLLCCC_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEMORY_OBJECT_CONTROL_STATE::Memory Type:LLC/eLLC Cacheability Control */ + + +#define GEN8_MEMORY_OBJECT_CONTROL_STATE_MemoryTypeLLCeLLCCacheabilityControl_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +MEMORY_OBJECT_CONTROL_STATE_MemoryTypeLLCeLLCCacheabilityControl_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_MEMORY_OBJECT_CONTROL_STATE_MemoryTypeLLCeLLCCacheabilityControl_start 5 + +static inline uint32_t ATTRIBUTE_PURE +MEMORY_OBJECT_CONTROL_STATE_MemoryTypeLLCeLLCCacheabilityControl_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MEMORY_OBJECT_CONTROL_STATE::Target Cache */ + + +#define GEN8_MEMORY_OBJECT_CONTROL_STATE_TargetCache_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +MEMORY_OBJECT_CONTROL_STATE_TargetCache_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_MEMORY_OBJECT_CONTROL_STATE_TargetCache_start 3 + +static inline uint32_t ATTRIBUTE_PURE +MEMORY_OBJECT_CONTROL_STATE_TargetCache_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_ARB_CHECK */ + + +#define GEN11_MI_ARB_CHECK_length 1 +#define GEN10_MI_ARB_CHECK_length 1 +#define GEN9_MI_ARB_CHECK_length 1 +#define GEN8_MI_ARB_CHECK_length 1 +#define GEN75_MI_ARB_CHECK_length 1 +#define GEN7_MI_ARB_CHECK_length 1 +#define GEN6_MI_ARB_CHECK_length 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_ARB_CHECK_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_ARB_CHECK::Command Type */ + + +#define GEN11_MI_ARB_CHECK_CommandType_bits 3 +#define GEN10_MI_ARB_CHECK_CommandType_bits 3 +#define GEN9_MI_ARB_CHECK_CommandType_bits 3 +#define GEN8_MI_ARB_CHECK_CommandType_bits 3 +#define GEN75_MI_ARB_CHECK_CommandType_bits 3 +#define GEN7_MI_ARB_CHECK_CommandType_bits 3 +#define GEN6_MI_ARB_CHECK_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_ARB_CHECK_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_ARB_CHECK_CommandType_start 29 +#define GEN10_MI_ARB_CHECK_CommandType_start 29 +#define GEN9_MI_ARB_CHECK_CommandType_start 29 +#define GEN8_MI_ARB_CHECK_CommandType_start 29 +#define GEN75_MI_ARB_CHECK_CommandType_start 29 +#define GEN7_MI_ARB_CHECK_CommandType_start 29 +#define GEN6_MI_ARB_CHECK_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_ARB_CHECK_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_ARB_CHECK::MI Command Opcode */ + + +#define GEN11_MI_ARB_CHECK_MICommandOpcode_bits 6 +#define GEN10_MI_ARB_CHECK_MICommandOpcode_bits 6 +#define GEN9_MI_ARB_CHECK_MICommandOpcode_bits 6 +#define GEN8_MI_ARB_CHECK_MICommandOpcode_bits 6 +#define GEN75_MI_ARB_CHECK_MICommandOpcode_bits 6 +#define GEN7_MI_ARB_CHECK_MICommandOpcode_bits 6 +#define GEN6_MI_ARB_CHECK_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_ARB_CHECK_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 6; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_ARB_CHECK_MICommandOpcode_start 23 +#define GEN10_MI_ARB_CHECK_MICommandOpcode_start 23 +#define GEN9_MI_ARB_CHECK_MICommandOpcode_start 23 +#define GEN8_MI_ARB_CHECK_MICommandOpcode_start 23 +#define GEN75_MI_ARB_CHECK_MICommandOpcode_start 23 +#define GEN7_MI_ARB_CHECK_MICommandOpcode_start 23 +#define GEN6_MI_ARB_CHECK_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_ARB_CHECK_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 23; + } else { + return 23; + } + case 6: return 23; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_ARB_ON_OFF */ + + +#define GEN11_MI_ARB_ON_OFF_length 1 +#define GEN10_MI_ARB_ON_OFF_length 1 +#define GEN9_MI_ARB_ON_OFF_length 1 +#define GEN8_MI_ARB_ON_OFF_length 1 +#define GEN75_MI_ARB_ON_OFF_length 1 +#define GEN7_MI_ARB_ON_OFF_length 1 +#define GEN6_MI_ARB_ON_OFF_length 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_ARB_ON_OFF_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_ARB_ON_OFF::Allow Lite Restore */ + + +#define GEN11_MI_ARB_ON_OFF_AllowLiteRestore_bits 1 +#define GEN10_MI_ARB_ON_OFF_AllowLiteRestore_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_ARB_ON_OFF_AllowLiteRestore_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_ARB_ON_OFF_AllowLiteRestore_start 1 +#define GEN10_MI_ARB_ON_OFF_AllowLiteRestore_start 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_ARB_ON_OFF_AllowLiteRestore_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_ARB_ON_OFF::Arbitration Enable */ + + +#define GEN11_MI_ARB_ON_OFF_ArbitrationEnable_bits 1 +#define GEN10_MI_ARB_ON_OFF_ArbitrationEnable_bits 1 +#define GEN9_MI_ARB_ON_OFF_ArbitrationEnable_bits 1 +#define GEN8_MI_ARB_ON_OFF_ArbitrationEnable_bits 1 +#define GEN75_MI_ARB_ON_OFF_ArbitrationEnable_bits 1 +#define GEN7_MI_ARB_ON_OFF_ArbitrationEnable_bits 1 +#define GEN6_MI_ARB_ON_OFF_ArbitrationEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_ARB_ON_OFF_ArbitrationEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_ARB_ON_OFF_ArbitrationEnable_start 0 +#define GEN10_MI_ARB_ON_OFF_ArbitrationEnable_start 0 +#define GEN9_MI_ARB_ON_OFF_ArbitrationEnable_start 0 +#define GEN8_MI_ARB_ON_OFF_ArbitrationEnable_start 0 +#define GEN75_MI_ARB_ON_OFF_ArbitrationEnable_start 0 +#define GEN7_MI_ARB_ON_OFF_ArbitrationEnable_start 0 +#define GEN6_MI_ARB_ON_OFF_ArbitrationEnable_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_ARB_ON_OFF_ArbitrationEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_ARB_ON_OFF::Command Type */ + + +#define GEN11_MI_ARB_ON_OFF_CommandType_bits 3 +#define GEN10_MI_ARB_ON_OFF_CommandType_bits 3 +#define GEN9_MI_ARB_ON_OFF_CommandType_bits 3 +#define GEN8_MI_ARB_ON_OFF_CommandType_bits 3 +#define GEN75_MI_ARB_ON_OFF_CommandType_bits 3 +#define GEN7_MI_ARB_ON_OFF_CommandType_bits 3 +#define GEN6_MI_ARB_ON_OFF_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_ARB_ON_OFF_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_ARB_ON_OFF_CommandType_start 29 +#define GEN10_MI_ARB_ON_OFF_CommandType_start 29 +#define GEN9_MI_ARB_ON_OFF_CommandType_start 29 +#define GEN8_MI_ARB_ON_OFF_CommandType_start 29 +#define GEN75_MI_ARB_ON_OFF_CommandType_start 29 +#define GEN7_MI_ARB_ON_OFF_CommandType_start 29 +#define GEN6_MI_ARB_ON_OFF_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_ARB_ON_OFF_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_ARB_ON_OFF::MI Command Opcode */ + + +#define GEN11_MI_ARB_ON_OFF_MICommandOpcode_bits 6 +#define GEN10_MI_ARB_ON_OFF_MICommandOpcode_bits 6 +#define GEN9_MI_ARB_ON_OFF_MICommandOpcode_bits 6 +#define GEN8_MI_ARB_ON_OFF_MICommandOpcode_bits 6 +#define GEN75_MI_ARB_ON_OFF_MICommandOpcode_bits 6 +#define GEN7_MI_ARB_ON_OFF_MICommandOpcode_bits 6 +#define GEN6_MI_ARB_ON_OFF_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_ARB_ON_OFF_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 6; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_ARB_ON_OFF_MICommandOpcode_start 23 +#define GEN10_MI_ARB_ON_OFF_MICommandOpcode_start 23 +#define GEN9_MI_ARB_ON_OFF_MICommandOpcode_start 23 +#define GEN8_MI_ARB_ON_OFF_MICommandOpcode_start 23 +#define GEN75_MI_ARB_ON_OFF_MICommandOpcode_start 23 +#define GEN7_MI_ARB_ON_OFF_MICommandOpcode_start 23 +#define GEN6_MI_ARB_ON_OFF_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_ARB_ON_OFF_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 23; + } else { + return 23; + } + case 6: return 23; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_ATOMIC */ + + +#define GEN11_MI_ATOMIC_length 3 +#define GEN10_MI_ATOMIC_length 3 +#define GEN9_MI_ATOMIC_length 3 +#define GEN8_MI_ATOMIC_length 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_ATOMIC::ATOMIC OPCODE */ + + +#define GEN11_MI_ATOMIC_ATOMICOPCODE_bits 8 +#define GEN10_MI_ATOMIC_ATOMICOPCODE_bits 8 +#define GEN9_MI_ATOMIC_ATOMICOPCODE_bits 8 +#define GEN8_MI_ATOMIC_ATOMICOPCODE_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_ATOMICOPCODE_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_ATOMIC_ATOMICOPCODE_start 8 +#define GEN10_MI_ATOMIC_ATOMICOPCODE_start 8 +#define GEN9_MI_ATOMIC_ATOMICOPCODE_start 8 +#define GEN8_MI_ATOMIC_ATOMICOPCODE_start 8 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_ATOMICOPCODE_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_ATOMIC::CS STALL */ + + +#define GEN11_MI_ATOMIC_CSSTALL_bits 1 +#define GEN10_MI_ATOMIC_CSSTALL_bits 1 +#define GEN9_MI_ATOMIC_CSSTALL_bits 1 +#define GEN8_MI_ATOMIC_CSSTALL_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_CSSTALL_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_ATOMIC_CSSTALL_start 17 +#define GEN10_MI_ATOMIC_CSSTALL_start 17 +#define GEN9_MI_ATOMIC_CSSTALL_start 17 +#define GEN8_MI_ATOMIC_CSSTALL_start 17 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_CSSTALL_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 17; + case 10: return 17; + case 9: return 17; + case 8: return 17; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_ATOMIC::Command Type */ + + +#define GEN11_MI_ATOMIC_CommandType_bits 3 +#define GEN10_MI_ATOMIC_CommandType_bits 3 +#define GEN9_MI_ATOMIC_CommandType_bits 3 +#define GEN8_MI_ATOMIC_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_ATOMIC_CommandType_start 29 +#define GEN10_MI_ATOMIC_CommandType_start 29 +#define GEN9_MI_ATOMIC_CommandType_start 29 +#define GEN8_MI_ATOMIC_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_ATOMIC::DWord Length */ + + +#define GEN11_MI_ATOMIC_DWordLength_bits 8 +#define GEN10_MI_ATOMIC_DWordLength_bits 8 +#define GEN9_MI_ATOMIC_DWordLength_bits 8 +#define GEN8_MI_ATOMIC_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_ATOMIC_DWordLength_start 0 +#define GEN10_MI_ATOMIC_DWordLength_start 0 +#define GEN9_MI_ATOMIC_DWordLength_start 0 +#define GEN8_MI_ATOMIC_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_ATOMIC::Data Size */ + + +#define GEN11_MI_ATOMIC_DataSize_bits 2 +#define GEN10_MI_ATOMIC_DataSize_bits 2 +#define GEN9_MI_ATOMIC_DataSize_bits 2 +#define GEN8_MI_ATOMIC_DataSize_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_DataSize_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_ATOMIC_DataSize_start 19 +#define GEN10_MI_ATOMIC_DataSize_start 19 +#define GEN9_MI_ATOMIC_DataSize_start 19 +#define GEN8_MI_ATOMIC_DataSize_start 19 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_DataSize_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 19; + case 10: return 19; + case 9: return 19; + case 8: return 19; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_ATOMIC::Inline Data */ + + +#define GEN11_MI_ATOMIC_InlineData_bits 1 +#define GEN10_MI_ATOMIC_InlineData_bits 1 +#define GEN9_MI_ATOMIC_InlineData_bits 1 +#define GEN8_MI_ATOMIC_InlineData_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_InlineData_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_ATOMIC_InlineData_start 18 +#define GEN10_MI_ATOMIC_InlineData_start 18 +#define GEN9_MI_ATOMIC_InlineData_start 18 +#define GEN8_MI_ATOMIC_InlineData_start 18 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_InlineData_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 18; + case 10: return 18; + case 9: return 18; + case 8: return 18; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_ATOMIC::MI Command Opcode */ + + +#define GEN11_MI_ATOMIC_MICommandOpcode_bits 6 +#define GEN10_MI_ATOMIC_MICommandOpcode_bits 6 +#define GEN9_MI_ATOMIC_MICommandOpcode_bits 6 +#define GEN8_MI_ATOMIC_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_ATOMIC_MICommandOpcode_start 23 +#define GEN10_MI_ATOMIC_MICommandOpcode_start 23 +#define GEN9_MI_ATOMIC_MICommandOpcode_start 23 +#define GEN8_MI_ATOMIC_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_ATOMIC::Memory Address */ + + +#define GEN11_MI_ATOMIC_MemoryAddress_bits 46 +#define GEN10_MI_ATOMIC_MemoryAddress_bits 46 +#define GEN9_MI_ATOMIC_MemoryAddress_bits 46 +#define GEN8_MI_ATOMIC_MemoryAddress_bits 46 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_MemoryAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 46; + case 10: return 46; + case 9: return 46; + case 8: return 46; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_ATOMIC_MemoryAddress_start 34 +#define GEN10_MI_ATOMIC_MemoryAddress_start 34 +#define GEN9_MI_ATOMIC_MemoryAddress_start 34 +#define GEN8_MI_ATOMIC_MemoryAddress_start 34 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_MemoryAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 34; + case 10: return 34; + case 9: return 34; + case 8: return 34; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_ATOMIC::Memory Type */ + + +#define GEN11_MI_ATOMIC_MemoryType_bits 1 +#define GEN10_MI_ATOMIC_MemoryType_bits 1 +#define GEN9_MI_ATOMIC_MemoryType_bits 1 +#define GEN8_MI_ATOMIC_MemoryType_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_MemoryType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_ATOMIC_MemoryType_start 22 +#define GEN10_MI_ATOMIC_MemoryType_start 22 +#define GEN9_MI_ATOMIC_MemoryType_start 22 +#define GEN8_MI_ATOMIC_MemoryType_start 22 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_MemoryType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 22; + case 10: return 22; + case 9: return 22; + case 8: return 22; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_ATOMIC::Operand1 Data Dword 0 */ + + +#define GEN11_MI_ATOMIC_Operand1DataDword0_bits 32 +#define GEN10_MI_ATOMIC_Operand1DataDword0_bits 32 +#define GEN9_MI_ATOMIC_Operand1DataDword0_bits 32 +#define GEN8_MI_ATOMIC_Operand1DataDword0_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_Operand1DataDword0_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_ATOMIC_Operand1DataDword0_start 96 +#define GEN10_MI_ATOMIC_Operand1DataDword0_start 96 +#define GEN9_MI_ATOMIC_Operand1DataDword0_start 96 +#define GEN8_MI_ATOMIC_Operand1DataDword0_start 96 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_Operand1DataDword0_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 96; + case 10: return 96; + case 9: return 96; + case 8: return 96; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_ATOMIC::Operand1 Data Dword 1 */ + + +#define GEN11_MI_ATOMIC_Operand1DataDword1_bits 32 +#define GEN10_MI_ATOMIC_Operand1DataDword1_bits 32 +#define GEN9_MI_ATOMIC_Operand1DataDword1_bits 32 +#define GEN8_MI_ATOMIC_Operand1DataDword1_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_Operand1DataDword1_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_ATOMIC_Operand1DataDword1_start 160 +#define GEN10_MI_ATOMIC_Operand1DataDword1_start 160 +#define GEN9_MI_ATOMIC_Operand1DataDword1_start 160 +#define GEN8_MI_ATOMIC_Operand1DataDword1_start 160 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_Operand1DataDword1_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 160; + case 10: return 160; + case 9: return 160; + case 8: return 160; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_ATOMIC::Operand1 Data Dword 2 */ + + +#define GEN11_MI_ATOMIC_Operand1DataDword2_bits 32 +#define GEN10_MI_ATOMIC_Operand1DataDword2_bits 32 +#define GEN9_MI_ATOMIC_Operand1DataDword2_bits 32 +#define GEN8_MI_ATOMIC_Operand1DataDword2_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_Operand1DataDword2_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_ATOMIC_Operand1DataDword2_start 224 +#define GEN10_MI_ATOMIC_Operand1DataDword2_start 224 +#define GEN9_MI_ATOMIC_Operand1DataDword2_start 224 +#define GEN8_MI_ATOMIC_Operand1DataDword2_start 224 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_Operand1DataDword2_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 224; + case 10: return 224; + case 9: return 224; + case 8: return 224; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_ATOMIC::Operand1 Data Dword 3 */ + + +#define GEN11_MI_ATOMIC_Operand1DataDword3_bits 32 +#define GEN10_MI_ATOMIC_Operand1DataDword3_bits 32 +#define GEN9_MI_ATOMIC_Operand1DataDword3_bits 32 +#define GEN8_MI_ATOMIC_Operand1DataDword3_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_Operand1DataDword3_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_ATOMIC_Operand1DataDword3_start 288 +#define GEN10_MI_ATOMIC_Operand1DataDword3_start 288 +#define GEN9_MI_ATOMIC_Operand1DataDword3_start 288 +#define GEN8_MI_ATOMIC_Operand1DataDword3_start 288 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_Operand1DataDword3_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 288; + case 10: return 288; + case 9: return 288; + case 8: return 288; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_ATOMIC::Operand2 Data Dword 0 */ + + +#define GEN11_MI_ATOMIC_Operand2DataDword0_bits 32 +#define GEN10_MI_ATOMIC_Operand2DataDword0_bits 32 +#define GEN9_MI_ATOMIC_Operand2DataDword0_bits 32 +#define GEN8_MI_ATOMIC_Operand2DataDword0_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_Operand2DataDword0_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_ATOMIC_Operand2DataDword0_start 128 +#define GEN10_MI_ATOMIC_Operand2DataDword0_start 128 +#define GEN9_MI_ATOMIC_Operand2DataDword0_start 128 +#define GEN8_MI_ATOMIC_Operand2DataDword0_start 128 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_Operand2DataDword0_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 128; + case 10: return 128; + case 9: return 128; + case 8: return 128; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_ATOMIC::Operand2 Data Dword 1 */ + + +#define GEN11_MI_ATOMIC_Operand2DataDword1_bits 32 +#define GEN10_MI_ATOMIC_Operand2DataDword1_bits 32 +#define GEN9_MI_ATOMIC_Operand2DataDword1_bits 32 +#define GEN8_MI_ATOMIC_Operand2DataDword1_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_Operand2DataDword1_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_ATOMIC_Operand2DataDword1_start 192 +#define GEN10_MI_ATOMIC_Operand2DataDword1_start 192 +#define GEN9_MI_ATOMIC_Operand2DataDword1_start 192 +#define GEN8_MI_ATOMIC_Operand2DataDword1_start 192 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_Operand2DataDword1_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 192; + case 10: return 192; + case 9: return 192; + case 8: return 192; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_ATOMIC::Operand2 Data Dword 2 */ + + +#define GEN11_MI_ATOMIC_Operand2DataDword2_bits 32 +#define GEN10_MI_ATOMIC_Operand2DataDword2_bits 32 +#define GEN9_MI_ATOMIC_Operand2DataDword2_bits 32 +#define GEN8_MI_ATOMIC_Operand2DataDword2_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_Operand2DataDword2_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_ATOMIC_Operand2DataDword2_start 256 +#define GEN10_MI_ATOMIC_Operand2DataDword2_start 256 +#define GEN9_MI_ATOMIC_Operand2DataDword2_start 256 +#define GEN8_MI_ATOMIC_Operand2DataDword2_start 256 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_Operand2DataDword2_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 256; + case 10: return 256; + case 9: return 256; + case 8: return 256; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_ATOMIC::Operand2 Data Dword 3 */ + + +#define GEN11_MI_ATOMIC_Operand2DataDword3_bits 32 +#define GEN10_MI_ATOMIC_Operand2DataDword3_bits 32 +#define GEN9_MI_ATOMIC_Operand2DataDword3_bits 32 +#define GEN8_MI_ATOMIC_Operand2DataDword3_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_Operand2DataDword3_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_ATOMIC_Operand2DataDword3_start 320 +#define GEN10_MI_ATOMIC_Operand2DataDword3_start 320 +#define GEN9_MI_ATOMIC_Operand2DataDword3_start 320 +#define GEN8_MI_ATOMIC_Operand2DataDword3_start 320 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_Operand2DataDword3_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 320; + case 10: return 320; + case 9: return 320; + case 8: return 320; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_ATOMIC::Post-Sync Operation */ + + +#define GEN11_MI_ATOMIC_PostSyncOperation_bits 1 +#define GEN10_MI_ATOMIC_PostSyncOperation_bits 1 +#define GEN9_MI_ATOMIC_PostSyncOperation_bits 1 +#define GEN8_MI_ATOMIC_PostSyncOperation_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_PostSyncOperation_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_ATOMIC_PostSyncOperation_start 21 +#define GEN10_MI_ATOMIC_PostSyncOperation_start 21 +#define GEN9_MI_ATOMIC_PostSyncOperation_start 21 +#define GEN8_MI_ATOMIC_PostSyncOperation_start 21 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_PostSyncOperation_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 21; + case 10: return 21; + case 9: return 21; + case 8: return 21; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_ATOMIC::Return Data Control */ + + +#define GEN11_MI_ATOMIC_ReturnDataControl_bits 1 +#define GEN10_MI_ATOMIC_ReturnDataControl_bits 1 +#define GEN9_MI_ATOMIC_ReturnDataControl_bits 1 +#define GEN8_MI_ATOMIC_ReturnDataControl_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_ReturnDataControl_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_ATOMIC_ReturnDataControl_start 16 +#define GEN10_MI_ATOMIC_ReturnDataControl_start 16 +#define GEN9_MI_ATOMIC_ReturnDataControl_start 16 +#define GEN8_MI_ATOMIC_ReturnDataControl_start 16 + +static inline uint32_t ATTRIBUTE_PURE +MI_ATOMIC_ReturnDataControl_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_BATCH_BUFFER_END */ + + +#define GEN11_MI_BATCH_BUFFER_END_length 1 +#define GEN10_MI_BATCH_BUFFER_END_length 1 +#define GEN9_MI_BATCH_BUFFER_END_length 1 +#define GEN8_MI_BATCH_BUFFER_END_length 1 +#define GEN75_MI_BATCH_BUFFER_END_length 1 +#define GEN7_MI_BATCH_BUFFER_END_length 1 +#define GEN6_MI_BATCH_BUFFER_END_length 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_BATCH_BUFFER_END_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_BATCH_BUFFER_END::Command Type */ + + +#define GEN11_MI_BATCH_BUFFER_END_CommandType_bits 3 +#define GEN10_MI_BATCH_BUFFER_END_CommandType_bits 3 +#define GEN9_MI_BATCH_BUFFER_END_CommandType_bits 3 +#define GEN8_MI_BATCH_BUFFER_END_CommandType_bits 3 +#define GEN75_MI_BATCH_BUFFER_END_CommandType_bits 3 +#define GEN7_MI_BATCH_BUFFER_END_CommandType_bits 3 +#define GEN6_MI_BATCH_BUFFER_END_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_BATCH_BUFFER_END_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_BATCH_BUFFER_END_CommandType_start 29 +#define GEN10_MI_BATCH_BUFFER_END_CommandType_start 29 +#define GEN9_MI_BATCH_BUFFER_END_CommandType_start 29 +#define GEN8_MI_BATCH_BUFFER_END_CommandType_start 29 +#define GEN75_MI_BATCH_BUFFER_END_CommandType_start 29 +#define GEN7_MI_BATCH_BUFFER_END_CommandType_start 29 +#define GEN6_MI_BATCH_BUFFER_END_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_BATCH_BUFFER_END_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_BATCH_BUFFER_END::End Context */ + + +#define GEN11_MI_BATCH_BUFFER_END_EndContext_bits 1 +#define GEN10_MI_BATCH_BUFFER_END_EndContext_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_BATCH_BUFFER_END_EndContext_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_BATCH_BUFFER_END_EndContext_start 0 +#define GEN10_MI_BATCH_BUFFER_END_EndContext_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_BATCH_BUFFER_END_EndContext_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_BATCH_BUFFER_END::MI Command Opcode */ + + +#define GEN11_MI_BATCH_BUFFER_END_MICommandOpcode_bits 6 +#define GEN10_MI_BATCH_BUFFER_END_MICommandOpcode_bits 6 +#define GEN9_MI_BATCH_BUFFER_END_MICommandOpcode_bits 6 +#define GEN8_MI_BATCH_BUFFER_END_MICommandOpcode_bits 6 +#define GEN75_MI_BATCH_BUFFER_END_MICommandOpcode_bits 6 +#define GEN7_MI_BATCH_BUFFER_END_MICommandOpcode_bits 6 +#define GEN6_MI_BATCH_BUFFER_END_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_BATCH_BUFFER_END_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 6; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_BATCH_BUFFER_END_MICommandOpcode_start 23 +#define GEN10_MI_BATCH_BUFFER_END_MICommandOpcode_start 23 +#define GEN9_MI_BATCH_BUFFER_END_MICommandOpcode_start 23 +#define GEN8_MI_BATCH_BUFFER_END_MICommandOpcode_start 23 +#define GEN75_MI_BATCH_BUFFER_END_MICommandOpcode_start 23 +#define GEN7_MI_BATCH_BUFFER_END_MICommandOpcode_start 23 +#define GEN6_MI_BATCH_BUFFER_END_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_BATCH_BUFFER_END_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 23; + } else { + return 23; + } + case 6: return 23; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_BATCH_BUFFER_START */ + + +#define GEN11_MI_BATCH_BUFFER_START_length 3 +#define GEN10_MI_BATCH_BUFFER_START_length 3 +#define GEN9_MI_BATCH_BUFFER_START_length 3 +#define GEN8_MI_BATCH_BUFFER_START_length 3 +#define GEN75_MI_BATCH_BUFFER_START_length 2 +#define GEN7_MI_BATCH_BUFFER_START_length 2 +#define GEN6_MI_BATCH_BUFFER_START_length 2 + +static inline uint32_t ATTRIBUTE_PURE +MI_BATCH_BUFFER_START_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_BATCH_BUFFER_START::Add Offset Enable */ + + +#define GEN10_MI_BATCH_BUFFER_START_AddOffsetEnable_bits 1 +#define GEN9_MI_BATCH_BUFFER_START_AddOffsetEnable_bits 1 +#define GEN8_MI_BATCH_BUFFER_START_AddOffsetEnable_bits 1 +#define GEN75_MI_BATCH_BUFFER_START_AddOffsetEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_BATCH_BUFFER_START_AddOffsetEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MI_BATCH_BUFFER_START_AddOffsetEnable_start 16 +#define GEN9_MI_BATCH_BUFFER_START_AddOffsetEnable_start 16 +#define GEN8_MI_BATCH_BUFFER_START_AddOffsetEnable_start 16 +#define GEN75_MI_BATCH_BUFFER_START_AddOffsetEnable_start 16 + +static inline uint32_t ATTRIBUTE_PURE +MI_BATCH_BUFFER_START_AddOffsetEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_BATCH_BUFFER_START::Address Space Indicator */ + + +#define GEN11_MI_BATCH_BUFFER_START_AddressSpaceIndicator_bits 1 +#define GEN10_MI_BATCH_BUFFER_START_AddressSpaceIndicator_bits 1 +#define GEN9_MI_BATCH_BUFFER_START_AddressSpaceIndicator_bits 1 +#define GEN8_MI_BATCH_BUFFER_START_AddressSpaceIndicator_bits 1 +#define GEN75_MI_BATCH_BUFFER_START_AddressSpaceIndicator_bits 1 +#define GEN7_MI_BATCH_BUFFER_START_AddressSpaceIndicator_bits 1 +#define GEN6_MI_BATCH_BUFFER_START_AddressSpaceIndicator_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_BATCH_BUFFER_START_AddressSpaceIndicator_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_BATCH_BUFFER_START_AddressSpaceIndicator_start 8 +#define GEN10_MI_BATCH_BUFFER_START_AddressSpaceIndicator_start 8 +#define GEN9_MI_BATCH_BUFFER_START_AddressSpaceIndicator_start 8 +#define GEN8_MI_BATCH_BUFFER_START_AddressSpaceIndicator_start 8 +#define GEN75_MI_BATCH_BUFFER_START_AddressSpaceIndicator_start 8 +#define GEN7_MI_BATCH_BUFFER_START_AddressSpaceIndicator_start 8 +#define GEN6_MI_BATCH_BUFFER_START_AddressSpaceIndicator_start 8 + +static inline uint32_t ATTRIBUTE_PURE +MI_BATCH_BUFFER_START_AddressSpaceIndicator_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_BATCH_BUFFER_START::Batch Buffer Start Address */ + + +#define GEN11_MI_BATCH_BUFFER_START_BatchBufferStartAddress_bits 62 +#define GEN10_MI_BATCH_BUFFER_START_BatchBufferStartAddress_bits 62 +#define GEN9_MI_BATCH_BUFFER_START_BatchBufferStartAddress_bits 62 +#define GEN8_MI_BATCH_BUFFER_START_BatchBufferStartAddress_bits 46 +#define GEN75_MI_BATCH_BUFFER_START_BatchBufferStartAddress_bits 30 +#define GEN7_MI_BATCH_BUFFER_START_BatchBufferStartAddress_bits 30 +#define GEN6_MI_BATCH_BUFFER_START_BatchBufferStartAddress_bits 30 + +static inline uint32_t ATTRIBUTE_PURE +MI_BATCH_BUFFER_START_BatchBufferStartAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 62; + case 10: return 62; + case 9: return 62; + case 8: return 46; + case 7: + if (devinfo->is_haswell) { + return 30; + } else { + return 30; + } + case 6: return 30; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_BATCH_BUFFER_START_BatchBufferStartAddress_start 34 +#define GEN10_MI_BATCH_BUFFER_START_BatchBufferStartAddress_start 34 +#define GEN9_MI_BATCH_BUFFER_START_BatchBufferStartAddress_start 34 +#define GEN8_MI_BATCH_BUFFER_START_BatchBufferStartAddress_start 34 +#define GEN75_MI_BATCH_BUFFER_START_BatchBufferStartAddress_start 34 +#define GEN7_MI_BATCH_BUFFER_START_BatchBufferStartAddress_start 34 +#define GEN6_MI_BATCH_BUFFER_START_BatchBufferStartAddress_start 34 + +static inline uint32_t ATTRIBUTE_PURE +MI_BATCH_BUFFER_START_BatchBufferStartAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 34; + case 10: return 34; + case 9: return 34; + case 8: return 34; + case 7: + if (devinfo->is_haswell) { + return 34; + } else { + return 34; + } + case 6: return 34; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_BATCH_BUFFER_START::Clear Command Buffer Enable */ + + +#define GEN75_MI_BATCH_BUFFER_START_ClearCommandBufferEnable_bits 1 +#define GEN7_MI_BATCH_BUFFER_START_ClearCommandBufferEnable_bits 1 +#define GEN6_MI_BATCH_BUFFER_START_ClearCommandBufferEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_BATCH_BUFFER_START_ClearCommandBufferEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_MI_BATCH_BUFFER_START_ClearCommandBufferEnable_start 11 +#define GEN7_MI_BATCH_BUFFER_START_ClearCommandBufferEnable_start 11 +#define GEN6_MI_BATCH_BUFFER_START_ClearCommandBufferEnable_start 11 + +static inline uint32_t ATTRIBUTE_PURE +MI_BATCH_BUFFER_START_ClearCommandBufferEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 11; + } else { + return 11; + } + case 6: return 11; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_BATCH_BUFFER_START::Command Type */ + + +#define GEN11_MI_BATCH_BUFFER_START_CommandType_bits 3 +#define GEN10_MI_BATCH_BUFFER_START_CommandType_bits 3 +#define GEN9_MI_BATCH_BUFFER_START_CommandType_bits 3 +#define GEN8_MI_BATCH_BUFFER_START_CommandType_bits 3 +#define GEN75_MI_BATCH_BUFFER_START_CommandType_bits 3 +#define GEN7_MI_BATCH_BUFFER_START_CommandType_bits 3 +#define GEN6_MI_BATCH_BUFFER_START_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_BATCH_BUFFER_START_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_BATCH_BUFFER_START_CommandType_start 29 +#define GEN10_MI_BATCH_BUFFER_START_CommandType_start 29 +#define GEN9_MI_BATCH_BUFFER_START_CommandType_start 29 +#define GEN8_MI_BATCH_BUFFER_START_CommandType_start 29 +#define GEN75_MI_BATCH_BUFFER_START_CommandType_start 29 +#define GEN7_MI_BATCH_BUFFER_START_CommandType_start 29 +#define GEN6_MI_BATCH_BUFFER_START_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_BATCH_BUFFER_START_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_BATCH_BUFFER_START::DWord Length */ + + +#define GEN11_MI_BATCH_BUFFER_START_DWordLength_bits 8 +#define GEN10_MI_BATCH_BUFFER_START_DWordLength_bits 8 +#define GEN9_MI_BATCH_BUFFER_START_DWordLength_bits 8 +#define GEN8_MI_BATCH_BUFFER_START_DWordLength_bits 8 +#define GEN75_MI_BATCH_BUFFER_START_DWordLength_bits 8 +#define GEN7_MI_BATCH_BUFFER_START_DWordLength_bits 8 +#define GEN6_MI_BATCH_BUFFER_START_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MI_BATCH_BUFFER_START_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_BATCH_BUFFER_START_DWordLength_start 0 +#define GEN10_MI_BATCH_BUFFER_START_DWordLength_start 0 +#define GEN9_MI_BATCH_BUFFER_START_DWordLength_start 0 +#define GEN8_MI_BATCH_BUFFER_START_DWordLength_start 0 +#define GEN75_MI_BATCH_BUFFER_START_DWordLength_start 0 +#define GEN7_MI_BATCH_BUFFER_START_DWordLength_start 0 +#define GEN6_MI_BATCH_BUFFER_START_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_BATCH_BUFFER_START_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_BATCH_BUFFER_START::MI Command Opcode */ + + +#define GEN11_MI_BATCH_BUFFER_START_MICommandOpcode_bits 6 +#define GEN10_MI_BATCH_BUFFER_START_MICommandOpcode_bits 6 +#define GEN9_MI_BATCH_BUFFER_START_MICommandOpcode_bits 6 +#define GEN8_MI_BATCH_BUFFER_START_MICommandOpcode_bits 6 +#define GEN75_MI_BATCH_BUFFER_START_MICommandOpcode_bits 6 +#define GEN7_MI_BATCH_BUFFER_START_MICommandOpcode_bits 6 +#define GEN6_MI_BATCH_BUFFER_START_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_BATCH_BUFFER_START_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 6; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_BATCH_BUFFER_START_MICommandOpcode_start 23 +#define GEN10_MI_BATCH_BUFFER_START_MICommandOpcode_start 23 +#define GEN9_MI_BATCH_BUFFER_START_MICommandOpcode_start 23 +#define GEN8_MI_BATCH_BUFFER_START_MICommandOpcode_start 23 +#define GEN75_MI_BATCH_BUFFER_START_MICommandOpcode_start 23 +#define GEN7_MI_BATCH_BUFFER_START_MICommandOpcode_start 23 +#define GEN6_MI_BATCH_BUFFER_START_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_BATCH_BUFFER_START_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 23; + } else { + return 23; + } + case 6: return 23; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_BATCH_BUFFER_START::Non-Privileged */ + + +#define GEN75_MI_BATCH_BUFFER_START_NonPrivileged_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_BATCH_BUFFER_START_NonPrivileged_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_MI_BATCH_BUFFER_START_NonPrivileged_start 13 + +static inline uint32_t ATTRIBUTE_PURE +MI_BATCH_BUFFER_START_NonPrivileged_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 13; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_BATCH_BUFFER_START::Predication Enable */ + + +#define GEN11_MI_BATCH_BUFFER_START_PredicationEnable_bits 1 +#define GEN10_MI_BATCH_BUFFER_START_PredicationEnable_bits 1 +#define GEN9_MI_BATCH_BUFFER_START_PredicationEnable_bits 1 +#define GEN8_MI_BATCH_BUFFER_START_PredicationEnable_bits 1 +#define GEN75_MI_BATCH_BUFFER_START_PredicationEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_BATCH_BUFFER_START_PredicationEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_BATCH_BUFFER_START_PredicationEnable_start 15 +#define GEN10_MI_BATCH_BUFFER_START_PredicationEnable_start 15 +#define GEN9_MI_BATCH_BUFFER_START_PredicationEnable_start 15 +#define GEN8_MI_BATCH_BUFFER_START_PredicationEnable_start 15 +#define GEN75_MI_BATCH_BUFFER_START_PredicationEnable_start 15 + +static inline uint32_t ATTRIBUTE_PURE +MI_BATCH_BUFFER_START_PredicationEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 15; + case 10: return 15; + case 9: return 15; + case 8: return 15; + case 7: + if (devinfo->is_haswell) { + return 15; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_BATCH_BUFFER_START::Resource Streamer Enable */ + + +#define GEN11_MI_BATCH_BUFFER_START_ResourceStreamerEnable_bits 1 +#define GEN10_MI_BATCH_BUFFER_START_ResourceStreamerEnable_bits 1 +#define GEN9_MI_BATCH_BUFFER_START_ResourceStreamerEnable_bits 1 +#define GEN8_MI_BATCH_BUFFER_START_ResourceStreamerEnable_bits 1 +#define GEN75_MI_BATCH_BUFFER_START_ResourceStreamerEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_BATCH_BUFFER_START_ResourceStreamerEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_BATCH_BUFFER_START_ResourceStreamerEnable_start 10 +#define GEN10_MI_BATCH_BUFFER_START_ResourceStreamerEnable_start 10 +#define GEN9_MI_BATCH_BUFFER_START_ResourceStreamerEnable_start 10 +#define GEN8_MI_BATCH_BUFFER_START_ResourceStreamerEnable_start 10 +#define GEN75_MI_BATCH_BUFFER_START_ResourceStreamerEnable_start 10 + +static inline uint32_t ATTRIBUTE_PURE +MI_BATCH_BUFFER_START_ResourceStreamerEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 10; + case 10: return 10; + case 9: return 10; + case 8: return 10; + case 7: + if (devinfo->is_haswell) { + return 10; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_BATCH_BUFFER_START::Second Level Batch Buffer */ + + +#define GEN11_MI_BATCH_BUFFER_START_SecondLevelBatchBuffer_bits 1 +#define GEN10_MI_BATCH_BUFFER_START_SecondLevelBatchBuffer_bits 1 +#define GEN9_MI_BATCH_BUFFER_START_SecondLevelBatchBuffer_bits 1 +#define GEN8_MI_BATCH_BUFFER_START_SecondLevelBatchBuffer_bits 1 +#define GEN75_MI_BATCH_BUFFER_START_SecondLevelBatchBuffer_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_BATCH_BUFFER_START_SecondLevelBatchBuffer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_BATCH_BUFFER_START_SecondLevelBatchBuffer_start 22 +#define GEN10_MI_BATCH_BUFFER_START_SecondLevelBatchBuffer_start 22 +#define GEN9_MI_BATCH_BUFFER_START_SecondLevelBatchBuffer_start 22 +#define GEN8_MI_BATCH_BUFFER_START_SecondLevelBatchBuffer_start 22 +#define GEN75_MI_BATCH_BUFFER_START_SecondLevelBatchBuffer_start 22 + +static inline uint32_t ATTRIBUTE_PURE +MI_BATCH_BUFFER_START_SecondLevelBatchBuffer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 22; + case 10: return 22; + case 9: return 22; + case 8: return 22; + case 7: + if (devinfo->is_haswell) { + return 22; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_CLFLUSH */ + + + + + +/* MI_CLFLUSH::Command Type */ + + +#define GEN11_MI_CLFLUSH_CommandType_bits 3 +#define GEN10_MI_CLFLUSH_CommandType_bits 3 +#define GEN9_MI_CLFLUSH_CommandType_bits 3 +#define GEN8_MI_CLFLUSH_CommandType_bits 3 +#define GEN75_MI_CLFLUSH_CommandType_bits 3 +#define GEN7_MI_CLFLUSH_CommandType_bits 3 +#define GEN6_MI_CLFLUSH_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_CLFLUSH_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_CLFLUSH_CommandType_start 29 +#define GEN10_MI_CLFLUSH_CommandType_start 29 +#define GEN9_MI_CLFLUSH_CommandType_start 29 +#define GEN8_MI_CLFLUSH_CommandType_start 29 +#define GEN75_MI_CLFLUSH_CommandType_start 29 +#define GEN7_MI_CLFLUSH_CommandType_start 29 +#define GEN6_MI_CLFLUSH_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_CLFLUSH_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_CLFLUSH::DW Representing a Half Cache Line */ + + +#define GEN11_MI_CLFLUSH_DWRepresentingaHalfCacheLine_bits 32 +#define GEN10_MI_CLFLUSH_DWRepresentingaHalfCacheLine_bits 32 +#define GEN9_MI_CLFLUSH_DWRepresentingaHalfCacheLine_bits 32 +#define GEN8_MI_CLFLUSH_DWRepresentingaHalfCacheLine_bits 32 +#define GEN75_MI_CLFLUSH_DWRepresentingaHalfCacheLine_bits 32 +#define GEN7_MI_CLFLUSH_DWRepresentingaHalfCacheLine_bits 32 +#define GEN6_MI_CLFLUSH_DWRepresentingaHalfCacheLine_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +MI_CLFLUSH_DWRepresentingaHalfCacheLine_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_CLFLUSH_DWRepresentingaHalfCacheLine_start 0 +#define GEN10_MI_CLFLUSH_DWRepresentingaHalfCacheLine_start 0 +#define GEN9_MI_CLFLUSH_DWRepresentingaHalfCacheLine_start 0 +#define GEN8_MI_CLFLUSH_DWRepresentingaHalfCacheLine_start 0 +#define GEN75_MI_CLFLUSH_DWRepresentingaHalfCacheLine_start 0 +#define GEN7_MI_CLFLUSH_DWRepresentingaHalfCacheLine_start 0 +#define GEN6_MI_CLFLUSH_DWRepresentingaHalfCacheLine_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_CLFLUSH_DWRepresentingaHalfCacheLine_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_CLFLUSH::DWord Length */ + + +#define GEN11_MI_CLFLUSH_DWordLength_bits 10 +#define GEN10_MI_CLFLUSH_DWordLength_bits 10 +#define GEN9_MI_CLFLUSH_DWordLength_bits 10 +#define GEN8_MI_CLFLUSH_DWordLength_bits 10 +#define GEN75_MI_CLFLUSH_DWordLength_bits 10 +#define GEN7_MI_CLFLUSH_DWordLength_bits 10 +#define GEN6_MI_CLFLUSH_DWordLength_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_CLFLUSH_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 10; + case 10: return 10; + case 9: return 10; + case 8: return 10; + case 7: + if (devinfo->is_haswell) { + return 10; + } else { + return 10; + } + case 6: return 6; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_CLFLUSH_DWordLength_start 0 +#define GEN10_MI_CLFLUSH_DWordLength_start 0 +#define GEN9_MI_CLFLUSH_DWordLength_start 0 +#define GEN8_MI_CLFLUSH_DWordLength_start 0 +#define GEN75_MI_CLFLUSH_DWordLength_start 0 +#define GEN7_MI_CLFLUSH_DWordLength_start 0 +#define GEN6_MI_CLFLUSH_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_CLFLUSH_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_CLFLUSH::MI Command Opcode */ + + +#define GEN11_MI_CLFLUSH_MICommandOpcode_bits 6 +#define GEN10_MI_CLFLUSH_MICommandOpcode_bits 6 +#define GEN9_MI_CLFLUSH_MICommandOpcode_bits 6 +#define GEN8_MI_CLFLUSH_MICommandOpcode_bits 6 +#define GEN75_MI_CLFLUSH_MICommandOpcode_bits 6 +#define GEN7_MI_CLFLUSH_MICommandOpcode_bits 6 +#define GEN6_MI_CLFLUSH_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_CLFLUSH_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 6; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_CLFLUSH_MICommandOpcode_start 23 +#define GEN10_MI_CLFLUSH_MICommandOpcode_start 23 +#define GEN9_MI_CLFLUSH_MICommandOpcode_start 23 +#define GEN8_MI_CLFLUSH_MICommandOpcode_start 23 +#define GEN75_MI_CLFLUSH_MICommandOpcode_start 23 +#define GEN7_MI_CLFLUSH_MICommandOpcode_start 23 +#define GEN6_MI_CLFLUSH_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_CLFLUSH_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 23; + } else { + return 23; + } + case 6: return 23; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_CLFLUSH::Page Base Address */ + + +#define GEN11_MI_CLFLUSH_PageBaseAddress_bits 36 +#define GEN10_MI_CLFLUSH_PageBaseAddress_bits 36 +#define GEN9_MI_CLFLUSH_PageBaseAddress_bits 36 +#define GEN8_MI_CLFLUSH_PageBaseAddress_bits 36 +#define GEN75_MI_CLFLUSH_PageBaseAddress_bits 20 +#define GEN7_MI_CLFLUSH_PageBaseAddress_bits 20 +#define GEN6_MI_CLFLUSH_PageBaseAddress_bits 20 + +static inline uint32_t ATTRIBUTE_PURE +MI_CLFLUSH_PageBaseAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 36; + case 10: return 36; + case 9: return 36; + case 8: return 36; + case 7: + if (devinfo->is_haswell) { + return 20; + } else { + return 20; + } + case 6: return 20; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_CLFLUSH_PageBaseAddress_start 44 +#define GEN10_MI_CLFLUSH_PageBaseAddress_start 44 +#define GEN9_MI_CLFLUSH_PageBaseAddress_start 44 +#define GEN8_MI_CLFLUSH_PageBaseAddress_start 44 +#define GEN75_MI_CLFLUSH_PageBaseAddress_start 44 +#define GEN7_MI_CLFLUSH_PageBaseAddress_start 44 +#define GEN6_MI_CLFLUSH_PageBaseAddress_start 44 + +static inline uint32_t ATTRIBUTE_PURE +MI_CLFLUSH_PageBaseAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 44; + case 10: return 44; + case 9: return 44; + case 8: return 44; + case 7: + if (devinfo->is_haswell) { + return 44; + } else { + return 44; + } + case 6: return 44; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_CLFLUSH::Page Base Address High */ + + +#define GEN75_MI_CLFLUSH_PageBaseAddressHigh_bits 16 +#define GEN7_MI_CLFLUSH_PageBaseAddressHigh_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +MI_CLFLUSH_PageBaseAddressHigh_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_MI_CLFLUSH_PageBaseAddressHigh_start 64 +#define GEN7_MI_CLFLUSH_PageBaseAddressHigh_start 64 + +static inline uint32_t ATTRIBUTE_PURE +MI_CLFLUSH_PageBaseAddressHigh_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_CLFLUSH::Starting Cacheline Offset */ + + +#define GEN11_MI_CLFLUSH_StartingCachelineOffset_bits 6 +#define GEN10_MI_CLFLUSH_StartingCachelineOffset_bits 6 +#define GEN9_MI_CLFLUSH_StartingCachelineOffset_bits 6 +#define GEN8_MI_CLFLUSH_StartingCachelineOffset_bits 6 +#define GEN75_MI_CLFLUSH_StartingCachelineOffset_bits 6 +#define GEN7_MI_CLFLUSH_StartingCachelineOffset_bits 6 +#define GEN6_MI_CLFLUSH_StartingCachelineOffset_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_CLFLUSH_StartingCachelineOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 6; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_CLFLUSH_StartingCachelineOffset_start 38 +#define GEN10_MI_CLFLUSH_StartingCachelineOffset_start 38 +#define GEN9_MI_CLFLUSH_StartingCachelineOffset_start 38 +#define GEN8_MI_CLFLUSH_StartingCachelineOffset_start 38 +#define GEN75_MI_CLFLUSH_StartingCachelineOffset_start 38 +#define GEN7_MI_CLFLUSH_StartingCachelineOffset_start 38 +#define GEN6_MI_CLFLUSH_StartingCachelineOffset_start 38 + +static inline uint32_t ATTRIBUTE_PURE +MI_CLFLUSH_StartingCachelineOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 38; + case 10: return 38; + case 9: return 38; + case 8: return 38; + case 7: + if (devinfo->is_haswell) { + return 38; + } else { + return 38; + } + case 6: return 38; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_CLFLUSH::Use Global GTT */ + + +#define GEN11_MI_CLFLUSH_UseGlobalGTT_bits 1 +#define GEN10_MI_CLFLUSH_UseGlobalGTT_bits 1 +#define GEN9_MI_CLFLUSH_UseGlobalGTT_bits 1 +#define GEN8_MI_CLFLUSH_UseGlobalGTT_bits 1 +#define GEN75_MI_CLFLUSH_UseGlobalGTT_bits 1 +#define GEN7_MI_CLFLUSH_UseGlobalGTT_bits 1 +#define GEN6_MI_CLFLUSH_UseGlobalGTT_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_CLFLUSH_UseGlobalGTT_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_CLFLUSH_UseGlobalGTT_start 22 +#define GEN10_MI_CLFLUSH_UseGlobalGTT_start 22 +#define GEN9_MI_CLFLUSH_UseGlobalGTT_start 22 +#define GEN8_MI_CLFLUSH_UseGlobalGTT_start 22 +#define GEN75_MI_CLFLUSH_UseGlobalGTT_start 22 +#define GEN7_MI_CLFLUSH_UseGlobalGTT_start 22 +#define GEN6_MI_CLFLUSH_UseGlobalGTT_start 22 + +static inline uint32_t ATTRIBUTE_PURE +MI_CLFLUSH_UseGlobalGTT_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 22; + case 10: return 22; + case 9: return 22; + case 8: return 22; + case 7: + if (devinfo->is_haswell) { + return 22; + } else { + return 22; + } + case 6: return 22; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_CONDITIONAL_BATCH_BUFFER_END */ + + +#define GEN11_MI_CONDITIONAL_BATCH_BUFFER_END_length 4 +#define GEN10_MI_CONDITIONAL_BATCH_BUFFER_END_length 4 +#define GEN9_MI_CONDITIONAL_BATCH_BUFFER_END_length 4 +#define GEN8_MI_CONDITIONAL_BATCH_BUFFER_END_length 3 +#define GEN75_MI_CONDITIONAL_BATCH_BUFFER_END_length 2 +#define GEN7_MI_CONDITIONAL_BATCH_BUFFER_END_length 2 +#define GEN6_MI_CONDITIONAL_BATCH_BUFFER_END_length 2 + +static inline uint32_t ATTRIBUTE_PURE +MI_CONDITIONAL_BATCH_BUFFER_END_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_CONDITIONAL_BATCH_BUFFER_END::Command Type */ + + +#define GEN11_MI_CONDITIONAL_BATCH_BUFFER_END_CommandType_bits 3 +#define GEN10_MI_CONDITIONAL_BATCH_BUFFER_END_CommandType_bits 3 +#define GEN9_MI_CONDITIONAL_BATCH_BUFFER_END_CommandType_bits 3 +#define GEN8_MI_CONDITIONAL_BATCH_BUFFER_END_CommandType_bits 3 +#define GEN75_MI_CONDITIONAL_BATCH_BUFFER_END_CommandType_bits 3 +#define GEN7_MI_CONDITIONAL_BATCH_BUFFER_END_CommandType_bits 3 +#define GEN6_MI_CONDITIONAL_BATCH_BUFFER_END_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_CONDITIONAL_BATCH_BUFFER_END_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_CONDITIONAL_BATCH_BUFFER_END_CommandType_start 29 +#define GEN10_MI_CONDITIONAL_BATCH_BUFFER_END_CommandType_start 29 +#define GEN9_MI_CONDITIONAL_BATCH_BUFFER_END_CommandType_start 29 +#define GEN8_MI_CONDITIONAL_BATCH_BUFFER_END_CommandType_start 29 +#define GEN75_MI_CONDITIONAL_BATCH_BUFFER_END_CommandType_start 29 +#define GEN7_MI_CONDITIONAL_BATCH_BUFFER_END_CommandType_start 29 +#define GEN6_MI_CONDITIONAL_BATCH_BUFFER_END_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_CONDITIONAL_BATCH_BUFFER_END_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_CONDITIONAL_BATCH_BUFFER_END::Compare Address */ + + +#define GEN11_MI_CONDITIONAL_BATCH_BUFFER_END_CompareAddress_bits 61 +#define GEN10_MI_CONDITIONAL_BATCH_BUFFER_END_CompareAddress_bits 61 +#define GEN9_MI_CONDITIONAL_BATCH_BUFFER_END_CompareAddress_bits 61 +#define GEN8_MI_CONDITIONAL_BATCH_BUFFER_END_CompareAddress_bits 45 +#define GEN75_MI_CONDITIONAL_BATCH_BUFFER_END_CompareAddress_bits 29 +#define GEN7_MI_CONDITIONAL_BATCH_BUFFER_END_CompareAddress_bits 29 +#define GEN6_MI_CONDITIONAL_BATCH_BUFFER_END_CompareAddress_bits 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_CONDITIONAL_BATCH_BUFFER_END_CompareAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 61; + case 10: return 61; + case 9: return 61; + case 8: return 45; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_CONDITIONAL_BATCH_BUFFER_END_CompareAddress_start 67 +#define GEN10_MI_CONDITIONAL_BATCH_BUFFER_END_CompareAddress_start 67 +#define GEN9_MI_CONDITIONAL_BATCH_BUFFER_END_CompareAddress_start 67 +#define GEN8_MI_CONDITIONAL_BATCH_BUFFER_END_CompareAddress_start 67 +#define GEN75_MI_CONDITIONAL_BATCH_BUFFER_END_CompareAddress_start 67 +#define GEN7_MI_CONDITIONAL_BATCH_BUFFER_END_CompareAddress_start 67 +#define GEN6_MI_CONDITIONAL_BATCH_BUFFER_END_CompareAddress_start 67 + +static inline uint32_t ATTRIBUTE_PURE +MI_CONDITIONAL_BATCH_BUFFER_END_CompareAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 67; + case 10: return 67; + case 9: return 67; + case 8: return 67; + case 7: + if (devinfo->is_haswell) { + return 67; + } else { + return 67; + } + case 6: return 67; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_CONDITIONAL_BATCH_BUFFER_END::Compare Data Dword */ + + +#define GEN11_MI_CONDITIONAL_BATCH_BUFFER_END_CompareDataDword_bits 32 +#define GEN10_MI_CONDITIONAL_BATCH_BUFFER_END_CompareDataDword_bits 32 +#define GEN9_MI_CONDITIONAL_BATCH_BUFFER_END_CompareDataDword_bits 32 +#define GEN8_MI_CONDITIONAL_BATCH_BUFFER_END_CompareDataDword_bits 32 +#define GEN75_MI_CONDITIONAL_BATCH_BUFFER_END_CompareDataDword_bits 32 +#define GEN7_MI_CONDITIONAL_BATCH_BUFFER_END_CompareDataDword_bits 32 +#define GEN6_MI_CONDITIONAL_BATCH_BUFFER_END_CompareDataDword_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +MI_CONDITIONAL_BATCH_BUFFER_END_CompareDataDword_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_CONDITIONAL_BATCH_BUFFER_END_CompareDataDword_start 32 +#define GEN10_MI_CONDITIONAL_BATCH_BUFFER_END_CompareDataDword_start 32 +#define GEN9_MI_CONDITIONAL_BATCH_BUFFER_END_CompareDataDword_start 32 +#define GEN8_MI_CONDITIONAL_BATCH_BUFFER_END_CompareDataDword_start 32 +#define GEN75_MI_CONDITIONAL_BATCH_BUFFER_END_CompareDataDword_start 32 +#define GEN7_MI_CONDITIONAL_BATCH_BUFFER_END_CompareDataDword_start 32 +#define GEN6_MI_CONDITIONAL_BATCH_BUFFER_END_CompareDataDword_start 32 + +static inline uint32_t ATTRIBUTE_PURE +MI_CONDITIONAL_BATCH_BUFFER_END_CompareDataDword_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_CONDITIONAL_BATCH_BUFFER_END::Compare Mask Mode */ + + +#define GEN11_MI_CONDITIONAL_BATCH_BUFFER_END_CompareMaskMode_bits 1 +#define GEN10_MI_CONDITIONAL_BATCH_BUFFER_END_CompareMaskMode_bits 1 +#define GEN9_MI_CONDITIONAL_BATCH_BUFFER_END_CompareMaskMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_CONDITIONAL_BATCH_BUFFER_END_CompareMaskMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_CONDITIONAL_BATCH_BUFFER_END_CompareMaskMode_start 19 +#define GEN10_MI_CONDITIONAL_BATCH_BUFFER_END_CompareMaskMode_start 19 +#define GEN9_MI_CONDITIONAL_BATCH_BUFFER_END_CompareMaskMode_start 19 + +static inline uint32_t ATTRIBUTE_PURE +MI_CONDITIONAL_BATCH_BUFFER_END_CompareMaskMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 19; + case 10: return 19; + case 9: return 19; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_CONDITIONAL_BATCH_BUFFER_END::Compare Semaphore */ + + +#define GEN11_MI_CONDITIONAL_BATCH_BUFFER_END_CompareSemaphore_bits 1 +#define GEN10_MI_CONDITIONAL_BATCH_BUFFER_END_CompareSemaphore_bits 1 +#define GEN9_MI_CONDITIONAL_BATCH_BUFFER_END_CompareSemaphore_bits 1 +#define GEN8_MI_CONDITIONAL_BATCH_BUFFER_END_CompareSemaphore_bits 1 +#define GEN75_MI_CONDITIONAL_BATCH_BUFFER_END_CompareSemaphore_bits 1 +#define GEN7_MI_CONDITIONAL_BATCH_BUFFER_END_CompareSemaphore_bits 1 +#define GEN6_MI_CONDITIONAL_BATCH_BUFFER_END_CompareSemaphore_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_CONDITIONAL_BATCH_BUFFER_END_CompareSemaphore_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_CONDITIONAL_BATCH_BUFFER_END_CompareSemaphore_start 21 +#define GEN10_MI_CONDITIONAL_BATCH_BUFFER_END_CompareSemaphore_start 21 +#define GEN9_MI_CONDITIONAL_BATCH_BUFFER_END_CompareSemaphore_start 21 +#define GEN8_MI_CONDITIONAL_BATCH_BUFFER_END_CompareSemaphore_start 21 +#define GEN75_MI_CONDITIONAL_BATCH_BUFFER_END_CompareSemaphore_start 21 +#define GEN7_MI_CONDITIONAL_BATCH_BUFFER_END_CompareSemaphore_start 21 +#define GEN6_MI_CONDITIONAL_BATCH_BUFFER_END_CompareSemaphore_start 21 + +static inline uint32_t ATTRIBUTE_PURE +MI_CONDITIONAL_BATCH_BUFFER_END_CompareSemaphore_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 21; + case 10: return 21; + case 9: return 21; + case 8: return 21; + case 7: + if (devinfo->is_haswell) { + return 21; + } else { + return 21; + } + case 6: return 21; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_CONDITIONAL_BATCH_BUFFER_END::DWord Length */ + + +#define GEN11_MI_CONDITIONAL_BATCH_BUFFER_END_DWordLength_bits 8 +#define GEN10_MI_CONDITIONAL_BATCH_BUFFER_END_DWordLength_bits 8 +#define GEN9_MI_CONDITIONAL_BATCH_BUFFER_END_DWordLength_bits 8 +#define GEN8_MI_CONDITIONAL_BATCH_BUFFER_END_DWordLength_bits 8 +#define GEN75_MI_CONDITIONAL_BATCH_BUFFER_END_DWordLength_bits 8 +#define GEN7_MI_CONDITIONAL_BATCH_BUFFER_END_DWordLength_bits 8 +#define GEN6_MI_CONDITIONAL_BATCH_BUFFER_END_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MI_CONDITIONAL_BATCH_BUFFER_END_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_CONDITIONAL_BATCH_BUFFER_END_DWordLength_start 0 +#define GEN10_MI_CONDITIONAL_BATCH_BUFFER_END_DWordLength_start 0 +#define GEN9_MI_CONDITIONAL_BATCH_BUFFER_END_DWordLength_start 0 +#define GEN8_MI_CONDITIONAL_BATCH_BUFFER_END_DWordLength_start 0 +#define GEN75_MI_CONDITIONAL_BATCH_BUFFER_END_DWordLength_start 0 +#define GEN7_MI_CONDITIONAL_BATCH_BUFFER_END_DWordLength_start 0 +#define GEN6_MI_CONDITIONAL_BATCH_BUFFER_END_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_CONDITIONAL_BATCH_BUFFER_END_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_CONDITIONAL_BATCH_BUFFER_END::MI Command Opcode */ + + +#define GEN11_MI_CONDITIONAL_BATCH_BUFFER_END_MICommandOpcode_bits 6 +#define GEN10_MI_CONDITIONAL_BATCH_BUFFER_END_MICommandOpcode_bits 6 +#define GEN9_MI_CONDITIONAL_BATCH_BUFFER_END_MICommandOpcode_bits 6 +#define GEN8_MI_CONDITIONAL_BATCH_BUFFER_END_MICommandOpcode_bits 6 +#define GEN75_MI_CONDITIONAL_BATCH_BUFFER_END_MICommandOpcode_bits 6 +#define GEN7_MI_CONDITIONAL_BATCH_BUFFER_END_MICommandOpcode_bits 6 +#define GEN6_MI_CONDITIONAL_BATCH_BUFFER_END_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_CONDITIONAL_BATCH_BUFFER_END_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 6; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_CONDITIONAL_BATCH_BUFFER_END_MICommandOpcode_start 23 +#define GEN10_MI_CONDITIONAL_BATCH_BUFFER_END_MICommandOpcode_start 23 +#define GEN9_MI_CONDITIONAL_BATCH_BUFFER_END_MICommandOpcode_start 23 +#define GEN8_MI_CONDITIONAL_BATCH_BUFFER_END_MICommandOpcode_start 23 +#define GEN75_MI_CONDITIONAL_BATCH_BUFFER_END_MICommandOpcode_start 23 +#define GEN7_MI_CONDITIONAL_BATCH_BUFFER_END_MICommandOpcode_start 23 +#define GEN6_MI_CONDITIONAL_BATCH_BUFFER_END_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_CONDITIONAL_BATCH_BUFFER_END_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 23; + } else { + return 23; + } + case 6: return 23; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_CONDITIONAL_BATCH_BUFFER_END::Use Global GTT */ + + +#define GEN11_MI_CONDITIONAL_BATCH_BUFFER_END_UseGlobalGTT_bits 1 +#define GEN10_MI_CONDITIONAL_BATCH_BUFFER_END_UseGlobalGTT_bits 1 +#define GEN9_MI_CONDITIONAL_BATCH_BUFFER_END_UseGlobalGTT_bits 1 +#define GEN8_MI_CONDITIONAL_BATCH_BUFFER_END_UseGlobalGTT_bits 1 +#define GEN75_MI_CONDITIONAL_BATCH_BUFFER_END_UseGlobalGTT_bits 1 +#define GEN7_MI_CONDITIONAL_BATCH_BUFFER_END_UseGlobalGTT_bits 1 +#define GEN6_MI_CONDITIONAL_BATCH_BUFFER_END_UseGlobalGTT_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_CONDITIONAL_BATCH_BUFFER_END_UseGlobalGTT_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_CONDITIONAL_BATCH_BUFFER_END_UseGlobalGTT_start 22 +#define GEN10_MI_CONDITIONAL_BATCH_BUFFER_END_UseGlobalGTT_start 22 +#define GEN9_MI_CONDITIONAL_BATCH_BUFFER_END_UseGlobalGTT_start 22 +#define GEN8_MI_CONDITIONAL_BATCH_BUFFER_END_UseGlobalGTT_start 22 +#define GEN75_MI_CONDITIONAL_BATCH_BUFFER_END_UseGlobalGTT_start 22 +#define GEN7_MI_CONDITIONAL_BATCH_BUFFER_END_UseGlobalGTT_start 22 +#define GEN6_MI_CONDITIONAL_BATCH_BUFFER_END_UseGlobalGTT_start 22 + +static inline uint32_t ATTRIBUTE_PURE +MI_CONDITIONAL_BATCH_BUFFER_END_UseGlobalGTT_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 22; + case 10: return 22; + case 9: return 22; + case 8: return 22; + case 7: + if (devinfo->is_haswell) { + return 22; + } else { + return 22; + } + case 6: return 22; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_COPY_MEM_MEM */ + + +#define GEN11_MI_COPY_MEM_MEM_length 5 +#define GEN10_MI_COPY_MEM_MEM_length 5 +#define GEN9_MI_COPY_MEM_MEM_length 5 +#define GEN8_MI_COPY_MEM_MEM_length 5 + +static inline uint32_t ATTRIBUTE_PURE +MI_COPY_MEM_MEM_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_COPY_MEM_MEM::Command Type */ + + +#define GEN11_MI_COPY_MEM_MEM_CommandType_bits 3 +#define GEN10_MI_COPY_MEM_MEM_CommandType_bits 3 +#define GEN9_MI_COPY_MEM_MEM_CommandType_bits 3 +#define GEN8_MI_COPY_MEM_MEM_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_COPY_MEM_MEM_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_COPY_MEM_MEM_CommandType_start 29 +#define GEN10_MI_COPY_MEM_MEM_CommandType_start 29 +#define GEN9_MI_COPY_MEM_MEM_CommandType_start 29 +#define GEN8_MI_COPY_MEM_MEM_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_COPY_MEM_MEM_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_COPY_MEM_MEM::DWord Length */ + + +#define GEN11_MI_COPY_MEM_MEM_DWordLength_bits 8 +#define GEN10_MI_COPY_MEM_MEM_DWordLength_bits 8 +#define GEN9_MI_COPY_MEM_MEM_DWordLength_bits 8 +#define GEN8_MI_COPY_MEM_MEM_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MI_COPY_MEM_MEM_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_COPY_MEM_MEM_DWordLength_start 0 +#define GEN10_MI_COPY_MEM_MEM_DWordLength_start 0 +#define GEN9_MI_COPY_MEM_MEM_DWordLength_start 0 +#define GEN8_MI_COPY_MEM_MEM_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_COPY_MEM_MEM_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_COPY_MEM_MEM::Destination Memory Address */ + + +#define GEN11_MI_COPY_MEM_MEM_DestinationMemoryAddress_bits 62 +#define GEN10_MI_COPY_MEM_MEM_DestinationMemoryAddress_bits 62 +#define GEN9_MI_COPY_MEM_MEM_DestinationMemoryAddress_bits 62 +#define GEN8_MI_COPY_MEM_MEM_DestinationMemoryAddress_bits 62 + +static inline uint32_t ATTRIBUTE_PURE +MI_COPY_MEM_MEM_DestinationMemoryAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 62; + case 10: return 62; + case 9: return 62; + case 8: return 62; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_COPY_MEM_MEM_DestinationMemoryAddress_start 34 +#define GEN10_MI_COPY_MEM_MEM_DestinationMemoryAddress_start 34 +#define GEN9_MI_COPY_MEM_MEM_DestinationMemoryAddress_start 34 +#define GEN8_MI_COPY_MEM_MEM_DestinationMemoryAddress_start 34 + +static inline uint32_t ATTRIBUTE_PURE +MI_COPY_MEM_MEM_DestinationMemoryAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 34; + case 10: return 34; + case 9: return 34; + case 8: return 34; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_COPY_MEM_MEM::MI Command Opcode */ + + +#define GEN11_MI_COPY_MEM_MEM_MICommandOpcode_bits 6 +#define GEN10_MI_COPY_MEM_MEM_MICommandOpcode_bits 6 +#define GEN9_MI_COPY_MEM_MEM_MICommandOpcode_bits 6 +#define GEN8_MI_COPY_MEM_MEM_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_COPY_MEM_MEM_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_COPY_MEM_MEM_MICommandOpcode_start 23 +#define GEN10_MI_COPY_MEM_MEM_MICommandOpcode_start 23 +#define GEN9_MI_COPY_MEM_MEM_MICommandOpcode_start 23 +#define GEN8_MI_COPY_MEM_MEM_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_COPY_MEM_MEM_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_COPY_MEM_MEM::Source Memory Address */ + + +#define GEN11_MI_COPY_MEM_MEM_SourceMemoryAddress_bits 62 +#define GEN10_MI_COPY_MEM_MEM_SourceMemoryAddress_bits 62 +#define GEN9_MI_COPY_MEM_MEM_SourceMemoryAddress_bits 62 +#define GEN8_MI_COPY_MEM_MEM_SourceMemoryAddress_bits 62 + +static inline uint32_t ATTRIBUTE_PURE +MI_COPY_MEM_MEM_SourceMemoryAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 62; + case 10: return 62; + case 9: return 62; + case 8: return 62; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_COPY_MEM_MEM_SourceMemoryAddress_start 98 +#define GEN10_MI_COPY_MEM_MEM_SourceMemoryAddress_start 98 +#define GEN9_MI_COPY_MEM_MEM_SourceMemoryAddress_start 98 +#define GEN8_MI_COPY_MEM_MEM_SourceMemoryAddress_start 98 + +static inline uint32_t ATTRIBUTE_PURE +MI_COPY_MEM_MEM_SourceMemoryAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 98; + case 10: return 98; + case 9: return 98; + case 8: return 98; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_COPY_MEM_MEM::Use Global GTT Destination */ + + +#define GEN11_MI_COPY_MEM_MEM_UseGlobalGTTDestination_bits 1 +#define GEN10_MI_COPY_MEM_MEM_UseGlobalGTTDestination_bits 1 +#define GEN9_MI_COPY_MEM_MEM_UseGlobalGTTDestination_bits 1 +#define GEN8_MI_COPY_MEM_MEM_UseGlobalGTTDestination_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_COPY_MEM_MEM_UseGlobalGTTDestination_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_COPY_MEM_MEM_UseGlobalGTTDestination_start 21 +#define GEN10_MI_COPY_MEM_MEM_UseGlobalGTTDestination_start 21 +#define GEN9_MI_COPY_MEM_MEM_UseGlobalGTTDestination_start 21 +#define GEN8_MI_COPY_MEM_MEM_UseGlobalGTTDestination_start 21 + +static inline uint32_t ATTRIBUTE_PURE +MI_COPY_MEM_MEM_UseGlobalGTTDestination_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 21; + case 10: return 21; + case 9: return 21; + case 8: return 21; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_COPY_MEM_MEM::Use Global GTT Source */ + + +#define GEN11_MI_COPY_MEM_MEM_UseGlobalGTTSource_bits 1 +#define GEN10_MI_COPY_MEM_MEM_UseGlobalGTTSource_bits 1 +#define GEN9_MI_COPY_MEM_MEM_UseGlobalGTTSource_bits 1 +#define GEN8_MI_COPY_MEM_MEM_UseGlobalGTTSource_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_COPY_MEM_MEM_UseGlobalGTTSource_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_COPY_MEM_MEM_UseGlobalGTTSource_start 22 +#define GEN10_MI_COPY_MEM_MEM_UseGlobalGTTSource_start 22 +#define GEN9_MI_COPY_MEM_MEM_UseGlobalGTTSource_start 22 +#define GEN8_MI_COPY_MEM_MEM_UseGlobalGTTSource_start 22 + +static inline uint32_t ATTRIBUTE_PURE +MI_COPY_MEM_MEM_UseGlobalGTTSource_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 22; + case 10: return 22; + case 9: return 22; + case 8: return 22; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_DISPLAY_FLIP */ + + +#define GEN11_MI_DISPLAY_FLIP_length 3 +#define GEN10_MI_DISPLAY_FLIP_length 3 +#define GEN9_MI_DISPLAY_FLIP_length 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_DISPLAY_FLIP_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_DISPLAY_FLIP::Async Flip Indicator */ + + +#define GEN11_MI_DISPLAY_FLIP_AsyncFlipIndicator_bits 1 +#define GEN10_MI_DISPLAY_FLIP_AsyncFlipIndicator_bits 1 +#define GEN9_MI_DISPLAY_FLIP_AsyncFlipIndicator_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_DISPLAY_FLIP_AsyncFlipIndicator_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_DISPLAY_FLIP_AsyncFlipIndicator_start 22 +#define GEN10_MI_DISPLAY_FLIP_AsyncFlipIndicator_start 22 +#define GEN9_MI_DISPLAY_FLIP_AsyncFlipIndicator_start 22 + +static inline uint32_t ATTRIBUTE_PURE +MI_DISPLAY_FLIP_AsyncFlipIndicator_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 22; + case 10: return 22; + case 9: return 22; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_DISPLAY_FLIP::Command Type */ + + +#define GEN11_MI_DISPLAY_FLIP_CommandType_bits 3 +#define GEN10_MI_DISPLAY_FLIP_CommandType_bits 3 +#define GEN9_MI_DISPLAY_FLIP_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_DISPLAY_FLIP_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_DISPLAY_FLIP_CommandType_start 29 +#define GEN10_MI_DISPLAY_FLIP_CommandType_start 29 +#define GEN9_MI_DISPLAY_FLIP_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_DISPLAY_FLIP_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_DISPLAY_FLIP::DWord Length */ + + +#define GEN11_MI_DISPLAY_FLIP_DWordLength_bits 8 +#define GEN10_MI_DISPLAY_FLIP_DWordLength_bits 8 +#define GEN9_MI_DISPLAY_FLIP_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MI_DISPLAY_FLIP_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_DISPLAY_FLIP_DWordLength_start 0 +#define GEN10_MI_DISPLAY_FLIP_DWordLength_start 0 +#define GEN9_MI_DISPLAY_FLIP_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_DISPLAY_FLIP_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_DISPLAY_FLIP::Display Buffer Base Address */ + + +#define GEN11_MI_DISPLAY_FLIP_DisplayBufferBaseAddress_bits 20 +#define GEN10_MI_DISPLAY_FLIP_DisplayBufferBaseAddress_bits 20 +#define GEN9_MI_DISPLAY_FLIP_DisplayBufferBaseAddress_bits 20 + +static inline uint32_t ATTRIBUTE_PURE +MI_DISPLAY_FLIP_DisplayBufferBaseAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 20; + case 10: return 20; + case 9: return 20; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_DISPLAY_FLIP_DisplayBufferBaseAddress_start 76 +#define GEN10_MI_DISPLAY_FLIP_DisplayBufferBaseAddress_start 76 +#define GEN9_MI_DISPLAY_FLIP_DisplayBufferBaseAddress_start 76 + +static inline uint32_t ATTRIBUTE_PURE +MI_DISPLAY_FLIP_DisplayBufferBaseAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 76; + case 10: return 76; + case 9: return 76; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_DISPLAY_FLIP::Display Buffer Pitch */ + + +#define GEN11_MI_DISPLAY_FLIP_DisplayBufferPitch_bits 10 +#define GEN10_MI_DISPLAY_FLIP_DisplayBufferPitch_bits 10 +#define GEN9_MI_DISPLAY_FLIP_DisplayBufferPitch_bits 10 + +static inline uint32_t ATTRIBUTE_PURE +MI_DISPLAY_FLIP_DisplayBufferPitch_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 10; + case 10: return 10; + case 9: return 10; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_DISPLAY_FLIP_DisplayBufferPitch_start 38 +#define GEN10_MI_DISPLAY_FLIP_DisplayBufferPitch_start 38 +#define GEN9_MI_DISPLAY_FLIP_DisplayBufferPitch_start 38 + +static inline uint32_t ATTRIBUTE_PURE +MI_DISPLAY_FLIP_DisplayBufferPitch_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 38; + case 10: return 38; + case 9: return 38; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_DISPLAY_FLIP::Display Plane Select */ + + +#define GEN11_MI_DISPLAY_FLIP_DisplayPlaneSelect_bits 6 +#define GEN10_MI_DISPLAY_FLIP_DisplayPlaneSelect_bits 5 +#define GEN9_MI_DISPLAY_FLIP_DisplayPlaneSelect_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +MI_DISPLAY_FLIP_DisplayPlaneSelect_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 5; + case 9: return 5; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_DISPLAY_FLIP_DisplayPlaneSelect_start 8 +#define GEN10_MI_DISPLAY_FLIP_DisplayPlaneSelect_start 8 +#define GEN9_MI_DISPLAY_FLIP_DisplayPlaneSelect_start 8 + +static inline uint32_t ATTRIBUTE_PURE +MI_DISPLAY_FLIP_DisplayPlaneSelect_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_DISPLAY_FLIP::Flip Type */ + + +#define GEN11_MI_DISPLAY_FLIP_FlipType_bits 2 +#define GEN10_MI_DISPLAY_FLIP_FlipType_bits 2 +#define GEN9_MI_DISPLAY_FLIP_FlipType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +MI_DISPLAY_FLIP_FlipType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_DISPLAY_FLIP_FlipType_start 64 +#define GEN10_MI_DISPLAY_FLIP_FlipType_start 64 +#define GEN9_MI_DISPLAY_FLIP_FlipType_start 64 + +static inline uint32_t ATTRIBUTE_PURE +MI_DISPLAY_FLIP_FlipType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_DISPLAY_FLIP::Left Eye Display Buffer Base Address */ + + +#define GEN11_MI_DISPLAY_FLIP_LeftEyeDisplayBufferBaseAddress_bits 20 +#define GEN10_MI_DISPLAY_FLIP_LeftEyeDisplayBufferBaseAddress_bits 20 +#define GEN9_MI_DISPLAY_FLIP_LeftEyeDisplayBufferBaseAddress_bits 20 + +static inline uint32_t ATTRIBUTE_PURE +MI_DISPLAY_FLIP_LeftEyeDisplayBufferBaseAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 20; + case 10: return 20; + case 9: return 20; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_DISPLAY_FLIP_LeftEyeDisplayBufferBaseAddress_start 108 +#define GEN10_MI_DISPLAY_FLIP_LeftEyeDisplayBufferBaseAddress_start 108 +#define GEN9_MI_DISPLAY_FLIP_LeftEyeDisplayBufferBaseAddress_start 108 + +static inline uint32_t ATTRIBUTE_PURE +MI_DISPLAY_FLIP_LeftEyeDisplayBufferBaseAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 108; + case 10: return 108; + case 9: return 108; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_DISPLAY_FLIP::MI Command Opcode */ + + +#define GEN11_MI_DISPLAY_FLIP_MICommandOpcode_bits 6 +#define GEN10_MI_DISPLAY_FLIP_MICommandOpcode_bits 6 +#define GEN9_MI_DISPLAY_FLIP_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_DISPLAY_FLIP_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_DISPLAY_FLIP_MICommandOpcode_start 23 +#define GEN10_MI_DISPLAY_FLIP_MICommandOpcode_start 23 +#define GEN9_MI_DISPLAY_FLIP_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_DISPLAY_FLIP_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_DISPLAY_FLIP::Stereoscopic 3D Mode */ + + +#define GEN11_MI_DISPLAY_FLIP_Stereoscopic3DMode_bits 1 +#define GEN10_MI_DISPLAY_FLIP_Stereoscopic3DMode_bits 1 +#define GEN9_MI_DISPLAY_FLIP_Stereoscopic3DMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_DISPLAY_FLIP_Stereoscopic3DMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_DISPLAY_FLIP_Stereoscopic3DMode_start 63 +#define GEN10_MI_DISPLAY_FLIP_Stereoscopic3DMode_start 63 +#define GEN9_MI_DISPLAY_FLIP_Stereoscopic3DMode_start 63 + +static inline uint32_t ATTRIBUTE_PURE +MI_DISPLAY_FLIP_Stereoscopic3DMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 63; + case 10: return 63; + case 9: return 63; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_DISPLAY_FLIP::Tile Parameter */ + + +#define GEN11_MI_DISPLAY_FLIP_TileParameter_bits 3 +#define GEN10_MI_DISPLAY_FLIP_TileParameter_bits 3 +#define GEN9_MI_DISPLAY_FLIP_TileParameter_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_DISPLAY_FLIP_TileParameter_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_DISPLAY_FLIP_TileParameter_start 32 +#define GEN10_MI_DISPLAY_FLIP_TileParameter_start 32 +#define GEN9_MI_DISPLAY_FLIP_TileParameter_start 32 + +static inline uint32_t ATTRIBUTE_PURE +MI_DISPLAY_FLIP_TileParameter_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_DISPLAY_FLIP::VRR Master Flip */ + + +#define GEN11_MI_DISPLAY_FLIP_VRRMasterFlip_bits 1 +#define GEN10_MI_DISPLAY_FLIP_VRRMasterFlip_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_DISPLAY_FLIP_VRRMasterFlip_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_DISPLAY_FLIP_VRRMasterFlip_start 75 +#define GEN10_MI_DISPLAY_FLIP_VRRMasterFlip_start 75 + +static inline uint32_t ATTRIBUTE_PURE +MI_DISPLAY_FLIP_VRRMasterFlip_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 75; + case 10: return 75; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_FLUSH */ + + +#define GEN75_MI_FLUSH_length 1 +#define GEN7_MI_FLUSH_length 1 +#define GEN6_MI_FLUSH_length 1 +#define GEN5_MI_FLUSH_length 1 +#define GEN45_MI_FLUSH_length 1 +#define GEN4_MI_FLUSH_length 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_FLUSH_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_FLUSH::Command Type */ + + +#define GEN75_MI_FLUSH_CommandType_bits 3 +#define GEN7_MI_FLUSH_CommandType_bits 3 +#define GEN6_MI_FLUSH_CommandType_bits 3 +#define GEN5_MI_FLUSH_CommandType_bits 3 +#define GEN45_MI_FLUSH_CommandType_bits 3 +#define GEN4_MI_FLUSH_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_FLUSH_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_MI_FLUSH_CommandType_start 29 +#define GEN7_MI_FLUSH_CommandType_start 29 +#define GEN6_MI_FLUSH_CommandType_start 29 +#define GEN5_MI_FLUSH_CommandType_start 29 +#define GEN45_MI_FLUSH_CommandType_start 29 +#define GEN4_MI_FLUSH_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_FLUSH_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 29; + case 4: + if (devinfo->is_g4x) { + return 29; + } else { + return 29; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_FLUSH::Generic Media State Clear */ + + +#define GEN75_MI_FLUSH_GenericMediaStateClear_bits 1 +#define GEN7_MI_FLUSH_GenericMediaStateClear_bits 1 +#define GEN6_MI_FLUSH_GenericMediaStateClear_bits 1 +#define GEN5_MI_FLUSH_GenericMediaStateClear_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_FLUSH_GenericMediaStateClear_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_MI_FLUSH_GenericMediaStateClear_start 4 +#define GEN7_MI_FLUSH_GenericMediaStateClear_start 4 +#define GEN6_MI_FLUSH_GenericMediaStateClear_start 4 +#define GEN5_MI_FLUSH_GenericMediaStateClear_start 4 + +static inline uint32_t ATTRIBUTE_PURE +MI_FLUSH_GenericMediaStateClear_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 4; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_FLUSH::Global Snapshot Count Reset */ + + +#define GEN75_MI_FLUSH_GlobalSnapshotCountReset_bits 1 +#define GEN7_MI_FLUSH_GlobalSnapshotCountReset_bits 1 +#define GEN6_MI_FLUSH_GlobalSnapshotCountReset_bits 1 +#define GEN5_MI_FLUSH_GlobalSnapshotCountReset_bits 1 +#define GEN45_MI_FLUSH_GlobalSnapshotCountReset_bits 1 +#define GEN4_MI_FLUSH_GlobalSnapshotCountReset_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_FLUSH_GlobalSnapshotCountReset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_MI_FLUSH_GlobalSnapshotCountReset_start 3 +#define GEN7_MI_FLUSH_GlobalSnapshotCountReset_start 3 +#define GEN6_MI_FLUSH_GlobalSnapshotCountReset_start 3 +#define GEN5_MI_FLUSH_GlobalSnapshotCountReset_start 3 +#define GEN45_MI_FLUSH_GlobalSnapshotCountReset_start 3 +#define GEN4_MI_FLUSH_GlobalSnapshotCountReset_start 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_FLUSH_GlobalSnapshotCountReset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_FLUSH::Indirect State Pointers Disable */ + + +#define GEN75_MI_FLUSH_IndirectStatePointersDisable_bits 1 +#define GEN7_MI_FLUSH_IndirectStatePointersDisable_bits 1 +#define GEN6_MI_FLUSH_IndirectStatePointersDisable_bits 1 +#define GEN5_MI_FLUSH_IndirectStatePointersDisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_FLUSH_IndirectStatePointersDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_MI_FLUSH_IndirectStatePointersDisable_start 5 +#define GEN7_MI_FLUSH_IndirectStatePointersDisable_start 5 +#define GEN6_MI_FLUSH_IndirectStatePointersDisable_start 5 +#define GEN5_MI_FLUSH_IndirectStatePointersDisable_start 5 + +static inline uint32_t ATTRIBUTE_PURE +MI_FLUSH_IndirectStatePointersDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 5; + } + case 6: return 5; + case 5: return 5; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_FLUSH::MI Command Opcode */ + + +#define GEN75_MI_FLUSH_MICommandOpcode_bits 6 +#define GEN7_MI_FLUSH_MICommandOpcode_bits 6 +#define GEN6_MI_FLUSH_MICommandOpcode_bits 6 +#define GEN5_MI_FLUSH_MICommandOpcode_bits 6 +#define GEN45_MI_FLUSH_MICommandOpcode_bits 6 +#define GEN4_MI_FLUSH_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_FLUSH_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 6; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_MI_FLUSH_MICommandOpcode_start 23 +#define GEN7_MI_FLUSH_MICommandOpcode_start 23 +#define GEN6_MI_FLUSH_MICommandOpcode_start 23 +#define GEN5_MI_FLUSH_MICommandOpcode_start 23 +#define GEN45_MI_FLUSH_MICommandOpcode_start 23 +#define GEN4_MI_FLUSH_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_FLUSH_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 23; + } else { + return 23; + } + case 6: return 23; + case 5: return 23; + case 4: + if (devinfo->is_g4x) { + return 23; + } else { + return 23; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_FLUSH::Protected Memory Enable */ + + +#define GEN5_MI_FLUSH_ProtectedMemoryEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_FLUSH_ProtectedMemoryEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_MI_FLUSH_ProtectedMemoryEnable_start 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_FLUSH_ProtectedMemoryEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_FLUSH::Render Cache Flush Inhibit */ + + +#define GEN75_MI_FLUSH_RenderCacheFlushInhibit_bits 1 +#define GEN7_MI_FLUSH_RenderCacheFlushInhibit_bits 1 +#define GEN6_MI_FLUSH_RenderCacheFlushInhibit_bits 1 +#define GEN5_MI_FLUSH_RenderCacheFlushInhibit_bits 1 +#define GEN45_MI_FLUSH_RenderCacheFlushInhibit_bits 1 +#define GEN4_MI_FLUSH_RenderCacheFlushInhibit_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_FLUSH_RenderCacheFlushInhibit_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_MI_FLUSH_RenderCacheFlushInhibit_start 2 +#define GEN7_MI_FLUSH_RenderCacheFlushInhibit_start 2 +#define GEN6_MI_FLUSH_RenderCacheFlushInhibit_start 2 +#define GEN5_MI_FLUSH_RenderCacheFlushInhibit_start 2 +#define GEN45_MI_FLUSH_RenderCacheFlushInhibit_start 2 +#define GEN4_MI_FLUSH_RenderCacheFlushInhibit_start 2 + +static inline uint32_t ATTRIBUTE_PURE +MI_FLUSH_RenderCacheFlushInhibit_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_FLUSH::State/Instruction Cache Invalidate */ + + +#define GEN75_MI_FLUSH_StateInstructionCacheInvalidate_bits 1 +#define GEN7_MI_FLUSH_StateInstructionCacheInvalidate_bits 1 +#define GEN6_MI_FLUSH_StateInstructionCacheInvalidate_bits 1 +#define GEN5_MI_FLUSH_StateInstructionCacheInvalidate_bits 1 +#define GEN45_MI_FLUSH_StateInstructionCacheInvalidate_bits 1 +#define GEN4_MI_FLUSH_StateInstructionCacheInvalidate_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_FLUSH_StateInstructionCacheInvalidate_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_MI_FLUSH_StateInstructionCacheInvalidate_start 1 +#define GEN7_MI_FLUSH_StateInstructionCacheInvalidate_start 1 +#define GEN6_MI_FLUSH_StateInstructionCacheInvalidate_start 1 +#define GEN5_MI_FLUSH_StateInstructionCacheInvalidate_start 1 +#define GEN45_MI_FLUSH_StateInstructionCacheInvalidate_start 1 +#define GEN4_MI_FLUSH_StateInstructionCacheInvalidate_start 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_FLUSH_StateInstructionCacheInvalidate_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_FORCE_WAKEUP */ + + +#define GEN11_MI_FORCE_WAKEUP_length 2 +#define GEN10_MI_FORCE_WAKEUP_length 2 +#define GEN9_MI_FORCE_WAKEUP_length 2 + +static inline uint32_t ATTRIBUTE_PURE +MI_FORCE_WAKEUP_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_FORCE_WAKEUP::Command Type */ + + +#define GEN11_MI_FORCE_WAKEUP_CommandType_bits 3 +#define GEN10_MI_FORCE_WAKEUP_CommandType_bits 3 +#define GEN9_MI_FORCE_WAKEUP_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_FORCE_WAKEUP_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_FORCE_WAKEUP_CommandType_start 29 +#define GEN10_MI_FORCE_WAKEUP_CommandType_start 29 +#define GEN9_MI_FORCE_WAKEUP_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_FORCE_WAKEUP_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_FORCE_WAKEUP::DWord Length */ + + +#define GEN11_MI_FORCE_WAKEUP_DWordLength_bits 8 +#define GEN10_MI_FORCE_WAKEUP_DWordLength_bits 8 +#define GEN9_MI_FORCE_WAKEUP_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MI_FORCE_WAKEUP_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_FORCE_WAKEUP_DWordLength_start 0 +#define GEN10_MI_FORCE_WAKEUP_DWordLength_start 0 +#define GEN9_MI_FORCE_WAKEUP_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_FORCE_WAKEUP_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_FORCE_WAKEUP::Force Media Awake */ + + +#define GEN10_MI_FORCE_WAKEUP_ForceMediaAwake_bits 1 +#define GEN9_MI_FORCE_WAKEUP_ForceMediaAwake_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_FORCE_WAKEUP_ForceMediaAwake_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MI_FORCE_WAKEUP_ForceMediaAwake_start 32 +#define GEN9_MI_FORCE_WAKEUP_ForceMediaAwake_start 32 + +static inline uint32_t ATTRIBUTE_PURE +MI_FORCE_WAKEUP_ForceMediaAwake_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 32; + case 9: return 32; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_FORCE_WAKEUP::Force Media-Slice0 Awake */ + + +#define GEN11_MI_FORCE_WAKEUP_ForceMediaSlice0Awake_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_FORCE_WAKEUP_ForceMediaSlice0Awake_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_FORCE_WAKEUP_ForceMediaSlice0Awake_start 32 + +static inline uint32_t ATTRIBUTE_PURE +MI_FORCE_WAKEUP_ForceMediaSlice0Awake_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_FORCE_WAKEUP::Force Media-Slice1 Awake */ + + +#define GEN11_MI_FORCE_WAKEUP_ForceMediaSlice1Awake_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_FORCE_WAKEUP_ForceMediaSlice1Awake_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_FORCE_WAKEUP_ForceMediaSlice1Awake_start 34 + +static inline uint32_t ATTRIBUTE_PURE +MI_FORCE_WAKEUP_ForceMediaSlice1Awake_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 34; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_FORCE_WAKEUP::Force Media-Slice2 Awake */ + + +#define GEN11_MI_FORCE_WAKEUP_ForceMediaSlice2Awake_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_FORCE_WAKEUP_ForceMediaSlice2Awake_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_FORCE_WAKEUP_ForceMediaSlice2Awake_start 35 + +static inline uint32_t ATTRIBUTE_PURE +MI_FORCE_WAKEUP_ForceMediaSlice2Awake_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 35; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_FORCE_WAKEUP::Force Media-Slice3 Awake */ + + +#define GEN11_MI_FORCE_WAKEUP_ForceMediaSlice3Awake_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_FORCE_WAKEUP_ForceMediaSlice3Awake_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_FORCE_WAKEUP_ForceMediaSlice3Awake_start 36 + +static inline uint32_t ATTRIBUTE_PURE +MI_FORCE_WAKEUP_ForceMediaSlice3Awake_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 36; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_FORCE_WAKEUP::Force Render Awake */ + + +#define GEN11_MI_FORCE_WAKEUP_ForceRenderAwake_bits 1 +#define GEN10_MI_FORCE_WAKEUP_ForceRenderAwake_bits 1 +#define GEN9_MI_FORCE_WAKEUP_ForceRenderAwake_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_FORCE_WAKEUP_ForceRenderAwake_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_FORCE_WAKEUP_ForceRenderAwake_start 33 +#define GEN10_MI_FORCE_WAKEUP_ForceRenderAwake_start 33 +#define GEN9_MI_FORCE_WAKEUP_ForceRenderAwake_start 33 + +static inline uint32_t ATTRIBUTE_PURE +MI_FORCE_WAKEUP_ForceRenderAwake_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 33; + case 10: return 33; + case 9: return 33; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_FORCE_WAKEUP::MI Command Opcode */ + + +#define GEN11_MI_FORCE_WAKEUP_MICommandOpcode_bits 6 +#define GEN10_MI_FORCE_WAKEUP_MICommandOpcode_bits 6 +#define GEN9_MI_FORCE_WAKEUP_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_FORCE_WAKEUP_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_FORCE_WAKEUP_MICommandOpcode_start 23 +#define GEN10_MI_FORCE_WAKEUP_MICommandOpcode_start 23 +#define GEN9_MI_FORCE_WAKEUP_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_FORCE_WAKEUP_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_FORCE_WAKEUP::Mask Bits */ + + +#define GEN11_MI_FORCE_WAKEUP_MaskBits_bits 16 +#define GEN10_MI_FORCE_WAKEUP_MaskBits_bits 16 +#define GEN9_MI_FORCE_WAKEUP_MaskBits_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +MI_FORCE_WAKEUP_MaskBits_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_FORCE_WAKEUP_MaskBits_start 48 +#define GEN10_MI_FORCE_WAKEUP_MaskBits_start 48 +#define GEN9_MI_FORCE_WAKEUP_MaskBits_start 48 + +static inline uint32_t ATTRIBUTE_PURE +MI_FORCE_WAKEUP_MaskBits_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_REGISTER_IMM */ + + +#define GEN11_MI_LOAD_REGISTER_IMM_length 3 +#define GEN10_MI_LOAD_REGISTER_IMM_length 3 +#define GEN9_MI_LOAD_REGISTER_IMM_length 3 +#define GEN8_MI_LOAD_REGISTER_IMM_length 3 +#define GEN75_MI_LOAD_REGISTER_IMM_length 3 +#define GEN7_MI_LOAD_REGISTER_IMM_length 3 +#define GEN6_MI_LOAD_REGISTER_IMM_length 3 +#define GEN5_MI_LOAD_REGISTER_IMM_length 3 +#define GEN45_MI_LOAD_REGISTER_IMM_length 3 +#define GEN4_MI_LOAD_REGISTER_IMM_length 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_IMM_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_REGISTER_IMM::Add CS MMIO Start Offset */ + + +#define GEN11_MI_LOAD_REGISTER_IMM_AddCSMMIOStartOffset_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_IMM_AddCSMMIOStartOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_LOAD_REGISTER_IMM_AddCSMMIOStartOffset_start 19 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_IMM_AddCSMMIOStartOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 19; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_REGISTER_IMM::Byte Write Disables */ + + +#define GEN11_MI_LOAD_REGISTER_IMM_ByteWriteDisables_bits 4 +#define GEN10_MI_LOAD_REGISTER_IMM_ByteWriteDisables_bits 4 +#define GEN9_MI_LOAD_REGISTER_IMM_ByteWriteDisables_bits 4 +#define GEN8_MI_LOAD_REGISTER_IMM_ByteWriteDisables_bits 4 +#define GEN75_MI_LOAD_REGISTER_IMM_ByteWriteDisables_bits 4 +#define GEN7_MI_LOAD_REGISTER_IMM_ByteWriteDisables_bits 4 +#define GEN6_MI_LOAD_REGISTER_IMM_ByteWriteDisables_bits 4 +#define GEN5_MI_LOAD_REGISTER_IMM_ByteWriteDisables_bits 4 +#define GEN45_MI_LOAD_REGISTER_IMM_ByteWriteDisables_bits 4 +#define GEN4_MI_LOAD_REGISTER_IMM_ByteWriteDisables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_IMM_ByteWriteDisables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 4; + case 4: + if (devinfo->is_g4x) { + return 4; + } else { + return 4; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_LOAD_REGISTER_IMM_ByteWriteDisables_start 8 +#define GEN10_MI_LOAD_REGISTER_IMM_ByteWriteDisables_start 8 +#define GEN9_MI_LOAD_REGISTER_IMM_ByteWriteDisables_start 8 +#define GEN8_MI_LOAD_REGISTER_IMM_ByteWriteDisables_start 8 +#define GEN75_MI_LOAD_REGISTER_IMM_ByteWriteDisables_start 8 +#define GEN7_MI_LOAD_REGISTER_IMM_ByteWriteDisables_start 8 +#define GEN6_MI_LOAD_REGISTER_IMM_ByteWriteDisables_start 8 +#define GEN5_MI_LOAD_REGISTER_IMM_ByteWriteDisables_start 8 +#define GEN45_MI_LOAD_REGISTER_IMM_ByteWriteDisables_start 8 +#define GEN4_MI_LOAD_REGISTER_IMM_ByteWriteDisables_start 8 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_IMM_ByteWriteDisables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_REGISTER_IMM::Command Type */ + + +#define GEN11_MI_LOAD_REGISTER_IMM_CommandType_bits 3 +#define GEN10_MI_LOAD_REGISTER_IMM_CommandType_bits 3 +#define GEN9_MI_LOAD_REGISTER_IMM_CommandType_bits 3 +#define GEN8_MI_LOAD_REGISTER_IMM_CommandType_bits 3 +#define GEN75_MI_LOAD_REGISTER_IMM_CommandType_bits 3 +#define GEN7_MI_LOAD_REGISTER_IMM_CommandType_bits 3 +#define GEN6_MI_LOAD_REGISTER_IMM_CommandType_bits 3 +#define GEN5_MI_LOAD_REGISTER_IMM_CommandType_bits 3 +#define GEN45_MI_LOAD_REGISTER_IMM_CommandType_bits 3 +#define GEN4_MI_LOAD_REGISTER_IMM_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_IMM_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_LOAD_REGISTER_IMM_CommandType_start 29 +#define GEN10_MI_LOAD_REGISTER_IMM_CommandType_start 29 +#define GEN9_MI_LOAD_REGISTER_IMM_CommandType_start 29 +#define GEN8_MI_LOAD_REGISTER_IMM_CommandType_start 29 +#define GEN75_MI_LOAD_REGISTER_IMM_CommandType_start 29 +#define GEN7_MI_LOAD_REGISTER_IMM_CommandType_start 29 +#define GEN6_MI_LOAD_REGISTER_IMM_CommandType_start 29 +#define GEN5_MI_LOAD_REGISTER_IMM_CommandType_start 29 +#define GEN45_MI_LOAD_REGISTER_IMM_CommandType_start 29 +#define GEN4_MI_LOAD_REGISTER_IMM_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_IMM_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 29; + case 4: + if (devinfo->is_g4x) { + return 29; + } else { + return 29; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_REGISTER_IMM::DWord Length */ + + +#define GEN11_MI_LOAD_REGISTER_IMM_DWordLength_bits 8 +#define GEN10_MI_LOAD_REGISTER_IMM_DWordLength_bits 8 +#define GEN9_MI_LOAD_REGISTER_IMM_DWordLength_bits 8 +#define GEN8_MI_LOAD_REGISTER_IMM_DWordLength_bits 8 +#define GEN75_MI_LOAD_REGISTER_IMM_DWordLength_bits 8 +#define GEN7_MI_LOAD_REGISTER_IMM_DWordLength_bits 8 +#define GEN6_MI_LOAD_REGISTER_IMM_DWordLength_bits 8 +#define GEN5_MI_LOAD_REGISTER_IMM_DWordLength_bits 6 +#define GEN45_MI_LOAD_REGISTER_IMM_DWordLength_bits 6 +#define GEN4_MI_LOAD_REGISTER_IMM_DWordLength_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_IMM_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_LOAD_REGISTER_IMM_DWordLength_start 0 +#define GEN10_MI_LOAD_REGISTER_IMM_DWordLength_start 0 +#define GEN9_MI_LOAD_REGISTER_IMM_DWordLength_start 0 +#define GEN8_MI_LOAD_REGISTER_IMM_DWordLength_start 0 +#define GEN75_MI_LOAD_REGISTER_IMM_DWordLength_start 0 +#define GEN7_MI_LOAD_REGISTER_IMM_DWordLength_start 0 +#define GEN6_MI_LOAD_REGISTER_IMM_DWordLength_start 0 +#define GEN5_MI_LOAD_REGISTER_IMM_DWordLength_start 0 +#define GEN45_MI_LOAD_REGISTER_IMM_DWordLength_start 0 +#define GEN4_MI_LOAD_REGISTER_IMM_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_IMM_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_REGISTER_IMM::Data DWord */ + + +#define GEN11_MI_LOAD_REGISTER_IMM_DataDWord_bits 32 +#define GEN10_MI_LOAD_REGISTER_IMM_DataDWord_bits 32 +#define GEN9_MI_LOAD_REGISTER_IMM_DataDWord_bits 32 +#define GEN8_MI_LOAD_REGISTER_IMM_DataDWord_bits 32 +#define GEN75_MI_LOAD_REGISTER_IMM_DataDWord_bits 32 +#define GEN7_MI_LOAD_REGISTER_IMM_DataDWord_bits 32 +#define GEN6_MI_LOAD_REGISTER_IMM_DataDWord_bits 32 +#define GEN5_MI_LOAD_REGISTER_IMM_DataDWord_bits 32 +#define GEN45_MI_LOAD_REGISTER_IMM_DataDWord_bits 32 +#define GEN4_MI_LOAD_REGISTER_IMM_DataDWord_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_IMM_DataDWord_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_LOAD_REGISTER_IMM_DataDWord_start 32 +#define GEN10_MI_LOAD_REGISTER_IMM_DataDWord_start 32 +#define GEN9_MI_LOAD_REGISTER_IMM_DataDWord_start 32 +#define GEN8_MI_LOAD_REGISTER_IMM_DataDWord_start 32 +#define GEN75_MI_LOAD_REGISTER_IMM_DataDWord_start 32 +#define GEN7_MI_LOAD_REGISTER_IMM_DataDWord_start 32 +#define GEN6_MI_LOAD_REGISTER_IMM_DataDWord_start 32 +#define GEN5_MI_LOAD_REGISTER_IMM_DataDWord_start 32 +#define GEN45_MI_LOAD_REGISTER_IMM_DataDWord_start 32 +#define GEN4_MI_LOAD_REGISTER_IMM_DataDWord_start 32 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_IMM_DataDWord_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_REGISTER_IMM::MI Command Opcode */ + + +#define GEN11_MI_LOAD_REGISTER_IMM_MICommandOpcode_bits 6 +#define GEN10_MI_LOAD_REGISTER_IMM_MICommandOpcode_bits 6 +#define GEN9_MI_LOAD_REGISTER_IMM_MICommandOpcode_bits 6 +#define GEN8_MI_LOAD_REGISTER_IMM_MICommandOpcode_bits 6 +#define GEN75_MI_LOAD_REGISTER_IMM_MICommandOpcode_bits 6 +#define GEN7_MI_LOAD_REGISTER_IMM_MICommandOpcode_bits 6 +#define GEN6_MI_LOAD_REGISTER_IMM_MICommandOpcode_bits 6 +#define GEN5_MI_LOAD_REGISTER_IMM_MICommandOpcode_bits 6 +#define GEN45_MI_LOAD_REGISTER_IMM_MICommandOpcode_bits 6 +#define GEN4_MI_LOAD_REGISTER_IMM_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_IMM_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 6; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_LOAD_REGISTER_IMM_MICommandOpcode_start 23 +#define GEN10_MI_LOAD_REGISTER_IMM_MICommandOpcode_start 23 +#define GEN9_MI_LOAD_REGISTER_IMM_MICommandOpcode_start 23 +#define GEN8_MI_LOAD_REGISTER_IMM_MICommandOpcode_start 23 +#define GEN75_MI_LOAD_REGISTER_IMM_MICommandOpcode_start 23 +#define GEN7_MI_LOAD_REGISTER_IMM_MICommandOpcode_start 23 +#define GEN6_MI_LOAD_REGISTER_IMM_MICommandOpcode_start 23 +#define GEN5_MI_LOAD_REGISTER_IMM_MICommandOpcode_start 23 +#define GEN45_MI_LOAD_REGISTER_IMM_MICommandOpcode_start 23 +#define GEN4_MI_LOAD_REGISTER_IMM_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_IMM_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 23; + } else { + return 23; + } + case 6: return 23; + case 5: return 23; + case 4: + if (devinfo->is_g4x) { + return 23; + } else { + return 23; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_REGISTER_IMM::Register Offset */ + + +#define GEN11_MI_LOAD_REGISTER_IMM_RegisterOffset_bits 21 +#define GEN10_MI_LOAD_REGISTER_IMM_RegisterOffset_bits 21 +#define GEN9_MI_LOAD_REGISTER_IMM_RegisterOffset_bits 21 +#define GEN8_MI_LOAD_REGISTER_IMM_RegisterOffset_bits 21 +#define GEN75_MI_LOAD_REGISTER_IMM_RegisterOffset_bits 21 +#define GEN7_MI_LOAD_REGISTER_IMM_RegisterOffset_bits 21 +#define GEN6_MI_LOAD_REGISTER_IMM_RegisterOffset_bits 21 +#define GEN5_MI_LOAD_REGISTER_IMM_RegisterOffset_bits 30 +#define GEN45_MI_LOAD_REGISTER_IMM_RegisterOffset_bits 30 +#define GEN4_MI_LOAD_REGISTER_IMM_RegisterOffset_bits 30 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_IMM_RegisterOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 21; + case 10: return 21; + case 9: return 21; + case 8: return 21; + case 7: + if (devinfo->is_haswell) { + return 21; + } else { + return 21; + } + case 6: return 21; + case 5: return 30; + case 4: + if (devinfo->is_g4x) { + return 30; + } else { + return 30; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_LOAD_REGISTER_IMM_RegisterOffset_start 2 +#define GEN10_MI_LOAD_REGISTER_IMM_RegisterOffset_start 2 +#define GEN9_MI_LOAD_REGISTER_IMM_RegisterOffset_start 2 +#define GEN8_MI_LOAD_REGISTER_IMM_RegisterOffset_start 2 +#define GEN75_MI_LOAD_REGISTER_IMM_RegisterOffset_start 2 +#define GEN7_MI_LOAD_REGISTER_IMM_RegisterOffset_start 2 +#define GEN6_MI_LOAD_REGISTER_IMM_RegisterOffset_start 2 +#define GEN5_MI_LOAD_REGISTER_IMM_RegisterOffset_start 2 +#define GEN45_MI_LOAD_REGISTER_IMM_RegisterOffset_start 2 +#define GEN4_MI_LOAD_REGISTER_IMM_RegisterOffset_start 2 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_IMM_RegisterOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_REGISTER_MEM */ + + +#define GEN11_MI_LOAD_REGISTER_MEM_length 4 +#define GEN10_MI_LOAD_REGISTER_MEM_length 4 +#define GEN9_MI_LOAD_REGISTER_MEM_length 4 +#define GEN8_MI_LOAD_REGISTER_MEM_length 4 +#define GEN75_MI_LOAD_REGISTER_MEM_length 3 +#define GEN7_MI_LOAD_REGISTER_MEM_length 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_MEM_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_REGISTER_MEM::Add CS MMIO Start Offset */ + + +#define GEN11_MI_LOAD_REGISTER_MEM_AddCSMMIOStartOffset_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_MEM_AddCSMMIOStartOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_LOAD_REGISTER_MEM_AddCSMMIOStartOffset_start 19 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_MEM_AddCSMMIOStartOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 19; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_REGISTER_MEM::Add Loop Variable */ + + +#define GEN11_MI_LOAD_REGISTER_MEM_AddLoopVariable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_MEM_AddLoopVariable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_LOAD_REGISTER_MEM_AddLoopVariable_start 20 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_MEM_AddLoopVariable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 20; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_REGISTER_MEM::Async Mode Enable */ + + +#define GEN11_MI_LOAD_REGISTER_MEM_AsyncModeEnable_bits 1 +#define GEN10_MI_LOAD_REGISTER_MEM_AsyncModeEnable_bits 1 +#define GEN9_MI_LOAD_REGISTER_MEM_AsyncModeEnable_bits 1 +#define GEN8_MI_LOAD_REGISTER_MEM_AsyncModeEnable_bits 1 +#define GEN75_MI_LOAD_REGISTER_MEM_AsyncModeEnable_bits 1 +#define GEN7_MI_LOAD_REGISTER_MEM_AsyncModeEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_MEM_AsyncModeEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_LOAD_REGISTER_MEM_AsyncModeEnable_start 21 +#define GEN10_MI_LOAD_REGISTER_MEM_AsyncModeEnable_start 21 +#define GEN9_MI_LOAD_REGISTER_MEM_AsyncModeEnable_start 21 +#define GEN8_MI_LOAD_REGISTER_MEM_AsyncModeEnable_start 21 +#define GEN75_MI_LOAD_REGISTER_MEM_AsyncModeEnable_start 21 +#define GEN7_MI_LOAD_REGISTER_MEM_AsyncModeEnable_start 21 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_MEM_AsyncModeEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 21; + case 10: return 21; + case 9: return 21; + case 8: return 21; + case 7: + if (devinfo->is_haswell) { + return 21; + } else { + return 21; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_REGISTER_MEM::Command Type */ + + +#define GEN11_MI_LOAD_REGISTER_MEM_CommandType_bits 3 +#define GEN10_MI_LOAD_REGISTER_MEM_CommandType_bits 3 +#define GEN9_MI_LOAD_REGISTER_MEM_CommandType_bits 3 +#define GEN8_MI_LOAD_REGISTER_MEM_CommandType_bits 3 +#define GEN75_MI_LOAD_REGISTER_MEM_CommandType_bits 3 +#define GEN7_MI_LOAD_REGISTER_MEM_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_MEM_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_LOAD_REGISTER_MEM_CommandType_start 29 +#define GEN10_MI_LOAD_REGISTER_MEM_CommandType_start 29 +#define GEN9_MI_LOAD_REGISTER_MEM_CommandType_start 29 +#define GEN8_MI_LOAD_REGISTER_MEM_CommandType_start 29 +#define GEN75_MI_LOAD_REGISTER_MEM_CommandType_start 29 +#define GEN7_MI_LOAD_REGISTER_MEM_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_MEM_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_REGISTER_MEM::DWord Length */ + + +#define GEN11_MI_LOAD_REGISTER_MEM_DWordLength_bits 8 +#define GEN10_MI_LOAD_REGISTER_MEM_DWordLength_bits 8 +#define GEN9_MI_LOAD_REGISTER_MEM_DWordLength_bits 8 +#define GEN8_MI_LOAD_REGISTER_MEM_DWordLength_bits 8 +#define GEN75_MI_LOAD_REGISTER_MEM_DWordLength_bits 8 +#define GEN7_MI_LOAD_REGISTER_MEM_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_MEM_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_LOAD_REGISTER_MEM_DWordLength_start 0 +#define GEN10_MI_LOAD_REGISTER_MEM_DWordLength_start 0 +#define GEN9_MI_LOAD_REGISTER_MEM_DWordLength_start 0 +#define GEN8_MI_LOAD_REGISTER_MEM_DWordLength_start 0 +#define GEN75_MI_LOAD_REGISTER_MEM_DWordLength_start 0 +#define GEN7_MI_LOAD_REGISTER_MEM_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_MEM_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_REGISTER_MEM::MI Command Opcode */ + + +#define GEN11_MI_LOAD_REGISTER_MEM_MICommandOpcode_bits 6 +#define GEN10_MI_LOAD_REGISTER_MEM_MICommandOpcode_bits 6 +#define GEN9_MI_LOAD_REGISTER_MEM_MICommandOpcode_bits 6 +#define GEN8_MI_LOAD_REGISTER_MEM_MICommandOpcode_bits 6 +#define GEN75_MI_LOAD_REGISTER_MEM_MICommandOpcode_bits 6 +#define GEN7_MI_LOAD_REGISTER_MEM_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_MEM_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_LOAD_REGISTER_MEM_MICommandOpcode_start 23 +#define GEN10_MI_LOAD_REGISTER_MEM_MICommandOpcode_start 23 +#define GEN9_MI_LOAD_REGISTER_MEM_MICommandOpcode_start 23 +#define GEN8_MI_LOAD_REGISTER_MEM_MICommandOpcode_start 23 +#define GEN75_MI_LOAD_REGISTER_MEM_MICommandOpcode_start 23 +#define GEN7_MI_LOAD_REGISTER_MEM_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_MEM_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 23; + } else { + return 23; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_REGISTER_MEM::Memory Address */ + + +#define GEN11_MI_LOAD_REGISTER_MEM_MemoryAddress_bits 62 +#define GEN10_MI_LOAD_REGISTER_MEM_MemoryAddress_bits 62 +#define GEN9_MI_LOAD_REGISTER_MEM_MemoryAddress_bits 62 +#define GEN8_MI_LOAD_REGISTER_MEM_MemoryAddress_bits 62 +#define GEN75_MI_LOAD_REGISTER_MEM_MemoryAddress_bits 30 +#define GEN7_MI_LOAD_REGISTER_MEM_MemoryAddress_bits 30 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_MEM_MemoryAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 62; + case 10: return 62; + case 9: return 62; + case 8: return 62; + case 7: + if (devinfo->is_haswell) { + return 30; + } else { + return 30; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_LOAD_REGISTER_MEM_MemoryAddress_start 66 +#define GEN10_MI_LOAD_REGISTER_MEM_MemoryAddress_start 66 +#define GEN9_MI_LOAD_REGISTER_MEM_MemoryAddress_start 66 +#define GEN8_MI_LOAD_REGISTER_MEM_MemoryAddress_start 66 +#define GEN75_MI_LOAD_REGISTER_MEM_MemoryAddress_start 66 +#define GEN7_MI_LOAD_REGISTER_MEM_MemoryAddress_start 66 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_MEM_MemoryAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 66; + case 10: return 66; + case 9: return 66; + case 8: return 66; + case 7: + if (devinfo->is_haswell) { + return 66; + } else { + return 66; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_REGISTER_MEM::Register Address */ + + +#define GEN11_MI_LOAD_REGISTER_MEM_RegisterAddress_bits 21 +#define GEN10_MI_LOAD_REGISTER_MEM_RegisterAddress_bits 21 +#define GEN9_MI_LOAD_REGISTER_MEM_RegisterAddress_bits 21 +#define GEN8_MI_LOAD_REGISTER_MEM_RegisterAddress_bits 21 +#define GEN75_MI_LOAD_REGISTER_MEM_RegisterAddress_bits 21 +#define GEN7_MI_LOAD_REGISTER_MEM_RegisterAddress_bits 21 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_MEM_RegisterAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 21; + case 10: return 21; + case 9: return 21; + case 8: return 21; + case 7: + if (devinfo->is_haswell) { + return 21; + } else { + return 21; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_LOAD_REGISTER_MEM_RegisterAddress_start 34 +#define GEN10_MI_LOAD_REGISTER_MEM_RegisterAddress_start 34 +#define GEN9_MI_LOAD_REGISTER_MEM_RegisterAddress_start 34 +#define GEN8_MI_LOAD_REGISTER_MEM_RegisterAddress_start 34 +#define GEN75_MI_LOAD_REGISTER_MEM_RegisterAddress_start 34 +#define GEN7_MI_LOAD_REGISTER_MEM_RegisterAddress_start 34 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_MEM_RegisterAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 34; + case 10: return 34; + case 9: return 34; + case 8: return 34; + case 7: + if (devinfo->is_haswell) { + return 34; + } else { + return 34; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_REGISTER_MEM::Use Global GTT */ + + +#define GEN11_MI_LOAD_REGISTER_MEM_UseGlobalGTT_bits 1 +#define GEN10_MI_LOAD_REGISTER_MEM_UseGlobalGTT_bits 1 +#define GEN9_MI_LOAD_REGISTER_MEM_UseGlobalGTT_bits 1 +#define GEN8_MI_LOAD_REGISTER_MEM_UseGlobalGTT_bits 1 +#define GEN75_MI_LOAD_REGISTER_MEM_UseGlobalGTT_bits 1 +#define GEN7_MI_LOAD_REGISTER_MEM_UseGlobalGTT_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_MEM_UseGlobalGTT_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_LOAD_REGISTER_MEM_UseGlobalGTT_start 22 +#define GEN10_MI_LOAD_REGISTER_MEM_UseGlobalGTT_start 22 +#define GEN9_MI_LOAD_REGISTER_MEM_UseGlobalGTT_start 22 +#define GEN8_MI_LOAD_REGISTER_MEM_UseGlobalGTT_start 22 +#define GEN75_MI_LOAD_REGISTER_MEM_UseGlobalGTT_start 22 +#define GEN7_MI_LOAD_REGISTER_MEM_UseGlobalGTT_start 22 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_MEM_UseGlobalGTT_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 22; + case 10: return 22; + case 9: return 22; + case 8: return 22; + case 7: + if (devinfo->is_haswell) { + return 22; + } else { + return 22; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_REGISTER_REG */ + + +#define GEN11_MI_LOAD_REGISTER_REG_length 3 +#define GEN10_MI_LOAD_REGISTER_REG_length 3 +#define GEN9_MI_LOAD_REGISTER_REG_length 3 +#define GEN8_MI_LOAD_REGISTER_REG_length 3 +#define GEN75_MI_LOAD_REGISTER_REG_length 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_REG_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_REGISTER_REG::Add CS MMIO Start Offset Destination */ + + +#define GEN11_MI_LOAD_REGISTER_REG_AddCSMMIOStartOffsetDestination_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_REG_AddCSMMIOStartOffsetDestination_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_LOAD_REGISTER_REG_AddCSMMIOStartOffsetDestination_start 19 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_REG_AddCSMMIOStartOffsetDestination_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 19; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_REGISTER_REG::Add CS MMIO Start Offset Source */ + + +#define GEN11_MI_LOAD_REGISTER_REG_AddCSMMIOStartOffsetSource_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_REG_AddCSMMIOStartOffsetSource_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_LOAD_REGISTER_REG_AddCSMMIOStartOffsetSource_start 18 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_REG_AddCSMMIOStartOffsetSource_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 18; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_REGISTER_REG::Command Type */ + + +#define GEN11_MI_LOAD_REGISTER_REG_CommandType_bits 3 +#define GEN10_MI_LOAD_REGISTER_REG_CommandType_bits 3 +#define GEN9_MI_LOAD_REGISTER_REG_CommandType_bits 3 +#define GEN8_MI_LOAD_REGISTER_REG_CommandType_bits 3 +#define GEN75_MI_LOAD_REGISTER_REG_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_REG_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_LOAD_REGISTER_REG_CommandType_start 29 +#define GEN10_MI_LOAD_REGISTER_REG_CommandType_start 29 +#define GEN9_MI_LOAD_REGISTER_REG_CommandType_start 29 +#define GEN8_MI_LOAD_REGISTER_REG_CommandType_start 29 +#define GEN75_MI_LOAD_REGISTER_REG_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_REG_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_REGISTER_REG::DWord Length */ + + +#define GEN11_MI_LOAD_REGISTER_REG_DWordLength_bits 8 +#define GEN10_MI_LOAD_REGISTER_REG_DWordLength_bits 8 +#define GEN9_MI_LOAD_REGISTER_REG_DWordLength_bits 8 +#define GEN8_MI_LOAD_REGISTER_REG_DWordLength_bits 8 +#define GEN75_MI_LOAD_REGISTER_REG_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_REG_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_LOAD_REGISTER_REG_DWordLength_start 0 +#define GEN10_MI_LOAD_REGISTER_REG_DWordLength_start 0 +#define GEN9_MI_LOAD_REGISTER_REG_DWordLength_start 0 +#define GEN8_MI_LOAD_REGISTER_REG_DWordLength_start 0 +#define GEN75_MI_LOAD_REGISTER_REG_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_REG_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_REGISTER_REG::Destination Register Address */ + + +#define GEN11_MI_LOAD_REGISTER_REG_DestinationRegisterAddress_bits 21 +#define GEN10_MI_LOAD_REGISTER_REG_DestinationRegisterAddress_bits 21 +#define GEN9_MI_LOAD_REGISTER_REG_DestinationRegisterAddress_bits 21 +#define GEN8_MI_LOAD_REGISTER_REG_DestinationRegisterAddress_bits 21 +#define GEN75_MI_LOAD_REGISTER_REG_DestinationRegisterAddress_bits 21 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_REG_DestinationRegisterAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 21; + case 10: return 21; + case 9: return 21; + case 8: return 21; + case 7: + if (devinfo->is_haswell) { + return 21; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_LOAD_REGISTER_REG_DestinationRegisterAddress_start 66 +#define GEN10_MI_LOAD_REGISTER_REG_DestinationRegisterAddress_start 66 +#define GEN9_MI_LOAD_REGISTER_REG_DestinationRegisterAddress_start 66 +#define GEN8_MI_LOAD_REGISTER_REG_DestinationRegisterAddress_start 66 +#define GEN75_MI_LOAD_REGISTER_REG_DestinationRegisterAddress_start 66 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_REG_DestinationRegisterAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 66; + case 10: return 66; + case 9: return 66; + case 8: return 66; + case 7: + if (devinfo->is_haswell) { + return 66; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_REGISTER_REG::MI Command Opcode */ + + +#define GEN11_MI_LOAD_REGISTER_REG_MICommandOpcode_bits 6 +#define GEN10_MI_LOAD_REGISTER_REG_MICommandOpcode_bits 6 +#define GEN9_MI_LOAD_REGISTER_REG_MICommandOpcode_bits 6 +#define GEN8_MI_LOAD_REGISTER_REG_MICommandOpcode_bits 6 +#define GEN75_MI_LOAD_REGISTER_REG_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_REG_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_LOAD_REGISTER_REG_MICommandOpcode_start 23 +#define GEN10_MI_LOAD_REGISTER_REG_MICommandOpcode_start 23 +#define GEN9_MI_LOAD_REGISTER_REG_MICommandOpcode_start 23 +#define GEN8_MI_LOAD_REGISTER_REG_MICommandOpcode_start 23 +#define GEN75_MI_LOAD_REGISTER_REG_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_REG_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 23; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_REGISTER_REG::Source Register Address */ + + +#define GEN11_MI_LOAD_REGISTER_REG_SourceRegisterAddress_bits 21 +#define GEN10_MI_LOAD_REGISTER_REG_SourceRegisterAddress_bits 21 +#define GEN9_MI_LOAD_REGISTER_REG_SourceRegisterAddress_bits 21 +#define GEN8_MI_LOAD_REGISTER_REG_SourceRegisterAddress_bits 21 +#define GEN75_MI_LOAD_REGISTER_REG_SourceRegisterAddress_bits 21 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_REG_SourceRegisterAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 21; + case 10: return 21; + case 9: return 21; + case 8: return 21; + case 7: + if (devinfo->is_haswell) { + return 21; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_LOAD_REGISTER_REG_SourceRegisterAddress_start 34 +#define GEN10_MI_LOAD_REGISTER_REG_SourceRegisterAddress_start 34 +#define GEN9_MI_LOAD_REGISTER_REG_SourceRegisterAddress_start 34 +#define GEN8_MI_LOAD_REGISTER_REG_SourceRegisterAddress_start 34 +#define GEN75_MI_LOAD_REGISTER_REG_SourceRegisterAddress_start 34 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_REGISTER_REG_SourceRegisterAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 34; + case 10: return 34; + case 9: return 34; + case 8: return 34; + case 7: + if (devinfo->is_haswell) { + return 34; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_SCAN_LINES_EXCL */ + + +#define GEN11_MI_LOAD_SCAN_LINES_EXCL_length 2 +#define GEN10_MI_LOAD_SCAN_LINES_EXCL_length 2 +#define GEN9_MI_LOAD_SCAN_LINES_EXCL_length 2 +#define GEN8_MI_LOAD_SCAN_LINES_EXCL_length 2 +#define GEN75_MI_LOAD_SCAN_LINES_EXCL_length 2 +#define GEN6_MI_LOAD_SCAN_LINES_EXCL_length 2 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_SCAN_LINES_EXCL_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 0; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_SCAN_LINES_EXCL::Command Type */ + + +#define GEN11_MI_LOAD_SCAN_LINES_EXCL_CommandType_bits 3 +#define GEN10_MI_LOAD_SCAN_LINES_EXCL_CommandType_bits 3 +#define GEN9_MI_LOAD_SCAN_LINES_EXCL_CommandType_bits 3 +#define GEN8_MI_LOAD_SCAN_LINES_EXCL_CommandType_bits 3 +#define GEN75_MI_LOAD_SCAN_LINES_EXCL_CommandType_bits 3 +#define GEN6_MI_LOAD_SCAN_LINES_EXCL_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_SCAN_LINES_EXCL_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_LOAD_SCAN_LINES_EXCL_CommandType_start 29 +#define GEN10_MI_LOAD_SCAN_LINES_EXCL_CommandType_start 29 +#define GEN9_MI_LOAD_SCAN_LINES_EXCL_CommandType_start 29 +#define GEN8_MI_LOAD_SCAN_LINES_EXCL_CommandType_start 29 +#define GEN75_MI_LOAD_SCAN_LINES_EXCL_CommandType_start 29 +#define GEN6_MI_LOAD_SCAN_LINES_EXCL_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_SCAN_LINES_EXCL_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 0; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_SCAN_LINES_EXCL::DWord Length */ + + +#define GEN11_MI_LOAD_SCAN_LINES_EXCL_DWordLength_bits 6 +#define GEN10_MI_LOAD_SCAN_LINES_EXCL_DWordLength_bits 6 +#define GEN9_MI_LOAD_SCAN_LINES_EXCL_DWordLength_bits 6 +#define GEN8_MI_LOAD_SCAN_LINES_EXCL_DWordLength_bits 6 +#define GEN75_MI_LOAD_SCAN_LINES_EXCL_DWordLength_bits 6 +#define GEN6_MI_LOAD_SCAN_LINES_EXCL_DWordLength_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_SCAN_LINES_EXCL_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 0; + } + case 6: return 6; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_LOAD_SCAN_LINES_EXCL_DWordLength_start 0 +#define GEN10_MI_LOAD_SCAN_LINES_EXCL_DWordLength_start 0 +#define GEN9_MI_LOAD_SCAN_LINES_EXCL_DWordLength_start 0 +#define GEN8_MI_LOAD_SCAN_LINES_EXCL_DWordLength_start 0 +#define GEN75_MI_LOAD_SCAN_LINES_EXCL_DWordLength_start 0 +#define GEN6_MI_LOAD_SCAN_LINES_EXCL_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_SCAN_LINES_EXCL_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_SCAN_LINES_EXCL::Display (Plane) Select */ + + +#define GEN11_MI_LOAD_SCAN_LINES_EXCL_DisplayPlaneSelect_bits 3 +#define GEN10_MI_LOAD_SCAN_LINES_EXCL_DisplayPlaneSelect_bits 3 +#define GEN9_MI_LOAD_SCAN_LINES_EXCL_DisplayPlaneSelect_bits 3 +#define GEN8_MI_LOAD_SCAN_LINES_EXCL_DisplayPlaneSelect_bits 3 +#define GEN75_MI_LOAD_SCAN_LINES_EXCL_DisplayPlaneSelect_bits 3 +#define GEN6_MI_LOAD_SCAN_LINES_EXCL_DisplayPlaneSelect_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_SCAN_LINES_EXCL_DisplayPlaneSelect_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_LOAD_SCAN_LINES_EXCL_DisplayPlaneSelect_start 19 +#define GEN10_MI_LOAD_SCAN_LINES_EXCL_DisplayPlaneSelect_start 19 +#define GEN9_MI_LOAD_SCAN_LINES_EXCL_DisplayPlaneSelect_start 19 +#define GEN8_MI_LOAD_SCAN_LINES_EXCL_DisplayPlaneSelect_start 19 +#define GEN75_MI_LOAD_SCAN_LINES_EXCL_DisplayPlaneSelect_start 19 +#define GEN6_MI_LOAD_SCAN_LINES_EXCL_DisplayPlaneSelect_start 19 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_SCAN_LINES_EXCL_DisplayPlaneSelect_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 19; + case 10: return 19; + case 9: return 19; + case 8: return 19; + case 7: + if (devinfo->is_haswell) { + return 19; + } else { + return 0; + } + case 6: return 19; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_SCAN_LINES_EXCL::End Scan Line Number */ + + +#define GEN11_MI_LOAD_SCAN_LINES_EXCL_EndScanLineNumber_bits 13 +#define GEN10_MI_LOAD_SCAN_LINES_EXCL_EndScanLineNumber_bits 13 +#define GEN9_MI_LOAD_SCAN_LINES_EXCL_EndScanLineNumber_bits 13 +#define GEN8_MI_LOAD_SCAN_LINES_EXCL_EndScanLineNumber_bits 13 +#define GEN75_MI_LOAD_SCAN_LINES_EXCL_EndScanLineNumber_bits 13 +#define GEN6_MI_LOAD_SCAN_LINES_EXCL_EndScanLineNumber_bits 13 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_SCAN_LINES_EXCL_EndScanLineNumber_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 13; + case 10: return 13; + case 9: return 13; + case 8: return 13; + case 7: + if (devinfo->is_haswell) { + return 13; + } else { + return 0; + } + case 6: return 13; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_LOAD_SCAN_LINES_EXCL_EndScanLineNumber_start 32 +#define GEN10_MI_LOAD_SCAN_LINES_EXCL_EndScanLineNumber_start 32 +#define GEN9_MI_LOAD_SCAN_LINES_EXCL_EndScanLineNumber_start 32 +#define GEN8_MI_LOAD_SCAN_LINES_EXCL_EndScanLineNumber_start 32 +#define GEN75_MI_LOAD_SCAN_LINES_EXCL_EndScanLineNumber_start 32 +#define GEN6_MI_LOAD_SCAN_LINES_EXCL_EndScanLineNumber_start 32 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_SCAN_LINES_EXCL_EndScanLineNumber_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 0; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_SCAN_LINES_EXCL::MI Command Opcode */ + + +#define GEN11_MI_LOAD_SCAN_LINES_EXCL_MICommandOpcode_bits 6 +#define GEN10_MI_LOAD_SCAN_LINES_EXCL_MICommandOpcode_bits 6 +#define GEN9_MI_LOAD_SCAN_LINES_EXCL_MICommandOpcode_bits 6 +#define GEN8_MI_LOAD_SCAN_LINES_EXCL_MICommandOpcode_bits 6 +#define GEN75_MI_LOAD_SCAN_LINES_EXCL_MICommandOpcode_bits 6 +#define GEN6_MI_LOAD_SCAN_LINES_EXCL_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_SCAN_LINES_EXCL_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 0; + } + case 6: return 6; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_LOAD_SCAN_LINES_EXCL_MICommandOpcode_start 23 +#define GEN10_MI_LOAD_SCAN_LINES_EXCL_MICommandOpcode_start 23 +#define GEN9_MI_LOAD_SCAN_LINES_EXCL_MICommandOpcode_start 23 +#define GEN8_MI_LOAD_SCAN_LINES_EXCL_MICommandOpcode_start 23 +#define GEN75_MI_LOAD_SCAN_LINES_EXCL_MICommandOpcode_start 23 +#define GEN6_MI_LOAD_SCAN_LINES_EXCL_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_SCAN_LINES_EXCL_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 23; + } else { + return 0; + } + case 6: return 23; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_SCAN_LINES_EXCL::Start Scan Line Number */ + + +#define GEN11_MI_LOAD_SCAN_LINES_EXCL_StartScanLineNumber_bits 13 +#define GEN10_MI_LOAD_SCAN_LINES_EXCL_StartScanLineNumber_bits 13 +#define GEN9_MI_LOAD_SCAN_LINES_EXCL_StartScanLineNumber_bits 13 +#define GEN8_MI_LOAD_SCAN_LINES_EXCL_StartScanLineNumber_bits 13 +#define GEN75_MI_LOAD_SCAN_LINES_EXCL_StartScanLineNumber_bits 13 +#define GEN6_MI_LOAD_SCAN_LINES_EXCL_StartScanLineNumber_bits 13 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_SCAN_LINES_EXCL_StartScanLineNumber_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 13; + case 10: return 13; + case 9: return 13; + case 8: return 13; + case 7: + if (devinfo->is_haswell) { + return 13; + } else { + return 0; + } + case 6: return 13; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_LOAD_SCAN_LINES_EXCL_StartScanLineNumber_start 48 +#define GEN10_MI_LOAD_SCAN_LINES_EXCL_StartScanLineNumber_start 48 +#define GEN9_MI_LOAD_SCAN_LINES_EXCL_StartScanLineNumber_start 48 +#define GEN8_MI_LOAD_SCAN_LINES_EXCL_StartScanLineNumber_start 48 +#define GEN75_MI_LOAD_SCAN_LINES_EXCL_StartScanLineNumber_start 48 +#define GEN6_MI_LOAD_SCAN_LINES_EXCL_StartScanLineNumber_start 48 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_SCAN_LINES_EXCL_StartScanLineNumber_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 48; + case 7: + if (devinfo->is_haswell) { + return 48; + } else { + return 0; + } + case 6: return 48; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_SCAN_LINES_INCL */ + + +#define GEN11_MI_LOAD_SCAN_LINES_INCL_length 2 +#define GEN10_MI_LOAD_SCAN_LINES_INCL_length 2 +#define GEN9_MI_LOAD_SCAN_LINES_INCL_length 2 +#define GEN8_MI_LOAD_SCAN_LINES_INCL_length 2 +#define GEN75_MI_LOAD_SCAN_LINES_INCL_length 2 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_SCAN_LINES_INCL_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_SCAN_LINES_INCL::Command Type */ + + +#define GEN11_MI_LOAD_SCAN_LINES_INCL_CommandType_bits 3 +#define GEN10_MI_LOAD_SCAN_LINES_INCL_CommandType_bits 3 +#define GEN9_MI_LOAD_SCAN_LINES_INCL_CommandType_bits 3 +#define GEN8_MI_LOAD_SCAN_LINES_INCL_CommandType_bits 3 +#define GEN75_MI_LOAD_SCAN_LINES_INCL_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_SCAN_LINES_INCL_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_LOAD_SCAN_LINES_INCL_CommandType_start 29 +#define GEN10_MI_LOAD_SCAN_LINES_INCL_CommandType_start 29 +#define GEN9_MI_LOAD_SCAN_LINES_INCL_CommandType_start 29 +#define GEN8_MI_LOAD_SCAN_LINES_INCL_CommandType_start 29 +#define GEN75_MI_LOAD_SCAN_LINES_INCL_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_SCAN_LINES_INCL_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_SCAN_LINES_INCL::DWord Length */ + + +#define GEN11_MI_LOAD_SCAN_LINES_INCL_DWordLength_bits 6 +#define GEN10_MI_LOAD_SCAN_LINES_INCL_DWordLength_bits 6 +#define GEN9_MI_LOAD_SCAN_LINES_INCL_DWordLength_bits 6 +#define GEN8_MI_LOAD_SCAN_LINES_INCL_DWordLength_bits 6 +#define GEN75_MI_LOAD_SCAN_LINES_INCL_DWordLength_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_SCAN_LINES_INCL_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_LOAD_SCAN_LINES_INCL_DWordLength_start 0 +#define GEN10_MI_LOAD_SCAN_LINES_INCL_DWordLength_start 0 +#define GEN9_MI_LOAD_SCAN_LINES_INCL_DWordLength_start 0 +#define GEN8_MI_LOAD_SCAN_LINES_INCL_DWordLength_start 0 +#define GEN75_MI_LOAD_SCAN_LINES_INCL_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_SCAN_LINES_INCL_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_SCAN_LINES_INCL::Display (Plane) Select */ + + +#define GEN11_MI_LOAD_SCAN_LINES_INCL_DisplayPlaneSelect_bits 3 +#define GEN10_MI_LOAD_SCAN_LINES_INCL_DisplayPlaneSelect_bits 3 +#define GEN9_MI_LOAD_SCAN_LINES_INCL_DisplayPlaneSelect_bits 3 +#define GEN8_MI_LOAD_SCAN_LINES_INCL_DisplayPlaneSelect_bits 3 +#define GEN75_MI_LOAD_SCAN_LINES_INCL_DisplayPlaneSelect_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_SCAN_LINES_INCL_DisplayPlaneSelect_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_LOAD_SCAN_LINES_INCL_DisplayPlaneSelect_start 19 +#define GEN10_MI_LOAD_SCAN_LINES_INCL_DisplayPlaneSelect_start 19 +#define GEN9_MI_LOAD_SCAN_LINES_INCL_DisplayPlaneSelect_start 19 +#define GEN8_MI_LOAD_SCAN_LINES_INCL_DisplayPlaneSelect_start 19 +#define GEN75_MI_LOAD_SCAN_LINES_INCL_DisplayPlaneSelect_start 19 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_SCAN_LINES_INCL_DisplayPlaneSelect_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 19; + case 10: return 19; + case 9: return 19; + case 8: return 19; + case 7: + if (devinfo->is_haswell) { + return 19; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_SCAN_LINES_INCL::End Scan Line Number */ + + +#define GEN11_MI_LOAD_SCAN_LINES_INCL_EndScanLineNumber_bits 13 +#define GEN10_MI_LOAD_SCAN_LINES_INCL_EndScanLineNumber_bits 13 +#define GEN9_MI_LOAD_SCAN_LINES_INCL_EndScanLineNumber_bits 13 +#define GEN8_MI_LOAD_SCAN_LINES_INCL_EndScanLineNumber_bits 13 +#define GEN75_MI_LOAD_SCAN_LINES_INCL_EndScanLineNumber_bits 13 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_SCAN_LINES_INCL_EndScanLineNumber_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 13; + case 10: return 13; + case 9: return 13; + case 8: return 13; + case 7: + if (devinfo->is_haswell) { + return 13; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_LOAD_SCAN_LINES_INCL_EndScanLineNumber_start 32 +#define GEN10_MI_LOAD_SCAN_LINES_INCL_EndScanLineNumber_start 32 +#define GEN9_MI_LOAD_SCAN_LINES_INCL_EndScanLineNumber_start 32 +#define GEN8_MI_LOAD_SCAN_LINES_INCL_EndScanLineNumber_start 32 +#define GEN75_MI_LOAD_SCAN_LINES_INCL_EndScanLineNumber_start 32 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_SCAN_LINES_INCL_EndScanLineNumber_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_SCAN_LINES_INCL::MI Command Opcode */ + + +#define GEN11_MI_LOAD_SCAN_LINES_INCL_MICommandOpcode_bits 6 +#define GEN10_MI_LOAD_SCAN_LINES_INCL_MICommandOpcode_bits 6 +#define GEN9_MI_LOAD_SCAN_LINES_INCL_MICommandOpcode_bits 6 +#define GEN8_MI_LOAD_SCAN_LINES_INCL_MICommandOpcode_bits 6 +#define GEN75_MI_LOAD_SCAN_LINES_INCL_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_SCAN_LINES_INCL_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_LOAD_SCAN_LINES_INCL_MICommandOpcode_start 23 +#define GEN10_MI_LOAD_SCAN_LINES_INCL_MICommandOpcode_start 23 +#define GEN9_MI_LOAD_SCAN_LINES_INCL_MICommandOpcode_start 23 +#define GEN8_MI_LOAD_SCAN_LINES_INCL_MICommandOpcode_start 23 +#define GEN75_MI_LOAD_SCAN_LINES_INCL_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_SCAN_LINES_INCL_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 23; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_SCAN_LINES_INCL::Scan Line Event Done Forward */ + + +#define GEN11_MI_LOAD_SCAN_LINES_INCL_ScanLineEventDoneForward_bits 2 +#define GEN10_MI_LOAD_SCAN_LINES_INCL_ScanLineEventDoneForward_bits 2 +#define GEN9_MI_LOAD_SCAN_LINES_INCL_ScanLineEventDoneForward_bits 2 +#define GEN8_MI_LOAD_SCAN_LINES_INCL_ScanLineEventDoneForward_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_SCAN_LINES_INCL_ScanLineEventDoneForward_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_LOAD_SCAN_LINES_INCL_ScanLineEventDoneForward_start 17 +#define GEN10_MI_LOAD_SCAN_LINES_INCL_ScanLineEventDoneForward_start 17 +#define GEN9_MI_LOAD_SCAN_LINES_INCL_ScanLineEventDoneForward_start 17 +#define GEN8_MI_LOAD_SCAN_LINES_INCL_ScanLineEventDoneForward_start 17 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_SCAN_LINES_INCL_ScanLineEventDoneForward_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 17; + case 10: return 17; + case 9: return 17; + case 8: return 17; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_SCAN_LINES_INCL::Start Scan Line Number */ + + +#define GEN11_MI_LOAD_SCAN_LINES_INCL_StartScanLineNumber_bits 13 +#define GEN10_MI_LOAD_SCAN_LINES_INCL_StartScanLineNumber_bits 13 +#define GEN9_MI_LOAD_SCAN_LINES_INCL_StartScanLineNumber_bits 13 +#define GEN8_MI_LOAD_SCAN_LINES_INCL_StartScanLineNumber_bits 13 +#define GEN75_MI_LOAD_SCAN_LINES_INCL_StartScanLineNumber_bits 13 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_SCAN_LINES_INCL_StartScanLineNumber_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 13; + case 10: return 13; + case 9: return 13; + case 8: return 13; + case 7: + if (devinfo->is_haswell) { + return 13; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_LOAD_SCAN_LINES_INCL_StartScanLineNumber_start 48 +#define GEN10_MI_LOAD_SCAN_LINES_INCL_StartScanLineNumber_start 48 +#define GEN9_MI_LOAD_SCAN_LINES_INCL_StartScanLineNumber_start 48 +#define GEN8_MI_LOAD_SCAN_LINES_INCL_StartScanLineNumber_start 48 +#define GEN75_MI_LOAD_SCAN_LINES_INCL_StartScanLineNumber_start 48 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_SCAN_LINES_INCL_StartScanLineNumber_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 48; + case 7: + if (devinfo->is_haswell) { + return 48; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_URB_MEM */ + + +#define GEN9_MI_LOAD_URB_MEM_length 4 +#define GEN8_MI_LOAD_URB_MEM_length 4 +#define GEN75_MI_LOAD_URB_MEM_length 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_URB_MEM_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_URB_MEM::Command Type */ + + +#define GEN9_MI_LOAD_URB_MEM_CommandType_bits 3 +#define GEN8_MI_LOAD_URB_MEM_CommandType_bits 3 +#define GEN75_MI_LOAD_URB_MEM_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_URB_MEM_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_MI_LOAD_URB_MEM_CommandType_start 29 +#define GEN8_MI_LOAD_URB_MEM_CommandType_start 29 +#define GEN75_MI_LOAD_URB_MEM_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_URB_MEM_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_URB_MEM::DWord Length */ + + +#define GEN9_MI_LOAD_URB_MEM_DWordLength_bits 8 +#define GEN8_MI_LOAD_URB_MEM_DWordLength_bits 8 +#define GEN75_MI_LOAD_URB_MEM_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_URB_MEM_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_MI_LOAD_URB_MEM_DWordLength_start 0 +#define GEN8_MI_LOAD_URB_MEM_DWordLength_start 0 +#define GEN75_MI_LOAD_URB_MEM_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_URB_MEM_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_URB_MEM::MI Command Opcode */ + + +#define GEN9_MI_LOAD_URB_MEM_MICommandOpcode_bits 6 +#define GEN8_MI_LOAD_URB_MEM_MICommandOpcode_bits 6 +#define GEN75_MI_LOAD_URB_MEM_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_URB_MEM_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_MI_LOAD_URB_MEM_MICommandOpcode_start 23 +#define GEN8_MI_LOAD_URB_MEM_MICommandOpcode_start 23 +#define GEN75_MI_LOAD_URB_MEM_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_URB_MEM_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 23; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_URB_MEM::Memory Address */ + + +#define GEN9_MI_LOAD_URB_MEM_MemoryAddress_bits 58 +#define GEN8_MI_LOAD_URB_MEM_MemoryAddress_bits 58 +#define GEN75_MI_LOAD_URB_MEM_MemoryAddress_bits 26 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_URB_MEM_MemoryAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 58; + case 8: return 58; + case 7: + if (devinfo->is_haswell) { + return 26; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_MI_LOAD_URB_MEM_MemoryAddress_start 70 +#define GEN8_MI_LOAD_URB_MEM_MemoryAddress_start 70 +#define GEN75_MI_LOAD_URB_MEM_MemoryAddress_start 70 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_URB_MEM_MemoryAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 70; + case 8: return 70; + case 7: + if (devinfo->is_haswell) { + return 70; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_LOAD_URB_MEM::URB Address */ + + +#define GEN9_MI_LOAD_URB_MEM_URBAddress_bits 13 +#define GEN8_MI_LOAD_URB_MEM_URBAddress_bits 13 +#define GEN75_MI_LOAD_URB_MEM_URBAddress_bits 13 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_URB_MEM_URBAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 13; + case 8: return 13; + case 7: + if (devinfo->is_haswell) { + return 13; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_MI_LOAD_URB_MEM_URBAddress_start 34 +#define GEN8_MI_LOAD_URB_MEM_URBAddress_start 34 +#define GEN75_MI_LOAD_URB_MEM_URBAddress_start 34 + +static inline uint32_t ATTRIBUTE_PURE +MI_LOAD_URB_MEM_URBAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 34; + case 8: return 34; + case 7: + if (devinfo->is_haswell) { + return 34; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_MATH */ + + + + + +/* MI_MATH::Command Type */ + + +#define GEN11_MI_MATH_CommandType_bits 3 +#define GEN10_MI_MATH_CommandType_bits 3 +#define GEN9_MI_MATH_CommandType_bits 3 +#define GEN8_MI_MATH_CommandType_bits 3 +#define GEN75_MI_MATH_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_MATH_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_MATH_CommandType_start 29 +#define GEN10_MI_MATH_CommandType_start 29 +#define GEN9_MI_MATH_CommandType_start 29 +#define GEN8_MI_MATH_CommandType_start 29 +#define GEN75_MI_MATH_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_MATH_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_MATH::DWord Length */ + + +#define GEN11_MI_MATH_DWordLength_bits 8 +#define GEN10_MI_MATH_DWordLength_bits 8 +#define GEN9_MI_MATH_DWordLength_bits 8 +#define GEN8_MI_MATH_DWordLength_bits 6 +#define GEN75_MI_MATH_DWordLength_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_MATH_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_MATH_DWordLength_start 0 +#define GEN10_MI_MATH_DWordLength_start 0 +#define GEN9_MI_MATH_DWordLength_start 0 +#define GEN8_MI_MATH_DWordLength_start 0 +#define GEN75_MI_MATH_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_MATH_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_MATH::Instruction */ + + +#define GEN11_MI_MATH_Instruction_bits 32 +#define GEN10_MI_MATH_Instruction_bits 32 +#define GEN9_MI_MATH_Instruction_bits 32 +#define GEN8_MI_MATH_Instruction_bits 32 +#define GEN75_MI_MATH_Instruction_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +MI_MATH_Instruction_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_MATH_Instruction_start 0 +#define GEN10_MI_MATH_Instruction_start 0 +#define GEN9_MI_MATH_Instruction_start 0 +#define GEN8_MI_MATH_Instruction_start 0 +#define GEN75_MI_MATH_Instruction_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_MATH_Instruction_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_MATH::MI Command Opcode */ + + +#define GEN11_MI_MATH_MICommandOpcode_bits 6 +#define GEN10_MI_MATH_MICommandOpcode_bits 6 +#define GEN9_MI_MATH_MICommandOpcode_bits 6 +#define GEN8_MI_MATH_MICommandOpcode_bits 6 +#define GEN75_MI_MATH_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_MATH_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_MATH_MICommandOpcode_start 23 +#define GEN10_MI_MATH_MICommandOpcode_start 23 +#define GEN9_MI_MATH_MICommandOpcode_start 23 +#define GEN8_MI_MATH_MICommandOpcode_start 23 +#define GEN75_MI_MATH_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_MATH_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 23; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_MATH_ALU_INSTRUCTION */ + + +#define GEN11_MI_MATH_ALU_INSTRUCTION_length 1 +#define GEN10_MI_MATH_ALU_INSTRUCTION_length 1 +#define GEN9_MI_MATH_ALU_INSTRUCTION_length 1 +#define GEN8_MI_MATH_ALU_INSTRUCTION_length 1 +#define GEN75_MI_MATH_ALU_INSTRUCTION_length 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_MATH_ALU_INSTRUCTION_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_MATH_ALU_INSTRUCTION::ALU Opcode */ + + +#define GEN11_MI_MATH_ALU_INSTRUCTION_ALUOpcode_bits 12 +#define GEN10_MI_MATH_ALU_INSTRUCTION_ALUOpcode_bits 12 +#define GEN9_MI_MATH_ALU_INSTRUCTION_ALUOpcode_bits 12 +#define GEN8_MI_MATH_ALU_INSTRUCTION_ALUOpcode_bits 12 +#define GEN75_MI_MATH_ALU_INSTRUCTION_ALUOpcode_bits 12 + +static inline uint32_t ATTRIBUTE_PURE +MI_MATH_ALU_INSTRUCTION_ALUOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 12; + case 10: return 12; + case 9: return 12; + case 8: return 12; + case 7: + if (devinfo->is_haswell) { + return 12; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_MATH_ALU_INSTRUCTION_ALUOpcode_start 20 +#define GEN10_MI_MATH_ALU_INSTRUCTION_ALUOpcode_start 20 +#define GEN9_MI_MATH_ALU_INSTRUCTION_ALUOpcode_start 20 +#define GEN8_MI_MATH_ALU_INSTRUCTION_ALUOpcode_start 20 +#define GEN75_MI_MATH_ALU_INSTRUCTION_ALUOpcode_start 20 + +static inline uint32_t ATTRIBUTE_PURE +MI_MATH_ALU_INSTRUCTION_ALUOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 20; + case 10: return 20; + case 9: return 20; + case 8: return 20; + case 7: + if (devinfo->is_haswell) { + return 20; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_MATH_ALU_INSTRUCTION::Operand 1 */ + + +#define GEN11_MI_MATH_ALU_INSTRUCTION_Operand1_bits 10 +#define GEN10_MI_MATH_ALU_INSTRUCTION_Operand1_bits 10 +#define GEN9_MI_MATH_ALU_INSTRUCTION_Operand1_bits 10 +#define GEN8_MI_MATH_ALU_INSTRUCTION_Operand1_bits 10 +#define GEN75_MI_MATH_ALU_INSTRUCTION_Operand1_bits 10 + +static inline uint32_t ATTRIBUTE_PURE +MI_MATH_ALU_INSTRUCTION_Operand1_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 10; + case 10: return 10; + case 9: return 10; + case 8: return 10; + case 7: + if (devinfo->is_haswell) { + return 10; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_MATH_ALU_INSTRUCTION_Operand1_start 10 +#define GEN10_MI_MATH_ALU_INSTRUCTION_Operand1_start 10 +#define GEN9_MI_MATH_ALU_INSTRUCTION_Operand1_start 10 +#define GEN8_MI_MATH_ALU_INSTRUCTION_Operand1_start 10 +#define GEN75_MI_MATH_ALU_INSTRUCTION_Operand1_start 10 + +static inline uint32_t ATTRIBUTE_PURE +MI_MATH_ALU_INSTRUCTION_Operand1_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 10; + case 10: return 10; + case 9: return 10; + case 8: return 10; + case 7: + if (devinfo->is_haswell) { + return 10; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_MATH_ALU_INSTRUCTION::Operand 2 */ + + +#define GEN11_MI_MATH_ALU_INSTRUCTION_Operand2_bits 10 +#define GEN10_MI_MATH_ALU_INSTRUCTION_Operand2_bits 10 +#define GEN9_MI_MATH_ALU_INSTRUCTION_Operand2_bits 10 +#define GEN8_MI_MATH_ALU_INSTRUCTION_Operand2_bits 10 +#define GEN75_MI_MATH_ALU_INSTRUCTION_Operand2_bits 10 + +static inline uint32_t ATTRIBUTE_PURE +MI_MATH_ALU_INSTRUCTION_Operand2_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 10; + case 10: return 10; + case 9: return 10; + case 8: return 10; + case 7: + if (devinfo->is_haswell) { + return 10; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_MATH_ALU_INSTRUCTION_Operand2_start 0 +#define GEN10_MI_MATH_ALU_INSTRUCTION_Operand2_start 0 +#define GEN9_MI_MATH_ALU_INSTRUCTION_Operand2_start 0 +#define GEN8_MI_MATH_ALU_INSTRUCTION_Operand2_start 0 +#define GEN75_MI_MATH_ALU_INSTRUCTION_Operand2_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_MATH_ALU_INSTRUCTION_Operand2_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_NOOP */ + + +#define GEN11_MI_NOOP_length 1 +#define GEN10_MI_NOOP_length 1 +#define GEN9_MI_NOOP_length 1 +#define GEN8_MI_NOOP_length 1 +#define GEN75_MI_NOOP_length 1 +#define GEN7_MI_NOOP_length 1 +#define GEN6_MI_NOOP_length 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_NOOP_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_NOOP::Command Type */ + + +#define GEN11_MI_NOOP_CommandType_bits 3 +#define GEN10_MI_NOOP_CommandType_bits 3 +#define GEN9_MI_NOOP_CommandType_bits 3 +#define GEN8_MI_NOOP_CommandType_bits 3 +#define GEN75_MI_NOOP_CommandType_bits 3 +#define GEN7_MI_NOOP_CommandType_bits 3 +#define GEN6_MI_NOOP_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_NOOP_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_NOOP_CommandType_start 29 +#define GEN10_MI_NOOP_CommandType_start 29 +#define GEN9_MI_NOOP_CommandType_start 29 +#define GEN8_MI_NOOP_CommandType_start 29 +#define GEN75_MI_NOOP_CommandType_start 29 +#define GEN7_MI_NOOP_CommandType_start 29 +#define GEN6_MI_NOOP_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_NOOP_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_NOOP::Identification Number */ + + +#define GEN11_MI_NOOP_IdentificationNumber_bits 22 +#define GEN10_MI_NOOP_IdentificationNumber_bits 22 +#define GEN9_MI_NOOP_IdentificationNumber_bits 22 +#define GEN8_MI_NOOP_IdentificationNumber_bits 22 +#define GEN75_MI_NOOP_IdentificationNumber_bits 22 +#define GEN7_MI_NOOP_IdentificationNumber_bits 22 +#define GEN6_MI_NOOP_IdentificationNumber_bits 22 + +static inline uint32_t ATTRIBUTE_PURE +MI_NOOP_IdentificationNumber_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 22; + case 10: return 22; + case 9: return 22; + case 8: return 22; + case 7: + if (devinfo->is_haswell) { + return 22; + } else { + return 22; + } + case 6: return 22; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_NOOP_IdentificationNumber_start 0 +#define GEN10_MI_NOOP_IdentificationNumber_start 0 +#define GEN9_MI_NOOP_IdentificationNumber_start 0 +#define GEN8_MI_NOOP_IdentificationNumber_start 0 +#define GEN75_MI_NOOP_IdentificationNumber_start 0 +#define GEN7_MI_NOOP_IdentificationNumber_start 0 +#define GEN6_MI_NOOP_IdentificationNumber_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_NOOP_IdentificationNumber_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_NOOP::Identification Number Register Write Enable */ + + +#define GEN11_MI_NOOP_IdentificationNumberRegisterWriteEnable_bits 1 +#define GEN10_MI_NOOP_IdentificationNumberRegisterWriteEnable_bits 1 +#define GEN9_MI_NOOP_IdentificationNumberRegisterWriteEnable_bits 1 +#define GEN8_MI_NOOP_IdentificationNumberRegisterWriteEnable_bits 1 +#define GEN75_MI_NOOP_IdentificationNumberRegisterWriteEnable_bits 1 +#define GEN7_MI_NOOP_IdentificationNumberRegisterWriteEnable_bits 1 +#define GEN6_MI_NOOP_IdentificationNumberRegisterWriteEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_NOOP_IdentificationNumberRegisterWriteEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_NOOP_IdentificationNumberRegisterWriteEnable_start 22 +#define GEN10_MI_NOOP_IdentificationNumberRegisterWriteEnable_start 22 +#define GEN9_MI_NOOP_IdentificationNumberRegisterWriteEnable_start 22 +#define GEN8_MI_NOOP_IdentificationNumberRegisterWriteEnable_start 22 +#define GEN75_MI_NOOP_IdentificationNumberRegisterWriteEnable_start 22 +#define GEN7_MI_NOOP_IdentificationNumberRegisterWriteEnable_start 22 +#define GEN6_MI_NOOP_IdentificationNumberRegisterWriteEnable_start 22 + +static inline uint32_t ATTRIBUTE_PURE +MI_NOOP_IdentificationNumberRegisterWriteEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 22; + case 10: return 22; + case 9: return 22; + case 8: return 22; + case 7: + if (devinfo->is_haswell) { + return 22; + } else { + return 22; + } + case 6: return 22; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_NOOP::MI Command Opcode */ + + +#define GEN11_MI_NOOP_MICommandOpcode_bits 6 +#define GEN10_MI_NOOP_MICommandOpcode_bits 6 +#define GEN9_MI_NOOP_MICommandOpcode_bits 6 +#define GEN8_MI_NOOP_MICommandOpcode_bits 6 +#define GEN75_MI_NOOP_MICommandOpcode_bits 6 +#define GEN7_MI_NOOP_MICommandOpcode_bits 6 +#define GEN6_MI_NOOP_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_NOOP_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 6; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_NOOP_MICommandOpcode_start 23 +#define GEN10_MI_NOOP_MICommandOpcode_start 23 +#define GEN9_MI_NOOP_MICommandOpcode_start 23 +#define GEN8_MI_NOOP_MICommandOpcode_start 23 +#define GEN75_MI_NOOP_MICommandOpcode_start 23 +#define GEN7_MI_NOOP_MICommandOpcode_start 23 +#define GEN6_MI_NOOP_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_NOOP_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 23; + } else { + return 23; + } + case 6: return 23; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_PREDICATE */ + + +#define GEN11_MI_PREDICATE_length 1 +#define GEN10_MI_PREDICATE_length 1 +#define GEN9_MI_PREDICATE_length 1 +#define GEN8_MI_PREDICATE_length 1 +#define GEN75_MI_PREDICATE_length 1 +#define GEN7_MI_PREDICATE_length 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_PREDICATE_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_PREDICATE::Combine Operation */ + + +#define GEN11_MI_PREDICATE_CombineOperation_bits 2 +#define GEN10_MI_PREDICATE_CombineOperation_bits 2 +#define GEN9_MI_PREDICATE_CombineOperation_bits 2 +#define GEN8_MI_PREDICATE_CombineOperation_bits 2 +#define GEN75_MI_PREDICATE_CombineOperation_bits 2 +#define GEN7_MI_PREDICATE_CombineOperation_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +MI_PREDICATE_CombineOperation_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_PREDICATE_CombineOperation_start 3 +#define GEN10_MI_PREDICATE_CombineOperation_start 3 +#define GEN9_MI_PREDICATE_CombineOperation_start 3 +#define GEN8_MI_PREDICATE_CombineOperation_start 3 +#define GEN75_MI_PREDICATE_CombineOperation_start 3 +#define GEN7_MI_PREDICATE_CombineOperation_start 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_PREDICATE_CombineOperation_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_PREDICATE::Command Type */ + + +#define GEN11_MI_PREDICATE_CommandType_bits 3 +#define GEN10_MI_PREDICATE_CommandType_bits 3 +#define GEN9_MI_PREDICATE_CommandType_bits 3 +#define GEN8_MI_PREDICATE_CommandType_bits 3 +#define GEN75_MI_PREDICATE_CommandType_bits 3 +#define GEN7_MI_PREDICATE_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_PREDICATE_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_PREDICATE_CommandType_start 29 +#define GEN10_MI_PREDICATE_CommandType_start 29 +#define GEN9_MI_PREDICATE_CommandType_start 29 +#define GEN8_MI_PREDICATE_CommandType_start 29 +#define GEN75_MI_PREDICATE_CommandType_start 29 +#define GEN7_MI_PREDICATE_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_PREDICATE_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_PREDICATE::Compare Operation */ + + +#define GEN11_MI_PREDICATE_CompareOperation_bits 2 +#define GEN10_MI_PREDICATE_CompareOperation_bits 2 +#define GEN9_MI_PREDICATE_CompareOperation_bits 2 +#define GEN8_MI_PREDICATE_CompareOperation_bits 2 +#define GEN75_MI_PREDICATE_CompareOperation_bits 2 +#define GEN7_MI_PREDICATE_CompareOperation_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +MI_PREDICATE_CompareOperation_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_PREDICATE_CompareOperation_start 0 +#define GEN10_MI_PREDICATE_CompareOperation_start 0 +#define GEN9_MI_PREDICATE_CompareOperation_start 0 +#define GEN8_MI_PREDICATE_CompareOperation_start 0 +#define GEN75_MI_PREDICATE_CompareOperation_start 0 +#define GEN7_MI_PREDICATE_CompareOperation_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_PREDICATE_CompareOperation_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_PREDICATE::Load Operation */ + + +#define GEN11_MI_PREDICATE_LoadOperation_bits 2 +#define GEN10_MI_PREDICATE_LoadOperation_bits 2 +#define GEN9_MI_PREDICATE_LoadOperation_bits 2 +#define GEN8_MI_PREDICATE_LoadOperation_bits 2 +#define GEN75_MI_PREDICATE_LoadOperation_bits 2 +#define GEN7_MI_PREDICATE_LoadOperation_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +MI_PREDICATE_LoadOperation_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_PREDICATE_LoadOperation_start 6 +#define GEN10_MI_PREDICATE_LoadOperation_start 6 +#define GEN9_MI_PREDICATE_LoadOperation_start 6 +#define GEN8_MI_PREDICATE_LoadOperation_start 6 +#define GEN75_MI_PREDICATE_LoadOperation_start 6 +#define GEN7_MI_PREDICATE_LoadOperation_start 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_PREDICATE_LoadOperation_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_PREDICATE::MI Command Opcode */ + + +#define GEN11_MI_PREDICATE_MICommandOpcode_bits 6 +#define GEN10_MI_PREDICATE_MICommandOpcode_bits 6 +#define GEN9_MI_PREDICATE_MICommandOpcode_bits 6 +#define GEN8_MI_PREDICATE_MICommandOpcode_bits 6 +#define GEN75_MI_PREDICATE_MICommandOpcode_bits 6 +#define GEN7_MI_PREDICATE_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_PREDICATE_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_PREDICATE_MICommandOpcode_start 23 +#define GEN10_MI_PREDICATE_MICommandOpcode_start 23 +#define GEN9_MI_PREDICATE_MICommandOpcode_start 23 +#define GEN8_MI_PREDICATE_MICommandOpcode_start 23 +#define GEN75_MI_PREDICATE_MICommandOpcode_start 23 +#define GEN7_MI_PREDICATE_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_PREDICATE_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 23; + } else { + return 23; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_REPORT_HEAD */ + + +#define GEN11_MI_REPORT_HEAD_length 1 +#define GEN10_MI_REPORT_HEAD_length 1 +#define GEN9_MI_REPORT_HEAD_length 1 +#define GEN8_MI_REPORT_HEAD_length 1 +#define GEN75_MI_REPORT_HEAD_length 1 +#define GEN7_MI_REPORT_HEAD_length 1 +#define GEN6_MI_REPORT_HEAD_length 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_REPORT_HEAD_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_REPORT_HEAD::Command Type */ + + +#define GEN11_MI_REPORT_HEAD_CommandType_bits 3 +#define GEN10_MI_REPORT_HEAD_CommandType_bits 3 +#define GEN9_MI_REPORT_HEAD_CommandType_bits 3 +#define GEN8_MI_REPORT_HEAD_CommandType_bits 3 +#define GEN75_MI_REPORT_HEAD_CommandType_bits 3 +#define GEN7_MI_REPORT_HEAD_CommandType_bits 3 +#define GEN6_MI_REPORT_HEAD_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_REPORT_HEAD_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_REPORT_HEAD_CommandType_start 29 +#define GEN10_MI_REPORT_HEAD_CommandType_start 29 +#define GEN9_MI_REPORT_HEAD_CommandType_start 29 +#define GEN8_MI_REPORT_HEAD_CommandType_start 29 +#define GEN75_MI_REPORT_HEAD_CommandType_start 29 +#define GEN7_MI_REPORT_HEAD_CommandType_start 29 +#define GEN6_MI_REPORT_HEAD_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_REPORT_HEAD_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_REPORT_HEAD::MI Command Opcode */ + + +#define GEN11_MI_REPORT_HEAD_MICommandOpcode_bits 6 +#define GEN10_MI_REPORT_HEAD_MICommandOpcode_bits 6 +#define GEN9_MI_REPORT_HEAD_MICommandOpcode_bits 6 +#define GEN8_MI_REPORT_HEAD_MICommandOpcode_bits 6 +#define GEN75_MI_REPORT_HEAD_MICommandOpcode_bits 6 +#define GEN7_MI_REPORT_HEAD_MICommandOpcode_bits 6 +#define GEN6_MI_REPORT_HEAD_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_REPORT_HEAD_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 6; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_REPORT_HEAD_MICommandOpcode_start 23 +#define GEN10_MI_REPORT_HEAD_MICommandOpcode_start 23 +#define GEN9_MI_REPORT_HEAD_MICommandOpcode_start 23 +#define GEN8_MI_REPORT_HEAD_MICommandOpcode_start 23 +#define GEN75_MI_REPORT_HEAD_MICommandOpcode_start 23 +#define GEN7_MI_REPORT_HEAD_MICommandOpcode_start 23 +#define GEN6_MI_REPORT_HEAD_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_REPORT_HEAD_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 23; + } else { + return 23; + } + case 6: return 23; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_REPORT_PERF_COUNT */ + + +#define GEN11_MI_REPORT_PERF_COUNT_length 4 +#define GEN10_MI_REPORT_PERF_COUNT_length 4 +#define GEN9_MI_REPORT_PERF_COUNT_length 4 +#define GEN8_MI_REPORT_PERF_COUNT_length 4 +#define GEN75_MI_REPORT_PERF_COUNT_length 3 +#define GEN7_MI_REPORT_PERF_COUNT_length 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_REPORT_PERF_COUNT_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_REPORT_PERF_COUNT::Command Type */ + + +#define GEN11_MI_REPORT_PERF_COUNT_CommandType_bits 3 +#define GEN10_MI_REPORT_PERF_COUNT_CommandType_bits 3 +#define GEN9_MI_REPORT_PERF_COUNT_CommandType_bits 3 +#define GEN8_MI_REPORT_PERF_COUNT_CommandType_bits 3 +#define GEN75_MI_REPORT_PERF_COUNT_CommandType_bits 3 +#define GEN7_MI_REPORT_PERF_COUNT_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_REPORT_PERF_COUNT_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_REPORT_PERF_COUNT_CommandType_start 29 +#define GEN10_MI_REPORT_PERF_COUNT_CommandType_start 29 +#define GEN9_MI_REPORT_PERF_COUNT_CommandType_start 29 +#define GEN8_MI_REPORT_PERF_COUNT_CommandType_start 29 +#define GEN75_MI_REPORT_PERF_COUNT_CommandType_start 29 +#define GEN7_MI_REPORT_PERF_COUNT_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_REPORT_PERF_COUNT_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_REPORT_PERF_COUNT::Core Mode Enable */ + + +#define GEN11_MI_REPORT_PERF_COUNT_CoreModeEnable_bits 1 +#define GEN10_MI_REPORT_PERF_COUNT_CoreModeEnable_bits 1 +#define GEN9_MI_REPORT_PERF_COUNT_CoreModeEnable_bits 1 +#define GEN8_MI_REPORT_PERF_COUNT_CoreModeEnable_bits 1 +#define GEN75_MI_REPORT_PERF_COUNT_CoreModeEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_REPORT_PERF_COUNT_CoreModeEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_REPORT_PERF_COUNT_CoreModeEnable_start 36 +#define GEN10_MI_REPORT_PERF_COUNT_CoreModeEnable_start 36 +#define GEN9_MI_REPORT_PERF_COUNT_CoreModeEnable_start 36 +#define GEN8_MI_REPORT_PERF_COUNT_CoreModeEnable_start 36 +#define GEN75_MI_REPORT_PERF_COUNT_CoreModeEnable_start 36 + +static inline uint32_t ATTRIBUTE_PURE +MI_REPORT_PERF_COUNT_CoreModeEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 36; + case 10: return 36; + case 9: return 36; + case 8: return 36; + case 7: + if (devinfo->is_haswell) { + return 36; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_REPORT_PERF_COUNT::DWord Length */ + + +#define GEN11_MI_REPORT_PERF_COUNT_DWordLength_bits 6 +#define GEN10_MI_REPORT_PERF_COUNT_DWordLength_bits 6 +#define GEN9_MI_REPORT_PERF_COUNT_DWordLength_bits 6 +#define GEN8_MI_REPORT_PERF_COUNT_DWordLength_bits 6 +#define GEN75_MI_REPORT_PERF_COUNT_DWordLength_bits 6 +#define GEN7_MI_REPORT_PERF_COUNT_DWordLength_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_REPORT_PERF_COUNT_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_REPORT_PERF_COUNT_DWordLength_start 0 +#define GEN10_MI_REPORT_PERF_COUNT_DWordLength_start 0 +#define GEN9_MI_REPORT_PERF_COUNT_DWordLength_start 0 +#define GEN8_MI_REPORT_PERF_COUNT_DWordLength_start 0 +#define GEN75_MI_REPORT_PERF_COUNT_DWordLength_start 0 +#define GEN7_MI_REPORT_PERF_COUNT_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_REPORT_PERF_COUNT_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_REPORT_PERF_COUNT::MI Command Opcode */ + + +#define GEN11_MI_REPORT_PERF_COUNT_MICommandOpcode_bits 6 +#define GEN10_MI_REPORT_PERF_COUNT_MICommandOpcode_bits 6 +#define GEN9_MI_REPORT_PERF_COUNT_MICommandOpcode_bits 6 +#define GEN8_MI_REPORT_PERF_COUNT_MICommandOpcode_bits 6 +#define GEN75_MI_REPORT_PERF_COUNT_MICommandOpcode_bits 6 +#define GEN7_MI_REPORT_PERF_COUNT_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_REPORT_PERF_COUNT_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_REPORT_PERF_COUNT_MICommandOpcode_start 23 +#define GEN10_MI_REPORT_PERF_COUNT_MICommandOpcode_start 23 +#define GEN9_MI_REPORT_PERF_COUNT_MICommandOpcode_start 23 +#define GEN8_MI_REPORT_PERF_COUNT_MICommandOpcode_start 23 +#define GEN75_MI_REPORT_PERF_COUNT_MICommandOpcode_start 23 +#define GEN7_MI_REPORT_PERF_COUNT_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_REPORT_PERF_COUNT_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 23; + } else { + return 23; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_REPORT_PERF_COUNT::Memory Address */ + + +#define GEN11_MI_REPORT_PERF_COUNT_MemoryAddress_bits 58 +#define GEN10_MI_REPORT_PERF_COUNT_MemoryAddress_bits 58 +#define GEN9_MI_REPORT_PERF_COUNT_MemoryAddress_bits 58 +#define GEN8_MI_REPORT_PERF_COUNT_MemoryAddress_bits 58 +#define GEN75_MI_REPORT_PERF_COUNT_MemoryAddress_bits 26 +#define GEN7_MI_REPORT_PERF_COUNT_MemoryAddress_bits 26 + +static inline uint32_t ATTRIBUTE_PURE +MI_REPORT_PERF_COUNT_MemoryAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 58; + case 10: return 58; + case 9: return 58; + case 8: return 58; + case 7: + if (devinfo->is_haswell) { + return 26; + } else { + return 26; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_REPORT_PERF_COUNT_MemoryAddress_start 38 +#define GEN10_MI_REPORT_PERF_COUNT_MemoryAddress_start 38 +#define GEN9_MI_REPORT_PERF_COUNT_MemoryAddress_start 38 +#define GEN8_MI_REPORT_PERF_COUNT_MemoryAddress_start 38 +#define GEN75_MI_REPORT_PERF_COUNT_MemoryAddress_start 38 +#define GEN7_MI_REPORT_PERF_COUNT_MemoryAddress_start 38 + +static inline uint32_t ATTRIBUTE_PURE +MI_REPORT_PERF_COUNT_MemoryAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 38; + case 10: return 38; + case 9: return 38; + case 8: return 38; + case 7: + if (devinfo->is_haswell) { + return 38; + } else { + return 38; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_REPORT_PERF_COUNT::Report ID */ + + +#define GEN11_MI_REPORT_PERF_COUNT_ReportID_bits 32 +#define GEN10_MI_REPORT_PERF_COUNT_ReportID_bits 32 +#define GEN9_MI_REPORT_PERF_COUNT_ReportID_bits 32 +#define GEN8_MI_REPORT_PERF_COUNT_ReportID_bits 32 +#define GEN75_MI_REPORT_PERF_COUNT_ReportID_bits 32 +#define GEN7_MI_REPORT_PERF_COUNT_ReportID_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +MI_REPORT_PERF_COUNT_ReportID_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_REPORT_PERF_COUNT_ReportID_start 96 +#define GEN10_MI_REPORT_PERF_COUNT_ReportID_start 96 +#define GEN9_MI_REPORT_PERF_COUNT_ReportID_start 96 +#define GEN8_MI_REPORT_PERF_COUNT_ReportID_start 96 +#define GEN75_MI_REPORT_PERF_COUNT_ReportID_start 64 +#define GEN7_MI_REPORT_PERF_COUNT_ReportID_start 64 + +static inline uint32_t ATTRIBUTE_PURE +MI_REPORT_PERF_COUNT_ReportID_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 96; + case 10: return 96; + case 9: return 96; + case 8: return 96; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_REPORT_PERF_COUNT::Use Global GTT */ + + +#define GEN11_MI_REPORT_PERF_COUNT_UseGlobalGTT_bits 1 +#define GEN10_MI_REPORT_PERF_COUNT_UseGlobalGTT_bits 1 +#define GEN9_MI_REPORT_PERF_COUNT_UseGlobalGTT_bits 1 +#define GEN8_MI_REPORT_PERF_COUNT_UseGlobalGTT_bits 1 +#define GEN75_MI_REPORT_PERF_COUNT_UseGlobalGTT_bits 1 +#define GEN7_MI_REPORT_PERF_COUNT_UseGlobalGTT_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_REPORT_PERF_COUNT_UseGlobalGTT_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_REPORT_PERF_COUNT_UseGlobalGTT_start 32 +#define GEN10_MI_REPORT_PERF_COUNT_UseGlobalGTT_start 32 +#define GEN9_MI_REPORT_PERF_COUNT_UseGlobalGTT_start 32 +#define GEN8_MI_REPORT_PERF_COUNT_UseGlobalGTT_start 32 +#define GEN75_MI_REPORT_PERF_COUNT_UseGlobalGTT_start 32 +#define GEN7_MI_REPORT_PERF_COUNT_UseGlobalGTT_start 32 + +static inline uint32_t ATTRIBUTE_PURE +MI_REPORT_PERF_COUNT_UseGlobalGTT_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_RS_CONTEXT */ + + +#define GEN11_MI_RS_CONTEXT_length 1 +#define GEN10_MI_RS_CONTEXT_length 1 +#define GEN9_MI_RS_CONTEXT_length 1 +#define GEN8_MI_RS_CONTEXT_length 1 +#define GEN75_MI_RS_CONTEXT_length 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_RS_CONTEXT_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_RS_CONTEXT::Command Type */ + + +#define GEN11_MI_RS_CONTEXT_CommandType_bits 3 +#define GEN10_MI_RS_CONTEXT_CommandType_bits 3 +#define GEN9_MI_RS_CONTEXT_CommandType_bits 3 +#define GEN8_MI_RS_CONTEXT_CommandType_bits 3 +#define GEN75_MI_RS_CONTEXT_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_RS_CONTEXT_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_RS_CONTEXT_CommandType_start 29 +#define GEN10_MI_RS_CONTEXT_CommandType_start 29 +#define GEN9_MI_RS_CONTEXT_CommandType_start 29 +#define GEN8_MI_RS_CONTEXT_CommandType_start 29 +#define GEN75_MI_RS_CONTEXT_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_RS_CONTEXT_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_RS_CONTEXT::MI Command Opcode */ + + +#define GEN11_MI_RS_CONTEXT_MICommandOpcode_bits 6 +#define GEN10_MI_RS_CONTEXT_MICommandOpcode_bits 6 +#define GEN9_MI_RS_CONTEXT_MICommandOpcode_bits 6 +#define GEN8_MI_RS_CONTEXT_MICommandOpcode_bits 6 +#define GEN75_MI_RS_CONTEXT_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_RS_CONTEXT_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_RS_CONTEXT_MICommandOpcode_start 23 +#define GEN10_MI_RS_CONTEXT_MICommandOpcode_start 23 +#define GEN9_MI_RS_CONTEXT_MICommandOpcode_start 23 +#define GEN8_MI_RS_CONTEXT_MICommandOpcode_start 23 +#define GEN75_MI_RS_CONTEXT_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_RS_CONTEXT_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 23; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_RS_CONTEXT::Resource Streamer Save */ + + +#define GEN11_MI_RS_CONTEXT_ResourceStreamerSave_bits 1 +#define GEN10_MI_RS_CONTEXT_ResourceStreamerSave_bits 1 +#define GEN9_MI_RS_CONTEXT_ResourceStreamerSave_bits 1 +#define GEN8_MI_RS_CONTEXT_ResourceStreamerSave_bits 1 +#define GEN75_MI_RS_CONTEXT_ResourceStreamerSave_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_RS_CONTEXT_ResourceStreamerSave_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_RS_CONTEXT_ResourceStreamerSave_start 0 +#define GEN10_MI_RS_CONTEXT_ResourceStreamerSave_start 0 +#define GEN9_MI_RS_CONTEXT_ResourceStreamerSave_start 0 +#define GEN8_MI_RS_CONTEXT_ResourceStreamerSave_start 0 +#define GEN75_MI_RS_CONTEXT_ResourceStreamerSave_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_RS_CONTEXT_ResourceStreamerSave_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_RS_CONTROL */ + + +#define GEN11_MI_RS_CONTROL_length 1 +#define GEN10_MI_RS_CONTROL_length 1 +#define GEN9_MI_RS_CONTROL_length 1 +#define GEN8_MI_RS_CONTROL_length 1 +#define GEN75_MI_RS_CONTROL_length 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_RS_CONTROL_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_RS_CONTROL::Command Type */ + + +#define GEN11_MI_RS_CONTROL_CommandType_bits 3 +#define GEN10_MI_RS_CONTROL_CommandType_bits 3 +#define GEN9_MI_RS_CONTROL_CommandType_bits 3 +#define GEN8_MI_RS_CONTROL_CommandType_bits 3 +#define GEN75_MI_RS_CONTROL_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_RS_CONTROL_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_RS_CONTROL_CommandType_start 29 +#define GEN10_MI_RS_CONTROL_CommandType_start 29 +#define GEN9_MI_RS_CONTROL_CommandType_start 29 +#define GEN8_MI_RS_CONTROL_CommandType_start 29 +#define GEN75_MI_RS_CONTROL_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_RS_CONTROL_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_RS_CONTROL::MI Command Opcode */ + + +#define GEN11_MI_RS_CONTROL_MICommandOpcode_bits 6 +#define GEN10_MI_RS_CONTROL_MICommandOpcode_bits 6 +#define GEN9_MI_RS_CONTROL_MICommandOpcode_bits 6 +#define GEN8_MI_RS_CONTROL_MICommandOpcode_bits 6 +#define GEN75_MI_RS_CONTROL_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_RS_CONTROL_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_RS_CONTROL_MICommandOpcode_start 23 +#define GEN10_MI_RS_CONTROL_MICommandOpcode_start 23 +#define GEN9_MI_RS_CONTROL_MICommandOpcode_start 23 +#define GEN8_MI_RS_CONTROL_MICommandOpcode_start 23 +#define GEN75_MI_RS_CONTROL_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_RS_CONTROL_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 23; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_RS_CONTROL::Resource Streamer Control */ + + +#define GEN11_MI_RS_CONTROL_ResourceStreamerControl_bits 1 +#define GEN10_MI_RS_CONTROL_ResourceStreamerControl_bits 1 +#define GEN9_MI_RS_CONTROL_ResourceStreamerControl_bits 1 +#define GEN8_MI_RS_CONTROL_ResourceStreamerControl_bits 1 +#define GEN75_MI_RS_CONTROL_ResourceStreamerControl_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_RS_CONTROL_ResourceStreamerControl_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_RS_CONTROL_ResourceStreamerControl_start 0 +#define GEN10_MI_RS_CONTROL_ResourceStreamerControl_start 0 +#define GEN9_MI_RS_CONTROL_ResourceStreamerControl_start 0 +#define GEN8_MI_RS_CONTROL_ResourceStreamerControl_start 0 +#define GEN75_MI_RS_CONTROL_ResourceStreamerControl_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_RS_CONTROL_ResourceStreamerControl_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_RS_STORE_DATA_IMM */ + + +#define GEN11_MI_RS_STORE_DATA_IMM_length 4 +#define GEN10_MI_RS_STORE_DATA_IMM_length 4 +#define GEN9_MI_RS_STORE_DATA_IMM_length 4 +#define GEN8_MI_RS_STORE_DATA_IMM_length 4 +#define GEN75_MI_RS_STORE_DATA_IMM_length 4 + +static inline uint32_t ATTRIBUTE_PURE +MI_RS_STORE_DATA_IMM_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_RS_STORE_DATA_IMM::Command Type */ + + +#define GEN11_MI_RS_STORE_DATA_IMM_CommandType_bits 3 +#define GEN10_MI_RS_STORE_DATA_IMM_CommandType_bits 3 +#define GEN9_MI_RS_STORE_DATA_IMM_CommandType_bits 3 +#define GEN8_MI_RS_STORE_DATA_IMM_CommandType_bits 3 +#define GEN75_MI_RS_STORE_DATA_IMM_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_RS_STORE_DATA_IMM_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_RS_STORE_DATA_IMM_CommandType_start 29 +#define GEN10_MI_RS_STORE_DATA_IMM_CommandType_start 29 +#define GEN9_MI_RS_STORE_DATA_IMM_CommandType_start 29 +#define GEN8_MI_RS_STORE_DATA_IMM_CommandType_start 29 +#define GEN75_MI_RS_STORE_DATA_IMM_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_RS_STORE_DATA_IMM_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_RS_STORE_DATA_IMM::Core Mode Enable */ + + +#define GEN11_MI_RS_STORE_DATA_IMM_CoreModeEnable_bits 1 +#define GEN10_MI_RS_STORE_DATA_IMM_CoreModeEnable_bits 1 +#define GEN9_MI_RS_STORE_DATA_IMM_CoreModeEnable_bits 1 +#define GEN8_MI_RS_STORE_DATA_IMM_CoreModeEnable_bits 1 +#define GEN75_MI_RS_STORE_DATA_IMM_CoreModeEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_RS_STORE_DATA_IMM_CoreModeEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_RS_STORE_DATA_IMM_CoreModeEnable_start 32 +#define GEN10_MI_RS_STORE_DATA_IMM_CoreModeEnable_start 32 +#define GEN9_MI_RS_STORE_DATA_IMM_CoreModeEnable_start 32 +#define GEN8_MI_RS_STORE_DATA_IMM_CoreModeEnable_start 32 +#define GEN75_MI_RS_STORE_DATA_IMM_CoreModeEnable_start 64 + +static inline uint32_t ATTRIBUTE_PURE +MI_RS_STORE_DATA_IMM_CoreModeEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_RS_STORE_DATA_IMM::DWord Length */ + + +#define GEN11_MI_RS_STORE_DATA_IMM_DWordLength_bits 8 +#define GEN10_MI_RS_STORE_DATA_IMM_DWordLength_bits 8 +#define GEN9_MI_RS_STORE_DATA_IMM_DWordLength_bits 8 +#define GEN8_MI_RS_STORE_DATA_IMM_DWordLength_bits 8 +#define GEN75_MI_RS_STORE_DATA_IMM_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MI_RS_STORE_DATA_IMM_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_RS_STORE_DATA_IMM_DWordLength_start 0 +#define GEN10_MI_RS_STORE_DATA_IMM_DWordLength_start 0 +#define GEN9_MI_RS_STORE_DATA_IMM_DWordLength_start 0 +#define GEN8_MI_RS_STORE_DATA_IMM_DWordLength_start 0 +#define GEN75_MI_RS_STORE_DATA_IMM_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_RS_STORE_DATA_IMM_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_RS_STORE_DATA_IMM::Data DWord 0 */ + + +#define GEN11_MI_RS_STORE_DATA_IMM_DataDWord0_bits 32 +#define GEN10_MI_RS_STORE_DATA_IMM_DataDWord0_bits 32 +#define GEN9_MI_RS_STORE_DATA_IMM_DataDWord0_bits 32 +#define GEN8_MI_RS_STORE_DATA_IMM_DataDWord0_bits 32 +#define GEN75_MI_RS_STORE_DATA_IMM_DataDWord0_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +MI_RS_STORE_DATA_IMM_DataDWord0_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_RS_STORE_DATA_IMM_DataDWord0_start 96 +#define GEN10_MI_RS_STORE_DATA_IMM_DataDWord0_start 96 +#define GEN9_MI_RS_STORE_DATA_IMM_DataDWord0_start 96 +#define GEN8_MI_RS_STORE_DATA_IMM_DataDWord0_start 96 +#define GEN75_MI_RS_STORE_DATA_IMM_DataDWord0_start 96 + +static inline uint32_t ATTRIBUTE_PURE +MI_RS_STORE_DATA_IMM_DataDWord0_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 96; + case 10: return 96; + case 9: return 96; + case 8: return 96; + case 7: + if (devinfo->is_haswell) { + return 96; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_RS_STORE_DATA_IMM::Destination Address */ + + +#define GEN11_MI_RS_STORE_DATA_IMM_DestinationAddress_bits 62 +#define GEN10_MI_RS_STORE_DATA_IMM_DestinationAddress_bits 62 +#define GEN9_MI_RS_STORE_DATA_IMM_DestinationAddress_bits 62 +#define GEN8_MI_RS_STORE_DATA_IMM_DestinationAddress_bits 62 +#define GEN75_MI_RS_STORE_DATA_IMM_DestinationAddress_bits 30 + +static inline uint32_t ATTRIBUTE_PURE +MI_RS_STORE_DATA_IMM_DestinationAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 62; + case 10: return 62; + case 9: return 62; + case 8: return 62; + case 7: + if (devinfo->is_haswell) { + return 30; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_RS_STORE_DATA_IMM_DestinationAddress_start 34 +#define GEN10_MI_RS_STORE_DATA_IMM_DestinationAddress_start 34 +#define GEN9_MI_RS_STORE_DATA_IMM_DestinationAddress_start 34 +#define GEN8_MI_RS_STORE_DATA_IMM_DestinationAddress_start 34 +#define GEN75_MI_RS_STORE_DATA_IMM_DestinationAddress_start 66 + +static inline uint32_t ATTRIBUTE_PURE +MI_RS_STORE_DATA_IMM_DestinationAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 34; + case 10: return 34; + case 9: return 34; + case 8: return 34; + case 7: + if (devinfo->is_haswell) { + return 66; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_RS_STORE_DATA_IMM::MI Command Opcode */ + + +#define GEN11_MI_RS_STORE_DATA_IMM_MICommandOpcode_bits 6 +#define GEN10_MI_RS_STORE_DATA_IMM_MICommandOpcode_bits 6 +#define GEN9_MI_RS_STORE_DATA_IMM_MICommandOpcode_bits 6 +#define GEN8_MI_RS_STORE_DATA_IMM_MICommandOpcode_bits 6 +#define GEN75_MI_RS_STORE_DATA_IMM_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_RS_STORE_DATA_IMM_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_RS_STORE_DATA_IMM_MICommandOpcode_start 23 +#define GEN10_MI_RS_STORE_DATA_IMM_MICommandOpcode_start 23 +#define GEN9_MI_RS_STORE_DATA_IMM_MICommandOpcode_start 23 +#define GEN8_MI_RS_STORE_DATA_IMM_MICommandOpcode_start 23 +#define GEN75_MI_RS_STORE_DATA_IMM_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_RS_STORE_DATA_IMM_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 23; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SEMAPHORE_MBOX */ + + +#define GEN75_MI_SEMAPHORE_MBOX_length 3 +#define GEN7_MI_SEMAPHORE_MBOX_length 3 +#define GEN6_MI_SEMAPHORE_MBOX_length 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_MBOX_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SEMAPHORE_MBOX::Command Type */ + + +#define GEN75_MI_SEMAPHORE_MBOX_CommandType_bits 3 +#define GEN7_MI_SEMAPHORE_MBOX_CommandType_bits 3 +#define GEN6_MI_SEMAPHORE_MBOX_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_MBOX_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_MI_SEMAPHORE_MBOX_CommandType_start 29 +#define GEN7_MI_SEMAPHORE_MBOX_CommandType_start 29 +#define GEN6_MI_SEMAPHORE_MBOX_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_MBOX_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SEMAPHORE_MBOX::DWord Length */ + + +#define GEN75_MI_SEMAPHORE_MBOX_DWordLength_bits 8 +#define GEN7_MI_SEMAPHORE_MBOX_DWordLength_bits 8 +#define GEN6_MI_SEMAPHORE_MBOX_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_MBOX_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_MI_SEMAPHORE_MBOX_DWordLength_start 0 +#define GEN7_MI_SEMAPHORE_MBOX_DWordLength_start 0 +#define GEN6_MI_SEMAPHORE_MBOX_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_MBOX_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SEMAPHORE_MBOX::General Register Select */ + + +#define GEN75_MI_SEMAPHORE_MBOX_GeneralRegisterSelect_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_MBOX_GeneralRegisterSelect_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_MI_SEMAPHORE_MBOX_GeneralRegisterSelect_start 8 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_MBOX_GeneralRegisterSelect_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SEMAPHORE_MBOX::MI Command Opcode */ + + +#define GEN75_MI_SEMAPHORE_MBOX_MICommandOpcode_bits 6 +#define GEN7_MI_SEMAPHORE_MBOX_MICommandOpcode_bits 6 +#define GEN6_MI_SEMAPHORE_MBOX_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_MBOX_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 6; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_MI_SEMAPHORE_MBOX_MICommandOpcode_start 23 +#define GEN7_MI_SEMAPHORE_MBOX_MICommandOpcode_start 23 +#define GEN6_MI_SEMAPHORE_MBOX_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_MBOX_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 23; + } else { + return 23; + } + case 6: return 23; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SEMAPHORE_MBOX::Register Select */ + + +#define GEN75_MI_SEMAPHORE_MBOX_RegisterSelect_bits 2 +#define GEN7_MI_SEMAPHORE_MBOX_RegisterSelect_bits 2 +#define GEN6_MI_SEMAPHORE_MBOX_RegisterSelect_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_MBOX_RegisterSelect_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_MI_SEMAPHORE_MBOX_RegisterSelect_start 16 +#define GEN7_MI_SEMAPHORE_MBOX_RegisterSelect_start 16 +#define GEN6_MI_SEMAPHORE_MBOX_RegisterSelect_start 16 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_MBOX_RegisterSelect_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SEMAPHORE_MBOX::Semaphore Data Dword */ + + +#define GEN75_MI_SEMAPHORE_MBOX_SemaphoreDataDword_bits 32 +#define GEN7_MI_SEMAPHORE_MBOX_SemaphoreDataDword_bits 32 +#define GEN6_MI_SEMAPHORE_MBOX_SemaphoreDataDword_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_MBOX_SemaphoreDataDword_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_MI_SEMAPHORE_MBOX_SemaphoreDataDword_start 32 +#define GEN7_MI_SEMAPHORE_MBOX_SemaphoreDataDword_start 32 +#define GEN6_MI_SEMAPHORE_MBOX_SemaphoreDataDword_start 32 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_MBOX_SemaphoreDataDword_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SEMAPHORE_SIGNAL */ + + +#define GEN11_MI_SEMAPHORE_SIGNAL_length 2 +#define GEN10_MI_SEMAPHORE_SIGNAL_length 2 +#define GEN9_MI_SEMAPHORE_SIGNAL_length 2 +#define GEN8_MI_SEMAPHORE_SIGNAL_length 2 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_SIGNAL_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SEMAPHORE_SIGNAL::Command Type */ + + +#define GEN11_MI_SEMAPHORE_SIGNAL_CommandType_bits 3 +#define GEN10_MI_SEMAPHORE_SIGNAL_CommandType_bits 3 +#define GEN9_MI_SEMAPHORE_SIGNAL_CommandType_bits 3 +#define GEN8_MI_SEMAPHORE_SIGNAL_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_SIGNAL_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_SEMAPHORE_SIGNAL_CommandType_start 29 +#define GEN10_MI_SEMAPHORE_SIGNAL_CommandType_start 29 +#define GEN9_MI_SEMAPHORE_SIGNAL_CommandType_start 29 +#define GEN8_MI_SEMAPHORE_SIGNAL_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_SIGNAL_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SEMAPHORE_SIGNAL::DWord Length */ + + +#define GEN11_MI_SEMAPHORE_SIGNAL_DWordLength_bits 8 +#define GEN10_MI_SEMAPHORE_SIGNAL_DWordLength_bits 8 +#define GEN9_MI_SEMAPHORE_SIGNAL_DWordLength_bits 8 +#define GEN8_MI_SEMAPHORE_SIGNAL_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_SIGNAL_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_SEMAPHORE_SIGNAL_DWordLength_start 0 +#define GEN10_MI_SEMAPHORE_SIGNAL_DWordLength_start 0 +#define GEN9_MI_SEMAPHORE_SIGNAL_DWordLength_start 0 +#define GEN8_MI_SEMAPHORE_SIGNAL_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_SIGNAL_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SEMAPHORE_SIGNAL::MI Command Opcode */ + + +#define GEN11_MI_SEMAPHORE_SIGNAL_MICommandOpcode_bits 6 +#define GEN10_MI_SEMAPHORE_SIGNAL_MICommandOpcode_bits 6 +#define GEN9_MI_SEMAPHORE_SIGNAL_MICommandOpcode_bits 6 +#define GEN8_MI_SEMAPHORE_SIGNAL_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_SIGNAL_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_SEMAPHORE_SIGNAL_MICommandOpcode_start 23 +#define GEN10_MI_SEMAPHORE_SIGNAL_MICommandOpcode_start 23 +#define GEN9_MI_SEMAPHORE_SIGNAL_MICommandOpcode_start 23 +#define GEN8_MI_SEMAPHORE_SIGNAL_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_SIGNAL_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SEMAPHORE_SIGNAL::Post-Sync Operation */ + + +#define GEN11_MI_SEMAPHORE_SIGNAL_PostSyncOperation_bits 1 +#define GEN10_MI_SEMAPHORE_SIGNAL_PostSyncOperation_bits 1 +#define GEN9_MI_SEMAPHORE_SIGNAL_PostSyncOperation_bits 1 +#define GEN8_MI_SEMAPHORE_SIGNAL_PostSyncOperation_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_SIGNAL_PostSyncOperation_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_SEMAPHORE_SIGNAL_PostSyncOperation_start 21 +#define GEN10_MI_SEMAPHORE_SIGNAL_PostSyncOperation_start 21 +#define GEN9_MI_SEMAPHORE_SIGNAL_PostSyncOperation_start 21 +#define GEN8_MI_SEMAPHORE_SIGNAL_PostSyncOperation_start 21 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_SIGNAL_PostSyncOperation_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 21; + case 10: return 21; + case 9: return 21; + case 8: return 21; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SEMAPHORE_SIGNAL::Target Context ID */ + + +#define GEN11_MI_SEMAPHORE_SIGNAL_TargetContextID_bits 32 +#define GEN10_MI_SEMAPHORE_SIGNAL_TargetContextID_bits 32 +#define GEN9_MI_SEMAPHORE_SIGNAL_TargetContextID_bits 32 +#define GEN8_MI_SEMAPHORE_SIGNAL_TargetContextID_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_SIGNAL_TargetContextID_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_SEMAPHORE_SIGNAL_TargetContextID_start 32 +#define GEN10_MI_SEMAPHORE_SIGNAL_TargetContextID_start 32 +#define GEN9_MI_SEMAPHORE_SIGNAL_TargetContextID_start 32 +#define GEN8_MI_SEMAPHORE_SIGNAL_TargetContextID_start 32 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_SIGNAL_TargetContextID_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SEMAPHORE_SIGNAL::Target Engine Select */ + + +#define GEN11_MI_SEMAPHORE_SIGNAL_TargetEngineSelect_bits 4 +#define GEN10_MI_SEMAPHORE_SIGNAL_TargetEngineSelect_bits 3 +#define GEN9_MI_SEMAPHORE_SIGNAL_TargetEngineSelect_bits 3 +#define GEN8_MI_SEMAPHORE_SIGNAL_TargetEngineSelect_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_SIGNAL_TargetEngineSelect_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_SEMAPHORE_SIGNAL_TargetEngineSelect_start 15 +#define GEN10_MI_SEMAPHORE_SIGNAL_TargetEngineSelect_start 15 +#define GEN9_MI_SEMAPHORE_SIGNAL_TargetEngineSelect_start 15 +#define GEN8_MI_SEMAPHORE_SIGNAL_TargetEngineSelect_start 15 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_SIGNAL_TargetEngineSelect_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 15; + case 10: return 15; + case 9: return 15; + case 8: return 15; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SEMAPHORE_WAIT */ + + +#define GEN11_MI_SEMAPHORE_WAIT_length 4 +#define GEN10_MI_SEMAPHORE_WAIT_length 4 +#define GEN9_MI_SEMAPHORE_WAIT_length 4 +#define GEN8_MI_SEMAPHORE_WAIT_length 4 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_WAIT_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SEMAPHORE_WAIT::Command Type */ + + +#define GEN11_MI_SEMAPHORE_WAIT_CommandType_bits 3 +#define GEN10_MI_SEMAPHORE_WAIT_CommandType_bits 3 +#define GEN9_MI_SEMAPHORE_WAIT_CommandType_bits 3 +#define GEN8_MI_SEMAPHORE_WAIT_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_WAIT_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_SEMAPHORE_WAIT_CommandType_start 29 +#define GEN10_MI_SEMAPHORE_WAIT_CommandType_start 29 +#define GEN9_MI_SEMAPHORE_WAIT_CommandType_start 29 +#define GEN8_MI_SEMAPHORE_WAIT_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_WAIT_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SEMAPHORE_WAIT::Compare Operation */ + + +#define GEN11_MI_SEMAPHORE_WAIT_CompareOperation_bits 3 +#define GEN10_MI_SEMAPHORE_WAIT_CompareOperation_bits 3 +#define GEN9_MI_SEMAPHORE_WAIT_CompareOperation_bits 3 +#define GEN8_MI_SEMAPHORE_WAIT_CompareOperation_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_WAIT_CompareOperation_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_SEMAPHORE_WAIT_CompareOperation_start 12 +#define GEN10_MI_SEMAPHORE_WAIT_CompareOperation_start 12 +#define GEN9_MI_SEMAPHORE_WAIT_CompareOperation_start 12 +#define GEN8_MI_SEMAPHORE_WAIT_CompareOperation_start 12 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_WAIT_CompareOperation_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 12; + case 10: return 12; + case 9: return 12; + case 8: return 12; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SEMAPHORE_WAIT::DWord Length */ + + +#define GEN11_MI_SEMAPHORE_WAIT_DWordLength_bits 8 +#define GEN10_MI_SEMAPHORE_WAIT_DWordLength_bits 8 +#define GEN9_MI_SEMAPHORE_WAIT_DWordLength_bits 8 +#define GEN8_MI_SEMAPHORE_WAIT_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_WAIT_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_SEMAPHORE_WAIT_DWordLength_start 0 +#define GEN10_MI_SEMAPHORE_WAIT_DWordLength_start 0 +#define GEN9_MI_SEMAPHORE_WAIT_DWordLength_start 0 +#define GEN8_MI_SEMAPHORE_WAIT_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_WAIT_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SEMAPHORE_WAIT::MI Command Opcode */ + + +#define GEN11_MI_SEMAPHORE_WAIT_MICommandOpcode_bits 6 +#define GEN10_MI_SEMAPHORE_WAIT_MICommandOpcode_bits 6 +#define GEN9_MI_SEMAPHORE_WAIT_MICommandOpcode_bits 6 +#define GEN8_MI_SEMAPHORE_WAIT_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_WAIT_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_SEMAPHORE_WAIT_MICommandOpcode_start 23 +#define GEN10_MI_SEMAPHORE_WAIT_MICommandOpcode_start 23 +#define GEN9_MI_SEMAPHORE_WAIT_MICommandOpcode_start 23 +#define GEN8_MI_SEMAPHORE_WAIT_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_WAIT_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SEMAPHORE_WAIT::Memory Type */ + + +#define GEN11_MI_SEMAPHORE_WAIT_MemoryType_bits 1 +#define GEN10_MI_SEMAPHORE_WAIT_MemoryType_bits 1 +#define GEN9_MI_SEMAPHORE_WAIT_MemoryType_bits 1 +#define GEN8_MI_SEMAPHORE_WAIT_MemoryType_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_WAIT_MemoryType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_SEMAPHORE_WAIT_MemoryType_start 22 +#define GEN10_MI_SEMAPHORE_WAIT_MemoryType_start 22 +#define GEN9_MI_SEMAPHORE_WAIT_MemoryType_start 22 +#define GEN8_MI_SEMAPHORE_WAIT_MemoryType_start 22 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_WAIT_MemoryType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 22; + case 10: return 22; + case 9: return 22; + case 8: return 22; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SEMAPHORE_WAIT::Register Poll Mode */ + + +#define GEN11_MI_SEMAPHORE_WAIT_RegisterPollMode_bits 1 +#define GEN10_MI_SEMAPHORE_WAIT_RegisterPollMode_bits 1 +#define GEN9_MI_SEMAPHORE_WAIT_RegisterPollMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_WAIT_RegisterPollMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_SEMAPHORE_WAIT_RegisterPollMode_start 16 +#define GEN10_MI_SEMAPHORE_WAIT_RegisterPollMode_start 16 +#define GEN9_MI_SEMAPHORE_WAIT_RegisterPollMode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_WAIT_RegisterPollMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SEMAPHORE_WAIT::Semaphore Address */ + + +#define GEN11_MI_SEMAPHORE_WAIT_SemaphoreAddress_bits 62 +#define GEN10_MI_SEMAPHORE_WAIT_SemaphoreAddress_bits 62 +#define GEN9_MI_SEMAPHORE_WAIT_SemaphoreAddress_bits 62 +#define GEN8_MI_SEMAPHORE_WAIT_SemaphoreAddress_bits 30 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_WAIT_SemaphoreAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 62; + case 10: return 62; + case 9: return 62; + case 8: return 30; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_SEMAPHORE_WAIT_SemaphoreAddress_start 66 +#define GEN10_MI_SEMAPHORE_WAIT_SemaphoreAddress_start 66 +#define GEN9_MI_SEMAPHORE_WAIT_SemaphoreAddress_start 66 +#define GEN8_MI_SEMAPHORE_WAIT_SemaphoreAddress_start 66 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_WAIT_SemaphoreAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 66; + case 10: return 66; + case 9: return 66; + case 8: return 66; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SEMAPHORE_WAIT::Semaphore Address High */ + + +#define GEN8_MI_SEMAPHORE_WAIT_SemaphoreAddressHigh_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_WAIT_SemaphoreAddressHigh_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_MI_SEMAPHORE_WAIT_SemaphoreAddressHigh_start 96 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_WAIT_SemaphoreAddressHigh_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 96; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SEMAPHORE_WAIT::Semaphore Data Dword */ + + +#define GEN11_MI_SEMAPHORE_WAIT_SemaphoreDataDword_bits 32 +#define GEN10_MI_SEMAPHORE_WAIT_SemaphoreDataDword_bits 32 +#define GEN9_MI_SEMAPHORE_WAIT_SemaphoreDataDword_bits 32 +#define GEN8_MI_SEMAPHORE_WAIT_SemaphoreDataDword_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_WAIT_SemaphoreDataDword_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_SEMAPHORE_WAIT_SemaphoreDataDword_start 32 +#define GEN10_MI_SEMAPHORE_WAIT_SemaphoreDataDword_start 32 +#define GEN9_MI_SEMAPHORE_WAIT_SemaphoreDataDword_start 32 +#define GEN8_MI_SEMAPHORE_WAIT_SemaphoreDataDword_start 32 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_WAIT_SemaphoreDataDword_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SEMAPHORE_WAIT::Wait Mode */ + + +#define GEN11_MI_SEMAPHORE_WAIT_WaitMode_bits 1 +#define GEN10_MI_SEMAPHORE_WAIT_WaitMode_bits 1 +#define GEN9_MI_SEMAPHORE_WAIT_WaitMode_bits 1 +#define GEN8_MI_SEMAPHORE_WAIT_WaitMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_WAIT_WaitMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_SEMAPHORE_WAIT_WaitMode_start 15 +#define GEN10_MI_SEMAPHORE_WAIT_WaitMode_start 15 +#define GEN9_MI_SEMAPHORE_WAIT_WaitMode_start 15 +#define GEN8_MI_SEMAPHORE_WAIT_WaitMode_start 15 + +static inline uint32_t ATTRIBUTE_PURE +MI_SEMAPHORE_WAIT_WaitMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 15; + case 10: return 15; + case 9: return 15; + case 8: return 15; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SET_CONTEXT */ + + +#define GEN11_MI_SET_CONTEXT_length 2 +#define GEN10_MI_SET_CONTEXT_length 2 +#define GEN9_MI_SET_CONTEXT_length 2 +#define GEN8_MI_SET_CONTEXT_length 2 +#define GEN75_MI_SET_CONTEXT_length 2 +#define GEN7_MI_SET_CONTEXT_length 2 +#define GEN6_MI_SET_CONTEXT_length 2 + +static inline uint32_t ATTRIBUTE_PURE +MI_SET_CONTEXT_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SET_CONTEXT::Command Type */ + + +#define GEN11_MI_SET_CONTEXT_CommandType_bits 3 +#define GEN10_MI_SET_CONTEXT_CommandType_bits 3 +#define GEN9_MI_SET_CONTEXT_CommandType_bits 3 +#define GEN8_MI_SET_CONTEXT_CommandType_bits 3 +#define GEN75_MI_SET_CONTEXT_CommandType_bits 3 +#define GEN7_MI_SET_CONTEXT_CommandType_bits 3 +#define GEN6_MI_SET_CONTEXT_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_SET_CONTEXT_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_SET_CONTEXT_CommandType_start 29 +#define GEN10_MI_SET_CONTEXT_CommandType_start 29 +#define GEN9_MI_SET_CONTEXT_CommandType_start 29 +#define GEN8_MI_SET_CONTEXT_CommandType_start 29 +#define GEN75_MI_SET_CONTEXT_CommandType_start 29 +#define GEN7_MI_SET_CONTEXT_CommandType_start 29 +#define GEN6_MI_SET_CONTEXT_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_SET_CONTEXT_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SET_CONTEXT::Core Mode Enable */ + + +#define GEN11_MI_SET_CONTEXT_CoreModeEnable_bits 1 +#define GEN10_MI_SET_CONTEXT_CoreModeEnable_bits 1 +#define GEN9_MI_SET_CONTEXT_CoreModeEnable_bits 1 +#define GEN8_MI_SET_CONTEXT_CoreModeEnable_bits 1 +#define GEN75_MI_SET_CONTEXT_CoreModeEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_SET_CONTEXT_CoreModeEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_SET_CONTEXT_CoreModeEnable_start 36 +#define GEN10_MI_SET_CONTEXT_CoreModeEnable_start 36 +#define GEN9_MI_SET_CONTEXT_CoreModeEnable_start 36 +#define GEN8_MI_SET_CONTEXT_CoreModeEnable_start 36 +#define GEN75_MI_SET_CONTEXT_CoreModeEnable_start 36 + +static inline uint32_t ATTRIBUTE_PURE +MI_SET_CONTEXT_CoreModeEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 36; + case 10: return 36; + case 9: return 36; + case 8: return 36; + case 7: + if (devinfo->is_haswell) { + return 36; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SET_CONTEXT::DWord Length */ + + +#define GEN11_MI_SET_CONTEXT_DWordLength_bits 8 +#define GEN10_MI_SET_CONTEXT_DWordLength_bits 8 +#define GEN9_MI_SET_CONTEXT_DWordLength_bits 8 +#define GEN8_MI_SET_CONTEXT_DWordLength_bits 8 +#define GEN75_MI_SET_CONTEXT_DWordLength_bits 8 +#define GEN7_MI_SET_CONTEXT_DWordLength_bits 8 +#define GEN6_MI_SET_CONTEXT_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MI_SET_CONTEXT_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_SET_CONTEXT_DWordLength_start 0 +#define GEN10_MI_SET_CONTEXT_DWordLength_start 0 +#define GEN9_MI_SET_CONTEXT_DWordLength_start 0 +#define GEN8_MI_SET_CONTEXT_DWordLength_start 0 +#define GEN75_MI_SET_CONTEXT_DWordLength_start 0 +#define GEN7_MI_SET_CONTEXT_DWordLength_start 0 +#define GEN6_MI_SET_CONTEXT_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_SET_CONTEXT_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SET_CONTEXT::Extended State Restore Enable */ + + +#define GEN7_MI_SET_CONTEXT_ExtendedStateRestoreEnable_bits 1 +#define GEN6_MI_SET_CONTEXT_ExtendedStateRestoreEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_SET_CONTEXT_ExtendedStateRestoreEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN7_MI_SET_CONTEXT_ExtendedStateRestoreEnable_start 34 +#define GEN6_MI_SET_CONTEXT_ExtendedStateRestoreEnable_start 34 + +static inline uint32_t ATTRIBUTE_PURE +MI_SET_CONTEXT_ExtendedStateRestoreEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 34; + } + case 6: return 34; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SET_CONTEXT::Extended State Save Enable */ + + +#define GEN7_MI_SET_CONTEXT_ExtendedStateSaveEnable_bits 1 +#define GEN6_MI_SET_CONTEXT_ExtendedStateSaveEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_SET_CONTEXT_ExtendedStateSaveEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN7_MI_SET_CONTEXT_ExtendedStateSaveEnable_start 35 +#define GEN6_MI_SET_CONTEXT_ExtendedStateSaveEnable_start 35 + +static inline uint32_t ATTRIBUTE_PURE +MI_SET_CONTEXT_ExtendedStateSaveEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 35; + } + case 6: return 35; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SET_CONTEXT::Force Restore */ + + +#define GEN11_MI_SET_CONTEXT_ForceRestore_bits 1 +#define GEN10_MI_SET_CONTEXT_ForceRestore_bits 1 +#define GEN9_MI_SET_CONTEXT_ForceRestore_bits 1 +#define GEN8_MI_SET_CONTEXT_ForceRestore_bits 1 +#define GEN75_MI_SET_CONTEXT_ForceRestore_bits 1 +#define GEN7_MI_SET_CONTEXT_ForceRestore_bits 1 +#define GEN6_MI_SET_CONTEXT_ForceRestore_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_SET_CONTEXT_ForceRestore_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_SET_CONTEXT_ForceRestore_start 33 +#define GEN10_MI_SET_CONTEXT_ForceRestore_start 33 +#define GEN9_MI_SET_CONTEXT_ForceRestore_start 33 +#define GEN8_MI_SET_CONTEXT_ForceRestore_start 33 +#define GEN75_MI_SET_CONTEXT_ForceRestore_start 33 +#define GEN7_MI_SET_CONTEXT_ForceRestore_start 33 +#define GEN6_MI_SET_CONTEXT_ForceRestore_start 33 + +static inline uint32_t ATTRIBUTE_PURE +MI_SET_CONTEXT_ForceRestore_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 33; + case 10: return 33; + case 9: return 33; + case 8: return 33; + case 7: + if (devinfo->is_haswell) { + return 33; + } else { + return 33; + } + case 6: return 33; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SET_CONTEXT::HD DVD Context */ + + +#define GEN6_MI_SET_CONTEXT_HDDVDContext_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_SET_CONTEXT_HDDVDContext_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_MI_SET_CONTEXT_HDDVDContext_start 41 + +static inline uint32_t ATTRIBUTE_PURE +MI_SET_CONTEXT_HDDVDContext_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 41; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SET_CONTEXT::Logical Context Address */ + + +#define GEN11_MI_SET_CONTEXT_LogicalContextAddress_bits 20 +#define GEN10_MI_SET_CONTEXT_LogicalContextAddress_bits 20 +#define GEN9_MI_SET_CONTEXT_LogicalContextAddress_bits 20 +#define GEN8_MI_SET_CONTEXT_LogicalContextAddress_bits 20 +#define GEN75_MI_SET_CONTEXT_LogicalContextAddress_bits 20 +#define GEN7_MI_SET_CONTEXT_LogicalContextAddress_bits 20 +#define GEN6_MI_SET_CONTEXT_LogicalContextAddress_bits 20 + +static inline uint32_t ATTRIBUTE_PURE +MI_SET_CONTEXT_LogicalContextAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 20; + case 10: return 20; + case 9: return 20; + case 8: return 20; + case 7: + if (devinfo->is_haswell) { + return 20; + } else { + return 20; + } + case 6: return 20; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_SET_CONTEXT_LogicalContextAddress_start 44 +#define GEN10_MI_SET_CONTEXT_LogicalContextAddress_start 44 +#define GEN9_MI_SET_CONTEXT_LogicalContextAddress_start 44 +#define GEN8_MI_SET_CONTEXT_LogicalContextAddress_start 44 +#define GEN75_MI_SET_CONTEXT_LogicalContextAddress_start 44 +#define GEN7_MI_SET_CONTEXT_LogicalContextAddress_start 44 +#define GEN6_MI_SET_CONTEXT_LogicalContextAddress_start 44 + +static inline uint32_t ATTRIBUTE_PURE +MI_SET_CONTEXT_LogicalContextAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 44; + case 10: return 44; + case 9: return 44; + case 8: return 44; + case 7: + if (devinfo->is_haswell) { + return 44; + } else { + return 44; + } + case 6: return 44; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SET_CONTEXT::MI Command Opcode */ + + +#define GEN11_MI_SET_CONTEXT_MICommandOpcode_bits 6 +#define GEN10_MI_SET_CONTEXT_MICommandOpcode_bits 6 +#define GEN9_MI_SET_CONTEXT_MICommandOpcode_bits 6 +#define GEN8_MI_SET_CONTEXT_MICommandOpcode_bits 6 +#define GEN75_MI_SET_CONTEXT_MICommandOpcode_bits 6 +#define GEN7_MI_SET_CONTEXT_MICommandOpcode_bits 6 +#define GEN6_MI_SET_CONTEXT_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_SET_CONTEXT_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 6; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_SET_CONTEXT_MICommandOpcode_start 23 +#define GEN10_MI_SET_CONTEXT_MICommandOpcode_start 23 +#define GEN9_MI_SET_CONTEXT_MICommandOpcode_start 23 +#define GEN8_MI_SET_CONTEXT_MICommandOpcode_start 23 +#define GEN75_MI_SET_CONTEXT_MICommandOpcode_start 23 +#define GEN7_MI_SET_CONTEXT_MICommandOpcode_start 23 +#define GEN6_MI_SET_CONTEXT_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_SET_CONTEXT_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 23; + } else { + return 23; + } + case 6: return 23; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SET_CONTEXT::Reserved, Must be 1 */ + + +#define GEN11_MI_SET_CONTEXT_ReservedMustbe1_bits 1 +#define GEN10_MI_SET_CONTEXT_ReservedMustbe1_bits 1 +#define GEN9_MI_SET_CONTEXT_ReservedMustbe1_bits 1 +#define GEN8_MI_SET_CONTEXT_ReservedMustbe1_bits 1 +#define GEN75_MI_SET_CONTEXT_ReservedMustbe1_bits 1 +#define GEN7_MI_SET_CONTEXT_ReservedMustbe1_bits 1 +#define GEN6_MI_SET_CONTEXT_ReservedMustbe1_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_SET_CONTEXT_ReservedMustbe1_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_SET_CONTEXT_ReservedMustbe1_start 40 +#define GEN10_MI_SET_CONTEXT_ReservedMustbe1_start 40 +#define GEN9_MI_SET_CONTEXT_ReservedMustbe1_start 40 +#define GEN8_MI_SET_CONTEXT_ReservedMustbe1_start 40 +#define GEN75_MI_SET_CONTEXT_ReservedMustbe1_start 40 +#define GEN7_MI_SET_CONTEXT_ReservedMustbe1_start 40 +#define GEN6_MI_SET_CONTEXT_ReservedMustbe1_start 40 + +static inline uint32_t ATTRIBUTE_PURE +MI_SET_CONTEXT_ReservedMustbe1_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 40; + case 10: return 40; + case 9: return 40; + case 8: return 40; + case 7: + if (devinfo->is_haswell) { + return 40; + } else { + return 40; + } + case 6: return 40; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SET_CONTEXT::Resource Streamer State Restore Enable */ + + +#define GEN11_MI_SET_CONTEXT_ResourceStreamerStateRestoreEnable_bits 1 +#define GEN10_MI_SET_CONTEXT_ResourceStreamerStateRestoreEnable_bits 1 +#define GEN9_MI_SET_CONTEXT_ResourceStreamerStateRestoreEnable_bits 1 +#define GEN8_MI_SET_CONTEXT_ResourceStreamerStateRestoreEnable_bits 1 +#define GEN75_MI_SET_CONTEXT_ResourceStreamerStateRestoreEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_SET_CONTEXT_ResourceStreamerStateRestoreEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_SET_CONTEXT_ResourceStreamerStateRestoreEnable_start 34 +#define GEN10_MI_SET_CONTEXT_ResourceStreamerStateRestoreEnable_start 34 +#define GEN9_MI_SET_CONTEXT_ResourceStreamerStateRestoreEnable_start 34 +#define GEN8_MI_SET_CONTEXT_ResourceStreamerStateRestoreEnable_start 34 +#define GEN75_MI_SET_CONTEXT_ResourceStreamerStateRestoreEnable_start 34 + +static inline uint32_t ATTRIBUTE_PURE +MI_SET_CONTEXT_ResourceStreamerStateRestoreEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 34; + case 10: return 34; + case 9: return 34; + case 8: return 34; + case 7: + if (devinfo->is_haswell) { + return 34; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SET_CONTEXT::Resource Streamer State Save Enable */ + + +#define GEN11_MI_SET_CONTEXT_ResourceStreamerStateSaveEnable_bits 1 +#define GEN10_MI_SET_CONTEXT_ResourceStreamerStateSaveEnable_bits 1 +#define GEN9_MI_SET_CONTEXT_ResourceStreamerStateSaveEnable_bits 1 +#define GEN8_MI_SET_CONTEXT_ResourceStreamerStateSaveEnable_bits 1 +#define GEN75_MI_SET_CONTEXT_ResourceStreamerStateSaveEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_SET_CONTEXT_ResourceStreamerStateSaveEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_SET_CONTEXT_ResourceStreamerStateSaveEnable_start 35 +#define GEN10_MI_SET_CONTEXT_ResourceStreamerStateSaveEnable_start 35 +#define GEN9_MI_SET_CONTEXT_ResourceStreamerStateSaveEnable_start 35 +#define GEN8_MI_SET_CONTEXT_ResourceStreamerStateSaveEnable_start 35 +#define GEN75_MI_SET_CONTEXT_ResourceStreamerStateSaveEnable_start 35 + +static inline uint32_t ATTRIBUTE_PURE +MI_SET_CONTEXT_ResourceStreamerStateSaveEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 35; + case 10: return 35; + case 9: return 35; + case 8: return 35; + case 7: + if (devinfo->is_haswell) { + return 35; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SET_CONTEXT::Restore Inhibit */ + + +#define GEN11_MI_SET_CONTEXT_RestoreInhibit_bits 1 +#define GEN10_MI_SET_CONTEXT_RestoreInhibit_bits 1 +#define GEN9_MI_SET_CONTEXT_RestoreInhibit_bits 1 +#define GEN8_MI_SET_CONTEXT_RestoreInhibit_bits 1 +#define GEN75_MI_SET_CONTEXT_RestoreInhibit_bits 1 +#define GEN7_MI_SET_CONTEXT_RestoreInhibit_bits 1 +#define GEN6_MI_SET_CONTEXT_RestoreInhibit_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_SET_CONTEXT_RestoreInhibit_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_SET_CONTEXT_RestoreInhibit_start 32 +#define GEN10_MI_SET_CONTEXT_RestoreInhibit_start 32 +#define GEN9_MI_SET_CONTEXT_RestoreInhibit_start 32 +#define GEN8_MI_SET_CONTEXT_RestoreInhibit_start 32 +#define GEN75_MI_SET_CONTEXT_RestoreInhibit_start 32 +#define GEN7_MI_SET_CONTEXT_RestoreInhibit_start 32 +#define GEN6_MI_SET_CONTEXT_RestoreInhibit_start 32 + +static inline uint32_t ATTRIBUTE_PURE +MI_SET_CONTEXT_RestoreInhibit_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SET_PREDICATE */ + + +#define GEN11_MI_SET_PREDICATE_length 1 +#define GEN10_MI_SET_PREDICATE_length 1 +#define GEN9_MI_SET_PREDICATE_length 1 +#define GEN8_MI_SET_PREDICATE_length 1 +#define GEN75_MI_SET_PREDICATE_length 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_SET_PREDICATE_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SET_PREDICATE::Command Type */ + + +#define GEN11_MI_SET_PREDICATE_CommandType_bits 3 +#define GEN10_MI_SET_PREDICATE_CommandType_bits 3 +#define GEN9_MI_SET_PREDICATE_CommandType_bits 3 +#define GEN8_MI_SET_PREDICATE_CommandType_bits 3 +#define GEN75_MI_SET_PREDICATE_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_SET_PREDICATE_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_SET_PREDICATE_CommandType_start 29 +#define GEN10_MI_SET_PREDICATE_CommandType_start 29 +#define GEN9_MI_SET_PREDICATE_CommandType_start 29 +#define GEN8_MI_SET_PREDICATE_CommandType_start 29 +#define GEN75_MI_SET_PREDICATE_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_SET_PREDICATE_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SET_PREDICATE::MI Command Opcode */ + + +#define GEN11_MI_SET_PREDICATE_MICommandOpcode_bits 6 +#define GEN10_MI_SET_PREDICATE_MICommandOpcode_bits 6 +#define GEN9_MI_SET_PREDICATE_MICommandOpcode_bits 6 +#define GEN8_MI_SET_PREDICATE_MICommandOpcode_bits 6 +#define GEN75_MI_SET_PREDICATE_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_SET_PREDICATE_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_SET_PREDICATE_MICommandOpcode_start 23 +#define GEN10_MI_SET_PREDICATE_MICommandOpcode_start 23 +#define GEN9_MI_SET_PREDICATE_MICommandOpcode_start 23 +#define GEN8_MI_SET_PREDICATE_MICommandOpcode_start 23 +#define GEN75_MI_SET_PREDICATE_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_SET_PREDICATE_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 23; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SET_PREDICATE::PREDICATE ENABLE */ + + +#define GEN11_MI_SET_PREDICATE_PREDICATEENABLE_bits 4 +#define GEN10_MI_SET_PREDICATE_PREDICATEENABLE_bits 4 +#define GEN9_MI_SET_PREDICATE_PREDICATEENABLE_bits 4 +#define GEN8_MI_SET_PREDICATE_PREDICATEENABLE_bits 4 +#define GEN75_MI_SET_PREDICATE_PREDICATEENABLE_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +MI_SET_PREDICATE_PREDICATEENABLE_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_SET_PREDICATE_PREDICATEENABLE_start 0 +#define GEN10_MI_SET_PREDICATE_PREDICATEENABLE_start 0 +#define GEN9_MI_SET_PREDICATE_PREDICATEENABLE_start 0 +#define GEN8_MI_SET_PREDICATE_PREDICATEENABLE_start 0 +#define GEN75_MI_SET_PREDICATE_PREDICATEENABLE_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_SET_PREDICATE_PREDICATEENABLE_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_STORE_DATA_IMM */ + + +#define GEN11_MI_STORE_DATA_IMM_length 4 +#define GEN10_MI_STORE_DATA_IMM_length 4 +#define GEN9_MI_STORE_DATA_IMM_length 4 +#define GEN8_MI_STORE_DATA_IMM_length 4 +#define GEN75_MI_STORE_DATA_IMM_length 4 +#define GEN7_MI_STORE_DATA_IMM_length 4 +#define GEN6_MI_STORE_DATA_IMM_length 4 +#define GEN5_MI_STORE_DATA_IMM_length 5 +#define GEN45_MI_STORE_DATA_IMM_length 5 +#define GEN4_MI_STORE_DATA_IMM_length 5 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_IMM_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 5; + case 4: + if (devinfo->is_g4x) { + return 5; + } else { + return 5; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_STORE_DATA_IMM::Address */ + + +#define GEN11_MI_STORE_DATA_IMM_Address_bits 46 +#define GEN10_MI_STORE_DATA_IMM_Address_bits 46 +#define GEN9_MI_STORE_DATA_IMM_Address_bits 46 +#define GEN8_MI_STORE_DATA_IMM_Address_bits 46 +#define GEN75_MI_STORE_DATA_IMM_Address_bits 30 +#define GEN7_MI_STORE_DATA_IMM_Address_bits 30 +#define GEN6_MI_STORE_DATA_IMM_Address_bits 30 +#define GEN5_MI_STORE_DATA_IMM_Address_bits 30 +#define GEN45_MI_STORE_DATA_IMM_Address_bits 30 +#define GEN4_MI_STORE_DATA_IMM_Address_bits 30 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_IMM_Address_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 46; + case 10: return 46; + case 9: return 46; + case 8: return 46; + case 7: + if (devinfo->is_haswell) { + return 30; + } else { + return 30; + } + case 6: return 30; + case 5: return 30; + case 4: + if (devinfo->is_g4x) { + return 30; + } else { + return 30; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_STORE_DATA_IMM_Address_start 34 +#define GEN10_MI_STORE_DATA_IMM_Address_start 34 +#define GEN9_MI_STORE_DATA_IMM_Address_start 34 +#define GEN8_MI_STORE_DATA_IMM_Address_start 34 +#define GEN75_MI_STORE_DATA_IMM_Address_start 66 +#define GEN7_MI_STORE_DATA_IMM_Address_start 66 +#define GEN6_MI_STORE_DATA_IMM_Address_start 66 +#define GEN5_MI_STORE_DATA_IMM_Address_start 66 +#define GEN45_MI_STORE_DATA_IMM_Address_start 66 +#define GEN4_MI_STORE_DATA_IMM_Address_start 66 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_IMM_Address_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 34; + case 10: return 34; + case 9: return 34; + case 8: return 34; + case 7: + if (devinfo->is_haswell) { + return 66; + } else { + return 66; + } + case 6: return 66; + case 5: return 66; + case 4: + if (devinfo->is_g4x) { + return 66; + } else { + return 66; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_STORE_DATA_IMM::BitFieldName */ + + +#define GEN45_MI_STORE_DATA_IMM_BitFieldName_bits 1 +#define GEN4_MI_STORE_DATA_IMM_BitFieldName_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_IMM_BitFieldName_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN45_MI_STORE_DATA_IMM_BitFieldName_start 21 +#define GEN4_MI_STORE_DATA_IMM_BitFieldName_start 21 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_IMM_BitFieldName_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 21; + } else { + return 21; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_STORE_DATA_IMM::Command Type */ + + +#define GEN11_MI_STORE_DATA_IMM_CommandType_bits 3 +#define GEN10_MI_STORE_DATA_IMM_CommandType_bits 3 +#define GEN9_MI_STORE_DATA_IMM_CommandType_bits 3 +#define GEN8_MI_STORE_DATA_IMM_CommandType_bits 3 +#define GEN75_MI_STORE_DATA_IMM_CommandType_bits 3 +#define GEN7_MI_STORE_DATA_IMM_CommandType_bits 3 +#define GEN6_MI_STORE_DATA_IMM_CommandType_bits 3 +#define GEN5_MI_STORE_DATA_IMM_CommandType_bits 3 +#define GEN45_MI_STORE_DATA_IMM_CommandType_bits 3 +#define GEN4_MI_STORE_DATA_IMM_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_IMM_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_STORE_DATA_IMM_CommandType_start 29 +#define GEN10_MI_STORE_DATA_IMM_CommandType_start 29 +#define GEN9_MI_STORE_DATA_IMM_CommandType_start 29 +#define GEN8_MI_STORE_DATA_IMM_CommandType_start 29 +#define GEN75_MI_STORE_DATA_IMM_CommandType_start 29 +#define GEN7_MI_STORE_DATA_IMM_CommandType_start 29 +#define GEN6_MI_STORE_DATA_IMM_CommandType_start 29 +#define GEN5_MI_STORE_DATA_IMM_CommandType_start 29 +#define GEN45_MI_STORE_DATA_IMM_CommandType_start 29 +#define GEN4_MI_STORE_DATA_IMM_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_IMM_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 29; + case 4: + if (devinfo->is_g4x) { + return 29; + } else { + return 29; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_STORE_DATA_IMM::Core Mode Enable */ + + +#define GEN11_MI_STORE_DATA_IMM_CoreModeEnable_bits 1 +#define GEN10_MI_STORE_DATA_IMM_CoreModeEnable_bits 1 +#define GEN9_MI_STORE_DATA_IMM_CoreModeEnable_bits 1 +#define GEN8_MI_STORE_DATA_IMM_CoreModeEnable_bits 1 +#define GEN75_MI_STORE_DATA_IMM_CoreModeEnable_bits 1 +#define GEN7_MI_STORE_DATA_IMM_CoreModeEnable_bits 1 +#define GEN6_MI_STORE_DATA_IMM_CoreModeEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_IMM_CoreModeEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_STORE_DATA_IMM_CoreModeEnable_start 32 +#define GEN10_MI_STORE_DATA_IMM_CoreModeEnable_start 32 +#define GEN9_MI_STORE_DATA_IMM_CoreModeEnable_start 32 +#define GEN8_MI_STORE_DATA_IMM_CoreModeEnable_start 32 +#define GEN75_MI_STORE_DATA_IMM_CoreModeEnable_start 64 +#define GEN7_MI_STORE_DATA_IMM_CoreModeEnable_start 64 +#define GEN6_MI_STORE_DATA_IMM_CoreModeEnable_start 64 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_IMM_CoreModeEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 64; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_STORE_DATA_IMM::DWord Length */ + + +#define GEN11_MI_STORE_DATA_IMM_DWordLength_bits 10 +#define GEN10_MI_STORE_DATA_IMM_DWordLength_bits 10 +#define GEN9_MI_STORE_DATA_IMM_DWordLength_bits 10 +#define GEN8_MI_STORE_DATA_IMM_DWordLength_bits 10 +#define GEN75_MI_STORE_DATA_IMM_DWordLength_bits 6 +#define GEN7_MI_STORE_DATA_IMM_DWordLength_bits 6 +#define GEN6_MI_STORE_DATA_IMM_DWordLength_bits 6 +#define GEN5_MI_STORE_DATA_IMM_DWordLength_bits 6 +#define GEN45_MI_STORE_DATA_IMM_DWordLength_bits 6 +#define GEN4_MI_STORE_DATA_IMM_DWordLength_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_IMM_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 10; + case 10: return 10; + case 9: return 10; + case 8: return 10; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 6; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_STORE_DATA_IMM_DWordLength_start 0 +#define GEN10_MI_STORE_DATA_IMM_DWordLength_start 0 +#define GEN9_MI_STORE_DATA_IMM_DWordLength_start 0 +#define GEN8_MI_STORE_DATA_IMM_DWordLength_start 0 +#define GEN75_MI_STORE_DATA_IMM_DWordLength_start 0 +#define GEN7_MI_STORE_DATA_IMM_DWordLength_start 0 +#define GEN6_MI_STORE_DATA_IMM_DWordLength_start 0 +#define GEN5_MI_STORE_DATA_IMM_DWordLength_start 0 +#define GEN45_MI_STORE_DATA_IMM_DWordLength_start 0 +#define GEN4_MI_STORE_DATA_IMM_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_IMM_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_STORE_DATA_IMM::Data DWord 0 */ + + +#define GEN5_MI_STORE_DATA_IMM_DataDWord0_bits 32 +#define GEN45_MI_STORE_DATA_IMM_DataDWord0_bits 32 +#define GEN4_MI_STORE_DATA_IMM_DataDWord0_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_IMM_DataDWord0_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_MI_STORE_DATA_IMM_DataDWord0_start 96 +#define GEN45_MI_STORE_DATA_IMM_DataDWord0_start 96 +#define GEN4_MI_STORE_DATA_IMM_DataDWord0_start 96 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_IMM_DataDWord0_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 96; + case 4: + if (devinfo->is_g4x) { + return 96; + } else { + return 96; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_STORE_DATA_IMM::Data DWord 1 */ + + +#define GEN5_MI_STORE_DATA_IMM_DataDWord1_bits 32 +#define GEN45_MI_STORE_DATA_IMM_DataDWord1_bits 32 +#define GEN4_MI_STORE_DATA_IMM_DataDWord1_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_IMM_DataDWord1_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_MI_STORE_DATA_IMM_DataDWord1_start 128 +#define GEN45_MI_STORE_DATA_IMM_DataDWord1_start 128 +#define GEN4_MI_STORE_DATA_IMM_DataDWord1_start 128 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_IMM_DataDWord1_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 128; + case 4: + if (devinfo->is_g4x) { + return 128; + } else { + return 128; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_STORE_DATA_IMM::Immediate Data */ + + +#define GEN11_MI_STORE_DATA_IMM_ImmediateData_bits 64 +#define GEN10_MI_STORE_DATA_IMM_ImmediateData_bits 64 +#define GEN9_MI_STORE_DATA_IMM_ImmediateData_bits 64 +#define GEN8_MI_STORE_DATA_IMM_ImmediateData_bits 64 +#define GEN75_MI_STORE_DATA_IMM_ImmediateData_bits 64 +#define GEN7_MI_STORE_DATA_IMM_ImmediateData_bits 64 +#define GEN6_MI_STORE_DATA_IMM_ImmediateData_bits 64 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_IMM_ImmediateData_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 64; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_STORE_DATA_IMM_ImmediateData_start 96 +#define GEN10_MI_STORE_DATA_IMM_ImmediateData_start 96 +#define GEN9_MI_STORE_DATA_IMM_ImmediateData_start 96 +#define GEN8_MI_STORE_DATA_IMM_ImmediateData_start 96 +#define GEN75_MI_STORE_DATA_IMM_ImmediateData_start 96 +#define GEN7_MI_STORE_DATA_IMM_ImmediateData_start 96 +#define GEN6_MI_STORE_DATA_IMM_ImmediateData_start 96 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_IMM_ImmediateData_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 96; + case 10: return 96; + case 9: return 96; + case 8: return 96; + case 7: + if (devinfo->is_haswell) { + return 96; + } else { + return 96; + } + case 6: return 96; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_STORE_DATA_IMM::MI Command Opcode */ + + +#define GEN11_MI_STORE_DATA_IMM_MICommandOpcode_bits 6 +#define GEN10_MI_STORE_DATA_IMM_MICommandOpcode_bits 6 +#define GEN9_MI_STORE_DATA_IMM_MICommandOpcode_bits 6 +#define GEN8_MI_STORE_DATA_IMM_MICommandOpcode_bits 6 +#define GEN75_MI_STORE_DATA_IMM_MICommandOpcode_bits 6 +#define GEN7_MI_STORE_DATA_IMM_MICommandOpcode_bits 6 +#define GEN6_MI_STORE_DATA_IMM_MICommandOpcode_bits 6 +#define GEN5_MI_STORE_DATA_IMM_MICommandOpcode_bits 6 +#define GEN45_MI_STORE_DATA_IMM_MICommandOpcode_bits 6 +#define GEN4_MI_STORE_DATA_IMM_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_IMM_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 6; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_STORE_DATA_IMM_MICommandOpcode_start 23 +#define GEN10_MI_STORE_DATA_IMM_MICommandOpcode_start 23 +#define GEN9_MI_STORE_DATA_IMM_MICommandOpcode_start 23 +#define GEN8_MI_STORE_DATA_IMM_MICommandOpcode_start 23 +#define GEN75_MI_STORE_DATA_IMM_MICommandOpcode_start 23 +#define GEN7_MI_STORE_DATA_IMM_MICommandOpcode_start 23 +#define GEN6_MI_STORE_DATA_IMM_MICommandOpcode_start 23 +#define GEN5_MI_STORE_DATA_IMM_MICommandOpcode_start 23 +#define GEN45_MI_STORE_DATA_IMM_MICommandOpcode_start 23 +#define GEN4_MI_STORE_DATA_IMM_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_IMM_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 23; + } else { + return 23; + } + case 6: return 23; + case 5: return 23; + case 4: + if (devinfo->is_g4x) { + return 23; + } else { + return 23; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_STORE_DATA_IMM::Memory Address Type */ + + +#define GEN5_MI_STORE_DATA_IMM_MemoryAddressType_bits 1 +#define GEN45_MI_STORE_DATA_IMM_MemoryAddressType_bits 1 +#define GEN4_MI_STORE_DATA_IMM_MemoryAddressType_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_IMM_MemoryAddressType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_MI_STORE_DATA_IMM_MemoryAddressType_start 22 +#define GEN45_MI_STORE_DATA_IMM_MemoryAddressType_start 22 +#define GEN4_MI_STORE_DATA_IMM_MemoryAddressType_start 22 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_IMM_MemoryAddressType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 22; + case 4: + if (devinfo->is_g4x) { + return 22; + } else { + return 22; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_STORE_DATA_IMM::Physical Start Address Extension */ + + +#define GEN5_MI_STORE_DATA_IMM_PhysicalStartAddressExtension_bits 4 +#define GEN45_MI_STORE_DATA_IMM_PhysicalStartAddressExtension_bits 4 +#define GEN4_MI_STORE_DATA_IMM_PhysicalStartAddressExtension_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_IMM_PhysicalStartAddressExtension_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 4; + case 4: + if (devinfo->is_g4x) { + return 4; + } else { + return 4; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_MI_STORE_DATA_IMM_PhysicalStartAddressExtension_start 32 +#define GEN45_MI_STORE_DATA_IMM_PhysicalStartAddressExtension_start 32 +#define GEN4_MI_STORE_DATA_IMM_PhysicalStartAddressExtension_start 32 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_IMM_PhysicalStartAddressExtension_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_STORE_DATA_IMM::Store Qword */ + + +#define GEN11_MI_STORE_DATA_IMM_StoreQword_bits 1 +#define GEN10_MI_STORE_DATA_IMM_StoreQword_bits 1 +#define GEN9_MI_STORE_DATA_IMM_StoreQword_bits 1 +#define GEN8_MI_STORE_DATA_IMM_StoreQword_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_IMM_StoreQword_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_STORE_DATA_IMM_StoreQword_start 21 +#define GEN10_MI_STORE_DATA_IMM_StoreQword_start 21 +#define GEN9_MI_STORE_DATA_IMM_StoreQword_start 21 +#define GEN8_MI_STORE_DATA_IMM_StoreQword_start 21 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_IMM_StoreQword_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 21; + case 10: return 21; + case 9: return 21; + case 8: return 21; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_STORE_DATA_IMM::Use Global GTT */ + + +#define GEN11_MI_STORE_DATA_IMM_UseGlobalGTT_bits 1 +#define GEN10_MI_STORE_DATA_IMM_UseGlobalGTT_bits 1 +#define GEN9_MI_STORE_DATA_IMM_UseGlobalGTT_bits 1 +#define GEN8_MI_STORE_DATA_IMM_UseGlobalGTT_bits 1 +#define GEN75_MI_STORE_DATA_IMM_UseGlobalGTT_bits 1 +#define GEN7_MI_STORE_DATA_IMM_UseGlobalGTT_bits 1 +#define GEN6_MI_STORE_DATA_IMM_UseGlobalGTT_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_IMM_UseGlobalGTT_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_STORE_DATA_IMM_UseGlobalGTT_start 22 +#define GEN10_MI_STORE_DATA_IMM_UseGlobalGTT_start 22 +#define GEN9_MI_STORE_DATA_IMM_UseGlobalGTT_start 22 +#define GEN8_MI_STORE_DATA_IMM_UseGlobalGTT_start 22 +#define GEN75_MI_STORE_DATA_IMM_UseGlobalGTT_start 22 +#define GEN7_MI_STORE_DATA_IMM_UseGlobalGTT_start 22 +#define GEN6_MI_STORE_DATA_IMM_UseGlobalGTT_start 22 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_IMM_UseGlobalGTT_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 22; + case 10: return 22; + case 9: return 22; + case 8: return 22; + case 7: + if (devinfo->is_haswell) { + return 22; + } else { + return 22; + } + case 6: return 22; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_STORE_DATA_INDEX */ + + +#define GEN11_MI_STORE_DATA_INDEX_length 3 +#define GEN10_MI_STORE_DATA_INDEX_length 3 +#define GEN9_MI_STORE_DATA_INDEX_length 3 +#define GEN8_MI_STORE_DATA_INDEX_length 3 +#define GEN75_MI_STORE_DATA_INDEX_length 3 +#define GEN7_MI_STORE_DATA_INDEX_length 3 +#define GEN6_MI_STORE_DATA_INDEX_length 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_INDEX_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_STORE_DATA_INDEX::Command Type */ + + +#define GEN11_MI_STORE_DATA_INDEX_CommandType_bits 3 +#define GEN10_MI_STORE_DATA_INDEX_CommandType_bits 3 +#define GEN9_MI_STORE_DATA_INDEX_CommandType_bits 3 +#define GEN8_MI_STORE_DATA_INDEX_CommandType_bits 3 +#define GEN75_MI_STORE_DATA_INDEX_CommandType_bits 3 +#define GEN7_MI_STORE_DATA_INDEX_CommandType_bits 3 +#define GEN6_MI_STORE_DATA_INDEX_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_INDEX_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_STORE_DATA_INDEX_CommandType_start 29 +#define GEN10_MI_STORE_DATA_INDEX_CommandType_start 29 +#define GEN9_MI_STORE_DATA_INDEX_CommandType_start 29 +#define GEN8_MI_STORE_DATA_INDEX_CommandType_start 29 +#define GEN75_MI_STORE_DATA_INDEX_CommandType_start 29 +#define GEN7_MI_STORE_DATA_INDEX_CommandType_start 29 +#define GEN6_MI_STORE_DATA_INDEX_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_INDEX_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_STORE_DATA_INDEX::DWord Length */ + + +#define GEN11_MI_STORE_DATA_INDEX_DWordLength_bits 8 +#define GEN10_MI_STORE_DATA_INDEX_DWordLength_bits 8 +#define GEN9_MI_STORE_DATA_INDEX_DWordLength_bits 8 +#define GEN8_MI_STORE_DATA_INDEX_DWordLength_bits 8 +#define GEN75_MI_STORE_DATA_INDEX_DWordLength_bits 8 +#define GEN7_MI_STORE_DATA_INDEX_DWordLength_bits 8 +#define GEN6_MI_STORE_DATA_INDEX_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_INDEX_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_STORE_DATA_INDEX_DWordLength_start 0 +#define GEN10_MI_STORE_DATA_INDEX_DWordLength_start 0 +#define GEN9_MI_STORE_DATA_INDEX_DWordLength_start 0 +#define GEN8_MI_STORE_DATA_INDEX_DWordLength_start 0 +#define GEN75_MI_STORE_DATA_INDEX_DWordLength_start 0 +#define GEN7_MI_STORE_DATA_INDEX_DWordLength_start 0 +#define GEN6_MI_STORE_DATA_INDEX_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_INDEX_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_STORE_DATA_INDEX::Data DWord 0 */ + + +#define GEN11_MI_STORE_DATA_INDEX_DataDWord0_bits 32 +#define GEN10_MI_STORE_DATA_INDEX_DataDWord0_bits 32 +#define GEN9_MI_STORE_DATA_INDEX_DataDWord0_bits 32 +#define GEN8_MI_STORE_DATA_INDEX_DataDWord0_bits 32 +#define GEN75_MI_STORE_DATA_INDEX_DataDWord0_bits 32 +#define GEN7_MI_STORE_DATA_INDEX_DataDWord0_bits 32 +#define GEN6_MI_STORE_DATA_INDEX_DataDWord0_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_INDEX_DataDWord0_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_STORE_DATA_INDEX_DataDWord0_start 64 +#define GEN10_MI_STORE_DATA_INDEX_DataDWord0_start 64 +#define GEN9_MI_STORE_DATA_INDEX_DataDWord0_start 64 +#define GEN8_MI_STORE_DATA_INDEX_DataDWord0_start 64 +#define GEN75_MI_STORE_DATA_INDEX_DataDWord0_start 64 +#define GEN7_MI_STORE_DATA_INDEX_DataDWord0_start 64 +#define GEN6_MI_STORE_DATA_INDEX_DataDWord0_start 64 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_INDEX_DataDWord0_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 64; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_STORE_DATA_INDEX::Data DWord 1 */ + + +#define GEN11_MI_STORE_DATA_INDEX_DataDWord1_bits 32 +#define GEN10_MI_STORE_DATA_INDEX_DataDWord1_bits 32 +#define GEN9_MI_STORE_DATA_INDEX_DataDWord1_bits 32 +#define GEN8_MI_STORE_DATA_INDEX_DataDWord1_bits 32 +#define GEN75_MI_STORE_DATA_INDEX_DataDWord1_bits 32 +#define GEN7_MI_STORE_DATA_INDEX_DataDWord1_bits 32 +#define GEN6_MI_STORE_DATA_INDEX_DataDWord1_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_INDEX_DataDWord1_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_STORE_DATA_INDEX_DataDWord1_start 96 +#define GEN10_MI_STORE_DATA_INDEX_DataDWord1_start 96 +#define GEN9_MI_STORE_DATA_INDEX_DataDWord1_start 96 +#define GEN8_MI_STORE_DATA_INDEX_DataDWord1_start 96 +#define GEN75_MI_STORE_DATA_INDEX_DataDWord1_start 96 +#define GEN7_MI_STORE_DATA_INDEX_DataDWord1_start 96 +#define GEN6_MI_STORE_DATA_INDEX_DataDWord1_start 96 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_INDEX_DataDWord1_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 96; + case 10: return 96; + case 9: return 96; + case 8: return 96; + case 7: + if (devinfo->is_haswell) { + return 96; + } else { + return 96; + } + case 6: return 96; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_STORE_DATA_INDEX::MI Command Opcode */ + + +#define GEN11_MI_STORE_DATA_INDEX_MICommandOpcode_bits 6 +#define GEN10_MI_STORE_DATA_INDEX_MICommandOpcode_bits 6 +#define GEN9_MI_STORE_DATA_INDEX_MICommandOpcode_bits 6 +#define GEN8_MI_STORE_DATA_INDEX_MICommandOpcode_bits 6 +#define GEN75_MI_STORE_DATA_INDEX_MICommandOpcode_bits 6 +#define GEN7_MI_STORE_DATA_INDEX_MICommandOpcode_bits 6 +#define GEN6_MI_STORE_DATA_INDEX_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_INDEX_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 6; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_STORE_DATA_INDEX_MICommandOpcode_start 23 +#define GEN10_MI_STORE_DATA_INDEX_MICommandOpcode_start 23 +#define GEN9_MI_STORE_DATA_INDEX_MICommandOpcode_start 23 +#define GEN8_MI_STORE_DATA_INDEX_MICommandOpcode_start 23 +#define GEN75_MI_STORE_DATA_INDEX_MICommandOpcode_start 23 +#define GEN7_MI_STORE_DATA_INDEX_MICommandOpcode_start 23 +#define GEN6_MI_STORE_DATA_INDEX_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_INDEX_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 23; + } else { + return 23; + } + case 6: return 23; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_STORE_DATA_INDEX::Offset */ + + +#define GEN11_MI_STORE_DATA_INDEX_Offset_bits 10 +#define GEN10_MI_STORE_DATA_INDEX_Offset_bits 10 +#define GEN9_MI_STORE_DATA_INDEX_Offset_bits 10 +#define GEN8_MI_STORE_DATA_INDEX_Offset_bits 10 +#define GEN75_MI_STORE_DATA_INDEX_Offset_bits 10 +#define GEN7_MI_STORE_DATA_INDEX_Offset_bits 10 +#define GEN6_MI_STORE_DATA_INDEX_Offset_bits 10 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_INDEX_Offset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 10; + case 10: return 10; + case 9: return 10; + case 8: return 10; + case 7: + if (devinfo->is_haswell) { + return 10; + } else { + return 10; + } + case 6: return 10; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_STORE_DATA_INDEX_Offset_start 34 +#define GEN10_MI_STORE_DATA_INDEX_Offset_start 34 +#define GEN9_MI_STORE_DATA_INDEX_Offset_start 34 +#define GEN8_MI_STORE_DATA_INDEX_Offset_start 34 +#define GEN75_MI_STORE_DATA_INDEX_Offset_start 34 +#define GEN7_MI_STORE_DATA_INDEX_Offset_start 34 +#define GEN6_MI_STORE_DATA_INDEX_Offset_start 34 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_INDEX_Offset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 34; + case 10: return 34; + case 9: return 34; + case 8: return 34; + case 7: + if (devinfo->is_haswell) { + return 34; + } else { + return 34; + } + case 6: return 34; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_STORE_DATA_INDEX::Use Per-Process Hardware Status Page */ + + +#define GEN11_MI_STORE_DATA_INDEX_UsePerProcessHardwareStatusPage_bits 1 +#define GEN10_MI_STORE_DATA_INDEX_UsePerProcessHardwareStatusPage_bits 1 +#define GEN9_MI_STORE_DATA_INDEX_UsePerProcessHardwareStatusPage_bits 1 +#define GEN8_MI_STORE_DATA_INDEX_UsePerProcessHardwareStatusPage_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_INDEX_UsePerProcessHardwareStatusPage_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_STORE_DATA_INDEX_UsePerProcessHardwareStatusPage_start 21 +#define GEN10_MI_STORE_DATA_INDEX_UsePerProcessHardwareStatusPage_start 21 +#define GEN9_MI_STORE_DATA_INDEX_UsePerProcessHardwareStatusPage_start 21 +#define GEN8_MI_STORE_DATA_INDEX_UsePerProcessHardwareStatusPage_start 21 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_DATA_INDEX_UsePerProcessHardwareStatusPage_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 21; + case 10: return 21; + case 9: return 21; + case 8: return 21; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_STORE_REGISTER_MEM */ + + +#define GEN11_MI_STORE_REGISTER_MEM_length 4 +#define GEN10_MI_STORE_REGISTER_MEM_length 4 +#define GEN9_MI_STORE_REGISTER_MEM_length 4 +#define GEN8_MI_STORE_REGISTER_MEM_length 4 +#define GEN75_MI_STORE_REGISTER_MEM_length 3 +#define GEN7_MI_STORE_REGISTER_MEM_length 3 +#define GEN6_MI_STORE_REGISTER_MEM_length 3 +#define GEN5_MI_STORE_REGISTER_MEM_length 3 +#define GEN45_MI_STORE_REGISTER_MEM_length 3 +#define GEN4_MI_STORE_REGISTER_MEM_length 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_REGISTER_MEM_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_STORE_REGISTER_MEM::Add CS MMIO Start Offset */ + + +#define GEN11_MI_STORE_REGISTER_MEM_AddCSMMIOStartOffset_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_REGISTER_MEM_AddCSMMIOStartOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_STORE_REGISTER_MEM_AddCSMMIOStartOffset_start 19 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_REGISTER_MEM_AddCSMMIOStartOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 19; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_STORE_REGISTER_MEM::Command Type */ + + +#define GEN11_MI_STORE_REGISTER_MEM_CommandType_bits 3 +#define GEN10_MI_STORE_REGISTER_MEM_CommandType_bits 3 +#define GEN9_MI_STORE_REGISTER_MEM_CommandType_bits 3 +#define GEN8_MI_STORE_REGISTER_MEM_CommandType_bits 3 +#define GEN75_MI_STORE_REGISTER_MEM_CommandType_bits 3 +#define GEN7_MI_STORE_REGISTER_MEM_CommandType_bits 3 +#define GEN6_MI_STORE_REGISTER_MEM_CommandType_bits 3 +#define GEN5_MI_STORE_REGISTER_MEM_CommandType_bits 3 +#define GEN45_MI_STORE_REGISTER_MEM_CommandType_bits 3 +#define GEN4_MI_STORE_REGISTER_MEM_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_REGISTER_MEM_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_STORE_REGISTER_MEM_CommandType_start 29 +#define GEN10_MI_STORE_REGISTER_MEM_CommandType_start 29 +#define GEN9_MI_STORE_REGISTER_MEM_CommandType_start 29 +#define GEN8_MI_STORE_REGISTER_MEM_CommandType_start 29 +#define GEN75_MI_STORE_REGISTER_MEM_CommandType_start 29 +#define GEN7_MI_STORE_REGISTER_MEM_CommandType_start 29 +#define GEN6_MI_STORE_REGISTER_MEM_CommandType_start 29 +#define GEN5_MI_STORE_REGISTER_MEM_CommandType_start 29 +#define GEN45_MI_STORE_REGISTER_MEM_CommandType_start 29 +#define GEN4_MI_STORE_REGISTER_MEM_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_REGISTER_MEM_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 29; + case 4: + if (devinfo->is_g4x) { + return 29; + } else { + return 29; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_STORE_REGISTER_MEM::DWord Length */ + + +#define GEN11_MI_STORE_REGISTER_MEM_DWordLength_bits 8 +#define GEN10_MI_STORE_REGISTER_MEM_DWordLength_bits 8 +#define GEN9_MI_STORE_REGISTER_MEM_DWordLength_bits 8 +#define GEN8_MI_STORE_REGISTER_MEM_DWordLength_bits 8 +#define GEN75_MI_STORE_REGISTER_MEM_DWordLength_bits 8 +#define GEN7_MI_STORE_REGISTER_MEM_DWordLength_bits 8 +#define GEN6_MI_STORE_REGISTER_MEM_DWordLength_bits 8 +#define GEN5_MI_STORE_REGISTER_MEM_DWordLength_bits 8 +#define GEN45_MI_STORE_REGISTER_MEM_DWordLength_bits 8 +#define GEN4_MI_STORE_REGISTER_MEM_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_REGISTER_MEM_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_STORE_REGISTER_MEM_DWordLength_start 0 +#define GEN10_MI_STORE_REGISTER_MEM_DWordLength_start 0 +#define GEN9_MI_STORE_REGISTER_MEM_DWordLength_start 0 +#define GEN8_MI_STORE_REGISTER_MEM_DWordLength_start 0 +#define GEN75_MI_STORE_REGISTER_MEM_DWordLength_start 0 +#define GEN7_MI_STORE_REGISTER_MEM_DWordLength_start 0 +#define GEN6_MI_STORE_REGISTER_MEM_DWordLength_start 0 +#define GEN5_MI_STORE_REGISTER_MEM_DWordLength_start 0 +#define GEN45_MI_STORE_REGISTER_MEM_DWordLength_start 0 +#define GEN4_MI_STORE_REGISTER_MEM_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_REGISTER_MEM_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_STORE_REGISTER_MEM::MI Command Opcode */ + + +#define GEN11_MI_STORE_REGISTER_MEM_MICommandOpcode_bits 6 +#define GEN10_MI_STORE_REGISTER_MEM_MICommandOpcode_bits 6 +#define GEN9_MI_STORE_REGISTER_MEM_MICommandOpcode_bits 6 +#define GEN8_MI_STORE_REGISTER_MEM_MICommandOpcode_bits 6 +#define GEN75_MI_STORE_REGISTER_MEM_MICommandOpcode_bits 6 +#define GEN7_MI_STORE_REGISTER_MEM_MICommandOpcode_bits 6 +#define GEN6_MI_STORE_REGISTER_MEM_MICommandOpcode_bits 6 +#define GEN5_MI_STORE_REGISTER_MEM_MICommandOpcode_bits 6 +#define GEN45_MI_STORE_REGISTER_MEM_MICommandOpcode_bits 6 +#define GEN4_MI_STORE_REGISTER_MEM_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_REGISTER_MEM_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 6; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_STORE_REGISTER_MEM_MICommandOpcode_start 23 +#define GEN10_MI_STORE_REGISTER_MEM_MICommandOpcode_start 23 +#define GEN9_MI_STORE_REGISTER_MEM_MICommandOpcode_start 23 +#define GEN8_MI_STORE_REGISTER_MEM_MICommandOpcode_start 23 +#define GEN75_MI_STORE_REGISTER_MEM_MICommandOpcode_start 23 +#define GEN7_MI_STORE_REGISTER_MEM_MICommandOpcode_start 23 +#define GEN6_MI_STORE_REGISTER_MEM_MICommandOpcode_start 23 +#define GEN5_MI_STORE_REGISTER_MEM_MICommandOpcode_start 23 +#define GEN45_MI_STORE_REGISTER_MEM_MICommandOpcode_start 23 +#define GEN4_MI_STORE_REGISTER_MEM_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_REGISTER_MEM_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 23; + } else { + return 23; + } + case 6: return 23; + case 5: return 23; + case 4: + if (devinfo->is_g4x) { + return 23; + } else { + return 23; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_STORE_REGISTER_MEM::Memory Address */ + + +#define GEN11_MI_STORE_REGISTER_MEM_MemoryAddress_bits 62 +#define GEN10_MI_STORE_REGISTER_MEM_MemoryAddress_bits 62 +#define GEN9_MI_STORE_REGISTER_MEM_MemoryAddress_bits 62 +#define GEN8_MI_STORE_REGISTER_MEM_MemoryAddress_bits 62 +#define GEN75_MI_STORE_REGISTER_MEM_MemoryAddress_bits 30 +#define GEN7_MI_STORE_REGISTER_MEM_MemoryAddress_bits 30 +#define GEN6_MI_STORE_REGISTER_MEM_MemoryAddress_bits 30 +#define GEN5_MI_STORE_REGISTER_MEM_MemoryAddress_bits 30 +#define GEN45_MI_STORE_REGISTER_MEM_MemoryAddress_bits 30 +#define GEN4_MI_STORE_REGISTER_MEM_MemoryAddress_bits 30 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_REGISTER_MEM_MemoryAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 62; + case 10: return 62; + case 9: return 62; + case 8: return 62; + case 7: + if (devinfo->is_haswell) { + return 30; + } else { + return 30; + } + case 6: return 30; + case 5: return 30; + case 4: + if (devinfo->is_g4x) { + return 30; + } else { + return 30; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_STORE_REGISTER_MEM_MemoryAddress_start 66 +#define GEN10_MI_STORE_REGISTER_MEM_MemoryAddress_start 66 +#define GEN9_MI_STORE_REGISTER_MEM_MemoryAddress_start 66 +#define GEN8_MI_STORE_REGISTER_MEM_MemoryAddress_start 66 +#define GEN75_MI_STORE_REGISTER_MEM_MemoryAddress_start 66 +#define GEN7_MI_STORE_REGISTER_MEM_MemoryAddress_start 66 +#define GEN6_MI_STORE_REGISTER_MEM_MemoryAddress_start 66 +#define GEN5_MI_STORE_REGISTER_MEM_MemoryAddress_start 66 +#define GEN45_MI_STORE_REGISTER_MEM_MemoryAddress_start 66 +#define GEN4_MI_STORE_REGISTER_MEM_MemoryAddress_start 66 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_REGISTER_MEM_MemoryAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 66; + case 10: return 66; + case 9: return 66; + case 8: return 66; + case 7: + if (devinfo->is_haswell) { + return 66; + } else { + return 66; + } + case 6: return 66; + case 5: return 66; + case 4: + if (devinfo->is_g4x) { + return 66; + } else { + return 66; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_STORE_REGISTER_MEM::Physical Start Address Extension */ + + +#define GEN45_MI_STORE_REGISTER_MEM_PhysicalStartAddressExtension_bits 4 +#define GEN4_MI_STORE_REGISTER_MEM_PhysicalStartAddressExtension_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_REGISTER_MEM_PhysicalStartAddressExtension_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 4; + } else { + return 4; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN45_MI_STORE_REGISTER_MEM_PhysicalStartAddressExtension_start 60 +#define GEN4_MI_STORE_REGISTER_MEM_PhysicalStartAddressExtension_start 60 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_REGISTER_MEM_PhysicalStartAddressExtension_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 60; + } else { + return 60; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_STORE_REGISTER_MEM::Predicate Enable */ + + +#define GEN11_MI_STORE_REGISTER_MEM_PredicateEnable_bits 1 +#define GEN10_MI_STORE_REGISTER_MEM_PredicateEnable_bits 1 +#define GEN9_MI_STORE_REGISTER_MEM_PredicateEnable_bits 1 +#define GEN8_MI_STORE_REGISTER_MEM_PredicateEnable_bits 1 +#define GEN75_MI_STORE_REGISTER_MEM_PredicateEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_REGISTER_MEM_PredicateEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_STORE_REGISTER_MEM_PredicateEnable_start 21 +#define GEN10_MI_STORE_REGISTER_MEM_PredicateEnable_start 21 +#define GEN9_MI_STORE_REGISTER_MEM_PredicateEnable_start 21 +#define GEN8_MI_STORE_REGISTER_MEM_PredicateEnable_start 21 +#define GEN75_MI_STORE_REGISTER_MEM_PredicateEnable_start 21 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_REGISTER_MEM_PredicateEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 21; + case 10: return 21; + case 9: return 21; + case 8: return 21; + case 7: + if (devinfo->is_haswell) { + return 21; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_STORE_REGISTER_MEM::Register Address */ + + +#define GEN11_MI_STORE_REGISTER_MEM_RegisterAddress_bits 21 +#define GEN10_MI_STORE_REGISTER_MEM_RegisterAddress_bits 21 +#define GEN9_MI_STORE_REGISTER_MEM_RegisterAddress_bits 21 +#define GEN8_MI_STORE_REGISTER_MEM_RegisterAddress_bits 21 +#define GEN75_MI_STORE_REGISTER_MEM_RegisterAddress_bits 21 +#define GEN7_MI_STORE_REGISTER_MEM_RegisterAddress_bits 21 +#define GEN6_MI_STORE_REGISTER_MEM_RegisterAddress_bits 21 +#define GEN5_MI_STORE_REGISTER_MEM_RegisterAddress_bits 24 +#define GEN45_MI_STORE_REGISTER_MEM_RegisterAddress_bits 21 +#define GEN4_MI_STORE_REGISTER_MEM_RegisterAddress_bits 21 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_REGISTER_MEM_RegisterAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 21; + case 10: return 21; + case 9: return 21; + case 8: return 21; + case 7: + if (devinfo->is_haswell) { + return 21; + } else { + return 21; + } + case 6: return 21; + case 5: return 24; + case 4: + if (devinfo->is_g4x) { + return 21; + } else { + return 21; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_STORE_REGISTER_MEM_RegisterAddress_start 34 +#define GEN10_MI_STORE_REGISTER_MEM_RegisterAddress_start 34 +#define GEN9_MI_STORE_REGISTER_MEM_RegisterAddress_start 34 +#define GEN8_MI_STORE_REGISTER_MEM_RegisterAddress_start 34 +#define GEN75_MI_STORE_REGISTER_MEM_RegisterAddress_start 34 +#define GEN7_MI_STORE_REGISTER_MEM_RegisterAddress_start 34 +#define GEN6_MI_STORE_REGISTER_MEM_RegisterAddress_start 34 +#define GEN5_MI_STORE_REGISTER_MEM_RegisterAddress_start 34 +#define GEN45_MI_STORE_REGISTER_MEM_RegisterAddress_start 34 +#define GEN4_MI_STORE_REGISTER_MEM_RegisterAddress_start 34 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_REGISTER_MEM_RegisterAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 34; + case 10: return 34; + case 9: return 34; + case 8: return 34; + case 7: + if (devinfo->is_haswell) { + return 34; + } else { + return 34; + } + case 6: return 34; + case 5: return 34; + case 4: + if (devinfo->is_g4x) { + return 34; + } else { + return 34; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_STORE_REGISTER_MEM::Use Global GTT */ + + +#define GEN11_MI_STORE_REGISTER_MEM_UseGlobalGTT_bits 1 +#define GEN10_MI_STORE_REGISTER_MEM_UseGlobalGTT_bits 1 +#define GEN9_MI_STORE_REGISTER_MEM_UseGlobalGTT_bits 1 +#define GEN8_MI_STORE_REGISTER_MEM_UseGlobalGTT_bits 1 +#define GEN75_MI_STORE_REGISTER_MEM_UseGlobalGTT_bits 1 +#define GEN7_MI_STORE_REGISTER_MEM_UseGlobalGTT_bits 1 +#define GEN6_MI_STORE_REGISTER_MEM_UseGlobalGTT_bits 1 +#define GEN5_MI_STORE_REGISTER_MEM_UseGlobalGTT_bits 1 +#define GEN45_MI_STORE_REGISTER_MEM_UseGlobalGTT_bits 1 +#define GEN4_MI_STORE_REGISTER_MEM_UseGlobalGTT_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_REGISTER_MEM_UseGlobalGTT_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_STORE_REGISTER_MEM_UseGlobalGTT_start 22 +#define GEN10_MI_STORE_REGISTER_MEM_UseGlobalGTT_start 22 +#define GEN9_MI_STORE_REGISTER_MEM_UseGlobalGTT_start 22 +#define GEN8_MI_STORE_REGISTER_MEM_UseGlobalGTT_start 22 +#define GEN75_MI_STORE_REGISTER_MEM_UseGlobalGTT_start 22 +#define GEN7_MI_STORE_REGISTER_MEM_UseGlobalGTT_start 22 +#define GEN6_MI_STORE_REGISTER_MEM_UseGlobalGTT_start 22 +#define GEN5_MI_STORE_REGISTER_MEM_UseGlobalGTT_start 22 +#define GEN45_MI_STORE_REGISTER_MEM_UseGlobalGTT_start 22 +#define GEN4_MI_STORE_REGISTER_MEM_UseGlobalGTT_start 22 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_REGISTER_MEM_UseGlobalGTT_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 22; + case 10: return 22; + case 9: return 22; + case 8: return 22; + case 7: + if (devinfo->is_haswell) { + return 22; + } else { + return 22; + } + case 6: return 22; + case 5: return 22; + case 4: + if (devinfo->is_g4x) { + return 22; + } else { + return 22; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_STORE_URB_MEM */ + + +#define GEN9_MI_STORE_URB_MEM_length 4 +#define GEN8_MI_STORE_URB_MEM_length 4 +#define GEN75_MI_STORE_URB_MEM_length 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_URB_MEM_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_STORE_URB_MEM::Command Type */ + + +#define GEN9_MI_STORE_URB_MEM_CommandType_bits 3 +#define GEN8_MI_STORE_URB_MEM_CommandType_bits 3 +#define GEN75_MI_STORE_URB_MEM_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_URB_MEM_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_MI_STORE_URB_MEM_CommandType_start 29 +#define GEN8_MI_STORE_URB_MEM_CommandType_start 29 +#define GEN75_MI_STORE_URB_MEM_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_URB_MEM_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_STORE_URB_MEM::DWord Length */ + + +#define GEN9_MI_STORE_URB_MEM_DWordLength_bits 8 +#define GEN8_MI_STORE_URB_MEM_DWordLength_bits 8 +#define GEN75_MI_STORE_URB_MEM_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_URB_MEM_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_MI_STORE_URB_MEM_DWordLength_start 0 +#define GEN8_MI_STORE_URB_MEM_DWordLength_start 0 +#define GEN75_MI_STORE_URB_MEM_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_URB_MEM_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_STORE_URB_MEM::MI Command Opcode */ + + +#define GEN9_MI_STORE_URB_MEM_MICommandOpcode_bits 6 +#define GEN8_MI_STORE_URB_MEM_MICommandOpcode_bits 6 +#define GEN75_MI_STORE_URB_MEM_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_URB_MEM_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_MI_STORE_URB_MEM_MICommandOpcode_start 23 +#define GEN8_MI_STORE_URB_MEM_MICommandOpcode_start 23 +#define GEN75_MI_STORE_URB_MEM_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_URB_MEM_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 23; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_STORE_URB_MEM::Memory Address */ + + +#define GEN9_MI_STORE_URB_MEM_MemoryAddress_bits 58 +#define GEN8_MI_STORE_URB_MEM_MemoryAddress_bits 58 +#define GEN75_MI_STORE_URB_MEM_MemoryAddress_bits 26 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_URB_MEM_MemoryAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 58; + case 8: return 58; + case 7: + if (devinfo->is_haswell) { + return 26; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_MI_STORE_URB_MEM_MemoryAddress_start 70 +#define GEN8_MI_STORE_URB_MEM_MemoryAddress_start 70 +#define GEN75_MI_STORE_URB_MEM_MemoryAddress_start 70 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_URB_MEM_MemoryAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 70; + case 8: return 70; + case 7: + if (devinfo->is_haswell) { + return 70; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_STORE_URB_MEM::URB Address */ + + +#define GEN9_MI_STORE_URB_MEM_URBAddress_bits 13 +#define GEN8_MI_STORE_URB_MEM_URBAddress_bits 13 +#define GEN75_MI_STORE_URB_MEM_URBAddress_bits 13 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_URB_MEM_URBAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 13; + case 8: return 13; + case 7: + if (devinfo->is_haswell) { + return 13; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_MI_STORE_URB_MEM_URBAddress_start 34 +#define GEN8_MI_STORE_URB_MEM_URBAddress_start 34 +#define GEN75_MI_STORE_URB_MEM_URBAddress_start 34 + +static inline uint32_t ATTRIBUTE_PURE +MI_STORE_URB_MEM_URBAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 34; + case 8: return 34; + case 7: + if (devinfo->is_haswell) { + return 34; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SUSPEND_FLUSH */ + + +#define GEN11_MI_SUSPEND_FLUSH_length 1 +#define GEN10_MI_SUSPEND_FLUSH_length 1 +#define GEN9_MI_SUSPEND_FLUSH_length 1 +#define GEN8_MI_SUSPEND_FLUSH_length 1 +#define GEN75_MI_SUSPEND_FLUSH_length 1 +#define GEN7_MI_SUSPEND_FLUSH_length 1 +#define GEN6_MI_SUSPEND_FLUSH_length 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_SUSPEND_FLUSH_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SUSPEND_FLUSH::Command Type */ + + +#define GEN11_MI_SUSPEND_FLUSH_CommandType_bits 3 +#define GEN10_MI_SUSPEND_FLUSH_CommandType_bits 3 +#define GEN9_MI_SUSPEND_FLUSH_CommandType_bits 3 +#define GEN8_MI_SUSPEND_FLUSH_CommandType_bits 3 +#define GEN75_MI_SUSPEND_FLUSH_CommandType_bits 3 +#define GEN7_MI_SUSPEND_FLUSH_CommandType_bits 3 +#define GEN6_MI_SUSPEND_FLUSH_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_SUSPEND_FLUSH_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_SUSPEND_FLUSH_CommandType_start 29 +#define GEN10_MI_SUSPEND_FLUSH_CommandType_start 29 +#define GEN9_MI_SUSPEND_FLUSH_CommandType_start 29 +#define GEN8_MI_SUSPEND_FLUSH_CommandType_start 29 +#define GEN75_MI_SUSPEND_FLUSH_CommandType_start 29 +#define GEN7_MI_SUSPEND_FLUSH_CommandType_start 29 +#define GEN6_MI_SUSPEND_FLUSH_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_SUSPEND_FLUSH_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SUSPEND_FLUSH::MI Command Opcode */ + + +#define GEN11_MI_SUSPEND_FLUSH_MICommandOpcode_bits 6 +#define GEN10_MI_SUSPEND_FLUSH_MICommandOpcode_bits 6 +#define GEN9_MI_SUSPEND_FLUSH_MICommandOpcode_bits 6 +#define GEN8_MI_SUSPEND_FLUSH_MICommandOpcode_bits 6 +#define GEN75_MI_SUSPEND_FLUSH_MICommandOpcode_bits 6 +#define GEN7_MI_SUSPEND_FLUSH_MICommandOpcode_bits 6 +#define GEN6_MI_SUSPEND_FLUSH_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_SUSPEND_FLUSH_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 6; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_SUSPEND_FLUSH_MICommandOpcode_start 23 +#define GEN10_MI_SUSPEND_FLUSH_MICommandOpcode_start 23 +#define GEN9_MI_SUSPEND_FLUSH_MICommandOpcode_start 23 +#define GEN8_MI_SUSPEND_FLUSH_MICommandOpcode_start 23 +#define GEN75_MI_SUSPEND_FLUSH_MICommandOpcode_start 23 +#define GEN7_MI_SUSPEND_FLUSH_MICommandOpcode_start 23 +#define GEN6_MI_SUSPEND_FLUSH_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_SUSPEND_FLUSH_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 23; + } else { + return 23; + } + case 6: return 23; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_SUSPEND_FLUSH::Suspend Flush */ + + +#define GEN11_MI_SUSPEND_FLUSH_SuspendFlush_bits 1 +#define GEN10_MI_SUSPEND_FLUSH_SuspendFlush_bits 1 +#define GEN9_MI_SUSPEND_FLUSH_SuspendFlush_bits 1 +#define GEN8_MI_SUSPEND_FLUSH_SuspendFlush_bits 1 +#define GEN75_MI_SUSPEND_FLUSH_SuspendFlush_bits 1 +#define GEN7_MI_SUSPEND_FLUSH_SuspendFlush_bits 1 +#define GEN6_MI_SUSPEND_FLUSH_SuspendFlush_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_SUSPEND_FLUSH_SuspendFlush_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_SUSPEND_FLUSH_SuspendFlush_start 0 +#define GEN10_MI_SUSPEND_FLUSH_SuspendFlush_start 0 +#define GEN9_MI_SUSPEND_FLUSH_SuspendFlush_start 0 +#define GEN8_MI_SUSPEND_FLUSH_SuspendFlush_start 0 +#define GEN75_MI_SUSPEND_FLUSH_SuspendFlush_start 0 +#define GEN7_MI_SUSPEND_FLUSH_SuspendFlush_start 0 +#define GEN6_MI_SUSPEND_FLUSH_SuspendFlush_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_SUSPEND_FLUSH_SuspendFlush_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_TOPOLOGY_FILTER */ + + +#define GEN11_MI_TOPOLOGY_FILTER_length 1 +#define GEN10_MI_TOPOLOGY_FILTER_length 1 +#define GEN9_MI_TOPOLOGY_FILTER_length 1 +#define GEN8_MI_TOPOLOGY_FILTER_length 1 +#define GEN75_MI_TOPOLOGY_FILTER_length 1 +#define GEN7_MI_TOPOLOGY_FILTER_length 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_TOPOLOGY_FILTER_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_TOPOLOGY_FILTER::Command Type */ + + +#define GEN11_MI_TOPOLOGY_FILTER_CommandType_bits 3 +#define GEN10_MI_TOPOLOGY_FILTER_CommandType_bits 3 +#define GEN9_MI_TOPOLOGY_FILTER_CommandType_bits 3 +#define GEN8_MI_TOPOLOGY_FILTER_CommandType_bits 3 +#define GEN75_MI_TOPOLOGY_FILTER_CommandType_bits 3 +#define GEN7_MI_TOPOLOGY_FILTER_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_TOPOLOGY_FILTER_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_TOPOLOGY_FILTER_CommandType_start 29 +#define GEN10_MI_TOPOLOGY_FILTER_CommandType_start 29 +#define GEN9_MI_TOPOLOGY_FILTER_CommandType_start 29 +#define GEN8_MI_TOPOLOGY_FILTER_CommandType_start 29 +#define GEN75_MI_TOPOLOGY_FILTER_CommandType_start 29 +#define GEN7_MI_TOPOLOGY_FILTER_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_TOPOLOGY_FILTER_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_TOPOLOGY_FILTER::MI Command Opcode */ + + +#define GEN11_MI_TOPOLOGY_FILTER_MICommandOpcode_bits 6 +#define GEN10_MI_TOPOLOGY_FILTER_MICommandOpcode_bits 6 +#define GEN9_MI_TOPOLOGY_FILTER_MICommandOpcode_bits 6 +#define GEN8_MI_TOPOLOGY_FILTER_MICommandOpcode_bits 6 +#define GEN75_MI_TOPOLOGY_FILTER_MICommandOpcode_bits 6 +#define GEN7_MI_TOPOLOGY_FILTER_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_TOPOLOGY_FILTER_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_TOPOLOGY_FILTER_MICommandOpcode_start 23 +#define GEN10_MI_TOPOLOGY_FILTER_MICommandOpcode_start 23 +#define GEN9_MI_TOPOLOGY_FILTER_MICommandOpcode_start 23 +#define GEN8_MI_TOPOLOGY_FILTER_MICommandOpcode_start 23 +#define GEN75_MI_TOPOLOGY_FILTER_MICommandOpcode_start 23 +#define GEN7_MI_TOPOLOGY_FILTER_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_TOPOLOGY_FILTER_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 23; + } else { + return 23; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_TOPOLOGY_FILTER::Topology Filter Value */ + + +#define GEN11_MI_TOPOLOGY_FILTER_TopologyFilterValue_bits 6 +#define GEN10_MI_TOPOLOGY_FILTER_TopologyFilterValue_bits 6 +#define GEN9_MI_TOPOLOGY_FILTER_TopologyFilterValue_bits 6 +#define GEN8_MI_TOPOLOGY_FILTER_TopologyFilterValue_bits 6 +#define GEN75_MI_TOPOLOGY_FILTER_TopologyFilterValue_bits 6 +#define GEN7_MI_TOPOLOGY_FILTER_TopologyFilterValue_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_TOPOLOGY_FILTER_TopologyFilterValue_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_TOPOLOGY_FILTER_TopologyFilterValue_start 0 +#define GEN10_MI_TOPOLOGY_FILTER_TopologyFilterValue_start 0 +#define GEN9_MI_TOPOLOGY_FILTER_TopologyFilterValue_start 0 +#define GEN8_MI_TOPOLOGY_FILTER_TopologyFilterValue_start 0 +#define GEN75_MI_TOPOLOGY_FILTER_TopologyFilterValue_start 0 +#define GEN7_MI_TOPOLOGY_FILTER_TopologyFilterValue_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_TOPOLOGY_FILTER_TopologyFilterValue_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_UPDATE_GTT */ + + + + + +/* MI_UPDATE_GTT::Command Type */ + + +#define GEN10_MI_UPDATE_GTT_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_UPDATE_GTT_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 3; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MI_UPDATE_GTT_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_UPDATE_GTT_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 29; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_UPDATE_GTT::DWord Length */ + + +#define GEN10_MI_UPDATE_GTT_DWordLength_bits 10 + +static inline uint32_t ATTRIBUTE_PURE +MI_UPDATE_GTT_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 10; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MI_UPDATE_GTT_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_UPDATE_GTT_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_UPDATE_GTT::Entry Address */ + + +#define GEN10_MI_UPDATE_GTT_EntryAddress_bits 20 + +static inline uint32_t ATTRIBUTE_PURE +MI_UPDATE_GTT_EntryAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 20; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MI_UPDATE_GTT_EntryAddress_start 44 + +static inline uint32_t ATTRIBUTE_PURE +MI_UPDATE_GTT_EntryAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 44; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_UPDATE_GTT::Entry Data */ + + +#define GEN10_MI_UPDATE_GTT_EntryData_bits 64 + +static inline uint32_t ATTRIBUTE_PURE +MI_UPDATE_GTT_EntryData_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 64; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MI_UPDATE_GTT_EntryData_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_UPDATE_GTT_EntryData_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_UPDATE_GTT::MI Command Opcode */ + + +#define GEN10_MI_UPDATE_GTT_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_UPDATE_GTT_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 6; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_MI_UPDATE_GTT_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_UPDATE_GTT_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 23; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_URB_ATOMIC_ALLOC */ + + +#define GEN9_MI_URB_ATOMIC_ALLOC_length 1 +#define GEN8_MI_URB_ATOMIC_ALLOC_length 1 +#define GEN75_MI_URB_ATOMIC_ALLOC_length 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_URB_ATOMIC_ALLOC_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_URB_ATOMIC_ALLOC::Command Type */ + + +#define GEN9_MI_URB_ATOMIC_ALLOC_CommandType_bits 3 +#define GEN8_MI_URB_ATOMIC_ALLOC_CommandType_bits 3 +#define GEN75_MI_URB_ATOMIC_ALLOC_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_URB_ATOMIC_ALLOC_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_MI_URB_ATOMIC_ALLOC_CommandType_start 29 +#define GEN8_MI_URB_ATOMIC_ALLOC_CommandType_start 29 +#define GEN75_MI_URB_ATOMIC_ALLOC_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_URB_ATOMIC_ALLOC_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_URB_ATOMIC_ALLOC::MI Command Opcode */ + + +#define GEN9_MI_URB_ATOMIC_ALLOC_MICommandOpcode_bits 6 +#define GEN8_MI_URB_ATOMIC_ALLOC_MICommandOpcode_bits 6 +#define GEN75_MI_URB_ATOMIC_ALLOC_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_URB_ATOMIC_ALLOC_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_MI_URB_ATOMIC_ALLOC_MICommandOpcode_start 23 +#define GEN8_MI_URB_ATOMIC_ALLOC_MICommandOpcode_start 23 +#define GEN75_MI_URB_ATOMIC_ALLOC_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_URB_ATOMIC_ALLOC_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 23; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_URB_ATOMIC_ALLOC::URB Atomic Storage Offset */ + + +#define GEN9_MI_URB_ATOMIC_ALLOC_URBAtomicStorageOffset_bits 8 +#define GEN8_MI_URB_ATOMIC_ALLOC_URBAtomicStorageOffset_bits 8 +#define GEN75_MI_URB_ATOMIC_ALLOC_URBAtomicStorageOffset_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MI_URB_ATOMIC_ALLOC_URBAtomicStorageOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_MI_URB_ATOMIC_ALLOC_URBAtomicStorageOffset_start 12 +#define GEN8_MI_URB_ATOMIC_ALLOC_URBAtomicStorageOffset_start 12 +#define GEN75_MI_URB_ATOMIC_ALLOC_URBAtomicStorageOffset_start 12 + +static inline uint32_t ATTRIBUTE_PURE +MI_URB_ATOMIC_ALLOC_URBAtomicStorageOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 12; + case 8: return 12; + case 7: + if (devinfo->is_haswell) { + return 12; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_URB_ATOMIC_ALLOC::URB Atomic Storage Size */ + + +#define GEN9_MI_URB_ATOMIC_ALLOC_URBAtomicStorageSize_bits 9 +#define GEN8_MI_URB_ATOMIC_ALLOC_URBAtomicStorageSize_bits 9 +#define GEN75_MI_URB_ATOMIC_ALLOC_URBAtomicStorageSize_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +MI_URB_ATOMIC_ALLOC_URBAtomicStorageSize_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_MI_URB_ATOMIC_ALLOC_URBAtomicStorageSize_start 0 +#define GEN8_MI_URB_ATOMIC_ALLOC_URBAtomicStorageSize_start 0 +#define GEN75_MI_URB_ATOMIC_ALLOC_URBAtomicStorageSize_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_URB_ATOMIC_ALLOC_URBAtomicStorageSize_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_URB_CLEAR */ + + +#define GEN8_MI_URB_CLEAR_length 2 +#define GEN75_MI_URB_CLEAR_length 2 +#define GEN7_MI_URB_CLEAR_length 2 +#define GEN6_MI_URB_CLEAR_length 2 + +static inline uint32_t ATTRIBUTE_PURE +MI_URB_CLEAR_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_URB_CLEAR::Command Type */ + + +#define GEN8_MI_URB_CLEAR_CommandType_bits 3 +#define GEN75_MI_URB_CLEAR_CommandType_bits 3 +#define GEN7_MI_URB_CLEAR_CommandType_bits 3 +#define GEN6_MI_URB_CLEAR_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_URB_CLEAR_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_MI_URB_CLEAR_CommandType_start 29 +#define GEN75_MI_URB_CLEAR_CommandType_start 29 +#define GEN7_MI_URB_CLEAR_CommandType_start 29 +#define GEN6_MI_URB_CLEAR_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_URB_CLEAR_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_URB_CLEAR::DWord Length */ + + +#define GEN8_MI_URB_CLEAR_DWordLength_bits 8 +#define GEN75_MI_URB_CLEAR_DWordLength_bits 8 +#define GEN7_MI_URB_CLEAR_DWordLength_bits 8 +#define GEN6_MI_URB_CLEAR_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +MI_URB_CLEAR_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_MI_URB_CLEAR_DWordLength_start 0 +#define GEN75_MI_URB_CLEAR_DWordLength_start 0 +#define GEN7_MI_URB_CLEAR_DWordLength_start 0 +#define GEN6_MI_URB_CLEAR_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_URB_CLEAR_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_URB_CLEAR::MI Command Opcode */ + + +#define GEN8_MI_URB_CLEAR_MICommandOpcode_bits 6 +#define GEN75_MI_URB_CLEAR_MICommandOpcode_bits 6 +#define GEN7_MI_URB_CLEAR_MICommandOpcode_bits 6 +#define GEN6_MI_URB_CLEAR_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_URB_CLEAR_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 6; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_MI_URB_CLEAR_MICommandOpcode_start 23 +#define GEN75_MI_URB_CLEAR_MICommandOpcode_start 23 +#define GEN7_MI_URB_CLEAR_MICommandOpcode_start 23 +#define GEN6_MI_URB_CLEAR_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_URB_CLEAR_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 23; + } else { + return 23; + } + case 6: return 23; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_URB_CLEAR::URB Address */ + + +#define GEN8_MI_URB_CLEAR_URBAddress_bits 15 +#define GEN75_MI_URB_CLEAR_URBAddress_bits 15 +#define GEN7_MI_URB_CLEAR_URBAddress_bits 14 +#define GEN6_MI_URB_CLEAR_URBAddress_bits 14 + +static inline uint32_t ATTRIBUTE_PURE +MI_URB_CLEAR_URBAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 15; + case 7: + if (devinfo->is_haswell) { + return 15; + } else { + return 14; + } + case 6: return 14; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_MI_URB_CLEAR_URBAddress_start 32 +#define GEN75_MI_URB_CLEAR_URBAddress_start 32 +#define GEN7_MI_URB_CLEAR_URBAddress_start 32 +#define GEN6_MI_URB_CLEAR_URBAddress_start 32 + +static inline uint32_t ATTRIBUTE_PURE +MI_URB_CLEAR_URBAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_URB_CLEAR::URB Clear Length */ + + +#define GEN8_MI_URB_CLEAR_URBClearLength_bits 14 +#define GEN75_MI_URB_CLEAR_URBClearLength_bits 14 +#define GEN7_MI_URB_CLEAR_URBClearLength_bits 13 +#define GEN6_MI_URB_CLEAR_URBClearLength_bits 13 + +static inline uint32_t ATTRIBUTE_PURE +MI_URB_CLEAR_URBClearLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 14; + case 7: + if (devinfo->is_haswell) { + return 14; + } else { + return 13; + } + case 6: return 13; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_MI_URB_CLEAR_URBClearLength_start 48 +#define GEN75_MI_URB_CLEAR_URBClearLength_start 48 +#define GEN7_MI_URB_CLEAR_URBClearLength_start 48 +#define GEN6_MI_URB_CLEAR_URBClearLength_start 48 + +static inline uint32_t ATTRIBUTE_PURE +MI_URB_CLEAR_URBClearLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 48; + case 7: + if (devinfo->is_haswell) { + return 48; + } else { + return 48; + } + case 6: return 48; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_USER_INTERRUPT */ + + +#define GEN11_MI_USER_INTERRUPT_length 1 +#define GEN10_MI_USER_INTERRUPT_length 1 +#define GEN9_MI_USER_INTERRUPT_length 1 +#define GEN8_MI_USER_INTERRUPT_length 1 +#define GEN75_MI_USER_INTERRUPT_length 1 +#define GEN7_MI_USER_INTERRUPT_length 1 +#define GEN6_MI_USER_INTERRUPT_length 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_USER_INTERRUPT_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_USER_INTERRUPT::Command Type */ + + +#define GEN11_MI_USER_INTERRUPT_CommandType_bits 3 +#define GEN10_MI_USER_INTERRUPT_CommandType_bits 3 +#define GEN9_MI_USER_INTERRUPT_CommandType_bits 3 +#define GEN8_MI_USER_INTERRUPT_CommandType_bits 3 +#define GEN75_MI_USER_INTERRUPT_CommandType_bits 3 +#define GEN7_MI_USER_INTERRUPT_CommandType_bits 3 +#define GEN6_MI_USER_INTERRUPT_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_USER_INTERRUPT_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_USER_INTERRUPT_CommandType_start 29 +#define GEN10_MI_USER_INTERRUPT_CommandType_start 29 +#define GEN9_MI_USER_INTERRUPT_CommandType_start 29 +#define GEN8_MI_USER_INTERRUPT_CommandType_start 29 +#define GEN75_MI_USER_INTERRUPT_CommandType_start 29 +#define GEN7_MI_USER_INTERRUPT_CommandType_start 29 +#define GEN6_MI_USER_INTERRUPT_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_USER_INTERRUPT_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_USER_INTERRUPT::MI Command Opcode */ + + +#define GEN11_MI_USER_INTERRUPT_MICommandOpcode_bits 6 +#define GEN10_MI_USER_INTERRUPT_MICommandOpcode_bits 6 +#define GEN9_MI_USER_INTERRUPT_MICommandOpcode_bits 6 +#define GEN8_MI_USER_INTERRUPT_MICommandOpcode_bits 6 +#define GEN75_MI_USER_INTERRUPT_MICommandOpcode_bits 6 +#define GEN7_MI_USER_INTERRUPT_MICommandOpcode_bits 6 +#define GEN6_MI_USER_INTERRUPT_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_USER_INTERRUPT_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 6; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_USER_INTERRUPT_MICommandOpcode_start 23 +#define GEN10_MI_USER_INTERRUPT_MICommandOpcode_start 23 +#define GEN9_MI_USER_INTERRUPT_MICommandOpcode_start 23 +#define GEN8_MI_USER_INTERRUPT_MICommandOpcode_start 23 +#define GEN75_MI_USER_INTERRUPT_MICommandOpcode_start 23 +#define GEN7_MI_USER_INTERRUPT_MICommandOpcode_start 23 +#define GEN6_MI_USER_INTERRUPT_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_USER_INTERRUPT_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 23; + } else { + return 23; + } + case 6: return 23; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT */ + + +#define GEN11_MI_WAIT_FOR_EVENT_length 1 +#define GEN10_MI_WAIT_FOR_EVENT_length 1 +#define GEN9_MI_WAIT_FOR_EVENT_length 1 +#define GEN8_MI_WAIT_FOR_EVENT_length 1 +#define GEN75_MI_WAIT_FOR_EVENT_length 1 +#define GEN7_MI_WAIT_FOR_EVENT_length 1 +#define GEN6_MI_WAIT_FOR_EVENT_length 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT::Command Type */ + + +#define GEN11_MI_WAIT_FOR_EVENT_CommandType_bits 3 +#define GEN10_MI_WAIT_FOR_EVENT_CommandType_bits 3 +#define GEN9_MI_WAIT_FOR_EVENT_CommandType_bits 3 +#define GEN8_MI_WAIT_FOR_EVENT_CommandType_bits 3 +#define GEN75_MI_WAIT_FOR_EVENT_CommandType_bits 3 +#define GEN7_MI_WAIT_FOR_EVENT_CommandType_bits 3 +#define GEN6_MI_WAIT_FOR_EVENT_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_WAIT_FOR_EVENT_CommandType_start 29 +#define GEN10_MI_WAIT_FOR_EVENT_CommandType_start 29 +#define GEN9_MI_WAIT_FOR_EVENT_CommandType_start 29 +#define GEN8_MI_WAIT_FOR_EVENT_CommandType_start 29 +#define GEN75_MI_WAIT_FOR_EVENT_CommandType_start 29 +#define GEN7_MI_WAIT_FOR_EVENT_CommandType_start 29 +#define GEN6_MI_WAIT_FOR_EVENT_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT::Condition Code Wait Select */ + + +#define GEN75_MI_WAIT_FOR_EVENT_ConditionCodeWaitSelect_bits 4 +#define GEN7_MI_WAIT_FOR_EVENT_ConditionCodeWaitSelect_bits 4 +#define GEN6_MI_WAIT_FOR_EVENT_ConditionCodeWaitSelect_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_ConditionCodeWaitSelect_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_MI_WAIT_FOR_EVENT_ConditionCodeWaitSelect_start 16 +#define GEN7_MI_WAIT_FOR_EVENT_ConditionCodeWaitSelect_start 16 +#define GEN6_MI_WAIT_FOR_EVENT_ConditionCodeWaitSelect_start 16 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_ConditionCodeWaitSelect_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT::Display Pipe A Horizontal Blank Wait Enable */ + + +#define GEN75_MI_WAIT_FOR_EVENT_DisplayPipeAHorizontalBlankWaitEnable_bits 1 +#define GEN7_MI_WAIT_FOR_EVENT_DisplayPipeAHorizontalBlankWaitEnable_bits 1 +#define GEN6_MI_WAIT_FOR_EVENT_DisplayPipeAHorizontalBlankWaitEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPipeAHorizontalBlankWaitEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_MI_WAIT_FOR_EVENT_DisplayPipeAHorizontalBlankWaitEnable_start 5 +#define GEN7_MI_WAIT_FOR_EVENT_DisplayPipeAHorizontalBlankWaitEnable_start 5 +#define GEN6_MI_WAIT_FOR_EVENT_DisplayPipeAHorizontalBlankWaitEnable_start 5 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPipeAHorizontalBlankWaitEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 5; + } + case 6: return 5; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT::Display Pipe A Scan Line Wait Enable */ + + +#define GEN8_MI_WAIT_FOR_EVENT_DisplayPipeAScanLineWaitEnable_bits 1 +#define GEN75_MI_WAIT_FOR_EVENT_DisplayPipeAScanLineWaitEnable_bits 1 +#define GEN7_MI_WAIT_FOR_EVENT_DisplayPipeAScanLineWaitEnable_bits 1 +#define GEN6_MI_WAIT_FOR_EVENT_DisplayPipeAScanLineWaitEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPipeAScanLineWaitEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_MI_WAIT_FOR_EVENT_DisplayPipeAScanLineWaitEnable_start 0 +#define GEN75_MI_WAIT_FOR_EVENT_DisplayPipeAScanLineWaitEnable_start 0 +#define GEN7_MI_WAIT_FOR_EVENT_DisplayPipeAScanLineWaitEnable_start 0 +#define GEN6_MI_WAIT_FOR_EVENT_DisplayPipeAScanLineWaitEnable_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPipeAScanLineWaitEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT::Display Pipe A Vertical Blank Wait Enable */ + + +#define GEN8_MI_WAIT_FOR_EVENT_DisplayPipeAVerticalBlankWaitEnable_bits 1 +#define GEN75_MI_WAIT_FOR_EVENT_DisplayPipeAVerticalBlankWaitEnable_bits 1 +#define GEN7_MI_WAIT_FOR_EVENT_DisplayPipeAVerticalBlankWaitEnable_bits 1 +#define GEN6_MI_WAIT_FOR_EVENT_DisplayPipeAVerticalBlankWaitEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPipeAVerticalBlankWaitEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_MI_WAIT_FOR_EVENT_DisplayPipeAVerticalBlankWaitEnable_start 3 +#define GEN75_MI_WAIT_FOR_EVENT_DisplayPipeAVerticalBlankWaitEnable_start 3 +#define GEN7_MI_WAIT_FOR_EVENT_DisplayPipeAVerticalBlankWaitEnable_start 3 +#define GEN6_MI_WAIT_FOR_EVENT_DisplayPipeAVerticalBlankWaitEnable_start 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPipeAVerticalBlankWaitEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT::Display Pipe B Horizontal Blank Wait Enable */ + + +#define GEN75_MI_WAIT_FOR_EVENT_DisplayPipeBHorizontalBlankWaitEnable_bits 1 +#define GEN7_MI_WAIT_FOR_EVENT_DisplayPipeBHorizontalBlankWaitEnable_bits 1 +#define GEN6_MI_WAIT_FOR_EVENT_DisplayPipeBHorizontalBlankWaitEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPipeBHorizontalBlankWaitEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_MI_WAIT_FOR_EVENT_DisplayPipeBHorizontalBlankWaitEnable_start 13 +#define GEN7_MI_WAIT_FOR_EVENT_DisplayPipeBHorizontalBlankWaitEnable_start 13 +#define GEN6_MI_WAIT_FOR_EVENT_DisplayPipeBHorizontalBlankWaitEnable_start 13 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPipeBHorizontalBlankWaitEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 13; + } else { + return 13; + } + case 6: return 13; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT::Display Pipe B Scan Line Wait Enable */ + + +#define GEN8_MI_WAIT_FOR_EVENT_DisplayPipeBScanLineWaitEnable_bits 1 +#define GEN75_MI_WAIT_FOR_EVENT_DisplayPipeBScanLineWaitEnable_bits 1 +#define GEN7_MI_WAIT_FOR_EVENT_DisplayPipeBScanLineWaitEnable_bits 1 +#define GEN6_MI_WAIT_FOR_EVENT_DisplayPipeBScanLineWaitEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPipeBScanLineWaitEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_MI_WAIT_FOR_EVENT_DisplayPipeBScanLineWaitEnable_start 8 +#define GEN75_MI_WAIT_FOR_EVENT_DisplayPipeBScanLineWaitEnable_start 8 +#define GEN7_MI_WAIT_FOR_EVENT_DisplayPipeBScanLineWaitEnable_start 8 +#define GEN6_MI_WAIT_FOR_EVENT_DisplayPipeBScanLineWaitEnable_start 8 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPipeBScanLineWaitEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT::Display Pipe B Vertical Blank Wait Enable */ + + +#define GEN8_MI_WAIT_FOR_EVENT_DisplayPipeBVerticalBlankWaitEnable_bits 1 +#define GEN75_MI_WAIT_FOR_EVENT_DisplayPipeBVerticalBlankWaitEnable_bits 1 +#define GEN7_MI_WAIT_FOR_EVENT_DisplayPipeBVerticalBlankWaitEnable_bits 1 +#define GEN6_MI_WAIT_FOR_EVENT_DisplayPipeBVerticalBlankWaitEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPipeBVerticalBlankWaitEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_MI_WAIT_FOR_EVENT_DisplayPipeBVerticalBlankWaitEnable_start 11 +#define GEN75_MI_WAIT_FOR_EVENT_DisplayPipeBVerticalBlankWaitEnable_start 11 +#define GEN7_MI_WAIT_FOR_EVENT_DisplayPipeBVerticalBlankWaitEnable_start 11 +#define GEN6_MI_WAIT_FOR_EVENT_DisplayPipeBVerticalBlankWaitEnable_start 11 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPipeBVerticalBlankWaitEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 11; + } else { + return 11; + } + case 6: return 11; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT::Display Pipe C Horizontal Blank Wait Enable */ + + +#define GEN75_MI_WAIT_FOR_EVENT_DisplayPipeCHorizontalBlankWaitEnable_bits 1 +#define GEN7_MI_WAIT_FOR_EVENT_DisplayPipeCHorizontalBlankWaitEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPipeCHorizontalBlankWaitEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_MI_WAIT_FOR_EVENT_DisplayPipeCHorizontalBlankWaitEnable_start 22 +#define GEN7_MI_WAIT_FOR_EVENT_DisplayPipeCHorizontalBlankWaitEnable_start 22 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPipeCHorizontalBlankWaitEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 22; + } else { + return 22; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT::Display Pipe C Scan Line Wait Enable */ + + +#define GEN8_MI_WAIT_FOR_EVENT_DisplayPipeCScanLineWaitEnable_bits 1 +#define GEN75_MI_WAIT_FOR_EVENT_DisplayPipeCScanLineWaitEnable_bits 1 +#define GEN7_MI_WAIT_FOR_EVENT_DisplayPipeCScanLineWaitEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPipeCScanLineWaitEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_MI_WAIT_FOR_EVENT_DisplayPipeCScanLineWaitEnable_start 14 +#define GEN75_MI_WAIT_FOR_EVENT_DisplayPipeCScanLineWaitEnable_start 14 +#define GEN7_MI_WAIT_FOR_EVENT_DisplayPipeCScanLineWaitEnable_start 14 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPipeCScanLineWaitEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 14; + case 7: + if (devinfo->is_haswell) { + return 14; + } else { + return 14; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT::Display Pipe C Vertical Blank Wait Enable */ + + +#define GEN8_MI_WAIT_FOR_EVENT_DisplayPipeCVerticalBlankWaitEnable_bits 1 +#define GEN75_MI_WAIT_FOR_EVENT_DisplayPipeCVerticalBlankWaitEnable_bits 1 +#define GEN7_MI_WAIT_FOR_EVENT_DisplayPipeCVerticalBlankWaitEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPipeCVerticalBlankWaitEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_MI_WAIT_FOR_EVENT_DisplayPipeCVerticalBlankWaitEnable_start 21 +#define GEN75_MI_WAIT_FOR_EVENT_DisplayPipeCVerticalBlankWaitEnable_start 21 +#define GEN7_MI_WAIT_FOR_EVENT_DisplayPipeCVerticalBlankWaitEnable_start 21 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPipeCVerticalBlankWaitEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 21; + case 7: + if (devinfo->is_haswell) { + return 21; + } else { + return 21; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT::Display Plane 1 A Vertical Blank Wait Enable */ + + +#define GEN11_MI_WAIT_FOR_EVENT_DisplayPlane1AVerticalBlankWaitEnable_bits 1 +#define GEN10_MI_WAIT_FOR_EVENT_DisplayPlane1AVerticalBlankWaitEnable_bits 1 +#define GEN9_MI_WAIT_FOR_EVENT_DisplayPlane1AVerticalBlankWaitEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlane1AVerticalBlankWaitEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_WAIT_FOR_EVENT_DisplayPlane1AVerticalBlankWaitEnable_start 3 +#define GEN10_MI_WAIT_FOR_EVENT_DisplayPlane1AVerticalBlankWaitEnable_start 3 +#define GEN9_MI_WAIT_FOR_EVENT_DisplayPlane1AVerticalBlankWaitEnable_start 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlane1AVerticalBlankWaitEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT::Display Plane 1 B Scan Line Wait Enable */ + + +#define GEN11_MI_WAIT_FOR_EVENT_DisplayPlane1BScanLineWaitEnable_bits 1 +#define GEN10_MI_WAIT_FOR_EVENT_DisplayPlane1BScanLineWaitEnable_bits 1 +#define GEN9_MI_WAIT_FOR_EVENT_DisplayPlane1BScanLineWaitEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlane1BScanLineWaitEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_WAIT_FOR_EVENT_DisplayPlane1BScanLineWaitEnable_start 8 +#define GEN10_MI_WAIT_FOR_EVENT_DisplayPlane1BScanLineWaitEnable_start 8 +#define GEN9_MI_WAIT_FOR_EVENT_DisplayPlane1BScanLineWaitEnable_start 8 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlane1BScanLineWaitEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT::Display Plane 1 B Vertical Blank Wait Enable */ + + +#define GEN11_MI_WAIT_FOR_EVENT_DisplayPlane1BVerticalBlankWaitEnable_bits 1 +#define GEN10_MI_WAIT_FOR_EVENT_DisplayPlane1BVerticalBlankWaitEnable_bits 1 +#define GEN9_MI_WAIT_FOR_EVENT_DisplayPlane1BVerticalBlankWaitEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlane1BVerticalBlankWaitEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_WAIT_FOR_EVENT_DisplayPlane1BVerticalBlankWaitEnable_start 11 +#define GEN10_MI_WAIT_FOR_EVENT_DisplayPlane1BVerticalBlankWaitEnable_start 11 +#define GEN9_MI_WAIT_FOR_EVENT_DisplayPlane1BVerticalBlankWaitEnable_start 11 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlane1BVerticalBlankWaitEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT::Display Plane 1 C Scan Line Wait Enable */ + + +#define GEN11_MI_WAIT_FOR_EVENT_DisplayPlane1CScanLineWaitEnable_bits 1 +#define GEN10_MI_WAIT_FOR_EVENT_DisplayPlane1CScanLineWaitEnable_bits 1 +#define GEN9_MI_WAIT_FOR_EVENT_DisplayPlane1CScanLineWaitEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlane1CScanLineWaitEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_WAIT_FOR_EVENT_DisplayPlane1CScanLineWaitEnable_start 14 +#define GEN10_MI_WAIT_FOR_EVENT_DisplayPlane1CScanLineWaitEnable_start 14 +#define GEN9_MI_WAIT_FOR_EVENT_DisplayPlane1CScanLineWaitEnable_start 14 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlane1CScanLineWaitEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 14; + case 10: return 14; + case 9: return 14; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT::Display Plane 1 C Vertical Blank Wait Enable */ + + +#define GEN11_MI_WAIT_FOR_EVENT_DisplayPlane1CVerticalBlankWaitEnable_bits 1 +#define GEN10_MI_WAIT_FOR_EVENT_DisplayPlane1CVerticalBlankWaitEnable_bits 1 +#define GEN9_MI_WAIT_FOR_EVENT_DisplayPlane1CVerticalBlankWaitEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlane1CVerticalBlankWaitEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_WAIT_FOR_EVENT_DisplayPlane1CVerticalBlankWaitEnable_start 21 +#define GEN10_MI_WAIT_FOR_EVENT_DisplayPlane1CVerticalBlankWaitEnable_start 21 +#define GEN9_MI_WAIT_FOR_EVENT_DisplayPlane1CVerticalBlankWaitEnable_start 21 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlane1CVerticalBlankWaitEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 21; + case 10: return 21; + case 9: return 21; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT::Display Plane 1 Flip Pending Wait Enable */ + + +#define GEN11_MI_WAIT_FOR_EVENT_DisplayPlane1FlipPendingWaitEnable_bits 1 +#define GEN10_MI_WAIT_FOR_EVENT_DisplayPlane1FlipPendingWaitEnable_bits 1 +#define GEN9_MI_WAIT_FOR_EVENT_DisplayPlane1FlipPendingWaitEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlane1FlipPendingWaitEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_WAIT_FOR_EVENT_DisplayPlane1FlipPendingWaitEnable_start 1 +#define GEN10_MI_WAIT_FOR_EVENT_DisplayPlane1FlipPendingWaitEnable_start 1 +#define GEN9_MI_WAIT_FOR_EVENT_DisplayPlane1FlipPendingWaitEnable_start 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlane1FlipPendingWaitEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT::Display Plane 10 Flip Pending Wait Enable */ + + +#define GEN11_MI_WAIT_FOR_EVENT_DisplayPlane10FlipPendingWaitEnable_bits 1 +#define GEN10_MI_WAIT_FOR_EVENT_DisplayPlane10FlipPendingWaitEnable_bits 1 +#define GEN9_MI_WAIT_FOR_EVENT_DisplayPlane10FlipPendingWaitEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlane10FlipPendingWaitEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_WAIT_FOR_EVENT_DisplayPlane10FlipPendingWaitEnable_start 17 +#define GEN10_MI_WAIT_FOR_EVENT_DisplayPlane10FlipPendingWaitEnable_start 17 +#define GEN9_MI_WAIT_FOR_EVENT_DisplayPlane10FlipPendingWaitEnable_start 17 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlane10FlipPendingWaitEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 17; + case 10: return 17; + case 9: return 17; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT::Display Plane 11 Flip Pending Wait Enable */ + + +#define GEN11_MI_WAIT_FOR_EVENT_DisplayPlane11FlipPendingWaitEnable_bits 1 +#define GEN10_MI_WAIT_FOR_EVENT_DisplayPlane11FlipPendingWaitEnable_bits 1 +#define GEN9_MI_WAIT_FOR_EVENT_DisplayPlane11FlipPendingWaitEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlane11FlipPendingWaitEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_WAIT_FOR_EVENT_DisplayPlane11FlipPendingWaitEnable_start 18 +#define GEN10_MI_WAIT_FOR_EVENT_DisplayPlane11FlipPendingWaitEnable_start 18 +#define GEN9_MI_WAIT_FOR_EVENT_DisplayPlane11FlipPendingWaitEnable_start 18 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlane11FlipPendingWaitEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 18; + case 10: return 18; + case 9: return 18; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT::Display Plane 12 Flip Pending Wait Enable */ + + +#define GEN11_MI_WAIT_FOR_EVENT_DisplayPlane12FlipPendingWaitEnable_bits 1 +#define GEN10_MI_WAIT_FOR_EVENT_DisplayPlane12FlipPendingWaitEnable_bits 1 +#define GEN9_MI_WAIT_FOR_EVENT_DisplayPlane12FlipPendingWaitEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlane12FlipPendingWaitEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_WAIT_FOR_EVENT_DisplayPlane12FlipPendingWaitEnable_start 19 +#define GEN10_MI_WAIT_FOR_EVENT_DisplayPlane12FlipPendingWaitEnable_start 19 +#define GEN9_MI_WAIT_FOR_EVENT_DisplayPlane12FlipPendingWaitEnable_start 19 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlane12FlipPendingWaitEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 19; + case 10: return 19; + case 9: return 19; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT::Display Plane 2 Flip Pending Wait Enable */ + + +#define GEN11_MI_WAIT_FOR_EVENT_DisplayPlane2FlipPendingWaitEnable_bits 1 +#define GEN10_MI_WAIT_FOR_EVENT_DisplayPlane2FlipPendingWaitEnable_bits 1 +#define GEN9_MI_WAIT_FOR_EVENT_DisplayPlane2FlipPendingWaitEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlane2FlipPendingWaitEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_WAIT_FOR_EVENT_DisplayPlane2FlipPendingWaitEnable_start 9 +#define GEN10_MI_WAIT_FOR_EVENT_DisplayPlane2FlipPendingWaitEnable_start 9 +#define GEN9_MI_WAIT_FOR_EVENT_DisplayPlane2FlipPendingWaitEnable_start 9 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlane2FlipPendingWaitEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 9; + case 10: return 9; + case 9: return 9; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT::Display Plane 3 Flip Pending Wait Enable */ + + +#define GEN11_MI_WAIT_FOR_EVENT_DisplayPlane3FlipPendingWaitEnable_bits 1 +#define GEN10_MI_WAIT_FOR_EVENT_DisplayPlane3FlipPendingWaitEnable_bits 1 +#define GEN9_MI_WAIT_FOR_EVENT_DisplayPlane3FlipPendingWaitEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlane3FlipPendingWaitEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_WAIT_FOR_EVENT_DisplayPlane3FlipPendingWaitEnable_start 15 +#define GEN10_MI_WAIT_FOR_EVENT_DisplayPlane3FlipPendingWaitEnable_start 15 +#define GEN9_MI_WAIT_FOR_EVENT_DisplayPlane3FlipPendingWaitEnable_start 15 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlane3FlipPendingWaitEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 15; + case 10: return 15; + case 9: return 15; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT::Display Plane 4 Flip Pending Wait Enable */ + + +#define GEN11_MI_WAIT_FOR_EVENT_DisplayPlane4FlipPendingWaitEnable_bits 1 +#define GEN10_MI_WAIT_FOR_EVENT_DisplayPlane4FlipPendingWaitEnable_bits 1 +#define GEN9_MI_WAIT_FOR_EVENT_DisplayPlane4FlipPendingWaitEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlane4FlipPendingWaitEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_WAIT_FOR_EVENT_DisplayPlane4FlipPendingWaitEnable_start 2 +#define GEN10_MI_WAIT_FOR_EVENT_DisplayPlane4FlipPendingWaitEnable_start 2 +#define GEN9_MI_WAIT_FOR_EVENT_DisplayPlane4FlipPendingWaitEnable_start 2 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlane4FlipPendingWaitEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT::Display Plane 5 Flip Pending Wait Enable */ + + +#define GEN11_MI_WAIT_FOR_EVENT_DisplayPlane5FlipPendingWaitEnable_bits 1 +#define GEN10_MI_WAIT_FOR_EVENT_DisplayPlane5FlipPendingWaitEnable_bits 1 +#define GEN9_MI_WAIT_FOR_EVENT_DisplayPlane5FlipPendingWaitEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlane5FlipPendingWaitEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_WAIT_FOR_EVENT_DisplayPlane5FlipPendingWaitEnable_start 10 +#define GEN10_MI_WAIT_FOR_EVENT_DisplayPlane5FlipPendingWaitEnable_start 10 +#define GEN9_MI_WAIT_FOR_EVENT_DisplayPlane5FlipPendingWaitEnable_start 10 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlane5FlipPendingWaitEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 10; + case 10: return 10; + case 9: return 10; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT::Display Plane 6 Flip Pending Wait Enable */ + + +#define GEN11_MI_WAIT_FOR_EVENT_DisplayPlane6FlipPendingWaitEnable_bits 1 +#define GEN10_MI_WAIT_FOR_EVENT_DisplayPlane6FlipPendingWaitEnable_bits 1 +#define GEN9_MI_WAIT_FOR_EVENT_DisplayPlane6FlipPendingWaitEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlane6FlipPendingWaitEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_WAIT_FOR_EVENT_DisplayPlane6FlipPendingWaitEnable_start 20 +#define GEN10_MI_WAIT_FOR_EVENT_DisplayPlane6FlipPendingWaitEnable_start 20 +#define GEN9_MI_WAIT_FOR_EVENT_DisplayPlane6FlipPendingWaitEnable_start 20 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlane6FlipPendingWaitEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 20; + case 10: return 20; + case 9: return 20; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT::Display Plane 7 Flip Pending Wait Enable */ + + +#define GEN11_MI_WAIT_FOR_EVENT_DisplayPlane7FlipPendingWaitEnable_bits 1 +#define GEN10_MI_WAIT_FOR_EVENT_DisplayPlane7FlipPendingWaitEnable_bits 1 +#define GEN9_MI_WAIT_FOR_EVENT_DisplayPlane7FlipPendingWaitEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlane7FlipPendingWaitEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_WAIT_FOR_EVENT_DisplayPlane7FlipPendingWaitEnable_start 6 +#define GEN10_MI_WAIT_FOR_EVENT_DisplayPlane7FlipPendingWaitEnable_start 6 +#define GEN9_MI_WAIT_FOR_EVENT_DisplayPlane7FlipPendingWaitEnable_start 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlane7FlipPendingWaitEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT::Display Plane 8 Flip Pending Wait Enable */ + + +#define GEN11_MI_WAIT_FOR_EVENT_DisplayPlane8FlipPendingWaitEnable_bits 1 +#define GEN10_MI_WAIT_FOR_EVENT_DisplayPlane8FlipPendingWaitEnable_bits 1 +#define GEN9_MI_WAIT_FOR_EVENT_DisplayPlane8FlipPendingWaitEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlane8FlipPendingWaitEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_WAIT_FOR_EVENT_DisplayPlane8FlipPendingWaitEnable_start 7 +#define GEN10_MI_WAIT_FOR_EVENT_DisplayPlane8FlipPendingWaitEnable_start 7 +#define GEN9_MI_WAIT_FOR_EVENT_DisplayPlane8FlipPendingWaitEnable_start 7 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlane8FlipPendingWaitEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT::Display Plane 9 Flip Pending Wait Enable */ + + +#define GEN11_MI_WAIT_FOR_EVENT_DisplayPlane9FlipPendingWaitEnable_bits 1 +#define GEN10_MI_WAIT_FOR_EVENT_DisplayPlane9FlipPendingWaitEnable_bits 1 +#define GEN9_MI_WAIT_FOR_EVENT_DisplayPlane9FlipPendingWaitEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlane9FlipPendingWaitEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_WAIT_FOR_EVENT_DisplayPlane9FlipPendingWaitEnable_start 16 +#define GEN10_MI_WAIT_FOR_EVENT_DisplayPlane9FlipPendingWaitEnable_start 16 +#define GEN9_MI_WAIT_FOR_EVENT_DisplayPlane9FlipPendingWaitEnable_start 16 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlane9FlipPendingWaitEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT::Display Plane A Flip Pending Wait Enable */ + + +#define GEN8_MI_WAIT_FOR_EVENT_DisplayPlaneAFlipPendingWaitEnable_bits 1 +#define GEN75_MI_WAIT_FOR_EVENT_DisplayPlaneAFlipPendingWaitEnable_bits 1 +#define GEN7_MI_WAIT_FOR_EVENT_DisplayPlaneAFlipPendingWaitEnable_bits 1 +#define GEN6_MI_WAIT_FOR_EVENT_DisplayPlaneAFlipPendingWaitEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlaneAFlipPendingWaitEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_MI_WAIT_FOR_EVENT_DisplayPlaneAFlipPendingWaitEnable_start 1 +#define GEN75_MI_WAIT_FOR_EVENT_DisplayPlaneAFlipPendingWaitEnable_start 1 +#define GEN7_MI_WAIT_FOR_EVENT_DisplayPlaneAFlipPendingWaitEnable_start 1 +#define GEN6_MI_WAIT_FOR_EVENT_DisplayPlaneAFlipPendingWaitEnable_start 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlaneAFlipPendingWaitEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT::Display Plane B Flip Pending Wait Enable */ + + +#define GEN8_MI_WAIT_FOR_EVENT_DisplayPlaneBFlipPendingWaitEnable_bits 1 +#define GEN75_MI_WAIT_FOR_EVENT_DisplayPlaneBFlipPendingWaitEnable_bits 1 +#define GEN7_MI_WAIT_FOR_EVENT_DisplayPlaneBFlipPendingWaitEnable_bits 1 +#define GEN6_MI_WAIT_FOR_EVENT_DisplayPlaneBFlipPendingWaitEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlaneBFlipPendingWaitEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_MI_WAIT_FOR_EVENT_DisplayPlaneBFlipPendingWaitEnable_start 9 +#define GEN75_MI_WAIT_FOR_EVENT_DisplayPlaneBFlipPendingWaitEnable_start 9 +#define GEN7_MI_WAIT_FOR_EVENT_DisplayPlaneBFlipPendingWaitEnable_start 9 +#define GEN6_MI_WAIT_FOR_EVENT_DisplayPlaneBFlipPendingWaitEnable_start 9 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlaneBFlipPendingWaitEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 9; + } + case 6: return 9; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT::Display Plane C Flip Pending Wait Enable */ + + +#define GEN8_MI_WAIT_FOR_EVENT_DisplayPlaneCFlipPendingWaitEnable_bits 1 +#define GEN75_MI_WAIT_FOR_EVENT_DisplayPlaneCFlipPendingWaitEnable_bits 1 +#define GEN7_MI_WAIT_FOR_EVENT_DisplayPlaneCFlipPendingWaitEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlaneCFlipPendingWaitEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_MI_WAIT_FOR_EVENT_DisplayPlaneCFlipPendingWaitEnable_start 15 +#define GEN75_MI_WAIT_FOR_EVENT_DisplayPlaneCFlipPendingWaitEnable_start 15 +#define GEN7_MI_WAIT_FOR_EVENT_DisplayPlaneCFlipPendingWaitEnable_start 15 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlaneCFlipPendingWaitEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 15; + case 7: + if (devinfo->is_haswell) { + return 15; + } else { + return 15; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT::Display Plnae 1 A Scan Line Wait Enable */ + + +#define GEN11_MI_WAIT_FOR_EVENT_DisplayPlnae1AScanLineWaitEnable_bits 1 +#define GEN10_MI_WAIT_FOR_EVENT_DisplayPlnae1AScanLineWaitEnable_bits 1 +#define GEN9_MI_WAIT_FOR_EVENT_DisplayPlnae1AScanLineWaitEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlnae1AScanLineWaitEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_WAIT_FOR_EVENT_DisplayPlnae1AScanLineWaitEnable_start 0 +#define GEN10_MI_WAIT_FOR_EVENT_DisplayPlnae1AScanLineWaitEnable_start 0 +#define GEN9_MI_WAIT_FOR_EVENT_DisplayPlnae1AScanLineWaitEnable_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplayPlnae1AScanLineWaitEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT::Display Sprite A Flip Pending Wait Enable */ + + +#define GEN8_MI_WAIT_FOR_EVENT_DisplaySpriteAFlipPendingWaitEnable_bits 1 +#define GEN75_MI_WAIT_FOR_EVENT_DisplaySpriteAFlipPendingWaitEnable_bits 1 +#define GEN7_MI_WAIT_FOR_EVENT_DisplaySpriteAFlipPendingWaitEnable_bits 1 +#define GEN6_MI_WAIT_FOR_EVENT_DisplaySpriteAFlipPendingWaitEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplaySpriteAFlipPendingWaitEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_MI_WAIT_FOR_EVENT_DisplaySpriteAFlipPendingWaitEnable_start 2 +#define GEN75_MI_WAIT_FOR_EVENT_DisplaySpriteAFlipPendingWaitEnable_start 2 +#define GEN7_MI_WAIT_FOR_EVENT_DisplaySpriteAFlipPendingWaitEnable_start 2 +#define GEN6_MI_WAIT_FOR_EVENT_DisplaySpriteAFlipPendingWaitEnable_start 2 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplaySpriteAFlipPendingWaitEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT::Display Sprite B Flip Pending Wait Enable */ + + +#define GEN8_MI_WAIT_FOR_EVENT_DisplaySpriteBFlipPendingWaitEnable_bits 1 +#define GEN75_MI_WAIT_FOR_EVENT_DisplaySpriteBFlipPendingWaitEnable_bits 1 +#define GEN7_MI_WAIT_FOR_EVENT_DisplaySpriteBFlipPendingWaitEnable_bits 1 +#define GEN6_MI_WAIT_FOR_EVENT_DisplaySpriteBFlipPendingWaitEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplaySpriteBFlipPendingWaitEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_MI_WAIT_FOR_EVENT_DisplaySpriteBFlipPendingWaitEnable_start 10 +#define GEN75_MI_WAIT_FOR_EVENT_DisplaySpriteBFlipPendingWaitEnable_start 10 +#define GEN7_MI_WAIT_FOR_EVENT_DisplaySpriteBFlipPendingWaitEnable_start 10 +#define GEN6_MI_WAIT_FOR_EVENT_DisplaySpriteBFlipPendingWaitEnable_start 10 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplaySpriteBFlipPendingWaitEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 10; + case 7: + if (devinfo->is_haswell) { + return 10; + } else { + return 10; + } + case 6: return 10; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT::Display Sprite C Flip Pending Wait Enable */ + + +#define GEN8_MI_WAIT_FOR_EVENT_DisplaySpriteCFlipPendingWaitEnable_bits 1 +#define GEN75_MI_WAIT_FOR_EVENT_DisplaySpriteCFlipPendingWaitEnable_bits 1 +#define GEN7_MI_WAIT_FOR_EVENT_DisplaySpriteCFlipPendingWaitEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplaySpriteCFlipPendingWaitEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_MI_WAIT_FOR_EVENT_DisplaySpriteCFlipPendingWaitEnable_start 20 +#define GEN75_MI_WAIT_FOR_EVENT_DisplaySpriteCFlipPendingWaitEnable_start 20 +#define GEN7_MI_WAIT_FOR_EVENT_DisplaySpriteCFlipPendingWaitEnable_start 20 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_DisplaySpriteCFlipPendingWaitEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 20; + case 7: + if (devinfo->is_haswell) { + return 20; + } else { + return 20; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT::MI Command Opcode */ + + +#define GEN11_MI_WAIT_FOR_EVENT_MICommandOpcode_bits 6 +#define GEN10_MI_WAIT_FOR_EVENT_MICommandOpcode_bits 6 +#define GEN9_MI_WAIT_FOR_EVENT_MICommandOpcode_bits 6 +#define GEN8_MI_WAIT_FOR_EVENT_MICommandOpcode_bits 6 +#define GEN75_MI_WAIT_FOR_EVENT_MICommandOpcode_bits 6 +#define GEN7_MI_WAIT_FOR_EVENT_MICommandOpcode_bits 6 +#define GEN6_MI_WAIT_FOR_EVENT_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 6; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_WAIT_FOR_EVENT_MICommandOpcode_start 23 +#define GEN10_MI_WAIT_FOR_EVENT_MICommandOpcode_start 23 +#define GEN9_MI_WAIT_FOR_EVENT_MICommandOpcode_start 23 +#define GEN8_MI_WAIT_FOR_EVENT_MICommandOpcode_start 23 +#define GEN75_MI_WAIT_FOR_EVENT_MICommandOpcode_start 23 +#define GEN7_MI_WAIT_FOR_EVENT_MICommandOpcode_start 23 +#define GEN6_MI_WAIT_FOR_EVENT_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 23; + } else { + return 23; + } + case 6: return 23; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT_2 */ + + +#define GEN11_MI_WAIT_FOR_EVENT_2_length 1 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_2_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT_2::Command Type */ + + +#define GEN11_MI_WAIT_FOR_EVENT_2_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_2_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_WAIT_FOR_EVENT_2_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_2_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT_2::Display Pipe Scan Line Wait Enable */ + + +#define GEN11_MI_WAIT_FOR_EVENT_2_DisplayPipeScanLineWaitEnable_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_2_DisplayPipeScanLineWaitEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_WAIT_FOR_EVENT_2_DisplayPipeScanLineWaitEnable_start 12 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_2_DisplayPipeScanLineWaitEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 12; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT_2::Display Pipe Vertical Blank Wait Enable */ + + +#define GEN11_MI_WAIT_FOR_EVENT_2_DisplayPipeVerticalBlankWaitEnable_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_2_DisplayPipeVerticalBlankWaitEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_WAIT_FOR_EVENT_2_DisplayPipeVerticalBlankWaitEnable_start 8 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_2_DisplayPipeVerticalBlankWaitEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT_2::Display Plane Flip Pending Wait Enable */ + + +#define GEN11_MI_WAIT_FOR_EVENT_2_DisplayPlaneFlipPendingWaitEnable_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_2_DisplayPlaneFlipPendingWaitEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_WAIT_FOR_EVENT_2_DisplayPlaneFlipPendingWaitEnable_start 0 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_2_DisplayPlaneFlipPendingWaitEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* MI_WAIT_FOR_EVENT_2::MI Command Opcode */ + + +#define GEN11_MI_WAIT_FOR_EVENT_2_MICommandOpcode_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_2_MICommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_MI_WAIT_FOR_EVENT_2_MICommandOpcode_start 23 + +static inline uint32_t ATTRIBUTE_PURE +MI_WAIT_FOR_EVENT_2_MICommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PALETTE_ENTRY */ + + +#define GEN11_PALETTE_ENTRY_length 1 +#define GEN10_PALETTE_ENTRY_length 1 +#define GEN9_PALETTE_ENTRY_length 1 +#define GEN8_PALETTE_ENTRY_length 1 +#define GEN75_PALETTE_ENTRY_length 1 +#define GEN7_PALETTE_ENTRY_length 1 +#define GEN6_PALETTE_ENTRY_length 1 + +static inline uint32_t ATTRIBUTE_PURE +PALETTE_ENTRY_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PALETTE_ENTRY::Alpha */ + + +#define GEN11_PALETTE_ENTRY_Alpha_bits 8 +#define GEN10_PALETTE_ENTRY_Alpha_bits 8 +#define GEN9_PALETTE_ENTRY_Alpha_bits 8 +#define GEN8_PALETTE_ENTRY_Alpha_bits 8 +#define GEN75_PALETTE_ENTRY_Alpha_bits 8 +#define GEN7_PALETTE_ENTRY_Alpha_bits 8 +#define GEN6_PALETTE_ENTRY_Alpha_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +PALETTE_ENTRY_Alpha_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PALETTE_ENTRY_Alpha_start 24 +#define GEN10_PALETTE_ENTRY_Alpha_start 24 +#define GEN9_PALETTE_ENTRY_Alpha_start 24 +#define GEN8_PALETTE_ENTRY_Alpha_start 24 +#define GEN75_PALETTE_ENTRY_Alpha_start 24 +#define GEN7_PALETTE_ENTRY_Alpha_start 24 +#define GEN6_PALETTE_ENTRY_Alpha_start 24 + +static inline uint32_t ATTRIBUTE_PURE +PALETTE_ENTRY_Alpha_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PALETTE_ENTRY::Blue */ + + +#define GEN11_PALETTE_ENTRY_Blue_bits 8 +#define GEN10_PALETTE_ENTRY_Blue_bits 8 +#define GEN9_PALETTE_ENTRY_Blue_bits 8 +#define GEN8_PALETTE_ENTRY_Blue_bits 8 +#define GEN75_PALETTE_ENTRY_Blue_bits 8 +#define GEN7_PALETTE_ENTRY_Blue_bits 8 +#define GEN6_PALETTE_ENTRY_Blue_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +PALETTE_ENTRY_Blue_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PALETTE_ENTRY_Blue_start 0 +#define GEN10_PALETTE_ENTRY_Blue_start 0 +#define GEN9_PALETTE_ENTRY_Blue_start 0 +#define GEN8_PALETTE_ENTRY_Blue_start 0 +#define GEN75_PALETTE_ENTRY_Blue_start 0 +#define GEN7_PALETTE_ENTRY_Blue_start 0 +#define GEN6_PALETTE_ENTRY_Blue_start 0 + +static inline uint32_t ATTRIBUTE_PURE +PALETTE_ENTRY_Blue_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PALETTE_ENTRY::Green */ + + +#define GEN11_PALETTE_ENTRY_Green_bits 8 +#define GEN10_PALETTE_ENTRY_Green_bits 8 +#define GEN9_PALETTE_ENTRY_Green_bits 8 +#define GEN8_PALETTE_ENTRY_Green_bits 8 +#define GEN75_PALETTE_ENTRY_Green_bits 8 +#define GEN7_PALETTE_ENTRY_Green_bits 8 +#define GEN6_PALETTE_ENTRY_Green_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +PALETTE_ENTRY_Green_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PALETTE_ENTRY_Green_start 8 +#define GEN10_PALETTE_ENTRY_Green_start 8 +#define GEN9_PALETTE_ENTRY_Green_start 8 +#define GEN8_PALETTE_ENTRY_Green_start 8 +#define GEN75_PALETTE_ENTRY_Green_start 8 +#define GEN7_PALETTE_ENTRY_Green_start 8 +#define GEN6_PALETTE_ENTRY_Green_start 8 + +static inline uint32_t ATTRIBUTE_PURE +PALETTE_ENTRY_Green_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PALETTE_ENTRY::Red */ + + +#define GEN11_PALETTE_ENTRY_Red_bits 8 +#define GEN10_PALETTE_ENTRY_Red_bits 8 +#define GEN9_PALETTE_ENTRY_Red_bits 8 +#define GEN8_PALETTE_ENTRY_Red_bits 8 +#define GEN75_PALETTE_ENTRY_Red_bits 8 +#define GEN7_PALETTE_ENTRY_Red_bits 8 +#define GEN6_PALETTE_ENTRY_Red_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +PALETTE_ENTRY_Red_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PALETTE_ENTRY_Red_start 16 +#define GEN10_PALETTE_ENTRY_Red_start 16 +#define GEN9_PALETTE_ENTRY_Red_start 16 +#define GEN8_PALETTE_ENTRY_Red_start 16 +#define GEN75_PALETTE_ENTRY_Red_start 16 +#define GEN7_PALETTE_ENTRY_Red_start 16 +#define GEN6_PALETTE_ENTRY_Red_start 16 + +static inline uint32_t ATTRIBUTE_PURE +PALETTE_ENTRY_Red_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPELINE_SELECT */ + + +#define GEN11_PIPELINE_SELECT_length 1 +#define GEN10_PIPELINE_SELECT_length 1 +#define GEN9_PIPELINE_SELECT_length 1 +#define GEN8_PIPELINE_SELECT_length 1 +#define GEN75_PIPELINE_SELECT_length 1 +#define GEN7_PIPELINE_SELECT_length 1 +#define GEN6_PIPELINE_SELECT_length 1 +#define GEN5_PIPELINE_SELECT_length 1 +#define GEN45_PIPELINE_SELECT_length 1 +#define GEN4_PIPELINE_SELECT_length 1 + +static inline uint32_t ATTRIBUTE_PURE +PIPELINE_SELECT_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPELINE_SELECT::3D Command Opcode */ + + +#define GEN11_PIPELINE_SELECT_3DCommandOpcode_bits 3 +#define GEN10_PIPELINE_SELECT_3DCommandOpcode_bits 3 +#define GEN9_PIPELINE_SELECT_3DCommandOpcode_bits 3 +#define GEN8_PIPELINE_SELECT_3DCommandOpcode_bits 3 +#define GEN75_PIPELINE_SELECT_3DCommandOpcode_bits 3 +#define GEN7_PIPELINE_SELECT_3DCommandOpcode_bits 3 +#define GEN6_PIPELINE_SELECT_3DCommandOpcode_bits 3 +#define GEN5_PIPELINE_SELECT_3DCommandOpcode_bits 3 +#define GEN45_PIPELINE_SELECT_3DCommandOpcode_bits 3 +#define GEN4_PIPELINE_SELECT_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +PIPELINE_SELECT_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PIPELINE_SELECT_3DCommandOpcode_start 24 +#define GEN10_PIPELINE_SELECT_3DCommandOpcode_start 24 +#define GEN9_PIPELINE_SELECT_3DCommandOpcode_start 24 +#define GEN8_PIPELINE_SELECT_3DCommandOpcode_start 24 +#define GEN75_PIPELINE_SELECT_3DCommandOpcode_start 24 +#define GEN7_PIPELINE_SELECT_3DCommandOpcode_start 24 +#define GEN6_PIPELINE_SELECT_3DCommandOpcode_start 24 +#define GEN5_PIPELINE_SELECT_3DCommandOpcode_start 24 +#define GEN45_PIPELINE_SELECT_3DCommandOpcode_start 24 +#define GEN4_PIPELINE_SELECT_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +PIPELINE_SELECT_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 24; + case 4: + if (devinfo->is_g4x) { + return 24; + } else { + return 24; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPELINE_SELECT::3D Command Sub Opcode */ + + +#define GEN11_PIPELINE_SELECT_3DCommandSubOpcode_bits 8 +#define GEN10_PIPELINE_SELECT_3DCommandSubOpcode_bits 8 +#define GEN9_PIPELINE_SELECT_3DCommandSubOpcode_bits 8 +#define GEN8_PIPELINE_SELECT_3DCommandSubOpcode_bits 8 +#define GEN75_PIPELINE_SELECT_3DCommandSubOpcode_bits 8 +#define GEN7_PIPELINE_SELECT_3DCommandSubOpcode_bits 8 +#define GEN6_PIPELINE_SELECT_3DCommandSubOpcode_bits 8 +#define GEN5_PIPELINE_SELECT_3DCommandSubOpcode_bits 8 +#define GEN45_PIPELINE_SELECT_3DCommandSubOpcode_bits 8 +#define GEN4_PIPELINE_SELECT_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +PIPELINE_SELECT_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PIPELINE_SELECT_3DCommandSubOpcode_start 16 +#define GEN10_PIPELINE_SELECT_3DCommandSubOpcode_start 16 +#define GEN9_PIPELINE_SELECT_3DCommandSubOpcode_start 16 +#define GEN8_PIPELINE_SELECT_3DCommandSubOpcode_start 16 +#define GEN75_PIPELINE_SELECT_3DCommandSubOpcode_start 16 +#define GEN7_PIPELINE_SELECT_3DCommandSubOpcode_start 16 +#define GEN6_PIPELINE_SELECT_3DCommandSubOpcode_start 16 +#define GEN5_PIPELINE_SELECT_3DCommandSubOpcode_start 16 +#define GEN45_PIPELINE_SELECT_3DCommandSubOpcode_start 16 +#define GEN4_PIPELINE_SELECT_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +PIPELINE_SELECT_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPELINE_SELECT::Command SubType */ + + +#define GEN11_PIPELINE_SELECT_CommandSubType_bits 2 +#define GEN10_PIPELINE_SELECT_CommandSubType_bits 2 +#define GEN9_PIPELINE_SELECT_CommandSubType_bits 2 +#define GEN8_PIPELINE_SELECT_CommandSubType_bits 2 +#define GEN75_PIPELINE_SELECT_CommandSubType_bits 2 +#define GEN7_PIPELINE_SELECT_CommandSubType_bits 2 +#define GEN6_PIPELINE_SELECT_CommandSubType_bits 2 +#define GEN5_PIPELINE_SELECT_CommandSubType_bits 2 +#define GEN45_PIPELINE_SELECT_CommandSubType_bits 2 +#define GEN4_PIPELINE_SELECT_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +PIPELINE_SELECT_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PIPELINE_SELECT_CommandSubType_start 27 +#define GEN10_PIPELINE_SELECT_CommandSubType_start 27 +#define GEN9_PIPELINE_SELECT_CommandSubType_start 27 +#define GEN8_PIPELINE_SELECT_CommandSubType_start 27 +#define GEN75_PIPELINE_SELECT_CommandSubType_start 27 +#define GEN7_PIPELINE_SELECT_CommandSubType_start 27 +#define GEN6_PIPELINE_SELECT_CommandSubType_start 27 +#define GEN5_PIPELINE_SELECT_CommandSubType_start 27 +#define GEN45_PIPELINE_SELECT_CommandSubType_start 27 +#define GEN4_PIPELINE_SELECT_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +PIPELINE_SELECT_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPELINE_SELECT::Command Type */ + + +#define GEN11_PIPELINE_SELECT_CommandType_bits 3 +#define GEN10_PIPELINE_SELECT_CommandType_bits 3 +#define GEN9_PIPELINE_SELECT_CommandType_bits 3 +#define GEN8_PIPELINE_SELECT_CommandType_bits 3 +#define GEN75_PIPELINE_SELECT_CommandType_bits 3 +#define GEN7_PIPELINE_SELECT_CommandType_bits 3 +#define GEN6_PIPELINE_SELECT_CommandType_bits 3 +#define GEN5_PIPELINE_SELECT_CommandType_bits 3 +#define GEN45_PIPELINE_SELECT_CommandType_bits 3 +#define GEN4_PIPELINE_SELECT_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +PIPELINE_SELECT_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PIPELINE_SELECT_CommandType_start 29 +#define GEN10_PIPELINE_SELECT_CommandType_start 29 +#define GEN9_PIPELINE_SELECT_CommandType_start 29 +#define GEN8_PIPELINE_SELECT_CommandType_start 29 +#define GEN75_PIPELINE_SELECT_CommandType_start 29 +#define GEN7_PIPELINE_SELECT_CommandType_start 29 +#define GEN6_PIPELINE_SELECT_CommandType_start 29 +#define GEN5_PIPELINE_SELECT_CommandType_start 29 +#define GEN45_PIPELINE_SELECT_CommandType_start 29 +#define GEN4_PIPELINE_SELECT_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +PIPELINE_SELECT_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 29; + case 4: + if (devinfo->is_g4x) { + return 29; + } else { + return 29; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPELINE_SELECT::Force Media Awake */ + + +#define GEN11_PIPELINE_SELECT_ForceMediaAwake_bits 1 +#define GEN10_PIPELINE_SELECT_ForceMediaAwake_bits 1 +#define GEN9_PIPELINE_SELECT_ForceMediaAwake_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +PIPELINE_SELECT_ForceMediaAwake_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PIPELINE_SELECT_ForceMediaAwake_start 5 +#define GEN10_PIPELINE_SELECT_ForceMediaAwake_start 5 +#define GEN9_PIPELINE_SELECT_ForceMediaAwake_start 5 + +static inline uint32_t ATTRIBUTE_PURE +PIPELINE_SELECT_ForceMediaAwake_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPELINE_SELECT::Mask Bits */ + + +#define GEN11_PIPELINE_SELECT_MaskBits_bits 8 +#define GEN10_PIPELINE_SELECT_MaskBits_bits 8 +#define GEN9_PIPELINE_SELECT_MaskBits_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +PIPELINE_SELECT_MaskBits_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PIPELINE_SELECT_MaskBits_start 8 +#define GEN10_PIPELINE_SELECT_MaskBits_start 8 +#define GEN9_PIPELINE_SELECT_MaskBits_start 8 + +static inline uint32_t ATTRIBUTE_PURE +PIPELINE_SELECT_MaskBits_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPELINE_SELECT::Media Sampler DOP Clock Gate Enable */ + + +#define GEN11_PIPELINE_SELECT_MediaSamplerDOPClockGateEnable_bits 1 +#define GEN10_PIPELINE_SELECT_MediaSamplerDOPClockGateEnable_bits 1 +#define GEN9_PIPELINE_SELECT_MediaSamplerDOPClockGateEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +PIPELINE_SELECT_MediaSamplerDOPClockGateEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PIPELINE_SELECT_MediaSamplerDOPClockGateEnable_start 4 +#define GEN10_PIPELINE_SELECT_MediaSamplerDOPClockGateEnable_start 4 +#define GEN9_PIPELINE_SELECT_MediaSamplerDOPClockGateEnable_start 4 + +static inline uint32_t ATTRIBUTE_PURE +PIPELINE_SELECT_MediaSamplerDOPClockGateEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPELINE_SELECT::Pipeline Selection */ + + +#define GEN11_PIPELINE_SELECT_PipelineSelection_bits 2 +#define GEN10_PIPELINE_SELECT_PipelineSelection_bits 2 +#define GEN9_PIPELINE_SELECT_PipelineSelection_bits 2 +#define GEN8_PIPELINE_SELECT_PipelineSelection_bits 2 +#define GEN75_PIPELINE_SELECT_PipelineSelection_bits 2 +#define GEN7_PIPELINE_SELECT_PipelineSelection_bits 2 +#define GEN6_PIPELINE_SELECT_PipelineSelection_bits 2 +#define GEN5_PIPELINE_SELECT_PipelineSelection_bits 2 +#define GEN45_PIPELINE_SELECT_PipelineSelection_bits 2 +#define GEN4_PIPELINE_SELECT_PipelineSelection_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +PIPELINE_SELECT_PipelineSelection_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PIPELINE_SELECT_PipelineSelection_start 0 +#define GEN10_PIPELINE_SELECT_PipelineSelection_start 0 +#define GEN9_PIPELINE_SELECT_PipelineSelection_start 0 +#define GEN8_PIPELINE_SELECT_PipelineSelection_start 0 +#define GEN75_PIPELINE_SELECT_PipelineSelection_start 0 +#define GEN7_PIPELINE_SELECT_PipelineSelection_start 0 +#define GEN6_PIPELINE_SELECT_PipelineSelection_start 0 +#define GEN5_PIPELINE_SELECT_PipelineSelection_start 0 +#define GEN45_PIPELINE_SELECT_PipelineSelection_start 0 +#define GEN4_PIPELINE_SELECT_PipelineSelection_start 0 + +static inline uint32_t ATTRIBUTE_PURE +PIPELINE_SELECT_PipelineSelection_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPE_CONTROL */ + + +#define GEN11_PIPE_CONTROL_length 6 +#define GEN10_PIPE_CONTROL_length 6 +#define GEN9_PIPE_CONTROL_length 6 +#define GEN8_PIPE_CONTROL_length 6 +#define GEN75_PIPE_CONTROL_length 5 +#define GEN7_PIPE_CONTROL_length 5 +#define GEN6_PIPE_CONTROL_length 5 +#define GEN5_PIPE_CONTROL_length 4 +#define GEN45_PIPE_CONTROL_length 4 +#define GEN4_PIPE_CONTROL_length 4 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 5; + } + case 6: return 5; + case 5: return 4; + case 4: + if (devinfo->is_g4x) { + return 4; + } else { + return 4; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPE_CONTROL::3D Command Opcode */ + + +#define GEN11_PIPE_CONTROL_3DCommandOpcode_bits 3 +#define GEN10_PIPE_CONTROL_3DCommandOpcode_bits 3 +#define GEN9_PIPE_CONTROL_3DCommandOpcode_bits 3 +#define GEN8_PIPE_CONTROL_3DCommandOpcode_bits 3 +#define GEN75_PIPE_CONTROL_3DCommandOpcode_bits 3 +#define GEN7_PIPE_CONTROL_3DCommandOpcode_bits 3 +#define GEN6_PIPE_CONTROL_3DCommandOpcode_bits 3 +#define GEN5_PIPE_CONTROL_3DCommandOpcode_bits 3 +#define GEN45_PIPE_CONTROL_3DCommandOpcode_bits 3 +#define GEN4_PIPE_CONTROL_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PIPE_CONTROL_3DCommandOpcode_start 24 +#define GEN10_PIPE_CONTROL_3DCommandOpcode_start 24 +#define GEN9_PIPE_CONTROL_3DCommandOpcode_start 24 +#define GEN8_PIPE_CONTROL_3DCommandOpcode_start 24 +#define GEN75_PIPE_CONTROL_3DCommandOpcode_start 24 +#define GEN7_PIPE_CONTROL_3DCommandOpcode_start 24 +#define GEN6_PIPE_CONTROL_3DCommandOpcode_start 24 +#define GEN5_PIPE_CONTROL_3DCommandOpcode_start 24 +#define GEN45_PIPE_CONTROL_3DCommandOpcode_start 24 +#define GEN4_PIPE_CONTROL_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 24; + case 4: + if (devinfo->is_g4x) { + return 24; + } else { + return 24; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPE_CONTROL::3D Command Sub Opcode */ + + +#define GEN11_PIPE_CONTROL_3DCommandSubOpcode_bits 8 +#define GEN10_PIPE_CONTROL_3DCommandSubOpcode_bits 8 +#define GEN9_PIPE_CONTROL_3DCommandSubOpcode_bits 8 +#define GEN8_PIPE_CONTROL_3DCommandSubOpcode_bits 8 +#define GEN75_PIPE_CONTROL_3DCommandSubOpcode_bits 8 +#define GEN7_PIPE_CONTROL_3DCommandSubOpcode_bits 8 +#define GEN6_PIPE_CONTROL_3DCommandSubOpcode_bits 8 +#define GEN5_PIPE_CONTROL_3DCommandSubOpcode_bits 8 +#define GEN45_PIPE_CONTROL_3DCommandSubOpcode_bits 8 +#define GEN4_PIPE_CONTROL_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PIPE_CONTROL_3DCommandSubOpcode_start 16 +#define GEN10_PIPE_CONTROL_3DCommandSubOpcode_start 16 +#define GEN9_PIPE_CONTROL_3DCommandSubOpcode_start 16 +#define GEN8_PIPE_CONTROL_3DCommandSubOpcode_start 16 +#define GEN75_PIPE_CONTROL_3DCommandSubOpcode_start 16 +#define GEN7_PIPE_CONTROL_3DCommandSubOpcode_start 16 +#define GEN6_PIPE_CONTROL_3DCommandSubOpcode_start 16 +#define GEN5_PIPE_CONTROL_3DCommandSubOpcode_start 16 +#define GEN45_PIPE_CONTROL_3DCommandSubOpcode_start 16 +#define GEN4_PIPE_CONTROL_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPE_CONTROL::Address */ + + +#define GEN11_PIPE_CONTROL_Address_bits 46 +#define GEN10_PIPE_CONTROL_Address_bits 46 +#define GEN9_PIPE_CONTROL_Address_bits 46 +#define GEN8_PIPE_CONTROL_Address_bits 46 +#define GEN75_PIPE_CONTROL_Address_bits 30 +#define GEN7_PIPE_CONTROL_Address_bits 30 +#define GEN6_PIPE_CONTROL_Address_bits 29 +#define GEN5_PIPE_CONTROL_Address_bits 29 +#define GEN45_PIPE_CONTROL_Address_bits 29 +#define GEN4_PIPE_CONTROL_Address_bits 29 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_Address_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 46; + case 10: return 46; + case 9: return 46; + case 8: return 46; + case 7: + if (devinfo->is_haswell) { + return 30; + } else { + return 30; + } + case 6: return 29; + case 5: return 29; + case 4: + if (devinfo->is_g4x) { + return 29; + } else { + return 29; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PIPE_CONTROL_Address_start 66 +#define GEN10_PIPE_CONTROL_Address_start 66 +#define GEN9_PIPE_CONTROL_Address_start 66 +#define GEN8_PIPE_CONTROL_Address_start 66 +#define GEN75_PIPE_CONTROL_Address_start 66 +#define GEN7_PIPE_CONTROL_Address_start 66 +#define GEN6_PIPE_CONTROL_Address_start 67 +#define GEN5_PIPE_CONTROL_Address_start 35 +#define GEN45_PIPE_CONTROL_Address_start 35 +#define GEN4_PIPE_CONTROL_Address_start 35 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_Address_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 66; + case 10: return 66; + case 9: return 66; + case 8: return 66; + case 7: + if (devinfo->is_haswell) { + return 66; + } else { + return 66; + } + case 6: return 67; + case 5: return 35; + case 4: + if (devinfo->is_g4x) { + return 35; + } else { + return 35; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPE_CONTROL::Command Streamer Stall Enable */ + + +#define GEN11_PIPE_CONTROL_CommandStreamerStallEnable_bits 1 +#define GEN10_PIPE_CONTROL_CommandStreamerStallEnable_bits 1 +#define GEN9_PIPE_CONTROL_CommandStreamerStallEnable_bits 1 +#define GEN8_PIPE_CONTROL_CommandStreamerStallEnable_bits 1 +#define GEN75_PIPE_CONTROL_CommandStreamerStallEnable_bits 1 +#define GEN7_PIPE_CONTROL_CommandStreamerStallEnable_bits 1 +#define GEN6_PIPE_CONTROL_CommandStreamerStallEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_CommandStreamerStallEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PIPE_CONTROL_CommandStreamerStallEnable_start 52 +#define GEN10_PIPE_CONTROL_CommandStreamerStallEnable_start 52 +#define GEN9_PIPE_CONTROL_CommandStreamerStallEnable_start 52 +#define GEN8_PIPE_CONTROL_CommandStreamerStallEnable_start 52 +#define GEN75_PIPE_CONTROL_CommandStreamerStallEnable_start 52 +#define GEN7_PIPE_CONTROL_CommandStreamerStallEnable_start 52 +#define GEN6_PIPE_CONTROL_CommandStreamerStallEnable_start 52 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_CommandStreamerStallEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 52; + case 10: return 52; + case 9: return 52; + case 8: return 52; + case 7: + if (devinfo->is_haswell) { + return 52; + } else { + return 52; + } + case 6: return 52; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPE_CONTROL::Command SubType */ + + +#define GEN11_PIPE_CONTROL_CommandSubType_bits 2 +#define GEN10_PIPE_CONTROL_CommandSubType_bits 2 +#define GEN9_PIPE_CONTROL_CommandSubType_bits 2 +#define GEN8_PIPE_CONTROL_CommandSubType_bits 2 +#define GEN75_PIPE_CONTROL_CommandSubType_bits 2 +#define GEN7_PIPE_CONTROL_CommandSubType_bits 2 +#define GEN6_PIPE_CONTROL_CommandSubType_bits 2 +#define GEN5_PIPE_CONTROL_CommandSubType_bits 2 +#define GEN45_PIPE_CONTROL_CommandSubType_bits 2 +#define GEN4_PIPE_CONTROL_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PIPE_CONTROL_CommandSubType_start 27 +#define GEN10_PIPE_CONTROL_CommandSubType_start 27 +#define GEN9_PIPE_CONTROL_CommandSubType_start 27 +#define GEN8_PIPE_CONTROL_CommandSubType_start 27 +#define GEN75_PIPE_CONTROL_CommandSubType_start 27 +#define GEN7_PIPE_CONTROL_CommandSubType_start 27 +#define GEN6_PIPE_CONTROL_CommandSubType_start 27 +#define GEN5_PIPE_CONTROL_CommandSubType_start 27 +#define GEN45_PIPE_CONTROL_CommandSubType_start 27 +#define GEN4_PIPE_CONTROL_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPE_CONTROL::Command Type */ + + +#define GEN11_PIPE_CONTROL_CommandType_bits 3 +#define GEN10_PIPE_CONTROL_CommandType_bits 3 +#define GEN9_PIPE_CONTROL_CommandType_bits 3 +#define GEN8_PIPE_CONTROL_CommandType_bits 3 +#define GEN75_PIPE_CONTROL_CommandType_bits 3 +#define GEN7_PIPE_CONTROL_CommandType_bits 3 +#define GEN6_PIPE_CONTROL_CommandType_bits 3 +#define GEN5_PIPE_CONTROL_CommandType_bits 3 +#define GEN45_PIPE_CONTROL_CommandType_bits 3 +#define GEN4_PIPE_CONTROL_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PIPE_CONTROL_CommandType_start 29 +#define GEN10_PIPE_CONTROL_CommandType_start 29 +#define GEN9_PIPE_CONTROL_CommandType_start 29 +#define GEN8_PIPE_CONTROL_CommandType_start 29 +#define GEN75_PIPE_CONTROL_CommandType_start 29 +#define GEN7_PIPE_CONTROL_CommandType_start 29 +#define GEN6_PIPE_CONTROL_CommandType_start 29 +#define GEN5_PIPE_CONTROL_CommandType_start 29 +#define GEN45_PIPE_CONTROL_CommandType_start 29 +#define GEN4_PIPE_CONTROL_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 29; + case 4: + if (devinfo->is_g4x) { + return 29; + } else { + return 29; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPE_CONTROL::Constant Cache Invalidation Enable */ + + +#define GEN11_PIPE_CONTROL_ConstantCacheInvalidationEnable_bits 1 +#define GEN10_PIPE_CONTROL_ConstantCacheInvalidationEnable_bits 1 +#define GEN9_PIPE_CONTROL_ConstantCacheInvalidationEnable_bits 1 +#define GEN8_PIPE_CONTROL_ConstantCacheInvalidationEnable_bits 1 +#define GEN75_PIPE_CONTROL_ConstantCacheInvalidationEnable_bits 1 +#define GEN7_PIPE_CONTROL_ConstantCacheInvalidationEnable_bits 1 +#define GEN6_PIPE_CONTROL_ConstantCacheInvalidationEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_ConstantCacheInvalidationEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PIPE_CONTROL_ConstantCacheInvalidationEnable_start 35 +#define GEN10_PIPE_CONTROL_ConstantCacheInvalidationEnable_start 35 +#define GEN9_PIPE_CONTROL_ConstantCacheInvalidationEnable_start 35 +#define GEN8_PIPE_CONTROL_ConstantCacheInvalidationEnable_start 35 +#define GEN75_PIPE_CONTROL_ConstantCacheInvalidationEnable_start 35 +#define GEN7_PIPE_CONTROL_ConstantCacheInvalidationEnable_start 35 +#define GEN6_PIPE_CONTROL_ConstantCacheInvalidationEnable_start 35 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_ConstantCacheInvalidationEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 35; + case 10: return 35; + case 9: return 35; + case 8: return 35; + case 7: + if (devinfo->is_haswell) { + return 35; + } else { + return 35; + } + case 6: return 35; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPE_CONTROL::DC Flush Enable */ + + +#define GEN11_PIPE_CONTROL_DCFlushEnable_bits 1 +#define GEN10_PIPE_CONTROL_DCFlushEnable_bits 1 +#define GEN9_PIPE_CONTROL_DCFlushEnable_bits 1 +#define GEN8_PIPE_CONTROL_DCFlushEnable_bits 1 +#define GEN75_PIPE_CONTROL_DCFlushEnable_bits 1 +#define GEN7_PIPE_CONTROL_DCFlushEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_DCFlushEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PIPE_CONTROL_DCFlushEnable_start 37 +#define GEN10_PIPE_CONTROL_DCFlushEnable_start 37 +#define GEN9_PIPE_CONTROL_DCFlushEnable_start 37 +#define GEN8_PIPE_CONTROL_DCFlushEnable_start 37 +#define GEN75_PIPE_CONTROL_DCFlushEnable_start 37 +#define GEN7_PIPE_CONTROL_DCFlushEnable_start 37 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_DCFlushEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 37; + case 10: return 37; + case 9: return 37; + case 8: return 37; + case 7: + if (devinfo->is_haswell) { + return 37; + } else { + return 37; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPE_CONTROL::DWord Length */ + + +#define GEN11_PIPE_CONTROL_DWordLength_bits 8 +#define GEN10_PIPE_CONTROL_DWordLength_bits 8 +#define GEN9_PIPE_CONTROL_DWordLength_bits 8 +#define GEN8_PIPE_CONTROL_DWordLength_bits 8 +#define GEN75_PIPE_CONTROL_DWordLength_bits 8 +#define GEN7_PIPE_CONTROL_DWordLength_bits 8 +#define GEN6_PIPE_CONTROL_DWordLength_bits 8 +#define GEN5_PIPE_CONTROL_DWordLength_bits 8 +#define GEN45_PIPE_CONTROL_DWordLength_bits 8 +#define GEN4_PIPE_CONTROL_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PIPE_CONTROL_DWordLength_start 0 +#define GEN10_PIPE_CONTROL_DWordLength_start 0 +#define GEN9_PIPE_CONTROL_DWordLength_start 0 +#define GEN8_PIPE_CONTROL_DWordLength_start 0 +#define GEN75_PIPE_CONTROL_DWordLength_start 0 +#define GEN7_PIPE_CONTROL_DWordLength_start 0 +#define GEN6_PIPE_CONTROL_DWordLength_start 0 +#define GEN5_PIPE_CONTROL_DWordLength_start 0 +#define GEN45_PIPE_CONTROL_DWordLength_start 0 +#define GEN4_PIPE_CONTROL_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPE_CONTROL::Depth Cache Flush Enable */ + + +#define GEN11_PIPE_CONTROL_DepthCacheFlushEnable_bits 1 +#define GEN10_PIPE_CONTROL_DepthCacheFlushEnable_bits 1 +#define GEN9_PIPE_CONTROL_DepthCacheFlushEnable_bits 1 +#define GEN8_PIPE_CONTROL_DepthCacheFlushEnable_bits 1 +#define GEN75_PIPE_CONTROL_DepthCacheFlushEnable_bits 1 +#define GEN7_PIPE_CONTROL_DepthCacheFlushEnable_bits 1 +#define GEN6_PIPE_CONTROL_DepthCacheFlushEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_DepthCacheFlushEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PIPE_CONTROL_DepthCacheFlushEnable_start 32 +#define GEN10_PIPE_CONTROL_DepthCacheFlushEnable_start 32 +#define GEN9_PIPE_CONTROL_DepthCacheFlushEnable_start 32 +#define GEN8_PIPE_CONTROL_DepthCacheFlushEnable_start 32 +#define GEN75_PIPE_CONTROL_DepthCacheFlushEnable_start 32 +#define GEN7_PIPE_CONTROL_DepthCacheFlushEnable_start 32 +#define GEN6_PIPE_CONTROL_DepthCacheFlushEnable_start 32 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_DepthCacheFlushEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPE_CONTROL::Depth Cache Flush Inhibit */ + + +#define GEN5_PIPE_CONTROL_DepthCacheFlushInhibit_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_DepthCacheFlushInhibit_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_PIPE_CONTROL_DepthCacheFlushInhibit_start 32 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_DepthCacheFlushInhibit_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPE_CONTROL::Depth Stall Enable */ + + +#define GEN11_PIPE_CONTROL_DepthStallEnable_bits 1 +#define GEN10_PIPE_CONTROL_DepthStallEnable_bits 1 +#define GEN9_PIPE_CONTROL_DepthStallEnable_bits 1 +#define GEN8_PIPE_CONTROL_DepthStallEnable_bits 1 +#define GEN75_PIPE_CONTROL_DepthStallEnable_bits 1 +#define GEN7_PIPE_CONTROL_DepthStallEnable_bits 1 +#define GEN6_PIPE_CONTROL_DepthStallEnable_bits 1 +#define GEN5_PIPE_CONTROL_DepthStallEnable_bits 1 +#define GEN45_PIPE_CONTROL_DepthStallEnable_bits 1 +#define GEN4_PIPE_CONTROL_DepthStallEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_DepthStallEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PIPE_CONTROL_DepthStallEnable_start 45 +#define GEN10_PIPE_CONTROL_DepthStallEnable_start 45 +#define GEN9_PIPE_CONTROL_DepthStallEnable_start 45 +#define GEN8_PIPE_CONTROL_DepthStallEnable_start 45 +#define GEN75_PIPE_CONTROL_DepthStallEnable_start 45 +#define GEN7_PIPE_CONTROL_DepthStallEnable_start 45 +#define GEN6_PIPE_CONTROL_DepthStallEnable_start 45 +#define GEN5_PIPE_CONTROL_DepthStallEnable_start 13 +#define GEN45_PIPE_CONTROL_DepthStallEnable_start 13 +#define GEN4_PIPE_CONTROL_DepthStallEnable_start 13 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_DepthStallEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 45; + case 10: return 45; + case 9: return 45; + case 8: return 45; + case 7: + if (devinfo->is_haswell) { + return 45; + } else { + return 45; + } + case 6: return 45; + case 5: return 13; + case 4: + if (devinfo->is_g4x) { + return 13; + } else { + return 13; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPE_CONTROL::Destination Address Type */ + + +#define GEN11_PIPE_CONTROL_DestinationAddressType_bits 1 +#define GEN10_PIPE_CONTROL_DestinationAddressType_bits 1 +#define GEN9_PIPE_CONTROL_DestinationAddressType_bits 1 +#define GEN8_PIPE_CONTROL_DestinationAddressType_bits 1 +#define GEN75_PIPE_CONTROL_DestinationAddressType_bits 1 +#define GEN7_PIPE_CONTROL_DestinationAddressType_bits 1 +#define GEN6_PIPE_CONTROL_DestinationAddressType_bits 1 +#define GEN5_PIPE_CONTROL_DestinationAddressType_bits 1 +#define GEN45_PIPE_CONTROL_DestinationAddressType_bits 1 +#define GEN4_PIPE_CONTROL_DestinationAddressType_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_DestinationAddressType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PIPE_CONTROL_DestinationAddressType_start 56 +#define GEN10_PIPE_CONTROL_DestinationAddressType_start 56 +#define GEN9_PIPE_CONTROL_DestinationAddressType_start 56 +#define GEN8_PIPE_CONTROL_DestinationAddressType_start 56 +#define GEN75_PIPE_CONTROL_DestinationAddressType_start 56 +#define GEN7_PIPE_CONTROL_DestinationAddressType_start 56 +#define GEN6_PIPE_CONTROL_DestinationAddressType_start 66 +#define GEN5_PIPE_CONTROL_DestinationAddressType_start 34 +#define GEN45_PIPE_CONTROL_DestinationAddressType_start 34 +#define GEN4_PIPE_CONTROL_DestinationAddressType_start 34 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_DestinationAddressType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 56; + case 10: return 56; + case 9: return 56; + case 8: return 56; + case 7: + if (devinfo->is_haswell) { + return 56; + } else { + return 56; + } + case 6: return 66; + case 5: return 34; + case 4: + if (devinfo->is_g4x) { + return 34; + } else { + return 34; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPE_CONTROL::Flush LLC */ + + +#define GEN11_PIPE_CONTROL_FlushLLC_bits 1 +#define GEN10_PIPE_CONTROL_FlushLLC_bits 1 +#define GEN9_PIPE_CONTROL_FlushLLC_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_FlushLLC_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PIPE_CONTROL_FlushLLC_start 58 +#define GEN10_PIPE_CONTROL_FlushLLC_start 58 +#define GEN9_PIPE_CONTROL_FlushLLC_start 58 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_FlushLLC_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 58; + case 10: return 58; + case 9: return 58; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPE_CONTROL::Generic Media State Clear */ + + +#define GEN11_PIPE_CONTROL_GenericMediaStateClear_bits 1 +#define GEN10_PIPE_CONTROL_GenericMediaStateClear_bits 1 +#define GEN9_PIPE_CONTROL_GenericMediaStateClear_bits 1 +#define GEN8_PIPE_CONTROL_GenericMediaStateClear_bits 1 +#define GEN75_PIPE_CONTROL_GenericMediaStateClear_bits 1 +#define GEN7_PIPE_CONTROL_GenericMediaStateClear_bits 1 +#define GEN6_PIPE_CONTROL_GenericMediaStateClear_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_GenericMediaStateClear_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PIPE_CONTROL_GenericMediaStateClear_start 48 +#define GEN10_PIPE_CONTROL_GenericMediaStateClear_start 48 +#define GEN9_PIPE_CONTROL_GenericMediaStateClear_start 48 +#define GEN8_PIPE_CONTROL_GenericMediaStateClear_start 48 +#define GEN75_PIPE_CONTROL_GenericMediaStateClear_start 48 +#define GEN7_PIPE_CONTROL_GenericMediaStateClear_start 48 +#define GEN6_PIPE_CONTROL_GenericMediaStateClear_start 48 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_GenericMediaStateClear_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 48; + case 7: + if (devinfo->is_haswell) { + return 48; + } else { + return 48; + } + case 6: return 48; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPE_CONTROL::Global Snapshot Count Reset */ + + +#define GEN11_PIPE_CONTROL_GlobalSnapshotCountReset_bits 1 +#define GEN10_PIPE_CONTROL_GlobalSnapshotCountReset_bits 1 +#define GEN9_PIPE_CONTROL_GlobalSnapshotCountReset_bits 1 +#define GEN8_PIPE_CONTROL_GlobalSnapshotCountReset_bits 1 +#define GEN75_PIPE_CONTROL_GlobalSnapshotCountReset_bits 1 +#define GEN7_PIPE_CONTROL_GlobalSnapshotCountReset_bits 1 +#define GEN6_PIPE_CONTROL_GlobalSnapshotCountReset_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_GlobalSnapshotCountReset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PIPE_CONTROL_GlobalSnapshotCountReset_start 51 +#define GEN10_PIPE_CONTROL_GlobalSnapshotCountReset_start 51 +#define GEN9_PIPE_CONTROL_GlobalSnapshotCountReset_start 51 +#define GEN8_PIPE_CONTROL_GlobalSnapshotCountReset_start 51 +#define GEN75_PIPE_CONTROL_GlobalSnapshotCountReset_start 51 +#define GEN7_PIPE_CONTROL_GlobalSnapshotCountReset_start 51 +#define GEN6_PIPE_CONTROL_GlobalSnapshotCountReset_start 51 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_GlobalSnapshotCountReset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 51; + case 10: return 51; + case 9: return 51; + case 8: return 51; + case 7: + if (devinfo->is_haswell) { + return 51; + } else { + return 51; + } + case 6: return 51; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPE_CONTROL::Immediate Data */ + + +#define GEN11_PIPE_CONTROL_ImmediateData_bits 64 +#define GEN10_PIPE_CONTROL_ImmediateData_bits 64 +#define GEN9_PIPE_CONTROL_ImmediateData_bits 64 +#define GEN8_PIPE_CONTROL_ImmediateData_bits 64 +#define GEN75_PIPE_CONTROL_ImmediateData_bits 64 +#define GEN7_PIPE_CONTROL_ImmediateData_bits 64 +#define GEN6_PIPE_CONTROL_ImmediateData_bits 64 +#define GEN5_PIPE_CONTROL_ImmediateData_bits 64 +#define GEN45_PIPE_CONTROL_ImmediateData_bits 64 +#define GEN4_PIPE_CONTROL_ImmediateData_bits 64 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_ImmediateData_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 64; + case 5: return 64; + case 4: + if (devinfo->is_g4x) { + return 64; + } else { + return 64; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PIPE_CONTROL_ImmediateData_start 128 +#define GEN10_PIPE_CONTROL_ImmediateData_start 128 +#define GEN9_PIPE_CONTROL_ImmediateData_start 128 +#define GEN8_PIPE_CONTROL_ImmediateData_start 128 +#define GEN75_PIPE_CONTROL_ImmediateData_start 96 +#define GEN7_PIPE_CONTROL_ImmediateData_start 96 +#define GEN6_PIPE_CONTROL_ImmediateData_start 96 +#define GEN5_PIPE_CONTROL_ImmediateData_start 64 +#define GEN45_PIPE_CONTROL_ImmediateData_start 64 +#define GEN4_PIPE_CONTROL_ImmediateData_start 64 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_ImmediateData_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 128; + case 10: return 128; + case 9: return 128; + case 8: return 128; + case 7: + if (devinfo->is_haswell) { + return 96; + } else { + return 96; + } + case 6: return 96; + case 5: return 64; + case 4: + if (devinfo->is_g4x) { + return 64; + } else { + return 64; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPE_CONTROL::Indirect State Pointers Disable */ + + +#define GEN11_PIPE_CONTROL_IndirectStatePointersDisable_bits 1 +#define GEN10_PIPE_CONTROL_IndirectStatePointersDisable_bits 1 +#define GEN9_PIPE_CONTROL_IndirectStatePointersDisable_bits 1 +#define GEN8_PIPE_CONTROL_IndirectStatePointersDisable_bits 1 +#define GEN75_PIPE_CONTROL_IndirectStatePointersDisable_bits 1 +#define GEN7_PIPE_CONTROL_IndirectStatePointersDisable_bits 1 +#define GEN6_PIPE_CONTROL_IndirectStatePointersDisable_bits 1 +#define GEN5_PIPE_CONTROL_IndirectStatePointersDisable_bits 1 +#define GEN45_PIPE_CONTROL_IndirectStatePointersDisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_IndirectStatePointersDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PIPE_CONTROL_IndirectStatePointersDisable_start 41 +#define GEN10_PIPE_CONTROL_IndirectStatePointersDisable_start 41 +#define GEN9_PIPE_CONTROL_IndirectStatePointersDisable_start 41 +#define GEN8_PIPE_CONTROL_IndirectStatePointersDisable_start 41 +#define GEN75_PIPE_CONTROL_IndirectStatePointersDisable_start 41 +#define GEN7_PIPE_CONTROL_IndirectStatePointersDisable_start 41 +#define GEN6_PIPE_CONTROL_IndirectStatePointersDisable_start 41 +#define GEN5_PIPE_CONTROL_IndirectStatePointersDisable_start 9 +#define GEN45_PIPE_CONTROL_IndirectStatePointersDisable_start 9 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_IndirectStatePointersDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 41; + case 10: return 41; + case 9: return 41; + case 8: return 41; + case 7: + if (devinfo->is_haswell) { + return 41; + } else { + return 41; + } + case 6: return 41; + case 5: return 9; + case 4: + if (devinfo->is_g4x) { + return 9; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPE_CONTROL::Instruction Cache Invalidate Enable */ + + +#define GEN11_PIPE_CONTROL_InstructionCacheInvalidateEnable_bits 1 +#define GEN10_PIPE_CONTROL_InstructionCacheInvalidateEnable_bits 1 +#define GEN9_PIPE_CONTROL_InstructionCacheInvalidateEnable_bits 1 +#define GEN8_PIPE_CONTROL_InstructionCacheInvalidateEnable_bits 1 +#define GEN75_PIPE_CONTROL_InstructionCacheInvalidateEnable_bits 1 +#define GEN7_PIPE_CONTROL_InstructionCacheInvalidateEnable_bits 1 +#define GEN6_PIPE_CONTROL_InstructionCacheInvalidateEnable_bits 1 +#define GEN5_PIPE_CONTROL_InstructionCacheInvalidateEnable_bits 1 +#define GEN45_PIPE_CONTROL_InstructionCacheInvalidateEnable_bits 1 +#define GEN4_PIPE_CONTROL_InstructionCacheInvalidateEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_InstructionCacheInvalidateEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PIPE_CONTROL_InstructionCacheInvalidateEnable_start 43 +#define GEN10_PIPE_CONTROL_InstructionCacheInvalidateEnable_start 43 +#define GEN9_PIPE_CONTROL_InstructionCacheInvalidateEnable_start 43 +#define GEN8_PIPE_CONTROL_InstructionCacheInvalidateEnable_start 43 +#define GEN75_PIPE_CONTROL_InstructionCacheInvalidateEnable_start 43 +#define GEN7_PIPE_CONTROL_InstructionCacheInvalidateEnable_start 43 +#define GEN6_PIPE_CONTROL_InstructionCacheInvalidateEnable_start 43 +#define GEN5_PIPE_CONTROL_InstructionCacheInvalidateEnable_start 11 +#define GEN45_PIPE_CONTROL_InstructionCacheInvalidateEnable_start 11 +#define GEN4_PIPE_CONTROL_InstructionCacheInvalidateEnable_start 11 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_InstructionCacheInvalidateEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 43; + case 10: return 43; + case 9: return 43; + case 8: return 43; + case 7: + if (devinfo->is_haswell) { + return 43; + } else { + return 43; + } + case 6: return 43; + case 5: return 11; + case 4: + if (devinfo->is_g4x) { + return 11; + } else { + return 11; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPE_CONTROL::LRI Post Sync Operation */ + + +#define GEN11_PIPE_CONTROL_LRIPostSyncOperation_bits 1 +#define GEN10_PIPE_CONTROL_LRIPostSyncOperation_bits 1 +#define GEN9_PIPE_CONTROL_LRIPostSyncOperation_bits 1 +#define GEN8_PIPE_CONTROL_LRIPostSyncOperation_bits 1 +#define GEN75_PIPE_CONTROL_LRIPostSyncOperation_bits 1 +#define GEN7_PIPE_CONTROL_LRIPostSyncOperation_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_LRIPostSyncOperation_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PIPE_CONTROL_LRIPostSyncOperation_start 55 +#define GEN10_PIPE_CONTROL_LRIPostSyncOperation_start 55 +#define GEN9_PIPE_CONTROL_LRIPostSyncOperation_start 55 +#define GEN8_PIPE_CONTROL_LRIPostSyncOperation_start 55 +#define GEN75_PIPE_CONTROL_LRIPostSyncOperation_start 55 +#define GEN7_PIPE_CONTROL_LRIPostSyncOperation_start 55 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_LRIPostSyncOperation_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 55; + case 10: return 55; + case 9: return 55; + case 8: return 55; + case 7: + if (devinfo->is_haswell) { + return 55; + } else { + return 55; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPE_CONTROL::Notify Enable */ + + +#define GEN11_PIPE_CONTROL_NotifyEnable_bits 1 +#define GEN10_PIPE_CONTROL_NotifyEnable_bits 1 +#define GEN9_PIPE_CONTROL_NotifyEnable_bits 1 +#define GEN8_PIPE_CONTROL_NotifyEnable_bits 1 +#define GEN75_PIPE_CONTROL_NotifyEnable_bits 1 +#define GEN7_PIPE_CONTROL_NotifyEnable_bits 1 +#define GEN6_PIPE_CONTROL_NotifyEnable_bits 1 +#define GEN5_PIPE_CONTROL_NotifyEnable_bits 1 +#define GEN45_PIPE_CONTROL_NotifyEnable_bits 1 +#define GEN4_PIPE_CONTROL_NotifyEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_NotifyEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PIPE_CONTROL_NotifyEnable_start 40 +#define GEN10_PIPE_CONTROL_NotifyEnable_start 40 +#define GEN9_PIPE_CONTROL_NotifyEnable_start 40 +#define GEN8_PIPE_CONTROL_NotifyEnable_start 40 +#define GEN75_PIPE_CONTROL_NotifyEnable_start 40 +#define GEN7_PIPE_CONTROL_NotifyEnable_start 40 +#define GEN6_PIPE_CONTROL_NotifyEnable_start 40 +#define GEN5_PIPE_CONTROL_NotifyEnable_start 8 +#define GEN45_PIPE_CONTROL_NotifyEnable_start 8 +#define GEN4_PIPE_CONTROL_NotifyEnable_start 8 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_NotifyEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 40; + case 10: return 40; + case 9: return 40; + case 8: return 40; + case 7: + if (devinfo->is_haswell) { + return 40; + } else { + return 40; + } + case 6: return 40; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPE_CONTROL::PSD Sync Enable */ + + +#define GEN11_PIPE_CONTROL_PSDSyncEnable_bits 1 +#define GEN10_PIPE_CONTROL_PSDSyncEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_PSDSyncEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PIPE_CONTROL_PSDSyncEnable_start 49 +#define GEN10_PIPE_CONTROL_PSDSyncEnable_start 49 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_PSDSyncEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 49; + case 10: return 49; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPE_CONTROL::Pipe Control Flush Enable */ + + +#define GEN11_PIPE_CONTROL_PipeControlFlushEnable_bits 1 +#define GEN10_PIPE_CONTROL_PipeControlFlushEnable_bits 1 +#define GEN9_PIPE_CONTROL_PipeControlFlushEnable_bits 1 +#define GEN8_PIPE_CONTROL_PipeControlFlushEnable_bits 1 +#define GEN75_PIPE_CONTROL_PipeControlFlushEnable_bits 1 +#define GEN7_PIPE_CONTROL_PipeControlFlushEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_PipeControlFlushEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PIPE_CONTROL_PipeControlFlushEnable_start 39 +#define GEN10_PIPE_CONTROL_PipeControlFlushEnable_start 39 +#define GEN9_PIPE_CONTROL_PipeControlFlushEnable_start 39 +#define GEN8_PIPE_CONTROL_PipeControlFlushEnable_start 39 +#define GEN75_PIPE_CONTROL_PipeControlFlushEnable_start 39 +#define GEN7_PIPE_CONTROL_PipeControlFlushEnable_start 39 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_PipeControlFlushEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 39; + case 10: return 39; + case 9: return 39; + case 8: return 39; + case 7: + if (devinfo->is_haswell) { + return 39; + } else { + return 39; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPE_CONTROL::Post Sync Operation */ + + +#define GEN11_PIPE_CONTROL_PostSyncOperation_bits 2 +#define GEN10_PIPE_CONTROL_PostSyncOperation_bits 2 +#define GEN9_PIPE_CONTROL_PostSyncOperation_bits 2 +#define GEN8_PIPE_CONTROL_PostSyncOperation_bits 2 +#define GEN75_PIPE_CONTROL_PostSyncOperation_bits 2 +#define GEN7_PIPE_CONTROL_PostSyncOperation_bits 2 +#define GEN6_PIPE_CONTROL_PostSyncOperation_bits 2 +#define GEN5_PIPE_CONTROL_PostSyncOperation_bits 2 +#define GEN45_PIPE_CONTROL_PostSyncOperation_bits 2 +#define GEN4_PIPE_CONTROL_PostSyncOperation_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_PostSyncOperation_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PIPE_CONTROL_PostSyncOperation_start 46 +#define GEN10_PIPE_CONTROL_PostSyncOperation_start 46 +#define GEN9_PIPE_CONTROL_PostSyncOperation_start 46 +#define GEN8_PIPE_CONTROL_PostSyncOperation_start 46 +#define GEN75_PIPE_CONTROL_PostSyncOperation_start 46 +#define GEN7_PIPE_CONTROL_PostSyncOperation_start 46 +#define GEN6_PIPE_CONTROL_PostSyncOperation_start 46 +#define GEN5_PIPE_CONTROL_PostSyncOperation_start 14 +#define GEN45_PIPE_CONTROL_PostSyncOperation_start 14 +#define GEN4_PIPE_CONTROL_PostSyncOperation_start 14 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_PostSyncOperation_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 46; + case 10: return 46; + case 9: return 46; + case 8: return 46; + case 7: + if (devinfo->is_haswell) { + return 46; + } else { + return 46; + } + case 6: return 46; + case 5: return 14; + case 4: + if (devinfo->is_g4x) { + return 14; + } else { + return 14; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPE_CONTROL::Render Target Cache Flush Enable */ + + +#define GEN11_PIPE_CONTROL_RenderTargetCacheFlushEnable_bits 1 +#define GEN10_PIPE_CONTROL_RenderTargetCacheFlushEnable_bits 1 +#define GEN9_PIPE_CONTROL_RenderTargetCacheFlushEnable_bits 1 +#define GEN8_PIPE_CONTROL_RenderTargetCacheFlushEnable_bits 1 +#define GEN75_PIPE_CONTROL_RenderTargetCacheFlushEnable_bits 1 +#define GEN7_PIPE_CONTROL_RenderTargetCacheFlushEnable_bits 1 +#define GEN6_PIPE_CONTROL_RenderTargetCacheFlushEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_RenderTargetCacheFlushEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PIPE_CONTROL_RenderTargetCacheFlushEnable_start 44 +#define GEN10_PIPE_CONTROL_RenderTargetCacheFlushEnable_start 44 +#define GEN9_PIPE_CONTROL_RenderTargetCacheFlushEnable_start 44 +#define GEN8_PIPE_CONTROL_RenderTargetCacheFlushEnable_start 44 +#define GEN75_PIPE_CONTROL_RenderTargetCacheFlushEnable_start 44 +#define GEN7_PIPE_CONTROL_RenderTargetCacheFlushEnable_start 44 +#define GEN6_PIPE_CONTROL_RenderTargetCacheFlushEnable_start 44 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_RenderTargetCacheFlushEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 44; + case 10: return 44; + case 9: return 44; + case 8: return 44; + case 7: + if (devinfo->is_haswell) { + return 44; + } else { + return 44; + } + case 6: return 44; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPE_CONTROL::Stall At Pixel Scoreboard */ + + +#define GEN11_PIPE_CONTROL_StallAtPixelScoreboard_bits 1 +#define GEN10_PIPE_CONTROL_StallAtPixelScoreboard_bits 1 +#define GEN9_PIPE_CONTROL_StallAtPixelScoreboard_bits 1 +#define GEN8_PIPE_CONTROL_StallAtPixelScoreboard_bits 1 +#define GEN75_PIPE_CONTROL_StallAtPixelScoreboard_bits 1 +#define GEN7_PIPE_CONTROL_StallAtPixelScoreboard_bits 1 +#define GEN6_PIPE_CONTROL_StallAtPixelScoreboard_bits 1 +#define GEN5_PIPE_CONTROL_StallAtPixelScoreboard_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_StallAtPixelScoreboard_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PIPE_CONTROL_StallAtPixelScoreboard_start 33 +#define GEN10_PIPE_CONTROL_StallAtPixelScoreboard_start 33 +#define GEN9_PIPE_CONTROL_StallAtPixelScoreboard_start 33 +#define GEN8_PIPE_CONTROL_StallAtPixelScoreboard_start 33 +#define GEN75_PIPE_CONTROL_StallAtPixelScoreboard_start 33 +#define GEN7_PIPE_CONTROL_StallAtPixelScoreboard_start 33 +#define GEN6_PIPE_CONTROL_StallAtPixelScoreboard_start 33 +#define GEN5_PIPE_CONTROL_StallAtPixelScoreboard_start 33 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_StallAtPixelScoreboard_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 33; + case 10: return 33; + case 9: return 33; + case 8: return 33; + case 7: + if (devinfo->is_haswell) { + return 33; + } else { + return 33; + } + case 6: return 33; + case 5: return 33; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPE_CONTROL::State Cache Invalidation Enable */ + + +#define GEN11_PIPE_CONTROL_StateCacheInvalidationEnable_bits 1 +#define GEN10_PIPE_CONTROL_StateCacheInvalidationEnable_bits 1 +#define GEN9_PIPE_CONTROL_StateCacheInvalidationEnable_bits 1 +#define GEN8_PIPE_CONTROL_StateCacheInvalidationEnable_bits 1 +#define GEN75_PIPE_CONTROL_StateCacheInvalidationEnable_bits 1 +#define GEN7_PIPE_CONTROL_StateCacheInvalidationEnable_bits 1 +#define GEN6_PIPE_CONTROL_StateCacheInvalidationEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_StateCacheInvalidationEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PIPE_CONTROL_StateCacheInvalidationEnable_start 34 +#define GEN10_PIPE_CONTROL_StateCacheInvalidationEnable_start 34 +#define GEN9_PIPE_CONTROL_StateCacheInvalidationEnable_start 34 +#define GEN8_PIPE_CONTROL_StateCacheInvalidationEnable_start 34 +#define GEN75_PIPE_CONTROL_StateCacheInvalidationEnable_start 34 +#define GEN7_PIPE_CONTROL_StateCacheInvalidationEnable_start 34 +#define GEN6_PIPE_CONTROL_StateCacheInvalidationEnable_start 34 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_StateCacheInvalidationEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 34; + case 10: return 34; + case 9: return 34; + case 8: return 34; + case 7: + if (devinfo->is_haswell) { + return 34; + } else { + return 34; + } + case 6: return 34; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPE_CONTROL::Store Data Index */ + + +#define GEN11_PIPE_CONTROL_StoreDataIndex_bits 1 +#define GEN10_PIPE_CONTROL_StoreDataIndex_bits 1 +#define GEN9_PIPE_CONTROL_StoreDataIndex_bits 1 +#define GEN8_PIPE_CONTROL_StoreDataIndex_bits 1 +#define GEN75_PIPE_CONTROL_StoreDataIndex_bits 1 +#define GEN7_PIPE_CONTROL_StoreDataIndex_bits 1 +#define GEN6_PIPE_CONTROL_StoreDataIndex_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_StoreDataIndex_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PIPE_CONTROL_StoreDataIndex_start 53 +#define GEN10_PIPE_CONTROL_StoreDataIndex_start 53 +#define GEN9_PIPE_CONTROL_StoreDataIndex_start 53 +#define GEN8_PIPE_CONTROL_StoreDataIndex_start 53 +#define GEN75_PIPE_CONTROL_StoreDataIndex_start 53 +#define GEN7_PIPE_CONTROL_StoreDataIndex_start 53 +#define GEN6_PIPE_CONTROL_StoreDataIndex_start 53 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_StoreDataIndex_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 53; + case 10: return 53; + case 9: return 53; + case 8: return 53; + case 7: + if (devinfo->is_haswell) { + return 53; + } else { + return 53; + } + case 6: return 53; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPE_CONTROL::Synchronize GFDT Surface */ + + +#define GEN6_PIPE_CONTROL_SynchronizeGFDTSurface_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_SynchronizeGFDTSurface_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_PIPE_CONTROL_SynchronizeGFDTSurface_start 49 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_SynchronizeGFDTSurface_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 49; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPE_CONTROL::TLB Invalidate */ + + +#define GEN11_PIPE_CONTROL_TLBInvalidate_bits 1 +#define GEN10_PIPE_CONTROL_TLBInvalidate_bits 1 +#define GEN9_PIPE_CONTROL_TLBInvalidate_bits 1 +#define GEN8_PIPE_CONTROL_TLBInvalidate_bits 1 +#define GEN75_PIPE_CONTROL_TLBInvalidate_bits 1 +#define GEN7_PIPE_CONTROL_TLBInvalidate_bits 1 +#define GEN6_PIPE_CONTROL_TLBInvalidate_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_TLBInvalidate_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PIPE_CONTROL_TLBInvalidate_start 50 +#define GEN10_PIPE_CONTROL_TLBInvalidate_start 50 +#define GEN9_PIPE_CONTROL_TLBInvalidate_start 50 +#define GEN8_PIPE_CONTROL_TLBInvalidate_start 50 +#define GEN75_PIPE_CONTROL_TLBInvalidate_start 50 +#define GEN7_PIPE_CONTROL_TLBInvalidate_start 50 +#define GEN6_PIPE_CONTROL_TLBInvalidate_start 50 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_TLBInvalidate_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 50; + case 10: return 50; + case 9: return 50; + case 8: return 50; + case 7: + if (devinfo->is_haswell) { + return 50; + } else { + return 50; + } + case 6: return 50; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPE_CONTROL::Texture Cache Flush Enable */ + + +#define GEN5_PIPE_CONTROL_TextureCacheFlushEnable_bits 1 +#define GEN45_PIPE_CONTROL_TextureCacheFlushEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_TextureCacheFlushEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_PIPE_CONTROL_TextureCacheFlushEnable_start 10 +#define GEN45_PIPE_CONTROL_TextureCacheFlushEnable_start 10 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_TextureCacheFlushEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 10; + case 4: + if (devinfo->is_g4x) { + return 10; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPE_CONTROL::Texture Cache Invalidation Enable */ + + +#define GEN11_PIPE_CONTROL_TextureCacheInvalidationEnable_bits 1 +#define GEN10_PIPE_CONTROL_TextureCacheInvalidationEnable_bits 1 +#define GEN9_PIPE_CONTROL_TextureCacheInvalidationEnable_bits 1 +#define GEN8_PIPE_CONTROL_TextureCacheInvalidationEnable_bits 1 +#define GEN75_PIPE_CONTROL_TextureCacheInvalidationEnable_bits 1 +#define GEN7_PIPE_CONTROL_TextureCacheInvalidationEnable_bits 1 +#define GEN6_PIPE_CONTROL_TextureCacheInvalidationEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_TextureCacheInvalidationEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PIPE_CONTROL_TextureCacheInvalidationEnable_start 42 +#define GEN10_PIPE_CONTROL_TextureCacheInvalidationEnable_start 42 +#define GEN9_PIPE_CONTROL_TextureCacheInvalidationEnable_start 42 +#define GEN8_PIPE_CONTROL_TextureCacheInvalidationEnable_start 42 +#define GEN75_PIPE_CONTROL_TextureCacheInvalidationEnable_start 42 +#define GEN7_PIPE_CONTROL_TextureCacheInvalidationEnable_start 42 +#define GEN6_PIPE_CONTROL_TextureCacheInvalidationEnable_start 42 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_TextureCacheInvalidationEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 42; + case 10: return 42; + case 9: return 42; + case 8: return 42; + case 7: + if (devinfo->is_haswell) { + return 42; + } else { + return 42; + } + case 6: return 42; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPE_CONTROL::VF Cache Invalidation Enable */ + + +#define GEN11_PIPE_CONTROL_VFCacheInvalidationEnable_bits 1 +#define GEN10_PIPE_CONTROL_VFCacheInvalidationEnable_bits 1 +#define GEN9_PIPE_CONTROL_VFCacheInvalidationEnable_bits 1 +#define GEN8_PIPE_CONTROL_VFCacheInvalidationEnable_bits 1 +#define GEN75_PIPE_CONTROL_VFCacheInvalidationEnable_bits 1 +#define GEN7_PIPE_CONTROL_VFCacheInvalidationEnable_bits 1 +#define GEN6_PIPE_CONTROL_VFCacheInvalidationEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_VFCacheInvalidationEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PIPE_CONTROL_VFCacheInvalidationEnable_start 36 +#define GEN10_PIPE_CONTROL_VFCacheInvalidationEnable_start 36 +#define GEN9_PIPE_CONTROL_VFCacheInvalidationEnable_start 36 +#define GEN8_PIPE_CONTROL_VFCacheInvalidationEnable_start 36 +#define GEN75_PIPE_CONTROL_VFCacheInvalidationEnable_start 36 +#define GEN7_PIPE_CONTROL_VFCacheInvalidationEnable_start 36 +#define GEN6_PIPE_CONTROL_VFCacheInvalidationEnable_start 36 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_VFCacheInvalidationEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 36; + case 10: return 36; + case 9: return 36; + case 8: return 36; + case 7: + if (devinfo->is_haswell) { + return 36; + } else { + return 36; + } + case 6: return 36; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PIPE_CONTROL::Write Cache Flush */ + + +#define GEN5_PIPE_CONTROL_WriteCacheFlush_bits 1 +#define GEN45_PIPE_CONTROL_WriteCacheFlush_bits 1 +#define GEN4_PIPE_CONTROL_WriteCacheFlush_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_WriteCacheFlush_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_PIPE_CONTROL_WriteCacheFlush_start 12 +#define GEN45_PIPE_CONTROL_WriteCacheFlush_start 12 +#define GEN4_PIPE_CONTROL_WriteCacheFlush_start 12 + +static inline uint32_t ATTRIBUTE_PURE +PIPE_CONTROL_WriteCacheFlush_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 12; + case 4: + if (devinfo->is_g4x) { + return 12; + } else { + return 12; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PS_INVOCATION_COUNT */ + + +#define GEN11_PS_INVOCATION_COUNT_length 2 +#define GEN10_PS_INVOCATION_COUNT_length 2 +#define GEN9_PS_INVOCATION_COUNT_length 2 +#define GEN8_PS_INVOCATION_COUNT_length 2 +#define GEN75_PS_INVOCATION_COUNT_length 2 +#define GEN7_PS_INVOCATION_COUNT_length 2 + +static inline uint32_t ATTRIBUTE_PURE +PS_INVOCATION_COUNT_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* PS_INVOCATION_COUNT::PS Invocation Count Report */ + + +#define GEN11_PS_INVOCATION_COUNT_PSInvocationCountReport_bits 64 +#define GEN10_PS_INVOCATION_COUNT_PSInvocationCountReport_bits 64 +#define GEN9_PS_INVOCATION_COUNT_PSInvocationCountReport_bits 64 +#define GEN8_PS_INVOCATION_COUNT_PSInvocationCountReport_bits 64 +#define GEN75_PS_INVOCATION_COUNT_PSInvocationCountReport_bits 64 +#define GEN7_PS_INVOCATION_COUNT_PSInvocationCountReport_bits 64 + +static inline uint32_t ATTRIBUTE_PURE +PS_INVOCATION_COUNT_PSInvocationCountReport_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_PS_INVOCATION_COUNT_PSInvocationCountReport_start 0 +#define GEN10_PS_INVOCATION_COUNT_PSInvocationCountReport_start 0 +#define GEN9_PS_INVOCATION_COUNT_PSInvocationCountReport_start 0 +#define GEN8_PS_INVOCATION_COUNT_PSInvocationCountReport_start 0 +#define GEN75_PS_INVOCATION_COUNT_PSInvocationCountReport_start 0 +#define GEN7_PS_INVOCATION_COUNT_PSInvocationCountReport_start 0 + +static inline uint32_t ATTRIBUTE_PURE +PS_INVOCATION_COUNT_PSInvocationCountReport_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RCS_FAULT_REG */ + + +#define GEN75_RCS_FAULT_REG_length 1 +#define GEN7_RCS_FAULT_REG_length 1 +#define GEN6_RCS_FAULT_REG_length 1 + +static inline uint32_t ATTRIBUTE_PURE +RCS_FAULT_REG_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RCS_FAULT_REG::Fault Type */ + + +#define GEN75_RCS_FAULT_REG_FaultType_bits 2 +#define GEN7_RCS_FAULT_REG_FaultType_bits 2 +#define GEN6_RCS_FAULT_REG_FaultType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +RCS_FAULT_REG_FaultType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_RCS_FAULT_REG_FaultType_start 1 +#define GEN7_RCS_FAULT_REG_FaultType_start 1 +#define GEN6_RCS_FAULT_REG_FaultType_start 1 + +static inline uint32_t ATTRIBUTE_PURE +RCS_FAULT_REG_FaultType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RCS_FAULT_REG::GTTSEL */ + + +#define GEN75_RCS_FAULT_REG_GTTSEL_bits 1 +#define GEN7_RCS_FAULT_REG_GTTSEL_bits 1 +#define GEN6_RCS_FAULT_REG_GTTSEL_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RCS_FAULT_REG_GTTSEL_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_RCS_FAULT_REG_GTTSEL_start 11 +#define GEN7_RCS_FAULT_REG_GTTSEL_start 11 +#define GEN6_RCS_FAULT_REG_GTTSEL_start 11 + +static inline uint32_t ATTRIBUTE_PURE +RCS_FAULT_REG_GTTSEL_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 11; + } else { + return 11; + } + case 6: return 11; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RCS_FAULT_REG::SRCID of Fault */ + + +#define GEN75_RCS_FAULT_REG_SRCIDofFault_bits 8 +#define GEN7_RCS_FAULT_REG_SRCIDofFault_bits 8 +#define GEN6_RCS_FAULT_REG_SRCIDofFault_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +RCS_FAULT_REG_SRCIDofFault_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_RCS_FAULT_REG_SRCIDofFault_start 3 +#define GEN7_RCS_FAULT_REG_SRCIDofFault_start 3 +#define GEN6_RCS_FAULT_REG_SRCIDofFault_start 3 + +static inline uint32_t ATTRIBUTE_PURE +RCS_FAULT_REG_SRCIDofFault_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RCS_FAULT_REG::Valid Bit */ + + +#define GEN75_RCS_FAULT_REG_ValidBit_bits 1 +#define GEN7_RCS_FAULT_REG_ValidBit_bits 1 +#define GEN6_RCS_FAULT_REG_ValidBit_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RCS_FAULT_REG_ValidBit_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_RCS_FAULT_REG_ValidBit_start 0 +#define GEN7_RCS_FAULT_REG_ValidBit_start 0 +#define GEN6_RCS_FAULT_REG_ValidBit_start 0 + +static inline uint32_t ATTRIBUTE_PURE +RCS_FAULT_REG_ValidBit_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RCS_FAULT_REG::Virtual Address of Fault */ + + +#define GEN75_RCS_FAULT_REG_VirtualAddressofFault_bits 20 +#define GEN7_RCS_FAULT_REG_VirtualAddressofFault_bits 20 +#define GEN6_RCS_FAULT_REG_VirtualAddressofFault_bits 20 + +static inline uint32_t ATTRIBUTE_PURE +RCS_FAULT_REG_VirtualAddressofFault_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 20; + } else { + return 20; + } + case 6: return 20; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_RCS_FAULT_REG_VirtualAddressofFault_start 12 +#define GEN7_RCS_FAULT_REG_VirtualAddressofFault_start 12 +#define GEN6_RCS_FAULT_REG_VirtualAddressofFault_start 12 + +static inline uint32_t ATTRIBUTE_PURE +RCS_FAULT_REG_VirtualAddressofFault_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 12; + } else { + return 12; + } + case 6: return 12; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RCS_RING_BUFFER_CTL */ + + +#define GEN9_RCS_RING_BUFFER_CTL_length 1 +#define GEN8_RCS_RING_BUFFER_CTL_length 1 +#define GEN75_RCS_RING_BUFFER_CTL_length 1 +#define GEN7_RCS_RING_BUFFER_CTL_length 1 +#define GEN6_RCS_RING_BUFFER_CTL_length 1 + +static inline uint32_t ATTRIBUTE_PURE +RCS_RING_BUFFER_CTL_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RCS_RING_BUFFER_CTL::Automatic Report Head Pointer */ + + +#define GEN9_RCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 +#define GEN8_RCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 +#define GEN75_RCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 +#define GEN7_RCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 +#define GEN6_RCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +RCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_RCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 +#define GEN8_RCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 +#define GEN75_RCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 +#define GEN7_RCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 +#define GEN6_RCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 + +static inline uint32_t ATTRIBUTE_PURE +RCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RCS_RING_BUFFER_CTL::Buffer Length (in pages - 1) */ + + +#define GEN9_RCS_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 +#define GEN8_RCS_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 +#define GEN75_RCS_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 +#define GEN7_RCS_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 +#define GEN6_RCS_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +RCS_RING_BUFFER_CTL_BufferLengthinpages1_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 9; + } + case 6: return 9; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_RCS_RING_BUFFER_CTL_BufferLengthinpages1_start 12 +#define GEN8_RCS_RING_BUFFER_CTL_BufferLengthinpages1_start 12 +#define GEN75_RCS_RING_BUFFER_CTL_BufferLengthinpages1_start 12 +#define GEN7_RCS_RING_BUFFER_CTL_BufferLengthinpages1_start 12 +#define GEN6_RCS_RING_BUFFER_CTL_BufferLengthinpages1_start 12 + +static inline uint32_t ATTRIBUTE_PURE +RCS_RING_BUFFER_CTL_BufferLengthinpages1_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 12; + case 8: return 12; + case 7: + if (devinfo->is_haswell) { + return 12; + } else { + return 12; + } + case 6: return 12; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RCS_RING_BUFFER_CTL::RBWait */ + + +#define GEN9_RCS_RING_BUFFER_CTL_RBWait_bits 1 +#define GEN8_RCS_RING_BUFFER_CTL_RBWait_bits 1 +#define GEN75_RCS_RING_BUFFER_CTL_RBWait_bits 1 +#define GEN7_RCS_RING_BUFFER_CTL_RBWait_bits 1 +#define GEN6_RCS_RING_BUFFER_CTL_RBWait_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RCS_RING_BUFFER_CTL_RBWait_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_RCS_RING_BUFFER_CTL_RBWait_start 11 +#define GEN8_RCS_RING_BUFFER_CTL_RBWait_start 11 +#define GEN75_RCS_RING_BUFFER_CTL_RBWait_start 11 +#define GEN7_RCS_RING_BUFFER_CTL_RBWait_start 11 +#define GEN6_RCS_RING_BUFFER_CTL_RBWait_start 11 + +static inline uint32_t ATTRIBUTE_PURE +RCS_RING_BUFFER_CTL_RBWait_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 11; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 11; + } else { + return 11; + } + case 6: return 11; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RCS_RING_BUFFER_CTL::Ring Buffer Enable */ + + +#define GEN9_RCS_RING_BUFFER_CTL_RingBufferEnable_bits 1 +#define GEN8_RCS_RING_BUFFER_CTL_RingBufferEnable_bits 1 +#define GEN75_RCS_RING_BUFFER_CTL_RingBufferEnable_bits 1 +#define GEN7_RCS_RING_BUFFER_CTL_RingBufferEnable_bits 1 +#define GEN6_RCS_RING_BUFFER_CTL_RingBufferEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RCS_RING_BUFFER_CTL_RingBufferEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_RCS_RING_BUFFER_CTL_RingBufferEnable_start 0 +#define GEN8_RCS_RING_BUFFER_CTL_RingBufferEnable_start 0 +#define GEN75_RCS_RING_BUFFER_CTL_RingBufferEnable_start 0 +#define GEN7_RCS_RING_BUFFER_CTL_RingBufferEnable_start 0 +#define GEN6_RCS_RING_BUFFER_CTL_RingBufferEnable_start 0 + +static inline uint32_t ATTRIBUTE_PURE +RCS_RING_BUFFER_CTL_RingBufferEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RCS_RING_BUFFER_CTL::Semaphore Wait */ + + +#define GEN9_RCS_RING_BUFFER_CTL_SemaphoreWait_bits 1 +#define GEN8_RCS_RING_BUFFER_CTL_SemaphoreWait_bits 1 +#define GEN75_RCS_RING_BUFFER_CTL_SemaphoreWait_bits 1 +#define GEN7_RCS_RING_BUFFER_CTL_SemaphoreWait_bits 1 +#define GEN6_RCS_RING_BUFFER_CTL_SemaphoreWait_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RCS_RING_BUFFER_CTL_SemaphoreWait_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_RCS_RING_BUFFER_CTL_SemaphoreWait_start 10 +#define GEN8_RCS_RING_BUFFER_CTL_SemaphoreWait_start 10 +#define GEN75_RCS_RING_BUFFER_CTL_SemaphoreWait_start 10 +#define GEN7_RCS_RING_BUFFER_CTL_SemaphoreWait_start 10 +#define GEN6_RCS_RING_BUFFER_CTL_SemaphoreWait_start 10 + +static inline uint32_t ATTRIBUTE_PURE +RCS_RING_BUFFER_CTL_SemaphoreWait_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 10; + case 8: return 10; + case 7: + if (devinfo->is_haswell) { + return 10; + } else { + return 10; + } + case 6: return 10; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE */ + + +#define GEN11_RENDER_SURFACE_STATE_length 16 +#define GEN10_RENDER_SURFACE_STATE_length 16 +#define GEN9_RENDER_SURFACE_STATE_length 16 +#define GEN8_RENDER_SURFACE_STATE_length 16 +#define GEN75_RENDER_SURFACE_STATE_length 8 +#define GEN7_RENDER_SURFACE_STATE_length 8 +#define GEN6_RENDER_SURFACE_STATE_length 6 +#define GEN5_RENDER_SURFACE_STATE_length 6 +#define GEN45_RENDER_SURFACE_STATE_length 6 +#define GEN4_RENDER_SURFACE_STATE_length 5 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 6; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 5; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Alpha Clear Color */ + + +#define GEN11_RENDER_SURFACE_STATE_AlphaClearColor_bits 32 +#define GEN10_RENDER_SURFACE_STATE_AlphaClearColor_bits 32 +#define GEN9_RENDER_SURFACE_STATE_AlphaClearColor_bits 32 +#define GEN8_RENDER_SURFACE_STATE_AlphaClearColor_bits 1 +#define GEN75_RENDER_SURFACE_STATE_AlphaClearColor_bits 1 +#define GEN7_RENDER_SURFACE_STATE_AlphaClearColor_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_AlphaClearColor_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_AlphaClearColor_start 480 +#define GEN10_RENDER_SURFACE_STATE_AlphaClearColor_start 480 +#define GEN9_RENDER_SURFACE_STATE_AlphaClearColor_start 480 +#define GEN8_RENDER_SURFACE_STATE_AlphaClearColor_start 252 +#define GEN75_RENDER_SURFACE_STATE_AlphaClearColor_start 252 +#define GEN7_RENDER_SURFACE_STATE_AlphaClearColor_start 252 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_AlphaClearColor_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 480; + case 10: return 480; + case 9: return 480; + case 8: return 252; + case 7: + if (devinfo->is_haswell) { + return 252; + } else { + return 252; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Append Counter Address */ + + +#define GEN75_RENDER_SURFACE_STATE_AppendCounterAddress_bits 26 +#define GEN7_RENDER_SURFACE_STATE_AppendCounterAddress_bits 26 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_AppendCounterAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 26; + } else { + return 26; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_RENDER_SURFACE_STATE_AppendCounterAddress_start 198 +#define GEN7_RENDER_SURFACE_STATE_AppendCounterAddress_start 198 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_AppendCounterAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 198; + } else { + return 198; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Append Counter Enable */ + + +#define GEN75_RENDER_SURFACE_STATE_AppendCounterEnable_bits 1 +#define GEN7_RENDER_SURFACE_STATE_AppendCounterEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_AppendCounterEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_RENDER_SURFACE_STATE_AppendCounterEnable_start 193 +#define GEN7_RENDER_SURFACE_STATE_AppendCounterEnable_start 193 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_AppendCounterEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 193; + } else { + return 193; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Auxiliary Surface Base Address */ + + +#define GEN11_RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_bits 52 +#define GEN10_RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_bits 52 +#define GEN9_RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_bits 52 +#define GEN8_RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_bits 52 +#define GEN75_RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_bits 20 +#define GEN7_RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_bits 20 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 52; + case 10: return 52; + case 9: return 52; + case 8: return 52; + case 7: + if (devinfo->is_haswell) { + return 20; + } else { + return 20; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_start 332 +#define GEN10_RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_start 332 +#define GEN9_RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_start 332 +#define GEN8_RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_start 332 +#define GEN75_RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_start 204 +#define GEN7_RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_start 204 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_AuxiliarySurfaceBaseAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 332; + case 10: return 332; + case 9: return 332; + case 8: return 332; + case 7: + if (devinfo->is_haswell) { + return 204; + } else { + return 204; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Auxiliary Surface Mode */ + + +#define GEN11_RENDER_SURFACE_STATE_AuxiliarySurfaceMode_bits 3 +#define GEN10_RENDER_SURFACE_STATE_AuxiliarySurfaceMode_bits 3 +#define GEN9_RENDER_SURFACE_STATE_AuxiliarySurfaceMode_bits 3 +#define GEN8_RENDER_SURFACE_STATE_AuxiliarySurfaceMode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_AuxiliarySurfaceMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_AuxiliarySurfaceMode_start 192 +#define GEN10_RENDER_SURFACE_STATE_AuxiliarySurfaceMode_start 192 +#define GEN9_RENDER_SURFACE_STATE_AuxiliarySurfaceMode_start 192 +#define GEN8_RENDER_SURFACE_STATE_AuxiliarySurfaceMode_start 192 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_AuxiliarySurfaceMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 192; + case 10: return 192; + case 9: return 192; + case 8: return 192; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Auxiliary Surface Pitch */ + + +#define GEN11_RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits 9 +#define GEN10_RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits 9 +#define GEN9_RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits 9 +#define GEN8_RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits 9 +#define GEN75_RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits 9 +#define GEN7_RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_AuxiliarySurfacePitch_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 9; + case 10: return 9; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 9; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_AuxiliarySurfacePitch_start 195 +#define GEN10_RENDER_SURFACE_STATE_AuxiliarySurfacePitch_start 195 +#define GEN9_RENDER_SURFACE_STATE_AuxiliarySurfacePitch_start 195 +#define GEN8_RENDER_SURFACE_STATE_AuxiliarySurfacePitch_start 195 +#define GEN75_RENDER_SURFACE_STATE_AuxiliarySurfacePitch_start 195 +#define GEN7_RENDER_SURFACE_STATE_AuxiliarySurfacePitch_start 195 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_AuxiliarySurfacePitch_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 195; + case 10: return 195; + case 9: return 195; + case 8: return 195; + case 7: + if (devinfo->is_haswell) { + return 195; + } else { + return 195; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Auxiliary Surface QPitch */ + + +#define GEN11_RENDER_SURFACE_STATE_AuxiliarySurfaceQPitch_bits 15 +#define GEN10_RENDER_SURFACE_STATE_AuxiliarySurfaceQPitch_bits 15 +#define GEN9_RENDER_SURFACE_STATE_AuxiliarySurfaceQPitch_bits 15 +#define GEN8_RENDER_SURFACE_STATE_AuxiliarySurfaceQPitch_bits 15 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_AuxiliarySurfaceQPitch_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 15; + case 10: return 15; + case 9: return 15; + case 8: return 15; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_AuxiliarySurfaceQPitch_start 208 +#define GEN10_RENDER_SURFACE_STATE_AuxiliarySurfaceQPitch_start 208 +#define GEN9_RENDER_SURFACE_STATE_AuxiliarySurfaceQPitch_start 208 +#define GEN8_RENDER_SURFACE_STATE_AuxiliarySurfaceQPitch_start 208 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_AuxiliarySurfaceQPitch_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 208; + case 10: return 208; + case 9: return 208; + case 8: return 208; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Auxiliary Table Index for Media Compressed Surface */ + + +#define GEN11_RENDER_SURFACE_STATE_AuxiliaryTableIndexforMediaCompressedSurface_bits 11 +#define GEN10_RENDER_SURFACE_STATE_AuxiliaryTableIndexforMediaCompressedSurface_bits 11 +#define GEN9_RENDER_SURFACE_STATE_AuxiliaryTableIndexforMediaCompressedSurface_bits 11 +#define GEN8_RENDER_SURFACE_STATE_AuxiliaryTableIndexforMediaCompressedSurface_bits 11 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_AuxiliaryTableIndexforMediaCompressedSurface_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_AuxiliaryTableIndexforMediaCompressedSurface_start 341 +#define GEN10_RENDER_SURFACE_STATE_AuxiliaryTableIndexforMediaCompressedSurface_start 341 +#define GEN9_RENDER_SURFACE_STATE_AuxiliaryTableIndexforMediaCompressedSurface_start 341 +#define GEN8_RENDER_SURFACE_STATE_AuxiliaryTableIndexforMediaCompressedSurface_start 341 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_AuxiliaryTableIndexforMediaCompressedSurface_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 341; + case 10: return 341; + case 9: return 341; + case 8: return 341; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Base Mip Level */ + + +#define GEN11_RENDER_SURFACE_STATE_BaseMipLevel_bits 5 +#define GEN10_RENDER_SURFACE_STATE_BaseMipLevel_bits 5 +#define GEN9_RENDER_SURFACE_STATE_BaseMipLevel_bits 5 +#define GEN8_RENDER_SURFACE_STATE_BaseMipLevel_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_BaseMipLevel_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_BaseMipLevel_start 51 +#define GEN10_RENDER_SURFACE_STATE_BaseMipLevel_start 51 +#define GEN9_RENDER_SURFACE_STATE_BaseMipLevel_start 51 +#define GEN8_RENDER_SURFACE_STATE_BaseMipLevel_start 51 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_BaseMipLevel_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 51; + case 10: return 51; + case 9: return 51; + case 8: return 51; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Blue Clear Color */ + + +#define GEN11_RENDER_SURFACE_STATE_BlueClearColor_bits 32 +#define GEN10_RENDER_SURFACE_STATE_BlueClearColor_bits 32 +#define GEN9_RENDER_SURFACE_STATE_BlueClearColor_bits 32 +#define GEN8_RENDER_SURFACE_STATE_BlueClearColor_bits 1 +#define GEN75_RENDER_SURFACE_STATE_BlueClearColor_bits 1 +#define GEN7_RENDER_SURFACE_STATE_BlueClearColor_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_BlueClearColor_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_BlueClearColor_start 448 +#define GEN10_RENDER_SURFACE_STATE_BlueClearColor_start 448 +#define GEN9_RENDER_SURFACE_STATE_BlueClearColor_start 448 +#define GEN8_RENDER_SURFACE_STATE_BlueClearColor_start 253 +#define GEN75_RENDER_SURFACE_STATE_BlueClearColor_start 253 +#define GEN7_RENDER_SURFACE_STATE_BlueClearColor_start 253 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_BlueClearColor_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 448; + case 10: return 448; + case 9: return 448; + case 8: return 253; + case 7: + if (devinfo->is_haswell) { + return 253; + } else { + return 253; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Clear Color Conversion Enable */ + + +#define GEN11_RENDER_SURFACE_STATE_ClearColorConversionEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_ClearColorConversionEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_ClearColorConversionEnable_start 389 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_ClearColorConversionEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 389; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Clear Value Address */ + + +#define GEN11_RENDER_SURFACE_STATE_ClearValueAddress_bits 42 +#define GEN10_RENDER_SURFACE_STATE_ClearValueAddress_bits 42 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_ClearValueAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 42; + case 10: return 42; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_ClearValueAddress_start 390 +#define GEN10_RENDER_SURFACE_STATE_ClearValueAddress_start 390 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_ClearValueAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 390; + case 10: return 390; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Clear Value Address Enable */ + + +#define GEN11_RENDER_SURFACE_STATE_ClearValueAddressEnable_bits 1 +#define GEN10_RENDER_SURFACE_STATE_ClearValueAddressEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_ClearValueAddressEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_ClearValueAddressEnable_start 330 +#define GEN10_RENDER_SURFACE_STATE_ClearValueAddressEnable_start 330 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_ClearValueAddressEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 330; + case 10: return 330; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Coherency Type */ + + +#define GEN11_RENDER_SURFACE_STATE_CoherencyType_bits 1 +#define GEN10_RENDER_SURFACE_STATE_CoherencyType_bits 1 +#define GEN9_RENDER_SURFACE_STATE_CoherencyType_bits 1 +#define GEN8_RENDER_SURFACE_STATE_CoherencyType_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_CoherencyType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_CoherencyType_start 174 +#define GEN10_RENDER_SURFACE_STATE_CoherencyType_start 174 +#define GEN9_RENDER_SURFACE_STATE_CoherencyType_start 174 +#define GEN8_RENDER_SURFACE_STATE_CoherencyType_start 174 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_CoherencyType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 174; + case 10: return 174; + case 9: return 174; + case 8: return 174; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Color Blend Enable */ + + +#define GEN5_RENDER_SURFACE_STATE_ColorBlendEnable_bits 1 +#define GEN45_RENDER_SURFACE_STATE_ColorBlendEnable_bits 1 +#define GEN4_RENDER_SURFACE_STATE_ColorBlendEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_ColorBlendEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_RENDER_SURFACE_STATE_ColorBlendEnable_start 13 +#define GEN45_RENDER_SURFACE_STATE_ColorBlendEnable_start 13 +#define GEN4_RENDER_SURFACE_STATE_ColorBlendEnable_start 13 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_ColorBlendEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 13; + case 4: + if (devinfo->is_g4x) { + return 13; + } else { + return 13; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Color Buffer Component Write Disables */ + + +#define GEN5_RENDER_SURFACE_STATE_ColorBufferComponentWriteDisables_bits 4 +#define GEN45_RENDER_SURFACE_STATE_ColorBufferComponentWriteDisables_bits 4 +#define GEN4_RENDER_SURFACE_STATE_ColorBufferComponentWriteDisables_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_ColorBufferComponentWriteDisables_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 4; + case 4: + if (devinfo->is_g4x) { + return 4; + } else { + return 4; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_RENDER_SURFACE_STATE_ColorBufferComponentWriteDisables_start 14 +#define GEN45_RENDER_SURFACE_STATE_ColorBufferComponentWriteDisables_start 14 +#define GEN4_RENDER_SURFACE_STATE_ColorBufferComponentWriteDisables_start 14 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_ColorBufferComponentWriteDisables_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 14; + case 4: + if (devinfo->is_g4x) { + return 14; + } else { + return 14; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Cube Face Enable - Negative X */ + + +#define GEN11_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_bits 1 +#define GEN10_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_bits 1 +#define GEN9_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_bits 1 +#define GEN8_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_bits 1 +#define GEN75_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_bits 1 +#define GEN7_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_bits 1 +#define GEN6_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_bits 1 +#define GEN5_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_bits 1 +#define GEN45_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_bits 1 +#define GEN4_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_start 5 +#define GEN10_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_start 5 +#define GEN9_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_start 5 +#define GEN8_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_start 5 +#define GEN75_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_start 5 +#define GEN7_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_start 5 +#define GEN6_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_start 5 +#define GEN5_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_start 5 +#define GEN45_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_start 5 +#define GEN4_RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_start 5 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_CubeFaceEnableNegativeX_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 5; + } + case 6: return 5; + case 5: return 5; + case 4: + if (devinfo->is_g4x) { + return 5; + } else { + return 5; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Cube Face Enable - Negative Y */ + + +#define GEN11_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_bits 1 +#define GEN10_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_bits 1 +#define GEN9_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_bits 1 +#define GEN8_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_bits 1 +#define GEN75_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_bits 1 +#define GEN7_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_bits 1 +#define GEN6_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_bits 1 +#define GEN5_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_bits 1 +#define GEN45_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_bits 1 +#define GEN4_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_start 3 +#define GEN10_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_start 3 +#define GEN9_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_start 3 +#define GEN8_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_start 3 +#define GEN75_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_start 3 +#define GEN7_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_start 3 +#define GEN6_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_start 3 +#define GEN5_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_start 3 +#define GEN45_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_start 3 +#define GEN4_RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_start 3 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_CubeFaceEnableNegativeY_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Cube Face Enable - Negative Z */ + + +#define GEN11_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_bits 1 +#define GEN10_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_bits 1 +#define GEN9_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_bits 1 +#define GEN8_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_bits 1 +#define GEN75_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_bits 1 +#define GEN7_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_bits 1 +#define GEN6_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_bits 1 +#define GEN5_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_bits 1 +#define GEN45_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_bits 1 +#define GEN4_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_start 1 +#define GEN10_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_start 1 +#define GEN9_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_start 1 +#define GEN8_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_start 1 +#define GEN75_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_start 1 +#define GEN7_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_start 1 +#define GEN6_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_start 1 +#define GEN5_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_start 1 +#define GEN45_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_start 1 +#define GEN4_RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_start 1 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_CubeFaceEnableNegativeZ_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Cube Face Enable - Positive X */ + + +#define GEN11_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_bits 1 +#define GEN10_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_bits 1 +#define GEN9_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_bits 1 +#define GEN8_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_bits 1 +#define GEN75_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_bits 1 +#define GEN7_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_bits 1 +#define GEN6_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_bits 1 +#define GEN5_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_bits 1 +#define GEN45_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_bits 1 +#define GEN4_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_start 4 +#define GEN10_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_start 4 +#define GEN9_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_start 4 +#define GEN8_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_start 4 +#define GEN75_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_start 4 +#define GEN7_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_start 4 +#define GEN6_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_start 4 +#define GEN5_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_start 4 +#define GEN45_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_start 4 +#define GEN4_RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_start 4 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_CubeFaceEnablePositiveX_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 4; + case 4: + if (devinfo->is_g4x) { + return 4; + } else { + return 4; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Cube Face Enable - Positive Y */ + + +#define GEN11_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_bits 1 +#define GEN10_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_bits 1 +#define GEN9_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_bits 1 +#define GEN8_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_bits 1 +#define GEN75_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_bits 1 +#define GEN7_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_bits 1 +#define GEN6_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_bits 1 +#define GEN5_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_bits 1 +#define GEN45_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_bits 1 +#define GEN4_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_start 2 +#define GEN10_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_start 2 +#define GEN9_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_start 2 +#define GEN8_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_start 2 +#define GEN75_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_start 2 +#define GEN7_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_start 2 +#define GEN6_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_start 2 +#define GEN5_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_start 2 +#define GEN45_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_start 2 +#define GEN4_RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_start 2 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_CubeFaceEnablePositiveY_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Cube Face Enable - Positive Z */ + + +#define GEN11_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_bits 1 +#define GEN10_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_bits 1 +#define GEN9_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_bits 1 +#define GEN8_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_bits 1 +#define GEN75_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_bits 1 +#define GEN7_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_bits 1 +#define GEN6_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_bits 1 +#define GEN5_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_bits 1 +#define GEN45_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_bits 1 +#define GEN4_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_start 0 +#define GEN10_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_start 0 +#define GEN9_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_start 0 +#define GEN8_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_start 0 +#define GEN75_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_start 0 +#define GEN7_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_start 0 +#define GEN6_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_start 0 +#define GEN5_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_start 0 +#define GEN45_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_start 0 +#define GEN4_RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_start 0 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_CubeFaceEnablePositiveZ_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Cube Map Corner Mode */ + + +#define GEN6_RENDER_SURFACE_STATE_CubeMapCornerMode_bits 1 +#define GEN5_RENDER_SURFACE_STATE_CubeMapCornerMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_CubeMapCornerMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_RENDER_SURFACE_STATE_CubeMapCornerMode_start 9 +#define GEN5_RENDER_SURFACE_STATE_CubeMapCornerMode_start 9 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_CubeMapCornerMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 9; + case 5: return 9; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Data Return Format */ + + +#define GEN6_RENDER_SURFACE_STATE_DataReturnFormat_bits 1 +#define GEN5_RENDER_SURFACE_STATE_DataReturnFormat_bits 1 +#define GEN45_RENDER_SURFACE_STATE_DataReturnFormat_bits 1 +#define GEN4_RENDER_SURFACE_STATE_DataReturnFormat_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_DataReturnFormat_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_RENDER_SURFACE_STATE_DataReturnFormat_start 27 +#define GEN5_RENDER_SURFACE_STATE_DataReturnFormat_start 27 +#define GEN45_RENDER_SURFACE_STATE_DataReturnFormat_start 27 +#define GEN4_RENDER_SURFACE_STATE_DataReturnFormat_start 27 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_DataReturnFormat_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 27; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Depth */ + + +#define GEN11_RENDER_SURFACE_STATE_Depth_bits 11 +#define GEN10_RENDER_SURFACE_STATE_Depth_bits 11 +#define GEN9_RENDER_SURFACE_STATE_Depth_bits 11 +#define GEN8_RENDER_SURFACE_STATE_Depth_bits 11 +#define GEN75_RENDER_SURFACE_STATE_Depth_bits 11 +#define GEN7_RENDER_SURFACE_STATE_Depth_bits 11 +#define GEN6_RENDER_SURFACE_STATE_Depth_bits 11 +#define GEN5_RENDER_SURFACE_STATE_Depth_bits 11 +#define GEN45_RENDER_SURFACE_STATE_Depth_bits 11 +#define GEN4_RENDER_SURFACE_STATE_Depth_bits 11 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_Depth_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 11; + } else { + return 11; + } + case 6: return 11; + case 5: return 11; + case 4: + if (devinfo->is_g4x) { + return 11; + } else { + return 11; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_Depth_start 117 +#define GEN10_RENDER_SURFACE_STATE_Depth_start 117 +#define GEN9_RENDER_SURFACE_STATE_Depth_start 117 +#define GEN8_RENDER_SURFACE_STATE_Depth_start 117 +#define GEN75_RENDER_SURFACE_STATE_Depth_start 117 +#define GEN7_RENDER_SURFACE_STATE_Depth_start 117 +#define GEN6_RENDER_SURFACE_STATE_Depth_start 117 +#define GEN5_RENDER_SURFACE_STATE_Depth_start 117 +#define GEN45_RENDER_SURFACE_STATE_Depth_start 117 +#define GEN4_RENDER_SURFACE_STATE_Depth_start 117 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_Depth_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 117; + case 10: return 117; + case 9: return 117; + case 8: return 117; + case 7: + if (devinfo->is_haswell) { + return 117; + } else { + return 117; + } + case 6: return 117; + case 5: return 117; + case 4: + if (devinfo->is_g4x) { + return 117; + } else { + return 117; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::EWA Disable For Cube */ + + +#define GEN11_RENDER_SURFACE_STATE_EWADisableForCube_bits 1 +#define GEN10_RENDER_SURFACE_STATE_EWADisableForCube_bits 1 +#define GEN9_RENDER_SURFACE_STATE_EWADisableForCube_bits 1 +#define GEN8_RENDER_SURFACE_STATE_EWADisableForCube_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_EWADisableForCube_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_EWADisableForCube_start 180 +#define GEN10_RENDER_SURFACE_STATE_EWADisableForCube_start 180 +#define GEN9_RENDER_SURFACE_STATE_EWADisableForCube_start 180 +#define GEN8_RENDER_SURFACE_STATE_EWADisableForCube_start 180 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_EWADisableForCube_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 180; + case 10: return 180; + case 9: return 180; + case 8: return 180; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Force Non-Comparison Reduction Type */ + + +#define GEN11_RENDER_SURFACE_STATE_ForceNonComparisonReductionType_bits 1 +#define GEN10_RENDER_SURFACE_STATE_ForceNonComparisonReductionType_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_ForceNonComparisonReductionType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_ForceNonComparisonReductionType_start 159 +#define GEN10_RENDER_SURFACE_STATE_ForceNonComparisonReductionType_start 159 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_ForceNonComparisonReductionType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 159; + case 10: return 159; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Green Clear Color */ + + +#define GEN11_RENDER_SURFACE_STATE_GreenClearColor_bits 32 +#define GEN10_RENDER_SURFACE_STATE_GreenClearColor_bits 32 +#define GEN9_RENDER_SURFACE_STATE_GreenClearColor_bits 32 +#define GEN8_RENDER_SURFACE_STATE_GreenClearColor_bits 1 +#define GEN75_RENDER_SURFACE_STATE_GreenClearColor_bits 1 +#define GEN7_RENDER_SURFACE_STATE_GreenClearColor_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_GreenClearColor_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_GreenClearColor_start 416 +#define GEN10_RENDER_SURFACE_STATE_GreenClearColor_start 416 +#define GEN9_RENDER_SURFACE_STATE_GreenClearColor_start 416 +#define GEN8_RENDER_SURFACE_STATE_GreenClearColor_start 254 +#define GEN75_RENDER_SURFACE_STATE_GreenClearColor_start 254 +#define GEN7_RENDER_SURFACE_STATE_GreenClearColor_start 254 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_GreenClearColor_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 416; + case 10: return 416; + case 9: return 416; + case 8: return 254; + case 7: + if (devinfo->is_haswell) { + return 254; + } else { + return 254; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Height */ + + +#define GEN11_RENDER_SURFACE_STATE_Height_bits 14 +#define GEN10_RENDER_SURFACE_STATE_Height_bits 14 +#define GEN9_RENDER_SURFACE_STATE_Height_bits 14 +#define GEN8_RENDER_SURFACE_STATE_Height_bits 14 +#define GEN75_RENDER_SURFACE_STATE_Height_bits 14 +#define GEN7_RENDER_SURFACE_STATE_Height_bits 14 +#define GEN6_RENDER_SURFACE_STATE_Height_bits 13 +#define GEN5_RENDER_SURFACE_STATE_Height_bits 13 +#define GEN45_RENDER_SURFACE_STATE_Height_bits 13 +#define GEN4_RENDER_SURFACE_STATE_Height_bits 13 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_Height_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 14; + case 10: return 14; + case 9: return 14; + case 8: return 14; + case 7: + if (devinfo->is_haswell) { + return 14; + } else { + return 14; + } + case 6: return 13; + case 5: return 13; + case 4: + if (devinfo->is_g4x) { + return 13; + } else { + return 13; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_Height_start 80 +#define GEN10_RENDER_SURFACE_STATE_Height_start 80 +#define GEN9_RENDER_SURFACE_STATE_Height_start 80 +#define GEN8_RENDER_SURFACE_STATE_Height_start 80 +#define GEN75_RENDER_SURFACE_STATE_Height_start 80 +#define GEN7_RENDER_SURFACE_STATE_Height_start 80 +#define GEN6_RENDER_SURFACE_STATE_Height_start 83 +#define GEN5_RENDER_SURFACE_STATE_Height_start 83 +#define GEN45_RENDER_SURFACE_STATE_Height_start 83 +#define GEN4_RENDER_SURFACE_STATE_Height_start 83 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_Height_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 80; + case 10: return 80; + case 9: return 80; + case 8: return 80; + case 7: + if (devinfo->is_haswell) { + return 80; + } else { + return 80; + } + case 6: return 83; + case 5: return 83; + case 4: + if (devinfo->is_g4x) { + return 83; + } else { + return 83; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Hierarchical Depth Clear Value */ + + +#define GEN9_RENDER_SURFACE_STATE_HierarchicalDepthClearValue_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_HierarchicalDepthClearValue_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 32; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_RENDER_SURFACE_STATE_HierarchicalDepthClearValue_start 384 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_HierarchicalDepthClearValue_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 384; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Integer Surface Format */ + + +#define GEN75_RENDER_SURFACE_STATE_IntegerSurfaceFormat_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_IntegerSurfaceFormat_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_RENDER_SURFACE_STATE_IntegerSurfaceFormat_start 114 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_IntegerSurfaceFormat_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 114; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::MCS Enable */ + + +#define GEN75_RENDER_SURFACE_STATE_MCSEnable_bits 1 +#define GEN7_RENDER_SURFACE_STATE_MCSEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_MCSEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_RENDER_SURFACE_STATE_MCSEnable_start 192 +#define GEN7_RENDER_SURFACE_STATE_MCSEnable_start 192 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_MCSEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 192; + } else { + return 192; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::MIP Count / LOD */ + + +#define GEN11_RENDER_SURFACE_STATE_MIPCountLOD_bits 4 +#define GEN10_RENDER_SURFACE_STATE_MIPCountLOD_bits 4 +#define GEN9_RENDER_SURFACE_STATE_MIPCountLOD_bits 4 +#define GEN8_RENDER_SURFACE_STATE_MIPCountLOD_bits 4 +#define GEN75_RENDER_SURFACE_STATE_MIPCountLOD_bits 4 +#define GEN7_RENDER_SURFACE_STATE_MIPCountLOD_bits 4 +#define GEN6_RENDER_SURFACE_STATE_MIPCountLOD_bits 4 +#define GEN5_RENDER_SURFACE_STATE_MIPCountLOD_bits 4 +#define GEN45_RENDER_SURFACE_STATE_MIPCountLOD_bits 4 +#define GEN4_RENDER_SURFACE_STATE_MIPCountLOD_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_MIPCountLOD_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 4; + case 4: + if (devinfo->is_g4x) { + return 4; + } else { + return 4; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_MIPCountLOD_start 160 +#define GEN10_RENDER_SURFACE_STATE_MIPCountLOD_start 160 +#define GEN9_RENDER_SURFACE_STATE_MIPCountLOD_start 160 +#define GEN8_RENDER_SURFACE_STATE_MIPCountLOD_start 160 +#define GEN75_RENDER_SURFACE_STATE_MIPCountLOD_start 160 +#define GEN7_RENDER_SURFACE_STATE_MIPCountLOD_start 160 +#define GEN6_RENDER_SURFACE_STATE_MIPCountLOD_start 66 +#define GEN5_RENDER_SURFACE_STATE_MIPCountLOD_start 66 +#define GEN45_RENDER_SURFACE_STATE_MIPCountLOD_start 66 +#define GEN4_RENDER_SURFACE_STATE_MIPCountLOD_start 66 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_MIPCountLOD_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 160; + case 10: return 160; + case 9: return 160; + case 8: return 160; + case 7: + if (devinfo->is_haswell) { + return 160; + } else { + return 160; + } + case 6: return 66; + case 5: return 66; + case 4: + if (devinfo->is_g4x) { + return 66; + } else { + return 66; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::MIP Map Layout Mode */ + + +#define GEN6_RENDER_SURFACE_STATE_MIPMapLayoutMode_bits 1 +#define GEN5_RENDER_SURFACE_STATE_MIPMapLayoutMode_bits 1 +#define GEN45_RENDER_SURFACE_STATE_MIPMapLayoutMode_bits 1 +#define GEN4_RENDER_SURFACE_STATE_MIPMapLayoutMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_MIPMapLayoutMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_RENDER_SURFACE_STATE_MIPMapLayoutMode_start 10 +#define GEN5_RENDER_SURFACE_STATE_MIPMapLayoutMode_start 10 +#define GEN45_RENDER_SURFACE_STATE_MIPMapLayoutMode_start 10 +#define GEN4_RENDER_SURFACE_STATE_MIPMapLayoutMode_start 10 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_MIPMapLayoutMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 10; + case 5: return 10; + case 4: + if (devinfo->is_g4x) { + return 10; + } else { + return 10; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::MOCS */ + + +#define GEN11_RENDER_SURFACE_STATE_MOCS_bits 7 +#define GEN10_RENDER_SURFACE_STATE_MOCS_bits 7 +#define GEN9_RENDER_SURFACE_STATE_MOCS_bits 7 +#define GEN8_RENDER_SURFACE_STATE_MOCS_bits 7 +#define GEN75_RENDER_SURFACE_STATE_MOCS_bits 4 +#define GEN7_RENDER_SURFACE_STATE_MOCS_bits 4 +#define GEN6_RENDER_SURFACE_STATE_MOCS_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_MOCS_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_MOCS_start 56 +#define GEN10_RENDER_SURFACE_STATE_MOCS_start 56 +#define GEN9_RENDER_SURFACE_STATE_MOCS_start 56 +#define GEN8_RENDER_SURFACE_STATE_MOCS_start 56 +#define GEN75_RENDER_SURFACE_STATE_MOCS_start 176 +#define GEN7_RENDER_SURFACE_STATE_MOCS_start 176 +#define GEN6_RENDER_SURFACE_STATE_MOCS_start 176 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_MOCS_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 56; + case 10: return 56; + case 9: return 56; + case 8: return 56; + case 7: + if (devinfo->is_haswell) { + return 176; + } else { + return 176; + } + case 6: return 176; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Media Boundary Pixel Mode */ + + +#define GEN11_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_bits 2 +#define GEN10_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_bits 2 +#define GEN9_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_bits 2 +#define GEN8_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_bits 2 +#define GEN75_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_bits 2 +#define GEN7_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_bits 2 +#define GEN6_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_bits 2 +#define GEN5_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_bits 2 +#define GEN45_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_bits 2 +#define GEN4_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_MediaBoundaryPixelMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_start 6 +#define GEN10_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_start 6 +#define GEN9_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_start 6 +#define GEN8_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_start 6 +#define GEN75_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_start 6 +#define GEN7_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_start 6 +#define GEN6_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_start 6 +#define GEN5_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_start 6 +#define GEN45_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_start 6 +#define GEN4_RENDER_SURFACE_STATE_MediaBoundaryPixelMode_start 6 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_MediaBoundaryPixelMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 6; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Memory Compression Enable */ + + +#define GEN11_RENDER_SURFACE_STATE_MemoryCompressionEnable_bits 1 +#define GEN10_RENDER_SURFACE_STATE_MemoryCompressionEnable_bits 1 +#define GEN9_RENDER_SURFACE_STATE_MemoryCompressionEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_MemoryCompressionEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_MemoryCompressionEnable_start 254 +#define GEN10_RENDER_SURFACE_STATE_MemoryCompressionEnable_start 254 +#define GEN9_RENDER_SURFACE_STATE_MemoryCompressionEnable_start 254 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_MemoryCompressionEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 254; + case 10: return 254; + case 9: return 254; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Memory Compression Mode */ + + +#define GEN11_RENDER_SURFACE_STATE_MemoryCompressionMode_bits 1 +#define GEN10_RENDER_SURFACE_STATE_MemoryCompressionMode_bits 1 +#define GEN9_RENDER_SURFACE_STATE_MemoryCompressionMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_MemoryCompressionMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_MemoryCompressionMode_start 255 +#define GEN10_RENDER_SURFACE_STATE_MemoryCompressionMode_start 255 +#define GEN9_RENDER_SURFACE_STATE_MemoryCompressionMode_start 255 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_MemoryCompressionMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 255; + case 10: return 255; + case 9: return 255; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Minimum Array Element */ + + +#define GEN11_RENDER_SURFACE_STATE_MinimumArrayElement_bits 11 +#define GEN10_RENDER_SURFACE_STATE_MinimumArrayElement_bits 11 +#define GEN9_RENDER_SURFACE_STATE_MinimumArrayElement_bits 11 +#define GEN8_RENDER_SURFACE_STATE_MinimumArrayElement_bits 11 +#define GEN75_RENDER_SURFACE_STATE_MinimumArrayElement_bits 11 +#define GEN7_RENDER_SURFACE_STATE_MinimumArrayElement_bits 11 +#define GEN6_RENDER_SURFACE_STATE_MinimumArrayElement_bits 11 +#define GEN5_RENDER_SURFACE_STATE_MinimumArrayElement_bits 11 +#define GEN45_RENDER_SURFACE_STATE_MinimumArrayElement_bits 11 +#define GEN4_RENDER_SURFACE_STATE_MinimumArrayElement_bits 11 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_MinimumArrayElement_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 11; + } else { + return 11; + } + case 6: return 11; + case 5: return 11; + case 4: + if (devinfo->is_g4x) { + return 11; + } else { + return 11; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_MinimumArrayElement_start 146 +#define GEN10_RENDER_SURFACE_STATE_MinimumArrayElement_start 146 +#define GEN9_RENDER_SURFACE_STATE_MinimumArrayElement_start 146 +#define GEN8_RENDER_SURFACE_STATE_MinimumArrayElement_start 146 +#define GEN75_RENDER_SURFACE_STATE_MinimumArrayElement_start 146 +#define GEN7_RENDER_SURFACE_STATE_MinimumArrayElement_start 146 +#define GEN6_RENDER_SURFACE_STATE_MinimumArrayElement_start 145 +#define GEN5_RENDER_SURFACE_STATE_MinimumArrayElement_start 145 +#define GEN45_RENDER_SURFACE_STATE_MinimumArrayElement_start 145 +#define GEN4_RENDER_SURFACE_STATE_MinimumArrayElement_start 145 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_MinimumArrayElement_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 146; + case 10: return 146; + case 9: return 146; + case 8: return 146; + case 7: + if (devinfo->is_haswell) { + return 146; + } else { + return 146; + } + case 6: return 145; + case 5: return 145; + case 4: + if (devinfo->is_g4x) { + return 145; + } else { + return 145; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Mip Tail Start LOD */ + + +#define GEN11_RENDER_SURFACE_STATE_MipTailStartLOD_bits 4 +#define GEN10_RENDER_SURFACE_STATE_MipTailStartLOD_bits 4 +#define GEN9_RENDER_SURFACE_STATE_MipTailStartLOD_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_MipTailStartLOD_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_MipTailStartLOD_start 168 +#define GEN10_RENDER_SURFACE_STATE_MipTailStartLOD_start 168 +#define GEN9_RENDER_SURFACE_STATE_MipTailStartLOD_start 168 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_MipTailStartLOD_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 168; + case 10: return 168; + case 9: return 168; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Multisample Position Palette Index */ + + +#define GEN11_RENDER_SURFACE_STATE_MultisamplePositionPaletteIndex_bits 3 +#define GEN10_RENDER_SURFACE_STATE_MultisamplePositionPaletteIndex_bits 3 +#define GEN9_RENDER_SURFACE_STATE_MultisamplePositionPaletteIndex_bits 3 +#define GEN8_RENDER_SURFACE_STATE_MultisamplePositionPaletteIndex_bits 3 +#define GEN75_RENDER_SURFACE_STATE_MultisamplePositionPaletteIndex_bits 3 +#define GEN7_RENDER_SURFACE_STATE_MultisamplePositionPaletteIndex_bits 3 +#define GEN6_RENDER_SURFACE_STATE_MultisamplePositionPaletteIndex_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_MultisamplePositionPaletteIndex_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_MultisamplePositionPaletteIndex_start 128 +#define GEN10_RENDER_SURFACE_STATE_MultisamplePositionPaletteIndex_start 128 +#define GEN9_RENDER_SURFACE_STATE_MultisamplePositionPaletteIndex_start 128 +#define GEN8_RENDER_SURFACE_STATE_MultisamplePositionPaletteIndex_start 128 +#define GEN75_RENDER_SURFACE_STATE_MultisamplePositionPaletteIndex_start 128 +#define GEN7_RENDER_SURFACE_STATE_MultisamplePositionPaletteIndex_start 128 +#define GEN6_RENDER_SURFACE_STATE_MultisamplePositionPaletteIndex_start 128 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_MultisamplePositionPaletteIndex_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 128; + case 10: return 128; + case 9: return 128; + case 8: return 128; + case 7: + if (devinfo->is_haswell) { + return 128; + } else { + return 128; + } + case 6: return 128; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Multisampled Surface Storage Format */ + + +#define GEN11_RENDER_SURFACE_STATE_MultisampledSurfaceStorageFormat_bits 1 +#define GEN10_RENDER_SURFACE_STATE_MultisampledSurfaceStorageFormat_bits 1 +#define GEN9_RENDER_SURFACE_STATE_MultisampledSurfaceStorageFormat_bits 1 +#define GEN8_RENDER_SURFACE_STATE_MultisampledSurfaceStorageFormat_bits 1 +#define GEN75_RENDER_SURFACE_STATE_MultisampledSurfaceStorageFormat_bits 1 +#define GEN7_RENDER_SURFACE_STATE_MultisampledSurfaceStorageFormat_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_MultisampledSurfaceStorageFormat_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_MultisampledSurfaceStorageFormat_start 134 +#define GEN10_RENDER_SURFACE_STATE_MultisampledSurfaceStorageFormat_start 134 +#define GEN9_RENDER_SURFACE_STATE_MultisampledSurfaceStorageFormat_start 134 +#define GEN8_RENDER_SURFACE_STATE_MultisampledSurfaceStorageFormat_start 134 +#define GEN75_RENDER_SURFACE_STATE_MultisampledSurfaceStorageFormat_start 134 +#define GEN7_RENDER_SURFACE_STATE_MultisampledSurfaceStorageFormat_start 134 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_MultisampledSurfaceStorageFormat_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 134; + case 10: return 134; + case 9: return 134; + case 8: return 134; + case 7: + if (devinfo->is_haswell) { + return 134; + } else { + return 134; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Number of Multisamples */ + + +#define GEN11_RENDER_SURFACE_STATE_NumberofMultisamples_bits 3 +#define GEN10_RENDER_SURFACE_STATE_NumberofMultisamples_bits 3 +#define GEN9_RENDER_SURFACE_STATE_NumberofMultisamples_bits 3 +#define GEN8_RENDER_SURFACE_STATE_NumberofMultisamples_bits 3 +#define GEN75_RENDER_SURFACE_STATE_NumberofMultisamples_bits 3 +#define GEN7_RENDER_SURFACE_STATE_NumberofMultisamples_bits 3 +#define GEN6_RENDER_SURFACE_STATE_NumberofMultisamples_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_NumberofMultisamples_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_NumberofMultisamples_start 131 +#define GEN10_RENDER_SURFACE_STATE_NumberofMultisamples_start 131 +#define GEN9_RENDER_SURFACE_STATE_NumberofMultisamples_start 131 +#define GEN8_RENDER_SURFACE_STATE_NumberofMultisamples_start 131 +#define GEN75_RENDER_SURFACE_STATE_NumberofMultisamples_start 131 +#define GEN7_RENDER_SURFACE_STATE_NumberofMultisamples_start 131 +#define GEN6_RENDER_SURFACE_STATE_NumberofMultisamples_start 132 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_NumberofMultisamples_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 131; + case 10: return 131; + case 9: return 131; + case 8: return 131; + case 7: + if (devinfo->is_haswell) { + return 131; + } else { + return 131; + } + case 6: return 132; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Quilt Height */ + + +#define GEN11_RENDER_SURFACE_STATE_QuiltHeight_bits 5 +#define GEN10_RENDER_SURFACE_STATE_QuiltHeight_bits 5 +#define GEN9_RENDER_SURFACE_STATE_QuiltHeight_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_QuiltHeight_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_QuiltHeight_start 325 +#define GEN10_RENDER_SURFACE_STATE_QuiltHeight_start 325 +#define GEN9_RENDER_SURFACE_STATE_QuiltHeight_start 325 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_QuiltHeight_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 325; + case 10: return 325; + case 9: return 325; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Quilt Width */ + + +#define GEN11_RENDER_SURFACE_STATE_QuiltWidth_bits 5 +#define GEN10_RENDER_SURFACE_STATE_QuiltWidth_bits 5 +#define GEN9_RENDER_SURFACE_STATE_QuiltWidth_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_QuiltWidth_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_QuiltWidth_start 320 +#define GEN10_RENDER_SURFACE_STATE_QuiltWidth_start 320 +#define GEN9_RENDER_SURFACE_STATE_QuiltWidth_start 320 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_QuiltWidth_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 320; + case 10: return 320; + case 9: return 320; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Red Clear Color */ + + +#define GEN11_RENDER_SURFACE_STATE_RedClearColor_bits 32 +#define GEN10_RENDER_SURFACE_STATE_RedClearColor_bits 32 +#define GEN9_RENDER_SURFACE_STATE_RedClearColor_bits 32 +#define GEN8_RENDER_SURFACE_STATE_RedClearColor_bits 1 +#define GEN75_RENDER_SURFACE_STATE_RedClearColor_bits 1 +#define GEN7_RENDER_SURFACE_STATE_RedClearColor_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_RedClearColor_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_RedClearColor_start 384 +#define GEN10_RENDER_SURFACE_STATE_RedClearColor_start 384 +#define GEN9_RENDER_SURFACE_STATE_RedClearColor_start 384 +#define GEN8_RENDER_SURFACE_STATE_RedClearColor_start 255 +#define GEN75_RENDER_SURFACE_STATE_RedClearColor_start 255 +#define GEN7_RENDER_SURFACE_STATE_RedClearColor_start 255 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_RedClearColor_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 384; + case 10: return 384; + case 9: return 384; + case 8: return 255; + case 7: + if (devinfo->is_haswell) { + return 255; + } else { + return 255; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Render Cache Read Write Mode */ + + +#define GEN11_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_bits 1 +#define GEN10_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_bits 1 +#define GEN9_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_bits 1 +#define GEN8_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_bits 1 +#define GEN75_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_bits 1 +#define GEN7_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_bits 1 +#define GEN6_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_bits 1 +#define GEN5_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_bits 1 +#define GEN45_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_bits 1 +#define GEN4_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_RenderCacheReadWriteMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_start 8 +#define GEN10_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_start 8 +#define GEN9_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_start 8 +#define GEN8_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_start 8 +#define GEN75_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_start 8 +#define GEN7_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_start 8 +#define GEN6_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_start 8 +#define GEN5_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_start 8 +#define GEN45_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_start 8 +#define GEN4_RENDER_SURFACE_STATE_RenderCacheReadWriteMode_start 8 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_RenderCacheReadWriteMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Render Target And Sample Unorm Rotation */ + + +#define GEN11_RENDER_SURFACE_STATE_RenderTargetAndSampleUnormRotation_bits 2 +#define GEN10_RENDER_SURFACE_STATE_RenderTargetAndSampleUnormRotation_bits 2 +#define GEN9_RENDER_SURFACE_STATE_RenderTargetAndSampleUnormRotation_bits 2 +#define GEN8_RENDER_SURFACE_STATE_RenderTargetAndSampleUnormRotation_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_RenderTargetAndSampleUnormRotation_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_RenderTargetAndSampleUnormRotation_start 157 +#define GEN10_RENDER_SURFACE_STATE_RenderTargetAndSampleUnormRotation_start 157 +#define GEN9_RENDER_SURFACE_STATE_RenderTargetAndSampleUnormRotation_start 157 +#define GEN8_RENDER_SURFACE_STATE_RenderTargetAndSampleUnormRotation_start 157 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_RenderTargetAndSampleUnormRotation_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 157; + case 10: return 157; + case 9: return 157; + case 8: return 157; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Render Target Rotation */ + + +#define GEN75_RENDER_SURFACE_STATE_RenderTargetRotation_bits 2 +#define GEN7_RENDER_SURFACE_STATE_RenderTargetRotation_bits 2 +#define GEN6_RENDER_SURFACE_STATE_RenderTargetRotation_bits 2 +#define GEN5_RENDER_SURFACE_STATE_RenderTargetRotation_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_RenderTargetRotation_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_RENDER_SURFACE_STATE_RenderTargetRotation_start 157 +#define GEN7_RENDER_SURFACE_STATE_RenderTargetRotation_start 157 +#define GEN6_RENDER_SURFACE_STATE_RenderTargetRotation_start 64 +#define GEN5_RENDER_SURFACE_STATE_RenderTargetRotation_start 64 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_RenderTargetRotation_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 157; + } else { + return 157; + } + case 6: return 64; + case 5: return 64; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Render Target View Extent */ + + +#define GEN11_RENDER_SURFACE_STATE_RenderTargetViewExtent_bits 11 +#define GEN10_RENDER_SURFACE_STATE_RenderTargetViewExtent_bits 11 +#define GEN9_RENDER_SURFACE_STATE_RenderTargetViewExtent_bits 11 +#define GEN8_RENDER_SURFACE_STATE_RenderTargetViewExtent_bits 11 +#define GEN75_RENDER_SURFACE_STATE_RenderTargetViewExtent_bits 11 +#define GEN7_RENDER_SURFACE_STATE_RenderTargetViewExtent_bits 11 +#define GEN6_RENDER_SURFACE_STATE_RenderTargetViewExtent_bits 9 +#define GEN5_RENDER_SURFACE_STATE_RenderTargetViewExtent_bits 9 +#define GEN45_RENDER_SURFACE_STATE_RenderTargetViewExtent_bits 9 +#define GEN4_RENDER_SURFACE_STATE_RenderTargetViewExtent_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_RenderTargetViewExtent_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 11; + } else { + return 11; + } + case 6: return 9; + case 5: return 9; + case 4: + if (devinfo->is_g4x) { + return 9; + } else { + return 9; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_RenderTargetViewExtent_start 135 +#define GEN10_RENDER_SURFACE_STATE_RenderTargetViewExtent_start 135 +#define GEN9_RENDER_SURFACE_STATE_RenderTargetViewExtent_start 135 +#define GEN8_RENDER_SURFACE_STATE_RenderTargetViewExtent_start 135 +#define GEN75_RENDER_SURFACE_STATE_RenderTargetViewExtent_start 135 +#define GEN7_RENDER_SURFACE_STATE_RenderTargetViewExtent_start 135 +#define GEN6_RENDER_SURFACE_STATE_RenderTargetViewExtent_start 136 +#define GEN5_RENDER_SURFACE_STATE_RenderTargetViewExtent_start 136 +#define GEN45_RENDER_SURFACE_STATE_RenderTargetViewExtent_start 136 +#define GEN4_RENDER_SURFACE_STATE_RenderTargetViewExtent_start 136 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_RenderTargetViewExtent_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 135; + case 10: return 135; + case 9: return 135; + case 8: return 135; + case 7: + if (devinfo->is_haswell) { + return 135; + } else { + return 135; + } + case 6: return 136; + case 5: return 136; + case 4: + if (devinfo->is_g4x) { + return 136; + } else { + return 136; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Reserved: MBZ */ + + +#define GEN75_RENDER_SURFACE_STATE_ReservedMBZ_bits 2 +#define GEN7_RENDER_SURFACE_STATE_ReservedMBZ_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_ReservedMBZ_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_RENDER_SURFACE_STATE_ReservedMBZ_start 222 +#define GEN7_RENDER_SURFACE_STATE_ReservedMBZ_start 222 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_ReservedMBZ_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 222; + } else { + return 222; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Resource Min LOD */ + + +#define GEN11_RENDER_SURFACE_STATE_ResourceMinLOD_bits 12 +#define GEN10_RENDER_SURFACE_STATE_ResourceMinLOD_bits 12 +#define GEN9_RENDER_SURFACE_STATE_ResourceMinLOD_bits 12 +#define GEN8_RENDER_SURFACE_STATE_ResourceMinLOD_bits 12 +#define GEN75_RENDER_SURFACE_STATE_ResourceMinLOD_bits 12 +#define GEN7_RENDER_SURFACE_STATE_ResourceMinLOD_bits 12 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_ResourceMinLOD_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 12; + case 10: return 12; + case 9: return 12; + case 8: return 12; + case 7: + if (devinfo->is_haswell) { + return 12; + } else { + return 12; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_ResourceMinLOD_start 224 +#define GEN10_RENDER_SURFACE_STATE_ResourceMinLOD_start 224 +#define GEN9_RENDER_SURFACE_STATE_ResourceMinLOD_start 224 +#define GEN8_RENDER_SURFACE_STATE_ResourceMinLOD_start 224 +#define GEN75_RENDER_SURFACE_STATE_ResourceMinLOD_start 224 +#define GEN7_RENDER_SURFACE_STATE_ResourceMinLOD_start 224 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_ResourceMinLOD_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 224; + case 10: return 224; + case 9: return 224; + case 8: return 224; + case 7: + if (devinfo->is_haswell) { + return 224; + } else { + return 224; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Sampler L2 Bypass Mode Disable */ + + +#define GEN11_RENDER_SURFACE_STATE_SamplerL2BypassModeDisable_bits 1 +#define GEN10_RENDER_SURFACE_STATE_SamplerL2BypassModeDisable_bits 1 +#define GEN9_RENDER_SURFACE_STATE_SamplerL2BypassModeDisable_bits 1 +#define GEN8_RENDER_SURFACE_STATE_SamplerL2BypassModeDisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_SamplerL2BypassModeDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_SamplerL2BypassModeDisable_start 9 +#define GEN10_RENDER_SURFACE_STATE_SamplerL2BypassModeDisable_start 9 +#define GEN9_RENDER_SURFACE_STATE_SamplerL2BypassModeDisable_start 9 +#define GEN8_RENDER_SURFACE_STATE_SamplerL2BypassModeDisable_start 9 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_SamplerL2BypassModeDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 9; + case 10: return 9; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Separate UV Plane Enable */ + + +#define GEN11_RENDER_SURFACE_STATE_SeparateUVPlaneEnable_bits 1 +#define GEN10_RENDER_SURFACE_STATE_SeparateUVPlaneEnable_bits 1 +#define GEN9_RENDER_SURFACE_STATE_SeparateUVPlaneEnable_bits 1 +#define GEN8_RENDER_SURFACE_STATE_SeparateUVPlaneEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_SeparateUVPlaneEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_SeparateUVPlaneEnable_start 223 +#define GEN10_RENDER_SURFACE_STATE_SeparateUVPlaneEnable_start 223 +#define GEN9_RENDER_SURFACE_STATE_SeparateUVPlaneEnable_start 223 +#define GEN8_RENDER_SURFACE_STATE_SeparateUVPlaneEnable_start 223 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_SeparateUVPlaneEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 223; + case 10: return 223; + case 9: return 223; + case 8: return 223; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Shader Channel Select Alpha */ + + +#define GEN11_RENDER_SURFACE_STATE_ShaderChannelSelectAlpha_bits 3 +#define GEN10_RENDER_SURFACE_STATE_ShaderChannelSelectAlpha_bits 3 +#define GEN9_RENDER_SURFACE_STATE_ShaderChannelSelectAlpha_bits 3 +#define GEN8_RENDER_SURFACE_STATE_ShaderChannelSelectAlpha_bits 3 +#define GEN75_RENDER_SURFACE_STATE_ShaderChannelSelectAlpha_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_ShaderChannelSelectAlpha_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_ShaderChannelSelectAlpha_start 240 +#define GEN10_RENDER_SURFACE_STATE_ShaderChannelSelectAlpha_start 240 +#define GEN9_RENDER_SURFACE_STATE_ShaderChannelSelectAlpha_start 240 +#define GEN8_RENDER_SURFACE_STATE_ShaderChannelSelectAlpha_start 240 +#define GEN75_RENDER_SURFACE_STATE_ShaderChannelSelectAlpha_start 240 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_ShaderChannelSelectAlpha_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 240; + case 10: return 240; + case 9: return 240; + case 8: return 240; + case 7: + if (devinfo->is_haswell) { + return 240; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Shader Channel Select Blue */ + + +#define GEN11_RENDER_SURFACE_STATE_ShaderChannelSelectBlue_bits 3 +#define GEN10_RENDER_SURFACE_STATE_ShaderChannelSelectBlue_bits 3 +#define GEN9_RENDER_SURFACE_STATE_ShaderChannelSelectBlue_bits 3 +#define GEN8_RENDER_SURFACE_STATE_ShaderChannelSelectBlue_bits 3 +#define GEN75_RENDER_SURFACE_STATE_ShaderChannelSelectBlue_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_ShaderChannelSelectBlue_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_ShaderChannelSelectBlue_start 243 +#define GEN10_RENDER_SURFACE_STATE_ShaderChannelSelectBlue_start 243 +#define GEN9_RENDER_SURFACE_STATE_ShaderChannelSelectBlue_start 243 +#define GEN8_RENDER_SURFACE_STATE_ShaderChannelSelectBlue_start 243 +#define GEN75_RENDER_SURFACE_STATE_ShaderChannelSelectBlue_start 243 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_ShaderChannelSelectBlue_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 243; + case 10: return 243; + case 9: return 243; + case 8: return 243; + case 7: + if (devinfo->is_haswell) { + return 243; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Shader Channel Select Green */ + + +#define GEN11_RENDER_SURFACE_STATE_ShaderChannelSelectGreen_bits 3 +#define GEN10_RENDER_SURFACE_STATE_ShaderChannelSelectGreen_bits 3 +#define GEN9_RENDER_SURFACE_STATE_ShaderChannelSelectGreen_bits 3 +#define GEN8_RENDER_SURFACE_STATE_ShaderChannelSelectGreen_bits 3 +#define GEN75_RENDER_SURFACE_STATE_ShaderChannelSelectGreen_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_ShaderChannelSelectGreen_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_ShaderChannelSelectGreen_start 246 +#define GEN10_RENDER_SURFACE_STATE_ShaderChannelSelectGreen_start 246 +#define GEN9_RENDER_SURFACE_STATE_ShaderChannelSelectGreen_start 246 +#define GEN8_RENDER_SURFACE_STATE_ShaderChannelSelectGreen_start 246 +#define GEN75_RENDER_SURFACE_STATE_ShaderChannelSelectGreen_start 246 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_ShaderChannelSelectGreen_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 246; + case 10: return 246; + case 9: return 246; + case 8: return 246; + case 7: + if (devinfo->is_haswell) { + return 246; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Shader Channel Select Red */ + + +#define GEN11_RENDER_SURFACE_STATE_ShaderChannelSelectRed_bits 3 +#define GEN10_RENDER_SURFACE_STATE_ShaderChannelSelectRed_bits 3 +#define GEN9_RENDER_SURFACE_STATE_ShaderChannelSelectRed_bits 3 +#define GEN8_RENDER_SURFACE_STATE_ShaderChannelSelectRed_bits 3 +#define GEN75_RENDER_SURFACE_STATE_ShaderChannelSelectRed_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_ShaderChannelSelectRed_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_ShaderChannelSelectRed_start 249 +#define GEN10_RENDER_SURFACE_STATE_ShaderChannelSelectRed_start 249 +#define GEN9_RENDER_SURFACE_STATE_ShaderChannelSelectRed_start 249 +#define GEN8_RENDER_SURFACE_STATE_ShaderChannelSelectRed_start 249 +#define GEN75_RENDER_SURFACE_STATE_ShaderChannelSelectRed_start 249 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_ShaderChannelSelectRed_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 249; + case 10: return 249; + case 9: return 249; + case 8: return 249; + case 7: + if (devinfo->is_haswell) { + return 249; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Strbuf Minimum Array Element */ + + +#define GEN75_RENDER_SURFACE_STATE_StrbufMinimumArrayElement_bits 27 +#define GEN7_RENDER_SURFACE_STATE_StrbufMinimumArrayElement_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_StrbufMinimumArrayElement_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_RENDER_SURFACE_STATE_StrbufMinimumArrayElement_start 128 +#define GEN7_RENDER_SURFACE_STATE_StrbufMinimumArrayElement_start 128 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_StrbufMinimumArrayElement_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 128; + } else { + return 128; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Surface Array */ + + +#define GEN11_RENDER_SURFACE_STATE_SurfaceArray_bits 1 +#define GEN10_RENDER_SURFACE_STATE_SurfaceArray_bits 1 +#define GEN9_RENDER_SURFACE_STATE_SurfaceArray_bits 1 +#define GEN8_RENDER_SURFACE_STATE_SurfaceArray_bits 1 +#define GEN75_RENDER_SURFACE_STATE_SurfaceArray_bits 1 +#define GEN7_RENDER_SURFACE_STATE_SurfaceArray_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_SurfaceArray_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_SurfaceArray_start 28 +#define GEN10_RENDER_SURFACE_STATE_SurfaceArray_start 28 +#define GEN9_RENDER_SURFACE_STATE_SurfaceArray_start 28 +#define GEN8_RENDER_SURFACE_STATE_SurfaceArray_start 28 +#define GEN75_RENDER_SURFACE_STATE_SurfaceArray_start 28 +#define GEN7_RENDER_SURFACE_STATE_SurfaceArray_start 28 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_SurfaceArray_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 28; + case 10: return 28; + case 9: return 28; + case 8: return 28; + case 7: + if (devinfo->is_haswell) { + return 28; + } else { + return 28; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Surface Array Spacing */ + + +#define GEN75_RENDER_SURFACE_STATE_SurfaceArraySpacing_bits 1 +#define GEN7_RENDER_SURFACE_STATE_SurfaceArraySpacing_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_SurfaceArraySpacing_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_RENDER_SURFACE_STATE_SurfaceArraySpacing_start 10 +#define GEN7_RENDER_SURFACE_STATE_SurfaceArraySpacing_start 10 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_SurfaceArraySpacing_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 10; + } else { + return 10; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Surface Base Address */ + + +#define GEN11_RENDER_SURFACE_STATE_SurfaceBaseAddress_bits 64 +#define GEN10_RENDER_SURFACE_STATE_SurfaceBaseAddress_bits 64 +#define GEN9_RENDER_SURFACE_STATE_SurfaceBaseAddress_bits 64 +#define GEN8_RENDER_SURFACE_STATE_SurfaceBaseAddress_bits 64 +#define GEN75_RENDER_SURFACE_STATE_SurfaceBaseAddress_bits 32 +#define GEN7_RENDER_SURFACE_STATE_SurfaceBaseAddress_bits 32 +#define GEN6_RENDER_SURFACE_STATE_SurfaceBaseAddress_bits 32 +#define GEN5_RENDER_SURFACE_STATE_SurfaceBaseAddress_bits 32 +#define GEN45_RENDER_SURFACE_STATE_SurfaceBaseAddress_bits 32 +#define GEN4_RENDER_SURFACE_STATE_SurfaceBaseAddress_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_SurfaceBaseAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_SurfaceBaseAddress_start 256 +#define GEN10_RENDER_SURFACE_STATE_SurfaceBaseAddress_start 256 +#define GEN9_RENDER_SURFACE_STATE_SurfaceBaseAddress_start 256 +#define GEN8_RENDER_SURFACE_STATE_SurfaceBaseAddress_start 256 +#define GEN75_RENDER_SURFACE_STATE_SurfaceBaseAddress_start 32 +#define GEN7_RENDER_SURFACE_STATE_SurfaceBaseAddress_start 32 +#define GEN6_RENDER_SURFACE_STATE_SurfaceBaseAddress_start 32 +#define GEN5_RENDER_SURFACE_STATE_SurfaceBaseAddress_start 32 +#define GEN45_RENDER_SURFACE_STATE_SurfaceBaseAddress_start 32 +#define GEN4_RENDER_SURFACE_STATE_SurfaceBaseAddress_start 32 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_SurfaceBaseAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 256; + case 10: return 256; + case 9: return 256; + case 8: return 256; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Surface Format */ + + +#define GEN11_RENDER_SURFACE_STATE_SurfaceFormat_bits 10 +#define GEN10_RENDER_SURFACE_STATE_SurfaceFormat_bits 10 +#define GEN9_RENDER_SURFACE_STATE_SurfaceFormat_bits 10 +#define GEN8_RENDER_SURFACE_STATE_SurfaceFormat_bits 9 +#define GEN75_RENDER_SURFACE_STATE_SurfaceFormat_bits 9 +#define GEN7_RENDER_SURFACE_STATE_SurfaceFormat_bits 9 +#define GEN6_RENDER_SURFACE_STATE_SurfaceFormat_bits 9 +#define GEN5_RENDER_SURFACE_STATE_SurfaceFormat_bits 9 +#define GEN45_RENDER_SURFACE_STATE_SurfaceFormat_bits 9 +#define GEN4_RENDER_SURFACE_STATE_SurfaceFormat_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_SurfaceFormat_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 10; + case 10: return 10; + case 9: return 10; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 9; + } + case 6: return 9; + case 5: return 9; + case 4: + if (devinfo->is_g4x) { + return 9; + } else { + return 9; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_SurfaceFormat_start 18 +#define GEN10_RENDER_SURFACE_STATE_SurfaceFormat_start 18 +#define GEN9_RENDER_SURFACE_STATE_SurfaceFormat_start 18 +#define GEN8_RENDER_SURFACE_STATE_SurfaceFormat_start 18 +#define GEN75_RENDER_SURFACE_STATE_SurfaceFormat_start 18 +#define GEN7_RENDER_SURFACE_STATE_SurfaceFormat_start 18 +#define GEN6_RENDER_SURFACE_STATE_SurfaceFormat_start 18 +#define GEN5_RENDER_SURFACE_STATE_SurfaceFormat_start 18 +#define GEN45_RENDER_SURFACE_STATE_SurfaceFormat_start 18 +#define GEN4_RENDER_SURFACE_STATE_SurfaceFormat_start 18 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_SurfaceFormat_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 18; + case 10: return 18; + case 9: return 18; + case 8: return 18; + case 7: + if (devinfo->is_haswell) { + return 18; + } else { + return 18; + } + case 6: return 18; + case 5: return 18; + case 4: + if (devinfo->is_g4x) { + return 18; + } else { + return 18; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Surface Horizontal Alignment */ + + +#define GEN11_RENDER_SURFACE_STATE_SurfaceHorizontalAlignment_bits 2 +#define GEN10_RENDER_SURFACE_STATE_SurfaceHorizontalAlignment_bits 2 +#define GEN9_RENDER_SURFACE_STATE_SurfaceHorizontalAlignment_bits 2 +#define GEN8_RENDER_SURFACE_STATE_SurfaceHorizontalAlignment_bits 2 +#define GEN75_RENDER_SURFACE_STATE_SurfaceHorizontalAlignment_bits 1 +#define GEN7_RENDER_SURFACE_STATE_SurfaceHorizontalAlignment_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_SurfaceHorizontalAlignment_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_SurfaceHorizontalAlignment_start 14 +#define GEN10_RENDER_SURFACE_STATE_SurfaceHorizontalAlignment_start 14 +#define GEN9_RENDER_SURFACE_STATE_SurfaceHorizontalAlignment_start 14 +#define GEN8_RENDER_SURFACE_STATE_SurfaceHorizontalAlignment_start 14 +#define GEN75_RENDER_SURFACE_STATE_SurfaceHorizontalAlignment_start 15 +#define GEN7_RENDER_SURFACE_STATE_SurfaceHorizontalAlignment_start 15 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_SurfaceHorizontalAlignment_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 14; + case 10: return 14; + case 9: return 14; + case 8: return 14; + case 7: + if (devinfo->is_haswell) { + return 15; + } else { + return 15; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Surface Min LOD */ + + +#define GEN11_RENDER_SURFACE_STATE_SurfaceMinLOD_bits 4 +#define GEN10_RENDER_SURFACE_STATE_SurfaceMinLOD_bits 4 +#define GEN9_RENDER_SURFACE_STATE_SurfaceMinLOD_bits 4 +#define GEN8_RENDER_SURFACE_STATE_SurfaceMinLOD_bits 4 +#define GEN75_RENDER_SURFACE_STATE_SurfaceMinLOD_bits 4 +#define GEN7_RENDER_SURFACE_STATE_SurfaceMinLOD_bits 4 +#define GEN6_RENDER_SURFACE_STATE_SurfaceMinLOD_bits 4 +#define GEN5_RENDER_SURFACE_STATE_SurfaceMinLOD_bits 4 +#define GEN45_RENDER_SURFACE_STATE_SurfaceMinLOD_bits 4 +#define GEN4_RENDER_SURFACE_STATE_SurfaceMinLOD_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_SurfaceMinLOD_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 4; + case 4: + if (devinfo->is_g4x) { + return 4; + } else { + return 4; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_SurfaceMinLOD_start 164 +#define GEN10_RENDER_SURFACE_STATE_SurfaceMinLOD_start 164 +#define GEN9_RENDER_SURFACE_STATE_SurfaceMinLOD_start 164 +#define GEN8_RENDER_SURFACE_STATE_SurfaceMinLOD_start 164 +#define GEN75_RENDER_SURFACE_STATE_SurfaceMinLOD_start 164 +#define GEN7_RENDER_SURFACE_STATE_SurfaceMinLOD_start 164 +#define GEN6_RENDER_SURFACE_STATE_SurfaceMinLOD_start 156 +#define GEN5_RENDER_SURFACE_STATE_SurfaceMinLOD_start 156 +#define GEN45_RENDER_SURFACE_STATE_SurfaceMinLOD_start 156 +#define GEN4_RENDER_SURFACE_STATE_SurfaceMinLOD_start 156 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_SurfaceMinLOD_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 164; + case 10: return 164; + case 9: return 164; + case 8: return 164; + case 7: + if (devinfo->is_haswell) { + return 164; + } else { + return 164; + } + case 6: return 156; + case 5: return 156; + case 4: + if (devinfo->is_g4x) { + return 156; + } else { + return 156; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Surface Pitch */ + + +#define GEN11_RENDER_SURFACE_STATE_SurfacePitch_bits 18 +#define GEN10_RENDER_SURFACE_STATE_SurfacePitch_bits 18 +#define GEN9_RENDER_SURFACE_STATE_SurfacePitch_bits 18 +#define GEN8_RENDER_SURFACE_STATE_SurfacePitch_bits 18 +#define GEN75_RENDER_SURFACE_STATE_SurfacePitch_bits 18 +#define GEN7_RENDER_SURFACE_STATE_SurfacePitch_bits 18 +#define GEN6_RENDER_SURFACE_STATE_SurfacePitch_bits 17 +#define GEN5_RENDER_SURFACE_STATE_SurfacePitch_bits 17 +#define GEN45_RENDER_SURFACE_STATE_SurfacePitch_bits 17 +#define GEN4_RENDER_SURFACE_STATE_SurfacePitch_bits 17 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_SurfacePitch_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 18; + case 10: return 18; + case 9: return 18; + case 8: return 18; + case 7: + if (devinfo->is_haswell) { + return 18; + } else { + return 18; + } + case 6: return 17; + case 5: return 17; + case 4: + if (devinfo->is_g4x) { + return 17; + } else { + return 17; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_SurfacePitch_start 96 +#define GEN10_RENDER_SURFACE_STATE_SurfacePitch_start 96 +#define GEN9_RENDER_SURFACE_STATE_SurfacePitch_start 96 +#define GEN8_RENDER_SURFACE_STATE_SurfacePitch_start 96 +#define GEN75_RENDER_SURFACE_STATE_SurfacePitch_start 96 +#define GEN7_RENDER_SURFACE_STATE_SurfacePitch_start 96 +#define GEN6_RENDER_SURFACE_STATE_SurfacePitch_start 99 +#define GEN5_RENDER_SURFACE_STATE_SurfacePitch_start 99 +#define GEN45_RENDER_SURFACE_STATE_SurfacePitch_start 99 +#define GEN4_RENDER_SURFACE_STATE_SurfacePitch_start 99 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_SurfacePitch_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 96; + case 10: return 96; + case 9: return 96; + case 8: return 96; + case 7: + if (devinfo->is_haswell) { + return 96; + } else { + return 96; + } + case 6: return 99; + case 5: return 99; + case 4: + if (devinfo->is_g4x) { + return 99; + } else { + return 99; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Surface QPitch */ + + +#define GEN11_RENDER_SURFACE_STATE_SurfaceQPitch_bits 15 +#define GEN10_RENDER_SURFACE_STATE_SurfaceQPitch_bits 15 +#define GEN9_RENDER_SURFACE_STATE_SurfaceQPitch_bits 15 +#define GEN8_RENDER_SURFACE_STATE_SurfaceQPitch_bits 15 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_SurfaceQPitch_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 15; + case 10: return 15; + case 9: return 15; + case 8: return 15; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_SurfaceQPitch_start 32 +#define GEN10_RENDER_SURFACE_STATE_SurfaceQPitch_start 32 +#define GEN9_RENDER_SURFACE_STATE_SurfaceQPitch_start 32 +#define GEN8_RENDER_SURFACE_STATE_SurfaceQPitch_start 32 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_SurfaceQPitch_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Surface Type */ + + +#define GEN11_RENDER_SURFACE_STATE_SurfaceType_bits 3 +#define GEN10_RENDER_SURFACE_STATE_SurfaceType_bits 3 +#define GEN9_RENDER_SURFACE_STATE_SurfaceType_bits 3 +#define GEN8_RENDER_SURFACE_STATE_SurfaceType_bits 3 +#define GEN75_RENDER_SURFACE_STATE_SurfaceType_bits 3 +#define GEN7_RENDER_SURFACE_STATE_SurfaceType_bits 3 +#define GEN6_RENDER_SURFACE_STATE_SurfaceType_bits 3 +#define GEN5_RENDER_SURFACE_STATE_SurfaceType_bits 3 +#define GEN45_RENDER_SURFACE_STATE_SurfaceType_bits 3 +#define GEN4_RENDER_SURFACE_STATE_SurfaceType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_SurfaceType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_SurfaceType_start 29 +#define GEN10_RENDER_SURFACE_STATE_SurfaceType_start 29 +#define GEN9_RENDER_SURFACE_STATE_SurfaceType_start 29 +#define GEN8_RENDER_SURFACE_STATE_SurfaceType_start 29 +#define GEN75_RENDER_SURFACE_STATE_SurfaceType_start 29 +#define GEN7_RENDER_SURFACE_STATE_SurfaceType_start 29 +#define GEN6_RENDER_SURFACE_STATE_SurfaceType_start 29 +#define GEN5_RENDER_SURFACE_STATE_SurfaceType_start 29 +#define GEN45_RENDER_SURFACE_STATE_SurfaceType_start 29 +#define GEN4_RENDER_SURFACE_STATE_SurfaceType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_SurfaceType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 29; + case 4: + if (devinfo->is_g4x) { + return 29; + } else { + return 29; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Surface Vertical Alignment */ + + +#define GEN11_RENDER_SURFACE_STATE_SurfaceVerticalAlignment_bits 2 +#define GEN10_RENDER_SURFACE_STATE_SurfaceVerticalAlignment_bits 2 +#define GEN9_RENDER_SURFACE_STATE_SurfaceVerticalAlignment_bits 2 +#define GEN8_RENDER_SURFACE_STATE_SurfaceVerticalAlignment_bits 2 +#define GEN75_RENDER_SURFACE_STATE_SurfaceVerticalAlignment_bits 2 +#define GEN7_RENDER_SURFACE_STATE_SurfaceVerticalAlignment_bits 2 +#define GEN6_RENDER_SURFACE_STATE_SurfaceVerticalAlignment_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_SurfaceVerticalAlignment_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_SurfaceVerticalAlignment_start 16 +#define GEN10_RENDER_SURFACE_STATE_SurfaceVerticalAlignment_start 16 +#define GEN9_RENDER_SURFACE_STATE_SurfaceVerticalAlignment_start 16 +#define GEN8_RENDER_SURFACE_STATE_SurfaceVerticalAlignment_start 16 +#define GEN75_RENDER_SURFACE_STATE_SurfaceVerticalAlignment_start 16 +#define GEN7_RENDER_SURFACE_STATE_SurfaceVerticalAlignment_start 16 +#define GEN6_RENDER_SURFACE_STATE_SurfaceVerticalAlignment_start 184 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_SurfaceVerticalAlignment_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 184; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Tile Address Mapping Mode */ + + +#define GEN11_RENDER_SURFACE_STATE_TileAddressMappingMode_bits 1 +#define GEN10_RENDER_SURFACE_STATE_TileAddressMappingMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_TileAddressMappingMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_TileAddressMappingMode_start 116 +#define GEN10_RENDER_SURFACE_STATE_TileAddressMappingMode_start 116 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_TileAddressMappingMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 116; + case 10: return 116; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Tile Mode */ + + +#define GEN11_RENDER_SURFACE_STATE_TileMode_bits 2 +#define GEN10_RENDER_SURFACE_STATE_TileMode_bits 2 +#define GEN9_RENDER_SURFACE_STATE_TileMode_bits 2 +#define GEN8_RENDER_SURFACE_STATE_TileMode_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_TileMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_TileMode_start 12 +#define GEN10_RENDER_SURFACE_STATE_TileMode_start 12 +#define GEN9_RENDER_SURFACE_STATE_TileMode_start 12 +#define GEN8_RENDER_SURFACE_STATE_TileMode_start 12 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_TileMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 12; + case 10: return 12; + case 9: return 12; + case 8: return 12; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Tile Walk */ + + +#define GEN75_RENDER_SURFACE_STATE_TileWalk_bits 1 +#define GEN7_RENDER_SURFACE_STATE_TileWalk_bits 1 +#define GEN6_RENDER_SURFACE_STATE_TileWalk_bits 1 +#define GEN5_RENDER_SURFACE_STATE_TileWalk_bits 1 +#define GEN45_RENDER_SURFACE_STATE_TileWalk_bits 1 +#define GEN4_RENDER_SURFACE_STATE_TileWalk_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_TileWalk_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_RENDER_SURFACE_STATE_TileWalk_start 13 +#define GEN7_RENDER_SURFACE_STATE_TileWalk_start 13 +#define GEN6_RENDER_SURFACE_STATE_TileWalk_start 96 +#define GEN5_RENDER_SURFACE_STATE_TileWalk_start 96 +#define GEN45_RENDER_SURFACE_STATE_TileWalk_start 96 +#define GEN4_RENDER_SURFACE_STATE_TileWalk_start 96 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_TileWalk_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 13; + } else { + return 13; + } + case 6: return 96; + case 5: return 96; + case 4: + if (devinfo->is_g4x) { + return 96; + } else { + return 96; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Tiled Resource Mode */ + + +#define GEN11_RENDER_SURFACE_STATE_TiledResourceMode_bits 2 +#define GEN10_RENDER_SURFACE_STATE_TiledResourceMode_bits 2 +#define GEN9_RENDER_SURFACE_STATE_TiledResourceMode_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_TiledResourceMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_TiledResourceMode_start 178 +#define GEN10_RENDER_SURFACE_STATE_TiledResourceMode_start 178 +#define GEN9_RENDER_SURFACE_STATE_TiledResourceMode_start 178 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_TiledResourceMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 178; + case 10: return 178; + case 9: return 178; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Tiled Surface */ + + +#define GEN75_RENDER_SURFACE_STATE_TiledSurface_bits 1 +#define GEN7_RENDER_SURFACE_STATE_TiledSurface_bits 1 +#define GEN6_RENDER_SURFACE_STATE_TiledSurface_bits 1 +#define GEN5_RENDER_SURFACE_STATE_TiledSurface_bits 1 +#define GEN45_RENDER_SURFACE_STATE_TiledSurface_bits 1 +#define GEN4_RENDER_SURFACE_STATE_TiledSurface_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_TiledSurface_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_RENDER_SURFACE_STATE_TiledSurface_start 14 +#define GEN7_RENDER_SURFACE_STATE_TiledSurface_start 14 +#define GEN6_RENDER_SURFACE_STATE_TiledSurface_start 97 +#define GEN5_RENDER_SURFACE_STATE_TiledSurface_start 97 +#define GEN45_RENDER_SURFACE_STATE_TiledSurface_start 97 +#define GEN4_RENDER_SURFACE_STATE_TiledSurface_start 97 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_TiledSurface_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 14; + } else { + return 14; + } + case 6: return 97; + case 5: return 97; + case 4: + if (devinfo->is_g4x) { + return 97; + } else { + return 97; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Vertical Line Stride */ + + +#define GEN11_RENDER_SURFACE_STATE_VerticalLineStride_bits 1 +#define GEN10_RENDER_SURFACE_STATE_VerticalLineStride_bits 1 +#define GEN9_RENDER_SURFACE_STATE_VerticalLineStride_bits 1 +#define GEN8_RENDER_SURFACE_STATE_VerticalLineStride_bits 1 +#define GEN75_RENDER_SURFACE_STATE_VerticalLineStride_bits 1 +#define GEN7_RENDER_SURFACE_STATE_VerticalLineStride_bits 1 +#define GEN6_RENDER_SURFACE_STATE_VerticalLineStride_bits 1 +#define GEN5_RENDER_SURFACE_STATE_VerticalLineStride_bits 1 +#define GEN45_RENDER_SURFACE_STATE_VerticalLineStride_bits 1 +#define GEN4_RENDER_SURFACE_STATE_VerticalLineStride_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_VerticalLineStride_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_VerticalLineStride_start 11 +#define GEN10_RENDER_SURFACE_STATE_VerticalLineStride_start 11 +#define GEN9_RENDER_SURFACE_STATE_VerticalLineStride_start 11 +#define GEN8_RENDER_SURFACE_STATE_VerticalLineStride_start 11 +#define GEN75_RENDER_SURFACE_STATE_VerticalLineStride_start 12 +#define GEN7_RENDER_SURFACE_STATE_VerticalLineStride_start 12 +#define GEN6_RENDER_SURFACE_STATE_VerticalLineStride_start 12 +#define GEN5_RENDER_SURFACE_STATE_VerticalLineStride_start 12 +#define GEN45_RENDER_SURFACE_STATE_VerticalLineStride_start 12 +#define GEN4_RENDER_SURFACE_STATE_VerticalLineStride_start 12 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_VerticalLineStride_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 12; + } else { + return 12; + } + case 6: return 12; + case 5: return 12; + case 4: + if (devinfo->is_g4x) { + return 12; + } else { + return 12; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Vertical Line Stride Offset */ + + +#define GEN11_RENDER_SURFACE_STATE_VerticalLineStrideOffset_bits 1 +#define GEN10_RENDER_SURFACE_STATE_VerticalLineStrideOffset_bits 1 +#define GEN9_RENDER_SURFACE_STATE_VerticalLineStrideOffset_bits 1 +#define GEN8_RENDER_SURFACE_STATE_VerticalLineStrideOffset_bits 1 +#define GEN75_RENDER_SURFACE_STATE_VerticalLineStrideOffset_bits 1 +#define GEN7_RENDER_SURFACE_STATE_VerticalLineStrideOffset_bits 1 +#define GEN6_RENDER_SURFACE_STATE_VerticalLineStrideOffset_bits 1 +#define GEN5_RENDER_SURFACE_STATE_VerticalLineStrideOffset_bits 1 +#define GEN45_RENDER_SURFACE_STATE_VerticalLineStrideOffset_bits 1 +#define GEN4_RENDER_SURFACE_STATE_VerticalLineStrideOffset_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_VerticalLineStrideOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_VerticalLineStrideOffset_start 10 +#define GEN10_RENDER_SURFACE_STATE_VerticalLineStrideOffset_start 10 +#define GEN9_RENDER_SURFACE_STATE_VerticalLineStrideOffset_start 10 +#define GEN8_RENDER_SURFACE_STATE_VerticalLineStrideOffset_start 10 +#define GEN75_RENDER_SURFACE_STATE_VerticalLineStrideOffset_start 11 +#define GEN7_RENDER_SURFACE_STATE_VerticalLineStrideOffset_start 11 +#define GEN6_RENDER_SURFACE_STATE_VerticalLineStrideOffset_start 11 +#define GEN5_RENDER_SURFACE_STATE_VerticalLineStrideOffset_start 11 +#define GEN45_RENDER_SURFACE_STATE_VerticalLineStrideOffset_start 11 +#define GEN4_RENDER_SURFACE_STATE_VerticalLineStrideOffset_start 11 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_VerticalLineStrideOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 10; + case 10: return 10; + case 9: return 10; + case 8: return 10; + case 7: + if (devinfo->is_haswell) { + return 11; + } else { + return 11; + } + case 6: return 11; + case 5: return 11; + case 4: + if (devinfo->is_g4x) { + return 11; + } else { + return 11; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Width */ + + +#define GEN11_RENDER_SURFACE_STATE_Width_bits 14 +#define GEN10_RENDER_SURFACE_STATE_Width_bits 14 +#define GEN9_RENDER_SURFACE_STATE_Width_bits 14 +#define GEN8_RENDER_SURFACE_STATE_Width_bits 14 +#define GEN75_RENDER_SURFACE_STATE_Width_bits 14 +#define GEN7_RENDER_SURFACE_STATE_Width_bits 14 +#define GEN6_RENDER_SURFACE_STATE_Width_bits 13 +#define GEN5_RENDER_SURFACE_STATE_Width_bits 13 +#define GEN45_RENDER_SURFACE_STATE_Width_bits 13 +#define GEN4_RENDER_SURFACE_STATE_Width_bits 13 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_Width_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 14; + case 10: return 14; + case 9: return 14; + case 8: return 14; + case 7: + if (devinfo->is_haswell) { + return 14; + } else { + return 14; + } + case 6: return 13; + case 5: return 13; + case 4: + if (devinfo->is_g4x) { + return 13; + } else { + return 13; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_Width_start 64 +#define GEN10_RENDER_SURFACE_STATE_Width_start 64 +#define GEN9_RENDER_SURFACE_STATE_Width_start 64 +#define GEN8_RENDER_SURFACE_STATE_Width_start 64 +#define GEN75_RENDER_SURFACE_STATE_Width_start 64 +#define GEN7_RENDER_SURFACE_STATE_Width_start 64 +#define GEN6_RENDER_SURFACE_STATE_Width_start 70 +#define GEN5_RENDER_SURFACE_STATE_Width_start 70 +#define GEN45_RENDER_SURFACE_STATE_Width_start 70 +#define GEN4_RENDER_SURFACE_STATE_Width_start 70 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_Width_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 70; + case 5: return 70; + case 4: + if (devinfo->is_g4x) { + return 70; + } else { + return 70; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::X Offset */ + + +#define GEN11_RENDER_SURFACE_STATE_XOffset_bits 7 +#define GEN10_RENDER_SURFACE_STATE_XOffset_bits 7 +#define GEN9_RENDER_SURFACE_STATE_XOffset_bits 7 +#define GEN8_RENDER_SURFACE_STATE_XOffset_bits 7 +#define GEN75_RENDER_SURFACE_STATE_XOffset_bits 7 +#define GEN7_RENDER_SURFACE_STATE_XOffset_bits 7 +#define GEN6_RENDER_SURFACE_STATE_XOffset_bits 7 +#define GEN5_RENDER_SURFACE_STATE_XOffset_bits 7 +#define GEN45_RENDER_SURFACE_STATE_XOffset_bits 7 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_XOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 7; + } else { + return 7; + } + case 6: return 7; + case 5: return 7; + case 4: + if (devinfo->is_g4x) { + return 7; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_XOffset_start 185 +#define GEN10_RENDER_SURFACE_STATE_XOffset_start 185 +#define GEN9_RENDER_SURFACE_STATE_XOffset_start 185 +#define GEN8_RENDER_SURFACE_STATE_XOffset_start 185 +#define GEN75_RENDER_SURFACE_STATE_XOffset_start 185 +#define GEN7_RENDER_SURFACE_STATE_XOffset_start 185 +#define GEN6_RENDER_SURFACE_STATE_XOffset_start 185 +#define GEN5_RENDER_SURFACE_STATE_XOffset_start 185 +#define GEN45_RENDER_SURFACE_STATE_XOffset_start 185 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_XOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 185; + case 10: return 185; + case 9: return 185; + case 8: return 185; + case 7: + if (devinfo->is_haswell) { + return 185; + } else { + return 185; + } + case 6: return 185; + case 5: return 185; + case 4: + if (devinfo->is_g4x) { + return 185; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::X Offset for U or UV Plane */ + + +#define GEN11_RENDER_SURFACE_STATE_XOffsetforUorUVPlane_bits 14 +#define GEN10_RENDER_SURFACE_STATE_XOffsetforUorUVPlane_bits 14 +#define GEN9_RENDER_SURFACE_STATE_XOffsetforUorUVPlane_bits 14 +#define GEN8_RENDER_SURFACE_STATE_XOffsetforUorUVPlane_bits 14 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_XOffsetforUorUVPlane_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 14; + case 10: return 14; + case 9: return 14; + case 8: return 14; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_XOffsetforUorUVPlane_start 208 +#define GEN10_RENDER_SURFACE_STATE_XOffsetforUorUVPlane_start 208 +#define GEN9_RENDER_SURFACE_STATE_XOffsetforUorUVPlane_start 208 +#define GEN8_RENDER_SURFACE_STATE_XOffsetforUorUVPlane_start 208 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_XOffsetforUorUVPlane_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 208; + case 10: return 208; + case 9: return 208; + case 8: return 208; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::X Offset for UV Plane */ + + +#define GEN75_RENDER_SURFACE_STATE_XOffsetforUVPlane_bits 14 +#define GEN7_RENDER_SURFACE_STATE_XOffsetforUVPlane_bits 14 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_XOffsetforUVPlane_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 14; + } else { + return 14; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_RENDER_SURFACE_STATE_XOffsetforUVPlane_start 208 +#define GEN7_RENDER_SURFACE_STATE_XOffsetforUVPlane_start 208 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_XOffsetforUVPlane_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 208; + } else { + return 208; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::X Offset for V Plane */ + + +#define GEN11_RENDER_SURFACE_STATE_XOffsetforVPlane_bits 14 +#define GEN10_RENDER_SURFACE_STATE_XOffsetforVPlane_bits 14 +#define GEN9_RENDER_SURFACE_STATE_XOffsetforVPlane_bits 14 +#define GEN8_RENDER_SURFACE_STATE_XOffsetforVPlane_bits 14 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_XOffsetforVPlane_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 14; + case 10: return 14; + case 9: return 14; + case 8: return 14; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_XOffsetforVPlane_start 368 +#define GEN10_RENDER_SURFACE_STATE_XOffsetforVPlane_start 368 +#define GEN9_RENDER_SURFACE_STATE_XOffsetforVPlane_start 368 +#define GEN8_RENDER_SURFACE_STATE_XOffsetforVPlane_start 368 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_XOffsetforVPlane_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 368; + case 10: return 368; + case 9: return 368; + case 8: return 368; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Y Offset */ + + +#define GEN11_RENDER_SURFACE_STATE_YOffset_bits 3 +#define GEN10_RENDER_SURFACE_STATE_YOffset_bits 3 +#define GEN9_RENDER_SURFACE_STATE_YOffset_bits 3 +#define GEN8_RENDER_SURFACE_STATE_YOffset_bits 3 +#define GEN75_RENDER_SURFACE_STATE_YOffset_bits 4 +#define GEN7_RENDER_SURFACE_STATE_YOffset_bits 4 +#define GEN6_RENDER_SURFACE_STATE_YOffset_bits 4 +#define GEN5_RENDER_SURFACE_STATE_YOffset_bits 4 +#define GEN45_RENDER_SURFACE_STATE_YOffset_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_YOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 4; + case 4: + if (devinfo->is_g4x) { + return 4; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_YOffset_start 181 +#define GEN10_RENDER_SURFACE_STATE_YOffset_start 181 +#define GEN9_RENDER_SURFACE_STATE_YOffset_start 181 +#define GEN8_RENDER_SURFACE_STATE_YOffset_start 181 +#define GEN75_RENDER_SURFACE_STATE_YOffset_start 180 +#define GEN7_RENDER_SURFACE_STATE_YOffset_start 180 +#define GEN6_RENDER_SURFACE_STATE_YOffset_start 180 +#define GEN5_RENDER_SURFACE_STATE_YOffset_start 180 +#define GEN45_RENDER_SURFACE_STATE_YOffset_start 180 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_YOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 181; + case 10: return 181; + case 9: return 181; + case 8: return 181; + case 7: + if (devinfo->is_haswell) { + return 180; + } else { + return 180; + } + case 6: return 180; + case 5: return 180; + case 4: + if (devinfo->is_g4x) { + return 180; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Y Offset for U or UV Plane */ + + +#define GEN11_RENDER_SURFACE_STATE_YOffsetforUorUVPlane_bits 14 +#define GEN10_RENDER_SURFACE_STATE_YOffsetforUorUVPlane_bits 14 +#define GEN9_RENDER_SURFACE_STATE_YOffsetforUorUVPlane_bits 14 +#define GEN8_RENDER_SURFACE_STATE_YOffsetforUorUVPlane_bits 14 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_YOffsetforUorUVPlane_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 14; + case 10: return 14; + case 9: return 14; + case 8: return 14; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_YOffsetforUorUVPlane_start 192 +#define GEN10_RENDER_SURFACE_STATE_YOffsetforUorUVPlane_start 192 +#define GEN9_RENDER_SURFACE_STATE_YOffsetforUorUVPlane_start 192 +#define GEN8_RENDER_SURFACE_STATE_YOffsetforUorUVPlane_start 192 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_YOffsetforUorUVPlane_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 192; + case 10: return 192; + case 9: return 192; + case 8: return 192; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Y Offset for UV Plane */ + + +#define GEN75_RENDER_SURFACE_STATE_YOffsetforUVPlane_bits 14 +#define GEN7_RENDER_SURFACE_STATE_YOffsetforUVPlane_bits 14 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_YOffsetforUVPlane_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 14; + } else { + return 14; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_RENDER_SURFACE_STATE_YOffsetforUVPlane_start 192 +#define GEN7_RENDER_SURFACE_STATE_YOffsetforUVPlane_start 192 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_YOffsetforUVPlane_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 192; + } else { + return 192; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* RENDER_SURFACE_STATE::Y Offset for V Plane */ + + +#define GEN11_RENDER_SURFACE_STATE_YOffsetforVPlane_bits 14 +#define GEN10_RENDER_SURFACE_STATE_YOffsetforVPlane_bits 14 +#define GEN9_RENDER_SURFACE_STATE_YOffsetforVPlane_bits 14 +#define GEN8_RENDER_SURFACE_STATE_YOffsetforVPlane_bits 14 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_YOffsetforVPlane_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 14; + case 10: return 14; + case 9: return 14; + case 8: return 14; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_RENDER_SURFACE_STATE_YOffsetforVPlane_start 352 +#define GEN10_RENDER_SURFACE_STATE_YOffsetforVPlane_start 352 +#define GEN9_RENDER_SURFACE_STATE_YOffsetforVPlane_start 352 +#define GEN8_RENDER_SURFACE_STATE_YOffsetforVPlane_start 352 + +static inline uint32_t ATTRIBUTE_PURE +RENDER_SURFACE_STATE_YOffsetforVPlane_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 352; + case 10: return 352; + case 9: return 352; + case 8: return 352; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* ROUNDINGPRECISIONTABLE_3_BITS */ + + +#define GEN11_ROUNDINGPRECISIONTABLE_3_BITS_length 1 +#define GEN10_ROUNDINGPRECISIONTABLE_3_BITS_length 1 +#define GEN9_ROUNDINGPRECISIONTABLE_3_BITS_length 1 + +static inline uint32_t ATTRIBUTE_PURE +ROUNDINGPRECISIONTABLE_3_BITS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* ROUNDINGPRECISIONTABLE_3_BITS::Rounding Precision */ + + +#define GEN11_ROUNDINGPRECISIONTABLE_3_BITS_RoundingPrecision_bits 3 +#define GEN10_ROUNDINGPRECISIONTABLE_3_BITS_RoundingPrecision_bits 3 +#define GEN9_ROUNDINGPRECISIONTABLE_3_BITS_RoundingPrecision_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +ROUNDINGPRECISIONTABLE_3_BITS_RoundingPrecision_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_ROUNDINGPRECISIONTABLE_3_BITS_RoundingPrecision_start 0 +#define GEN10_ROUNDINGPRECISIONTABLE_3_BITS_RoundingPrecision_start 0 +#define GEN9_ROUNDINGPRECISIONTABLE_3_BITS_RoundingPrecision_start 0 + +static inline uint32_t ATTRIBUTE_PURE +ROUNDINGPRECISIONTABLE_3_BITS_RoundingPrecision_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* ROW_INSTDONE */ + + +#define GEN11_ROW_INSTDONE_length 1 +#define GEN10_ROW_INSTDONE_length 1 +#define GEN9_ROW_INSTDONE_length 1 +#define GEN8_ROW_INSTDONE_length 1 +#define GEN75_ROW_INSTDONE_length 1 +#define GEN7_ROW_INSTDONE_length 1 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* ROW_INSTDONE::BC Done */ + + +#define GEN11_ROW_INSTDONE_BCDone_bits 1 +#define GEN10_ROW_INSTDONE_BCDone_bits 1 +#define GEN9_ROW_INSTDONE_BCDone_bits 1 +#define GEN8_ROW_INSTDONE_BCDone_bits 1 +#define GEN75_ROW_INSTDONE_BCDone_bits 1 +#define GEN7_ROW_INSTDONE_BCDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_BCDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_ROW_INSTDONE_BCDone_start 0 +#define GEN10_ROW_INSTDONE_BCDone_start 0 +#define GEN9_ROW_INSTDONE_BCDone_start 0 +#define GEN8_ROW_INSTDONE_BCDone_start 0 +#define GEN75_ROW_INSTDONE_BCDone_start 0 +#define GEN7_ROW_INSTDONE_BCDone_start 0 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_BCDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* ROW_INSTDONE::DAPR Done */ + + +#define GEN11_ROW_INSTDONE_DAPRDone_bits 1 +#define GEN10_ROW_INSTDONE_DAPRDone_bits 1 +#define GEN9_ROW_INSTDONE_DAPRDone_bits 1 +#define GEN8_ROW_INSTDONE_DAPRDone_bits 1 +#define GEN75_ROW_INSTDONE_DAPRDone_bits 1 +#define GEN7_ROW_INSTDONE_DAPRDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_DAPRDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_ROW_INSTDONE_DAPRDone_start 3 +#define GEN10_ROW_INSTDONE_DAPRDone_start 3 +#define GEN9_ROW_INSTDONE_DAPRDone_start 3 +#define GEN8_ROW_INSTDONE_DAPRDone_start 3 +#define GEN75_ROW_INSTDONE_DAPRDone_start 3 +#define GEN7_ROW_INSTDONE_DAPRDone_start 3 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_DAPRDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* ROW_INSTDONE::DC Done */ + + +#define GEN75_ROW_INSTDONE_DCDone_bits 1 +#define GEN7_ROW_INSTDONE_DCDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_DCDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_ROW_INSTDONE_DCDone_start 2 +#define GEN7_ROW_INSTDONE_DCDone_start 2 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_DCDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* ROW_INSTDONE::EU00 Done SS0 */ + + +#define GEN11_ROW_INSTDONE_EU00DoneSS0_bits 1 +#define GEN10_ROW_INSTDONE_EU00DoneSS0_bits 1 +#define GEN9_ROW_INSTDONE_EU00DoneSS0_bits 1 +#define GEN8_ROW_INSTDONE_EU00DoneSS0_bits 1 +#define GEN75_ROW_INSTDONE_EU00DoneSS0_bits 1 +#define GEN7_ROW_INSTDONE_EU00DoneSS0_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_EU00DoneSS0_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_ROW_INSTDONE_EU00DoneSS0_start 16 +#define GEN10_ROW_INSTDONE_EU00DoneSS0_start 16 +#define GEN9_ROW_INSTDONE_EU00DoneSS0_start 16 +#define GEN8_ROW_INSTDONE_EU00DoneSS0_start 16 +#define GEN75_ROW_INSTDONE_EU00DoneSS0_start 16 +#define GEN7_ROW_INSTDONE_EU00DoneSS0_start 16 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_EU00DoneSS0_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* ROW_INSTDONE::EU01 Done SS0 */ + + +#define GEN11_ROW_INSTDONE_EU01DoneSS0_bits 1 +#define GEN10_ROW_INSTDONE_EU01DoneSS0_bits 1 +#define GEN9_ROW_INSTDONE_EU01DoneSS0_bits 1 +#define GEN8_ROW_INSTDONE_EU01DoneSS0_bits 1 +#define GEN75_ROW_INSTDONE_EU01DoneSS0_bits 1 +#define GEN7_ROW_INSTDONE_EU01DoneSS0_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_EU01DoneSS0_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_ROW_INSTDONE_EU01DoneSS0_start 17 +#define GEN10_ROW_INSTDONE_EU01DoneSS0_start 17 +#define GEN9_ROW_INSTDONE_EU01DoneSS0_start 17 +#define GEN8_ROW_INSTDONE_EU01DoneSS0_start 17 +#define GEN75_ROW_INSTDONE_EU01DoneSS0_start 17 +#define GEN7_ROW_INSTDONE_EU01DoneSS0_start 17 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_EU01DoneSS0_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 17; + case 10: return 17; + case 9: return 17; + case 8: return 17; + case 7: + if (devinfo->is_haswell) { + return 17; + } else { + return 17; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* ROW_INSTDONE::EU02 Done SS0 */ + + +#define GEN11_ROW_INSTDONE_EU02DoneSS0_bits 1 +#define GEN10_ROW_INSTDONE_EU02DoneSS0_bits 1 +#define GEN9_ROW_INSTDONE_EU02DoneSS0_bits 1 +#define GEN8_ROW_INSTDONE_EU02DoneSS0_bits 1 +#define GEN75_ROW_INSTDONE_EU02DoneSS0_bits 1 +#define GEN7_ROW_INSTDONE_EU02DoneSS0_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_EU02DoneSS0_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_ROW_INSTDONE_EU02DoneSS0_start 18 +#define GEN10_ROW_INSTDONE_EU02DoneSS0_start 18 +#define GEN9_ROW_INSTDONE_EU02DoneSS0_start 18 +#define GEN8_ROW_INSTDONE_EU02DoneSS0_start 18 +#define GEN75_ROW_INSTDONE_EU02DoneSS0_start 18 +#define GEN7_ROW_INSTDONE_EU02DoneSS0_start 18 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_EU02DoneSS0_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 18; + case 10: return 18; + case 9: return 18; + case 8: return 18; + case 7: + if (devinfo->is_haswell) { + return 18; + } else { + return 18; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* ROW_INSTDONE::EU03 Done SS0 */ + + +#define GEN11_ROW_INSTDONE_EU03DoneSS0_bits 1 +#define GEN10_ROW_INSTDONE_EU03DoneSS0_bits 1 +#define GEN9_ROW_INSTDONE_EU03DoneSS0_bits 1 +#define GEN8_ROW_INSTDONE_EU03DoneSS0_bits 1 +#define GEN75_ROW_INSTDONE_EU03DoneSS0_bits 1 +#define GEN7_ROW_INSTDONE_EU03DoneSS0_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_EU03DoneSS0_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_ROW_INSTDONE_EU03DoneSS0_start 19 +#define GEN10_ROW_INSTDONE_EU03DoneSS0_start 19 +#define GEN9_ROW_INSTDONE_EU03DoneSS0_start 19 +#define GEN8_ROW_INSTDONE_EU03DoneSS0_start 19 +#define GEN75_ROW_INSTDONE_EU03DoneSS0_start 19 +#define GEN7_ROW_INSTDONE_EU03DoneSS0_start 19 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_EU03DoneSS0_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 19; + case 10: return 19; + case 9: return 19; + case 8: return 19; + case 7: + if (devinfo->is_haswell) { + return 19; + } else { + return 19; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* ROW_INSTDONE::EU04 Done SS0 */ + + +#define GEN75_ROW_INSTDONE_EU04DoneSS0_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_EU04DoneSS0_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_ROW_INSTDONE_EU04DoneSS0_start 20 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_EU04DoneSS0_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 20; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* ROW_INSTDONE::EU10 Done SS0 */ + + +#define GEN11_ROW_INSTDONE_EU10DoneSS0_bits 1 +#define GEN10_ROW_INSTDONE_EU10DoneSS0_bits 1 +#define GEN9_ROW_INSTDONE_EU10DoneSS0_bits 1 +#define GEN8_ROW_INSTDONE_EU10DoneSS0_bits 1 +#define GEN75_ROW_INSTDONE_EU10DoneSS0_bits 1 +#define GEN7_ROW_INSTDONE_EU10DoneSS0_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_EU10DoneSS0_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_ROW_INSTDONE_EU10DoneSS0_start 21 +#define GEN10_ROW_INSTDONE_EU10DoneSS0_start 21 +#define GEN9_ROW_INSTDONE_EU10DoneSS0_start 21 +#define GEN8_ROW_INSTDONE_EU10DoneSS0_start 21 +#define GEN75_ROW_INSTDONE_EU10DoneSS0_start 21 +#define GEN7_ROW_INSTDONE_EU10DoneSS0_start 21 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_EU10DoneSS0_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 21; + case 10: return 21; + case 9: return 21; + case 8: return 21; + case 7: + if (devinfo->is_haswell) { + return 21; + } else { + return 21; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* ROW_INSTDONE::EU11 Done SS0 */ + + +#define GEN11_ROW_INSTDONE_EU11DoneSS0_bits 1 +#define GEN10_ROW_INSTDONE_EU11DoneSS0_bits 1 +#define GEN9_ROW_INSTDONE_EU11DoneSS0_bits 1 +#define GEN8_ROW_INSTDONE_EU11DoneSS0_bits 1 +#define GEN75_ROW_INSTDONE_EU11DoneSS0_bits 1 +#define GEN7_ROW_INSTDONE_EU11DoneSS0_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_EU11DoneSS0_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_ROW_INSTDONE_EU11DoneSS0_start 22 +#define GEN10_ROW_INSTDONE_EU11DoneSS0_start 22 +#define GEN9_ROW_INSTDONE_EU11DoneSS0_start 22 +#define GEN8_ROW_INSTDONE_EU11DoneSS0_start 22 +#define GEN75_ROW_INSTDONE_EU11DoneSS0_start 22 +#define GEN7_ROW_INSTDONE_EU11DoneSS0_start 22 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_EU11DoneSS0_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 22; + case 10: return 22; + case 9: return 22; + case 8: return 22; + case 7: + if (devinfo->is_haswell) { + return 22; + } else { + return 22; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* ROW_INSTDONE::EU12 Done SS0 */ + + +#define GEN11_ROW_INSTDONE_EU12DoneSS0_bits 1 +#define GEN10_ROW_INSTDONE_EU12DoneSS0_bits 1 +#define GEN9_ROW_INSTDONE_EU12DoneSS0_bits 1 +#define GEN8_ROW_INSTDONE_EU12DoneSS0_bits 1 +#define GEN75_ROW_INSTDONE_EU12DoneSS0_bits 1 +#define GEN7_ROW_INSTDONE_EU12DoneSS0_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_EU12DoneSS0_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_ROW_INSTDONE_EU12DoneSS0_start 23 +#define GEN10_ROW_INSTDONE_EU12DoneSS0_start 23 +#define GEN9_ROW_INSTDONE_EU12DoneSS0_start 23 +#define GEN8_ROW_INSTDONE_EU12DoneSS0_start 23 +#define GEN75_ROW_INSTDONE_EU12DoneSS0_start 23 +#define GEN7_ROW_INSTDONE_EU12DoneSS0_start 23 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_EU12DoneSS0_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 23; + } else { + return 23; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* ROW_INSTDONE::EU13 Done SS0 */ + + +#define GEN11_ROW_INSTDONE_EU13DoneSS0_bits 1 +#define GEN10_ROW_INSTDONE_EU13DoneSS0_bits 1 +#define GEN9_ROW_INSTDONE_EU13DoneSS0_bits 1 +#define GEN8_ROW_INSTDONE_EU13DoneSS0_bits 1 +#define GEN75_ROW_INSTDONE_EU13DoneSS0_bits 1 +#define GEN7_ROW_INSTDONE_EU13DoneSS0_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_EU13DoneSS0_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_ROW_INSTDONE_EU13DoneSS0_start 24 +#define GEN10_ROW_INSTDONE_EU13DoneSS0_start 24 +#define GEN9_ROW_INSTDONE_EU13DoneSS0_start 24 +#define GEN8_ROW_INSTDONE_EU13DoneSS0_start 24 +#define GEN75_ROW_INSTDONE_EU13DoneSS0_start 24 +#define GEN7_ROW_INSTDONE_EU13DoneSS0_start 24 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_EU13DoneSS0_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* ROW_INSTDONE::EU14 Done SS0 */ + + +#define GEN75_ROW_INSTDONE_EU14DoneSS0_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_EU14DoneSS0_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_ROW_INSTDONE_EU14DoneSS0_start 25 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_EU14DoneSS0_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 25; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* ROW_INSTDONE::GW Done */ + + +#define GEN75_ROW_INSTDONE_GWDone_bits 1 +#define GEN7_ROW_INSTDONE_GWDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_GWDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_ROW_INSTDONE_GWDone_start 8 +#define GEN7_ROW_INSTDONE_GWDone_start 8 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_GWDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* ROW_INSTDONE::IC Done */ + + +#define GEN11_ROW_INSTDONE_ICDone_bits 1 +#define GEN10_ROW_INSTDONE_ICDone_bits 1 +#define GEN9_ROW_INSTDONE_ICDone_bits 1 +#define GEN8_ROW_INSTDONE_ICDone_bits 1 +#define GEN75_ROW_INSTDONE_ICDone_bits 1 +#define GEN7_ROW_INSTDONE_ICDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_ICDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_ROW_INSTDONE_ICDone_start 12 +#define GEN10_ROW_INSTDONE_ICDone_start 12 +#define GEN9_ROW_INSTDONE_ICDone_start 12 +#define GEN8_ROW_INSTDONE_ICDone_start 12 +#define GEN75_ROW_INSTDONE_ICDone_start 12 +#define GEN7_ROW_INSTDONE_ICDone_start 12 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_ICDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 12; + case 10: return 12; + case 9: return 12; + case 8: return 12; + case 7: + if (devinfo->is_haswell) { + return 12; + } else { + return 12; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* ROW_INSTDONE::MA0 Done */ + + +#define GEN11_ROW_INSTDONE_MA0Done_bits 1 +#define GEN10_ROW_INSTDONE_MA0Done_bits 1 +#define GEN9_ROW_INSTDONE_MA0Done_bits 1 +#define GEN8_ROW_INSTDONE_MA0Done_bits 1 +#define GEN75_ROW_INSTDONE_MA0Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_MA0Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_ROW_INSTDONE_MA0Done_start 15 +#define GEN10_ROW_INSTDONE_MA0Done_start 15 +#define GEN9_ROW_INSTDONE_MA0Done_start 15 +#define GEN8_ROW_INSTDONE_MA0Done_start 15 +#define GEN75_ROW_INSTDONE_MA0Done_start 15 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_MA0Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 15; + case 10: return 15; + case 9: return 15; + case 8: return 15; + case 7: + if (devinfo->is_haswell) { + return 15; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* ROW_INSTDONE::MA0 Done SS0 */ + + +#define GEN7_ROW_INSTDONE_MA0DoneSS0_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_MA0DoneSS0_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN7_ROW_INSTDONE_MA0DoneSS0_start 20 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_MA0DoneSS0_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 20; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* ROW_INSTDONE::MA1 Done */ + + +#define GEN7_ROW_INSTDONE_MA1Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_MA1Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN7_ROW_INSTDONE_MA1Done_start 25 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_MA1Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 25; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* ROW_INSTDONE::MA1 Done SS0 */ + + +#define GEN11_ROW_INSTDONE_MA1DoneSS0_bits 1 +#define GEN10_ROW_INSTDONE_MA1DoneSS0_bits 1 +#define GEN9_ROW_INSTDONE_MA1DoneSS0_bits 1 +#define GEN8_ROW_INSTDONE_MA1DoneSS0_bits 1 +#define GEN75_ROW_INSTDONE_MA1DoneSS0_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_MA1DoneSS0_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_ROW_INSTDONE_MA1DoneSS0_start 26 +#define GEN10_ROW_INSTDONE_MA1DoneSS0_start 26 +#define GEN9_ROW_INSTDONE_MA1DoneSS0_start 26 +#define GEN8_ROW_INSTDONE_MA1DoneSS0_start 26 +#define GEN75_ROW_INSTDONE_MA1DoneSS0_start 26 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_MA1DoneSS0_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 26; + case 10: return 26; + case 9: return 26; + case 8: return 26; + case 7: + if (devinfo->is_haswell) { + return 26; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* ROW_INSTDONE::PSD Done */ + + +#define GEN11_ROW_INSTDONE_PSDDone_bits 1 +#define GEN10_ROW_INSTDONE_PSDDone_bits 1 +#define GEN9_ROW_INSTDONE_PSDDone_bits 1 +#define GEN8_ROW_INSTDONE_PSDDone_bits 1 +#define GEN75_ROW_INSTDONE_PSDDone_bits 1 +#define GEN7_ROW_INSTDONE_PSDDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_PSDDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_ROW_INSTDONE_PSDDone_start 1 +#define GEN10_ROW_INSTDONE_PSDDone_start 1 +#define GEN9_ROW_INSTDONE_PSDDone_start 1 +#define GEN8_ROW_INSTDONE_PSDDone_start 1 +#define GEN75_ROW_INSTDONE_PSDDone_start 1 +#define GEN7_ROW_INSTDONE_PSDDone_start 1 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_PSDDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* ROW_INSTDONE::TDL Done */ + + +#define GEN11_ROW_INSTDONE_TDLDone_bits 1 +#define GEN10_ROW_INSTDONE_TDLDone_bits 1 +#define GEN9_ROW_INSTDONE_TDLDone_bits 1 +#define GEN8_ROW_INSTDONE_TDLDone_bits 1 +#define GEN75_ROW_INSTDONE_TDLDone_bits 1 +#define GEN7_ROW_INSTDONE_TDLDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_TDLDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_ROW_INSTDONE_TDLDone_start 6 +#define GEN10_ROW_INSTDONE_TDLDone_start 6 +#define GEN9_ROW_INSTDONE_TDLDone_start 6 +#define GEN8_ROW_INSTDONE_TDLDone_start 6 +#define GEN75_ROW_INSTDONE_TDLDone_start 6 +#define GEN7_ROW_INSTDONE_TDLDone_start 6 + +static inline uint32_t ATTRIBUTE_PURE +ROW_INSTDONE_TDLDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE */ + + +#define GEN11_SAMPLER_BORDER_COLOR_STATE_length 4 +#define GEN10_SAMPLER_BORDER_COLOR_STATE_length 4 +#define GEN9_SAMPLER_BORDER_COLOR_STATE_length 4 +#define GEN8_SAMPLER_BORDER_COLOR_STATE_length 4 +#define GEN75_SAMPLER_BORDER_COLOR_STATE_length 20 +#define GEN7_SAMPLER_BORDER_COLOR_STATE_length 4 +#define GEN6_SAMPLER_BORDER_COLOR_STATE_length 12 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_length 12 +#define GEN45_SAMPLER_BORDER_COLOR_STATE_length 12 +#define GEN4_SAMPLER_BORDER_COLOR_STATE_length 12 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 20; + } else { + return 4; + } + case 6: return 12; + case 5: return 12; + case 4: + if (devinfo->is_g4x) { + return 12; + } else { + return 12; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color 16bit Alpha */ + + +#define GEN75_SAMPLER_BORDER_COLOR_STATE_BorderColor16bitAlpha_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColor16bitAlpha_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_SAMPLER_BORDER_COLOR_STATE_BorderColor16bitAlpha_start 592 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColor16bitAlpha_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 592; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color 16bit Blue */ + + +#define GEN75_SAMPLER_BORDER_COLOR_STATE_BorderColor16bitBlue_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColor16bitBlue_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_SAMPLER_BORDER_COLOR_STATE_BorderColor16bitBlue_start 576 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColor16bitBlue_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 576; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color 16bit Green */ + + +#define GEN75_SAMPLER_BORDER_COLOR_STATE_BorderColor16bitGreen_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColor16bitGreen_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_SAMPLER_BORDER_COLOR_STATE_BorderColor16bitGreen_start 528 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColor16bitGreen_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 528; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color 16bit Red */ + + +#define GEN75_SAMPLER_BORDER_COLOR_STATE_BorderColor16bitRed_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColor16bitRed_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_SAMPLER_BORDER_COLOR_STATE_BorderColor16bitRed_start 512 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColor16bitRed_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 512; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color 32bit Alpha */ + + +#define GEN11_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitAlpha_bits 32 +#define GEN10_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitAlpha_bits 32 +#define GEN9_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitAlpha_bits 32 +#define GEN8_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitAlpha_bits 32 +#define GEN75_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitAlpha_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColor32bitAlpha_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitAlpha_start 96 +#define GEN10_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitAlpha_start 96 +#define GEN9_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitAlpha_start 96 +#define GEN8_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitAlpha_start 96 +#define GEN75_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitAlpha_start 608 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColor32bitAlpha_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 96; + case 10: return 96; + case 9: return 96; + case 8: return 96; + case 7: + if (devinfo->is_haswell) { + return 608; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color 32bit Blue */ + + +#define GEN11_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitBlue_bits 32 +#define GEN10_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitBlue_bits 32 +#define GEN9_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitBlue_bits 32 +#define GEN8_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitBlue_bits 32 +#define GEN75_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitBlue_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColor32bitBlue_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitBlue_start 64 +#define GEN10_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitBlue_start 64 +#define GEN9_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitBlue_start 64 +#define GEN8_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitBlue_start 64 +#define GEN75_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitBlue_start 576 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColor32bitBlue_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 576; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color 32bit Green */ + + +#define GEN11_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitGreen_bits 32 +#define GEN10_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitGreen_bits 32 +#define GEN9_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitGreen_bits 32 +#define GEN8_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitGreen_bits 32 +#define GEN75_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitGreen_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColor32bitGreen_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitGreen_start 32 +#define GEN10_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitGreen_start 32 +#define GEN9_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitGreen_start 32 +#define GEN8_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitGreen_start 32 +#define GEN75_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitGreen_start 544 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColor32bitGreen_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 544; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color 32bit Red */ + + +#define GEN11_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitRed_bits 32 +#define GEN10_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitRed_bits 32 +#define GEN9_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitRed_bits 32 +#define GEN8_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitRed_bits 32 +#define GEN75_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitRed_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColor32bitRed_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitRed_start 0 +#define GEN10_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitRed_start 0 +#define GEN9_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitRed_start 0 +#define GEN8_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitRed_start 0 +#define GEN75_SAMPLER_BORDER_COLOR_STATE_BorderColor32bitRed_start 512 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColor32bitRed_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 512; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color 8bit Alpha */ + + +#define GEN75_SAMPLER_BORDER_COLOR_STATE_BorderColor8bitAlpha_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColor8bitAlpha_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_SAMPLER_BORDER_COLOR_STATE_BorderColor8bitAlpha_start 536 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColor8bitAlpha_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 536; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color 8bit Blue */ + + +#define GEN75_SAMPLER_BORDER_COLOR_STATE_BorderColor8bitBlue_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColor8bitBlue_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_SAMPLER_BORDER_COLOR_STATE_BorderColor8bitBlue_start 528 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColor8bitBlue_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 528; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color 8bit Green */ + + +#define GEN75_SAMPLER_BORDER_COLOR_STATE_BorderColor8bitGreen_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColor8bitGreen_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_SAMPLER_BORDER_COLOR_STATE_BorderColor8bitGreen_start 520 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColor8bitGreen_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 520; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color 8bit Red */ + + +#define GEN75_SAMPLER_BORDER_COLOR_STATE_BorderColor8bitRed_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColor8bitRed_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_SAMPLER_BORDER_COLOR_STATE_BorderColor8bitRed_start 512 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColor8bitRed_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 512; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color Alpha */ + + +#define GEN45_SAMPLER_BORDER_COLOR_STATE_BorderColorAlpha_bits 32 +#define GEN4_SAMPLER_BORDER_COLOR_STATE_BorderColorAlpha_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorAlpha_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN45_SAMPLER_BORDER_COLOR_STATE_BorderColorAlpha_start 96 +#define GEN4_SAMPLER_BORDER_COLOR_STATE_BorderColorAlpha_start 96 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorAlpha_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 96; + } else { + return 96; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color Blue */ + + +#define GEN45_SAMPLER_BORDER_COLOR_STATE_BorderColorBlue_bits 32 +#define GEN4_SAMPLER_BORDER_COLOR_STATE_BorderColorBlue_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorBlue_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN45_SAMPLER_BORDER_COLOR_STATE_BorderColorBlue_start 64 +#define GEN4_SAMPLER_BORDER_COLOR_STATE_BorderColorBlue_start 64 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorBlue_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 64; + } else { + return 64; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color Float Alpha */ + + +#define GEN11_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatAlpha_bits 32 +#define GEN10_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatAlpha_bits 32 +#define GEN9_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatAlpha_bits 32 +#define GEN8_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatAlpha_bits 32 +#define GEN75_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatAlpha_bits 32 +#define GEN7_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatAlpha_bits 32 +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatAlpha_bits 32 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatAlpha_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorFloatAlpha_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatAlpha_start 96 +#define GEN10_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatAlpha_start 96 +#define GEN9_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatAlpha_start 96 +#define GEN8_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatAlpha_start 96 +#define GEN75_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatAlpha_start 96 +#define GEN7_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatAlpha_start 96 +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatAlpha_start 128 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatAlpha_start 128 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorFloatAlpha_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 96; + case 10: return 96; + case 9: return 96; + case 8: return 96; + case 7: + if (devinfo->is_haswell) { + return 96; + } else { + return 96; + } + case 6: return 128; + case 5: return 128; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color Float Blue */ + + +#define GEN11_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatBlue_bits 32 +#define GEN10_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatBlue_bits 32 +#define GEN9_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatBlue_bits 32 +#define GEN8_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatBlue_bits 32 +#define GEN75_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatBlue_bits 32 +#define GEN7_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatBlue_bits 32 +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatBlue_bits 32 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatBlue_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorFloatBlue_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatBlue_start 64 +#define GEN10_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatBlue_start 64 +#define GEN9_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatBlue_start 64 +#define GEN8_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatBlue_start 64 +#define GEN75_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatBlue_start 64 +#define GEN7_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatBlue_start 64 +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatBlue_start 96 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatBlue_start 96 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorFloatBlue_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 96; + case 5: return 96; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color Float Green */ + + +#define GEN11_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatGreen_bits 32 +#define GEN10_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatGreen_bits 32 +#define GEN9_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatGreen_bits 32 +#define GEN8_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatGreen_bits 32 +#define GEN75_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatGreen_bits 32 +#define GEN7_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatGreen_bits 32 +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatGreen_bits 32 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatGreen_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorFloatGreen_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatGreen_start 32 +#define GEN10_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatGreen_start 32 +#define GEN9_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatGreen_start 32 +#define GEN8_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatGreen_start 32 +#define GEN75_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatGreen_start 32 +#define GEN7_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatGreen_start 32 +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatGreen_start 64 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatGreen_start 64 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorFloatGreen_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 64; + case 5: return 64; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color Float Red */ + + +#define GEN11_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatRed_bits 32 +#define GEN10_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatRed_bits 32 +#define GEN9_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatRed_bits 32 +#define GEN8_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatRed_bits 32 +#define GEN75_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatRed_bits 32 +#define GEN7_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatRed_bits 32 +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatRed_bits 32 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatRed_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorFloatRed_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatRed_start 0 +#define GEN10_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatRed_start 0 +#define GEN9_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatRed_start 0 +#define GEN8_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatRed_start 0 +#define GEN75_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatRed_start 0 +#define GEN7_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatRed_start 0 +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatRed_start 32 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorFloatRed_start 32 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorFloatRed_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color Float16 Alpha */ + + +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Alpha_bits 16 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Alpha_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Alpha_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Alpha_start 208 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Alpha_start 208 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Alpha_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 208; + case 5: return 208; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color Float16 Blue */ + + +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Blue_bits 16 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Blue_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Blue_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Blue_start 192 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Blue_start 192 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Blue_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 192; + case 5: return 192; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color Float16 Green */ + + +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Green_bits 16 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Green_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Green_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Green_start 176 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Green_start 176 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Green_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 176; + case 5: return 176; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color Float16 Red */ + + +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Red_bits 16 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Red_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Red_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Red_start 160 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Red_start 160 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorFloat16Red_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 160; + case 5: return 160; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color Green */ + + +#define GEN45_SAMPLER_BORDER_COLOR_STATE_BorderColorGreen_bits 32 +#define GEN4_SAMPLER_BORDER_COLOR_STATE_BorderColorGreen_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorGreen_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN45_SAMPLER_BORDER_COLOR_STATE_BorderColorGreen_start 32 +#define GEN4_SAMPLER_BORDER_COLOR_STATE_BorderColorGreen_start 32 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorGreen_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color Red */ + + +#define GEN45_SAMPLER_BORDER_COLOR_STATE_BorderColorRed_bits 32 +#define GEN4_SAMPLER_BORDER_COLOR_STATE_BorderColorRed_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorRed_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN45_SAMPLER_BORDER_COLOR_STATE_BorderColorRed_start 0 +#define GEN4_SAMPLER_BORDER_COLOR_STATE_BorderColorRed_start 0 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorRed_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color Snorm16 Alpha */ + + +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Alpha_bits 16 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Alpha_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Alpha_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Alpha_start 336 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Alpha_start 336 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Alpha_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 336; + case 5: return 336; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color Snorm16 Blue */ + + +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Blue_bits 16 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Blue_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Blue_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Blue_start 320 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Blue_start 320 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Blue_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 320; + case 5: return 320; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color Snorm16 Green */ + + +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Green_bits 16 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Green_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Green_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Green_start 304 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Green_start 304 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Green_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 304; + case 5: return 304; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color Snorm16 Red */ + + +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Red_bits 16 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Red_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Red_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Red_start 288 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Red_start 288 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm16Red_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 288; + case 5: return 288; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color Snorm8 Alpha */ + + +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Alpha_bits 8 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Alpha_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Alpha_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Alpha_start 376 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Alpha_start 376 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Alpha_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 376; + case 5: return 376; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color Snorm8 Blue */ + + +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Blue_bits 8 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Blue_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Blue_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Blue_start 368 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Blue_start 368 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Blue_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 368; + case 5: return 368; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color Snorm8 Green */ + + +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Green_bits 8 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Green_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Green_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Green_start 360 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Green_start 360 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Green_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 360; + case 5: return 360; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color Snorm8 Red */ + + +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Red_bits 8 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Red_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Red_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Red_start 352 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Red_start 352 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorSnorm8Red_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 352; + case 5: return 352; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color Unorm Alpha */ + + +#define GEN7_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormAlpha_bits 8 +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormAlpha_bits 8 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormAlpha_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorUnormAlpha_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN7_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormAlpha_start 24 +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormAlpha_start 24 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormAlpha_start 24 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorUnormAlpha_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 24; + } + case 6: return 24; + case 5: return 24; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color Unorm Blue */ + + +#define GEN7_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormBlue_bits 8 +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormBlue_bits 8 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormBlue_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorUnormBlue_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN7_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormBlue_start 16 +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormBlue_start 16 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormBlue_start 16 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorUnormBlue_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 16; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color Unorm Green */ + + +#define GEN7_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormGreen_bits 8 +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormGreen_bits 8 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormGreen_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorUnormGreen_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN7_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormGreen_start 8 +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormGreen_start 8 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormGreen_start 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorUnormGreen_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color Unorm Red */ + + +#define GEN7_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormRed_bits 8 +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormRed_bits 8 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormRed_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorUnormRed_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN7_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormRed_start 0 +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormRed_start 0 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorUnormRed_start 0 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorUnormRed_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color Unorm16 Alpha */ + + +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Alpha_bits 16 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Alpha_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Alpha_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Alpha_start 272 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Alpha_start 272 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Alpha_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 272; + case 5: return 272; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color Unorm16 Blue */ + + +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Blue_bits 16 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Blue_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Blue_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Blue_start 256 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Blue_start 256 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Blue_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 256; + case 5: return 256; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color Unorm16 Green */ + + +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Green_bits 16 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Green_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Green_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Green_start 240 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Green_start 240 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Green_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 240; + case 5: return 240; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_BORDER_COLOR_STATE::Border Color Unorm16 Red */ + + +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Red_bits 16 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Red_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Red_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Red_start 224 +#define GEN5_SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Red_start 224 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_BORDER_COLOR_STATE_BorderColorUnorm16Red_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 224; + case 5: return 224; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INDIRECT_STATE_BORDER_COLOR */ + + +#define GEN11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_length 4 +#define GEN10_SAMPLER_INDIRECT_STATE_BORDER_COLOR_length 4 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INDIRECT_STATE_BORDER_COLOR_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INDIRECT_STATE_BORDER_COLOR::Border Color Alpha As Float */ + + +#define GEN11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsFloat_bits 32 +#define GEN10_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsFloat_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsFloat_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsFloat_start 96 +#define GEN10_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsFloat_start 96 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsFloat_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 96; + case 10: return 96; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INDIRECT_STATE_BORDER_COLOR::Border Color Alpha As S31 */ + + +#define GEN11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsS31_bits 32 +#define GEN10_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsS31_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsS31_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsS31_start 96 +#define GEN10_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsS31_start 96 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsS31_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 96; + case 10: return 96; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INDIRECT_STATE_BORDER_COLOR::Border Color Alpha As U32 */ + + +#define GEN11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsU32_bits 32 +#define GEN10_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsU32_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsU32_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsU32_start 96 +#define GEN10_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsU32_start 96 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsU32_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 96; + case 10: return 96; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INDIRECT_STATE_BORDER_COLOR::Border Color Alpha As U8 */ + + +#define GEN11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsU8_bits 8 +#define GEN10_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsU8_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsU8_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsU8_start 24 +#define GEN10_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsU8_start 24 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorAlphaAsU8_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INDIRECT_STATE_BORDER_COLOR::Border Color Blue As Float */ + + +#define GEN11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsFloat_bits 32 +#define GEN10_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsFloat_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsFloat_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsFloat_start 64 +#define GEN10_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsFloat_start 64 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsFloat_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INDIRECT_STATE_BORDER_COLOR::Border Color Blue As S31 */ + + +#define GEN11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsS31_bits 32 +#define GEN10_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsS31_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsS31_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsS31_start 64 +#define GEN10_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsS31_start 64 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsS31_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INDIRECT_STATE_BORDER_COLOR::Border Color Blue As U32 */ + + +#define GEN11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsU32_bits 32 +#define GEN10_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsU32_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsU32_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsU32_start 64 +#define GEN10_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsU32_start 64 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsU32_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INDIRECT_STATE_BORDER_COLOR::Border Color Blue As U8 */ + + +#define GEN11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsU8_bits 8 +#define GEN10_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsU8_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsU8_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsU8_start 16 +#define GEN10_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsU8_start 16 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorBlueAsU8_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INDIRECT_STATE_BORDER_COLOR::Border Color Green As Float */ + + +#define GEN11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsFloat_bits 32 +#define GEN10_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsFloat_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsFloat_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsFloat_start 32 +#define GEN10_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsFloat_start 32 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsFloat_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INDIRECT_STATE_BORDER_COLOR::Border Color Green As S31 */ + + +#define GEN11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsS31_bits 32 +#define GEN10_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsS31_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsS31_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsS31_start 32 +#define GEN10_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsS31_start 32 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsS31_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INDIRECT_STATE_BORDER_COLOR::Border Color Green As U32 */ + + +#define GEN11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsU32_bits 32 +#define GEN10_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsU32_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsU32_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsU32_start 32 +#define GEN10_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsU32_start 32 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsU32_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INDIRECT_STATE_BORDER_COLOR::Border Color Green As U8 */ + + +#define GEN11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsU8_bits 8 +#define GEN10_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsU8_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsU8_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsU8_start 8 +#define GEN10_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsU8_start 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorGreenAsU8_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INDIRECT_STATE_BORDER_COLOR::Border Color Red As Float */ + + +#define GEN11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsFloat_bits 32 +#define GEN10_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsFloat_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsFloat_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsFloat_start 0 +#define GEN10_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsFloat_start 0 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsFloat_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INDIRECT_STATE_BORDER_COLOR::Border Color Red As S31 */ + + +#define GEN11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsS31_bits 32 +#define GEN10_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsS31_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsS31_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsS31_start 0 +#define GEN10_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsS31_start 0 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsS31_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INDIRECT_STATE_BORDER_COLOR::Border Color Red As U32 */ + + +#define GEN11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsU32_bits 32 +#define GEN10_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsU32_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsU32_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsU32_start 0 +#define GEN10_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsU32_start 0 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsU32_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INDIRECT_STATE_BORDER_COLOR::Border Color Red As U8 */ + + +#define GEN11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsU8_bits 8 +#define GEN10_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsU8_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsU8_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsU8_start 0 +#define GEN10_SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsU8_start 0 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INDIRECT_STATE_BORDER_COLOR_BorderColorRedAsU8_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INSTDONE */ + + +#define GEN11_SAMPLER_INSTDONE_length 1 +#define GEN10_SAMPLER_INSTDONE_length 1 +#define GEN9_SAMPLER_INSTDONE_length 1 +#define GEN8_SAMPLER_INSTDONE_length 1 +#define GEN75_SAMPLER_INSTDONE_length 1 +#define GEN7_SAMPLER_INSTDONE_length 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INSTDONE::AVS Done */ + + +#define GEN11_SAMPLER_INSTDONE_AVSDone_bits 1 +#define GEN10_SAMPLER_INSTDONE_AVSDone_bits 1 +#define GEN9_SAMPLER_INSTDONE_AVSDone_bits 1 +#define GEN8_SAMPLER_INSTDONE_AVSDone_bits 1 +#define GEN75_SAMPLER_INSTDONE_AVSDone_bits 1 +#define GEN7_SAMPLER_INSTDONE_AVSDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_AVSDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_INSTDONE_AVSDone_start 12 +#define GEN10_SAMPLER_INSTDONE_AVSDone_start 12 +#define GEN9_SAMPLER_INSTDONE_AVSDone_start 12 +#define GEN8_SAMPLER_INSTDONE_AVSDone_start 12 +#define GEN75_SAMPLER_INSTDONE_AVSDone_start 12 +#define GEN7_SAMPLER_INSTDONE_AVSDone_start 12 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_AVSDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 12; + case 10: return 12; + case 9: return 12; + case 8: return 12; + case 7: + if (devinfo->is_haswell) { + return 12; + } else { + return 12; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INSTDONE::BDM Done */ + + +#define GEN11_SAMPLER_INSTDONE_BDMDone_bits 1 +#define GEN10_SAMPLER_INSTDONE_BDMDone_bits 1 +#define GEN9_SAMPLER_INSTDONE_BDMDone_bits 1 +#define GEN8_SAMPLER_INSTDONE_BDMDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_BDMDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_INSTDONE_BDMDone_start 19 +#define GEN10_SAMPLER_INSTDONE_BDMDone_start 19 +#define GEN9_SAMPLER_INSTDONE_BDMDone_start 19 +#define GEN8_SAMPLER_INSTDONE_BDMDone_start 19 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_BDMDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 19; + case 10: return 19; + case 9: return 19; + case 8: return 19; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INSTDONE::CRE Done */ + + +#define GEN11_SAMPLER_INSTDONE_CREDone_bits 1 +#define GEN10_SAMPLER_INSTDONE_CREDone_bits 1 +#define GEN9_SAMPLER_INSTDONE_CREDone_bits 1 +#define GEN8_SAMPLER_INSTDONE_CREDone_bits 1 +#define GEN75_SAMPLER_INSTDONE_CREDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_CREDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_INSTDONE_CREDone_start 14 +#define GEN10_SAMPLER_INSTDONE_CREDone_start 14 +#define GEN9_SAMPLER_INSTDONE_CREDone_start 14 +#define GEN8_SAMPLER_INSTDONE_CREDone_start 14 +#define GEN75_SAMPLER_INSTDONE_CREDone_start 14 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_CREDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 14; + case 10: return 14; + case 9: return 14; + case 8: return 14; + case 7: + if (devinfo->is_haswell) { + return 14; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INSTDONE::DG0 Done */ + + +#define GEN11_SAMPLER_INSTDONE_DG0Done_bits 1 +#define GEN10_SAMPLER_INSTDONE_DG0Done_bits 1 +#define GEN9_SAMPLER_INSTDONE_DG0Done_bits 1 +#define GEN8_SAMPLER_INSTDONE_DG0Done_bits 1 +#define GEN75_SAMPLER_INSTDONE_DG0Done_bits 1 +#define GEN7_SAMPLER_INSTDONE_DG0Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_DG0Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_INSTDONE_DG0Done_start 3 +#define GEN10_SAMPLER_INSTDONE_DG0Done_start 3 +#define GEN9_SAMPLER_INSTDONE_DG0Done_start 3 +#define GEN8_SAMPLER_INSTDONE_DG0Done_start 3 +#define GEN75_SAMPLER_INSTDONE_DG0Done_start 3 +#define GEN7_SAMPLER_INSTDONE_DG0Done_start 3 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_DG0Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INSTDONE::DM0 Done */ + + +#define GEN11_SAMPLER_INSTDONE_DM0Done_bits 1 +#define GEN10_SAMPLER_INSTDONE_DM0Done_bits 1 +#define GEN9_SAMPLER_INSTDONE_DM0Done_bits 1 +#define GEN8_SAMPLER_INSTDONE_DM0Done_bits 1 +#define GEN75_SAMPLER_INSTDONE_DM0Done_bits 1 +#define GEN7_SAMPLER_INSTDONE_DM0Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_DM0Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_INSTDONE_DM0Done_start 5 +#define GEN10_SAMPLER_INSTDONE_DM0Done_start 5 +#define GEN9_SAMPLER_INSTDONE_DM0Done_start 5 +#define GEN8_SAMPLER_INSTDONE_DM0Done_start 5 +#define GEN75_SAMPLER_INSTDONE_DM0Done_start 5 +#define GEN7_SAMPLER_INSTDONE_DM0Done_start 5 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_DM0Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 5; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INSTDONE::DM1 Done */ + + +#define GEN75_SAMPLER_INSTDONE_DM1Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_DM1Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_SAMPLER_INSTDONE_DM1Done_start 20 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_DM1Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 20; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INSTDONE::FL0 Done */ + + +#define GEN11_SAMPLER_INSTDONE_FL0Done_bits 1 +#define GEN10_SAMPLER_INSTDONE_FL0Done_bits 1 +#define GEN9_SAMPLER_INSTDONE_FL0Done_bits 1 +#define GEN8_SAMPLER_INSTDONE_FL0Done_bits 1 +#define GEN75_SAMPLER_INSTDONE_FL0Done_bits 1 +#define GEN7_SAMPLER_INSTDONE_FL0Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_FL0Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_INSTDONE_FL0Done_start 7 +#define GEN10_SAMPLER_INSTDONE_FL0Done_start 7 +#define GEN9_SAMPLER_INSTDONE_FL0Done_start 7 +#define GEN8_SAMPLER_INSTDONE_FL0Done_start 7 +#define GEN75_SAMPLER_INSTDONE_FL0Done_start 7 +#define GEN7_SAMPLER_INSTDONE_FL0Done_start 7 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_FL0Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 7; + } else { + return 7; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INSTDONE::FT0 Done */ + + +#define GEN11_SAMPLER_INSTDONE_FT0Done_bits 1 +#define GEN10_SAMPLER_INSTDONE_FT0Done_bits 1 +#define GEN9_SAMPLER_INSTDONE_FT0Done_bits 1 +#define GEN8_SAMPLER_INSTDONE_FT0Done_bits 1 +#define GEN75_SAMPLER_INSTDONE_FT0Done_bits 1 +#define GEN7_SAMPLER_INSTDONE_FT0Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_FT0Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_INSTDONE_FT0Done_start 4 +#define GEN10_SAMPLER_INSTDONE_FT0Done_start 4 +#define GEN9_SAMPLER_INSTDONE_FT0Done_start 4 +#define GEN8_SAMPLER_INSTDONE_FT0Done_start 4 +#define GEN75_SAMPLER_INSTDONE_FT0Done_start 4 +#define GEN7_SAMPLER_INSTDONE_FT0Done_start 4 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_FT0Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INSTDONE::FT1 Done */ + + +#define GEN75_SAMPLER_INSTDONE_FT1Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_FT1Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_SAMPLER_INSTDONE_FT1Done_start 19 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_FT1Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 19; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INSTDONE::IEF Done */ + + +#define GEN11_SAMPLER_INSTDONE_IEFDone_bits 1 +#define GEN10_SAMPLER_INSTDONE_IEFDone_bits 1 +#define GEN9_SAMPLER_INSTDONE_IEFDone_bits 1 +#define GEN8_SAMPLER_INSTDONE_IEFDone_bits 1 +#define GEN75_SAMPLER_INSTDONE_IEFDone_bits 1 +#define GEN7_SAMPLER_INSTDONE_IEFDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_IEFDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_INSTDONE_IEFDone_start 13 +#define GEN10_SAMPLER_INSTDONE_IEFDone_start 13 +#define GEN9_SAMPLER_INSTDONE_IEFDone_start 13 +#define GEN8_SAMPLER_INSTDONE_IEFDone_start 13 +#define GEN75_SAMPLER_INSTDONE_IEFDone_start 13 +#define GEN7_SAMPLER_INSTDONE_IEFDone_start 13 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_IEFDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 13; + case 10: return 13; + case 9: return 13; + case 8: return 13; + case 7: + if (devinfo->is_haswell) { + return 13; + } else { + return 13; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INSTDONE::IME Done */ + + +#define GEN11_SAMPLER_INSTDONE_IMEDone_bits 1 +#define GEN10_SAMPLER_INSTDONE_IMEDone_bits 1 +#define GEN9_SAMPLER_INSTDONE_IMEDone_bits 1 +#define GEN8_SAMPLER_INSTDONE_IMEDone_bits 1 +#define GEN75_SAMPLER_INSTDONE_IMEDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_IMEDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_INSTDONE_IMEDone_start 0 +#define GEN10_SAMPLER_INSTDONE_IMEDone_start 0 +#define GEN9_SAMPLER_INSTDONE_IMEDone_start 0 +#define GEN8_SAMPLER_INSTDONE_IMEDone_start 0 +#define GEN75_SAMPLER_INSTDONE_IMEDone_start 0 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_IMEDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INSTDONE::MT0 Done */ + + +#define GEN11_SAMPLER_INSTDONE_MT0Done_bits 1 +#define GEN10_SAMPLER_INSTDONE_MT0Done_bits 1 +#define GEN9_SAMPLER_INSTDONE_MT0Done_bits 1 +#define GEN8_SAMPLER_INSTDONE_MT0Done_bits 1 +#define GEN75_SAMPLER_INSTDONE_MT0Done_bits 1 +#define GEN7_SAMPLER_INSTDONE_MT0Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_MT0Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_INSTDONE_MT0Done_start 11 +#define GEN10_SAMPLER_INSTDONE_MT0Done_start 11 +#define GEN9_SAMPLER_INSTDONE_MT0Done_start 11 +#define GEN8_SAMPLER_INSTDONE_MT0Done_start 11 +#define GEN75_SAMPLER_INSTDONE_MT0Done_start 11 +#define GEN7_SAMPLER_INSTDONE_MT0Done_start 11 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_MT0Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 11; + } else { + return 11; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INSTDONE::MT1 Done */ + + +#define GEN75_SAMPLER_INSTDONE_MT1Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_MT1Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_SAMPLER_INSTDONE_MT1Done_start 21 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_MT1Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 21; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INSTDONE::PL0 Done */ + + +#define GEN11_SAMPLER_INSTDONE_PL0Done_bits 1 +#define GEN10_SAMPLER_INSTDONE_PL0Done_bits 1 +#define GEN9_SAMPLER_INSTDONE_PL0Done_bits 1 +#define GEN8_SAMPLER_INSTDONE_PL0Done_bits 1 +#define GEN75_SAMPLER_INSTDONE_PL0Done_bits 1 +#define GEN7_SAMPLER_INSTDONE_PL0Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_PL0Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_INSTDONE_PL0Done_start 1 +#define GEN10_SAMPLER_INSTDONE_PL0Done_start 1 +#define GEN9_SAMPLER_INSTDONE_PL0Done_start 1 +#define GEN8_SAMPLER_INSTDONE_PL0Done_start 1 +#define GEN75_SAMPLER_INSTDONE_PL0Done_start 1 +#define GEN7_SAMPLER_INSTDONE_PL0Done_start 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_PL0Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INSTDONE::QC Done */ + + +#define GEN11_SAMPLER_INSTDONE_QCDone_bits 1 +#define GEN10_SAMPLER_INSTDONE_QCDone_bits 1 +#define GEN9_SAMPLER_INSTDONE_QCDone_bits 1 +#define GEN8_SAMPLER_INSTDONE_QCDone_bits 1 +#define GEN75_SAMPLER_INSTDONE_QCDone_bits 1 +#define GEN7_SAMPLER_INSTDONE_QCDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_QCDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_INSTDONE_QCDone_start 8 +#define GEN10_SAMPLER_INSTDONE_QCDone_start 8 +#define GEN9_SAMPLER_INSTDONE_QCDone_start 8 +#define GEN8_SAMPLER_INSTDONE_QCDone_start 8 +#define GEN75_SAMPLER_INSTDONE_QCDone_start 8 +#define GEN7_SAMPLER_INSTDONE_QCDone_start 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_QCDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INSTDONE::SC Done */ + + +#define GEN11_SAMPLER_INSTDONE_SCDone_bits 1 +#define GEN10_SAMPLER_INSTDONE_SCDone_bits 1 +#define GEN9_SAMPLER_INSTDONE_SCDone_bits 1 +#define GEN8_SAMPLER_INSTDONE_SCDone_bits 1 +#define GEN75_SAMPLER_INSTDONE_SCDone_bits 1 +#define GEN7_SAMPLER_INSTDONE_SCDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_SCDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_INSTDONE_SCDone_start 6 +#define GEN10_SAMPLER_INSTDONE_SCDone_start 6 +#define GEN9_SAMPLER_INSTDONE_SCDone_start 6 +#define GEN8_SAMPLER_INSTDONE_SCDone_start 6 +#define GEN75_SAMPLER_INSTDONE_SCDone_start 6 +#define GEN7_SAMPLER_INSTDONE_SCDone_start 6 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_SCDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INSTDONE::SI0 Done */ + + +#define GEN11_SAMPLER_INSTDONE_SI0Done_bits 1 +#define GEN10_SAMPLER_INSTDONE_SI0Done_bits 1 +#define GEN9_SAMPLER_INSTDONE_SI0Done_bits 1 +#define GEN8_SAMPLER_INSTDONE_SI0Done_bits 1 +#define GEN75_SAMPLER_INSTDONE_SI0Done_bits 1 +#define GEN7_SAMPLER_INSTDONE_SI0Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_SI0Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_INSTDONE_SI0Done_start 10 +#define GEN10_SAMPLER_INSTDONE_SI0Done_start 10 +#define GEN9_SAMPLER_INSTDONE_SI0Done_start 10 +#define GEN8_SAMPLER_INSTDONE_SI0Done_start 10 +#define GEN75_SAMPLER_INSTDONE_SI0Done_start 10 +#define GEN7_SAMPLER_INSTDONE_SI0Done_start 10 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_SI0Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 10; + case 10: return 10; + case 9: return 10; + case 8: return 10; + case 7: + if (devinfo->is_haswell) { + return 10; + } else { + return 10; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INSTDONE::SO0 Done */ + + +#define GEN11_SAMPLER_INSTDONE_SO0Done_bits 1 +#define GEN10_SAMPLER_INSTDONE_SO0Done_bits 1 +#define GEN9_SAMPLER_INSTDONE_SO0Done_bits 1 +#define GEN8_SAMPLER_INSTDONE_SO0Done_bits 1 +#define GEN75_SAMPLER_INSTDONE_SO0Done_bits 1 +#define GEN7_SAMPLER_INSTDONE_SO0Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_SO0Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_INSTDONE_SO0Done_start 2 +#define GEN10_SAMPLER_INSTDONE_SO0Done_start 2 +#define GEN9_SAMPLER_INSTDONE_SO0Done_start 2 +#define GEN8_SAMPLER_INSTDONE_SO0Done_start 2 +#define GEN75_SAMPLER_INSTDONE_SO0Done_start 2 +#define GEN7_SAMPLER_INSTDONE_SO0Done_start 2 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_SO0Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INSTDONE::SVSM ARB1 */ + + +#define GEN11_SAMPLER_INSTDONE_SVSMARB1_bits 1 +#define GEN10_SAMPLER_INSTDONE_SVSMARB1_bits 1 +#define GEN9_SAMPLER_INSTDONE_SVSMARB1_bits 1 +#define GEN8_SAMPLER_INSTDONE_SVSMARB1_bits 1 +#define GEN75_SAMPLER_INSTDONE_SVSMARB1_bits 1 +#define GEN7_SAMPLER_INSTDONE_SVSMARB1_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_SVSMARB1_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_INSTDONE_SVSMARB1_start 17 +#define GEN10_SAMPLER_INSTDONE_SVSMARB1_start 17 +#define GEN9_SAMPLER_INSTDONE_SVSMARB1_start 17 +#define GEN8_SAMPLER_INSTDONE_SVSMARB1_start 17 +#define GEN75_SAMPLER_INSTDONE_SVSMARB1_start 17 +#define GEN7_SAMPLER_INSTDONE_SVSMARB1_start 17 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_SVSMARB1_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 17; + case 10: return 17; + case 9: return 17; + case 8: return 17; + case 7: + if (devinfo->is_haswell) { + return 17; + } else { + return 17; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INSTDONE::SVSM ARB2 */ + + +#define GEN11_SAMPLER_INSTDONE_SVSMARB2_bits 1 +#define GEN10_SAMPLER_INSTDONE_SVSMARB2_bits 1 +#define GEN9_SAMPLER_INSTDONE_SVSMARB2_bits 1 +#define GEN8_SAMPLER_INSTDONE_SVSMARB2_bits 1 +#define GEN75_SAMPLER_INSTDONE_SVSMARB2_bits 1 +#define GEN7_SAMPLER_INSTDONE_SVSMARB2_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_SVSMARB2_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_INSTDONE_SVSMARB2_start 16 +#define GEN10_SAMPLER_INSTDONE_SVSMARB2_start 16 +#define GEN9_SAMPLER_INSTDONE_SVSMARB2_start 16 +#define GEN8_SAMPLER_INSTDONE_SVSMARB2_start 16 +#define GEN75_SAMPLER_INSTDONE_SVSMARB2_start 16 +#define GEN7_SAMPLER_INSTDONE_SVSMARB2_start 16 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_SVSMARB2_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INSTDONE::SVSM ARB3 */ + + +#define GEN9_SAMPLER_INSTDONE_SVSMARB3_bits 1 +#define GEN8_SAMPLER_INSTDONE_SVSMARB3_bits 1 +#define GEN75_SAMPLER_INSTDONE_SVSMARB3_bits 1 +#define GEN7_SAMPLER_INSTDONE_SVSMARB3_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_SVSMARB3_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_SAMPLER_INSTDONE_SVSMARB3_start 15 +#define GEN8_SAMPLER_INSTDONE_SVSMARB3_start 15 +#define GEN75_SAMPLER_INSTDONE_SVSMARB3_start 15 +#define GEN7_SAMPLER_INSTDONE_SVSMARB3_start 15 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_SVSMARB3_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 15; + case 8: return 15; + case 7: + if (devinfo->is_haswell) { + return 15; + } else { + return 15; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INSTDONE::SVSM Adapter */ + + +#define GEN11_SAMPLER_INSTDONE_SVSMAdapter_bits 1 +#define GEN10_SAMPLER_INSTDONE_SVSMAdapter_bits 1 +#define GEN9_SAMPLER_INSTDONE_SVSMAdapter_bits 1 +#define GEN8_SAMPLER_INSTDONE_SVSMAdapter_bits 1 +#define GEN75_SAMPLER_INSTDONE_SVSMAdapter_bits 1 +#define GEN7_SAMPLER_INSTDONE_SVSMAdapter_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_SVSMAdapter_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_INSTDONE_SVSMAdapter_start 18 +#define GEN10_SAMPLER_INSTDONE_SVSMAdapter_start 18 +#define GEN9_SAMPLER_INSTDONE_SVSMAdapter_start 18 +#define GEN8_SAMPLER_INSTDONE_SVSMAdapter_start 18 +#define GEN75_SAMPLER_INSTDONE_SVSMAdapter_start 18 +#define GEN7_SAMPLER_INSTDONE_SVSMAdapter_start 18 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_SVSMAdapter_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 18; + case 10: return 18; + case 9: return 18; + case 8: return 18; + case 7: + if (devinfo->is_haswell) { + return 18; + } else { + return 18; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INSTDONE::SVSM Done */ + + +#define GEN11_SAMPLER_INSTDONE_SVSMDone_bits 1 +#define GEN10_SAMPLER_INSTDONE_SVSMDone_bits 1 +#define GEN9_SAMPLER_INSTDONE_SVSMDone_bits 1 +#define GEN8_SAMPLER_INSTDONE_SVSMDone_bits 1 +#define GEN75_SAMPLER_INSTDONE_SVSMDone_bits 1 +#define GEN7_SAMPLER_INSTDONE_SVSMDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_SVSMDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_INSTDONE_SVSMDone_start 9 +#define GEN10_SAMPLER_INSTDONE_SVSMDone_start 9 +#define GEN9_SAMPLER_INSTDONE_SVSMDone_start 9 +#define GEN8_SAMPLER_INSTDONE_SVSMDone_start 9 +#define GEN75_SAMPLER_INSTDONE_SVSMDone_start 9 +#define GEN7_SAMPLER_INSTDONE_SVSMDone_start 9 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_SVSMDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 9; + case 10: return 9; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 9; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INSTDONE::SVSM_ARB_SIFM */ + + +#define GEN11_SAMPLER_INSTDONE_SVSM_ARB_SIFM_bits 1 +#define GEN10_SAMPLER_INSTDONE_SVSM_ARB_SIFM_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_SVSM_ARB_SIFM_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_INSTDONE_SVSM_ARB_SIFM_start 15 +#define GEN10_SAMPLER_INSTDONE_SVSM_ARB_SIFM_start 15 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_SVSM_ARB_SIFM_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 15; + case 10: return 15; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INSTDONE::VDI Done */ + + +#define GEN7_SAMPLER_INSTDONE_VDIDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_VDIDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN7_SAMPLER_INSTDONE_VDIDone_start 14 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_VDIDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 14; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_INSTDONE::VME Done */ + + +#define GEN7_SAMPLER_INSTDONE_VMEDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_VMEDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN7_SAMPLER_INSTDONE_VMEDone_start 0 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_INSTDONE_VMEDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_MODE */ + + +#define GEN11_SAMPLER_MODE_length 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_MODE_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_MODE::Headerless Message for Pre-emptable Contexts */ + + +#define GEN11_SAMPLER_MODE_HeaderlessMessageforPreemptableContexts_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_MODE_HeaderlessMessageforPreemptableContexts_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_MODE_HeaderlessMessageforPreemptableContexts_start 5 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_MODE_HeaderlessMessageforPreemptableContexts_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_MODE::Headerless Message for Pre-emptable Contexts Mask */ + + +#define GEN11_SAMPLER_MODE_HeaderlessMessageforPreemptableContextsMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_MODE_HeaderlessMessageforPreemptableContextsMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_MODE_HeaderlessMessageforPreemptableContextsMask_start 21 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_MODE_HeaderlessMessageforPreemptableContextsMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 21; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE */ + + +#define GEN11_SAMPLER_STATE_length 4 +#define GEN10_SAMPLER_STATE_length 4 +#define GEN9_SAMPLER_STATE_length 4 +#define GEN8_SAMPLER_STATE_length 4 +#define GEN75_SAMPLER_STATE_length 4 +#define GEN7_SAMPLER_STATE_length 4 +#define GEN6_SAMPLER_STATE_length 4 +#define GEN5_SAMPLER_STATE_length 4 +#define GEN45_SAMPLER_STATE_length 4 +#define GEN4_SAMPLER_STATE_length 4 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 4; + case 4: + if (devinfo->is_g4x) { + return 4; + } else { + return 4; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::Anisotropic Algorithm */ + + +#define GEN11_SAMPLER_STATE_AnisotropicAlgorithm_bits 1 +#define GEN10_SAMPLER_STATE_AnisotropicAlgorithm_bits 1 +#define GEN9_SAMPLER_STATE_AnisotropicAlgorithm_bits 1 +#define GEN8_SAMPLER_STATE_AnisotropicAlgorithm_bits 1 +#define GEN75_SAMPLER_STATE_AnisotropicAlgorithm_bits 1 +#define GEN7_SAMPLER_STATE_AnisotropicAlgorithm_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_AnisotropicAlgorithm_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_AnisotropicAlgorithm_start 0 +#define GEN10_SAMPLER_STATE_AnisotropicAlgorithm_start 0 +#define GEN9_SAMPLER_STATE_AnisotropicAlgorithm_start 0 +#define GEN8_SAMPLER_STATE_AnisotropicAlgorithm_start 0 +#define GEN75_SAMPLER_STATE_AnisotropicAlgorithm_start 0 +#define GEN7_SAMPLER_STATE_AnisotropicAlgorithm_start 0 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_AnisotropicAlgorithm_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::Base Mip Level */ + + +#define GEN8_SAMPLER_STATE_BaseMipLevel_bits 5 +#define GEN75_SAMPLER_STATE_BaseMipLevel_bits 5 +#define GEN7_SAMPLER_STATE_BaseMipLevel_bits 5 +#define GEN6_SAMPLER_STATE_BaseMipLevel_bits 5 +#define GEN5_SAMPLER_STATE_BaseMipLevel_bits 5 +#define GEN45_SAMPLER_STATE_BaseMipLevel_bits 5 +#define GEN4_SAMPLER_STATE_BaseMipLevel_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_BaseMipLevel_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 5; + } + case 6: return 5; + case 5: return 5; + case 4: + if (devinfo->is_g4x) { + return 5; + } else { + return 5; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_SAMPLER_STATE_BaseMipLevel_start 22 +#define GEN75_SAMPLER_STATE_BaseMipLevel_start 22 +#define GEN7_SAMPLER_STATE_BaseMipLevel_start 22 +#define GEN6_SAMPLER_STATE_BaseMipLevel_start 22 +#define GEN5_SAMPLER_STATE_BaseMipLevel_start 22 +#define GEN45_SAMPLER_STATE_BaseMipLevel_start 22 +#define GEN4_SAMPLER_STATE_BaseMipLevel_start 22 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_BaseMipLevel_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 22; + case 7: + if (devinfo->is_haswell) { + return 22; + } else { + return 22; + } + case 6: return 22; + case 5: return 22; + case 4: + if (devinfo->is_g4x) { + return 22; + } else { + return 22; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::Border Color Pointer */ + + +#define GEN11_SAMPLER_STATE_BorderColorPointer_bits 18 +#define GEN10_SAMPLER_STATE_BorderColorPointer_bits 18 +#define GEN9_SAMPLER_STATE_BorderColorPointer_bits 18 +#define GEN8_SAMPLER_STATE_BorderColorPointer_bits 18 +#define GEN75_SAMPLER_STATE_BorderColorPointer_bits 27 +#define GEN7_SAMPLER_STATE_BorderColorPointer_bits 27 +#define GEN6_SAMPLER_STATE_BorderColorPointer_bits 27 +#define GEN5_SAMPLER_STATE_BorderColorPointer_bits 27 +#define GEN45_SAMPLER_STATE_BorderColorPointer_bits 27 +#define GEN4_SAMPLER_STATE_BorderColorPointer_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_BorderColorPointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 18; + case 10: return 18; + case 9: return 18; + case 8: return 18; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_BorderColorPointer_start 70 +#define GEN10_SAMPLER_STATE_BorderColorPointer_start 70 +#define GEN9_SAMPLER_STATE_BorderColorPointer_start 70 +#define GEN8_SAMPLER_STATE_BorderColorPointer_start 70 +#define GEN75_SAMPLER_STATE_BorderColorPointer_start 69 +#define GEN7_SAMPLER_STATE_BorderColorPointer_start 69 +#define GEN6_SAMPLER_STATE_BorderColorPointer_start 69 +#define GEN5_SAMPLER_STATE_BorderColorPointer_start 69 +#define GEN45_SAMPLER_STATE_BorderColorPointer_start 69 +#define GEN4_SAMPLER_STATE_BorderColorPointer_start 69 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_BorderColorPointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 70; + case 10: return 70; + case 9: return 70; + case 8: return 70; + case 7: + if (devinfo->is_haswell) { + return 69; + } else { + return 69; + } + case 6: return 69; + case 5: return 69; + case 4: + if (devinfo->is_g4x) { + return 69; + } else { + return 69; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::ChromaKey Enable */ + + +#define GEN11_SAMPLER_STATE_ChromaKeyEnable_bits 1 +#define GEN10_SAMPLER_STATE_ChromaKeyEnable_bits 1 +#define GEN9_SAMPLER_STATE_ChromaKeyEnable_bits 1 +#define GEN8_SAMPLER_STATE_ChromaKeyEnable_bits 1 +#define GEN75_SAMPLER_STATE_ChromaKeyEnable_bits 1 +#define GEN7_SAMPLER_STATE_ChromaKeyEnable_bits 1 +#define GEN6_SAMPLER_STATE_ChromaKeyEnable_bits 1 +#define GEN5_SAMPLER_STATE_ChromaKeyEnable_bits 1 +#define GEN45_SAMPLER_STATE_ChromaKeyEnable_bits 1 +#define GEN4_SAMPLER_STATE_ChromaKeyEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_ChromaKeyEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_ChromaKeyEnable_start 39 +#define GEN10_SAMPLER_STATE_ChromaKeyEnable_start 39 +#define GEN9_SAMPLER_STATE_ChromaKeyEnable_start 39 +#define GEN8_SAMPLER_STATE_ChromaKeyEnable_start 39 +#define GEN75_SAMPLER_STATE_ChromaKeyEnable_start 121 +#define GEN7_SAMPLER_STATE_ChromaKeyEnable_start 121 +#define GEN6_SAMPLER_STATE_ChromaKeyEnable_start 121 +#define GEN5_SAMPLER_STATE_ChromaKeyEnable_start 121 +#define GEN45_SAMPLER_STATE_ChromaKeyEnable_start 121 +#define GEN4_SAMPLER_STATE_ChromaKeyEnable_start 121 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_ChromaKeyEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 39; + case 10: return 39; + case 9: return 39; + case 8: return 39; + case 7: + if (devinfo->is_haswell) { + return 121; + } else { + return 121; + } + case 6: return 121; + case 5: return 121; + case 4: + if (devinfo->is_g4x) { + return 121; + } else { + return 121; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::ChromaKey Index */ + + +#define GEN11_SAMPLER_STATE_ChromaKeyIndex_bits 2 +#define GEN10_SAMPLER_STATE_ChromaKeyIndex_bits 2 +#define GEN9_SAMPLER_STATE_ChromaKeyIndex_bits 2 +#define GEN8_SAMPLER_STATE_ChromaKeyIndex_bits 2 +#define GEN75_SAMPLER_STATE_ChromaKeyIndex_bits 2 +#define GEN7_SAMPLER_STATE_ChromaKeyIndex_bits 2 +#define GEN6_SAMPLER_STATE_ChromaKeyIndex_bits 2 +#define GEN5_SAMPLER_STATE_ChromaKeyIndex_bits 2 +#define GEN45_SAMPLER_STATE_ChromaKeyIndex_bits 2 +#define GEN4_SAMPLER_STATE_ChromaKeyIndex_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_ChromaKeyIndex_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_ChromaKeyIndex_start 37 +#define GEN10_SAMPLER_STATE_ChromaKeyIndex_start 37 +#define GEN9_SAMPLER_STATE_ChromaKeyIndex_start 37 +#define GEN8_SAMPLER_STATE_ChromaKeyIndex_start 37 +#define GEN75_SAMPLER_STATE_ChromaKeyIndex_start 119 +#define GEN7_SAMPLER_STATE_ChromaKeyIndex_start 119 +#define GEN6_SAMPLER_STATE_ChromaKeyIndex_start 119 +#define GEN5_SAMPLER_STATE_ChromaKeyIndex_start 119 +#define GEN45_SAMPLER_STATE_ChromaKeyIndex_start 119 +#define GEN4_SAMPLER_STATE_ChromaKeyIndex_start 119 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_ChromaKeyIndex_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 37; + case 10: return 37; + case 9: return 37; + case 8: return 37; + case 7: + if (devinfo->is_haswell) { + return 119; + } else { + return 119; + } + case 6: return 119; + case 5: return 119; + case 4: + if (devinfo->is_g4x) { + return 119; + } else { + return 119; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::ChromaKey Mode */ + + +#define GEN11_SAMPLER_STATE_ChromaKeyMode_bits 1 +#define GEN10_SAMPLER_STATE_ChromaKeyMode_bits 1 +#define GEN9_SAMPLER_STATE_ChromaKeyMode_bits 1 +#define GEN8_SAMPLER_STATE_ChromaKeyMode_bits 1 +#define GEN75_SAMPLER_STATE_ChromaKeyMode_bits 1 +#define GEN7_SAMPLER_STATE_ChromaKeyMode_bits 1 +#define GEN6_SAMPLER_STATE_ChromaKeyMode_bits 1 +#define GEN5_SAMPLER_STATE_ChromaKeyMode_bits 1 +#define GEN45_SAMPLER_STATE_ChromaKeyMode_bits 1 +#define GEN4_SAMPLER_STATE_ChromaKeyMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_ChromaKeyMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_ChromaKeyMode_start 36 +#define GEN10_SAMPLER_STATE_ChromaKeyMode_start 36 +#define GEN9_SAMPLER_STATE_ChromaKeyMode_start 36 +#define GEN8_SAMPLER_STATE_ChromaKeyMode_start 36 +#define GEN75_SAMPLER_STATE_ChromaKeyMode_start 118 +#define GEN7_SAMPLER_STATE_ChromaKeyMode_start 118 +#define GEN6_SAMPLER_STATE_ChromaKeyMode_start 118 +#define GEN5_SAMPLER_STATE_ChromaKeyMode_start 118 +#define GEN45_SAMPLER_STATE_ChromaKeyMode_start 118 +#define GEN4_SAMPLER_STATE_ChromaKeyMode_start 118 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_ChromaKeyMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 36; + case 10: return 36; + case 9: return 36; + case 8: return 36; + case 7: + if (devinfo->is_haswell) { + return 118; + } else { + return 118; + } + case 6: return 118; + case 5: return 118; + case 4: + if (devinfo->is_g4x) { + return 118; + } else { + return 118; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::Coarse LOD Quality Mode */ + + +#define GEN11_SAMPLER_STATE_CoarseLODQualityMode_bits 5 +#define GEN10_SAMPLER_STATE_CoarseLODQualityMode_bits 5 +#define GEN9_SAMPLER_STATE_CoarseLODQualityMode_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_CoarseLODQualityMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_CoarseLODQualityMode_start 22 +#define GEN10_SAMPLER_STATE_CoarseLODQualityMode_start 22 +#define GEN9_SAMPLER_STATE_CoarseLODQualityMode_start 22 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_CoarseLODQualityMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 22; + case 10: return 22; + case 9: return 22; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::Cube Surface Control Mode */ + + +#define GEN11_SAMPLER_STATE_CubeSurfaceControlMode_bits 1 +#define GEN10_SAMPLER_STATE_CubeSurfaceControlMode_bits 1 +#define GEN9_SAMPLER_STATE_CubeSurfaceControlMode_bits 1 +#define GEN8_SAMPLER_STATE_CubeSurfaceControlMode_bits 1 +#define GEN75_SAMPLER_STATE_CubeSurfaceControlMode_bits 1 +#define GEN7_SAMPLER_STATE_CubeSurfaceControlMode_bits 1 +#define GEN6_SAMPLER_STATE_CubeSurfaceControlMode_bits 1 +#define GEN5_SAMPLER_STATE_CubeSurfaceControlMode_bits 1 +#define GEN45_SAMPLER_STATE_CubeSurfaceControlMode_bits 1 +#define GEN4_SAMPLER_STATE_CubeSurfaceControlMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_CubeSurfaceControlMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_CubeSurfaceControlMode_start 32 +#define GEN10_SAMPLER_STATE_CubeSurfaceControlMode_start 32 +#define GEN9_SAMPLER_STATE_CubeSurfaceControlMode_start 32 +#define GEN8_SAMPLER_STATE_CubeSurfaceControlMode_start 32 +#define GEN75_SAMPLER_STATE_CubeSurfaceControlMode_start 32 +#define GEN7_SAMPLER_STATE_CubeSurfaceControlMode_start 32 +#define GEN6_SAMPLER_STATE_CubeSurfaceControlMode_start 41 +#define GEN5_SAMPLER_STATE_CubeSurfaceControlMode_start 41 +#define GEN45_SAMPLER_STATE_CubeSurfaceControlMode_start 41 +#define GEN4_SAMPLER_STATE_CubeSurfaceControlMode_start 41 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_CubeSurfaceControlMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 41; + case 5: return 41; + case 4: + if (devinfo->is_g4x) { + return 41; + } else { + return 41; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::Force gather4 Behavior */ + + +#define GEN11_SAMPLER_STATE_Forcegather4Behavior_bits 1 +#define GEN10_SAMPLER_STATE_Forcegather4Behavior_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_Forcegather4Behavior_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_Forcegather4Behavior_start 69 +#define GEN10_SAMPLER_STATE_Forcegather4Behavior_start 69 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_Forcegather4Behavior_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 69; + case 10: return 69; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::LOD Clamp Magnification Mode */ + + +#define GEN11_SAMPLER_STATE_LODClampMagnificationMode_bits 1 +#define GEN10_SAMPLER_STATE_LODClampMagnificationMode_bits 1 +#define GEN9_SAMPLER_STATE_LODClampMagnificationMode_bits 1 +#define GEN8_SAMPLER_STATE_LODClampMagnificationMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_LODClampMagnificationMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_LODClampMagnificationMode_start 64 +#define GEN10_SAMPLER_STATE_LODClampMagnificationMode_start 64 +#define GEN9_SAMPLER_STATE_LODClampMagnificationMode_start 64 +#define GEN8_SAMPLER_STATE_LODClampMagnificationMode_start 64 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_LODClampMagnificationMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::LOD PreClamp Enable */ + + +#define GEN75_SAMPLER_STATE_LODPreClampEnable_bits 1 +#define GEN7_SAMPLER_STATE_LODPreClampEnable_bits 1 +#define GEN6_SAMPLER_STATE_LODPreClampEnable_bits 1 +#define GEN5_SAMPLER_STATE_LODPreClampEnable_bits 1 +#define GEN45_SAMPLER_STATE_LODPreClampEnable_bits 1 +#define GEN4_SAMPLER_STATE_LODPreClampEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_LODPreClampEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_SAMPLER_STATE_LODPreClampEnable_start 28 +#define GEN7_SAMPLER_STATE_LODPreClampEnable_start 28 +#define GEN6_SAMPLER_STATE_LODPreClampEnable_start 28 +#define GEN5_SAMPLER_STATE_LODPreClampEnable_start 28 +#define GEN45_SAMPLER_STATE_LODPreClampEnable_start 28 +#define GEN4_SAMPLER_STATE_LODPreClampEnable_start 28 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_LODPreClampEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 28; + } else { + return 28; + } + case 6: return 28; + case 5: return 28; + case 4: + if (devinfo->is_g4x) { + return 28; + } else { + return 28; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::LOD PreClamp Mode */ + + +#define GEN11_SAMPLER_STATE_LODPreClampMode_bits 2 +#define GEN10_SAMPLER_STATE_LODPreClampMode_bits 2 +#define GEN9_SAMPLER_STATE_LODPreClampMode_bits 2 +#define GEN8_SAMPLER_STATE_LODPreClampMode_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_LODPreClampMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_LODPreClampMode_start 27 +#define GEN10_SAMPLER_STATE_LODPreClampMode_start 27 +#define GEN9_SAMPLER_STATE_LODPreClampMode_start 27 +#define GEN8_SAMPLER_STATE_LODPreClampMode_start 27 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_LODPreClampMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::Mag Mode Filter */ + + +#define GEN11_SAMPLER_STATE_MagModeFilter_bits 3 +#define GEN10_SAMPLER_STATE_MagModeFilter_bits 3 +#define GEN9_SAMPLER_STATE_MagModeFilter_bits 3 +#define GEN8_SAMPLER_STATE_MagModeFilter_bits 3 +#define GEN75_SAMPLER_STATE_MagModeFilter_bits 3 +#define GEN7_SAMPLER_STATE_MagModeFilter_bits 3 +#define GEN6_SAMPLER_STATE_MagModeFilter_bits 3 +#define GEN5_SAMPLER_STATE_MagModeFilter_bits 3 +#define GEN45_SAMPLER_STATE_MagModeFilter_bits 3 +#define GEN4_SAMPLER_STATE_MagModeFilter_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_MagModeFilter_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_MagModeFilter_start 17 +#define GEN10_SAMPLER_STATE_MagModeFilter_start 17 +#define GEN9_SAMPLER_STATE_MagModeFilter_start 17 +#define GEN8_SAMPLER_STATE_MagModeFilter_start 17 +#define GEN75_SAMPLER_STATE_MagModeFilter_start 17 +#define GEN7_SAMPLER_STATE_MagModeFilter_start 17 +#define GEN6_SAMPLER_STATE_MagModeFilter_start 17 +#define GEN5_SAMPLER_STATE_MagModeFilter_start 17 +#define GEN45_SAMPLER_STATE_MagModeFilter_start 17 +#define GEN4_SAMPLER_STATE_MagModeFilter_start 17 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_MagModeFilter_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 17; + case 10: return 17; + case 9: return 17; + case 8: return 17; + case 7: + if (devinfo->is_haswell) { + return 17; + } else { + return 17; + } + case 6: return 17; + case 5: return 17; + case 4: + if (devinfo->is_g4x) { + return 17; + } else { + return 17; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::Max LOD */ + + +#define GEN11_SAMPLER_STATE_MaxLOD_bits 12 +#define GEN10_SAMPLER_STATE_MaxLOD_bits 12 +#define GEN9_SAMPLER_STATE_MaxLOD_bits 12 +#define GEN8_SAMPLER_STATE_MaxLOD_bits 12 +#define GEN75_SAMPLER_STATE_MaxLOD_bits 12 +#define GEN7_SAMPLER_STATE_MaxLOD_bits 12 +#define GEN6_SAMPLER_STATE_MaxLOD_bits 10 +#define GEN5_SAMPLER_STATE_MaxLOD_bits 10 +#define GEN45_SAMPLER_STATE_MaxLOD_bits 10 +#define GEN4_SAMPLER_STATE_MaxLOD_bits 10 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_MaxLOD_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 12; + case 10: return 12; + case 9: return 12; + case 8: return 12; + case 7: + if (devinfo->is_haswell) { + return 12; + } else { + return 12; + } + case 6: return 10; + case 5: return 10; + case 4: + if (devinfo->is_g4x) { + return 10; + } else { + return 10; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_MaxLOD_start 40 +#define GEN10_SAMPLER_STATE_MaxLOD_start 40 +#define GEN9_SAMPLER_STATE_MaxLOD_start 40 +#define GEN8_SAMPLER_STATE_MaxLOD_start 40 +#define GEN75_SAMPLER_STATE_MaxLOD_start 40 +#define GEN7_SAMPLER_STATE_MaxLOD_start 40 +#define GEN6_SAMPLER_STATE_MaxLOD_start 44 +#define GEN5_SAMPLER_STATE_MaxLOD_start 44 +#define GEN45_SAMPLER_STATE_MaxLOD_start 44 +#define GEN4_SAMPLER_STATE_MaxLOD_start 44 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_MaxLOD_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 40; + case 10: return 40; + case 9: return 40; + case 8: return 40; + case 7: + if (devinfo->is_haswell) { + return 40; + } else { + return 40; + } + case 6: return 44; + case 5: return 44; + case 4: + if (devinfo->is_g4x) { + return 44; + } else { + return 44; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::Maximum Anisotropy */ + + +#define GEN11_SAMPLER_STATE_MaximumAnisotropy_bits 3 +#define GEN10_SAMPLER_STATE_MaximumAnisotropy_bits 3 +#define GEN9_SAMPLER_STATE_MaximumAnisotropy_bits 3 +#define GEN8_SAMPLER_STATE_MaximumAnisotropy_bits 3 +#define GEN75_SAMPLER_STATE_MaximumAnisotropy_bits 3 +#define GEN7_SAMPLER_STATE_MaximumAnisotropy_bits 3 +#define GEN6_SAMPLER_STATE_MaximumAnisotropy_bits 3 +#define GEN5_SAMPLER_STATE_MaximumAnisotropy_bits 3 +#define GEN45_SAMPLER_STATE_MaximumAnisotropy_bits 3 +#define GEN4_SAMPLER_STATE_MaximumAnisotropy_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_MaximumAnisotropy_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_MaximumAnisotropy_start 115 +#define GEN10_SAMPLER_STATE_MaximumAnisotropy_start 115 +#define GEN9_SAMPLER_STATE_MaximumAnisotropy_start 115 +#define GEN8_SAMPLER_STATE_MaximumAnisotropy_start 115 +#define GEN75_SAMPLER_STATE_MaximumAnisotropy_start 115 +#define GEN7_SAMPLER_STATE_MaximumAnisotropy_start 115 +#define GEN6_SAMPLER_STATE_MaximumAnisotropy_start 115 +#define GEN5_SAMPLER_STATE_MaximumAnisotropy_start 115 +#define GEN45_SAMPLER_STATE_MaximumAnisotropy_start 115 +#define GEN4_SAMPLER_STATE_MaximumAnisotropy_start 115 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_MaximumAnisotropy_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 115; + case 10: return 115; + case 9: return 115; + case 8: return 115; + case 7: + if (devinfo->is_haswell) { + return 115; + } else { + return 115; + } + case 6: return 115; + case 5: return 115; + case 4: + if (devinfo->is_g4x) { + return 115; + } else { + return 115; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::Min LOD */ + + +#define GEN11_SAMPLER_STATE_MinLOD_bits 12 +#define GEN10_SAMPLER_STATE_MinLOD_bits 12 +#define GEN9_SAMPLER_STATE_MinLOD_bits 12 +#define GEN8_SAMPLER_STATE_MinLOD_bits 12 +#define GEN75_SAMPLER_STATE_MinLOD_bits 12 +#define GEN7_SAMPLER_STATE_MinLOD_bits 12 +#define GEN6_SAMPLER_STATE_MinLOD_bits 10 +#define GEN5_SAMPLER_STATE_MinLOD_bits 10 +#define GEN45_SAMPLER_STATE_MinLOD_bits 10 +#define GEN4_SAMPLER_STATE_MinLOD_bits 10 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_MinLOD_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 12; + case 10: return 12; + case 9: return 12; + case 8: return 12; + case 7: + if (devinfo->is_haswell) { + return 12; + } else { + return 12; + } + case 6: return 10; + case 5: return 10; + case 4: + if (devinfo->is_g4x) { + return 10; + } else { + return 10; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_MinLOD_start 52 +#define GEN10_SAMPLER_STATE_MinLOD_start 52 +#define GEN9_SAMPLER_STATE_MinLOD_start 52 +#define GEN8_SAMPLER_STATE_MinLOD_start 52 +#define GEN75_SAMPLER_STATE_MinLOD_start 52 +#define GEN7_SAMPLER_STATE_MinLOD_start 52 +#define GEN6_SAMPLER_STATE_MinLOD_start 54 +#define GEN5_SAMPLER_STATE_MinLOD_start 54 +#define GEN45_SAMPLER_STATE_MinLOD_start 54 +#define GEN4_SAMPLER_STATE_MinLOD_start 54 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_MinLOD_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 52; + case 10: return 52; + case 9: return 52; + case 8: return 52; + case 7: + if (devinfo->is_haswell) { + return 52; + } else { + return 52; + } + case 6: return 54; + case 5: return 54; + case 4: + if (devinfo->is_g4x) { + return 54; + } else { + return 54; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::Min Mode Filter */ + + +#define GEN11_SAMPLER_STATE_MinModeFilter_bits 3 +#define GEN10_SAMPLER_STATE_MinModeFilter_bits 3 +#define GEN9_SAMPLER_STATE_MinModeFilter_bits 3 +#define GEN8_SAMPLER_STATE_MinModeFilter_bits 3 +#define GEN75_SAMPLER_STATE_MinModeFilter_bits 3 +#define GEN7_SAMPLER_STATE_MinModeFilter_bits 3 +#define GEN6_SAMPLER_STATE_MinModeFilter_bits 3 +#define GEN5_SAMPLER_STATE_MinModeFilter_bits 3 +#define GEN45_SAMPLER_STATE_MinModeFilter_bits 3 +#define GEN4_SAMPLER_STATE_MinModeFilter_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_MinModeFilter_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_MinModeFilter_start 14 +#define GEN10_SAMPLER_STATE_MinModeFilter_start 14 +#define GEN9_SAMPLER_STATE_MinModeFilter_start 14 +#define GEN8_SAMPLER_STATE_MinModeFilter_start 14 +#define GEN75_SAMPLER_STATE_MinModeFilter_start 14 +#define GEN7_SAMPLER_STATE_MinModeFilter_start 14 +#define GEN6_SAMPLER_STATE_MinModeFilter_start 14 +#define GEN5_SAMPLER_STATE_MinModeFilter_start 14 +#define GEN45_SAMPLER_STATE_MinModeFilter_start 14 +#define GEN4_SAMPLER_STATE_MinModeFilter_start 14 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_MinModeFilter_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 14; + case 10: return 14; + case 9: return 14; + case 8: return 14; + case 7: + if (devinfo->is_haswell) { + return 14; + } else { + return 14; + } + case 6: return 14; + case 5: return 14; + case 4: + if (devinfo->is_g4x) { + return 14; + } else { + return 14; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::Min and Mag State Not Equal */ + + +#define GEN6_SAMPLER_STATE_MinandMagStateNotEqual_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_MinandMagStateNotEqual_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_SAMPLER_STATE_MinandMagStateNotEqual_start 27 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_MinandMagStateNotEqual_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::Mip Mode Filter */ + + +#define GEN11_SAMPLER_STATE_MipModeFilter_bits 2 +#define GEN10_SAMPLER_STATE_MipModeFilter_bits 2 +#define GEN9_SAMPLER_STATE_MipModeFilter_bits 2 +#define GEN8_SAMPLER_STATE_MipModeFilter_bits 2 +#define GEN75_SAMPLER_STATE_MipModeFilter_bits 2 +#define GEN7_SAMPLER_STATE_MipModeFilter_bits 2 +#define GEN6_SAMPLER_STATE_MipModeFilter_bits 2 +#define GEN5_SAMPLER_STATE_MipModeFilter_bits 2 +#define GEN45_SAMPLER_STATE_MipModeFilter_bits 2 +#define GEN4_SAMPLER_STATE_MipModeFilter_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_MipModeFilter_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_MipModeFilter_start 20 +#define GEN10_SAMPLER_STATE_MipModeFilter_start 20 +#define GEN9_SAMPLER_STATE_MipModeFilter_start 20 +#define GEN8_SAMPLER_STATE_MipModeFilter_start 20 +#define GEN75_SAMPLER_STATE_MipModeFilter_start 20 +#define GEN7_SAMPLER_STATE_MipModeFilter_start 20 +#define GEN6_SAMPLER_STATE_MipModeFilter_start 20 +#define GEN5_SAMPLER_STATE_MipModeFilter_start 20 +#define GEN45_SAMPLER_STATE_MipModeFilter_start 20 +#define GEN4_SAMPLER_STATE_MipModeFilter_start 20 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_MipModeFilter_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 20; + case 10: return 20; + case 9: return 20; + case 8: return 20; + case 7: + if (devinfo->is_haswell) { + return 20; + } else { + return 20; + } + case 6: return 20; + case 5: return 20; + case 4: + if (devinfo->is_g4x) { + return 20; + } else { + return 20; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::Monochrome Filter Height */ + + +#define GEN5_SAMPLER_STATE_MonochromeFilterHeight_bits 3 +#define GEN45_SAMPLER_STATE_MonochromeFilterHeight_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_MonochromeFilterHeight_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SAMPLER_STATE_MonochromeFilterHeight_start 125 +#define GEN45_SAMPLER_STATE_MonochromeFilterHeight_start 125 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_MonochromeFilterHeight_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 125; + case 4: + if (devinfo->is_g4x) { + return 125; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::Monochrome Filter Height: Reserved */ + + +#define GEN6_SAMPLER_STATE_MonochromeFilterHeightReserved_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_MonochromeFilterHeightReserved_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_SAMPLER_STATE_MonochromeFilterHeightReserved_start 125 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_MonochromeFilterHeightReserved_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 125; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::Monochrome Filter Width */ + + +#define GEN6_SAMPLER_STATE_MonochromeFilterWidth_bits 3 +#define GEN5_SAMPLER_STATE_MonochromeFilterWidth_bits 3 +#define GEN45_SAMPLER_STATE_MonochromeFilterWidth_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_MonochromeFilterWidth_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_SAMPLER_STATE_MonochromeFilterWidth_start 122 +#define GEN5_SAMPLER_STATE_MonochromeFilterWidth_start 122 +#define GEN45_SAMPLER_STATE_MonochromeFilterWidth_start 122 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_MonochromeFilterWidth_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 122; + case 5: return 122; + case 4: + if (devinfo->is_g4x) { + return 122; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::Non-normalized Coordinate Enable */ + + +#define GEN11_SAMPLER_STATE_NonnormalizedCoordinateEnable_bits 1 +#define GEN10_SAMPLER_STATE_NonnormalizedCoordinateEnable_bits 1 +#define GEN9_SAMPLER_STATE_NonnormalizedCoordinateEnable_bits 1 +#define GEN8_SAMPLER_STATE_NonnormalizedCoordinateEnable_bits 1 +#define GEN75_SAMPLER_STATE_NonnormalizedCoordinateEnable_bits 1 +#define GEN7_SAMPLER_STATE_NonnormalizedCoordinateEnable_bits 1 +#define GEN6_SAMPLER_STATE_NonnormalizedCoordinateEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_NonnormalizedCoordinateEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_NonnormalizedCoordinateEnable_start 106 +#define GEN10_SAMPLER_STATE_NonnormalizedCoordinateEnable_start 106 +#define GEN9_SAMPLER_STATE_NonnormalizedCoordinateEnable_start 106 +#define GEN8_SAMPLER_STATE_NonnormalizedCoordinateEnable_start 106 +#define GEN75_SAMPLER_STATE_NonnormalizedCoordinateEnable_start 106 +#define GEN7_SAMPLER_STATE_NonnormalizedCoordinateEnable_start 106 +#define GEN6_SAMPLER_STATE_NonnormalizedCoordinateEnable_start 96 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_NonnormalizedCoordinateEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 106; + case 10: return 106; + case 9: return 106; + case 8: return 106; + case 7: + if (devinfo->is_haswell) { + return 106; + } else { + return 106; + } + case 6: return 96; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::R Address Mag Filter Rounding Enable */ + + +#define GEN11_SAMPLER_STATE_RAddressMagFilterRoundingEnable_bits 1 +#define GEN10_SAMPLER_STATE_RAddressMagFilterRoundingEnable_bits 1 +#define GEN9_SAMPLER_STATE_RAddressMagFilterRoundingEnable_bits 1 +#define GEN8_SAMPLER_STATE_RAddressMagFilterRoundingEnable_bits 1 +#define GEN75_SAMPLER_STATE_RAddressMagFilterRoundingEnable_bits 1 +#define GEN7_SAMPLER_STATE_RAddressMagFilterRoundingEnable_bits 1 +#define GEN6_SAMPLER_STATE_RAddressMagFilterRoundingEnable_bits 1 +#define GEN5_SAMPLER_STATE_RAddressMagFilterRoundingEnable_bits 1 +#define GEN45_SAMPLER_STATE_RAddressMagFilterRoundingEnable_bits 1 +#define GEN4_SAMPLER_STATE_RAddressMagFilterRoundingEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_RAddressMagFilterRoundingEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_RAddressMagFilterRoundingEnable_start 110 +#define GEN10_SAMPLER_STATE_RAddressMagFilterRoundingEnable_start 110 +#define GEN9_SAMPLER_STATE_RAddressMagFilterRoundingEnable_start 110 +#define GEN8_SAMPLER_STATE_RAddressMagFilterRoundingEnable_start 110 +#define GEN75_SAMPLER_STATE_RAddressMagFilterRoundingEnable_start 110 +#define GEN7_SAMPLER_STATE_RAddressMagFilterRoundingEnable_start 110 +#define GEN6_SAMPLER_STATE_RAddressMagFilterRoundingEnable_start 110 +#define GEN5_SAMPLER_STATE_RAddressMagFilterRoundingEnable_start 110 +#define GEN45_SAMPLER_STATE_RAddressMagFilterRoundingEnable_start 110 +#define GEN4_SAMPLER_STATE_RAddressMagFilterRoundingEnable_start 110 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_RAddressMagFilterRoundingEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 110; + case 10: return 110; + case 9: return 110; + case 8: return 110; + case 7: + if (devinfo->is_haswell) { + return 110; + } else { + return 110; + } + case 6: return 110; + case 5: return 110; + case 4: + if (devinfo->is_g4x) { + return 110; + } else { + return 110; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::R Address Min Filter Rounding Enable */ + + +#define GEN11_SAMPLER_STATE_RAddressMinFilterRoundingEnable_bits 1 +#define GEN10_SAMPLER_STATE_RAddressMinFilterRoundingEnable_bits 1 +#define GEN9_SAMPLER_STATE_RAddressMinFilterRoundingEnable_bits 1 +#define GEN8_SAMPLER_STATE_RAddressMinFilterRoundingEnable_bits 1 +#define GEN75_SAMPLER_STATE_RAddressMinFilterRoundingEnable_bits 1 +#define GEN7_SAMPLER_STATE_RAddressMinFilterRoundingEnable_bits 1 +#define GEN6_SAMPLER_STATE_RAddressMinFilterRoundingEnable_bits 1 +#define GEN5_SAMPLER_STATE_RAddressMinFilterRoundingEnable_bits 1 +#define GEN45_SAMPLER_STATE_RAddressMinFilterRoundingEnable_bits 1 +#define GEN4_SAMPLER_STATE_RAddressMinFilterRoundingEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_RAddressMinFilterRoundingEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_RAddressMinFilterRoundingEnable_start 109 +#define GEN10_SAMPLER_STATE_RAddressMinFilterRoundingEnable_start 109 +#define GEN9_SAMPLER_STATE_RAddressMinFilterRoundingEnable_start 109 +#define GEN8_SAMPLER_STATE_RAddressMinFilterRoundingEnable_start 109 +#define GEN75_SAMPLER_STATE_RAddressMinFilterRoundingEnable_start 109 +#define GEN7_SAMPLER_STATE_RAddressMinFilterRoundingEnable_start 109 +#define GEN6_SAMPLER_STATE_RAddressMinFilterRoundingEnable_start 109 +#define GEN5_SAMPLER_STATE_RAddressMinFilterRoundingEnable_start 109 +#define GEN45_SAMPLER_STATE_RAddressMinFilterRoundingEnable_start 109 +#define GEN4_SAMPLER_STATE_RAddressMinFilterRoundingEnable_start 109 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_RAddressMinFilterRoundingEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 109; + case 10: return 109; + case 9: return 109; + case 8: return 109; + case 7: + if (devinfo->is_haswell) { + return 109; + } else { + return 109; + } + case 6: return 109; + case 5: return 109; + case 4: + if (devinfo->is_g4x) { + return 109; + } else { + return 109; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::Reduction Type */ + + +#define GEN11_SAMPLER_STATE_ReductionType_bits 2 +#define GEN10_SAMPLER_STATE_ReductionType_bits 2 +#define GEN9_SAMPLER_STATE_ReductionType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_ReductionType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_ReductionType_start 118 +#define GEN10_SAMPLER_STATE_ReductionType_start 118 +#define GEN9_SAMPLER_STATE_ReductionType_start 118 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_ReductionType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 118; + case 10: return 118; + case 9: return 118; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::Reduction Type Enable */ + + +#define GEN11_SAMPLER_STATE_ReductionTypeEnable_bits 1 +#define GEN10_SAMPLER_STATE_ReductionTypeEnable_bits 1 +#define GEN9_SAMPLER_STATE_ReductionTypeEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_ReductionTypeEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_ReductionTypeEnable_start 105 +#define GEN10_SAMPLER_STATE_ReductionTypeEnable_start 105 +#define GEN9_SAMPLER_STATE_ReductionTypeEnable_start 105 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_ReductionTypeEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 105; + case 10: return 105; + case 9: return 105; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::Return Filter Weight for Border Texels */ + + +#define GEN11_SAMPLER_STATE_ReturnFilterWeightforBorderTexels_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_ReturnFilterWeightforBorderTexels_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_ReturnFilterWeightforBorderTexels_start 67 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_ReturnFilterWeightforBorderTexels_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 67; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::Return Filter Weight for Null Texels */ + + +#define GEN11_SAMPLER_STATE_ReturnFilterWeightforNullTexels_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_ReturnFilterWeightforNullTexels_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_ReturnFilterWeightforNullTexels_start 66 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_ReturnFilterWeightforNullTexels_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 66; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::SRGB DECODE */ + + +#define GEN11_SAMPLER_STATE_SRGBDECODE_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_SRGBDECODE_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_SRGBDECODE_start 65 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_SRGBDECODE_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 65; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::Sampler Disable */ + + +#define GEN11_SAMPLER_STATE_SamplerDisable_bits 1 +#define GEN10_SAMPLER_STATE_SamplerDisable_bits 1 +#define GEN9_SAMPLER_STATE_SamplerDisable_bits 1 +#define GEN8_SAMPLER_STATE_SamplerDisable_bits 1 +#define GEN75_SAMPLER_STATE_SamplerDisable_bits 1 +#define GEN7_SAMPLER_STATE_SamplerDisable_bits 1 +#define GEN6_SAMPLER_STATE_SamplerDisable_bits 1 +#define GEN5_SAMPLER_STATE_SamplerDisable_bits 1 +#define GEN45_SAMPLER_STATE_SamplerDisable_bits 1 +#define GEN4_SAMPLER_STATE_SamplerDisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_SamplerDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_SamplerDisable_start 31 +#define GEN10_SAMPLER_STATE_SamplerDisable_start 31 +#define GEN9_SAMPLER_STATE_SamplerDisable_start 31 +#define GEN8_SAMPLER_STATE_SamplerDisable_start 31 +#define GEN75_SAMPLER_STATE_SamplerDisable_start 31 +#define GEN7_SAMPLER_STATE_SamplerDisable_start 31 +#define GEN6_SAMPLER_STATE_SamplerDisable_start 31 +#define GEN5_SAMPLER_STATE_SamplerDisable_start 31 +#define GEN45_SAMPLER_STATE_SamplerDisable_start 31 +#define GEN4_SAMPLER_STATE_SamplerDisable_start 31 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_SamplerDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 31; + case 10: return 31; + case 9: return 31; + case 8: return 31; + case 7: + if (devinfo->is_haswell) { + return 31; + } else { + return 31; + } + case 6: return 31; + case 5: return 31; + case 4: + if (devinfo->is_g4x) { + return 31; + } else { + return 31; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::Shadow Function */ + + +#define GEN11_SAMPLER_STATE_ShadowFunction_bits 3 +#define GEN10_SAMPLER_STATE_ShadowFunction_bits 3 +#define GEN9_SAMPLER_STATE_ShadowFunction_bits 3 +#define GEN8_SAMPLER_STATE_ShadowFunction_bits 3 +#define GEN75_SAMPLER_STATE_ShadowFunction_bits 3 +#define GEN7_SAMPLER_STATE_ShadowFunction_bits 3 +#define GEN6_SAMPLER_STATE_ShadowFunction_bits 3 +#define GEN5_SAMPLER_STATE_ShadowFunction_bits 3 +#define GEN45_SAMPLER_STATE_ShadowFunction_bits 3 +#define GEN4_SAMPLER_STATE_ShadowFunction_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_ShadowFunction_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_ShadowFunction_start 33 +#define GEN10_SAMPLER_STATE_ShadowFunction_start 33 +#define GEN9_SAMPLER_STATE_ShadowFunction_start 33 +#define GEN8_SAMPLER_STATE_ShadowFunction_start 33 +#define GEN75_SAMPLER_STATE_ShadowFunction_start 33 +#define GEN7_SAMPLER_STATE_ShadowFunction_start 33 +#define GEN6_SAMPLER_STATE_ShadowFunction_start 0 +#define GEN5_SAMPLER_STATE_ShadowFunction_start 0 +#define GEN45_SAMPLER_STATE_ShadowFunction_start 0 +#define GEN4_SAMPLER_STATE_ShadowFunction_start 0 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_ShadowFunction_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 33; + case 10: return 33; + case 9: return 33; + case 8: return 33; + case 7: + if (devinfo->is_haswell) { + return 33; + } else { + return 33; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::TCX Address Control Mode */ + + +#define GEN11_SAMPLER_STATE_TCXAddressControlMode_bits 3 +#define GEN10_SAMPLER_STATE_TCXAddressControlMode_bits 3 +#define GEN9_SAMPLER_STATE_TCXAddressControlMode_bits 3 +#define GEN8_SAMPLER_STATE_TCXAddressControlMode_bits 3 +#define GEN75_SAMPLER_STATE_TCXAddressControlMode_bits 3 +#define GEN7_SAMPLER_STATE_TCXAddressControlMode_bits 3 +#define GEN6_SAMPLER_STATE_TCXAddressControlMode_bits 3 +#define GEN5_SAMPLER_STATE_TCXAddressControlMode_bits 3 +#define GEN45_SAMPLER_STATE_TCXAddressControlMode_bits 3 +#define GEN4_SAMPLER_STATE_TCXAddressControlMode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_TCXAddressControlMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_TCXAddressControlMode_start 102 +#define GEN10_SAMPLER_STATE_TCXAddressControlMode_start 102 +#define GEN9_SAMPLER_STATE_TCXAddressControlMode_start 102 +#define GEN8_SAMPLER_STATE_TCXAddressControlMode_start 102 +#define GEN75_SAMPLER_STATE_TCXAddressControlMode_start 102 +#define GEN7_SAMPLER_STATE_TCXAddressControlMode_start 102 +#define GEN6_SAMPLER_STATE_TCXAddressControlMode_start 38 +#define GEN5_SAMPLER_STATE_TCXAddressControlMode_start 38 +#define GEN45_SAMPLER_STATE_TCXAddressControlMode_start 38 +#define GEN4_SAMPLER_STATE_TCXAddressControlMode_start 38 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_TCXAddressControlMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 102; + case 10: return 102; + case 9: return 102; + case 8: return 102; + case 7: + if (devinfo->is_haswell) { + return 102; + } else { + return 102; + } + case 6: return 38; + case 5: return 38; + case 4: + if (devinfo->is_g4x) { + return 38; + } else { + return 38; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::TCY Address Control Mode */ + + +#define GEN11_SAMPLER_STATE_TCYAddressControlMode_bits 3 +#define GEN10_SAMPLER_STATE_TCYAddressControlMode_bits 3 +#define GEN9_SAMPLER_STATE_TCYAddressControlMode_bits 3 +#define GEN8_SAMPLER_STATE_TCYAddressControlMode_bits 3 +#define GEN75_SAMPLER_STATE_TCYAddressControlMode_bits 3 +#define GEN7_SAMPLER_STATE_TCYAddressControlMode_bits 3 +#define GEN6_SAMPLER_STATE_TCYAddressControlMode_bits 3 +#define GEN5_SAMPLER_STATE_TCYAddressControlMode_bits 3 +#define GEN45_SAMPLER_STATE_TCYAddressControlMode_bits 3 +#define GEN4_SAMPLER_STATE_TCYAddressControlMode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_TCYAddressControlMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_TCYAddressControlMode_start 99 +#define GEN10_SAMPLER_STATE_TCYAddressControlMode_start 99 +#define GEN9_SAMPLER_STATE_TCYAddressControlMode_start 99 +#define GEN8_SAMPLER_STATE_TCYAddressControlMode_start 99 +#define GEN75_SAMPLER_STATE_TCYAddressControlMode_start 99 +#define GEN7_SAMPLER_STATE_TCYAddressControlMode_start 99 +#define GEN6_SAMPLER_STATE_TCYAddressControlMode_start 35 +#define GEN5_SAMPLER_STATE_TCYAddressControlMode_start 35 +#define GEN45_SAMPLER_STATE_TCYAddressControlMode_start 35 +#define GEN4_SAMPLER_STATE_TCYAddressControlMode_start 35 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_TCYAddressControlMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 99; + case 10: return 99; + case 9: return 99; + case 8: return 99; + case 7: + if (devinfo->is_haswell) { + return 99; + } else { + return 99; + } + case 6: return 35; + case 5: return 35; + case 4: + if (devinfo->is_g4x) { + return 35; + } else { + return 35; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::TCZ Address Control Mode */ + + +#define GEN11_SAMPLER_STATE_TCZAddressControlMode_bits 3 +#define GEN10_SAMPLER_STATE_TCZAddressControlMode_bits 3 +#define GEN9_SAMPLER_STATE_TCZAddressControlMode_bits 3 +#define GEN8_SAMPLER_STATE_TCZAddressControlMode_bits 3 +#define GEN75_SAMPLER_STATE_TCZAddressControlMode_bits 3 +#define GEN7_SAMPLER_STATE_TCZAddressControlMode_bits 3 +#define GEN6_SAMPLER_STATE_TCZAddressControlMode_bits 3 +#define GEN5_SAMPLER_STATE_TCZAddressControlMode_bits 3 +#define GEN45_SAMPLER_STATE_TCZAddressControlMode_bits 3 +#define GEN4_SAMPLER_STATE_TCZAddressControlMode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_TCZAddressControlMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_TCZAddressControlMode_start 96 +#define GEN10_SAMPLER_STATE_TCZAddressControlMode_start 96 +#define GEN9_SAMPLER_STATE_TCZAddressControlMode_start 96 +#define GEN8_SAMPLER_STATE_TCZAddressControlMode_start 96 +#define GEN75_SAMPLER_STATE_TCZAddressControlMode_start 96 +#define GEN7_SAMPLER_STATE_TCZAddressControlMode_start 96 +#define GEN6_SAMPLER_STATE_TCZAddressControlMode_start 32 +#define GEN5_SAMPLER_STATE_TCZAddressControlMode_start 32 +#define GEN45_SAMPLER_STATE_TCZAddressControlMode_start 32 +#define GEN4_SAMPLER_STATE_TCZAddressControlMode_start 32 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_TCZAddressControlMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 96; + case 10: return 96; + case 9: return 96; + case 8: return 96; + case 7: + if (devinfo->is_haswell) { + return 96; + } else { + return 96; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::Texture Border Color Mode */ + + +#define GEN11_SAMPLER_STATE_TextureBorderColorMode_bits 1 +#define GEN10_SAMPLER_STATE_TextureBorderColorMode_bits 1 +#define GEN9_SAMPLER_STATE_TextureBorderColorMode_bits 1 +#define GEN8_SAMPLER_STATE_TextureBorderColorMode_bits 1 +#define GEN75_SAMPLER_STATE_TextureBorderColorMode_bits 1 +#define GEN7_SAMPLER_STATE_TextureBorderColorMode_bits 1 +#define GEN6_SAMPLER_STATE_TextureBorderColorMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_TextureBorderColorMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_TextureBorderColorMode_start 29 +#define GEN10_SAMPLER_STATE_TextureBorderColorMode_start 29 +#define GEN9_SAMPLER_STATE_TextureBorderColorMode_start 29 +#define GEN8_SAMPLER_STATE_TextureBorderColorMode_start 29 +#define GEN75_SAMPLER_STATE_TextureBorderColorMode_start 29 +#define GEN7_SAMPLER_STATE_TextureBorderColorMode_start 29 +#define GEN6_SAMPLER_STATE_TextureBorderColorMode_start 29 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_TextureBorderColorMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::Texture LOD Bias */ + + +#define GEN11_SAMPLER_STATE_TextureLODBias_bits 13 +#define GEN10_SAMPLER_STATE_TextureLODBias_bits 13 +#define GEN9_SAMPLER_STATE_TextureLODBias_bits 13 +#define GEN8_SAMPLER_STATE_TextureLODBias_bits 13 +#define GEN75_SAMPLER_STATE_TextureLODBias_bits 13 +#define GEN7_SAMPLER_STATE_TextureLODBias_bits 13 +#define GEN6_SAMPLER_STATE_TextureLODBias_bits 11 +#define GEN5_SAMPLER_STATE_TextureLODBias_bits 11 +#define GEN45_SAMPLER_STATE_TextureLODBias_bits 11 +#define GEN4_SAMPLER_STATE_TextureLODBias_bits 11 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_TextureLODBias_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 13; + case 10: return 13; + case 9: return 13; + case 8: return 13; + case 7: + if (devinfo->is_haswell) { + return 13; + } else { + return 13; + } + case 6: return 11; + case 5: return 11; + case 4: + if (devinfo->is_g4x) { + return 11; + } else { + return 11; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_TextureLODBias_start 1 +#define GEN10_SAMPLER_STATE_TextureLODBias_start 1 +#define GEN9_SAMPLER_STATE_TextureLODBias_start 1 +#define GEN8_SAMPLER_STATE_TextureLODBias_start 1 +#define GEN75_SAMPLER_STATE_TextureLODBias_start 1 +#define GEN7_SAMPLER_STATE_TextureLODBias_start 1 +#define GEN6_SAMPLER_STATE_TextureLODBias_start 3 +#define GEN5_SAMPLER_STATE_TextureLODBias_start 3 +#define GEN45_SAMPLER_STATE_TextureLODBias_start 3 +#define GEN4_SAMPLER_STATE_TextureLODBias_start 3 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_TextureLODBias_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::Trilinear Filter Quality */ + + +#define GEN11_SAMPLER_STATE_TrilinearFilterQuality_bits 2 +#define GEN10_SAMPLER_STATE_TrilinearFilterQuality_bits 2 +#define GEN9_SAMPLER_STATE_TrilinearFilterQuality_bits 2 +#define GEN8_SAMPLER_STATE_TrilinearFilterQuality_bits 2 +#define GEN75_SAMPLER_STATE_TrilinearFilterQuality_bits 2 +#define GEN7_SAMPLER_STATE_TrilinearFilterQuality_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_TrilinearFilterQuality_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_TrilinearFilterQuality_start 107 +#define GEN10_SAMPLER_STATE_TrilinearFilterQuality_start 107 +#define GEN9_SAMPLER_STATE_TrilinearFilterQuality_start 107 +#define GEN8_SAMPLER_STATE_TrilinearFilterQuality_start 107 +#define GEN75_SAMPLER_STATE_TrilinearFilterQuality_start 107 +#define GEN7_SAMPLER_STATE_TrilinearFilterQuality_start 107 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_TrilinearFilterQuality_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 107; + case 10: return 107; + case 9: return 107; + case 8: return 107; + case 7: + if (devinfo->is_haswell) { + return 107; + } else { + return 107; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::U Address Mag Filter Rounding Enable */ + + +#define GEN11_SAMPLER_STATE_UAddressMagFilterRoundingEnable_bits 1 +#define GEN10_SAMPLER_STATE_UAddressMagFilterRoundingEnable_bits 1 +#define GEN9_SAMPLER_STATE_UAddressMagFilterRoundingEnable_bits 1 +#define GEN8_SAMPLER_STATE_UAddressMagFilterRoundingEnable_bits 1 +#define GEN75_SAMPLER_STATE_UAddressMagFilterRoundingEnable_bits 1 +#define GEN7_SAMPLER_STATE_UAddressMagFilterRoundingEnable_bits 1 +#define GEN6_SAMPLER_STATE_UAddressMagFilterRoundingEnable_bits 1 +#define GEN5_SAMPLER_STATE_UAddressMagFilterRoundingEnable_bits 1 +#define GEN45_SAMPLER_STATE_UAddressMagFilterRoundingEnable_bits 1 +#define GEN4_SAMPLER_STATE_UAddressMagFilterRoundingEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_UAddressMagFilterRoundingEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_UAddressMagFilterRoundingEnable_start 114 +#define GEN10_SAMPLER_STATE_UAddressMagFilterRoundingEnable_start 114 +#define GEN9_SAMPLER_STATE_UAddressMagFilterRoundingEnable_start 114 +#define GEN8_SAMPLER_STATE_UAddressMagFilterRoundingEnable_start 114 +#define GEN75_SAMPLER_STATE_UAddressMagFilterRoundingEnable_start 114 +#define GEN7_SAMPLER_STATE_UAddressMagFilterRoundingEnable_start 114 +#define GEN6_SAMPLER_STATE_UAddressMagFilterRoundingEnable_start 114 +#define GEN5_SAMPLER_STATE_UAddressMagFilterRoundingEnable_start 114 +#define GEN45_SAMPLER_STATE_UAddressMagFilterRoundingEnable_start 114 +#define GEN4_SAMPLER_STATE_UAddressMagFilterRoundingEnable_start 114 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_UAddressMagFilterRoundingEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 114; + case 10: return 114; + case 9: return 114; + case 8: return 114; + case 7: + if (devinfo->is_haswell) { + return 114; + } else { + return 114; + } + case 6: return 114; + case 5: return 114; + case 4: + if (devinfo->is_g4x) { + return 114; + } else { + return 114; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::U Address Min Filter Rounding Enable */ + + +#define GEN11_SAMPLER_STATE_UAddressMinFilterRoundingEnable_bits 1 +#define GEN10_SAMPLER_STATE_UAddressMinFilterRoundingEnable_bits 1 +#define GEN9_SAMPLER_STATE_UAddressMinFilterRoundingEnable_bits 1 +#define GEN8_SAMPLER_STATE_UAddressMinFilterRoundingEnable_bits 1 +#define GEN75_SAMPLER_STATE_UAddressMinFilterRoundingEnable_bits 1 +#define GEN7_SAMPLER_STATE_UAddressMinFilterRoundingEnable_bits 1 +#define GEN6_SAMPLER_STATE_UAddressMinFilterRoundingEnable_bits 1 +#define GEN5_SAMPLER_STATE_UAddressMinFilterRoundingEnable_bits 1 +#define GEN45_SAMPLER_STATE_UAddressMinFilterRoundingEnable_bits 1 +#define GEN4_SAMPLER_STATE_UAddressMinFilterRoundingEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_UAddressMinFilterRoundingEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_UAddressMinFilterRoundingEnable_start 113 +#define GEN10_SAMPLER_STATE_UAddressMinFilterRoundingEnable_start 113 +#define GEN9_SAMPLER_STATE_UAddressMinFilterRoundingEnable_start 113 +#define GEN8_SAMPLER_STATE_UAddressMinFilterRoundingEnable_start 113 +#define GEN75_SAMPLER_STATE_UAddressMinFilterRoundingEnable_start 113 +#define GEN7_SAMPLER_STATE_UAddressMinFilterRoundingEnable_start 113 +#define GEN6_SAMPLER_STATE_UAddressMinFilterRoundingEnable_start 113 +#define GEN5_SAMPLER_STATE_UAddressMinFilterRoundingEnable_start 113 +#define GEN45_SAMPLER_STATE_UAddressMinFilterRoundingEnable_start 113 +#define GEN4_SAMPLER_STATE_UAddressMinFilterRoundingEnable_start 113 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_UAddressMinFilterRoundingEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 113; + case 10: return 113; + case 9: return 113; + case 8: return 113; + case 7: + if (devinfo->is_haswell) { + return 113; + } else { + return 113; + } + case 6: return 113; + case 5: return 113; + case 4: + if (devinfo->is_g4x) { + return 113; + } else { + return 113; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::V Address Mag Filter Rounding Enable */ + + +#define GEN11_SAMPLER_STATE_VAddressMagFilterRoundingEnable_bits 1 +#define GEN10_SAMPLER_STATE_VAddressMagFilterRoundingEnable_bits 1 +#define GEN9_SAMPLER_STATE_VAddressMagFilterRoundingEnable_bits 1 +#define GEN8_SAMPLER_STATE_VAddressMagFilterRoundingEnable_bits 1 +#define GEN75_SAMPLER_STATE_VAddressMagFilterRoundingEnable_bits 1 +#define GEN7_SAMPLER_STATE_VAddressMagFilterRoundingEnable_bits 1 +#define GEN6_SAMPLER_STATE_VAddressMagFilterRoundingEnable_bits 1 +#define GEN5_SAMPLER_STATE_VAddressMagFilterRoundingEnable_bits 1 +#define GEN45_SAMPLER_STATE_VAddressMagFilterRoundingEnable_bits 1 +#define GEN4_SAMPLER_STATE_VAddressMagFilterRoundingEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_VAddressMagFilterRoundingEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_VAddressMagFilterRoundingEnable_start 112 +#define GEN10_SAMPLER_STATE_VAddressMagFilterRoundingEnable_start 112 +#define GEN9_SAMPLER_STATE_VAddressMagFilterRoundingEnable_start 112 +#define GEN8_SAMPLER_STATE_VAddressMagFilterRoundingEnable_start 112 +#define GEN75_SAMPLER_STATE_VAddressMagFilterRoundingEnable_start 112 +#define GEN7_SAMPLER_STATE_VAddressMagFilterRoundingEnable_start 112 +#define GEN6_SAMPLER_STATE_VAddressMagFilterRoundingEnable_start 112 +#define GEN5_SAMPLER_STATE_VAddressMagFilterRoundingEnable_start 112 +#define GEN45_SAMPLER_STATE_VAddressMagFilterRoundingEnable_start 112 +#define GEN4_SAMPLER_STATE_VAddressMagFilterRoundingEnable_start 112 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_VAddressMagFilterRoundingEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 112; + case 10: return 112; + case 9: return 112; + case 8: return 112; + case 7: + if (devinfo->is_haswell) { + return 112; + } else { + return 112; + } + case 6: return 112; + case 5: return 112; + case 4: + if (devinfo->is_g4x) { + return 112; + } else { + return 112; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE::V Address Min Filter Rounding Enable */ + + +#define GEN11_SAMPLER_STATE_VAddressMinFilterRoundingEnable_bits 1 +#define GEN10_SAMPLER_STATE_VAddressMinFilterRoundingEnable_bits 1 +#define GEN9_SAMPLER_STATE_VAddressMinFilterRoundingEnable_bits 1 +#define GEN8_SAMPLER_STATE_VAddressMinFilterRoundingEnable_bits 1 +#define GEN75_SAMPLER_STATE_VAddressMinFilterRoundingEnable_bits 1 +#define GEN7_SAMPLER_STATE_VAddressMinFilterRoundingEnable_bits 1 +#define GEN6_SAMPLER_STATE_VAddressMinFilterRoundingEnable_bits 1 +#define GEN5_SAMPLER_STATE_VAddressMinFilterRoundingEnable_bits 1 +#define GEN45_SAMPLER_STATE_VAddressMinFilterRoundingEnable_bits 1 +#define GEN4_SAMPLER_STATE_VAddressMinFilterRoundingEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_VAddressMinFilterRoundingEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_VAddressMinFilterRoundingEnable_start 111 +#define GEN10_SAMPLER_STATE_VAddressMinFilterRoundingEnable_start 111 +#define GEN9_SAMPLER_STATE_VAddressMinFilterRoundingEnable_start 111 +#define GEN8_SAMPLER_STATE_VAddressMinFilterRoundingEnable_start 111 +#define GEN75_SAMPLER_STATE_VAddressMinFilterRoundingEnable_start 111 +#define GEN7_SAMPLER_STATE_VAddressMinFilterRoundingEnable_start 111 +#define GEN6_SAMPLER_STATE_VAddressMinFilterRoundingEnable_start 111 +#define GEN5_SAMPLER_STATE_VAddressMinFilterRoundingEnable_start 111 +#define GEN45_SAMPLER_STATE_VAddressMinFilterRoundingEnable_start 111 +#define GEN4_SAMPLER_STATE_VAddressMinFilterRoundingEnable_start 111 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_VAddressMinFilterRoundingEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 111; + case 10: return 111; + case 9: return 111; + case 8: return 111; + case 7: + if (devinfo->is_haswell) { + return 111; + } else { + return 111; + } + case 6: return 111; + case 5: return 111; + case 4: + if (devinfo->is_g4x) { + return 111; + } else { + return 111; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE_8X8_AVS_COEFFICIENTS */ + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_length 8 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_length 8 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_length 8 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_length 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 0X Filter Coefficient[n,0] */ + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn0_bits 8 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn0_bits 8 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn0_bits 8 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn0_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn0_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn0_start 0 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn0_start 0 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn0_start 0 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn0_start 0 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn0_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 0X Filter Coefficient[n,1] */ + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn1_bits 8 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn1_bits 8 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn1_bits 8 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn1_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn1_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn1_start 16 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn1_start 16 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn1_start 16 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn1_start 16 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn1_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 0X Filter Coefficient[n,2] */ + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn2_bits 8 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn2_bits 8 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn2_bits 8 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn2_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn2_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn2_start 32 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn2_start 32 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn2_start 32 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn2_start 32 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn2_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 0X Filter Coefficient[n,3] */ + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn3_bits 8 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn3_bits 8 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn3_bits 8 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn3_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn3_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn3_start 48 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn3_start 48 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn3_start 48 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn3_start 48 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn3_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 48; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 0X Filter Coefficient[n,4] */ + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn4_bits 8 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn4_bits 8 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn4_bits 8 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn4_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn4_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn4_start 64 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn4_start 64 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn4_start 64 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn4_start 64 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn4_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 0X Filter Coefficient[n,5] */ + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn5_bits 8 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn5_bits 8 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn5_bits 8 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn5_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn5_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn5_start 80 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn5_start 80 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn5_start 80 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn5_start 80 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn5_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 80; + case 10: return 80; + case 9: return 80; + case 8: return 80; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 0X Filter Coefficient[n,6] */ + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn6_bits 8 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn6_bits 8 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn6_bits 8 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn6_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn6_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn6_start 96 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn6_start 96 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn6_start 96 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn6_start 96 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn6_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 96; + case 10: return 96; + case 9: return 96; + case 8: return 96; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 0X Filter Coefficient[n,7] */ + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn7_bits 8 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn7_bits 8 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn7_bits 8 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn7_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn7_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn7_start 112 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn7_start 112 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn7_start 112 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn7_start 112 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0XFilterCoefficientn7_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 112; + case 10: return 112; + case 9: return 112; + case 8: return 112; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 0Y Filter Coefficient[n,0] */ + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn0_bits 8 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn0_bits 8 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn0_bits 8 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn0_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn0_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn0_start 8 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn0_start 8 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn0_start 8 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn0_start 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn0_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 0Y Filter Coefficient[n,1] */ + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn1_bits 8 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn1_bits 8 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn1_bits 8 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn1_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn1_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn1_start 24 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn1_start 24 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn1_start 24 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn1_start 24 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn1_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 0Y Filter Coefficient[n,2] */ + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn2_bits 8 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn2_bits 8 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn2_bits 8 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn2_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn2_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn2_start 40 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn2_start 40 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn2_start 40 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn2_start 40 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn2_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 40; + case 10: return 40; + case 9: return 40; + case 8: return 40; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 0Y Filter Coefficient[n,3] */ + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn3_bits 8 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn3_bits 8 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn3_bits 8 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn3_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn3_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn3_start 56 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn3_start 56 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn3_start 56 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn3_start 56 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn3_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 56; + case 10: return 56; + case 9: return 56; + case 8: return 56; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 0Y Filter Coefficient[n,4] */ + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn4_bits 8 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn4_bits 8 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn4_bits 8 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn4_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn4_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn4_start 72 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn4_start 72 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn4_start 72 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn4_start 72 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn4_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 72; + case 10: return 72; + case 9: return 72; + case 8: return 72; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 0Y Filter Coefficient[n,5] */ + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn5_bits 8 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn5_bits 8 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn5_bits 8 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn5_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn5_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn5_start 88 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn5_start 88 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn5_start 88 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn5_start 88 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn5_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 88; + case 10: return 88; + case 9: return 88; + case 8: return 88; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 0Y Filter Coefficient[n,6] */ + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn6_bits 8 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn6_bits 8 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn6_bits 8 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn6_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn6_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn6_start 104 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn6_start 104 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn6_start 104 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn6_start 104 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn6_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 104; + case 10: return 104; + case 9: return 104; + case 8: return 104; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 0Y Filter Coefficient[n,7] */ + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn7_bits 8 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn7_bits 8 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn7_bits 8 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn7_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn7_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn7_start 120 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn7_start 120 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn7_start 120 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn7_start 120 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table0YFilterCoefficientn7_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 120; + case 10: return 120; + case 9: return 120; + case 8: return 120; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 1X Filter Coefficient[n,2] */ + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn2_bits 8 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn2_bits 8 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn2_bits 8 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn2_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn2_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn2_start 144 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn2_start 144 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn2_start 144 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn2_start 144 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn2_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 144; + case 10: return 144; + case 9: return 144; + case 8: return 144; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 1X Filter Coefficient[n,3] */ + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn3_bits 8 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn3_bits 8 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn3_bits 8 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn3_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn3_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn3_start 152 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn3_start 152 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn3_start 152 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn3_start 152 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn3_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 152; + case 10: return 152; + case 9: return 152; + case 8: return 152; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 1X Filter Coefficient[n,4] */ + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn4_bits 8 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn4_bits 8 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn4_bits 8 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn4_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn4_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn4_start 160 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn4_start 160 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn4_start 160 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn4_start 160 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn4_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 160; + case 10: return 160; + case 9: return 160; + case 8: return 160; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 1X Filter Coefficient[n,5] */ + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn5_bits 8 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn5_bits 8 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn5_bits 8 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn5_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn5_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn5_start 168 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn5_start 168 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn5_start 168 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn5_start 168 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1XFilterCoefficientn5_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 168; + case 10: return 168; + case 9: return 168; + case 8: return 168; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 1Y Filter Coefficient[n,2] */ + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn2_bits 8 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn2_bits 8 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn2_bits 8 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn2_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn2_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn2_start 208 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn2_start 208 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn2_start 208 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn2_start 208 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn2_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 208; + case 10: return 208; + case 9: return 208; + case 8: return 208; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 1Y Filter Coefficient[n,3] */ + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn3_bits 8 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn3_bits 8 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn3_bits 8 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn3_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn3_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn3_start 216 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn3_start 216 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn3_start 216 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn3_start 216 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn3_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 216; + case 10: return 216; + case 9: return 216; + case 8: return 216; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 1Y Filter Coefficient[n,4] */ + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn4_bits 8 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn4_bits 8 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn4_bits 8 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn4_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn4_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn4_start 224 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn4_start 224 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn4_start 224 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn4_start 224 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn4_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 224; + case 10: return 224; + case 9: return 224; + case 8: return 224; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SAMPLER_STATE_8X8_AVS_COEFFICIENTS::Table 1Y Filter Coefficient[n,5] */ + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn5_bits 8 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn5_bits 8 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn5_bits 8 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn5_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn5_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn5_start 232 +#define GEN10_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn5_start 232 +#define GEN9_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn5_start 232 +#define GEN8_SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn5_start 232 + +static inline uint32_t ATTRIBUTE_PURE +SAMPLER_STATE_8X8_AVS_COEFFICIENTS_Table1YFilterCoefficientn5_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 232; + case 10: return 232; + case 9: return 232; + case 8: return 232; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SCISSOR_RECT */ + + +#define GEN11_SCISSOR_RECT_length 2 +#define GEN10_SCISSOR_RECT_length 2 +#define GEN9_SCISSOR_RECT_length 2 +#define GEN8_SCISSOR_RECT_length 2 +#define GEN75_SCISSOR_RECT_length 2 +#define GEN7_SCISSOR_RECT_length 2 +#define GEN6_SCISSOR_RECT_length 2 +#define GEN5_SCISSOR_RECT_length 2 +#define GEN45_SCISSOR_RECT_length 2 +#define GEN4_SCISSOR_RECT_length 2 + +static inline uint32_t ATTRIBUTE_PURE +SCISSOR_RECT_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SCISSOR_RECT::Scissor Rectangle X Max */ + + +#define GEN11_SCISSOR_RECT_ScissorRectangleXMax_bits 16 +#define GEN10_SCISSOR_RECT_ScissorRectangleXMax_bits 16 +#define GEN9_SCISSOR_RECT_ScissorRectangleXMax_bits 16 +#define GEN8_SCISSOR_RECT_ScissorRectangleXMax_bits 16 +#define GEN75_SCISSOR_RECT_ScissorRectangleXMax_bits 16 +#define GEN7_SCISSOR_RECT_ScissorRectangleXMax_bits 16 +#define GEN6_SCISSOR_RECT_ScissorRectangleXMax_bits 16 +#define GEN5_SCISSOR_RECT_ScissorRectangleXMax_bits 16 +#define GEN45_SCISSOR_RECT_ScissorRectangleXMax_bits 16 +#define GEN4_SCISSOR_RECT_ScissorRectangleXMax_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +SCISSOR_RECT_ScissorRectangleXMax_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SCISSOR_RECT_ScissorRectangleXMax_start 32 +#define GEN10_SCISSOR_RECT_ScissorRectangleXMax_start 32 +#define GEN9_SCISSOR_RECT_ScissorRectangleXMax_start 32 +#define GEN8_SCISSOR_RECT_ScissorRectangleXMax_start 32 +#define GEN75_SCISSOR_RECT_ScissorRectangleXMax_start 32 +#define GEN7_SCISSOR_RECT_ScissorRectangleXMax_start 32 +#define GEN6_SCISSOR_RECT_ScissorRectangleXMax_start 32 +#define GEN5_SCISSOR_RECT_ScissorRectangleXMax_start 32 +#define GEN45_SCISSOR_RECT_ScissorRectangleXMax_start 32 +#define GEN4_SCISSOR_RECT_ScissorRectangleXMax_start 32 + +static inline uint32_t ATTRIBUTE_PURE +SCISSOR_RECT_ScissorRectangleXMax_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SCISSOR_RECT::Scissor Rectangle X Min */ + + +#define GEN11_SCISSOR_RECT_ScissorRectangleXMin_bits 16 +#define GEN10_SCISSOR_RECT_ScissorRectangleXMin_bits 16 +#define GEN9_SCISSOR_RECT_ScissorRectangleXMin_bits 16 +#define GEN8_SCISSOR_RECT_ScissorRectangleXMin_bits 16 +#define GEN75_SCISSOR_RECT_ScissorRectangleXMin_bits 16 +#define GEN7_SCISSOR_RECT_ScissorRectangleXMin_bits 16 +#define GEN6_SCISSOR_RECT_ScissorRectangleXMin_bits 16 +#define GEN5_SCISSOR_RECT_ScissorRectangleXMin_bits 16 +#define GEN45_SCISSOR_RECT_ScissorRectangleXMin_bits 16 +#define GEN4_SCISSOR_RECT_ScissorRectangleXMin_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +SCISSOR_RECT_ScissorRectangleXMin_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SCISSOR_RECT_ScissorRectangleXMin_start 0 +#define GEN10_SCISSOR_RECT_ScissorRectangleXMin_start 0 +#define GEN9_SCISSOR_RECT_ScissorRectangleXMin_start 0 +#define GEN8_SCISSOR_RECT_ScissorRectangleXMin_start 0 +#define GEN75_SCISSOR_RECT_ScissorRectangleXMin_start 0 +#define GEN7_SCISSOR_RECT_ScissorRectangleXMin_start 0 +#define GEN6_SCISSOR_RECT_ScissorRectangleXMin_start 0 +#define GEN5_SCISSOR_RECT_ScissorRectangleXMin_start 0 +#define GEN45_SCISSOR_RECT_ScissorRectangleXMin_start 0 +#define GEN4_SCISSOR_RECT_ScissorRectangleXMin_start 0 + +static inline uint32_t ATTRIBUTE_PURE +SCISSOR_RECT_ScissorRectangleXMin_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SCISSOR_RECT::Scissor Rectangle Y Max */ + + +#define GEN11_SCISSOR_RECT_ScissorRectangleYMax_bits 16 +#define GEN10_SCISSOR_RECT_ScissorRectangleYMax_bits 16 +#define GEN9_SCISSOR_RECT_ScissorRectangleYMax_bits 16 +#define GEN8_SCISSOR_RECT_ScissorRectangleYMax_bits 16 +#define GEN75_SCISSOR_RECT_ScissorRectangleYMax_bits 16 +#define GEN7_SCISSOR_RECT_ScissorRectangleYMax_bits 16 +#define GEN6_SCISSOR_RECT_ScissorRectangleYMax_bits 16 +#define GEN5_SCISSOR_RECT_ScissorRectangleYMax_bits 16 +#define GEN45_SCISSOR_RECT_ScissorRectangleYMax_bits 16 +#define GEN4_SCISSOR_RECT_ScissorRectangleYMax_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +SCISSOR_RECT_ScissorRectangleYMax_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SCISSOR_RECT_ScissorRectangleYMax_start 48 +#define GEN10_SCISSOR_RECT_ScissorRectangleYMax_start 48 +#define GEN9_SCISSOR_RECT_ScissorRectangleYMax_start 48 +#define GEN8_SCISSOR_RECT_ScissorRectangleYMax_start 48 +#define GEN75_SCISSOR_RECT_ScissorRectangleYMax_start 48 +#define GEN7_SCISSOR_RECT_ScissorRectangleYMax_start 48 +#define GEN6_SCISSOR_RECT_ScissorRectangleYMax_start 48 +#define GEN5_SCISSOR_RECT_ScissorRectangleYMax_start 48 +#define GEN45_SCISSOR_RECT_ScissorRectangleYMax_start 48 +#define GEN4_SCISSOR_RECT_ScissorRectangleYMax_start 48 + +static inline uint32_t ATTRIBUTE_PURE +SCISSOR_RECT_ScissorRectangleYMax_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 48; + case 7: + if (devinfo->is_haswell) { + return 48; + } else { + return 48; + } + case 6: return 48; + case 5: return 48; + case 4: + if (devinfo->is_g4x) { + return 48; + } else { + return 48; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SCISSOR_RECT::Scissor Rectangle Y Min */ + + +#define GEN11_SCISSOR_RECT_ScissorRectangleYMin_bits 16 +#define GEN10_SCISSOR_RECT_ScissorRectangleYMin_bits 16 +#define GEN9_SCISSOR_RECT_ScissorRectangleYMin_bits 16 +#define GEN8_SCISSOR_RECT_ScissorRectangleYMin_bits 16 +#define GEN75_SCISSOR_RECT_ScissorRectangleYMin_bits 16 +#define GEN7_SCISSOR_RECT_ScissorRectangleYMin_bits 16 +#define GEN6_SCISSOR_RECT_ScissorRectangleYMin_bits 16 +#define GEN5_SCISSOR_RECT_ScissorRectangleYMin_bits 16 +#define GEN45_SCISSOR_RECT_ScissorRectangleYMin_bits 16 +#define GEN4_SCISSOR_RECT_ScissorRectangleYMin_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +SCISSOR_RECT_ScissorRectangleYMin_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SCISSOR_RECT_ScissorRectangleYMin_start 16 +#define GEN10_SCISSOR_RECT_ScissorRectangleYMin_start 16 +#define GEN9_SCISSOR_RECT_ScissorRectangleYMin_start 16 +#define GEN8_SCISSOR_RECT_ScissorRectangleYMin_start 16 +#define GEN75_SCISSOR_RECT_ScissorRectangleYMin_start 16 +#define GEN7_SCISSOR_RECT_ScissorRectangleYMin_start 16 +#define GEN6_SCISSOR_RECT_ScissorRectangleYMin_start 16 +#define GEN5_SCISSOR_RECT_ScissorRectangleYMin_start 16 +#define GEN45_SCISSOR_RECT_ScissorRectangleYMin_start 16 +#define GEN4_SCISSOR_RECT_ScissorRectangleYMin_start 16 + +static inline uint32_t ATTRIBUTE_PURE +SCISSOR_RECT_ScissorRectangleYMin_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SCRATCH1 */ + + +#define GEN75_SCRATCH1_length 1 + +static inline uint32_t ATTRIBUTE_PURE +SCRATCH1_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SCRATCH1::L3 Atomic Disable */ + + +#define GEN75_SCRATCH1_L3AtomicDisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SCRATCH1_L3AtomicDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_SCRATCH1_L3AtomicDisable_start 27 + +static inline uint32_t ATTRIBUTE_PURE +SCRATCH1_L3AtomicDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SC_INSTDONE */ + + +#define GEN11_SC_INSTDONE_length 1 +#define GEN10_SC_INSTDONE_length 1 +#define GEN9_SC_INSTDONE_length 1 +#define GEN8_SC_INSTDONE_length 1 +#define GEN75_SC_INSTDONE_length 1 +#define GEN7_SC_INSTDONE_length 1 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SC_INSTDONE::DAPB Done */ + + +#define GEN11_SC_INSTDONE_DAPBDone_bits 1 +#define GEN10_SC_INSTDONE_DAPBDone_bits 1 +#define GEN9_SC_INSTDONE_DAPBDone_bits 1 +#define GEN8_SC_INSTDONE_DAPBDone_bits 1 +#define GEN75_SC_INSTDONE_DAPBDone_bits 1 +#define GEN7_SC_INSTDONE_DAPBDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_DAPBDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SC_INSTDONE_DAPBDone_start 12 +#define GEN10_SC_INSTDONE_DAPBDone_start 12 +#define GEN9_SC_INSTDONE_DAPBDone_start 12 +#define GEN8_SC_INSTDONE_DAPBDone_start 12 +#define GEN75_SC_INSTDONE_DAPBDone_start 12 +#define GEN7_SC_INSTDONE_DAPBDone_start 12 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_DAPBDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 12; + case 10: return 12; + case 9: return 12; + case 8: return 12; + case 7: + if (devinfo->is_haswell) { + return 12; + } else { + return 12; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SC_INSTDONE::DAPRBE Done */ + + +#define GEN11_SC_INSTDONE_DAPRBEDone_bits 1 +#define GEN10_SC_INSTDONE_DAPRBEDone_bits 1 +#define GEN9_SC_INSTDONE_DAPRBEDone_bits 1 +#define GEN8_SC_INSTDONE_DAPRBEDone_bits 1 +#define GEN75_SC_INSTDONE_DAPRBEDone_bits 1 +#define GEN7_SC_INSTDONE_DAPRBEDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_DAPRBEDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SC_INSTDONE_DAPRBEDone_start 13 +#define GEN10_SC_INSTDONE_DAPRBEDone_start 13 +#define GEN9_SC_INSTDONE_DAPRBEDone_start 13 +#define GEN8_SC_INSTDONE_DAPRBEDone_start 13 +#define GEN75_SC_INSTDONE_DAPRBEDone_start 13 +#define GEN7_SC_INSTDONE_DAPRBEDone_start 13 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_DAPRBEDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 13; + case 10: return 13; + case 9: return 13; + case 8: return 13; + case 7: + if (devinfo->is_haswell) { + return 13; + } else { + return 13; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SC_INSTDONE::DC0 Done */ + + +#define GEN11_SC_INSTDONE_DC0Done_bits 1 +#define GEN10_SC_INSTDONE_DC0Done_bits 1 +#define GEN9_SC_INSTDONE_DC0Done_bits 1 +#define GEN8_SC_INSTDONE_DC0Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_DC0Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SC_INSTDONE_DC0Done_start 16 +#define GEN10_SC_INSTDONE_DC0Done_start 16 +#define GEN9_SC_INSTDONE_DC0Done_start 16 +#define GEN8_SC_INSTDONE_DC0Done_start 16 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_DC0Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SC_INSTDONE::DC1 Done */ + + +#define GEN11_SC_INSTDONE_DC1Done_bits 1 +#define GEN10_SC_INSTDONE_DC1Done_bits 1 +#define GEN9_SC_INSTDONE_DC1Done_bits 1 +#define GEN8_SC_INSTDONE_DC1Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_DC1Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SC_INSTDONE_DC1Done_start 17 +#define GEN10_SC_INSTDONE_DC1Done_start 17 +#define GEN9_SC_INSTDONE_DC1Done_start 17 +#define GEN8_SC_INSTDONE_DC1Done_start 17 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_DC1Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 17; + case 10: return 17; + case 9: return 17; + case 8: return 17; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SC_INSTDONE::DC2 Done */ + + +#define GEN11_SC_INSTDONE_DC2Done_bits 1 +#define GEN10_SC_INSTDONE_DC2Done_bits 1 +#define GEN9_SC_INSTDONE_DC2Done_bits 1 +#define GEN8_SC_INSTDONE_DC2Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_DC2Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SC_INSTDONE_DC2Done_start 18 +#define GEN10_SC_INSTDONE_DC2Done_start 18 +#define GEN9_SC_INSTDONE_DC2Done_start 18 +#define GEN8_SC_INSTDONE_DC2Done_start 18 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_DC2Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 18; + case 10: return 18; + case 9: return 18; + case 8: return 18; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SC_INSTDONE::DC3 Done */ + + +#define GEN11_SC_INSTDONE_DC3Done_bits 1 +#define GEN10_SC_INSTDONE_DC3Done_bits 1 +#define GEN9_SC_INSTDONE_DC3Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_DC3Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SC_INSTDONE_DC3Done_start 19 +#define GEN10_SC_INSTDONE_DC3Done_start 19 +#define GEN9_SC_INSTDONE_DC3Done_start 19 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_DC3Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 19; + case 10: return 19; + case 9: return 19; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SC_INSTDONE::GW0 Done */ + + +#define GEN11_SC_INSTDONE_GW0Done_bits 1 +#define GEN10_SC_INSTDONE_GW0Done_bits 1 +#define GEN9_SC_INSTDONE_GW0Done_bits 1 +#define GEN8_SC_INSTDONE_GW0Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_GW0Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SC_INSTDONE_GW0Done_start 20 +#define GEN10_SC_INSTDONE_GW0Done_start 20 +#define GEN9_SC_INSTDONE_GW0Done_start 20 +#define GEN8_SC_INSTDONE_GW0Done_start 20 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_GW0Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 20; + case 10: return 20; + case 9: return 20; + case 8: return 20; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SC_INSTDONE::GW1 Done */ + + +#define GEN11_SC_INSTDONE_GW1Done_bits 1 +#define GEN10_SC_INSTDONE_GW1Done_bits 1 +#define GEN9_SC_INSTDONE_GW1Done_bits 1 +#define GEN8_SC_INSTDONE_GW1Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_GW1Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SC_INSTDONE_GW1Done_start 21 +#define GEN10_SC_INSTDONE_GW1Done_start 21 +#define GEN9_SC_INSTDONE_GW1Done_start 21 +#define GEN8_SC_INSTDONE_GW1Done_start 21 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_GW1Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 21; + case 10: return 21; + case 9: return 21; + case 8: return 21; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SC_INSTDONE::GW2 Done */ + + +#define GEN11_SC_INSTDONE_GW2Done_bits 1 +#define GEN10_SC_INSTDONE_GW2Done_bits 1 +#define GEN9_SC_INSTDONE_GW2Done_bits 1 +#define GEN8_SC_INSTDONE_GW2Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_GW2Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SC_INSTDONE_GW2Done_start 22 +#define GEN10_SC_INSTDONE_GW2Done_start 22 +#define GEN9_SC_INSTDONE_GW2Done_start 22 +#define GEN8_SC_INSTDONE_GW2Done_start 22 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_GW2Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 22; + case 10: return 22; + case 9: return 22; + case 8: return 22; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SC_INSTDONE::GW3 Done */ + + +#define GEN11_SC_INSTDONE_GW3Done_bits 1 +#define GEN10_SC_INSTDONE_GW3Done_bits 1 +#define GEN9_SC_INSTDONE_GW3Done_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_GW3Done_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SC_INSTDONE_GW3Done_start 23 +#define GEN10_SC_INSTDONE_GW3Done_start 23 +#define GEN9_SC_INSTDONE_GW3Done_start 23 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_GW3Done_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SC_INSTDONE::HIZ Done */ + + +#define GEN11_SC_INSTDONE_HIZDone_bits 1 +#define GEN10_SC_INSTDONE_HIZDone_bits 1 +#define GEN9_SC_INSTDONE_HIZDone_bits 1 +#define GEN8_SC_INSTDONE_HIZDone_bits 1 +#define GEN75_SC_INSTDONE_HIZDone_bits 1 +#define GEN7_SC_INSTDONE_HIZDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_HIZDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SC_INSTDONE_HIZDone_start 3 +#define GEN10_SC_INSTDONE_HIZDone_start 3 +#define GEN9_SC_INSTDONE_HIZDone_start 3 +#define GEN8_SC_INSTDONE_HIZDone_start 3 +#define GEN75_SC_INSTDONE_HIZDone_start 3 +#define GEN7_SC_INSTDONE_HIZDone_start 3 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_HIZDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SC_INSTDONE::IECP Done */ + + +#define GEN7_SC_INSTDONE_IECPDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_IECPDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN7_SC_INSTDONE_IECPDone_start 14 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_IECPDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 14; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SC_INSTDONE::IZ Done */ + + +#define GEN11_SC_INSTDONE_IZDone_bits 1 +#define GEN10_SC_INSTDONE_IZDone_bits 1 +#define GEN9_SC_INSTDONE_IZDone_bits 1 +#define GEN8_SC_INSTDONE_IZDone_bits 1 +#define GEN75_SC_INSTDONE_IZDone_bits 1 +#define GEN7_SC_INSTDONE_IZDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_IZDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SC_INSTDONE_IZDone_start 5 +#define GEN10_SC_INSTDONE_IZDone_start 5 +#define GEN9_SC_INSTDONE_IZDone_start 5 +#define GEN8_SC_INSTDONE_IZDone_start 5 +#define GEN75_SC_INSTDONE_IZDone_start 5 +#define GEN7_SC_INSTDONE_IZDone_start 5 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_IZDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 5; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SC_INSTDONE::RCC Done */ + + +#define GEN11_SC_INSTDONE_RCCDone_bits 1 +#define GEN10_SC_INSTDONE_RCCDone_bits 1 +#define GEN9_SC_INSTDONE_RCCDone_bits 1 +#define GEN8_SC_INSTDONE_RCCDone_bits 1 +#define GEN75_SC_INSTDONE_RCCDone_bits 1 +#define GEN7_SC_INSTDONE_RCCDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_RCCDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SC_INSTDONE_RCCDone_start 9 +#define GEN10_SC_INSTDONE_RCCDone_start 9 +#define GEN9_SC_INSTDONE_RCCDone_start 9 +#define GEN8_SC_INSTDONE_RCCDone_start 9 +#define GEN75_SC_INSTDONE_RCCDone_start 9 +#define GEN7_SC_INSTDONE_RCCDone_start 9 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_RCCDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 9; + case 10: return 9; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 9; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SC_INSTDONE::RCPBE Done */ + + +#define GEN11_SC_INSTDONE_RCPBEDone_bits 1 +#define GEN10_SC_INSTDONE_RCPBEDone_bits 1 +#define GEN9_SC_INSTDONE_RCPBEDone_bits 1 +#define GEN8_SC_INSTDONE_RCPBEDone_bits 1 +#define GEN75_SC_INSTDONE_RCPBEDone_bits 1 +#define GEN7_SC_INSTDONE_RCPBEDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_RCPBEDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SC_INSTDONE_RCPBEDone_start 10 +#define GEN10_SC_INSTDONE_RCPBEDone_start 10 +#define GEN9_SC_INSTDONE_RCPBEDone_start 10 +#define GEN8_SC_INSTDONE_RCPBEDone_start 10 +#define GEN75_SC_INSTDONE_RCPBEDone_start 10 +#define GEN7_SC_INSTDONE_RCPBEDone_start 10 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_RCPBEDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 10; + case 10: return 10; + case 9: return 10; + case 8: return 10; + case 7: + if (devinfo->is_haswell) { + return 10; + } else { + return 10; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SC_INSTDONE::RCPFE Done */ + + +#define GEN11_SC_INSTDONE_RCPFEDone_bits 1 +#define GEN10_SC_INSTDONE_RCPFEDone_bits 1 +#define GEN9_SC_INSTDONE_RCPFEDone_bits 1 +#define GEN8_SC_INSTDONE_RCPFEDone_bits 1 +#define GEN75_SC_INSTDONE_RCPFEDone_bits 1 +#define GEN7_SC_INSTDONE_RCPFEDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_RCPFEDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SC_INSTDONE_RCPFEDone_start 11 +#define GEN10_SC_INSTDONE_RCPFEDone_start 11 +#define GEN9_SC_INSTDONE_RCPFEDone_start 11 +#define GEN8_SC_INSTDONE_RCPFEDone_start 11 +#define GEN75_SC_INSTDONE_RCPFEDone_start 11 +#define GEN7_SC_INSTDONE_RCPFEDone_start 11 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_RCPFEDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 11; + } else { + return 11; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SC_INSTDONE::RCZ Done */ + + +#define GEN11_SC_INSTDONE_RCZDone_bits 1 +#define GEN10_SC_INSTDONE_RCZDone_bits 1 +#define GEN9_SC_INSTDONE_RCZDone_bits 1 +#define GEN8_SC_INSTDONE_RCZDone_bits 1 +#define GEN75_SC_INSTDONE_RCZDone_bits 1 +#define GEN7_SC_INSTDONE_RCZDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_RCZDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SC_INSTDONE_RCZDone_start 8 +#define GEN10_SC_INSTDONE_RCZDone_start 8 +#define GEN9_SC_INSTDONE_RCZDone_start 8 +#define GEN8_SC_INSTDONE_RCZDone_start 8 +#define GEN75_SC_INSTDONE_RCZDone_start 8 +#define GEN7_SC_INSTDONE_RCZDone_start 8 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_RCZDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SC_INSTDONE::SARB Done */ + + +#define GEN11_SC_INSTDONE_SARBDone_bits 1 +#define GEN10_SC_INSTDONE_SARBDone_bits 1 +#define GEN9_SC_INSTDONE_SARBDone_bits 1 +#define GEN8_SC_INSTDONE_SARBDone_bits 1 +#define GEN75_SC_INSTDONE_SARBDone_bits 1 +#define GEN7_SC_INSTDONE_SARBDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_SARBDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SC_INSTDONE_SARBDone_start 15 +#define GEN10_SC_INSTDONE_SARBDone_start 15 +#define GEN9_SC_INSTDONE_SARBDone_start 15 +#define GEN8_SC_INSTDONE_SARBDone_start 15 +#define GEN75_SC_INSTDONE_SARBDone_start 15 +#define GEN7_SC_INSTDONE_SARBDone_start 15 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_SARBDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 15; + case 10: return 15; + case 9: return 15; + case 8: return 15; + case 7: + if (devinfo->is_haswell) { + return 15; + } else { + return 15; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SC_INSTDONE::SBE Done */ + + +#define GEN11_SC_INSTDONE_SBEDone_bits 1 +#define GEN10_SC_INSTDONE_SBEDone_bits 1 +#define GEN9_SC_INSTDONE_SBEDone_bits 1 +#define GEN8_SC_INSTDONE_SBEDone_bits 1 +#define GEN75_SC_INSTDONE_SBEDone_bits 1 +#define GEN7_SC_INSTDONE_SBEDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_SBEDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SC_INSTDONE_SBEDone_start 6 +#define GEN10_SC_INSTDONE_SBEDone_start 6 +#define GEN9_SC_INSTDONE_SBEDone_start 6 +#define GEN8_SC_INSTDONE_SBEDone_start 6 +#define GEN75_SC_INSTDONE_SBEDone_start 6 +#define GEN7_SC_INSTDONE_SBEDone_start 6 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_SBEDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SC_INSTDONE::SFBE Done */ + + +#define GEN11_SC_INSTDONE_SFBEDone_bits 1 +#define GEN10_SC_INSTDONE_SFBEDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_SFBEDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SC_INSTDONE_SFBEDone_start 25 +#define GEN10_SC_INSTDONE_SFBEDone_start 25 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_SFBEDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 25; + case 10: return 25; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SC_INSTDONE::STC Done */ + + +#define GEN11_SC_INSTDONE_STCDone_bits 1 +#define GEN10_SC_INSTDONE_STCDone_bits 1 +#define GEN9_SC_INSTDONE_STCDone_bits 1 +#define GEN8_SC_INSTDONE_STCDone_bits 1 +#define GEN75_SC_INSTDONE_STCDone_bits 1 +#define GEN7_SC_INSTDONE_STCDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_STCDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SC_INSTDONE_STCDone_start 4 +#define GEN10_SC_INSTDONE_STCDone_start 4 +#define GEN9_SC_INSTDONE_STCDone_start 4 +#define GEN8_SC_INSTDONE_STCDone_start 4 +#define GEN75_SC_INSTDONE_STCDone_start 4 +#define GEN7_SC_INSTDONE_STCDone_start 4 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_STCDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SC_INSTDONE::SVL Done */ + + +#define GEN11_SC_INSTDONE_SVLDone_bits 1 +#define GEN10_SC_INSTDONE_SVLDone_bits 1 +#define GEN9_SC_INSTDONE_SVLDone_bits 1 +#define GEN8_SC_INSTDONE_SVLDone_bits 1 +#define GEN75_SC_INSTDONE_SVLDone_bits 1 +#define GEN7_SC_INSTDONE_SVLDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_SVLDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SC_INSTDONE_SVLDone_start 0 +#define GEN10_SC_INSTDONE_SVLDone_start 0 +#define GEN9_SC_INSTDONE_SVLDone_start 0 +#define GEN8_SC_INSTDONE_SVLDone_start 0 +#define GEN75_SC_INSTDONE_SVLDone_start 0 +#define GEN7_SC_INSTDONE_SVLDone_start 0 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_SVLDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SC_INSTDONE::TDC Done */ + + +#define GEN11_SC_INSTDONE_TDCDone_bits 1 +#define GEN10_SC_INSTDONE_TDCDone_bits 1 +#define GEN9_SC_INSTDONE_TDCDone_bits 1 +#define GEN8_SC_INSTDONE_TDCDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_TDCDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SC_INSTDONE_TDCDone_start 24 +#define GEN10_SC_INSTDONE_TDCDone_start 24 +#define GEN9_SC_INSTDONE_TDCDone_start 24 +#define GEN8_SC_INSTDONE_TDCDone_start 24 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_TDCDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SC_INSTDONE::VSC Done */ + + +#define GEN7_SC_INSTDONE_VSCDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_VSCDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN7_SC_INSTDONE_VSCDone_start 16 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_VSCDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SC_INSTDONE::WMBE Done */ + + +#define GEN11_SC_INSTDONE_WMBEDone_bits 1 +#define GEN10_SC_INSTDONE_WMBEDone_bits 1 +#define GEN9_SC_INSTDONE_WMBEDone_bits 1 +#define GEN8_SC_INSTDONE_WMBEDone_bits 1 +#define GEN75_SC_INSTDONE_WMBEDone_bits 1 +#define GEN7_SC_INSTDONE_WMBEDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_WMBEDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SC_INSTDONE_WMBEDone_start 2 +#define GEN10_SC_INSTDONE_WMBEDone_start 2 +#define GEN9_SC_INSTDONE_WMBEDone_start 2 +#define GEN8_SC_INSTDONE_WMBEDone_start 2 +#define GEN75_SC_INSTDONE_WMBEDone_start 2 +#define GEN7_SC_INSTDONE_WMBEDone_start 2 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_WMBEDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SC_INSTDONE::WMFE Done */ + + +#define GEN11_SC_INSTDONE_WMFEDone_bits 1 +#define GEN10_SC_INSTDONE_WMFEDone_bits 1 +#define GEN9_SC_INSTDONE_WMFEDone_bits 1 +#define GEN8_SC_INSTDONE_WMFEDone_bits 1 +#define GEN75_SC_INSTDONE_WMFEDone_bits 1 +#define GEN7_SC_INSTDONE_WMFEDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_WMFEDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SC_INSTDONE_WMFEDone_start 1 +#define GEN10_SC_INSTDONE_WMFEDone_start 1 +#define GEN9_SC_INSTDONE_WMFEDone_start 1 +#define GEN8_SC_INSTDONE_WMFEDone_start 1 +#define GEN75_SC_INSTDONE_WMFEDone_start 1 +#define GEN7_SC_INSTDONE_WMFEDone_start 1 + +static inline uint32_t ATTRIBUTE_PURE +SC_INSTDONE_WMFEDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_CLIP_VIEWPORT */ + + +#define GEN11_SF_CLIP_VIEWPORT_length 16 +#define GEN10_SF_CLIP_VIEWPORT_length 16 +#define GEN9_SF_CLIP_VIEWPORT_length 16 +#define GEN8_SF_CLIP_VIEWPORT_length 16 +#define GEN75_SF_CLIP_VIEWPORT_length 16 +#define GEN7_SF_CLIP_VIEWPORT_length 16 + +static inline uint32_t ATTRIBUTE_PURE +SF_CLIP_VIEWPORT_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_CLIP_VIEWPORT::Viewport Matrix Element m00 */ + + +#define GEN11_SF_CLIP_VIEWPORT_ViewportMatrixElementm00_bits 32 +#define GEN10_SF_CLIP_VIEWPORT_ViewportMatrixElementm00_bits 32 +#define GEN9_SF_CLIP_VIEWPORT_ViewportMatrixElementm00_bits 32 +#define GEN8_SF_CLIP_VIEWPORT_ViewportMatrixElementm00_bits 32 +#define GEN75_SF_CLIP_VIEWPORT_ViewportMatrixElementm00_bits 32 +#define GEN7_SF_CLIP_VIEWPORT_ViewportMatrixElementm00_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SF_CLIP_VIEWPORT_ViewportMatrixElementm00_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SF_CLIP_VIEWPORT_ViewportMatrixElementm00_start 0 +#define GEN10_SF_CLIP_VIEWPORT_ViewportMatrixElementm00_start 0 +#define GEN9_SF_CLIP_VIEWPORT_ViewportMatrixElementm00_start 0 +#define GEN8_SF_CLIP_VIEWPORT_ViewportMatrixElementm00_start 0 +#define GEN75_SF_CLIP_VIEWPORT_ViewportMatrixElementm00_start 0 +#define GEN7_SF_CLIP_VIEWPORT_ViewportMatrixElementm00_start 0 + +static inline uint32_t ATTRIBUTE_PURE +SF_CLIP_VIEWPORT_ViewportMatrixElementm00_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_CLIP_VIEWPORT::Viewport Matrix Element m11 */ + + +#define GEN11_SF_CLIP_VIEWPORT_ViewportMatrixElementm11_bits 32 +#define GEN10_SF_CLIP_VIEWPORT_ViewportMatrixElementm11_bits 32 +#define GEN9_SF_CLIP_VIEWPORT_ViewportMatrixElementm11_bits 32 +#define GEN8_SF_CLIP_VIEWPORT_ViewportMatrixElementm11_bits 32 +#define GEN75_SF_CLIP_VIEWPORT_ViewportMatrixElementm11_bits 32 +#define GEN7_SF_CLIP_VIEWPORT_ViewportMatrixElementm11_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SF_CLIP_VIEWPORT_ViewportMatrixElementm11_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SF_CLIP_VIEWPORT_ViewportMatrixElementm11_start 32 +#define GEN10_SF_CLIP_VIEWPORT_ViewportMatrixElementm11_start 32 +#define GEN9_SF_CLIP_VIEWPORT_ViewportMatrixElementm11_start 32 +#define GEN8_SF_CLIP_VIEWPORT_ViewportMatrixElementm11_start 32 +#define GEN75_SF_CLIP_VIEWPORT_ViewportMatrixElementm11_start 32 +#define GEN7_SF_CLIP_VIEWPORT_ViewportMatrixElementm11_start 32 + +static inline uint32_t ATTRIBUTE_PURE +SF_CLIP_VIEWPORT_ViewportMatrixElementm11_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_CLIP_VIEWPORT::Viewport Matrix Element m22 */ + + +#define GEN11_SF_CLIP_VIEWPORT_ViewportMatrixElementm22_bits 32 +#define GEN10_SF_CLIP_VIEWPORT_ViewportMatrixElementm22_bits 32 +#define GEN9_SF_CLIP_VIEWPORT_ViewportMatrixElementm22_bits 32 +#define GEN8_SF_CLIP_VIEWPORT_ViewportMatrixElementm22_bits 32 +#define GEN75_SF_CLIP_VIEWPORT_ViewportMatrixElementm22_bits 32 +#define GEN7_SF_CLIP_VIEWPORT_ViewportMatrixElementm22_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SF_CLIP_VIEWPORT_ViewportMatrixElementm22_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SF_CLIP_VIEWPORT_ViewportMatrixElementm22_start 64 +#define GEN10_SF_CLIP_VIEWPORT_ViewportMatrixElementm22_start 64 +#define GEN9_SF_CLIP_VIEWPORT_ViewportMatrixElementm22_start 64 +#define GEN8_SF_CLIP_VIEWPORT_ViewportMatrixElementm22_start 64 +#define GEN75_SF_CLIP_VIEWPORT_ViewportMatrixElementm22_start 64 +#define GEN7_SF_CLIP_VIEWPORT_ViewportMatrixElementm22_start 64 + +static inline uint32_t ATTRIBUTE_PURE +SF_CLIP_VIEWPORT_ViewportMatrixElementm22_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_CLIP_VIEWPORT::Viewport Matrix Element m30 */ + + +#define GEN11_SF_CLIP_VIEWPORT_ViewportMatrixElementm30_bits 32 +#define GEN10_SF_CLIP_VIEWPORT_ViewportMatrixElementm30_bits 32 +#define GEN9_SF_CLIP_VIEWPORT_ViewportMatrixElementm30_bits 32 +#define GEN8_SF_CLIP_VIEWPORT_ViewportMatrixElementm30_bits 32 +#define GEN75_SF_CLIP_VIEWPORT_ViewportMatrixElementm30_bits 32 +#define GEN7_SF_CLIP_VIEWPORT_ViewportMatrixElementm30_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SF_CLIP_VIEWPORT_ViewportMatrixElementm30_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SF_CLIP_VIEWPORT_ViewportMatrixElementm30_start 96 +#define GEN10_SF_CLIP_VIEWPORT_ViewportMatrixElementm30_start 96 +#define GEN9_SF_CLIP_VIEWPORT_ViewportMatrixElementm30_start 96 +#define GEN8_SF_CLIP_VIEWPORT_ViewportMatrixElementm30_start 96 +#define GEN75_SF_CLIP_VIEWPORT_ViewportMatrixElementm30_start 96 +#define GEN7_SF_CLIP_VIEWPORT_ViewportMatrixElementm30_start 96 + +static inline uint32_t ATTRIBUTE_PURE +SF_CLIP_VIEWPORT_ViewportMatrixElementm30_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 96; + case 10: return 96; + case 9: return 96; + case 8: return 96; + case 7: + if (devinfo->is_haswell) { + return 96; + } else { + return 96; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_CLIP_VIEWPORT::Viewport Matrix Element m31 */ + + +#define GEN11_SF_CLIP_VIEWPORT_ViewportMatrixElementm31_bits 32 +#define GEN10_SF_CLIP_VIEWPORT_ViewportMatrixElementm31_bits 32 +#define GEN9_SF_CLIP_VIEWPORT_ViewportMatrixElementm31_bits 32 +#define GEN8_SF_CLIP_VIEWPORT_ViewportMatrixElementm31_bits 32 +#define GEN75_SF_CLIP_VIEWPORT_ViewportMatrixElementm31_bits 32 +#define GEN7_SF_CLIP_VIEWPORT_ViewportMatrixElementm31_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SF_CLIP_VIEWPORT_ViewportMatrixElementm31_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SF_CLIP_VIEWPORT_ViewportMatrixElementm31_start 128 +#define GEN10_SF_CLIP_VIEWPORT_ViewportMatrixElementm31_start 128 +#define GEN9_SF_CLIP_VIEWPORT_ViewportMatrixElementm31_start 128 +#define GEN8_SF_CLIP_VIEWPORT_ViewportMatrixElementm31_start 128 +#define GEN75_SF_CLIP_VIEWPORT_ViewportMatrixElementm31_start 128 +#define GEN7_SF_CLIP_VIEWPORT_ViewportMatrixElementm31_start 128 + +static inline uint32_t ATTRIBUTE_PURE +SF_CLIP_VIEWPORT_ViewportMatrixElementm31_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 128; + case 10: return 128; + case 9: return 128; + case 8: return 128; + case 7: + if (devinfo->is_haswell) { + return 128; + } else { + return 128; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_CLIP_VIEWPORT::Viewport Matrix Element m32 */ + + +#define GEN11_SF_CLIP_VIEWPORT_ViewportMatrixElementm32_bits 32 +#define GEN10_SF_CLIP_VIEWPORT_ViewportMatrixElementm32_bits 32 +#define GEN9_SF_CLIP_VIEWPORT_ViewportMatrixElementm32_bits 32 +#define GEN8_SF_CLIP_VIEWPORT_ViewportMatrixElementm32_bits 32 +#define GEN75_SF_CLIP_VIEWPORT_ViewportMatrixElementm32_bits 32 +#define GEN7_SF_CLIP_VIEWPORT_ViewportMatrixElementm32_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SF_CLIP_VIEWPORT_ViewportMatrixElementm32_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SF_CLIP_VIEWPORT_ViewportMatrixElementm32_start 160 +#define GEN10_SF_CLIP_VIEWPORT_ViewportMatrixElementm32_start 160 +#define GEN9_SF_CLIP_VIEWPORT_ViewportMatrixElementm32_start 160 +#define GEN8_SF_CLIP_VIEWPORT_ViewportMatrixElementm32_start 160 +#define GEN75_SF_CLIP_VIEWPORT_ViewportMatrixElementm32_start 160 +#define GEN7_SF_CLIP_VIEWPORT_ViewportMatrixElementm32_start 160 + +static inline uint32_t ATTRIBUTE_PURE +SF_CLIP_VIEWPORT_ViewportMatrixElementm32_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 160; + case 10: return 160; + case 9: return 160; + case 8: return 160; + case 7: + if (devinfo->is_haswell) { + return 160; + } else { + return 160; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_CLIP_VIEWPORT::X Max Clip Guardband */ + + +#define GEN11_SF_CLIP_VIEWPORT_XMaxClipGuardband_bits 32 +#define GEN10_SF_CLIP_VIEWPORT_XMaxClipGuardband_bits 32 +#define GEN9_SF_CLIP_VIEWPORT_XMaxClipGuardband_bits 32 +#define GEN8_SF_CLIP_VIEWPORT_XMaxClipGuardband_bits 32 +#define GEN75_SF_CLIP_VIEWPORT_XMaxClipGuardband_bits 32 +#define GEN7_SF_CLIP_VIEWPORT_XMaxClipGuardband_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SF_CLIP_VIEWPORT_XMaxClipGuardband_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SF_CLIP_VIEWPORT_XMaxClipGuardband_start 288 +#define GEN10_SF_CLIP_VIEWPORT_XMaxClipGuardband_start 288 +#define GEN9_SF_CLIP_VIEWPORT_XMaxClipGuardband_start 288 +#define GEN8_SF_CLIP_VIEWPORT_XMaxClipGuardband_start 288 +#define GEN75_SF_CLIP_VIEWPORT_XMaxClipGuardband_start 288 +#define GEN7_SF_CLIP_VIEWPORT_XMaxClipGuardband_start 288 + +static inline uint32_t ATTRIBUTE_PURE +SF_CLIP_VIEWPORT_XMaxClipGuardband_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 288; + case 10: return 288; + case 9: return 288; + case 8: return 288; + case 7: + if (devinfo->is_haswell) { + return 288; + } else { + return 288; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_CLIP_VIEWPORT::X Max ViewPort */ + + +#define GEN11_SF_CLIP_VIEWPORT_XMaxViewPort_bits 32 +#define GEN10_SF_CLIP_VIEWPORT_XMaxViewPort_bits 32 +#define GEN9_SF_CLIP_VIEWPORT_XMaxViewPort_bits 32 +#define GEN8_SF_CLIP_VIEWPORT_XMaxViewPort_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SF_CLIP_VIEWPORT_XMaxViewPort_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SF_CLIP_VIEWPORT_XMaxViewPort_start 416 +#define GEN10_SF_CLIP_VIEWPORT_XMaxViewPort_start 416 +#define GEN9_SF_CLIP_VIEWPORT_XMaxViewPort_start 416 +#define GEN8_SF_CLIP_VIEWPORT_XMaxViewPort_start 416 + +static inline uint32_t ATTRIBUTE_PURE +SF_CLIP_VIEWPORT_XMaxViewPort_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 416; + case 10: return 416; + case 9: return 416; + case 8: return 416; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_CLIP_VIEWPORT::X Min Clip Guardband */ + + +#define GEN11_SF_CLIP_VIEWPORT_XMinClipGuardband_bits 32 +#define GEN10_SF_CLIP_VIEWPORT_XMinClipGuardband_bits 32 +#define GEN9_SF_CLIP_VIEWPORT_XMinClipGuardband_bits 32 +#define GEN8_SF_CLIP_VIEWPORT_XMinClipGuardband_bits 32 +#define GEN75_SF_CLIP_VIEWPORT_XMinClipGuardband_bits 32 +#define GEN7_SF_CLIP_VIEWPORT_XMinClipGuardband_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SF_CLIP_VIEWPORT_XMinClipGuardband_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SF_CLIP_VIEWPORT_XMinClipGuardband_start 256 +#define GEN10_SF_CLIP_VIEWPORT_XMinClipGuardband_start 256 +#define GEN9_SF_CLIP_VIEWPORT_XMinClipGuardband_start 256 +#define GEN8_SF_CLIP_VIEWPORT_XMinClipGuardband_start 256 +#define GEN75_SF_CLIP_VIEWPORT_XMinClipGuardband_start 256 +#define GEN7_SF_CLIP_VIEWPORT_XMinClipGuardband_start 256 + +static inline uint32_t ATTRIBUTE_PURE +SF_CLIP_VIEWPORT_XMinClipGuardband_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 256; + case 10: return 256; + case 9: return 256; + case 8: return 256; + case 7: + if (devinfo->is_haswell) { + return 256; + } else { + return 256; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_CLIP_VIEWPORT::X Min ViewPort */ + + +#define GEN11_SF_CLIP_VIEWPORT_XMinViewPort_bits 32 +#define GEN10_SF_CLIP_VIEWPORT_XMinViewPort_bits 32 +#define GEN9_SF_CLIP_VIEWPORT_XMinViewPort_bits 32 +#define GEN8_SF_CLIP_VIEWPORT_XMinViewPort_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SF_CLIP_VIEWPORT_XMinViewPort_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SF_CLIP_VIEWPORT_XMinViewPort_start 384 +#define GEN10_SF_CLIP_VIEWPORT_XMinViewPort_start 384 +#define GEN9_SF_CLIP_VIEWPORT_XMinViewPort_start 384 +#define GEN8_SF_CLIP_VIEWPORT_XMinViewPort_start 384 + +static inline uint32_t ATTRIBUTE_PURE +SF_CLIP_VIEWPORT_XMinViewPort_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 384; + case 10: return 384; + case 9: return 384; + case 8: return 384; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_CLIP_VIEWPORT::Y Max Clip Guardband */ + + +#define GEN11_SF_CLIP_VIEWPORT_YMaxClipGuardband_bits 32 +#define GEN10_SF_CLIP_VIEWPORT_YMaxClipGuardband_bits 32 +#define GEN9_SF_CLIP_VIEWPORT_YMaxClipGuardband_bits 32 +#define GEN8_SF_CLIP_VIEWPORT_YMaxClipGuardband_bits 32 +#define GEN75_SF_CLIP_VIEWPORT_YMaxClipGuardband_bits 32 +#define GEN7_SF_CLIP_VIEWPORT_YMaxClipGuardband_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SF_CLIP_VIEWPORT_YMaxClipGuardband_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SF_CLIP_VIEWPORT_YMaxClipGuardband_start 352 +#define GEN10_SF_CLIP_VIEWPORT_YMaxClipGuardband_start 352 +#define GEN9_SF_CLIP_VIEWPORT_YMaxClipGuardband_start 352 +#define GEN8_SF_CLIP_VIEWPORT_YMaxClipGuardband_start 352 +#define GEN75_SF_CLIP_VIEWPORT_YMaxClipGuardband_start 352 +#define GEN7_SF_CLIP_VIEWPORT_YMaxClipGuardband_start 352 + +static inline uint32_t ATTRIBUTE_PURE +SF_CLIP_VIEWPORT_YMaxClipGuardband_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 352; + case 10: return 352; + case 9: return 352; + case 8: return 352; + case 7: + if (devinfo->is_haswell) { + return 352; + } else { + return 352; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_CLIP_VIEWPORT::Y Max ViewPort */ + + +#define GEN11_SF_CLIP_VIEWPORT_YMaxViewPort_bits 32 +#define GEN10_SF_CLIP_VIEWPORT_YMaxViewPort_bits 32 +#define GEN9_SF_CLIP_VIEWPORT_YMaxViewPort_bits 32 +#define GEN8_SF_CLIP_VIEWPORT_YMaxViewPort_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SF_CLIP_VIEWPORT_YMaxViewPort_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SF_CLIP_VIEWPORT_YMaxViewPort_start 480 +#define GEN10_SF_CLIP_VIEWPORT_YMaxViewPort_start 480 +#define GEN9_SF_CLIP_VIEWPORT_YMaxViewPort_start 480 +#define GEN8_SF_CLIP_VIEWPORT_YMaxViewPort_start 480 + +static inline uint32_t ATTRIBUTE_PURE +SF_CLIP_VIEWPORT_YMaxViewPort_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 480; + case 10: return 480; + case 9: return 480; + case 8: return 480; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_CLIP_VIEWPORT::Y Min Clip Guardband */ + + +#define GEN11_SF_CLIP_VIEWPORT_YMinClipGuardband_bits 32 +#define GEN10_SF_CLIP_VIEWPORT_YMinClipGuardband_bits 32 +#define GEN9_SF_CLIP_VIEWPORT_YMinClipGuardband_bits 32 +#define GEN8_SF_CLIP_VIEWPORT_YMinClipGuardband_bits 32 +#define GEN75_SF_CLIP_VIEWPORT_YMinClipGuardband_bits 32 +#define GEN7_SF_CLIP_VIEWPORT_YMinClipGuardband_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SF_CLIP_VIEWPORT_YMinClipGuardband_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SF_CLIP_VIEWPORT_YMinClipGuardband_start 320 +#define GEN10_SF_CLIP_VIEWPORT_YMinClipGuardband_start 320 +#define GEN9_SF_CLIP_VIEWPORT_YMinClipGuardband_start 320 +#define GEN8_SF_CLIP_VIEWPORT_YMinClipGuardband_start 320 +#define GEN75_SF_CLIP_VIEWPORT_YMinClipGuardband_start 320 +#define GEN7_SF_CLIP_VIEWPORT_YMinClipGuardband_start 320 + +static inline uint32_t ATTRIBUTE_PURE +SF_CLIP_VIEWPORT_YMinClipGuardband_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 320; + case 10: return 320; + case 9: return 320; + case 8: return 320; + case 7: + if (devinfo->is_haswell) { + return 320; + } else { + return 320; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_CLIP_VIEWPORT::Y Min ViewPort */ + + +#define GEN11_SF_CLIP_VIEWPORT_YMinViewPort_bits 32 +#define GEN10_SF_CLIP_VIEWPORT_YMinViewPort_bits 32 +#define GEN9_SF_CLIP_VIEWPORT_YMinViewPort_bits 32 +#define GEN8_SF_CLIP_VIEWPORT_YMinViewPort_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SF_CLIP_VIEWPORT_YMinViewPort_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SF_CLIP_VIEWPORT_YMinViewPort_start 448 +#define GEN10_SF_CLIP_VIEWPORT_YMinViewPort_start 448 +#define GEN9_SF_CLIP_VIEWPORT_YMinViewPort_start 448 +#define GEN8_SF_CLIP_VIEWPORT_YMinViewPort_start 448 + +static inline uint32_t ATTRIBUTE_PURE +SF_CLIP_VIEWPORT_YMinViewPort_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 448; + case 10: return 448; + case 9: return 448; + case 8: return 448; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_OUTPUT_ATTRIBUTE_DETAIL */ + + +#define GEN11_SF_OUTPUT_ATTRIBUTE_DETAIL_length 1 +#define GEN10_SF_OUTPUT_ATTRIBUTE_DETAIL_length 1 +#define GEN9_SF_OUTPUT_ATTRIBUTE_DETAIL_length 1 +#define GEN8_SF_OUTPUT_ATTRIBUTE_DETAIL_length 1 +#define GEN75_SF_OUTPUT_ATTRIBUTE_DETAIL_length 1 +#define GEN7_SF_OUTPUT_ATTRIBUTE_DETAIL_length 1 +#define GEN6_SF_OUTPUT_ATTRIBUTE_DETAIL_length 1 + +static inline uint32_t ATTRIBUTE_PURE +SF_OUTPUT_ATTRIBUTE_DETAIL_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_OUTPUT_ATTRIBUTE_DETAIL::Component Override W */ + + +#define GEN11_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideW_bits 1 +#define GEN10_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideW_bits 1 +#define GEN9_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideW_bits 1 +#define GEN8_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideW_bits 1 +#define GEN75_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideW_bits 1 +#define GEN7_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideW_bits 1 +#define GEN6_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideW_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideW_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideW_start 15 +#define GEN10_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideW_start 15 +#define GEN9_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideW_start 15 +#define GEN8_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideW_start 15 +#define GEN75_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideW_start 15 +#define GEN7_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideW_start 15 +#define GEN6_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideW_start 15 + +static inline uint32_t ATTRIBUTE_PURE +SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideW_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 15; + case 10: return 15; + case 9: return 15; + case 8: return 15; + case 7: + if (devinfo->is_haswell) { + return 15; + } else { + return 15; + } + case 6: return 15; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_OUTPUT_ATTRIBUTE_DETAIL::Component Override X */ + + +#define GEN11_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideX_bits 1 +#define GEN10_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideX_bits 1 +#define GEN9_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideX_bits 1 +#define GEN8_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideX_bits 1 +#define GEN75_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideX_bits 1 +#define GEN7_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideX_bits 1 +#define GEN6_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideX_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideX_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideX_start 12 +#define GEN10_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideX_start 12 +#define GEN9_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideX_start 12 +#define GEN8_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideX_start 12 +#define GEN75_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideX_start 12 +#define GEN7_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideX_start 12 +#define GEN6_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideX_start 12 + +static inline uint32_t ATTRIBUTE_PURE +SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideX_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 12; + case 10: return 12; + case 9: return 12; + case 8: return 12; + case 7: + if (devinfo->is_haswell) { + return 12; + } else { + return 12; + } + case 6: return 12; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_OUTPUT_ATTRIBUTE_DETAIL::Component Override Y */ + + +#define GEN11_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideY_bits 1 +#define GEN10_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideY_bits 1 +#define GEN9_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideY_bits 1 +#define GEN8_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideY_bits 1 +#define GEN75_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideY_bits 1 +#define GEN7_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideY_bits 1 +#define GEN6_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideY_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideY_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideY_start 13 +#define GEN10_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideY_start 13 +#define GEN9_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideY_start 13 +#define GEN8_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideY_start 13 +#define GEN75_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideY_start 13 +#define GEN7_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideY_start 13 +#define GEN6_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideY_start 13 + +static inline uint32_t ATTRIBUTE_PURE +SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideY_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 13; + case 10: return 13; + case 9: return 13; + case 8: return 13; + case 7: + if (devinfo->is_haswell) { + return 13; + } else { + return 13; + } + case 6: return 13; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_OUTPUT_ATTRIBUTE_DETAIL::Component Override Z */ + + +#define GEN11_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideZ_bits 1 +#define GEN10_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideZ_bits 1 +#define GEN9_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideZ_bits 1 +#define GEN8_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideZ_bits 1 +#define GEN75_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideZ_bits 1 +#define GEN7_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideZ_bits 1 +#define GEN6_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideZ_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideZ_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideZ_start 14 +#define GEN10_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideZ_start 14 +#define GEN9_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideZ_start 14 +#define GEN8_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideZ_start 14 +#define GEN75_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideZ_start 14 +#define GEN7_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideZ_start 14 +#define GEN6_SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideZ_start 14 + +static inline uint32_t ATTRIBUTE_PURE +SF_OUTPUT_ATTRIBUTE_DETAIL_ComponentOverrideZ_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 14; + case 10: return 14; + case 9: return 14; + case 8: return 14; + case 7: + if (devinfo->is_haswell) { + return 14; + } else { + return 14; + } + case 6: return 14; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_OUTPUT_ATTRIBUTE_DETAIL::Constant Source */ + + +#define GEN11_SF_OUTPUT_ATTRIBUTE_DETAIL_ConstantSource_bits 2 +#define GEN10_SF_OUTPUT_ATTRIBUTE_DETAIL_ConstantSource_bits 2 +#define GEN9_SF_OUTPUT_ATTRIBUTE_DETAIL_ConstantSource_bits 2 +#define GEN8_SF_OUTPUT_ATTRIBUTE_DETAIL_ConstantSource_bits 2 +#define GEN75_SF_OUTPUT_ATTRIBUTE_DETAIL_ConstantSource_bits 2 +#define GEN7_SF_OUTPUT_ATTRIBUTE_DETAIL_ConstantSource_bits 2 +#define GEN6_SF_OUTPUT_ATTRIBUTE_DETAIL_ConstantSource_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +SF_OUTPUT_ATTRIBUTE_DETAIL_ConstantSource_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SF_OUTPUT_ATTRIBUTE_DETAIL_ConstantSource_start 9 +#define GEN10_SF_OUTPUT_ATTRIBUTE_DETAIL_ConstantSource_start 9 +#define GEN9_SF_OUTPUT_ATTRIBUTE_DETAIL_ConstantSource_start 9 +#define GEN8_SF_OUTPUT_ATTRIBUTE_DETAIL_ConstantSource_start 9 +#define GEN75_SF_OUTPUT_ATTRIBUTE_DETAIL_ConstantSource_start 9 +#define GEN7_SF_OUTPUT_ATTRIBUTE_DETAIL_ConstantSource_start 9 +#define GEN6_SF_OUTPUT_ATTRIBUTE_DETAIL_ConstantSource_start 9 + +static inline uint32_t ATTRIBUTE_PURE +SF_OUTPUT_ATTRIBUTE_DETAIL_ConstantSource_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 9; + case 10: return 9; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 9; + } + case 6: return 9; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_OUTPUT_ATTRIBUTE_DETAIL::Source Attribute */ + + +#define GEN11_SF_OUTPUT_ATTRIBUTE_DETAIL_SourceAttribute_bits 5 +#define GEN10_SF_OUTPUT_ATTRIBUTE_DETAIL_SourceAttribute_bits 5 +#define GEN9_SF_OUTPUT_ATTRIBUTE_DETAIL_SourceAttribute_bits 5 +#define GEN8_SF_OUTPUT_ATTRIBUTE_DETAIL_SourceAttribute_bits 5 +#define GEN75_SF_OUTPUT_ATTRIBUTE_DETAIL_SourceAttribute_bits 5 +#define GEN7_SF_OUTPUT_ATTRIBUTE_DETAIL_SourceAttribute_bits 5 +#define GEN6_SF_OUTPUT_ATTRIBUTE_DETAIL_SourceAttribute_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +SF_OUTPUT_ATTRIBUTE_DETAIL_SourceAttribute_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 5; + } + case 6: return 5; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SF_OUTPUT_ATTRIBUTE_DETAIL_SourceAttribute_start 0 +#define GEN10_SF_OUTPUT_ATTRIBUTE_DETAIL_SourceAttribute_start 0 +#define GEN9_SF_OUTPUT_ATTRIBUTE_DETAIL_SourceAttribute_start 0 +#define GEN8_SF_OUTPUT_ATTRIBUTE_DETAIL_SourceAttribute_start 0 +#define GEN75_SF_OUTPUT_ATTRIBUTE_DETAIL_SourceAttribute_start 0 +#define GEN7_SF_OUTPUT_ATTRIBUTE_DETAIL_SourceAttribute_start 0 +#define GEN6_SF_OUTPUT_ATTRIBUTE_DETAIL_SourceAttribute_start 0 + +static inline uint32_t ATTRIBUTE_PURE +SF_OUTPUT_ATTRIBUTE_DETAIL_SourceAttribute_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_OUTPUT_ATTRIBUTE_DETAIL::Swizzle Control Mode */ + + +#define GEN11_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleControlMode_bits 1 +#define GEN10_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleControlMode_bits 1 +#define GEN9_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleControlMode_bits 1 +#define GEN8_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleControlMode_bits 1 +#define GEN75_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleControlMode_bits 1 +#define GEN7_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleControlMode_bits 1 +#define GEN6_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleControlMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleControlMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleControlMode_start 11 +#define GEN10_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleControlMode_start 11 +#define GEN9_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleControlMode_start 11 +#define GEN8_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleControlMode_start 11 +#define GEN75_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleControlMode_start 11 +#define GEN7_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleControlMode_start 11 +#define GEN6_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleControlMode_start 11 + +static inline uint32_t ATTRIBUTE_PURE +SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleControlMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 11; + } else { + return 11; + } + case 6: return 11; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_OUTPUT_ATTRIBUTE_DETAIL::Swizzle Select */ + + +#define GEN11_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleSelect_bits 2 +#define GEN10_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleSelect_bits 2 +#define GEN9_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleSelect_bits 2 +#define GEN8_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleSelect_bits 2 +#define GEN75_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleSelect_bits 2 +#define GEN7_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleSelect_bits 2 +#define GEN6_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleSelect_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleSelect_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleSelect_start 6 +#define GEN10_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleSelect_start 6 +#define GEN9_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleSelect_start 6 +#define GEN8_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleSelect_start 6 +#define GEN75_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleSelect_start 6 +#define GEN7_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleSelect_start 6 +#define GEN6_SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleSelect_start 6 + +static inline uint32_t ATTRIBUTE_PURE +SF_OUTPUT_ATTRIBUTE_DETAIL_SwizzleSelect_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 6; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE */ + + +#define GEN5_SF_STATE_length 8 +#define GEN45_SF_STATE_length 8 +#define GEN4_SF_STATE_length 8 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::2x2 Pixel Triangle Filter Disable */ + + +#define GEN5_SF_STATE_2x2PixelTriangleFilterDisable_bits 1 +#define GEN45_SF_STATE_2x2PixelTriangleFilterDisable_bits 1 +#define GEN4_SF_STATE_2x2PixelTriangleFilterDisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_2x2PixelTriangleFilterDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_2x2PixelTriangleFilterDisable_start 210 +#define GEN45_SF_STATE_2x2PixelTriangleFilterDisable_start 210 +#define GEN4_SF_STATE_2x2PixelTriangleFilterDisable_start 210 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_2x2PixelTriangleFilterDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 210; + case 4: + if (devinfo->is_g4x) { + return 210; + } else { + return 210; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::AA Line Distance Mode */ + + +#define GEN5_SF_STATE_AALineDistanceMode_bits 1 +#define GEN45_SF_STATE_AALineDistanceMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_AALineDistanceMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_AALineDistanceMode_start 238 +#define GEN45_SF_STATE_AALineDistanceMode_start 238 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_AALineDistanceMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 238; + case 4: + if (devinfo->is_g4x) { + return 238; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Anti-Aliasing Enable */ + + +#define GEN5_SF_STATE_AntiAliasingEnable_bits 1 +#define GEN45_SF_STATE_AntiAliasingEnable_bits 1 +#define GEN4_SF_STATE_AntiAliasingEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_AntiAliasingEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_AntiAliasingEnable_start 223 +#define GEN45_SF_STATE_AntiAliasingEnable_start 223 +#define GEN4_SF_STATE_AntiAliasingEnable_start 223 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_AntiAliasingEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 223; + case 4: + if (devinfo->is_g4x) { + return 223; + } else { + return 223; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Binding Table Entry Count */ + + +#define GEN5_SF_STATE_BindingTableEntryCount_bits 8 +#define GEN45_SF_STATE_BindingTableEntryCount_bits 8 +#define GEN4_SF_STATE_BindingTableEntryCount_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_BindingTableEntryCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_BindingTableEntryCount_start 50 +#define GEN45_SF_STATE_BindingTableEntryCount_start 50 +#define GEN4_SF_STATE_BindingTableEntryCount_start 50 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_BindingTableEntryCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 50; + case 4: + if (devinfo->is_g4x) { + return 50; + } else { + return 50; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Constant URB Entry Read Length */ + + +#define GEN5_SF_STATE_ConstantURBEntryReadLength_bits 6 +#define GEN45_SF_STATE_ConstantURBEntryReadLength_bits 6 +#define GEN4_SF_STATE_ConstantURBEntryReadLength_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_ConstantURBEntryReadLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_ConstantURBEntryReadLength_start 121 +#define GEN45_SF_STATE_ConstantURBEntryReadLength_start 121 +#define GEN4_SF_STATE_ConstantURBEntryReadLength_start 121 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_ConstantURBEntryReadLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 121; + case 4: + if (devinfo->is_g4x) { + return 121; + } else { + return 121; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Constant URB Entry Read Offset */ + + +#define GEN5_SF_STATE_ConstantURBEntryReadOffset_bits 6 +#define GEN45_SF_STATE_ConstantURBEntryReadOffset_bits 6 +#define GEN4_SF_STATE_ConstantURBEntryReadOffset_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_ConstantURBEntryReadOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_ConstantURBEntryReadOffset_start 114 +#define GEN45_SF_STATE_ConstantURBEntryReadOffset_start 114 +#define GEN4_SF_STATE_ConstantURBEntryReadOffset_start 114 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_ConstantURBEntryReadOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 114; + case 4: + if (devinfo->is_g4x) { + return 114; + } else { + return 114; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Cull Mode */ + + +#define GEN5_SF_STATE_CullMode_bits 2 +#define GEN45_SF_STATE_CullMode_bits 2 +#define GEN4_SF_STATE_CullMode_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_CullMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_CullMode_start 221 +#define GEN45_SF_STATE_CullMode_start 221 +#define GEN4_SF_STATE_CullMode_start 221 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_CullMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 221; + case 4: + if (devinfo->is_g4x) { + return 221; + } else { + return 221; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Destination Origin Horizontal Bias */ + + +#define GEN5_SF_STATE_DestinationOriginHorizontalBias_bits 4 +#define GEN45_SF_STATE_DestinationOriginHorizontalBias_bits 4 +#define GEN4_SF_STATE_DestinationOriginHorizontalBias_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_DestinationOriginHorizontalBias_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 4; + case 4: + if (devinfo->is_g4x) { + return 4; + } else { + return 4; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_DestinationOriginHorizontalBias_start 205 +#define GEN45_SF_STATE_DestinationOriginHorizontalBias_start 205 +#define GEN4_SF_STATE_DestinationOriginHorizontalBias_start 205 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_DestinationOriginHorizontalBias_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 205; + case 4: + if (devinfo->is_g4x) { + return 205; + } else { + return 205; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Destination Origin Vertical Bias */ + + +#define GEN5_SF_STATE_DestinationOriginVerticalBias_bits 4 +#define GEN45_SF_STATE_DestinationOriginVerticalBias_bits 4 +#define GEN4_SF_STATE_DestinationOriginVerticalBias_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_DestinationOriginVerticalBias_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 4; + case 4: + if (devinfo->is_g4x) { + return 4; + } else { + return 4; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_DestinationOriginVerticalBias_start 201 +#define GEN45_SF_STATE_DestinationOriginVerticalBias_start 201 +#define GEN4_SF_STATE_DestinationOriginVerticalBias_start 201 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_DestinationOriginVerticalBias_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 201; + case 4: + if (devinfo->is_g4x) { + return 201; + } else { + return 201; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Dispatch GRF Start Register For URB Data */ + + +#define GEN5_SF_STATE_DispatchGRFStartRegisterForURBData_bits 4 +#define GEN45_SF_STATE_DispatchGRFStartRegisterForURBData_bits 4 +#define GEN4_SF_STATE_DispatchGRFStartRegisterForURBData_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_DispatchGRFStartRegisterForURBData_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 4; + case 4: + if (devinfo->is_g4x) { + return 4; + } else { + return 4; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_DispatchGRFStartRegisterForURBData_start 96 +#define GEN45_SF_STATE_DispatchGRFStartRegisterForURBData_start 96 +#define GEN4_SF_STATE_DispatchGRFStartRegisterForURBData_start 96 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_DispatchGRFStartRegisterForURBData_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 96; + case 4: + if (devinfo->is_g4x) { + return 96; + } else { + return 96; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Fast Scissor Clip Disable */ + + +#define GEN5_SF_STATE_FastScissorClipDisable_bits 1 +#define GEN45_SF_STATE_FastScissorClipDisable_bits 1 +#define GEN4_SF_STATE_FastScissorClipDisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_FastScissorClipDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_FastScissorClipDisable_start 220 +#define GEN45_SF_STATE_FastScissorClipDisable_start 220 +#define GEN4_SF_STATE_FastScissorClipDisable_start 220 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_FastScissorClipDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 220; + case 4: + if (devinfo->is_g4x) { + return 220; + } else { + return 220; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Floating Point Mode */ + + +#define GEN5_SF_STATE_FloatingPointMode_bits 1 +#define GEN45_SF_STATE_FloatingPointMode_bits 1 +#define GEN4_SF_STATE_FloatingPointMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_FloatingPointMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_FloatingPointMode_start 48 +#define GEN45_SF_STATE_FloatingPointMode_start 48 +#define GEN4_SF_STATE_FloatingPointMode_start 48 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_FloatingPointMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 48; + case 4: + if (devinfo->is_g4x) { + return 48; + } else { + return 48; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Front Winding */ + + +#define GEN5_SF_STATE_FrontWinding_bits 1 +#define GEN45_SF_STATE_FrontWinding_bits 1 +#define GEN4_SF_STATE_FrontWinding_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_FrontWinding_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_FrontWinding_start 160 +#define GEN45_SF_STATE_FrontWinding_start 160 +#define GEN4_SF_STATE_FrontWinding_start 160 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_FrontWinding_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 160; + case 4: + if (devinfo->is_g4x) { + return 160; + } else { + return 160; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::GRF Register Count */ + + +#define GEN5_SF_STATE_GRFRegisterCount_bits 3 +#define GEN45_SF_STATE_GRFRegisterCount_bits 3 +#define GEN4_SF_STATE_GRFRegisterCount_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_GRFRegisterCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_GRFRegisterCount_start 1 +#define GEN45_SF_STATE_GRFRegisterCount_start 1 +#define GEN4_SF_STATE_GRFRegisterCount_start 1 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_GRFRegisterCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Illegal Opcode Exception Enable */ + + +#define GEN5_SF_STATE_IllegalOpcodeExceptionEnable_bits 1 +#define GEN45_SF_STATE_IllegalOpcodeExceptionEnable_bits 1 +#define GEN4_SF_STATE_IllegalOpcodeExceptionEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_IllegalOpcodeExceptionEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_IllegalOpcodeExceptionEnable_start 45 +#define GEN45_SF_STATE_IllegalOpcodeExceptionEnable_start 45 +#define GEN4_SF_STATE_IllegalOpcodeExceptionEnable_start 45 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_IllegalOpcodeExceptionEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 45; + case 4: + if (devinfo->is_g4x) { + return 45; + } else { + return 45; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Kernel Start Pointer */ + + +#define GEN5_SF_STATE_KernelStartPointer_bits 26 +#define GEN45_SF_STATE_KernelStartPointer_bits 26 +#define GEN4_SF_STATE_KernelStartPointer_bits 26 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_KernelStartPointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 26; + case 4: + if (devinfo->is_g4x) { + return 26; + } else { + return 26; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_KernelStartPointer_start 6 +#define GEN45_SF_STATE_KernelStartPointer_start 6 +#define GEN4_SF_STATE_KernelStartPointer_start 6 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_KernelStartPointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Last Pixel Enable */ + + +#define GEN5_SF_STATE_LastPixelEnable_bits 1 +#define GEN45_SF_STATE_LastPixelEnable_bits 1 +#define GEN4_SF_STATE_LastPixelEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_LastPixelEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_LastPixelEnable_start 255 +#define GEN45_SF_STATE_LastPixelEnable_start 255 +#define GEN4_SF_STATE_LastPixelEnable_start 255 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_LastPixelEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 255; + case 4: + if (devinfo->is_g4x) { + return 255; + } else { + return 255; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Line End Cap Antialiasing Region Width */ + + +#define GEN5_SF_STATE_LineEndCapAntialiasingRegionWidth_bits 2 +#define GEN45_SF_STATE_LineEndCapAntialiasingRegionWidth_bits 2 +#define GEN4_SF_STATE_LineEndCapAntialiasingRegionWidth_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_LineEndCapAntialiasingRegionWidth_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_LineEndCapAntialiasingRegionWidth_start 214 +#define GEN45_SF_STATE_LineEndCapAntialiasingRegionWidth_start 214 +#define GEN4_SF_STATE_LineEndCapAntialiasingRegionWidth_start 214 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_LineEndCapAntialiasingRegionWidth_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 214; + case 4: + if (devinfo->is_g4x) { + return 214; + } else { + return 214; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Line Strip/List Provoking Vertex Select */ + + +#define GEN5_SF_STATE_LineStripListProvokingVertexSelect_bits 2 +#define GEN45_SF_STATE_LineStripListProvokingVertexSelect_bits 2 +#define GEN4_SF_STATE_LineStripListProvokingVertexSelect_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_LineStripListProvokingVertexSelect_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_LineStripListProvokingVertexSelect_start 251 +#define GEN45_SF_STATE_LineStripListProvokingVertexSelect_start 251 +#define GEN4_SF_STATE_LineStripListProvokingVertexSelect_start 251 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_LineStripListProvokingVertexSelect_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 251; + case 4: + if (devinfo->is_g4x) { + return 251; + } else { + return 251; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Line Width */ + + +#define GEN5_SF_STATE_LineWidth_bits 4 +#define GEN45_SF_STATE_LineWidth_bits 4 +#define GEN4_SF_STATE_LineWidth_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_LineWidth_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 4; + case 4: + if (devinfo->is_g4x) { + return 4; + } else { + return 4; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_LineWidth_start 216 +#define GEN45_SF_STATE_LineWidth_start 216 +#define GEN4_SF_STATE_LineWidth_start 216 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_LineWidth_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 216; + case 4: + if (devinfo->is_g4x) { + return 216; + } else { + return 216; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Mask Stack Exception Enable */ + + +#define GEN5_SF_STATE_MaskStackExceptionEnable_bits 1 +#define GEN45_SF_STATE_MaskStackExceptionEnable_bits 1 +#define GEN4_SF_STATE_MaskStackExceptionEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_MaskStackExceptionEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_MaskStackExceptionEnable_start 43 +#define GEN45_SF_STATE_MaskStackExceptionEnable_start 43 +#define GEN4_SF_STATE_MaskStackExceptionEnable_start 43 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_MaskStackExceptionEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 43; + case 4: + if (devinfo->is_g4x) { + return 43; + } else { + return 43; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Maximum Number of Threads */ + + +#define GEN5_SF_STATE_MaximumNumberofThreads_bits 6 +#define GEN45_SF_STATE_MaximumNumberofThreads_bits 6 +#define GEN4_SF_STATE_MaximumNumberofThreads_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_MaximumNumberofThreads_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_MaximumNumberofThreads_start 153 +#define GEN45_SF_STATE_MaximumNumberofThreads_start 153 +#define GEN4_SF_STATE_MaximumNumberofThreads_start 153 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_MaximumNumberofThreads_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 153; + case 4: + if (devinfo->is_g4x) { + return 153; + } else { + return 153; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Number of URB Entries */ + + +#define GEN5_SF_STATE_NumberofURBEntries_bits 8 +#define GEN45_SF_STATE_NumberofURBEntries_bits 8 +#define GEN4_SF_STATE_NumberofURBEntries_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_NumberofURBEntries_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_NumberofURBEntries_start 139 +#define GEN45_SF_STATE_NumberofURBEntries_start 139 +#define GEN4_SF_STATE_NumberofURBEntries_start 139 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_NumberofURBEntries_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 139; + case 4: + if (devinfo->is_g4x) { + return 139; + } else { + return 139; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Per-Thread Scratch Space */ + + +#define GEN5_SF_STATE_PerThreadScratchSpace_bits 4 +#define GEN45_SF_STATE_PerThreadScratchSpace_bits 4 +#define GEN4_SF_STATE_PerThreadScratchSpace_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_PerThreadScratchSpace_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 4; + case 4: + if (devinfo->is_g4x) { + return 4; + } else { + return 4; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_PerThreadScratchSpace_start 64 +#define GEN45_SF_STATE_PerThreadScratchSpace_start 64 +#define GEN4_SF_STATE_PerThreadScratchSpace_start 64 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_PerThreadScratchSpace_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 64; + case 4: + if (devinfo->is_g4x) { + return 64; + } else { + return 64; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Point Rasterization Rule */ + + +#define GEN5_SF_STATE_PointRasterizationRule_bits 2 +#define GEN45_SF_STATE_PointRasterizationRule_bits 2 +#define GEN4_SF_STATE_PointRasterizationRule_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_PointRasterizationRule_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_PointRasterizationRule_start 212 +#define GEN45_SF_STATE_PointRasterizationRule_start 212 +#define GEN4_SF_STATE_PointRasterizationRule_start 212 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_PointRasterizationRule_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 212; + case 4: + if (devinfo->is_g4x) { + return 212; + } else { + return 212; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Point Width */ + + +#define GEN5_SF_STATE_PointWidth_bits 11 +#define GEN45_SF_STATE_PointWidth_bits 11 +#define GEN4_SF_STATE_PointWidth_bits 11 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_PointWidth_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 11; + case 4: + if (devinfo->is_g4x) { + return 11; + } else { + return 11; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_PointWidth_start 224 +#define GEN45_SF_STATE_PointWidth_start 224 +#define GEN4_SF_STATE_PointWidth_start 224 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_PointWidth_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 224; + case 4: + if (devinfo->is_g4x) { + return 224; + } else { + return 224; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Point Width Source */ + + +#define GEN5_SF_STATE_PointWidthSource_bits 1 +#define GEN45_SF_STATE_PointWidthSource_bits 1 +#define GEN4_SF_STATE_PointWidthSource_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_PointWidthSource_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_PointWidthSource_start 235 +#define GEN45_SF_STATE_PointWidthSource_start 235 +#define GEN4_SF_STATE_PointWidthSource_start 235 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_PointWidthSource_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 235; + case 4: + if (devinfo->is_g4x) { + return 235; + } else { + return 235; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Scissor Rectangle Enable */ + + +#define GEN5_SF_STATE_ScissorRectangleEnable_bits 1 +#define GEN45_SF_STATE_ScissorRectangleEnable_bits 1 +#define GEN4_SF_STATE_ScissorRectangleEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_ScissorRectangleEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_ScissorRectangleEnable_start 209 +#define GEN45_SF_STATE_ScissorRectangleEnable_start 209 +#define GEN4_SF_STATE_ScissorRectangleEnable_start 209 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_ScissorRectangleEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 209; + case 4: + if (devinfo->is_g4x) { + return 209; + } else { + return 209; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Scratch Space Base Pointer */ + + +#define GEN5_SF_STATE_ScratchSpaceBasePointer_bits 22 +#define GEN45_SF_STATE_ScratchSpaceBasePointer_bits 22 +#define GEN4_SF_STATE_ScratchSpaceBasePointer_bits 22 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_ScratchSpaceBasePointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 22; + case 4: + if (devinfo->is_g4x) { + return 22; + } else { + return 22; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_ScratchSpaceBasePointer_start 74 +#define GEN45_SF_STATE_ScratchSpaceBasePointer_start 74 +#define GEN4_SF_STATE_ScratchSpaceBasePointer_start 74 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_ScratchSpaceBasePointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 74; + case 4: + if (devinfo->is_g4x) { + return 74; + } else { + return 74; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Setup Viewport State Offset */ + + +#define GEN5_SF_STATE_SetupViewportStateOffset_bits 27 +#define GEN45_SF_STATE_SetupViewportStateOffset_bits 27 +#define GEN4_SF_STATE_SetupViewportStateOffset_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_SetupViewportStateOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_SetupViewportStateOffset_start 165 +#define GEN45_SF_STATE_SetupViewportStateOffset_start 165 +#define GEN4_SF_STATE_SetupViewportStateOffset_start 165 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_SetupViewportStateOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 165; + case 4: + if (devinfo->is_g4x) { + return 165; + } else { + return 165; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Single Program Flow */ + + +#define GEN5_SF_STATE_SingleProgramFlow_bits 1 +#define GEN45_SF_STATE_SingleProgramFlow_bits 1 +#define GEN4_SF_STATE_SingleProgramFlow_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_SingleProgramFlow_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_SingleProgramFlow_start 63 +#define GEN45_SF_STATE_SingleProgramFlow_start 63 +#define GEN4_SF_STATE_SingleProgramFlow_start 63 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_SingleProgramFlow_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 63; + case 4: + if (devinfo->is_g4x) { + return 63; + } else { + return 63; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Software Exception Enable */ + + +#define GEN5_SF_STATE_SoftwareExceptionEnable_bits 1 +#define GEN45_SF_STATE_SoftwareExceptionEnable_bits 1 +#define GEN4_SF_STATE_SoftwareExceptionEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_SoftwareExceptionEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_SoftwareExceptionEnable_start 39 +#define GEN45_SF_STATE_SoftwareExceptionEnable_start 39 +#define GEN4_SF_STATE_SoftwareExceptionEnable_start 39 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_SoftwareExceptionEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 39; + case 4: + if (devinfo->is_g4x) { + return 39; + } else { + return 39; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Sprite Point Enable */ + + +#define GEN5_SF_STATE_SpritePointEnable_bits 1 +#define GEN45_SF_STATE_SpritePointEnable_bits 1 +#define GEN4_SF_STATE_SpritePointEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_SpritePointEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_SpritePointEnable_start 237 +#define GEN45_SF_STATE_SpritePointEnable_start 237 +#define GEN4_SF_STATE_SpritePointEnable_start 237 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_SpritePointEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 237; + case 4: + if (devinfo->is_g4x) { + return 237; + } else { + return 237; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Statistics Enable */ + + +#define GEN45_SF_STATE_StatisticsEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_StatisticsEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN45_SF_STATE_StatisticsEnable_start 138 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_StatisticsEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 138; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Thread Priority */ + + +#define GEN5_SF_STATE_ThreadPriority_bits 1 +#define GEN45_SF_STATE_ThreadPriority_bits 1 +#define GEN4_SF_STATE_ThreadPriority_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_ThreadPriority_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_ThreadPriority_start 49 +#define GEN45_SF_STATE_ThreadPriority_start 49 +#define GEN4_SF_STATE_ThreadPriority_start 49 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_ThreadPriority_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 49; + case 4: + if (devinfo->is_g4x) { + return 49; + } else { + return 49; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Triangle Fan Provoking Vertex Select */ + + +#define GEN5_SF_STATE_TriangleFanProvokingVertexSelect_bits 2 +#define GEN45_SF_STATE_TriangleFanProvokingVertexSelect_bits 2 +#define GEN4_SF_STATE_TriangleFanProvokingVertexSelect_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_TriangleFanProvokingVertexSelect_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_TriangleFanProvokingVertexSelect_start 249 +#define GEN45_SF_STATE_TriangleFanProvokingVertexSelect_start 249 +#define GEN4_SF_STATE_TriangleFanProvokingVertexSelect_start 249 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_TriangleFanProvokingVertexSelect_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 249; + case 4: + if (devinfo->is_g4x) { + return 249; + } else { + return 249; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Triangle Strip/List Provoking Vertex Select */ + + +#define GEN5_SF_STATE_TriangleStripListProvokingVertexSelect_bits 2 +#define GEN45_SF_STATE_TriangleStripListProvokingVertexSelect_bits 2 +#define GEN4_SF_STATE_TriangleStripListProvokingVertexSelect_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_TriangleStripListProvokingVertexSelect_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_TriangleStripListProvokingVertexSelect_start 253 +#define GEN45_SF_STATE_TriangleStripListProvokingVertexSelect_start 253 +#define GEN4_SF_STATE_TriangleStripListProvokingVertexSelect_start 253 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_TriangleStripListProvokingVertexSelect_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 253; + case 4: + if (devinfo->is_g4x) { + return 253; + } else { + return 253; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::URB Entry Allocation Size */ + + +#define GEN5_SF_STATE_URBEntryAllocationSize_bits 5 +#define GEN45_SF_STATE_URBEntryAllocationSize_bits 5 +#define GEN4_SF_STATE_URBEntryAllocationSize_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_URBEntryAllocationSize_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 5; + case 4: + if (devinfo->is_g4x) { + return 5; + } else { + return 5; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_URBEntryAllocationSize_start 147 +#define GEN45_SF_STATE_URBEntryAllocationSize_start 147 +#define GEN4_SF_STATE_URBEntryAllocationSize_start 147 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_URBEntryAllocationSize_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 147; + case 4: + if (devinfo->is_g4x) { + return 147; + } else { + return 147; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Vertex Sub Pixel Precision Select */ + + +#define GEN5_SF_STATE_VertexSubPixelPrecisionSelect_bits 1 +#define GEN45_SF_STATE_VertexSubPixelPrecisionSelect_bits 1 +#define GEN4_SF_STATE_VertexSubPixelPrecisionSelect_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_VertexSubPixelPrecisionSelect_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_VertexSubPixelPrecisionSelect_start 236 +#define GEN45_SF_STATE_VertexSubPixelPrecisionSelect_start 236 +#define GEN4_SF_STATE_VertexSubPixelPrecisionSelect_start 236 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_VertexSubPixelPrecisionSelect_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 236; + case 4: + if (devinfo->is_g4x) { + return 236; + } else { + return 236; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Vertex URB Entry Read Length */ + + +#define GEN5_SF_STATE_VertexURBEntryReadLength_bits 6 +#define GEN45_SF_STATE_VertexURBEntryReadLength_bits 6 +#define GEN4_SF_STATE_VertexURBEntryReadLength_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_VertexURBEntryReadLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_VertexURBEntryReadLength_start 107 +#define GEN45_SF_STATE_VertexURBEntryReadLength_start 107 +#define GEN4_SF_STATE_VertexURBEntryReadLength_start 107 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_VertexURBEntryReadLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 107; + case 4: + if (devinfo->is_g4x) { + return 107; + } else { + return 107; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Vertex URB Entry Read Offset */ + + +#define GEN5_SF_STATE_VertexURBEntryReadOffset_bits 6 +#define GEN45_SF_STATE_VertexURBEntryReadOffset_bits 6 +#define GEN4_SF_STATE_VertexURBEntryReadOffset_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_VertexURBEntryReadOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_VertexURBEntryReadOffset_start 100 +#define GEN45_SF_STATE_VertexURBEntryReadOffset_start 100 +#define GEN4_SF_STATE_VertexURBEntryReadOffset_start 100 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_VertexURBEntryReadOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 100; + case 4: + if (devinfo->is_g4x) { + return 100; + } else { + return 100; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Viewport Transform Enable */ + + +#define GEN5_SF_STATE_ViewportTransformEnable_bits 1 +#define GEN45_SF_STATE_ViewportTransformEnable_bits 1 +#define GEN4_SF_STATE_ViewportTransformEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_ViewportTransformEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_ViewportTransformEnable_start 161 +#define GEN45_SF_STATE_ViewportTransformEnable_start 161 +#define GEN4_SF_STATE_ViewportTransformEnable_start 161 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_ViewportTransformEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 161; + case 4: + if (devinfo->is_g4x) { + return 161; + } else { + return 161; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_STATE::Zero Pixel Triangle Filter Disable */ + + +#define GEN5_SF_STATE_ZeroPixelTriangleFilterDisable_bits 1 +#define GEN45_SF_STATE_ZeroPixelTriangleFilterDisable_bits 1 +#define GEN4_SF_STATE_ZeroPixelTriangleFilterDisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_ZeroPixelTriangleFilterDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_STATE_ZeroPixelTriangleFilterDisable_start 211 +#define GEN45_SF_STATE_ZeroPixelTriangleFilterDisable_start 211 +#define GEN4_SF_STATE_ZeroPixelTriangleFilterDisable_start 211 + +static inline uint32_t ATTRIBUTE_PURE +SF_STATE_ZeroPixelTriangleFilterDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 211; + case 4: + if (devinfo->is_g4x) { + return 211; + } else { + return 211; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_VIEWPORT */ + + +#define GEN6_SF_VIEWPORT_length 8 +#define GEN5_SF_VIEWPORT_length 8 +#define GEN45_SF_VIEWPORT_length 8 +#define GEN4_SF_VIEWPORT_length 8 + +static inline uint32_t ATTRIBUTE_PURE +SF_VIEWPORT_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_VIEWPORT::Scissor Rectangle */ + + +#define GEN5_SF_VIEWPORT_ScissorRectangle_bits 64 +#define GEN45_SF_VIEWPORT_ScissorRectangle_bits 64 +#define GEN4_SF_VIEWPORT_ScissorRectangle_bits 64 + +static inline uint32_t ATTRIBUTE_PURE +SF_VIEWPORT_ScissorRectangle_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 64; + case 4: + if (devinfo->is_g4x) { + return 64; + } else { + return 64; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_SF_VIEWPORT_ScissorRectangle_start 192 +#define GEN45_SF_VIEWPORT_ScissorRectangle_start 192 +#define GEN4_SF_VIEWPORT_ScissorRectangle_start 192 + +static inline uint32_t ATTRIBUTE_PURE +SF_VIEWPORT_ScissorRectangle_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 192; + case 4: + if (devinfo->is_g4x) { + return 192; + } else { + return 192; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_VIEWPORT::Viewport Matrix Element m00 */ + + +#define GEN6_SF_VIEWPORT_ViewportMatrixElementm00_bits 32 +#define GEN5_SF_VIEWPORT_ViewportMatrixElementm00_bits 32 +#define GEN45_SF_VIEWPORT_ViewportMatrixElementm00_bits 32 +#define GEN4_SF_VIEWPORT_ViewportMatrixElementm00_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SF_VIEWPORT_ViewportMatrixElementm00_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_SF_VIEWPORT_ViewportMatrixElementm00_start 0 +#define GEN5_SF_VIEWPORT_ViewportMatrixElementm00_start 0 +#define GEN45_SF_VIEWPORT_ViewportMatrixElementm00_start 0 +#define GEN4_SF_VIEWPORT_ViewportMatrixElementm00_start 0 + +static inline uint32_t ATTRIBUTE_PURE +SF_VIEWPORT_ViewportMatrixElementm00_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_VIEWPORT::Viewport Matrix Element m11 */ + + +#define GEN6_SF_VIEWPORT_ViewportMatrixElementm11_bits 32 +#define GEN5_SF_VIEWPORT_ViewportMatrixElementm11_bits 32 +#define GEN45_SF_VIEWPORT_ViewportMatrixElementm11_bits 32 +#define GEN4_SF_VIEWPORT_ViewportMatrixElementm11_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SF_VIEWPORT_ViewportMatrixElementm11_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_SF_VIEWPORT_ViewportMatrixElementm11_start 32 +#define GEN5_SF_VIEWPORT_ViewportMatrixElementm11_start 32 +#define GEN45_SF_VIEWPORT_ViewportMatrixElementm11_start 32 +#define GEN4_SF_VIEWPORT_ViewportMatrixElementm11_start 32 + +static inline uint32_t ATTRIBUTE_PURE +SF_VIEWPORT_ViewportMatrixElementm11_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_VIEWPORT::Viewport Matrix Element m22 */ + + +#define GEN6_SF_VIEWPORT_ViewportMatrixElementm22_bits 32 +#define GEN5_SF_VIEWPORT_ViewportMatrixElementm22_bits 32 +#define GEN45_SF_VIEWPORT_ViewportMatrixElementm22_bits 32 +#define GEN4_SF_VIEWPORT_ViewportMatrixElementm22_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SF_VIEWPORT_ViewportMatrixElementm22_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_SF_VIEWPORT_ViewportMatrixElementm22_start 64 +#define GEN5_SF_VIEWPORT_ViewportMatrixElementm22_start 64 +#define GEN45_SF_VIEWPORT_ViewportMatrixElementm22_start 64 +#define GEN4_SF_VIEWPORT_ViewportMatrixElementm22_start 64 + +static inline uint32_t ATTRIBUTE_PURE +SF_VIEWPORT_ViewportMatrixElementm22_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 64; + case 5: return 64; + case 4: + if (devinfo->is_g4x) { + return 64; + } else { + return 64; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_VIEWPORT::Viewport Matrix Element m30 */ + + +#define GEN6_SF_VIEWPORT_ViewportMatrixElementm30_bits 32 +#define GEN5_SF_VIEWPORT_ViewportMatrixElementm30_bits 32 +#define GEN45_SF_VIEWPORT_ViewportMatrixElementm30_bits 32 +#define GEN4_SF_VIEWPORT_ViewportMatrixElementm30_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SF_VIEWPORT_ViewportMatrixElementm30_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_SF_VIEWPORT_ViewportMatrixElementm30_start 96 +#define GEN5_SF_VIEWPORT_ViewportMatrixElementm30_start 96 +#define GEN45_SF_VIEWPORT_ViewportMatrixElementm30_start 96 +#define GEN4_SF_VIEWPORT_ViewportMatrixElementm30_start 96 + +static inline uint32_t ATTRIBUTE_PURE +SF_VIEWPORT_ViewportMatrixElementm30_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 96; + case 5: return 96; + case 4: + if (devinfo->is_g4x) { + return 96; + } else { + return 96; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_VIEWPORT::Viewport Matrix Element m31 */ + + +#define GEN6_SF_VIEWPORT_ViewportMatrixElementm31_bits 32 +#define GEN5_SF_VIEWPORT_ViewportMatrixElementm31_bits 32 +#define GEN45_SF_VIEWPORT_ViewportMatrixElementm31_bits 32 +#define GEN4_SF_VIEWPORT_ViewportMatrixElementm31_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SF_VIEWPORT_ViewportMatrixElementm31_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_SF_VIEWPORT_ViewportMatrixElementm31_start 128 +#define GEN5_SF_VIEWPORT_ViewportMatrixElementm31_start 128 +#define GEN45_SF_VIEWPORT_ViewportMatrixElementm31_start 128 +#define GEN4_SF_VIEWPORT_ViewportMatrixElementm31_start 128 + +static inline uint32_t ATTRIBUTE_PURE +SF_VIEWPORT_ViewportMatrixElementm31_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 128; + case 5: return 128; + case 4: + if (devinfo->is_g4x) { + return 128; + } else { + return 128; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SF_VIEWPORT::Viewport Matrix Element m32 */ + + +#define GEN6_SF_VIEWPORT_ViewportMatrixElementm32_bits 32 +#define GEN5_SF_VIEWPORT_ViewportMatrixElementm32_bits 32 +#define GEN45_SF_VIEWPORT_ViewportMatrixElementm32_bits 32 +#define GEN4_SF_VIEWPORT_ViewportMatrixElementm32_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +SF_VIEWPORT_ViewportMatrixElementm32_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN6_SF_VIEWPORT_ViewportMatrixElementm32_start 160 +#define GEN5_SF_VIEWPORT_ViewportMatrixElementm32_start 160 +#define GEN45_SF_VIEWPORT_ViewportMatrixElementm32_start 160 +#define GEN4_SF_VIEWPORT_ViewportMatrixElementm32_start 160 + +static inline uint32_t ATTRIBUTE_PURE +SF_VIEWPORT_ViewportMatrixElementm32_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 160; + case 5: return 160; + case 4: + if (devinfo->is_g4x) { + return 160; + } else { + return 160; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SLICE_COMMON_ECO_CHICKEN1 */ + + +#define GEN9_SLICE_COMMON_ECO_CHICKEN1_length 1 + +static inline uint32_t ATTRIBUTE_PURE +SLICE_COMMON_ECO_CHICKEN1_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SLICE_COMMON_ECO_CHICKEN1::GLK Barrier Mode */ + + +#define GEN9_SLICE_COMMON_ECO_CHICKEN1_GLKBarrierMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SLICE_COMMON_ECO_CHICKEN1_GLKBarrierMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_SLICE_COMMON_ECO_CHICKEN1_GLKBarrierMode_start 7 + +static inline uint32_t ATTRIBUTE_PURE +SLICE_COMMON_ECO_CHICKEN1_GLKBarrierMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 7; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SLICE_COMMON_ECO_CHICKEN1::GLK Barrier Mode Mask */ + + +#define GEN9_SLICE_COMMON_ECO_CHICKEN1_GLKBarrierModeMask_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SLICE_COMMON_ECO_CHICKEN1_GLKBarrierModeMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_SLICE_COMMON_ECO_CHICKEN1_GLKBarrierModeMask_start 23 + +static inline uint32_t ATTRIBUTE_PURE +SLICE_COMMON_ECO_CHICKEN1_GLKBarrierModeMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 23; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_DECL */ + + +#define GEN11_SO_DECL_length 1 +#define GEN10_SO_DECL_length 1 +#define GEN9_SO_DECL_length 1 +#define GEN8_SO_DECL_length 1 +#define GEN75_SO_DECL_length 1 +#define GEN7_SO_DECL_length 1 + +static inline uint32_t ATTRIBUTE_PURE +SO_DECL_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_DECL::Component Mask */ + + +#define GEN11_SO_DECL_ComponentMask_bits 4 +#define GEN10_SO_DECL_ComponentMask_bits 4 +#define GEN9_SO_DECL_ComponentMask_bits 4 +#define GEN8_SO_DECL_ComponentMask_bits 4 +#define GEN75_SO_DECL_ComponentMask_bits 4 +#define GEN7_SO_DECL_ComponentMask_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +SO_DECL_ComponentMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SO_DECL_ComponentMask_start 0 +#define GEN10_SO_DECL_ComponentMask_start 0 +#define GEN9_SO_DECL_ComponentMask_start 0 +#define GEN8_SO_DECL_ComponentMask_start 0 +#define GEN75_SO_DECL_ComponentMask_start 0 +#define GEN7_SO_DECL_ComponentMask_start 0 + +static inline uint32_t ATTRIBUTE_PURE +SO_DECL_ComponentMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_DECL::Hole Flag */ + + +#define GEN11_SO_DECL_HoleFlag_bits 1 +#define GEN10_SO_DECL_HoleFlag_bits 1 +#define GEN9_SO_DECL_HoleFlag_bits 1 +#define GEN8_SO_DECL_HoleFlag_bits 1 +#define GEN75_SO_DECL_HoleFlag_bits 1 +#define GEN7_SO_DECL_HoleFlag_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +SO_DECL_HoleFlag_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SO_DECL_HoleFlag_start 11 +#define GEN10_SO_DECL_HoleFlag_start 11 +#define GEN9_SO_DECL_HoleFlag_start 11 +#define GEN8_SO_DECL_HoleFlag_start 11 +#define GEN75_SO_DECL_HoleFlag_start 11 +#define GEN7_SO_DECL_HoleFlag_start 11 + +static inline uint32_t ATTRIBUTE_PURE +SO_DECL_HoleFlag_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 11; + } else { + return 11; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_DECL::Output Buffer Slot */ + + +#define GEN11_SO_DECL_OutputBufferSlot_bits 2 +#define GEN10_SO_DECL_OutputBufferSlot_bits 2 +#define GEN9_SO_DECL_OutputBufferSlot_bits 2 +#define GEN8_SO_DECL_OutputBufferSlot_bits 2 +#define GEN75_SO_DECL_OutputBufferSlot_bits 2 +#define GEN7_SO_DECL_OutputBufferSlot_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +SO_DECL_OutputBufferSlot_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SO_DECL_OutputBufferSlot_start 12 +#define GEN10_SO_DECL_OutputBufferSlot_start 12 +#define GEN9_SO_DECL_OutputBufferSlot_start 12 +#define GEN8_SO_DECL_OutputBufferSlot_start 12 +#define GEN75_SO_DECL_OutputBufferSlot_start 12 +#define GEN7_SO_DECL_OutputBufferSlot_start 12 + +static inline uint32_t ATTRIBUTE_PURE +SO_DECL_OutputBufferSlot_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 12; + case 10: return 12; + case 9: return 12; + case 8: return 12; + case 7: + if (devinfo->is_haswell) { + return 12; + } else { + return 12; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_DECL::Register Index */ + + +#define GEN11_SO_DECL_RegisterIndex_bits 6 +#define GEN10_SO_DECL_RegisterIndex_bits 6 +#define GEN9_SO_DECL_RegisterIndex_bits 6 +#define GEN8_SO_DECL_RegisterIndex_bits 6 +#define GEN75_SO_DECL_RegisterIndex_bits 6 +#define GEN7_SO_DECL_RegisterIndex_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +SO_DECL_RegisterIndex_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SO_DECL_RegisterIndex_start 4 +#define GEN10_SO_DECL_RegisterIndex_start 4 +#define GEN9_SO_DECL_RegisterIndex_start 4 +#define GEN8_SO_DECL_RegisterIndex_start 4 +#define GEN75_SO_DECL_RegisterIndex_start 4 +#define GEN7_SO_DECL_RegisterIndex_start 4 + +static inline uint32_t ATTRIBUTE_PURE +SO_DECL_RegisterIndex_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_DECL_ENTRY */ + + +#define GEN11_SO_DECL_ENTRY_length 2 +#define GEN10_SO_DECL_ENTRY_length 2 +#define GEN9_SO_DECL_ENTRY_length 2 +#define GEN8_SO_DECL_ENTRY_length 2 +#define GEN75_SO_DECL_ENTRY_length 2 +#define GEN7_SO_DECL_ENTRY_length 2 + +static inline uint32_t ATTRIBUTE_PURE +SO_DECL_ENTRY_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_DECL_ENTRY::Stream 0 Decl */ + + +#define GEN11_SO_DECL_ENTRY_Stream0Decl_bits 16 +#define GEN10_SO_DECL_ENTRY_Stream0Decl_bits 16 +#define GEN9_SO_DECL_ENTRY_Stream0Decl_bits 16 +#define GEN8_SO_DECL_ENTRY_Stream0Decl_bits 16 +#define GEN75_SO_DECL_ENTRY_Stream0Decl_bits 16 +#define GEN7_SO_DECL_ENTRY_Stream0Decl_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +SO_DECL_ENTRY_Stream0Decl_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SO_DECL_ENTRY_Stream0Decl_start 0 +#define GEN10_SO_DECL_ENTRY_Stream0Decl_start 0 +#define GEN9_SO_DECL_ENTRY_Stream0Decl_start 0 +#define GEN8_SO_DECL_ENTRY_Stream0Decl_start 0 +#define GEN75_SO_DECL_ENTRY_Stream0Decl_start 0 +#define GEN7_SO_DECL_ENTRY_Stream0Decl_start 0 + +static inline uint32_t ATTRIBUTE_PURE +SO_DECL_ENTRY_Stream0Decl_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_DECL_ENTRY::Stream 1 Decl */ + + +#define GEN11_SO_DECL_ENTRY_Stream1Decl_bits 16 +#define GEN10_SO_DECL_ENTRY_Stream1Decl_bits 16 +#define GEN9_SO_DECL_ENTRY_Stream1Decl_bits 16 +#define GEN8_SO_DECL_ENTRY_Stream1Decl_bits 16 +#define GEN75_SO_DECL_ENTRY_Stream1Decl_bits 16 +#define GEN7_SO_DECL_ENTRY_Stream1Decl_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +SO_DECL_ENTRY_Stream1Decl_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SO_DECL_ENTRY_Stream1Decl_start 16 +#define GEN10_SO_DECL_ENTRY_Stream1Decl_start 16 +#define GEN9_SO_DECL_ENTRY_Stream1Decl_start 16 +#define GEN8_SO_DECL_ENTRY_Stream1Decl_start 16 +#define GEN75_SO_DECL_ENTRY_Stream1Decl_start 16 +#define GEN7_SO_DECL_ENTRY_Stream1Decl_start 16 + +static inline uint32_t ATTRIBUTE_PURE +SO_DECL_ENTRY_Stream1Decl_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_DECL_ENTRY::Stream 2 Decl */ + + +#define GEN11_SO_DECL_ENTRY_Stream2Decl_bits 16 +#define GEN10_SO_DECL_ENTRY_Stream2Decl_bits 16 +#define GEN9_SO_DECL_ENTRY_Stream2Decl_bits 16 +#define GEN8_SO_DECL_ENTRY_Stream2Decl_bits 16 +#define GEN75_SO_DECL_ENTRY_Stream2Decl_bits 16 +#define GEN7_SO_DECL_ENTRY_Stream2Decl_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +SO_DECL_ENTRY_Stream2Decl_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SO_DECL_ENTRY_Stream2Decl_start 32 +#define GEN10_SO_DECL_ENTRY_Stream2Decl_start 32 +#define GEN9_SO_DECL_ENTRY_Stream2Decl_start 32 +#define GEN8_SO_DECL_ENTRY_Stream2Decl_start 32 +#define GEN75_SO_DECL_ENTRY_Stream2Decl_start 32 +#define GEN7_SO_DECL_ENTRY_Stream2Decl_start 32 + +static inline uint32_t ATTRIBUTE_PURE +SO_DECL_ENTRY_Stream2Decl_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_DECL_ENTRY::Stream 3 Decl */ + + +#define GEN11_SO_DECL_ENTRY_Stream3Decl_bits 16 +#define GEN10_SO_DECL_ENTRY_Stream3Decl_bits 16 +#define GEN9_SO_DECL_ENTRY_Stream3Decl_bits 16 +#define GEN8_SO_DECL_ENTRY_Stream3Decl_bits 16 +#define GEN75_SO_DECL_ENTRY_Stream3Decl_bits 16 +#define GEN7_SO_DECL_ENTRY_Stream3Decl_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +SO_DECL_ENTRY_Stream3Decl_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SO_DECL_ENTRY_Stream3Decl_start 48 +#define GEN10_SO_DECL_ENTRY_Stream3Decl_start 48 +#define GEN9_SO_DECL_ENTRY_Stream3Decl_start 48 +#define GEN8_SO_DECL_ENTRY_Stream3Decl_start 48 +#define GEN75_SO_DECL_ENTRY_Stream3Decl_start 48 +#define GEN7_SO_DECL_ENTRY_Stream3Decl_start 48 + +static inline uint32_t ATTRIBUTE_PURE +SO_DECL_ENTRY_Stream3Decl_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 48; + case 7: + if (devinfo->is_haswell) { + return 48; + } else { + return 48; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_NUM_PRIMS_WRITTEN0 */ + + +#define GEN11_SO_NUM_PRIMS_WRITTEN0_length 2 +#define GEN10_SO_NUM_PRIMS_WRITTEN0_length 2 +#define GEN9_SO_NUM_PRIMS_WRITTEN0_length 2 +#define GEN8_SO_NUM_PRIMS_WRITTEN0_length 2 +#define GEN75_SO_NUM_PRIMS_WRITTEN0_length 2 +#define GEN7_SO_NUM_PRIMS_WRITTEN0_length 2 + +static inline uint32_t ATTRIBUTE_PURE +SO_NUM_PRIMS_WRITTEN0_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_NUM_PRIMS_WRITTEN0::Num Prims Written Count */ + + +#define GEN11_SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_bits 64 +#define GEN10_SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_bits 64 +#define GEN9_SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_bits 64 +#define GEN8_SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_bits 64 +#define GEN75_SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_bits 64 +#define GEN7_SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_bits 64 + +static inline uint32_t ATTRIBUTE_PURE +SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_start 0 +#define GEN10_SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_start 0 +#define GEN9_SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_start 0 +#define GEN8_SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_start 0 +#define GEN75_SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_start 0 +#define GEN7_SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_start 0 + +static inline uint32_t ATTRIBUTE_PURE +SO_NUM_PRIMS_WRITTEN0_NumPrimsWrittenCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_NUM_PRIMS_WRITTEN1 */ + + +#define GEN11_SO_NUM_PRIMS_WRITTEN1_length 2 +#define GEN10_SO_NUM_PRIMS_WRITTEN1_length 2 +#define GEN9_SO_NUM_PRIMS_WRITTEN1_length 2 +#define GEN8_SO_NUM_PRIMS_WRITTEN1_length 2 +#define GEN75_SO_NUM_PRIMS_WRITTEN1_length 2 +#define GEN7_SO_NUM_PRIMS_WRITTEN1_length 2 + +static inline uint32_t ATTRIBUTE_PURE +SO_NUM_PRIMS_WRITTEN1_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_NUM_PRIMS_WRITTEN1::Num Prims Written Count */ + + +#define GEN11_SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_bits 64 +#define GEN10_SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_bits 64 +#define GEN9_SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_bits 64 +#define GEN8_SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_bits 64 +#define GEN75_SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_bits 64 +#define GEN7_SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_bits 64 + +static inline uint32_t ATTRIBUTE_PURE +SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_start 0 +#define GEN10_SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_start 0 +#define GEN9_SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_start 0 +#define GEN8_SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_start 0 +#define GEN75_SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_start 0 +#define GEN7_SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_start 0 + +static inline uint32_t ATTRIBUTE_PURE +SO_NUM_PRIMS_WRITTEN1_NumPrimsWrittenCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_NUM_PRIMS_WRITTEN2 */ + + +#define GEN11_SO_NUM_PRIMS_WRITTEN2_length 2 +#define GEN10_SO_NUM_PRIMS_WRITTEN2_length 2 +#define GEN9_SO_NUM_PRIMS_WRITTEN2_length 2 +#define GEN8_SO_NUM_PRIMS_WRITTEN2_length 2 +#define GEN75_SO_NUM_PRIMS_WRITTEN2_length 2 +#define GEN7_SO_NUM_PRIMS_WRITTEN2_length 2 + +static inline uint32_t ATTRIBUTE_PURE +SO_NUM_PRIMS_WRITTEN2_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_NUM_PRIMS_WRITTEN2::Num Prims Written Count */ + + +#define GEN11_SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_bits 64 +#define GEN10_SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_bits 64 +#define GEN9_SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_bits 64 +#define GEN8_SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_bits 64 +#define GEN75_SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_bits 64 +#define GEN7_SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_bits 64 + +static inline uint32_t ATTRIBUTE_PURE +SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_start 0 +#define GEN10_SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_start 0 +#define GEN9_SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_start 0 +#define GEN8_SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_start 0 +#define GEN75_SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_start 0 +#define GEN7_SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_start 0 + +static inline uint32_t ATTRIBUTE_PURE +SO_NUM_PRIMS_WRITTEN2_NumPrimsWrittenCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_NUM_PRIMS_WRITTEN3 */ + + +#define GEN11_SO_NUM_PRIMS_WRITTEN3_length 2 +#define GEN10_SO_NUM_PRIMS_WRITTEN3_length 2 +#define GEN9_SO_NUM_PRIMS_WRITTEN3_length 2 +#define GEN8_SO_NUM_PRIMS_WRITTEN3_length 2 +#define GEN75_SO_NUM_PRIMS_WRITTEN3_length 2 +#define GEN7_SO_NUM_PRIMS_WRITTEN3_length 2 + +static inline uint32_t ATTRIBUTE_PURE +SO_NUM_PRIMS_WRITTEN3_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_NUM_PRIMS_WRITTEN3::Num Prims Written Count */ + + +#define GEN11_SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_bits 64 +#define GEN10_SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_bits 64 +#define GEN9_SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_bits 64 +#define GEN8_SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_bits 64 +#define GEN75_SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_bits 64 +#define GEN7_SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_bits 64 + +static inline uint32_t ATTRIBUTE_PURE +SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_start 0 +#define GEN10_SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_start 0 +#define GEN9_SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_start 0 +#define GEN8_SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_start 0 +#define GEN75_SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_start 0 +#define GEN7_SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_start 0 + +static inline uint32_t ATTRIBUTE_PURE +SO_NUM_PRIMS_WRITTEN3_NumPrimsWrittenCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_PRIM_STORAGE_NEEDED0 */ + + +#define GEN11_SO_PRIM_STORAGE_NEEDED0_length 2 +#define GEN10_SO_PRIM_STORAGE_NEEDED0_length 2 +#define GEN9_SO_PRIM_STORAGE_NEEDED0_length 2 +#define GEN8_SO_PRIM_STORAGE_NEEDED0_length 2 +#define GEN75_SO_PRIM_STORAGE_NEEDED0_length 2 +#define GEN7_SO_PRIM_STORAGE_NEEDED0_length 2 + +static inline uint32_t ATTRIBUTE_PURE +SO_PRIM_STORAGE_NEEDED0_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_PRIM_STORAGE_NEEDED0::Prim Storage Needed Count */ + + +#define GEN11_SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_bits 64 +#define GEN10_SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_bits 64 +#define GEN9_SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_bits 64 +#define GEN8_SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_bits 64 +#define GEN75_SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_bits 64 +#define GEN7_SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_bits 64 + +static inline uint32_t ATTRIBUTE_PURE +SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_start 0 +#define GEN10_SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_start 0 +#define GEN9_SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_start 0 +#define GEN8_SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_start 0 +#define GEN75_SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_start 0 +#define GEN7_SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_start 0 + +static inline uint32_t ATTRIBUTE_PURE +SO_PRIM_STORAGE_NEEDED0_PrimStorageNeededCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_PRIM_STORAGE_NEEDED1 */ + + +#define GEN11_SO_PRIM_STORAGE_NEEDED1_length 2 +#define GEN10_SO_PRIM_STORAGE_NEEDED1_length 2 +#define GEN9_SO_PRIM_STORAGE_NEEDED1_length 2 +#define GEN8_SO_PRIM_STORAGE_NEEDED1_length 2 +#define GEN75_SO_PRIM_STORAGE_NEEDED1_length 2 +#define GEN7_SO_PRIM_STORAGE_NEEDED1_length 2 + +static inline uint32_t ATTRIBUTE_PURE +SO_PRIM_STORAGE_NEEDED1_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_PRIM_STORAGE_NEEDED1::Prim Storage Needed Count */ + + +#define GEN11_SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_bits 64 +#define GEN10_SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_bits 64 +#define GEN9_SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_bits 64 +#define GEN8_SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_bits 64 +#define GEN75_SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_bits 64 +#define GEN7_SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_bits 64 + +static inline uint32_t ATTRIBUTE_PURE +SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_start 0 +#define GEN10_SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_start 0 +#define GEN9_SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_start 0 +#define GEN8_SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_start 0 +#define GEN75_SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_start 0 +#define GEN7_SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_start 0 + +static inline uint32_t ATTRIBUTE_PURE +SO_PRIM_STORAGE_NEEDED1_PrimStorageNeededCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_PRIM_STORAGE_NEEDED2 */ + + +#define GEN11_SO_PRIM_STORAGE_NEEDED2_length 2 +#define GEN10_SO_PRIM_STORAGE_NEEDED2_length 2 +#define GEN9_SO_PRIM_STORAGE_NEEDED2_length 2 +#define GEN8_SO_PRIM_STORAGE_NEEDED2_length 2 +#define GEN75_SO_PRIM_STORAGE_NEEDED2_length 2 +#define GEN7_SO_PRIM_STORAGE_NEEDED2_length 2 + +static inline uint32_t ATTRIBUTE_PURE +SO_PRIM_STORAGE_NEEDED2_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_PRIM_STORAGE_NEEDED2::Prim Storage Needed Count */ + + +#define GEN11_SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_bits 64 +#define GEN10_SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_bits 64 +#define GEN9_SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_bits 64 +#define GEN8_SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_bits 64 +#define GEN75_SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_bits 64 +#define GEN7_SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_bits 64 + +static inline uint32_t ATTRIBUTE_PURE +SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_start 0 +#define GEN10_SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_start 0 +#define GEN9_SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_start 0 +#define GEN8_SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_start 0 +#define GEN75_SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_start 0 +#define GEN7_SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_start 0 + +static inline uint32_t ATTRIBUTE_PURE +SO_PRIM_STORAGE_NEEDED2_PrimStorageNeededCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_PRIM_STORAGE_NEEDED3 */ + + +#define GEN11_SO_PRIM_STORAGE_NEEDED3_length 2 +#define GEN10_SO_PRIM_STORAGE_NEEDED3_length 2 +#define GEN9_SO_PRIM_STORAGE_NEEDED3_length 2 +#define GEN8_SO_PRIM_STORAGE_NEEDED3_length 2 +#define GEN75_SO_PRIM_STORAGE_NEEDED3_length 2 +#define GEN7_SO_PRIM_STORAGE_NEEDED3_length 2 + +static inline uint32_t ATTRIBUTE_PURE +SO_PRIM_STORAGE_NEEDED3_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_PRIM_STORAGE_NEEDED3::Prim Storage Needed Count */ + + +#define GEN11_SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_bits 64 +#define GEN10_SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_bits 64 +#define GEN9_SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_bits 64 +#define GEN8_SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_bits 64 +#define GEN75_SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_bits 64 +#define GEN7_SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_bits 64 + +static inline uint32_t ATTRIBUTE_PURE +SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_start 0 +#define GEN10_SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_start 0 +#define GEN9_SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_start 0 +#define GEN8_SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_start 0 +#define GEN75_SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_start 0 +#define GEN7_SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_start 0 + +static inline uint32_t ATTRIBUTE_PURE +SO_PRIM_STORAGE_NEEDED3_PrimStorageNeededCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_WRITE_OFFSET0 */ + + +#define GEN11_SO_WRITE_OFFSET0_length 1 +#define GEN10_SO_WRITE_OFFSET0_length 1 +#define GEN9_SO_WRITE_OFFSET0_length 1 +#define GEN8_SO_WRITE_OFFSET0_length 1 +#define GEN75_SO_WRITE_OFFSET0_length 1 +#define GEN7_SO_WRITE_OFFSET0_length 1 + +static inline uint32_t ATTRIBUTE_PURE +SO_WRITE_OFFSET0_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_WRITE_OFFSET0::Write Offset */ + + +#define GEN11_SO_WRITE_OFFSET0_WriteOffset_bits 30 +#define GEN10_SO_WRITE_OFFSET0_WriteOffset_bits 30 +#define GEN9_SO_WRITE_OFFSET0_WriteOffset_bits 30 +#define GEN8_SO_WRITE_OFFSET0_WriteOffset_bits 30 +#define GEN75_SO_WRITE_OFFSET0_WriteOffset_bits 30 +#define GEN7_SO_WRITE_OFFSET0_WriteOffset_bits 30 + +static inline uint32_t ATTRIBUTE_PURE +SO_WRITE_OFFSET0_WriteOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 30; + case 10: return 30; + case 9: return 30; + case 8: return 30; + case 7: + if (devinfo->is_haswell) { + return 30; + } else { + return 30; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SO_WRITE_OFFSET0_WriteOffset_start 2 +#define GEN10_SO_WRITE_OFFSET0_WriteOffset_start 2 +#define GEN9_SO_WRITE_OFFSET0_WriteOffset_start 2 +#define GEN8_SO_WRITE_OFFSET0_WriteOffset_start 2 +#define GEN75_SO_WRITE_OFFSET0_WriteOffset_start 2 +#define GEN7_SO_WRITE_OFFSET0_WriteOffset_start 2 + +static inline uint32_t ATTRIBUTE_PURE +SO_WRITE_OFFSET0_WriteOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_WRITE_OFFSET1 */ + + +#define GEN11_SO_WRITE_OFFSET1_length 1 +#define GEN10_SO_WRITE_OFFSET1_length 1 +#define GEN9_SO_WRITE_OFFSET1_length 1 +#define GEN8_SO_WRITE_OFFSET1_length 1 +#define GEN75_SO_WRITE_OFFSET1_length 1 +#define GEN7_SO_WRITE_OFFSET1_length 1 + +static inline uint32_t ATTRIBUTE_PURE +SO_WRITE_OFFSET1_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_WRITE_OFFSET1::Write Offset */ + + +#define GEN11_SO_WRITE_OFFSET1_WriteOffset_bits 30 +#define GEN10_SO_WRITE_OFFSET1_WriteOffset_bits 30 +#define GEN9_SO_WRITE_OFFSET1_WriteOffset_bits 30 +#define GEN8_SO_WRITE_OFFSET1_WriteOffset_bits 30 +#define GEN75_SO_WRITE_OFFSET1_WriteOffset_bits 30 +#define GEN7_SO_WRITE_OFFSET1_WriteOffset_bits 30 + +static inline uint32_t ATTRIBUTE_PURE +SO_WRITE_OFFSET1_WriteOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 30; + case 10: return 30; + case 9: return 30; + case 8: return 30; + case 7: + if (devinfo->is_haswell) { + return 30; + } else { + return 30; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SO_WRITE_OFFSET1_WriteOffset_start 2 +#define GEN10_SO_WRITE_OFFSET1_WriteOffset_start 2 +#define GEN9_SO_WRITE_OFFSET1_WriteOffset_start 2 +#define GEN8_SO_WRITE_OFFSET1_WriteOffset_start 2 +#define GEN75_SO_WRITE_OFFSET1_WriteOffset_start 2 +#define GEN7_SO_WRITE_OFFSET1_WriteOffset_start 2 + +static inline uint32_t ATTRIBUTE_PURE +SO_WRITE_OFFSET1_WriteOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_WRITE_OFFSET2 */ + + +#define GEN11_SO_WRITE_OFFSET2_length 1 +#define GEN10_SO_WRITE_OFFSET2_length 1 +#define GEN9_SO_WRITE_OFFSET2_length 1 +#define GEN8_SO_WRITE_OFFSET2_length 1 +#define GEN75_SO_WRITE_OFFSET2_length 1 +#define GEN7_SO_WRITE_OFFSET2_length 1 + +static inline uint32_t ATTRIBUTE_PURE +SO_WRITE_OFFSET2_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_WRITE_OFFSET2::Write Offset */ + + +#define GEN11_SO_WRITE_OFFSET2_WriteOffset_bits 30 +#define GEN10_SO_WRITE_OFFSET2_WriteOffset_bits 30 +#define GEN9_SO_WRITE_OFFSET2_WriteOffset_bits 30 +#define GEN8_SO_WRITE_OFFSET2_WriteOffset_bits 30 +#define GEN75_SO_WRITE_OFFSET2_WriteOffset_bits 30 +#define GEN7_SO_WRITE_OFFSET2_WriteOffset_bits 30 + +static inline uint32_t ATTRIBUTE_PURE +SO_WRITE_OFFSET2_WriteOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 30; + case 10: return 30; + case 9: return 30; + case 8: return 30; + case 7: + if (devinfo->is_haswell) { + return 30; + } else { + return 30; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SO_WRITE_OFFSET2_WriteOffset_start 2 +#define GEN10_SO_WRITE_OFFSET2_WriteOffset_start 2 +#define GEN9_SO_WRITE_OFFSET2_WriteOffset_start 2 +#define GEN8_SO_WRITE_OFFSET2_WriteOffset_start 2 +#define GEN75_SO_WRITE_OFFSET2_WriteOffset_start 2 +#define GEN7_SO_WRITE_OFFSET2_WriteOffset_start 2 + +static inline uint32_t ATTRIBUTE_PURE +SO_WRITE_OFFSET2_WriteOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_WRITE_OFFSET3 */ + + +#define GEN11_SO_WRITE_OFFSET3_length 1 +#define GEN10_SO_WRITE_OFFSET3_length 1 +#define GEN9_SO_WRITE_OFFSET3_length 1 +#define GEN8_SO_WRITE_OFFSET3_length 1 +#define GEN75_SO_WRITE_OFFSET3_length 1 +#define GEN7_SO_WRITE_OFFSET3_length 1 + +static inline uint32_t ATTRIBUTE_PURE +SO_WRITE_OFFSET3_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SO_WRITE_OFFSET3::Write Offset */ + + +#define GEN11_SO_WRITE_OFFSET3_WriteOffset_bits 30 +#define GEN10_SO_WRITE_OFFSET3_WriteOffset_bits 30 +#define GEN9_SO_WRITE_OFFSET3_WriteOffset_bits 30 +#define GEN8_SO_WRITE_OFFSET3_WriteOffset_bits 30 +#define GEN75_SO_WRITE_OFFSET3_WriteOffset_bits 30 +#define GEN7_SO_WRITE_OFFSET3_WriteOffset_bits 30 + +static inline uint32_t ATTRIBUTE_PURE +SO_WRITE_OFFSET3_WriteOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 30; + case 10: return 30; + case 9: return 30; + case 8: return 30; + case 7: + if (devinfo->is_haswell) { + return 30; + } else { + return 30; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_SO_WRITE_OFFSET3_WriteOffset_start 2 +#define GEN10_SO_WRITE_OFFSET3_WriteOffset_start 2 +#define GEN9_SO_WRITE_OFFSET3_WriteOffset_start 2 +#define GEN8_SO_WRITE_OFFSET3_WriteOffset_start 2 +#define GEN75_SO_WRITE_OFFSET3_WriteOffset_start 2 +#define GEN7_SO_WRITE_OFFSET3_WriteOffset_start 2 + +static inline uint32_t ATTRIBUTE_PURE +SO_WRITE_OFFSET3_WriteOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS */ + + +#define GEN11_STATE_BASE_ADDRESS_length 22 +#define GEN10_STATE_BASE_ADDRESS_length 22 +#define GEN9_STATE_BASE_ADDRESS_length 19 +#define GEN8_STATE_BASE_ADDRESS_length 16 +#define GEN75_STATE_BASE_ADDRESS_length 10 +#define GEN7_STATE_BASE_ADDRESS_length 10 +#define GEN6_STATE_BASE_ADDRESS_length 10 +#define GEN5_STATE_BASE_ADDRESS_length 8 +#define GEN45_STATE_BASE_ADDRESS_length 6 +#define GEN4_STATE_BASE_ADDRESS_length 6 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 22; + case 10: return 22; + case 9: return 19; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 10; + } else { + return 10; + } + case 6: return 10; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::3D Command Opcode */ + + +#define GEN11_STATE_BASE_ADDRESS_3DCommandOpcode_bits 3 +#define GEN10_STATE_BASE_ADDRESS_3DCommandOpcode_bits 3 +#define GEN9_STATE_BASE_ADDRESS_3DCommandOpcode_bits 3 +#define GEN8_STATE_BASE_ADDRESS_3DCommandOpcode_bits 3 +#define GEN75_STATE_BASE_ADDRESS_3DCommandOpcode_bits 3 +#define GEN7_STATE_BASE_ADDRESS_3DCommandOpcode_bits 3 +#define GEN6_STATE_BASE_ADDRESS_3DCommandOpcode_bits 3 +#define GEN5_STATE_BASE_ADDRESS_3DCommandOpcode_bits 3 +#define GEN45_STATE_BASE_ADDRESS_3DCommandOpcode_bits 3 +#define GEN4_STATE_BASE_ADDRESS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_BASE_ADDRESS_3DCommandOpcode_start 24 +#define GEN10_STATE_BASE_ADDRESS_3DCommandOpcode_start 24 +#define GEN9_STATE_BASE_ADDRESS_3DCommandOpcode_start 24 +#define GEN8_STATE_BASE_ADDRESS_3DCommandOpcode_start 24 +#define GEN75_STATE_BASE_ADDRESS_3DCommandOpcode_start 24 +#define GEN7_STATE_BASE_ADDRESS_3DCommandOpcode_start 24 +#define GEN6_STATE_BASE_ADDRESS_3DCommandOpcode_start 24 +#define GEN5_STATE_BASE_ADDRESS_3DCommandOpcode_start 24 +#define GEN45_STATE_BASE_ADDRESS_3DCommandOpcode_start 24 +#define GEN4_STATE_BASE_ADDRESS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 24; + case 4: + if (devinfo->is_g4x) { + return 24; + } else { + return 24; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::3D Command Sub Opcode */ + + +#define GEN11_STATE_BASE_ADDRESS_3DCommandSubOpcode_bits 8 +#define GEN10_STATE_BASE_ADDRESS_3DCommandSubOpcode_bits 8 +#define GEN9_STATE_BASE_ADDRESS_3DCommandSubOpcode_bits 8 +#define GEN8_STATE_BASE_ADDRESS_3DCommandSubOpcode_bits 8 +#define GEN75_STATE_BASE_ADDRESS_3DCommandSubOpcode_bits 8 +#define GEN7_STATE_BASE_ADDRESS_3DCommandSubOpcode_bits 8 +#define GEN6_STATE_BASE_ADDRESS_3DCommandSubOpcode_bits 8 +#define GEN5_STATE_BASE_ADDRESS_3DCommandSubOpcode_bits 8 +#define GEN45_STATE_BASE_ADDRESS_3DCommandSubOpcode_bits 8 +#define GEN4_STATE_BASE_ADDRESS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_BASE_ADDRESS_3DCommandSubOpcode_start 16 +#define GEN10_STATE_BASE_ADDRESS_3DCommandSubOpcode_start 16 +#define GEN9_STATE_BASE_ADDRESS_3DCommandSubOpcode_start 16 +#define GEN8_STATE_BASE_ADDRESS_3DCommandSubOpcode_start 16 +#define GEN75_STATE_BASE_ADDRESS_3DCommandSubOpcode_start 16 +#define GEN7_STATE_BASE_ADDRESS_3DCommandSubOpcode_start 16 +#define GEN6_STATE_BASE_ADDRESS_3DCommandSubOpcode_start 16 +#define GEN5_STATE_BASE_ADDRESS_3DCommandSubOpcode_start 16 +#define GEN45_STATE_BASE_ADDRESS_3DCommandSubOpcode_start 16 +#define GEN4_STATE_BASE_ADDRESS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::Bindless Sampler State Base Address */ + + +#define GEN11_STATE_BASE_ADDRESS_BindlessSamplerStateBaseAddress_bits 52 +#define GEN10_STATE_BASE_ADDRESS_BindlessSamplerStateBaseAddress_bits 52 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_BindlessSamplerStateBaseAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 52; + case 10: return 52; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_BASE_ADDRESS_BindlessSamplerStateBaseAddress_start 620 +#define GEN10_STATE_BASE_ADDRESS_BindlessSamplerStateBaseAddress_start 620 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_BindlessSamplerStateBaseAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 620; + case 10: return 620; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::Bindless Sampler State Base Address Modify Enable */ + + +#define GEN11_STATE_BASE_ADDRESS_BindlessSamplerStateBaseAddressModifyEnable_bits 1 +#define GEN10_STATE_BASE_ADDRESS_BindlessSamplerStateBaseAddressModifyEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_BindlessSamplerStateBaseAddressModifyEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_BASE_ADDRESS_BindlessSamplerStateBaseAddressModifyEnable_start 608 +#define GEN10_STATE_BASE_ADDRESS_BindlessSamplerStateBaseAddressModifyEnable_start 608 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_BindlessSamplerStateBaseAddressModifyEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 608; + case 10: return 608; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::Bindless Sampler State Buffer Size */ + + +#define GEN11_STATE_BASE_ADDRESS_BindlessSamplerStateBufferSize_bits 20 +#define GEN10_STATE_BASE_ADDRESS_BindlessSamplerStateBufferSize_bits 20 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_BindlessSamplerStateBufferSize_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 20; + case 10: return 20; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_BASE_ADDRESS_BindlessSamplerStateBufferSize_start 684 +#define GEN10_STATE_BASE_ADDRESS_BindlessSamplerStateBufferSize_start 684 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_BindlessSamplerStateBufferSize_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 684; + case 10: return 684; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::Bindless Sampler State MOCS */ + + +#define GEN11_STATE_BASE_ADDRESS_BindlessSamplerStateMOCS_bits 7 +#define GEN10_STATE_BASE_ADDRESS_BindlessSamplerStateMOCS_bits 7 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_BindlessSamplerStateMOCS_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_BASE_ADDRESS_BindlessSamplerStateMOCS_start 612 +#define GEN10_STATE_BASE_ADDRESS_BindlessSamplerStateMOCS_start 612 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_BindlessSamplerStateMOCS_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 612; + case 10: return 612; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::Bindless Surface State Base Address */ + + +#define GEN11_STATE_BASE_ADDRESS_BindlessSurfaceStateBaseAddress_bits 52 +#define GEN10_STATE_BASE_ADDRESS_BindlessSurfaceStateBaseAddress_bits 52 +#define GEN9_STATE_BASE_ADDRESS_BindlessSurfaceStateBaseAddress_bits 52 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_BindlessSurfaceStateBaseAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 52; + case 10: return 52; + case 9: return 52; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_BASE_ADDRESS_BindlessSurfaceStateBaseAddress_start 524 +#define GEN10_STATE_BASE_ADDRESS_BindlessSurfaceStateBaseAddress_start 524 +#define GEN9_STATE_BASE_ADDRESS_BindlessSurfaceStateBaseAddress_start 524 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_BindlessSurfaceStateBaseAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 524; + case 10: return 524; + case 9: return 524; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::Bindless Surface State Base Address Modify Enable */ + + +#define GEN11_STATE_BASE_ADDRESS_BindlessSurfaceStateBaseAddressModifyEnable_bits 1 +#define GEN10_STATE_BASE_ADDRESS_BindlessSurfaceStateBaseAddressModifyEnable_bits 1 +#define GEN9_STATE_BASE_ADDRESS_BindlessSurfaceStateBaseAddressModifyEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_BindlessSurfaceStateBaseAddressModifyEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_BASE_ADDRESS_BindlessSurfaceStateBaseAddressModifyEnable_start 512 +#define GEN10_STATE_BASE_ADDRESS_BindlessSurfaceStateBaseAddressModifyEnable_start 512 +#define GEN9_STATE_BASE_ADDRESS_BindlessSurfaceStateBaseAddressModifyEnable_start 512 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_BindlessSurfaceStateBaseAddressModifyEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 512; + case 10: return 512; + case 9: return 512; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::Bindless Surface State MOCS */ + + +#define GEN11_STATE_BASE_ADDRESS_BindlessSurfaceStateMOCS_bits 7 +#define GEN10_STATE_BASE_ADDRESS_BindlessSurfaceStateMOCS_bits 7 +#define GEN9_STATE_BASE_ADDRESS_BindlessSurfaceStateMOCS_bits 7 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_BindlessSurfaceStateMOCS_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_BASE_ADDRESS_BindlessSurfaceStateMOCS_start 516 +#define GEN10_STATE_BASE_ADDRESS_BindlessSurfaceStateMOCS_start 516 +#define GEN9_STATE_BASE_ADDRESS_BindlessSurfaceStateMOCS_start 516 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_BindlessSurfaceStateMOCS_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 516; + case 10: return 516; + case 9: return 516; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::Bindless Surface State Size */ + + +#define GEN11_STATE_BASE_ADDRESS_BindlessSurfaceStateSize_bits 20 +#define GEN10_STATE_BASE_ADDRESS_BindlessSurfaceStateSize_bits 20 +#define GEN9_STATE_BASE_ADDRESS_BindlessSurfaceStateSize_bits 20 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_BindlessSurfaceStateSize_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 20; + case 10: return 20; + case 9: return 20; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_BASE_ADDRESS_BindlessSurfaceStateSize_start 588 +#define GEN10_STATE_BASE_ADDRESS_BindlessSurfaceStateSize_start 588 +#define GEN9_STATE_BASE_ADDRESS_BindlessSurfaceStateSize_start 588 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_BindlessSurfaceStateSize_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 588; + case 10: return 588; + case 9: return 588; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::Command SubType */ + + +#define GEN11_STATE_BASE_ADDRESS_CommandSubType_bits 2 +#define GEN10_STATE_BASE_ADDRESS_CommandSubType_bits 2 +#define GEN9_STATE_BASE_ADDRESS_CommandSubType_bits 2 +#define GEN8_STATE_BASE_ADDRESS_CommandSubType_bits 2 +#define GEN75_STATE_BASE_ADDRESS_CommandSubType_bits 2 +#define GEN7_STATE_BASE_ADDRESS_CommandSubType_bits 2 +#define GEN6_STATE_BASE_ADDRESS_CommandSubType_bits 2 +#define GEN5_STATE_BASE_ADDRESS_CommandSubType_bits 2 +#define GEN45_STATE_BASE_ADDRESS_CommandSubType_bits 2 +#define GEN4_STATE_BASE_ADDRESS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_BASE_ADDRESS_CommandSubType_start 27 +#define GEN10_STATE_BASE_ADDRESS_CommandSubType_start 27 +#define GEN9_STATE_BASE_ADDRESS_CommandSubType_start 27 +#define GEN8_STATE_BASE_ADDRESS_CommandSubType_start 27 +#define GEN75_STATE_BASE_ADDRESS_CommandSubType_start 27 +#define GEN7_STATE_BASE_ADDRESS_CommandSubType_start 27 +#define GEN6_STATE_BASE_ADDRESS_CommandSubType_start 27 +#define GEN5_STATE_BASE_ADDRESS_CommandSubType_start 27 +#define GEN45_STATE_BASE_ADDRESS_CommandSubType_start 27 +#define GEN4_STATE_BASE_ADDRESS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::Command Type */ + + +#define GEN11_STATE_BASE_ADDRESS_CommandType_bits 3 +#define GEN10_STATE_BASE_ADDRESS_CommandType_bits 3 +#define GEN9_STATE_BASE_ADDRESS_CommandType_bits 3 +#define GEN8_STATE_BASE_ADDRESS_CommandType_bits 3 +#define GEN75_STATE_BASE_ADDRESS_CommandType_bits 3 +#define GEN7_STATE_BASE_ADDRESS_CommandType_bits 3 +#define GEN6_STATE_BASE_ADDRESS_CommandType_bits 3 +#define GEN5_STATE_BASE_ADDRESS_CommandType_bits 3 +#define GEN45_STATE_BASE_ADDRESS_CommandType_bits 3 +#define GEN4_STATE_BASE_ADDRESS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_BASE_ADDRESS_CommandType_start 29 +#define GEN10_STATE_BASE_ADDRESS_CommandType_start 29 +#define GEN9_STATE_BASE_ADDRESS_CommandType_start 29 +#define GEN8_STATE_BASE_ADDRESS_CommandType_start 29 +#define GEN75_STATE_BASE_ADDRESS_CommandType_start 29 +#define GEN7_STATE_BASE_ADDRESS_CommandType_start 29 +#define GEN6_STATE_BASE_ADDRESS_CommandType_start 29 +#define GEN5_STATE_BASE_ADDRESS_CommandType_start 29 +#define GEN45_STATE_BASE_ADDRESS_CommandType_start 29 +#define GEN4_STATE_BASE_ADDRESS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 29; + case 4: + if (devinfo->is_g4x) { + return 29; + } else { + return 29; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::DWord Length */ + + +#define GEN11_STATE_BASE_ADDRESS_DWordLength_bits 8 +#define GEN10_STATE_BASE_ADDRESS_DWordLength_bits 8 +#define GEN9_STATE_BASE_ADDRESS_DWordLength_bits 8 +#define GEN8_STATE_BASE_ADDRESS_DWordLength_bits 8 +#define GEN75_STATE_BASE_ADDRESS_DWordLength_bits 8 +#define GEN7_STATE_BASE_ADDRESS_DWordLength_bits 8 +#define GEN6_STATE_BASE_ADDRESS_DWordLength_bits 8 +#define GEN5_STATE_BASE_ADDRESS_DWordLength_bits 8 +#define GEN45_STATE_BASE_ADDRESS_DWordLength_bits 8 +#define GEN4_STATE_BASE_ADDRESS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_BASE_ADDRESS_DWordLength_start 0 +#define GEN10_STATE_BASE_ADDRESS_DWordLength_start 0 +#define GEN9_STATE_BASE_ADDRESS_DWordLength_start 0 +#define GEN8_STATE_BASE_ADDRESS_DWordLength_start 0 +#define GEN75_STATE_BASE_ADDRESS_DWordLength_start 0 +#define GEN7_STATE_BASE_ADDRESS_DWordLength_start 0 +#define GEN6_STATE_BASE_ADDRESS_DWordLength_start 0 +#define GEN5_STATE_BASE_ADDRESS_DWordLength_start 0 +#define GEN45_STATE_BASE_ADDRESS_DWordLength_start 0 +#define GEN4_STATE_BASE_ADDRESS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::Dynamic State Access Upper Bound */ + + +#define GEN75_STATE_BASE_ADDRESS_DynamicStateAccessUpperBound_bits 20 +#define GEN7_STATE_BASE_ADDRESS_DynamicStateAccessUpperBound_bits 20 +#define GEN6_STATE_BASE_ADDRESS_DynamicStateAccessUpperBound_bits 20 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_DynamicStateAccessUpperBound_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 20; + } else { + return 20; + } + case 6: return 20; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_STATE_BASE_ADDRESS_DynamicStateAccessUpperBound_start 236 +#define GEN7_STATE_BASE_ADDRESS_DynamicStateAccessUpperBound_start 236 +#define GEN6_STATE_BASE_ADDRESS_DynamicStateAccessUpperBound_start 236 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_DynamicStateAccessUpperBound_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 236; + } else { + return 236; + } + case 6: return 236; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::Dynamic State Access Upper Bound Modify Enable */ + + +#define GEN75_STATE_BASE_ADDRESS_DynamicStateAccessUpperBoundModifyEnable_bits 1 +#define GEN7_STATE_BASE_ADDRESS_DynamicStateAccessUpperBoundModifyEnable_bits 1 +#define GEN6_STATE_BASE_ADDRESS_DynamicStateAccessUpperBoundModifyEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_DynamicStateAccessUpperBoundModifyEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_STATE_BASE_ADDRESS_DynamicStateAccessUpperBoundModifyEnable_start 224 +#define GEN7_STATE_BASE_ADDRESS_DynamicStateAccessUpperBoundModifyEnable_start 224 +#define GEN6_STATE_BASE_ADDRESS_DynamicStateAccessUpperBoundModifyEnable_start 224 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_DynamicStateAccessUpperBoundModifyEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 224; + } else { + return 224; + } + case 6: return 224; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::Dynamic State Base Address */ + + +#define GEN11_STATE_BASE_ADDRESS_DynamicStateBaseAddress_bits 52 +#define GEN10_STATE_BASE_ADDRESS_DynamicStateBaseAddress_bits 52 +#define GEN9_STATE_BASE_ADDRESS_DynamicStateBaseAddress_bits 52 +#define GEN8_STATE_BASE_ADDRESS_DynamicStateBaseAddress_bits 52 +#define GEN75_STATE_BASE_ADDRESS_DynamicStateBaseAddress_bits 20 +#define GEN7_STATE_BASE_ADDRESS_DynamicStateBaseAddress_bits 20 +#define GEN6_STATE_BASE_ADDRESS_DynamicStateBaseAddress_bits 20 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_DynamicStateBaseAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 52; + case 10: return 52; + case 9: return 52; + case 8: return 52; + case 7: + if (devinfo->is_haswell) { + return 20; + } else { + return 20; + } + case 6: return 20; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_BASE_ADDRESS_DynamicStateBaseAddress_start 204 +#define GEN10_STATE_BASE_ADDRESS_DynamicStateBaseAddress_start 204 +#define GEN9_STATE_BASE_ADDRESS_DynamicStateBaseAddress_start 204 +#define GEN8_STATE_BASE_ADDRESS_DynamicStateBaseAddress_start 204 +#define GEN75_STATE_BASE_ADDRESS_DynamicStateBaseAddress_start 108 +#define GEN7_STATE_BASE_ADDRESS_DynamicStateBaseAddress_start 108 +#define GEN6_STATE_BASE_ADDRESS_DynamicStateBaseAddress_start 108 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_DynamicStateBaseAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 204; + case 10: return 204; + case 9: return 204; + case 8: return 204; + case 7: + if (devinfo->is_haswell) { + return 108; + } else { + return 108; + } + case 6: return 108; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::Dynamic State Base Address Modify Enable */ + + +#define GEN11_STATE_BASE_ADDRESS_DynamicStateBaseAddressModifyEnable_bits 1 +#define GEN10_STATE_BASE_ADDRESS_DynamicStateBaseAddressModifyEnable_bits 1 +#define GEN9_STATE_BASE_ADDRESS_DynamicStateBaseAddressModifyEnable_bits 1 +#define GEN8_STATE_BASE_ADDRESS_DynamicStateBaseAddressModifyEnable_bits 1 +#define GEN75_STATE_BASE_ADDRESS_DynamicStateBaseAddressModifyEnable_bits 1 +#define GEN7_STATE_BASE_ADDRESS_DynamicStateBaseAddressModifyEnable_bits 1 +#define GEN6_STATE_BASE_ADDRESS_DynamicStateBaseAddressModifyEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_DynamicStateBaseAddressModifyEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_BASE_ADDRESS_DynamicStateBaseAddressModifyEnable_start 192 +#define GEN10_STATE_BASE_ADDRESS_DynamicStateBaseAddressModifyEnable_start 192 +#define GEN9_STATE_BASE_ADDRESS_DynamicStateBaseAddressModifyEnable_start 192 +#define GEN8_STATE_BASE_ADDRESS_DynamicStateBaseAddressModifyEnable_start 192 +#define GEN75_STATE_BASE_ADDRESS_DynamicStateBaseAddressModifyEnable_start 96 +#define GEN7_STATE_BASE_ADDRESS_DynamicStateBaseAddressModifyEnable_start 96 +#define GEN6_STATE_BASE_ADDRESS_DynamicStateBaseAddressModifyEnable_start 96 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_DynamicStateBaseAddressModifyEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 192; + case 10: return 192; + case 9: return 192; + case 8: return 192; + case 7: + if (devinfo->is_haswell) { + return 96; + } else { + return 96; + } + case 6: return 96; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::Dynamic State Buffer Size */ + + +#define GEN11_STATE_BASE_ADDRESS_DynamicStateBufferSize_bits 20 +#define GEN10_STATE_BASE_ADDRESS_DynamicStateBufferSize_bits 20 +#define GEN9_STATE_BASE_ADDRESS_DynamicStateBufferSize_bits 20 +#define GEN8_STATE_BASE_ADDRESS_DynamicStateBufferSize_bits 20 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_DynamicStateBufferSize_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 20; + case 10: return 20; + case 9: return 20; + case 8: return 20; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_BASE_ADDRESS_DynamicStateBufferSize_start 428 +#define GEN10_STATE_BASE_ADDRESS_DynamicStateBufferSize_start 428 +#define GEN9_STATE_BASE_ADDRESS_DynamicStateBufferSize_start 428 +#define GEN8_STATE_BASE_ADDRESS_DynamicStateBufferSize_start 428 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_DynamicStateBufferSize_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 428; + case 10: return 428; + case 9: return 428; + case 8: return 428; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::Dynamic State Buffer Size Modify Enable */ + + +#define GEN11_STATE_BASE_ADDRESS_DynamicStateBufferSizeModifyEnable_bits 1 +#define GEN10_STATE_BASE_ADDRESS_DynamicStateBufferSizeModifyEnable_bits 1 +#define GEN9_STATE_BASE_ADDRESS_DynamicStateBufferSizeModifyEnable_bits 1 +#define GEN8_STATE_BASE_ADDRESS_DynamicStateBufferSizeModifyEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_DynamicStateBufferSizeModifyEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_BASE_ADDRESS_DynamicStateBufferSizeModifyEnable_start 416 +#define GEN10_STATE_BASE_ADDRESS_DynamicStateBufferSizeModifyEnable_start 416 +#define GEN9_STATE_BASE_ADDRESS_DynamicStateBufferSizeModifyEnable_start 416 +#define GEN8_STATE_BASE_ADDRESS_DynamicStateBufferSizeModifyEnable_start 416 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_DynamicStateBufferSizeModifyEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 416; + case 10: return 416; + case 9: return 416; + case 8: return 416; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::Dynamic State MOCS */ + + +#define GEN11_STATE_BASE_ADDRESS_DynamicStateMOCS_bits 7 +#define GEN10_STATE_BASE_ADDRESS_DynamicStateMOCS_bits 7 +#define GEN9_STATE_BASE_ADDRESS_DynamicStateMOCS_bits 7 +#define GEN8_STATE_BASE_ADDRESS_DynamicStateMOCS_bits 7 +#define GEN75_STATE_BASE_ADDRESS_DynamicStateMOCS_bits 4 +#define GEN7_STATE_BASE_ADDRESS_DynamicStateMOCS_bits 4 +#define GEN6_STATE_BASE_ADDRESS_DynamicStateMOCS_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_DynamicStateMOCS_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_BASE_ADDRESS_DynamicStateMOCS_start 196 +#define GEN10_STATE_BASE_ADDRESS_DynamicStateMOCS_start 196 +#define GEN9_STATE_BASE_ADDRESS_DynamicStateMOCS_start 196 +#define GEN8_STATE_BASE_ADDRESS_DynamicStateMOCS_start 196 +#define GEN75_STATE_BASE_ADDRESS_DynamicStateMOCS_start 104 +#define GEN7_STATE_BASE_ADDRESS_DynamicStateMOCS_start 104 +#define GEN6_STATE_BASE_ADDRESS_DynamicStateMOCS_start 104 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_DynamicStateMOCS_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 196; + case 10: return 196; + case 9: return 196; + case 8: return 196; + case 7: + if (devinfo->is_haswell) { + return 104; + } else { + return 104; + } + case 6: return 104; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::General State Access Upper Bound */ + + +#define GEN75_STATE_BASE_ADDRESS_GeneralStateAccessUpperBound_bits 20 +#define GEN7_STATE_BASE_ADDRESS_GeneralStateAccessUpperBound_bits 20 +#define GEN6_STATE_BASE_ADDRESS_GeneralStateAccessUpperBound_bits 20 +#define GEN5_STATE_BASE_ADDRESS_GeneralStateAccessUpperBound_bits 20 +#define GEN45_STATE_BASE_ADDRESS_GeneralStateAccessUpperBound_bits 20 +#define GEN4_STATE_BASE_ADDRESS_GeneralStateAccessUpperBound_bits 20 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_GeneralStateAccessUpperBound_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 20; + } else { + return 20; + } + case 6: return 20; + case 5: return 20; + case 4: + if (devinfo->is_g4x) { + return 20; + } else { + return 20; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_STATE_BASE_ADDRESS_GeneralStateAccessUpperBound_start 204 +#define GEN7_STATE_BASE_ADDRESS_GeneralStateAccessUpperBound_start 204 +#define GEN6_STATE_BASE_ADDRESS_GeneralStateAccessUpperBound_start 204 +#define GEN5_STATE_BASE_ADDRESS_GeneralStateAccessUpperBound_start 172 +#define GEN45_STATE_BASE_ADDRESS_GeneralStateAccessUpperBound_start 140 +#define GEN4_STATE_BASE_ADDRESS_GeneralStateAccessUpperBound_start 140 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_GeneralStateAccessUpperBound_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 204; + } else { + return 204; + } + case 6: return 204; + case 5: return 172; + case 4: + if (devinfo->is_g4x) { + return 140; + } else { + return 140; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::General State Access Upper Bound Modify Enable */ + + +#define GEN75_STATE_BASE_ADDRESS_GeneralStateAccessUpperBoundModifyEnable_bits 1 +#define GEN7_STATE_BASE_ADDRESS_GeneralStateAccessUpperBoundModifyEnable_bits 1 +#define GEN6_STATE_BASE_ADDRESS_GeneralStateAccessUpperBoundModifyEnable_bits 1 +#define GEN5_STATE_BASE_ADDRESS_GeneralStateAccessUpperBoundModifyEnable_bits 1 +#define GEN45_STATE_BASE_ADDRESS_GeneralStateAccessUpperBoundModifyEnable_bits 1 +#define GEN4_STATE_BASE_ADDRESS_GeneralStateAccessUpperBoundModifyEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_GeneralStateAccessUpperBoundModifyEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_STATE_BASE_ADDRESS_GeneralStateAccessUpperBoundModifyEnable_start 192 +#define GEN7_STATE_BASE_ADDRESS_GeneralStateAccessUpperBoundModifyEnable_start 192 +#define GEN6_STATE_BASE_ADDRESS_GeneralStateAccessUpperBoundModifyEnable_start 192 +#define GEN5_STATE_BASE_ADDRESS_GeneralStateAccessUpperBoundModifyEnable_start 160 +#define GEN45_STATE_BASE_ADDRESS_GeneralStateAccessUpperBoundModifyEnable_start 128 +#define GEN4_STATE_BASE_ADDRESS_GeneralStateAccessUpperBoundModifyEnable_start 128 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_GeneralStateAccessUpperBoundModifyEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 192; + } else { + return 192; + } + case 6: return 192; + case 5: return 160; + case 4: + if (devinfo->is_g4x) { + return 128; + } else { + return 128; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::General State Base Address */ + + +#define GEN11_STATE_BASE_ADDRESS_GeneralStateBaseAddress_bits 52 +#define GEN10_STATE_BASE_ADDRESS_GeneralStateBaseAddress_bits 52 +#define GEN9_STATE_BASE_ADDRESS_GeneralStateBaseAddress_bits 52 +#define GEN8_STATE_BASE_ADDRESS_GeneralStateBaseAddress_bits 52 +#define GEN75_STATE_BASE_ADDRESS_GeneralStateBaseAddress_bits 20 +#define GEN7_STATE_BASE_ADDRESS_GeneralStateBaseAddress_bits 20 +#define GEN6_STATE_BASE_ADDRESS_GeneralStateBaseAddress_bits 20 +#define GEN5_STATE_BASE_ADDRESS_GeneralStateBaseAddress_bits 20 +#define GEN45_STATE_BASE_ADDRESS_GeneralStateBaseAddress_bits 20 +#define GEN4_STATE_BASE_ADDRESS_GeneralStateBaseAddress_bits 20 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_GeneralStateBaseAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 52; + case 10: return 52; + case 9: return 52; + case 8: return 52; + case 7: + if (devinfo->is_haswell) { + return 20; + } else { + return 20; + } + case 6: return 20; + case 5: return 20; + case 4: + if (devinfo->is_g4x) { + return 20; + } else { + return 20; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_BASE_ADDRESS_GeneralStateBaseAddress_start 44 +#define GEN10_STATE_BASE_ADDRESS_GeneralStateBaseAddress_start 44 +#define GEN9_STATE_BASE_ADDRESS_GeneralStateBaseAddress_start 44 +#define GEN8_STATE_BASE_ADDRESS_GeneralStateBaseAddress_start 44 +#define GEN75_STATE_BASE_ADDRESS_GeneralStateBaseAddress_start 44 +#define GEN7_STATE_BASE_ADDRESS_GeneralStateBaseAddress_start 44 +#define GEN6_STATE_BASE_ADDRESS_GeneralStateBaseAddress_start 44 +#define GEN5_STATE_BASE_ADDRESS_GeneralStateBaseAddress_start 44 +#define GEN45_STATE_BASE_ADDRESS_GeneralStateBaseAddress_start 44 +#define GEN4_STATE_BASE_ADDRESS_GeneralStateBaseAddress_start 44 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_GeneralStateBaseAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 44; + case 10: return 44; + case 9: return 44; + case 8: return 44; + case 7: + if (devinfo->is_haswell) { + return 44; + } else { + return 44; + } + case 6: return 44; + case 5: return 44; + case 4: + if (devinfo->is_g4x) { + return 44; + } else { + return 44; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::General State Base Address Modify Enable */ + + +#define GEN11_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_bits 1 +#define GEN10_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_bits 1 +#define GEN9_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_bits 1 +#define GEN8_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_bits 1 +#define GEN75_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_bits 1 +#define GEN7_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_bits 1 +#define GEN6_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_bits 1 +#define GEN5_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_bits 1 +#define GEN45_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_bits 1 +#define GEN4_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_start 32 +#define GEN10_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_start 32 +#define GEN9_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_start 32 +#define GEN8_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_start 32 +#define GEN75_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_start 32 +#define GEN7_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_start 32 +#define GEN6_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_start 32 +#define GEN5_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_start 32 +#define GEN45_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_start 32 +#define GEN4_STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_start 32 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_GeneralStateBaseAddressModifyEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::General State Buffer Size */ + + +#define GEN11_STATE_BASE_ADDRESS_GeneralStateBufferSize_bits 20 +#define GEN10_STATE_BASE_ADDRESS_GeneralStateBufferSize_bits 20 +#define GEN9_STATE_BASE_ADDRESS_GeneralStateBufferSize_bits 20 +#define GEN8_STATE_BASE_ADDRESS_GeneralStateBufferSize_bits 20 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_GeneralStateBufferSize_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 20; + case 10: return 20; + case 9: return 20; + case 8: return 20; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_BASE_ADDRESS_GeneralStateBufferSize_start 396 +#define GEN10_STATE_BASE_ADDRESS_GeneralStateBufferSize_start 396 +#define GEN9_STATE_BASE_ADDRESS_GeneralStateBufferSize_start 396 +#define GEN8_STATE_BASE_ADDRESS_GeneralStateBufferSize_start 396 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_GeneralStateBufferSize_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 396; + case 10: return 396; + case 9: return 396; + case 8: return 396; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::General State Buffer Size Modify Enable */ + + +#define GEN11_STATE_BASE_ADDRESS_GeneralStateBufferSizeModifyEnable_bits 1 +#define GEN10_STATE_BASE_ADDRESS_GeneralStateBufferSizeModifyEnable_bits 1 +#define GEN9_STATE_BASE_ADDRESS_GeneralStateBufferSizeModifyEnable_bits 1 +#define GEN8_STATE_BASE_ADDRESS_GeneralStateBufferSizeModifyEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_GeneralStateBufferSizeModifyEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_BASE_ADDRESS_GeneralStateBufferSizeModifyEnable_start 384 +#define GEN10_STATE_BASE_ADDRESS_GeneralStateBufferSizeModifyEnable_start 384 +#define GEN9_STATE_BASE_ADDRESS_GeneralStateBufferSizeModifyEnable_start 384 +#define GEN8_STATE_BASE_ADDRESS_GeneralStateBufferSizeModifyEnable_start 384 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_GeneralStateBufferSizeModifyEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 384; + case 10: return 384; + case 9: return 384; + case 8: return 384; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::General State MOCS */ + + +#define GEN11_STATE_BASE_ADDRESS_GeneralStateMOCS_bits 7 +#define GEN10_STATE_BASE_ADDRESS_GeneralStateMOCS_bits 7 +#define GEN9_STATE_BASE_ADDRESS_GeneralStateMOCS_bits 7 +#define GEN8_STATE_BASE_ADDRESS_GeneralStateMOCS_bits 7 +#define GEN75_STATE_BASE_ADDRESS_GeneralStateMOCS_bits 4 +#define GEN7_STATE_BASE_ADDRESS_GeneralStateMOCS_bits 4 +#define GEN6_STATE_BASE_ADDRESS_GeneralStateMOCS_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_GeneralStateMOCS_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_BASE_ADDRESS_GeneralStateMOCS_start 36 +#define GEN10_STATE_BASE_ADDRESS_GeneralStateMOCS_start 36 +#define GEN9_STATE_BASE_ADDRESS_GeneralStateMOCS_start 36 +#define GEN8_STATE_BASE_ADDRESS_GeneralStateMOCS_start 36 +#define GEN75_STATE_BASE_ADDRESS_GeneralStateMOCS_start 40 +#define GEN7_STATE_BASE_ADDRESS_GeneralStateMOCS_start 40 +#define GEN6_STATE_BASE_ADDRESS_GeneralStateMOCS_start 40 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_GeneralStateMOCS_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 36; + case 10: return 36; + case 9: return 36; + case 8: return 36; + case 7: + if (devinfo->is_haswell) { + return 40; + } else { + return 40; + } + case 6: return 40; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::Indirect Object Access Upper Bound */ + + +#define GEN75_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBound_bits 20 +#define GEN7_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBound_bits 20 +#define GEN6_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBound_bits 20 +#define GEN5_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBound_bits 20 +#define GEN45_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBound_bits 20 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_IndirectObjectAccessUpperBound_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 20; + } else { + return 20; + } + case 6: return 20; + case 5: return 20; + case 4: + if (devinfo->is_g4x) { + return 20; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBound_start 268 +#define GEN7_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBound_start 268 +#define GEN6_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBound_start 268 +#define GEN5_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBound_start 204 +#define GEN45_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBound_start 172 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_IndirectObjectAccessUpperBound_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 268; + } else { + return 268; + } + case 6: return 268; + case 5: return 204; + case 4: + if (devinfo->is_g4x) { + return 172; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::Indirect Object Access Upper Bound Modify Enable */ + + +#define GEN75_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBoundModifyEnable_bits 1 +#define GEN7_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBoundModifyEnable_bits 1 +#define GEN6_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBoundModifyEnable_bits 1 +#define GEN5_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBoundModifyEnable_bits 1 +#define GEN45_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBoundModifyEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_IndirectObjectAccessUpperBoundModifyEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBoundModifyEnable_start 256 +#define GEN7_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBoundModifyEnable_start 256 +#define GEN6_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBoundModifyEnable_start 256 +#define GEN5_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBoundModifyEnable_start 192 +#define GEN45_STATE_BASE_ADDRESS_IndirectObjectAccessUpperBoundModifyEnable_start 160 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_IndirectObjectAccessUpperBoundModifyEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 256; + } else { + return 256; + } + case 6: return 256; + case 5: return 192; + case 4: + if (devinfo->is_g4x) { + return 160; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::Indirect Object Base Address */ + + +#define GEN11_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_bits 52 +#define GEN10_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_bits 52 +#define GEN9_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_bits 52 +#define GEN8_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_bits 52 +#define GEN75_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_bits 20 +#define GEN7_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_bits 20 +#define GEN6_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_bits 20 +#define GEN5_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_bits 20 +#define GEN45_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_bits 20 +#define GEN4_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_bits 20 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_IndirectObjectBaseAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 52; + case 10: return 52; + case 9: return 52; + case 8: return 52; + case 7: + if (devinfo->is_haswell) { + return 20; + } else { + return 20; + } + case 6: return 20; + case 5: return 20; + case 4: + if (devinfo->is_g4x) { + return 20; + } else { + return 20; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_start 268 +#define GEN10_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_start 268 +#define GEN9_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_start 268 +#define GEN8_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_start 268 +#define GEN75_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_start 140 +#define GEN7_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_start 140 +#define GEN6_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_start 140 +#define GEN5_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_start 108 +#define GEN45_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_start 108 +#define GEN4_STATE_BASE_ADDRESS_IndirectObjectBaseAddress_start 108 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_IndirectObjectBaseAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 268; + case 10: return 268; + case 9: return 268; + case 8: return 268; + case 7: + if (devinfo->is_haswell) { + return 140; + } else { + return 140; + } + case 6: return 140; + case 5: return 108; + case 4: + if (devinfo->is_g4x) { + return 108; + } else { + return 108; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::Indirect Object Base Address Modify Enable */ + + +#define GEN11_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_bits 1 +#define GEN10_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_bits 1 +#define GEN9_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_bits 1 +#define GEN8_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_bits 1 +#define GEN75_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_bits 1 +#define GEN7_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_bits 1 +#define GEN6_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_bits 1 +#define GEN5_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_bits 1 +#define GEN45_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_bits 1 +#define GEN4_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_start 256 +#define GEN10_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_start 256 +#define GEN9_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_start 256 +#define GEN8_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_start 256 +#define GEN75_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_start 128 +#define GEN7_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_start 128 +#define GEN6_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_start 128 +#define GEN5_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_start 96 +#define GEN45_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_start 96 +#define GEN4_STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_start 96 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_IndirectObjectBaseAddressModifyEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 256; + case 10: return 256; + case 9: return 256; + case 8: return 256; + case 7: + if (devinfo->is_haswell) { + return 128; + } else { + return 128; + } + case 6: return 128; + case 5: return 96; + case 4: + if (devinfo->is_g4x) { + return 96; + } else { + return 96; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::Indirect Object Buffer Size */ + + +#define GEN11_STATE_BASE_ADDRESS_IndirectObjectBufferSize_bits 20 +#define GEN10_STATE_BASE_ADDRESS_IndirectObjectBufferSize_bits 20 +#define GEN9_STATE_BASE_ADDRESS_IndirectObjectBufferSize_bits 20 +#define GEN8_STATE_BASE_ADDRESS_IndirectObjectBufferSize_bits 20 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_IndirectObjectBufferSize_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 20; + case 10: return 20; + case 9: return 20; + case 8: return 20; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_BASE_ADDRESS_IndirectObjectBufferSize_start 460 +#define GEN10_STATE_BASE_ADDRESS_IndirectObjectBufferSize_start 460 +#define GEN9_STATE_BASE_ADDRESS_IndirectObjectBufferSize_start 460 +#define GEN8_STATE_BASE_ADDRESS_IndirectObjectBufferSize_start 460 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_IndirectObjectBufferSize_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 460; + case 10: return 460; + case 9: return 460; + case 8: return 460; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::Indirect Object Buffer Size Modify Enable */ + + +#define GEN11_STATE_BASE_ADDRESS_IndirectObjectBufferSizeModifyEnable_bits 1 +#define GEN10_STATE_BASE_ADDRESS_IndirectObjectBufferSizeModifyEnable_bits 1 +#define GEN9_STATE_BASE_ADDRESS_IndirectObjectBufferSizeModifyEnable_bits 1 +#define GEN8_STATE_BASE_ADDRESS_IndirectObjectBufferSizeModifyEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_IndirectObjectBufferSizeModifyEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_BASE_ADDRESS_IndirectObjectBufferSizeModifyEnable_start 448 +#define GEN10_STATE_BASE_ADDRESS_IndirectObjectBufferSizeModifyEnable_start 448 +#define GEN9_STATE_BASE_ADDRESS_IndirectObjectBufferSizeModifyEnable_start 448 +#define GEN8_STATE_BASE_ADDRESS_IndirectObjectBufferSizeModifyEnable_start 448 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_IndirectObjectBufferSizeModifyEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 448; + case 10: return 448; + case 9: return 448; + case 8: return 448; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::Indirect Object MOCS */ + + +#define GEN11_STATE_BASE_ADDRESS_IndirectObjectMOCS_bits 7 +#define GEN10_STATE_BASE_ADDRESS_IndirectObjectMOCS_bits 7 +#define GEN9_STATE_BASE_ADDRESS_IndirectObjectMOCS_bits 7 +#define GEN8_STATE_BASE_ADDRESS_IndirectObjectMOCS_bits 7 +#define GEN75_STATE_BASE_ADDRESS_IndirectObjectMOCS_bits 4 +#define GEN7_STATE_BASE_ADDRESS_IndirectObjectMOCS_bits 4 +#define GEN6_STATE_BASE_ADDRESS_IndirectObjectMOCS_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_IndirectObjectMOCS_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_BASE_ADDRESS_IndirectObjectMOCS_start 260 +#define GEN10_STATE_BASE_ADDRESS_IndirectObjectMOCS_start 260 +#define GEN9_STATE_BASE_ADDRESS_IndirectObjectMOCS_start 260 +#define GEN8_STATE_BASE_ADDRESS_IndirectObjectMOCS_start 260 +#define GEN75_STATE_BASE_ADDRESS_IndirectObjectMOCS_start 136 +#define GEN7_STATE_BASE_ADDRESS_IndirectObjectMOCS_start 136 +#define GEN6_STATE_BASE_ADDRESS_IndirectObjectMOCS_start 136 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_IndirectObjectMOCS_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 260; + case 10: return 260; + case 9: return 260; + case 8: return 260; + case 7: + if (devinfo->is_haswell) { + return 136; + } else { + return 136; + } + case 6: return 136; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::Instruction Access Upper Bound */ + + +#define GEN75_STATE_BASE_ADDRESS_InstructionAccessUpperBound_bits 20 +#define GEN7_STATE_BASE_ADDRESS_InstructionAccessUpperBound_bits 20 +#define GEN6_STATE_BASE_ADDRESS_InstructionAccessUpperBound_bits 20 +#define GEN5_STATE_BASE_ADDRESS_InstructionAccessUpperBound_bits 20 +#define GEN4_STATE_BASE_ADDRESS_InstructionAccessUpperBound_bits 20 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_InstructionAccessUpperBound_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 20; + } else { + return 20; + } + case 6: return 20; + case 5: return 20; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 20; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_STATE_BASE_ADDRESS_InstructionAccessUpperBound_start 300 +#define GEN7_STATE_BASE_ADDRESS_InstructionAccessUpperBound_start 300 +#define GEN6_STATE_BASE_ADDRESS_InstructionAccessUpperBound_start 300 +#define GEN5_STATE_BASE_ADDRESS_InstructionAccessUpperBound_start 236 +#define GEN4_STATE_BASE_ADDRESS_InstructionAccessUpperBound_start 172 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_InstructionAccessUpperBound_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 300; + } else { + return 300; + } + case 6: return 300; + case 5: return 236; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 172; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::Instruction Access Upper Bound Modify Enable */ + + +#define GEN75_STATE_BASE_ADDRESS_InstructionAccessUpperBoundModifyEnable_bits 1 +#define GEN7_STATE_BASE_ADDRESS_InstructionAccessUpperBoundModifyEnable_bits 1 +#define GEN6_STATE_BASE_ADDRESS_InstructionAccessUpperBoundModifyEnable_bits 1 +#define GEN5_STATE_BASE_ADDRESS_InstructionAccessUpperBoundModifyEnable_bits 1 +#define GEN4_STATE_BASE_ADDRESS_InstructionAccessUpperBoundModifyEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_InstructionAccessUpperBoundModifyEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_STATE_BASE_ADDRESS_InstructionAccessUpperBoundModifyEnable_start 288 +#define GEN7_STATE_BASE_ADDRESS_InstructionAccessUpperBoundModifyEnable_start 288 +#define GEN6_STATE_BASE_ADDRESS_InstructionAccessUpperBoundModifyEnable_start 288 +#define GEN5_STATE_BASE_ADDRESS_InstructionAccessUpperBoundModifyEnable_start 224 +#define GEN4_STATE_BASE_ADDRESS_InstructionAccessUpperBoundModifyEnable_start 160 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_InstructionAccessUpperBoundModifyEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 288; + } else { + return 288; + } + case 6: return 288; + case 5: return 224; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 160; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::Instruction Base Address */ + + +#define GEN11_STATE_BASE_ADDRESS_InstructionBaseAddress_bits 52 +#define GEN10_STATE_BASE_ADDRESS_InstructionBaseAddress_bits 52 +#define GEN9_STATE_BASE_ADDRESS_InstructionBaseAddress_bits 52 +#define GEN8_STATE_BASE_ADDRESS_InstructionBaseAddress_bits 52 +#define GEN75_STATE_BASE_ADDRESS_InstructionBaseAddress_bits 20 +#define GEN7_STATE_BASE_ADDRESS_InstructionBaseAddress_bits 20 +#define GEN6_STATE_BASE_ADDRESS_InstructionBaseAddress_bits 20 +#define GEN5_STATE_BASE_ADDRESS_InstructionBaseAddress_bits 20 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_InstructionBaseAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 52; + case 10: return 52; + case 9: return 52; + case 8: return 52; + case 7: + if (devinfo->is_haswell) { + return 20; + } else { + return 20; + } + case 6: return 20; + case 5: return 20; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_BASE_ADDRESS_InstructionBaseAddress_start 332 +#define GEN10_STATE_BASE_ADDRESS_InstructionBaseAddress_start 332 +#define GEN9_STATE_BASE_ADDRESS_InstructionBaseAddress_start 332 +#define GEN8_STATE_BASE_ADDRESS_InstructionBaseAddress_start 332 +#define GEN75_STATE_BASE_ADDRESS_InstructionBaseAddress_start 172 +#define GEN7_STATE_BASE_ADDRESS_InstructionBaseAddress_start 172 +#define GEN6_STATE_BASE_ADDRESS_InstructionBaseAddress_start 172 +#define GEN5_STATE_BASE_ADDRESS_InstructionBaseAddress_start 140 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_InstructionBaseAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 332; + case 10: return 332; + case 9: return 332; + case 8: return 332; + case 7: + if (devinfo->is_haswell) { + return 172; + } else { + return 172; + } + case 6: return 172; + case 5: return 140; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::Instruction Base Address Modify Enable */ + + +#define GEN11_STATE_BASE_ADDRESS_InstructionBaseAddressModifyEnable_bits 1 +#define GEN10_STATE_BASE_ADDRESS_InstructionBaseAddressModifyEnable_bits 1 +#define GEN9_STATE_BASE_ADDRESS_InstructionBaseAddressModifyEnable_bits 1 +#define GEN8_STATE_BASE_ADDRESS_InstructionBaseAddressModifyEnable_bits 1 +#define GEN75_STATE_BASE_ADDRESS_InstructionBaseAddressModifyEnable_bits 1 +#define GEN7_STATE_BASE_ADDRESS_InstructionBaseAddressModifyEnable_bits 1 +#define GEN6_STATE_BASE_ADDRESS_InstructionBaseAddressModifyEnable_bits 1 +#define GEN5_STATE_BASE_ADDRESS_InstructionBaseAddressModifyEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_InstructionBaseAddressModifyEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_BASE_ADDRESS_InstructionBaseAddressModifyEnable_start 320 +#define GEN10_STATE_BASE_ADDRESS_InstructionBaseAddressModifyEnable_start 320 +#define GEN9_STATE_BASE_ADDRESS_InstructionBaseAddressModifyEnable_start 320 +#define GEN8_STATE_BASE_ADDRESS_InstructionBaseAddressModifyEnable_start 320 +#define GEN75_STATE_BASE_ADDRESS_InstructionBaseAddressModifyEnable_start 160 +#define GEN7_STATE_BASE_ADDRESS_InstructionBaseAddressModifyEnable_start 160 +#define GEN6_STATE_BASE_ADDRESS_InstructionBaseAddressModifyEnable_start 160 +#define GEN5_STATE_BASE_ADDRESS_InstructionBaseAddressModifyEnable_start 128 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_InstructionBaseAddressModifyEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 320; + case 10: return 320; + case 9: return 320; + case 8: return 320; + case 7: + if (devinfo->is_haswell) { + return 160; + } else { + return 160; + } + case 6: return 160; + case 5: return 128; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::Instruction Buffer Size */ + + +#define GEN11_STATE_BASE_ADDRESS_InstructionBufferSize_bits 20 +#define GEN10_STATE_BASE_ADDRESS_InstructionBufferSize_bits 20 +#define GEN9_STATE_BASE_ADDRESS_InstructionBufferSize_bits 20 +#define GEN8_STATE_BASE_ADDRESS_InstructionBufferSize_bits 20 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_InstructionBufferSize_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 20; + case 10: return 20; + case 9: return 20; + case 8: return 20; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_BASE_ADDRESS_InstructionBufferSize_start 492 +#define GEN10_STATE_BASE_ADDRESS_InstructionBufferSize_start 492 +#define GEN9_STATE_BASE_ADDRESS_InstructionBufferSize_start 492 +#define GEN8_STATE_BASE_ADDRESS_InstructionBufferSize_start 492 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_InstructionBufferSize_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 492; + case 10: return 492; + case 9: return 492; + case 8: return 492; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::Instruction Buffer size Modify Enable */ + + +#define GEN11_STATE_BASE_ADDRESS_InstructionBuffersizeModifyEnable_bits 1 +#define GEN10_STATE_BASE_ADDRESS_InstructionBuffersizeModifyEnable_bits 1 +#define GEN9_STATE_BASE_ADDRESS_InstructionBuffersizeModifyEnable_bits 1 +#define GEN8_STATE_BASE_ADDRESS_InstructionBuffersizeModifyEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_InstructionBuffersizeModifyEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_BASE_ADDRESS_InstructionBuffersizeModifyEnable_start 480 +#define GEN10_STATE_BASE_ADDRESS_InstructionBuffersizeModifyEnable_start 480 +#define GEN9_STATE_BASE_ADDRESS_InstructionBuffersizeModifyEnable_start 480 +#define GEN8_STATE_BASE_ADDRESS_InstructionBuffersizeModifyEnable_start 480 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_InstructionBuffersizeModifyEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 480; + case 10: return 480; + case 9: return 480; + case 8: return 480; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::Instruction MOCS */ + + +#define GEN11_STATE_BASE_ADDRESS_InstructionMOCS_bits 7 +#define GEN10_STATE_BASE_ADDRESS_InstructionMOCS_bits 7 +#define GEN9_STATE_BASE_ADDRESS_InstructionMOCS_bits 7 +#define GEN8_STATE_BASE_ADDRESS_InstructionMOCS_bits 7 +#define GEN75_STATE_BASE_ADDRESS_InstructionMOCS_bits 4 +#define GEN7_STATE_BASE_ADDRESS_InstructionMOCS_bits 4 +#define GEN6_STATE_BASE_ADDRESS_InstructionMOCS_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_InstructionMOCS_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_BASE_ADDRESS_InstructionMOCS_start 324 +#define GEN10_STATE_BASE_ADDRESS_InstructionMOCS_start 324 +#define GEN9_STATE_BASE_ADDRESS_InstructionMOCS_start 324 +#define GEN8_STATE_BASE_ADDRESS_InstructionMOCS_start 324 +#define GEN75_STATE_BASE_ADDRESS_InstructionMOCS_start 168 +#define GEN7_STATE_BASE_ADDRESS_InstructionMOCS_start 168 +#define GEN6_STATE_BASE_ADDRESS_InstructionMOCS_start 168 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_InstructionMOCS_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 324; + case 10: return 324; + case 9: return 324; + case 8: return 324; + case 7: + if (devinfo->is_haswell) { + return 168; + } else { + return 168; + } + case 6: return 168; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::Stateless Data Port Access Force Write Thru */ + + +#define GEN7_STATE_BASE_ADDRESS_StatelessDataPortAccessForceWriteThru_bits 1 +#define GEN6_STATE_BASE_ADDRESS_StatelessDataPortAccessForceWriteThru_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_StatelessDataPortAccessForceWriteThru_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN7_STATE_BASE_ADDRESS_StatelessDataPortAccessForceWriteThru_start 35 +#define GEN6_STATE_BASE_ADDRESS_StatelessDataPortAccessForceWriteThru_start 35 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_StatelessDataPortAccessForceWriteThru_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 35; + } + case 6: return 35; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::Stateless Data Port Access MOCS */ + + +#define GEN11_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_bits 7 +#define GEN10_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_bits 7 +#define GEN9_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_bits 7 +#define GEN8_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_bits 7 +#define GEN75_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_bits 4 +#define GEN7_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_bits 4 +#define GEN6_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_start 112 +#define GEN10_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_start 112 +#define GEN9_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_start 112 +#define GEN8_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_start 112 +#define GEN75_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_start 36 +#define GEN7_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_start 36 +#define GEN6_STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_start 36 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_StatelessDataPortAccessMOCS_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 112; + case 10: return 112; + case 9: return 112; + case 8: return 112; + case 7: + if (devinfo->is_haswell) { + return 36; + } else { + return 36; + } + case 6: return 36; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::Surface State Base Address */ + + +#define GEN11_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_bits 52 +#define GEN10_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_bits 52 +#define GEN9_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_bits 52 +#define GEN8_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_bits 52 +#define GEN75_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_bits 20 +#define GEN7_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_bits 20 +#define GEN6_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_bits 20 +#define GEN5_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_bits 20 +#define GEN45_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_bits 20 +#define GEN4_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_bits 20 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_SurfaceStateBaseAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 52; + case 10: return 52; + case 9: return 52; + case 8: return 52; + case 7: + if (devinfo->is_haswell) { + return 20; + } else { + return 20; + } + case 6: return 20; + case 5: return 20; + case 4: + if (devinfo->is_g4x) { + return 20; + } else { + return 20; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_start 140 +#define GEN10_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_start 140 +#define GEN9_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_start 140 +#define GEN8_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_start 140 +#define GEN75_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_start 76 +#define GEN7_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_start 76 +#define GEN6_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_start 76 +#define GEN5_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_start 76 +#define GEN45_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_start 76 +#define GEN4_STATE_BASE_ADDRESS_SurfaceStateBaseAddress_start 76 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_SurfaceStateBaseAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 140; + case 10: return 140; + case 9: return 140; + case 8: return 140; + case 7: + if (devinfo->is_haswell) { + return 76; + } else { + return 76; + } + case 6: return 76; + case 5: return 76; + case 4: + if (devinfo->is_g4x) { + return 76; + } else { + return 76; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::Surface State Base Address Modify Enable */ + + +#define GEN11_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_bits 1 +#define GEN10_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_bits 1 +#define GEN9_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_bits 1 +#define GEN8_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_bits 1 +#define GEN75_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_bits 1 +#define GEN7_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_bits 1 +#define GEN6_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_bits 1 +#define GEN5_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_bits 1 +#define GEN45_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_bits 1 +#define GEN4_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_start 128 +#define GEN10_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_start 128 +#define GEN9_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_start 128 +#define GEN8_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_start 128 +#define GEN75_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_start 64 +#define GEN7_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_start 64 +#define GEN6_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_start 64 +#define GEN5_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_start 64 +#define GEN45_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_start 64 +#define GEN4_STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_start 64 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_SurfaceStateBaseAddressModifyEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 128; + case 10: return 128; + case 9: return 128; + case 8: return 128; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 64; + case 5: return 64; + case 4: + if (devinfo->is_g4x) { + return 64; + } else { + return 64; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_BASE_ADDRESS::Surface State MOCS */ + + +#define GEN11_STATE_BASE_ADDRESS_SurfaceStateMOCS_bits 7 +#define GEN10_STATE_BASE_ADDRESS_SurfaceStateMOCS_bits 7 +#define GEN9_STATE_BASE_ADDRESS_SurfaceStateMOCS_bits 7 +#define GEN8_STATE_BASE_ADDRESS_SurfaceStateMOCS_bits 7 +#define GEN75_STATE_BASE_ADDRESS_SurfaceStateMOCS_bits 4 +#define GEN7_STATE_BASE_ADDRESS_SurfaceStateMOCS_bits 4 +#define GEN6_STATE_BASE_ADDRESS_SurfaceStateMOCS_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_SurfaceStateMOCS_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_BASE_ADDRESS_SurfaceStateMOCS_start 132 +#define GEN10_STATE_BASE_ADDRESS_SurfaceStateMOCS_start 132 +#define GEN9_STATE_BASE_ADDRESS_SurfaceStateMOCS_start 132 +#define GEN8_STATE_BASE_ADDRESS_SurfaceStateMOCS_start 132 +#define GEN75_STATE_BASE_ADDRESS_SurfaceStateMOCS_start 72 +#define GEN7_STATE_BASE_ADDRESS_SurfaceStateMOCS_start 72 +#define GEN6_STATE_BASE_ADDRESS_SurfaceStateMOCS_start 72 + +static inline uint32_t ATTRIBUTE_PURE +STATE_BASE_ADDRESS_SurfaceStateMOCS_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 132; + case 10: return 132; + case 9: return 132; + case 8: return 132; + case 7: + if (devinfo->is_haswell) { + return 72; + } else { + return 72; + } + case 6: return 72; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_PREFETCH */ + + +#define GEN9_STATE_PREFETCH_length 2 +#define GEN8_STATE_PREFETCH_length 2 +#define GEN75_STATE_PREFETCH_length 2 +#define GEN7_STATE_PREFETCH_length 2 +#define GEN6_STATE_PREFETCH_length 2 + +static inline uint32_t ATTRIBUTE_PURE +STATE_PREFETCH_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_PREFETCH::3D Command Opcode */ + + +#define GEN9_STATE_PREFETCH_3DCommandOpcode_bits 3 +#define GEN8_STATE_PREFETCH_3DCommandOpcode_bits 3 +#define GEN75_STATE_PREFETCH_3DCommandOpcode_bits 3 +#define GEN7_STATE_PREFETCH_3DCommandOpcode_bits 3 +#define GEN6_STATE_PREFETCH_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +STATE_PREFETCH_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_STATE_PREFETCH_3DCommandOpcode_start 24 +#define GEN8_STATE_PREFETCH_3DCommandOpcode_start 24 +#define GEN75_STATE_PREFETCH_3DCommandOpcode_start 24 +#define GEN7_STATE_PREFETCH_3DCommandOpcode_start 24 +#define GEN6_STATE_PREFETCH_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +STATE_PREFETCH_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_PREFETCH::3D Command Sub Opcode */ + + +#define GEN9_STATE_PREFETCH_3DCommandSubOpcode_bits 8 +#define GEN8_STATE_PREFETCH_3DCommandSubOpcode_bits 8 +#define GEN75_STATE_PREFETCH_3DCommandSubOpcode_bits 8 +#define GEN7_STATE_PREFETCH_3DCommandSubOpcode_bits 8 +#define GEN6_STATE_PREFETCH_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +STATE_PREFETCH_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_STATE_PREFETCH_3DCommandSubOpcode_start 16 +#define GEN8_STATE_PREFETCH_3DCommandSubOpcode_start 16 +#define GEN75_STATE_PREFETCH_3DCommandSubOpcode_start 16 +#define GEN7_STATE_PREFETCH_3DCommandSubOpcode_start 16 +#define GEN6_STATE_PREFETCH_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +STATE_PREFETCH_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_PREFETCH::Command SubType */ + + +#define GEN9_STATE_PREFETCH_CommandSubType_bits 2 +#define GEN8_STATE_PREFETCH_CommandSubType_bits 2 +#define GEN75_STATE_PREFETCH_CommandSubType_bits 2 +#define GEN7_STATE_PREFETCH_CommandSubType_bits 2 +#define GEN6_STATE_PREFETCH_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +STATE_PREFETCH_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_STATE_PREFETCH_CommandSubType_start 27 +#define GEN8_STATE_PREFETCH_CommandSubType_start 27 +#define GEN75_STATE_PREFETCH_CommandSubType_start 27 +#define GEN7_STATE_PREFETCH_CommandSubType_start 27 +#define GEN6_STATE_PREFETCH_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +STATE_PREFETCH_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_PREFETCH::Command Type */ + + +#define GEN9_STATE_PREFETCH_CommandType_bits 3 +#define GEN8_STATE_PREFETCH_CommandType_bits 3 +#define GEN75_STATE_PREFETCH_CommandType_bits 3 +#define GEN7_STATE_PREFETCH_CommandType_bits 3 +#define GEN6_STATE_PREFETCH_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +STATE_PREFETCH_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_STATE_PREFETCH_CommandType_start 29 +#define GEN8_STATE_PREFETCH_CommandType_start 29 +#define GEN75_STATE_PREFETCH_CommandType_start 29 +#define GEN7_STATE_PREFETCH_CommandType_start 29 +#define GEN6_STATE_PREFETCH_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +STATE_PREFETCH_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_PREFETCH::DWord Length */ + + +#define GEN9_STATE_PREFETCH_DWordLength_bits 8 +#define GEN8_STATE_PREFETCH_DWordLength_bits 8 +#define GEN75_STATE_PREFETCH_DWordLength_bits 8 +#define GEN7_STATE_PREFETCH_DWordLength_bits 8 +#define GEN6_STATE_PREFETCH_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +STATE_PREFETCH_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_STATE_PREFETCH_DWordLength_start 0 +#define GEN8_STATE_PREFETCH_DWordLength_start 0 +#define GEN75_STATE_PREFETCH_DWordLength_start 0 +#define GEN7_STATE_PREFETCH_DWordLength_start 0 +#define GEN6_STATE_PREFETCH_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +STATE_PREFETCH_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_PREFETCH::Prefetch Count */ + + +#define GEN9_STATE_PREFETCH_PrefetchCount_bits 3 +#define GEN8_STATE_PREFETCH_PrefetchCount_bits 3 +#define GEN75_STATE_PREFETCH_PrefetchCount_bits 3 +#define GEN7_STATE_PREFETCH_PrefetchCount_bits 3 +#define GEN6_STATE_PREFETCH_PrefetchCount_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +STATE_PREFETCH_PrefetchCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_STATE_PREFETCH_PrefetchCount_start 32 +#define GEN8_STATE_PREFETCH_PrefetchCount_start 32 +#define GEN75_STATE_PREFETCH_PrefetchCount_start 32 +#define GEN7_STATE_PREFETCH_PrefetchCount_start 32 +#define GEN6_STATE_PREFETCH_PrefetchCount_start 32 + +static inline uint32_t ATTRIBUTE_PURE +STATE_PREFETCH_PrefetchCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_PREFETCH::Prefetch Pointer */ + + +#define GEN9_STATE_PREFETCH_PrefetchPointer_bits 26 +#define GEN8_STATE_PREFETCH_PrefetchPointer_bits 26 +#define GEN75_STATE_PREFETCH_PrefetchPointer_bits 26 +#define GEN7_STATE_PREFETCH_PrefetchPointer_bits 26 +#define GEN6_STATE_PREFETCH_PrefetchPointer_bits 26 + +static inline uint32_t ATTRIBUTE_PURE +STATE_PREFETCH_PrefetchPointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 26; + case 8: return 26; + case 7: + if (devinfo->is_haswell) { + return 26; + } else { + return 26; + } + case 6: return 26; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_STATE_PREFETCH_PrefetchPointer_start 38 +#define GEN8_STATE_PREFETCH_PrefetchPointer_start 38 +#define GEN75_STATE_PREFETCH_PrefetchPointer_start 38 +#define GEN7_STATE_PREFETCH_PrefetchPointer_start 38 +#define GEN6_STATE_PREFETCH_PrefetchPointer_start 38 + +static inline uint32_t ATTRIBUTE_PURE +STATE_PREFETCH_PrefetchPointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 38; + case 8: return 38; + case 7: + if (devinfo->is_haswell) { + return 38; + } else { + return 38; + } + case 6: return 38; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_SIP */ + + +#define GEN11_STATE_SIP_length 3 +#define GEN10_STATE_SIP_length 3 +#define GEN9_STATE_SIP_length 3 +#define GEN8_STATE_SIP_length 3 +#define GEN75_STATE_SIP_length 2 +#define GEN7_STATE_SIP_length 2 +#define GEN6_STATE_SIP_length 2 +#define GEN5_STATE_SIP_length 2 +#define GEN45_STATE_SIP_length 2 +#define GEN4_STATE_SIP_length 2 + +static inline uint32_t ATTRIBUTE_PURE +STATE_SIP_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_SIP::3D Command Opcode */ + + +#define GEN11_STATE_SIP_3DCommandOpcode_bits 3 +#define GEN10_STATE_SIP_3DCommandOpcode_bits 3 +#define GEN9_STATE_SIP_3DCommandOpcode_bits 3 +#define GEN8_STATE_SIP_3DCommandOpcode_bits 3 +#define GEN75_STATE_SIP_3DCommandOpcode_bits 3 +#define GEN7_STATE_SIP_3DCommandOpcode_bits 3 +#define GEN6_STATE_SIP_3DCommandOpcode_bits 3 +#define GEN5_STATE_SIP_3DCommandOpcode_bits 3 +#define GEN45_STATE_SIP_3DCommandOpcode_bits 3 +#define GEN4_STATE_SIP_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +STATE_SIP_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_SIP_3DCommandOpcode_start 24 +#define GEN10_STATE_SIP_3DCommandOpcode_start 24 +#define GEN9_STATE_SIP_3DCommandOpcode_start 24 +#define GEN8_STATE_SIP_3DCommandOpcode_start 24 +#define GEN75_STATE_SIP_3DCommandOpcode_start 24 +#define GEN7_STATE_SIP_3DCommandOpcode_start 24 +#define GEN6_STATE_SIP_3DCommandOpcode_start 24 +#define GEN5_STATE_SIP_3DCommandOpcode_start 24 +#define GEN45_STATE_SIP_3DCommandOpcode_start 24 +#define GEN4_STATE_SIP_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +STATE_SIP_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 24; + case 4: + if (devinfo->is_g4x) { + return 24; + } else { + return 24; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_SIP::3D Command Sub Opcode */ + + +#define GEN11_STATE_SIP_3DCommandSubOpcode_bits 8 +#define GEN10_STATE_SIP_3DCommandSubOpcode_bits 8 +#define GEN9_STATE_SIP_3DCommandSubOpcode_bits 8 +#define GEN8_STATE_SIP_3DCommandSubOpcode_bits 8 +#define GEN75_STATE_SIP_3DCommandSubOpcode_bits 8 +#define GEN7_STATE_SIP_3DCommandSubOpcode_bits 8 +#define GEN6_STATE_SIP_3DCommandSubOpcode_bits 8 +#define GEN5_STATE_SIP_3DCommandSubOpcode_bits 8 +#define GEN45_STATE_SIP_3DCommandSubOpcode_bits 8 +#define GEN4_STATE_SIP_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +STATE_SIP_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_SIP_3DCommandSubOpcode_start 16 +#define GEN10_STATE_SIP_3DCommandSubOpcode_start 16 +#define GEN9_STATE_SIP_3DCommandSubOpcode_start 16 +#define GEN8_STATE_SIP_3DCommandSubOpcode_start 16 +#define GEN75_STATE_SIP_3DCommandSubOpcode_start 16 +#define GEN7_STATE_SIP_3DCommandSubOpcode_start 16 +#define GEN6_STATE_SIP_3DCommandSubOpcode_start 16 +#define GEN5_STATE_SIP_3DCommandSubOpcode_start 16 +#define GEN45_STATE_SIP_3DCommandSubOpcode_start 16 +#define GEN4_STATE_SIP_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +STATE_SIP_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_SIP::Command SubType */ + + +#define GEN11_STATE_SIP_CommandSubType_bits 2 +#define GEN10_STATE_SIP_CommandSubType_bits 2 +#define GEN9_STATE_SIP_CommandSubType_bits 2 +#define GEN8_STATE_SIP_CommandSubType_bits 2 +#define GEN75_STATE_SIP_CommandSubType_bits 2 +#define GEN7_STATE_SIP_CommandSubType_bits 2 +#define GEN6_STATE_SIP_CommandSubType_bits 2 +#define GEN5_STATE_SIP_CommandSubType_bits 2 +#define GEN45_STATE_SIP_CommandSubType_bits 2 +#define GEN4_STATE_SIP_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +STATE_SIP_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_SIP_CommandSubType_start 27 +#define GEN10_STATE_SIP_CommandSubType_start 27 +#define GEN9_STATE_SIP_CommandSubType_start 27 +#define GEN8_STATE_SIP_CommandSubType_start 27 +#define GEN75_STATE_SIP_CommandSubType_start 27 +#define GEN7_STATE_SIP_CommandSubType_start 27 +#define GEN6_STATE_SIP_CommandSubType_start 27 +#define GEN5_STATE_SIP_CommandSubType_start 27 +#define GEN45_STATE_SIP_CommandSubType_start 27 +#define GEN4_STATE_SIP_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +STATE_SIP_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_SIP::Command Type */ + + +#define GEN11_STATE_SIP_CommandType_bits 3 +#define GEN10_STATE_SIP_CommandType_bits 3 +#define GEN9_STATE_SIP_CommandType_bits 3 +#define GEN8_STATE_SIP_CommandType_bits 3 +#define GEN75_STATE_SIP_CommandType_bits 3 +#define GEN7_STATE_SIP_CommandType_bits 3 +#define GEN6_STATE_SIP_CommandType_bits 3 +#define GEN5_STATE_SIP_CommandType_bits 3 +#define GEN45_STATE_SIP_CommandType_bits 3 +#define GEN4_STATE_SIP_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +STATE_SIP_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_SIP_CommandType_start 29 +#define GEN10_STATE_SIP_CommandType_start 29 +#define GEN9_STATE_SIP_CommandType_start 29 +#define GEN8_STATE_SIP_CommandType_start 29 +#define GEN75_STATE_SIP_CommandType_start 29 +#define GEN7_STATE_SIP_CommandType_start 29 +#define GEN6_STATE_SIP_CommandType_start 29 +#define GEN5_STATE_SIP_CommandType_start 29 +#define GEN45_STATE_SIP_CommandType_start 29 +#define GEN4_STATE_SIP_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +STATE_SIP_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 29; + case 5: return 29; + case 4: + if (devinfo->is_g4x) { + return 29; + } else { + return 29; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_SIP::DWord Length */ + + +#define GEN11_STATE_SIP_DWordLength_bits 8 +#define GEN10_STATE_SIP_DWordLength_bits 8 +#define GEN9_STATE_SIP_DWordLength_bits 8 +#define GEN8_STATE_SIP_DWordLength_bits 8 +#define GEN75_STATE_SIP_DWordLength_bits 8 +#define GEN7_STATE_SIP_DWordLength_bits 8 +#define GEN6_STATE_SIP_DWordLength_bits 8 +#define GEN5_STATE_SIP_DWordLength_bits 8 +#define GEN45_STATE_SIP_DWordLength_bits 8 +#define GEN4_STATE_SIP_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +STATE_SIP_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_SIP_DWordLength_start 0 +#define GEN10_STATE_SIP_DWordLength_start 0 +#define GEN9_STATE_SIP_DWordLength_start 0 +#define GEN8_STATE_SIP_DWordLength_start 0 +#define GEN75_STATE_SIP_DWordLength_start 0 +#define GEN7_STATE_SIP_DWordLength_start 0 +#define GEN6_STATE_SIP_DWordLength_start 0 +#define GEN5_STATE_SIP_DWordLength_start 0 +#define GEN45_STATE_SIP_DWordLength_start 0 +#define GEN4_STATE_SIP_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +STATE_SIP_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* STATE_SIP::System Instruction Pointer */ + + +#define GEN11_STATE_SIP_SystemInstructionPointer_bits 60 +#define GEN10_STATE_SIP_SystemInstructionPointer_bits 60 +#define GEN9_STATE_SIP_SystemInstructionPointer_bits 60 +#define GEN8_STATE_SIP_SystemInstructionPointer_bits 60 +#define GEN75_STATE_SIP_SystemInstructionPointer_bits 28 +#define GEN7_STATE_SIP_SystemInstructionPointer_bits 28 +#define GEN6_STATE_SIP_SystemInstructionPointer_bits 28 +#define GEN5_STATE_SIP_SystemInstructionPointer_bits 28 +#define GEN45_STATE_SIP_SystemInstructionPointer_bits 28 +#define GEN4_STATE_SIP_SystemInstructionPointer_bits 28 + +static inline uint32_t ATTRIBUTE_PURE +STATE_SIP_SystemInstructionPointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 60; + case 10: return 60; + case 9: return 60; + case 8: return 60; + case 7: + if (devinfo->is_haswell) { + return 28; + } else { + return 28; + } + case 6: return 28; + case 5: return 28; + case 4: + if (devinfo->is_g4x) { + return 28; + } else { + return 28; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_STATE_SIP_SystemInstructionPointer_start 36 +#define GEN10_STATE_SIP_SystemInstructionPointer_start 36 +#define GEN9_STATE_SIP_SystemInstructionPointer_start 36 +#define GEN8_STATE_SIP_SystemInstructionPointer_start 36 +#define GEN75_STATE_SIP_SystemInstructionPointer_start 36 +#define GEN7_STATE_SIP_SystemInstructionPointer_start 36 +#define GEN6_STATE_SIP_SystemInstructionPointer_start 36 +#define GEN5_STATE_SIP_SystemInstructionPointer_start 36 +#define GEN45_STATE_SIP_SystemInstructionPointer_start 36 +#define GEN4_STATE_SIP_SystemInstructionPointer_start 36 + +static inline uint32_t ATTRIBUTE_PURE +STATE_SIP_SystemInstructionPointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 36; + case 10: return 36; + case 9: return 36; + case 8: return 36; + case 7: + if (devinfo->is_haswell) { + return 36; + } else { + return 36; + } + case 6: return 36; + case 5: return 36; + case 4: + if (devinfo->is_g4x) { + return 36; + } else { + return 36; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SWTESS_BASE_ADDRESS */ + + +#define GEN8_SWTESS_BASE_ADDRESS_length 2 +#define GEN75_SWTESS_BASE_ADDRESS_length 2 +#define GEN7_SWTESS_BASE_ADDRESS_length 2 + +static inline uint32_t ATTRIBUTE_PURE +SWTESS_BASE_ADDRESS_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SWTESS_BASE_ADDRESS::3D Command Opcode */ + + +#define GEN8_SWTESS_BASE_ADDRESS_3DCommandOpcode_bits 3 +#define GEN75_SWTESS_BASE_ADDRESS_3DCommandOpcode_bits 3 +#define GEN7_SWTESS_BASE_ADDRESS_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +SWTESS_BASE_ADDRESS_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_SWTESS_BASE_ADDRESS_3DCommandOpcode_start 24 +#define GEN75_SWTESS_BASE_ADDRESS_3DCommandOpcode_start 24 +#define GEN7_SWTESS_BASE_ADDRESS_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +SWTESS_BASE_ADDRESS_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SWTESS_BASE_ADDRESS::3D Command Sub Opcode */ + + +#define GEN8_SWTESS_BASE_ADDRESS_3DCommandSubOpcode_bits 8 +#define GEN75_SWTESS_BASE_ADDRESS_3DCommandSubOpcode_bits 8 +#define GEN7_SWTESS_BASE_ADDRESS_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SWTESS_BASE_ADDRESS_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_SWTESS_BASE_ADDRESS_3DCommandSubOpcode_start 16 +#define GEN75_SWTESS_BASE_ADDRESS_3DCommandSubOpcode_start 16 +#define GEN7_SWTESS_BASE_ADDRESS_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +SWTESS_BASE_ADDRESS_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SWTESS_BASE_ADDRESS::Command SubType */ + + +#define GEN8_SWTESS_BASE_ADDRESS_CommandSubType_bits 2 +#define GEN75_SWTESS_BASE_ADDRESS_CommandSubType_bits 2 +#define GEN7_SWTESS_BASE_ADDRESS_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +SWTESS_BASE_ADDRESS_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_SWTESS_BASE_ADDRESS_CommandSubType_start 27 +#define GEN75_SWTESS_BASE_ADDRESS_CommandSubType_start 27 +#define GEN7_SWTESS_BASE_ADDRESS_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +SWTESS_BASE_ADDRESS_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SWTESS_BASE_ADDRESS::Command Type */ + + +#define GEN8_SWTESS_BASE_ADDRESS_CommandType_bits 3 +#define GEN75_SWTESS_BASE_ADDRESS_CommandType_bits 3 +#define GEN7_SWTESS_BASE_ADDRESS_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +SWTESS_BASE_ADDRESS_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_SWTESS_BASE_ADDRESS_CommandType_start 29 +#define GEN75_SWTESS_BASE_ADDRESS_CommandType_start 29 +#define GEN7_SWTESS_BASE_ADDRESS_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +SWTESS_BASE_ADDRESS_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 29; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SWTESS_BASE_ADDRESS::DWord Length */ + + +#define GEN8_SWTESS_BASE_ADDRESS_DWordLength_bits 8 +#define GEN75_SWTESS_BASE_ADDRESS_DWordLength_bits 8 +#define GEN7_SWTESS_BASE_ADDRESS_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +SWTESS_BASE_ADDRESS_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_SWTESS_BASE_ADDRESS_DWordLength_start 0 +#define GEN75_SWTESS_BASE_ADDRESS_DWordLength_start 0 +#define GEN7_SWTESS_BASE_ADDRESS_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +SWTESS_BASE_ADDRESS_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SWTESS_BASE_ADDRESS::SW Tessellation Base Address */ + + +#define GEN8_SWTESS_BASE_ADDRESS_SWTessellationBaseAddress_bits 36 +#define GEN75_SWTESS_BASE_ADDRESS_SWTessellationBaseAddress_bits 20 +#define GEN7_SWTESS_BASE_ADDRESS_SWTessellationBaseAddress_bits 20 + +static inline uint32_t ATTRIBUTE_PURE +SWTESS_BASE_ADDRESS_SWTessellationBaseAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 36; + case 7: + if (devinfo->is_haswell) { + return 20; + } else { + return 20; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_SWTESS_BASE_ADDRESS_SWTessellationBaseAddress_start 44 +#define GEN75_SWTESS_BASE_ADDRESS_SWTessellationBaseAddress_start 44 +#define GEN7_SWTESS_BASE_ADDRESS_SWTessellationBaseAddress_start 44 + +static inline uint32_t ATTRIBUTE_PURE +SWTESS_BASE_ADDRESS_SWTessellationBaseAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 44; + case 7: + if (devinfo->is_haswell) { + return 44; + } else { + return 44; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* SWTESS_BASE_ADDRESS::SW Tessellation MOCS */ + + +#define GEN8_SWTESS_BASE_ADDRESS_SWTessellationMOCS_bits 4 +#define GEN75_SWTESS_BASE_ADDRESS_SWTessellationMOCS_bits 4 +#define GEN7_SWTESS_BASE_ADDRESS_SWTessellationMOCS_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +SWTESS_BASE_ADDRESS_SWTessellationMOCS_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN8_SWTESS_BASE_ADDRESS_SWTessellationMOCS_start 40 +#define GEN75_SWTESS_BASE_ADDRESS_SWTessellationMOCS_start 40 +#define GEN7_SWTESS_BASE_ADDRESS_SWTessellationMOCS_start 40 + +static inline uint32_t ATTRIBUTE_PURE +SWTESS_BASE_ADDRESS_SWTessellationMOCS_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 40; + case 7: + if (devinfo->is_haswell) { + return 40; + } else { + return 40; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* URB_FENCE */ + + +#define GEN5_URB_FENCE_length 3 +#define GEN45_URB_FENCE_length 3 +#define GEN4_URB_FENCE_length 3 + +static inline uint32_t ATTRIBUTE_PURE +URB_FENCE_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* URB_FENCE::3D Command Opcode */ + + +#define GEN5_URB_FENCE_3DCommandOpcode_bits 3 +#define GEN45_URB_FENCE_3DCommandOpcode_bits 3 +#define GEN4_URB_FENCE_3DCommandOpcode_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +URB_FENCE_3DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_URB_FENCE_3DCommandOpcode_start 24 +#define GEN45_URB_FENCE_3DCommandOpcode_start 24 +#define GEN4_URB_FENCE_3DCommandOpcode_start 24 + +static inline uint32_t ATTRIBUTE_PURE +URB_FENCE_3DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 24; + case 4: + if (devinfo->is_g4x) { + return 24; + } else { + return 24; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* URB_FENCE::3D Command Sub Opcode */ + + +#define GEN5_URB_FENCE_3DCommandSubOpcode_bits 8 +#define GEN45_URB_FENCE_3DCommandSubOpcode_bits 8 +#define GEN4_URB_FENCE_3DCommandSubOpcode_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +URB_FENCE_3DCommandSubOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_URB_FENCE_3DCommandSubOpcode_start 16 +#define GEN45_URB_FENCE_3DCommandSubOpcode_start 16 +#define GEN4_URB_FENCE_3DCommandSubOpcode_start 16 + +static inline uint32_t ATTRIBUTE_PURE +URB_FENCE_3DCommandSubOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* URB_FENCE::CLIP Fence */ + + +#define GEN5_URB_FENCE_CLIPFence_bits 10 +#define GEN45_URB_FENCE_CLIPFence_bits 10 +#define GEN4_URB_FENCE_CLIPFence_bits 10 + +static inline uint32_t ATTRIBUTE_PURE +URB_FENCE_CLIPFence_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 10; + case 4: + if (devinfo->is_g4x) { + return 10; + } else { + return 10; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_URB_FENCE_CLIPFence_start 52 +#define GEN45_URB_FENCE_CLIPFence_start 52 +#define GEN4_URB_FENCE_CLIPFence_start 52 + +static inline uint32_t ATTRIBUTE_PURE +URB_FENCE_CLIPFence_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 52; + case 4: + if (devinfo->is_g4x) { + return 52; + } else { + return 52; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* URB_FENCE::CLIP Unit URB Reallocation Request */ + + +#define GEN5_URB_FENCE_CLIPUnitURBReallocationRequest_bits 1 +#define GEN45_URB_FENCE_CLIPUnitURBReallocationRequest_bits 1 +#define GEN4_URB_FENCE_CLIPUnitURBReallocationRequest_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +URB_FENCE_CLIPUnitURBReallocationRequest_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_URB_FENCE_CLIPUnitURBReallocationRequest_start 10 +#define GEN45_URB_FENCE_CLIPUnitURBReallocationRequest_start 10 +#define GEN4_URB_FENCE_CLIPUnitURBReallocationRequest_start 10 + +static inline uint32_t ATTRIBUTE_PURE +URB_FENCE_CLIPUnitURBReallocationRequest_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 10; + case 4: + if (devinfo->is_g4x) { + return 10; + } else { + return 10; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* URB_FENCE::CS Fence */ + + +#define GEN5_URB_FENCE_CSFence_bits 11 +#define GEN45_URB_FENCE_CSFence_bits 11 +#define GEN4_URB_FENCE_CSFence_bits 11 + +static inline uint32_t ATTRIBUTE_PURE +URB_FENCE_CSFence_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 11; + case 4: + if (devinfo->is_g4x) { + return 11; + } else { + return 11; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_URB_FENCE_CSFence_start 84 +#define GEN45_URB_FENCE_CSFence_start 84 +#define GEN4_URB_FENCE_CSFence_start 84 + +static inline uint32_t ATTRIBUTE_PURE +URB_FENCE_CSFence_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 84; + case 4: + if (devinfo->is_g4x) { + return 84; + } else { + return 84; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* URB_FENCE::CS Unit URB Reallocation Request */ + + +#define GEN5_URB_FENCE_CSUnitURBReallocationRequest_bits 1 +#define GEN45_URB_FENCE_CSUnitURBReallocationRequest_bits 1 +#define GEN4_URB_FENCE_CSUnitURBReallocationRequest_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +URB_FENCE_CSUnitURBReallocationRequest_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_URB_FENCE_CSUnitURBReallocationRequest_start 13 +#define GEN45_URB_FENCE_CSUnitURBReallocationRequest_start 13 +#define GEN4_URB_FENCE_CSUnitURBReallocationRequest_start 13 + +static inline uint32_t ATTRIBUTE_PURE +URB_FENCE_CSUnitURBReallocationRequest_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 13; + case 4: + if (devinfo->is_g4x) { + return 13; + } else { + return 13; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* URB_FENCE::Command SubType */ + + +#define GEN5_URB_FENCE_CommandSubType_bits 2 +#define GEN45_URB_FENCE_CommandSubType_bits 2 +#define GEN4_URB_FENCE_CommandSubType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +URB_FENCE_CommandSubType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_URB_FENCE_CommandSubType_start 27 +#define GEN45_URB_FENCE_CommandSubType_start 27 +#define GEN4_URB_FENCE_CommandSubType_start 27 + +static inline uint32_t ATTRIBUTE_PURE +URB_FENCE_CommandSubType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* URB_FENCE::Command Type */ + + +#define GEN5_URB_FENCE_CommandType_bits 3 +#define GEN45_URB_FENCE_CommandType_bits 3 +#define GEN4_URB_FENCE_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +URB_FENCE_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_URB_FENCE_CommandType_start 29 +#define GEN45_URB_FENCE_CommandType_start 29 +#define GEN4_URB_FENCE_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +URB_FENCE_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 29; + case 4: + if (devinfo->is_g4x) { + return 29; + } else { + return 29; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* URB_FENCE::DWord Length */ + + +#define GEN5_URB_FENCE_DWordLength_bits 8 +#define GEN45_URB_FENCE_DWordLength_bits 8 +#define GEN4_URB_FENCE_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +URB_FENCE_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_URB_FENCE_DWordLength_start 0 +#define GEN45_URB_FENCE_DWordLength_start 0 +#define GEN4_URB_FENCE_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +URB_FENCE_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* URB_FENCE::GS Fence */ + + +#define GEN5_URB_FENCE_GSFence_bits 10 +#define GEN45_URB_FENCE_GSFence_bits 10 +#define GEN4_URB_FENCE_GSFence_bits 10 + +static inline uint32_t ATTRIBUTE_PURE +URB_FENCE_GSFence_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 10; + case 4: + if (devinfo->is_g4x) { + return 10; + } else { + return 10; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_URB_FENCE_GSFence_start 42 +#define GEN45_URB_FENCE_GSFence_start 42 +#define GEN4_URB_FENCE_GSFence_start 42 + +static inline uint32_t ATTRIBUTE_PURE +URB_FENCE_GSFence_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 42; + case 4: + if (devinfo->is_g4x) { + return 42; + } else { + return 42; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* URB_FENCE::GS Unit URB Reallocation Request */ + + +#define GEN5_URB_FENCE_GSUnitURBReallocationRequest_bits 1 +#define GEN45_URB_FENCE_GSUnitURBReallocationRequest_bits 1 +#define GEN4_URB_FENCE_GSUnitURBReallocationRequest_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +URB_FENCE_GSUnitURBReallocationRequest_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_URB_FENCE_GSUnitURBReallocationRequest_start 9 +#define GEN45_URB_FENCE_GSUnitURBReallocationRequest_start 9 +#define GEN4_URB_FENCE_GSUnitURBReallocationRequest_start 9 + +static inline uint32_t ATTRIBUTE_PURE +URB_FENCE_GSUnitURBReallocationRequest_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 9; + case 4: + if (devinfo->is_g4x) { + return 9; + } else { + return 9; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* URB_FENCE::SF Fence */ + + +#define GEN5_URB_FENCE_SFFence_bits 10 +#define GEN45_URB_FENCE_SFFence_bits 10 +#define GEN4_URB_FENCE_SFFence_bits 10 + +static inline uint32_t ATTRIBUTE_PURE +URB_FENCE_SFFence_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 10; + case 4: + if (devinfo->is_g4x) { + return 10; + } else { + return 10; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_URB_FENCE_SFFence_start 64 +#define GEN45_URB_FENCE_SFFence_start 64 +#define GEN4_URB_FENCE_SFFence_start 64 + +static inline uint32_t ATTRIBUTE_PURE +URB_FENCE_SFFence_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 64; + case 4: + if (devinfo->is_g4x) { + return 64; + } else { + return 64; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* URB_FENCE::SF Unit URB Reallocation Request */ + + +#define GEN5_URB_FENCE_SFUnitURBReallocationRequest_bits 1 +#define GEN45_URB_FENCE_SFUnitURBReallocationRequest_bits 1 +#define GEN4_URB_FENCE_SFUnitURBReallocationRequest_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +URB_FENCE_SFUnitURBReallocationRequest_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_URB_FENCE_SFUnitURBReallocationRequest_start 11 +#define GEN45_URB_FENCE_SFUnitURBReallocationRequest_start 11 +#define GEN4_URB_FENCE_SFUnitURBReallocationRequest_start 11 + +static inline uint32_t ATTRIBUTE_PURE +URB_FENCE_SFUnitURBReallocationRequest_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 11; + case 4: + if (devinfo->is_g4x) { + return 11; + } else { + return 11; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* URB_FENCE::VFE Fence */ + + +#define GEN5_URB_FENCE_VFEFence_bits 10 +#define GEN45_URB_FENCE_VFEFence_bits 10 +#define GEN4_URB_FENCE_VFEFence_bits 10 + +static inline uint32_t ATTRIBUTE_PURE +URB_FENCE_VFEFence_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 10; + case 4: + if (devinfo->is_g4x) { + return 10; + } else { + return 10; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_URB_FENCE_VFEFence_start 74 +#define GEN45_URB_FENCE_VFEFence_start 74 +#define GEN4_URB_FENCE_VFEFence_start 74 + +static inline uint32_t ATTRIBUTE_PURE +URB_FENCE_VFEFence_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 74; + case 4: + if (devinfo->is_g4x) { + return 74; + } else { + return 74; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* URB_FENCE::VFE Unit URB Reallocation Request */ + + +#define GEN5_URB_FENCE_VFEUnitURBReallocationRequest_bits 1 +#define GEN45_URB_FENCE_VFEUnitURBReallocationRequest_bits 1 +#define GEN4_URB_FENCE_VFEUnitURBReallocationRequest_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +URB_FENCE_VFEUnitURBReallocationRequest_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_URB_FENCE_VFEUnitURBReallocationRequest_start 12 +#define GEN45_URB_FENCE_VFEUnitURBReallocationRequest_start 12 +#define GEN4_URB_FENCE_VFEUnitURBReallocationRequest_start 12 + +static inline uint32_t ATTRIBUTE_PURE +URB_FENCE_VFEUnitURBReallocationRequest_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 12; + case 4: + if (devinfo->is_g4x) { + return 12; + } else { + return 12; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* URB_FENCE::VS Fence */ + + +#define GEN5_URB_FENCE_VSFence_bits 10 +#define GEN45_URB_FENCE_VSFence_bits 10 +#define GEN4_URB_FENCE_VSFence_bits 10 + +static inline uint32_t ATTRIBUTE_PURE +URB_FENCE_VSFence_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 10; + case 4: + if (devinfo->is_g4x) { + return 10; + } else { + return 10; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_URB_FENCE_VSFence_start 32 +#define GEN45_URB_FENCE_VSFence_start 32 +#define GEN4_URB_FENCE_VSFence_start 32 + +static inline uint32_t ATTRIBUTE_PURE +URB_FENCE_VSFence_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* URB_FENCE::VS Unit URB Reallocation Request */ + + +#define GEN5_URB_FENCE_VSUnitURBReallocationRequest_bits 1 +#define GEN45_URB_FENCE_VSUnitURBReallocationRequest_bits 1 +#define GEN4_URB_FENCE_VSUnitURBReallocationRequest_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +URB_FENCE_VSUnitURBReallocationRequest_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_URB_FENCE_VSUnitURBReallocationRequest_start 8 +#define GEN45_URB_FENCE_VSUnitURBReallocationRequest_start 8 +#define GEN4_URB_FENCE_VSUnitURBReallocationRequest_start 8 + +static inline uint32_t ATTRIBUTE_PURE +URB_FENCE_VSUnitURBReallocationRequest_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS2_RING_BUFFER_CTL */ + + +#define GEN9_VCS2_RING_BUFFER_CTL_length 1 +#define GEN8_VCS2_RING_BUFFER_CTL_length 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS2_RING_BUFFER_CTL_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS2_RING_BUFFER_CTL::Automatic Report Head Pointer */ + + +#define GEN9_VCS2_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 +#define GEN8_VCS2_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +VCS2_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_VCS2_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 +#define GEN8_VCS2_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS2_RING_BUFFER_CTL_AutomaticReportHeadPointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS2_RING_BUFFER_CTL::Buffer Length (in pages - 1) */ + + +#define GEN9_VCS2_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 +#define GEN8_VCS2_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +VCS2_RING_BUFFER_CTL_BufferLengthinpages1_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_VCS2_RING_BUFFER_CTL_BufferLengthinpages1_start 12 +#define GEN8_VCS2_RING_BUFFER_CTL_BufferLengthinpages1_start 12 + +static inline uint32_t ATTRIBUTE_PURE +VCS2_RING_BUFFER_CTL_BufferLengthinpages1_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 12; + case 8: return 12; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS2_RING_BUFFER_CTL::Disable Register Accesses */ + + +#define GEN9_VCS2_RING_BUFFER_CTL_DisableRegisterAccesses_bits 1 +#define GEN8_VCS2_RING_BUFFER_CTL_DisableRegisterAccesses_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS2_RING_BUFFER_CTL_DisableRegisterAccesses_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_VCS2_RING_BUFFER_CTL_DisableRegisterAccesses_start 8 +#define GEN8_VCS2_RING_BUFFER_CTL_DisableRegisterAccesses_start 8 + +static inline uint32_t ATTRIBUTE_PURE +VCS2_RING_BUFFER_CTL_DisableRegisterAccesses_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS2_RING_BUFFER_CTL::RBWait */ + + +#define GEN9_VCS2_RING_BUFFER_CTL_RBWait_bits 1 +#define GEN8_VCS2_RING_BUFFER_CTL_RBWait_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS2_RING_BUFFER_CTL_RBWait_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_VCS2_RING_BUFFER_CTL_RBWait_start 11 +#define GEN8_VCS2_RING_BUFFER_CTL_RBWait_start 11 + +static inline uint32_t ATTRIBUTE_PURE +VCS2_RING_BUFFER_CTL_RBWait_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 11; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS2_RING_BUFFER_CTL::Ring Buffer Enable */ + + +#define GEN9_VCS2_RING_BUFFER_CTL_RingBufferEnable_bits 1 +#define GEN8_VCS2_RING_BUFFER_CTL_RingBufferEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS2_RING_BUFFER_CTL_RingBufferEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_VCS2_RING_BUFFER_CTL_RingBufferEnable_start 0 +#define GEN8_VCS2_RING_BUFFER_CTL_RingBufferEnable_start 0 + +static inline uint32_t ATTRIBUTE_PURE +VCS2_RING_BUFFER_CTL_RingBufferEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS2_RING_BUFFER_CTL::Semaphore Wait */ + + +#define GEN9_VCS2_RING_BUFFER_CTL_SemaphoreWait_bits 1 +#define GEN8_VCS2_RING_BUFFER_CTL_SemaphoreWait_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS2_RING_BUFFER_CTL_SemaphoreWait_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_VCS2_RING_BUFFER_CTL_SemaphoreWait_start 10 +#define GEN8_VCS2_RING_BUFFER_CTL_SemaphoreWait_start 10 + +static inline uint32_t ATTRIBUTE_PURE +VCS2_RING_BUFFER_CTL_SemaphoreWait_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 10; + case 8: return 10; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_ACTHD_UDW */ + + +#define GEN9_VCS_ACTHD_UDW_length 1 +#define GEN8_VCS_ACTHD_UDW_length 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_ACTHD_UDW_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_ACTHD_UDW::Head Pointer Upper DWORD */ + + +#define GEN9_VCS_ACTHD_UDW_HeadPointerUpperDWORD_bits 16 +#define GEN8_VCS_ACTHD_UDW_HeadPointerUpperDWORD_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +VCS_ACTHD_UDW_HeadPointerUpperDWORD_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_VCS_ACTHD_UDW_HeadPointerUpperDWORD_start 0 +#define GEN8_VCS_ACTHD_UDW_HeadPointerUpperDWORD_start 0 + +static inline uint32_t ATTRIBUTE_PURE +VCS_ACTHD_UDW_HeadPointerUpperDWORD_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_FAULT_REG */ + + +#define GEN75_VCS_FAULT_REG_length 1 +#define GEN7_VCS_FAULT_REG_length 1 +#define GEN6_VCS_FAULT_REG_length 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_FAULT_REG_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_FAULT_REG::Fault Type */ + + +#define GEN75_VCS_FAULT_REG_FaultType_bits 2 +#define GEN7_VCS_FAULT_REG_FaultType_bits 2 +#define GEN6_VCS_FAULT_REG_FaultType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +VCS_FAULT_REG_FaultType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_VCS_FAULT_REG_FaultType_start 1 +#define GEN7_VCS_FAULT_REG_FaultType_start 1 +#define GEN6_VCS_FAULT_REG_FaultType_start 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_FAULT_REG_FaultType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_FAULT_REG::GTTSEL */ + + +#define GEN75_VCS_FAULT_REG_GTTSEL_bits 1 +#define GEN7_VCS_FAULT_REG_GTTSEL_bits 1 +#define GEN6_VCS_FAULT_REG_GTTSEL_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_FAULT_REG_GTTSEL_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_VCS_FAULT_REG_GTTSEL_start 11 +#define GEN7_VCS_FAULT_REG_GTTSEL_start 11 +#define GEN6_VCS_FAULT_REG_GTTSEL_start 11 + +static inline uint32_t ATTRIBUTE_PURE +VCS_FAULT_REG_GTTSEL_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 11; + } else { + return 11; + } + case 6: return 11; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_FAULT_REG::SRCID of Fault */ + + +#define GEN75_VCS_FAULT_REG_SRCIDofFault_bits 8 +#define GEN7_VCS_FAULT_REG_SRCIDofFault_bits 8 +#define GEN6_VCS_FAULT_REG_SRCIDofFault_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +VCS_FAULT_REG_SRCIDofFault_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_VCS_FAULT_REG_SRCIDofFault_start 3 +#define GEN7_VCS_FAULT_REG_SRCIDofFault_start 3 +#define GEN6_VCS_FAULT_REG_SRCIDofFault_start 3 + +static inline uint32_t ATTRIBUTE_PURE +VCS_FAULT_REG_SRCIDofFault_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_FAULT_REG::Valid Bit */ + + +#define GEN75_VCS_FAULT_REG_ValidBit_bits 1 +#define GEN7_VCS_FAULT_REG_ValidBit_bits 1 +#define GEN6_VCS_FAULT_REG_ValidBit_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_FAULT_REG_ValidBit_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_VCS_FAULT_REG_ValidBit_start 0 +#define GEN7_VCS_FAULT_REG_ValidBit_start 0 +#define GEN6_VCS_FAULT_REG_ValidBit_start 0 + +static inline uint32_t ATTRIBUTE_PURE +VCS_FAULT_REG_ValidBit_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_FAULT_REG::Virtual Address of Fault */ + + +#define GEN75_VCS_FAULT_REG_VirtualAddressofFault_bits 20 +#define GEN7_VCS_FAULT_REG_VirtualAddressofFault_bits 20 +#define GEN6_VCS_FAULT_REG_VirtualAddressofFault_bits 20 + +static inline uint32_t ATTRIBUTE_PURE +VCS_FAULT_REG_VirtualAddressofFault_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 20; + } else { + return 20; + } + case 6: return 20; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_VCS_FAULT_REG_VirtualAddressofFault_start 12 +#define GEN7_VCS_FAULT_REG_VirtualAddressofFault_start 12 +#define GEN6_VCS_FAULT_REG_VirtualAddressofFault_start 12 + +static inline uint32_t ATTRIBUTE_PURE +VCS_FAULT_REG_VirtualAddressofFault_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 12; + } else { + return 12; + } + case 6: return 12; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_INSTDONE */ + + +#define GEN11_VCS_INSTDONE_length 1 +#define GEN10_VCS_INSTDONE_length 1 +#define GEN9_VCS_INSTDONE_length 1 +#define GEN8_VCS_INSTDONE_length 1 +#define GEN75_VCS_INSTDONE_length 1 +#define GEN7_VCS_INSTDONE_length 1 +#define GEN6_VCS_INSTDONE_length 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_INSTDONE::BSP Done */ + + +#define GEN11_VCS_INSTDONE_BSPDone_bits 1 +#define GEN10_VCS_INSTDONE_BSPDone_bits 1 +#define GEN9_VCS_INSTDONE_BSPDone_bits 1 +#define GEN8_VCS_INSTDONE_BSPDone_bits 1 +#define GEN75_VCS_INSTDONE_BSPDone_bits 1 +#define GEN7_VCS_INSTDONE_BSPDone_bits 1 +#define GEN6_VCS_INSTDONE_BSPDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_BSPDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VCS_INSTDONE_BSPDone_start 6 +#define GEN10_VCS_INSTDONE_BSPDone_start 6 +#define GEN9_VCS_INSTDONE_BSPDone_start 6 +#define GEN8_VCS_INSTDONE_BSPDone_start 6 +#define GEN75_VCS_INSTDONE_BSPDone_start 6 +#define GEN7_VCS_INSTDONE_BSPDone_start 6 +#define GEN6_VCS_INSTDONE_BSPDone_start 6 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_BSPDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 6; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_INSTDONE::GAC Done */ + + +#define GEN11_VCS_INSTDONE_GACDone_bits 1 +#define GEN10_VCS_INSTDONE_GACDone_bits 1 +#define GEN9_VCS_INSTDONE_GACDone_bits 1 +#define GEN8_VCS_INSTDONE_GACDone_bits 1 +#define GEN75_VCS_INSTDONE_GACDone_bits 1 +#define GEN7_VCS_INSTDONE_GACDone_bits 1 +#define GEN6_VCS_INSTDONE_GACDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_GACDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VCS_INSTDONE_GACDone_start 31 +#define GEN10_VCS_INSTDONE_GACDone_start 31 +#define GEN9_VCS_INSTDONE_GACDone_start 31 +#define GEN8_VCS_INSTDONE_GACDone_start 31 +#define GEN75_VCS_INSTDONE_GACDone_start 31 +#define GEN7_VCS_INSTDONE_GACDone_start 31 +#define GEN6_VCS_INSTDONE_GACDone_start 31 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_GACDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 31; + case 10: return 31; + case 9: return 31; + case 8: return 31; + case 7: + if (devinfo->is_haswell) { + return 31; + } else { + return 31; + } + case 6: return 31; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_INSTDONE::JPG Done */ + + +#define GEN11_VCS_INSTDONE_JPGDone_bits 1 +#define GEN10_VCS_INSTDONE_JPGDone_bits 1 +#define GEN9_VCS_INSTDONE_JPGDone_bits 1 +#define GEN8_VCS_INSTDONE_JPGDone_bits 1 +#define GEN75_VCS_INSTDONE_JPGDone_bits 1 +#define GEN7_VCS_INSTDONE_JPGDone_bits 1 +#define GEN6_VCS_INSTDONE_JPGDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_JPGDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VCS_INSTDONE_JPGDone_start 21 +#define GEN10_VCS_INSTDONE_JPGDone_start 21 +#define GEN9_VCS_INSTDONE_JPGDone_start 21 +#define GEN8_VCS_INSTDONE_JPGDone_start 21 +#define GEN75_VCS_INSTDONE_JPGDone_start 21 +#define GEN7_VCS_INSTDONE_JPGDone_start 21 +#define GEN6_VCS_INSTDONE_JPGDone_start 21 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_JPGDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 21; + case 10: return 21; + case 9: return 21; + case 8: return 21; + case 7: + if (devinfo->is_haswell) { + return 21; + } else { + return 21; + } + case 6: return 21; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_INSTDONE::MPC Done */ + + +#define GEN11_VCS_INSTDONE_MPCDone_bits 1 +#define GEN10_VCS_INSTDONE_MPCDone_bits 1 +#define GEN9_VCS_INSTDONE_MPCDone_bits 1 +#define GEN8_VCS_INSTDONE_MPCDone_bits 1 +#define GEN75_VCS_INSTDONE_MPCDone_bits 1 +#define GEN7_VCS_INSTDONE_MPCDone_bits 1 +#define GEN6_VCS_INSTDONE_MPCDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_MPCDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VCS_INSTDONE_MPCDone_start 4 +#define GEN10_VCS_INSTDONE_MPCDone_start 4 +#define GEN9_VCS_INSTDONE_MPCDone_start 4 +#define GEN8_VCS_INSTDONE_MPCDone_start 4 +#define GEN75_VCS_INSTDONE_MPCDone_start 4 +#define GEN7_VCS_INSTDONE_MPCDone_start 4 +#define GEN6_VCS_INSTDONE_MPCDone_start 4 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_MPCDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_INSTDONE::QRC Done */ + + +#define GEN11_VCS_INSTDONE_QRCDone_bits 1 +#define GEN10_VCS_INSTDONE_QRCDone_bits 1 +#define GEN9_VCS_INSTDONE_QRCDone_bits 1 +#define GEN8_VCS_INSTDONE_QRCDone_bits 1 +#define GEN75_VCS_INSTDONE_QRCDone_bits 1 +#define GEN7_VCS_INSTDONE_QRCDone_bits 1 +#define GEN6_VCS_INSTDONE_QRCDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_QRCDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VCS_INSTDONE_QRCDone_start 2 +#define GEN10_VCS_INSTDONE_QRCDone_start 2 +#define GEN9_VCS_INSTDONE_QRCDone_start 2 +#define GEN8_VCS_INSTDONE_QRCDone_start 2 +#define GEN75_VCS_INSTDONE_QRCDone_start 2 +#define GEN7_VCS_INSTDONE_QRCDone_start 2 +#define GEN6_VCS_INSTDONE_QRCDone_start 2 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_QRCDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_INSTDONE::Reserved */ + + +#define GEN11_VCS_INSTDONE_Reserved_bits 1 +#define GEN10_VCS_INSTDONE_Reserved_bits 1 +#define GEN9_VCS_INSTDONE_Reserved_bits 1 +#define GEN8_VCS_INSTDONE_Reserved_bits 1 +#define GEN75_VCS_INSTDONE_Reserved_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_Reserved_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VCS_INSTDONE_Reserved_start 29 +#define GEN10_VCS_INSTDONE_Reserved_start 29 +#define GEN9_VCS_INSTDONE_Reserved_start 29 +#define GEN8_VCS_INSTDONE_Reserved_start 29 +#define GEN75_VCS_INSTDONE_Reserved_start 29 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_Reserved_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 29; + case 10: return 29; + case 9: return 29; + case 8: return 29; + case 7: + if (devinfo->is_haswell) { + return 29; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_INSTDONE::Ring Enable */ + + +#define GEN11_VCS_INSTDONE_RingEnable_bits 1 +#define GEN10_VCS_INSTDONE_RingEnable_bits 1 +#define GEN9_VCS_INSTDONE_RingEnable_bits 1 +#define GEN8_VCS_INSTDONE_RingEnable_bits 1 +#define GEN75_VCS_INSTDONE_RingEnable_bits 1 +#define GEN7_VCS_INSTDONE_RingEnable_bits 1 +#define GEN6_VCS_INSTDONE_RingEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_RingEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VCS_INSTDONE_RingEnable_start 0 +#define GEN10_VCS_INSTDONE_RingEnable_start 0 +#define GEN9_VCS_INSTDONE_RingEnable_start 0 +#define GEN8_VCS_INSTDONE_RingEnable_start 0 +#define GEN75_VCS_INSTDONE_RingEnable_start 0 +#define GEN7_VCS_INSTDONE_RingEnable_start 0 +#define GEN6_VCS_INSTDONE_RingEnable_start 0 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_RingEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_INSTDONE::SEC Done */ + + +#define GEN11_VCS_INSTDONE_SECDone_bits 1 +#define GEN10_VCS_INSTDONE_SECDone_bits 1 +#define GEN9_VCS_INSTDONE_SECDone_bits 1 +#define GEN8_VCS_INSTDONE_SECDone_bits 1 +#define GEN75_VCS_INSTDONE_SECDone_bits 1 +#define GEN7_VCS_INSTDONE_SECDone_bits 1 +#define GEN6_VCS_INSTDONE_SECDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_SECDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VCS_INSTDONE_SECDone_start 3 +#define GEN10_VCS_INSTDONE_SECDone_start 3 +#define GEN9_VCS_INSTDONE_SECDone_start 3 +#define GEN8_VCS_INSTDONE_SECDone_start 3 +#define GEN75_VCS_INSTDONE_SECDone_start 3 +#define GEN7_VCS_INSTDONE_SECDone_start 3 +#define GEN6_VCS_INSTDONE_SECDone_start 3 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_SECDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_INSTDONE::USB Done */ + + +#define GEN11_VCS_INSTDONE_USBDone_bits 1 +#define GEN10_VCS_INSTDONE_USBDone_bits 1 +#define GEN9_VCS_INSTDONE_USBDone_bits 1 +#define GEN8_VCS_INSTDONE_USBDone_bits 1 +#define GEN75_VCS_INSTDONE_USBDone_bits 1 +#define GEN7_VCS_INSTDONE_USBDone_bits 1 +#define GEN6_VCS_INSTDONE_USBDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_USBDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VCS_INSTDONE_USBDone_start 1 +#define GEN10_VCS_INSTDONE_USBDone_start 1 +#define GEN9_VCS_INSTDONE_USBDone_start 1 +#define GEN8_VCS_INSTDONE_USBDone_start 1 +#define GEN75_VCS_INSTDONE_USBDone_start 1 +#define GEN7_VCS_INSTDONE_USBDone_start 1 +#define GEN6_VCS_INSTDONE_USBDone_start 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_USBDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_INSTDONE::VAC Done */ + + +#define GEN11_VCS_INSTDONE_VACDone_bits 1 +#define GEN10_VCS_INSTDONE_VACDone_bits 1 +#define GEN9_VCS_INSTDONE_VACDone_bits 1 +#define GEN8_VCS_INSTDONE_VACDone_bits 1 +#define GEN75_VCS_INSTDONE_VACDone_bits 1 +#define GEN7_VCS_INSTDONE_VACDone_bits 1 +#define GEN6_VCS_INSTDONE_VACDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VACDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VCS_INSTDONE_VACDone_start 19 +#define GEN10_VCS_INSTDONE_VACDone_start 19 +#define GEN9_VCS_INSTDONE_VACDone_start 19 +#define GEN8_VCS_INSTDONE_VACDone_start 19 +#define GEN75_VCS_INSTDONE_VACDone_start 19 +#define GEN7_VCS_INSTDONE_VACDone_start 19 +#define GEN6_VCS_INSTDONE_VACDone_start 19 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VACDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 19; + case 10: return 19; + case 9: return 19; + case 8: return 19; + case 7: + if (devinfo->is_haswell) { + return 19; + } else { + return 19; + } + case 6: return 19; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_INSTDONE::VAD Done */ + + +#define GEN11_VCS_INSTDONE_VADDone_bits 1 +#define GEN10_VCS_INSTDONE_VADDone_bits 1 +#define GEN9_VCS_INSTDONE_VADDone_bits 1 +#define GEN8_VCS_INSTDONE_VADDone_bits 1 +#define GEN75_VCS_INSTDONE_VADDone_bits 1 +#define GEN7_VCS_INSTDONE_VADDone_bits 1 +#define GEN6_VCS_INSTDONE_VADDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VADDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VCS_INSTDONE_VADDone_start 16 +#define GEN10_VCS_INSTDONE_VADDone_start 16 +#define GEN9_VCS_INSTDONE_VADDone_start 16 +#define GEN8_VCS_INSTDONE_VADDone_start 16 +#define GEN75_VCS_INSTDONE_VADDone_start 16 +#define GEN7_VCS_INSTDONE_VADDone_start 16 +#define GEN6_VCS_INSTDONE_VADDone_start 16 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VADDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_INSTDONE::VAM Done */ + + +#define GEN11_VCS_INSTDONE_VAMDone_bits 1 +#define GEN10_VCS_INSTDONE_VAMDone_bits 1 +#define GEN9_VCS_INSTDONE_VAMDone_bits 1 +#define GEN8_VCS_INSTDONE_VAMDone_bits 1 +#define GEN75_VCS_INSTDONE_VAMDone_bits 1 +#define GEN7_VCS_INSTDONE_VAMDone_bits 1 +#define GEN6_VCS_INSTDONE_VAMDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VAMDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VCS_INSTDONE_VAMDone_start 20 +#define GEN10_VCS_INSTDONE_VAMDone_start 20 +#define GEN9_VCS_INSTDONE_VAMDone_start 20 +#define GEN8_VCS_INSTDONE_VAMDone_start 20 +#define GEN75_VCS_INSTDONE_VAMDone_start 20 +#define GEN7_VCS_INSTDONE_VAMDone_start 20 +#define GEN6_VCS_INSTDONE_VAMDone_start 20 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VAMDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 20; + case 10: return 20; + case 9: return 20; + case 8: return 20; + case 7: + if (devinfo->is_haswell) { + return 20; + } else { + return 20; + } + case 6: return 20; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_INSTDONE::VBP Done */ + + +#define GEN11_VCS_INSTDONE_VBPDone_bits 1 +#define GEN10_VCS_INSTDONE_VBPDone_bits 1 +#define GEN9_VCS_INSTDONE_VBPDone_bits 1 +#define GEN8_VCS_INSTDONE_VBPDone_bits 1 +#define GEN75_VCS_INSTDONE_VBPDone_bits 1 +#define GEN7_VCS_INSTDONE_VBPDone_bits 1 +#define GEN6_VCS_INSTDONE_VBPDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VBPDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VCS_INSTDONE_VBPDone_start 22 +#define GEN10_VCS_INSTDONE_VBPDone_start 22 +#define GEN9_VCS_INSTDONE_VBPDone_start 22 +#define GEN8_VCS_INSTDONE_VBPDone_start 22 +#define GEN75_VCS_INSTDONE_VBPDone_start 22 +#define GEN7_VCS_INSTDONE_VBPDone_start 22 +#define GEN6_VCS_INSTDONE_VBPDone_start 22 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VBPDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 22; + case 10: return 22; + case 9: return 22; + case 8: return 22; + case 7: + if (devinfo->is_haswell) { + return 22; + } else { + return 22; + } + case 6: return 22; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_INSTDONE::VCD Done */ + + +#define GEN11_VCS_INSTDONE_VCDDone_bits 1 +#define GEN10_VCS_INSTDONE_VCDDone_bits 1 +#define GEN9_VCS_INSTDONE_VCDDone_bits 1 +#define GEN8_VCS_INSTDONE_VCDDone_bits 1 +#define GEN75_VCS_INSTDONE_VCDDone_bits 1 +#define GEN7_VCS_INSTDONE_VCDDone_bits 1 +#define GEN6_VCS_INSTDONE_VCDDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VCDDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VCS_INSTDONE_VCDDone_start 15 +#define GEN10_VCS_INSTDONE_VCDDone_start 15 +#define GEN9_VCS_INSTDONE_VCDDone_start 15 +#define GEN8_VCS_INSTDONE_VCDDone_start 15 +#define GEN75_VCS_INSTDONE_VCDDone_start 15 +#define GEN7_VCS_INSTDONE_VCDDone_start 15 +#define GEN6_VCS_INSTDONE_VCDDone_start 15 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VCDDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 15; + case 10: return 15; + case 9: return 15; + case 8: return 15; + case 7: + if (devinfo->is_haswell) { + return 15; + } else { + return 15; + } + case 6: return 15; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_INSTDONE::VCI Done */ + + +#define GEN11_VCS_INSTDONE_VCIDone_bits 1 +#define GEN10_VCS_INSTDONE_VCIDone_bits 1 +#define GEN9_VCS_INSTDONE_VCIDone_bits 1 +#define GEN8_VCS_INSTDONE_VCIDone_bits 1 +#define GEN75_VCS_INSTDONE_VCIDone_bits 1 +#define GEN7_VCS_INSTDONE_VCIDone_bits 1 +#define GEN6_VCS_INSTDONE_VCIDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VCIDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VCS_INSTDONE_VCIDone_start 24 +#define GEN10_VCS_INSTDONE_VCIDone_start 24 +#define GEN9_VCS_INSTDONE_VCIDone_start 24 +#define GEN8_VCS_INSTDONE_VCIDone_start 24 +#define GEN75_VCS_INSTDONE_VCIDone_start 24 +#define GEN7_VCS_INSTDONE_VCIDone_start 24 +#define GEN6_VCS_INSTDONE_VCIDone_start 24 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VCIDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 24; + case 10: return 24; + case 9: return 24; + case 8: return 24; + case 7: + if (devinfo->is_haswell) { + return 24; + } else { + return 24; + } + case 6: return 24; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_INSTDONE::VCP Done */ + + +#define GEN11_VCS_INSTDONE_VCPDone_bits 1 +#define GEN10_VCS_INSTDONE_VCPDone_bits 1 +#define GEN9_VCS_INSTDONE_VCPDone_bits 1 +#define GEN8_VCS_INSTDONE_VCPDone_bits 1 +#define GEN75_VCS_INSTDONE_VCPDone_bits 1 +#define GEN7_VCS_INSTDONE_VCPDone_bits 1 +#define GEN6_VCS_INSTDONE_VCPDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VCPDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VCS_INSTDONE_VCPDone_start 14 +#define GEN10_VCS_INSTDONE_VCPDone_start 14 +#define GEN9_VCS_INSTDONE_VCPDone_start 14 +#define GEN8_VCS_INSTDONE_VCPDone_start 14 +#define GEN75_VCS_INSTDONE_VCPDone_start 14 +#define GEN7_VCS_INSTDONE_VCPDone_start 14 +#define GEN6_VCS_INSTDONE_VCPDone_start 14 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VCPDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 14; + case 10: return 14; + case 9: return 14; + case 8: return 14; + case 7: + if (devinfo->is_haswell) { + return 14; + } else { + return 14; + } + case 6: return 14; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_INSTDONE::VCR Done */ + + +#define GEN10_VCS_INSTDONE_VCRDone_bits 1 +#define GEN9_VCS_INSTDONE_VCRDone_bits 1 +#define GEN8_VCS_INSTDONE_VCRDone_bits 1 +#define GEN75_VCS_INSTDONE_VCRDone_bits 1 +#define GEN7_VCS_INSTDONE_VCRDone_bits 1 +#define GEN6_VCS_INSTDONE_VCRDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VCRDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_VCS_INSTDONE_VCRDone_start 25 +#define GEN9_VCS_INSTDONE_VCRDone_start 25 +#define GEN8_VCS_INSTDONE_VCRDone_start 25 +#define GEN75_VCS_INSTDONE_VCRDone_start 25 +#define GEN7_VCS_INSTDONE_VCRDone_start 25 +#define GEN6_VCS_INSTDONE_VCRDone_start 25 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VCRDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 25; + case 9: return 25; + case 8: return 25; + case 7: + if (devinfo->is_haswell) { + return 25; + } else { + return 25; + } + case 6: return 25; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_INSTDONE::VCS Done */ + + +#define GEN11_VCS_INSTDONE_VCSDone_bits 1 +#define GEN10_VCS_INSTDONE_VCSDone_bits 1 +#define GEN9_VCS_INSTDONE_VCSDone_bits 1 +#define GEN8_VCS_INSTDONE_VCSDone_bits 1 +#define GEN75_VCS_INSTDONE_VCSDone_bits 1 +#define GEN7_VCS_INSTDONE_VCSDone_bits 1 +#define GEN6_VCS_INSTDONE_VCSDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VCSDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VCS_INSTDONE_VCSDone_start 30 +#define GEN10_VCS_INSTDONE_VCSDone_start 30 +#define GEN9_VCS_INSTDONE_VCSDone_start 30 +#define GEN8_VCS_INSTDONE_VCSDone_start 30 +#define GEN75_VCS_INSTDONE_VCSDone_start 30 +#define GEN7_VCS_INSTDONE_VCSDone_start 30 +#define GEN6_VCS_INSTDONE_VCSDone_start 30 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VCSDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 30; + case 10: return 30; + case 9: return 30; + case 8: return 30; + case 7: + if (devinfo->is_haswell) { + return 30; + } else { + return 30; + } + case 6: return 30; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_INSTDONE::VDS Done */ + + +#define GEN11_VCS_INSTDONE_VDSDone_bits 1 +#define GEN10_VCS_INSTDONE_VDSDone_bits 1 +#define GEN9_VCS_INSTDONE_VDSDone_bits 1 +#define GEN8_VCS_INSTDONE_VDSDone_bits 1 +#define GEN75_VCS_INSTDONE_VDSDone_bits 1 +#define GEN7_VCS_INSTDONE_VDSDone_bits 1 +#define GEN6_VCS_INSTDONE_VDSDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VDSDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VCS_INSTDONE_VDSDone_start 12 +#define GEN10_VCS_INSTDONE_VDSDone_start 12 +#define GEN9_VCS_INSTDONE_VDSDone_start 12 +#define GEN8_VCS_INSTDONE_VDSDone_start 12 +#define GEN75_VCS_INSTDONE_VDSDone_start 12 +#define GEN7_VCS_INSTDONE_VDSDone_start 12 +#define GEN6_VCS_INSTDONE_VDSDone_start 12 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VDSDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 12; + case 10: return 12; + case 9: return 12; + case 8: return 12; + case 7: + if (devinfo->is_haswell) { + return 12; + } else { + return 12; + } + case 6: return 12; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_INSTDONE::VFT Done */ + + +#define GEN11_VCS_INSTDONE_VFTDone_bits 1 +#define GEN10_VCS_INSTDONE_VFTDone_bits 1 +#define GEN9_VCS_INSTDONE_VFTDone_bits 1 +#define GEN8_VCS_INSTDONE_VFTDone_bits 1 +#define GEN75_VCS_INSTDONE_VFTDone_bits 1 +#define GEN7_VCS_INSTDONE_VFTDone_bits 1 +#define GEN6_VCS_INSTDONE_VFTDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VFTDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VCS_INSTDONE_VFTDone_start 5 +#define GEN10_VCS_INSTDONE_VFTDone_start 5 +#define GEN9_VCS_INSTDONE_VFTDone_start 5 +#define GEN8_VCS_INSTDONE_VFTDone_start 5 +#define GEN75_VCS_INSTDONE_VFTDone_start 5 +#define GEN7_VCS_INSTDONE_VFTDone_start 5 +#define GEN6_VCS_INSTDONE_VFTDone_start 5 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VFTDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 5; + case 10: return 5; + case 9: return 5; + case 8: return 5; + case 7: + if (devinfo->is_haswell) { + return 5; + } else { + return 5; + } + case 6: return 5; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_INSTDONE::VHR Done */ + + +#define GEN11_VCS_INSTDONE_VHRDone_bits 1 +#define GEN10_VCS_INSTDONE_VHRDone_bits 1 +#define GEN9_VCS_INSTDONE_VHRDone_bits 1 +#define GEN8_VCS_INSTDONE_VHRDone_bits 1 +#define GEN75_VCS_INSTDONE_VHRDone_bits 1 +#define GEN7_VCS_INSTDONE_VHRDone_bits 1 +#define GEN6_VCS_INSTDONE_VHRDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VHRDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VCS_INSTDONE_VHRDone_start 23 +#define GEN10_VCS_INSTDONE_VHRDone_start 23 +#define GEN9_VCS_INSTDONE_VHRDone_start 23 +#define GEN8_VCS_INSTDONE_VHRDone_start 23 +#define GEN75_VCS_INSTDONE_VHRDone_start 23 +#define GEN7_VCS_INSTDONE_VHRDone_start 23 +#define GEN6_VCS_INSTDONE_VHRDone_start 23 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VHRDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 23; + case 10: return 23; + case 9: return 23; + case 8: return 23; + case 7: + if (devinfo->is_haswell) { + return 23; + } else { + return 23; + } + case 6: return 23; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_INSTDONE::VIN Done */ + + +#define GEN11_VCS_INSTDONE_VINDone_bits 1 +#define GEN10_VCS_INSTDONE_VINDone_bits 1 +#define GEN9_VCS_INSTDONE_VINDone_bits 1 +#define GEN8_VCS_INSTDONE_VINDone_bits 1 +#define GEN75_VCS_INSTDONE_VINDone_bits 1 +#define GEN7_VCS_INSTDONE_VINDone_bits 1 +#define GEN6_VCS_INSTDONE_VINDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VINDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VCS_INSTDONE_VINDone_start 26 +#define GEN10_VCS_INSTDONE_VINDone_start 26 +#define GEN9_VCS_INSTDONE_VINDone_start 26 +#define GEN8_VCS_INSTDONE_VINDone_start 26 +#define GEN75_VCS_INSTDONE_VINDone_start 26 +#define GEN7_VCS_INSTDONE_VINDone_start 26 +#define GEN6_VCS_INSTDONE_VINDone_start 26 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VINDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 26; + case 10: return 26; + case 9: return 26; + case 8: return 26; + case 7: + if (devinfo->is_haswell) { + return 26; + } else { + return 26; + } + case 6: return 26; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_INSTDONE::VIP Done */ + + +#define GEN11_VCS_INSTDONE_VIPDone_bits 1 +#define GEN10_VCS_INSTDONE_VIPDone_bits 1 +#define GEN9_VCS_INSTDONE_VIPDone_bits 1 +#define GEN8_VCS_INSTDONE_VIPDone_bits 1 +#define GEN75_VCS_INSTDONE_VIPDone_bits 1 +#define GEN7_VCS_INSTDONE_VIPDone_bits 1 +#define GEN6_VCS_INSTDONE_VIPDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VIPDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VCS_INSTDONE_VIPDone_start 10 +#define GEN10_VCS_INSTDONE_VIPDone_start 10 +#define GEN9_VCS_INSTDONE_VIPDone_start 10 +#define GEN8_VCS_INSTDONE_VIPDone_start 10 +#define GEN75_VCS_INSTDONE_VIPDone_start 10 +#define GEN7_VCS_INSTDONE_VIPDone_start 10 +#define GEN6_VCS_INSTDONE_VIPDone_start 10 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VIPDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 10; + case 10: return 10; + case 9: return 10; + case 8: return 10; + case 7: + if (devinfo->is_haswell) { + return 10; + } else { + return 10; + } + case 6: return 10; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_INSTDONE::VIS Done */ + + +#define GEN11_VCS_INSTDONE_VISDone_bits 1 +#define GEN10_VCS_INSTDONE_VISDone_bits 1 +#define GEN9_VCS_INSTDONE_VISDone_bits 1 +#define GEN8_VCS_INSTDONE_VISDone_bits 1 +#define GEN75_VCS_INSTDONE_VISDone_bits 1 +#define GEN7_VCS_INSTDONE_VISDone_bits 1 +#define GEN6_VCS_INSTDONE_VISDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VISDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VCS_INSTDONE_VISDone_start 18 +#define GEN10_VCS_INSTDONE_VISDone_start 18 +#define GEN9_VCS_INSTDONE_VISDone_start 18 +#define GEN8_VCS_INSTDONE_VISDone_start 18 +#define GEN75_VCS_INSTDONE_VISDone_start 18 +#define GEN7_VCS_INSTDONE_VISDone_start 18 +#define GEN6_VCS_INSTDONE_VISDone_start 18 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VISDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 18; + case 10: return 18; + case 9: return 18; + case 8: return 18; + case 7: + if (devinfo->is_haswell) { + return 18; + } else { + return 18; + } + case 6: return 18; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_INSTDONE::VIT Done */ + + +#define GEN11_VCS_INSTDONE_VITDone_bits 1 +#define GEN10_VCS_INSTDONE_VITDone_bits 1 +#define GEN9_VCS_INSTDONE_VITDone_bits 1 +#define GEN8_VCS_INSTDONE_VITDone_bits 1 +#define GEN75_VCS_INSTDONE_VITDone_bits 1 +#define GEN7_VCS_INSTDONE_VITDone_bits 1 +#define GEN6_VCS_INSTDONE_VITDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VITDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VCS_INSTDONE_VITDone_start 11 +#define GEN10_VCS_INSTDONE_VITDone_start 11 +#define GEN9_VCS_INSTDONE_VITDone_start 11 +#define GEN8_VCS_INSTDONE_VITDone_start 11 +#define GEN75_VCS_INSTDONE_VITDone_start 11 +#define GEN7_VCS_INSTDONE_VITDone_start 11 +#define GEN6_VCS_INSTDONE_VITDone_start 11 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VITDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 11; + case 10: return 11; + case 9: return 11; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 11; + } else { + return 11; + } + case 6: return 11; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_INSTDONE::VLF Done */ + + +#define GEN11_VCS_INSTDONE_VLFDone_bits 1 +#define GEN10_VCS_INSTDONE_VLFDone_bits 1 +#define GEN9_VCS_INSTDONE_VLFDone_bits 1 +#define GEN8_VCS_INSTDONE_VLFDone_bits 1 +#define GEN75_VCS_INSTDONE_VLFDone_bits 1 +#define GEN7_VCS_INSTDONE_VLFDone_bits 1 +#define GEN6_VCS_INSTDONE_VLFDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VLFDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VCS_INSTDONE_VLFDone_start 7 +#define GEN10_VCS_INSTDONE_VLFDone_start 7 +#define GEN9_VCS_INSTDONE_VLFDone_start 7 +#define GEN8_VCS_INSTDONE_VLFDone_start 7 +#define GEN75_VCS_INSTDONE_VLFDone_start 7 +#define GEN7_VCS_INSTDONE_VLFDone_start 7 +#define GEN6_VCS_INSTDONE_VLFDone_start 7 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VLFDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 7; + } else { + return 7; + } + case 6: return 7; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_INSTDONE::VMC Done */ + + +#define GEN11_VCS_INSTDONE_VMCDone_bits 1 +#define GEN10_VCS_INSTDONE_VMCDone_bits 1 +#define GEN9_VCS_INSTDONE_VMCDone_bits 1 +#define GEN8_VCS_INSTDONE_VMCDone_bits 1 +#define GEN75_VCS_INSTDONE_VMCDone_bits 1 +#define GEN7_VCS_INSTDONE_VMCDone_bits 1 +#define GEN6_VCS_INSTDONE_VMCDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VMCDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VCS_INSTDONE_VMCDone_start 9 +#define GEN10_VCS_INSTDONE_VMCDone_start 9 +#define GEN9_VCS_INSTDONE_VMCDone_start 9 +#define GEN8_VCS_INSTDONE_VMCDone_start 9 +#define GEN75_VCS_INSTDONE_VMCDone_start 9 +#define GEN7_VCS_INSTDONE_VMCDone_start 9 +#define GEN6_VCS_INSTDONE_VMCDone_start 9 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VMCDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 9; + case 10: return 9; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 9; + } + case 6: return 9; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_INSTDONE::VMD Done */ + + +#define GEN11_VCS_INSTDONE_VMDDone_bits 1 +#define GEN10_VCS_INSTDONE_VMDDone_bits 1 +#define GEN9_VCS_INSTDONE_VMDDone_bits 1 +#define GEN8_VCS_INSTDONE_VMDDone_bits 1 +#define GEN75_VCS_INSTDONE_VMDDone_bits 1 +#define GEN7_VCS_INSTDONE_VMDDone_bits 1 +#define GEN6_VCS_INSTDONE_VMDDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VMDDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VCS_INSTDONE_VMDDone_start 17 +#define GEN10_VCS_INSTDONE_VMDDone_start 17 +#define GEN9_VCS_INSTDONE_VMDDone_start 17 +#define GEN8_VCS_INSTDONE_VMDDone_start 17 +#define GEN75_VCS_INSTDONE_VMDDone_start 17 +#define GEN7_VCS_INSTDONE_VMDDone_start 17 +#define GEN6_VCS_INSTDONE_VMDDone_start 17 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VMDDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 17; + case 10: return 17; + case 9: return 17; + case 8: return 17; + case 7: + if (devinfo->is_haswell) { + return 17; + } else { + return 17; + } + case 6: return 17; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_INSTDONE::VMX Done */ + + +#define GEN11_VCS_INSTDONE_VMXDone_bits 1 +#define GEN10_VCS_INSTDONE_VMXDone_bits 1 +#define GEN9_VCS_INSTDONE_VMXDone_bits 1 +#define GEN8_VCS_INSTDONE_VMXDone_bits 1 +#define GEN75_VCS_INSTDONE_VMXDone_bits 1 +#define GEN7_VCS_INSTDONE_VMXDone_bits 1 +#define GEN6_VCS_INSTDONE_VMXDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VMXDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VCS_INSTDONE_VMXDone_start 13 +#define GEN10_VCS_INSTDONE_VMXDone_start 13 +#define GEN9_VCS_INSTDONE_VMXDone_start 13 +#define GEN8_VCS_INSTDONE_VMXDone_start 13 +#define GEN75_VCS_INSTDONE_VMXDone_start 13 +#define GEN7_VCS_INSTDONE_VMXDone_start 13 +#define GEN6_VCS_INSTDONE_VMXDone_start 13 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VMXDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 13; + case 10: return 13; + case 9: return 13; + case 8: return 13; + case 7: + if (devinfo->is_haswell) { + return 13; + } else { + return 13; + } + case 6: return 13; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_INSTDONE::VOP Done */ + + +#define GEN11_VCS_INSTDONE_VOPDone_bits 1 +#define GEN10_VCS_INSTDONE_VOPDone_bits 1 +#define GEN9_VCS_INSTDONE_VOPDone_bits 1 +#define GEN8_VCS_INSTDONE_VOPDone_bits 1 +#define GEN75_VCS_INSTDONE_VOPDone_bits 1 +#define GEN7_VCS_INSTDONE_VOPDone_bits 1 +#define GEN6_VCS_INSTDONE_VOPDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VOPDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VCS_INSTDONE_VOPDone_start 8 +#define GEN10_VCS_INSTDONE_VOPDone_start 8 +#define GEN9_VCS_INSTDONE_VOPDone_start 8 +#define GEN8_VCS_INSTDONE_VOPDone_start 8 +#define GEN75_VCS_INSTDONE_VOPDone_start 8 +#define GEN7_VCS_INSTDONE_VOPDone_start 8 +#define GEN6_VCS_INSTDONE_VOPDone_start 8 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VOPDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 8; + case 10: return 8; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_INSTDONE::VPR Done */ + + +#define GEN11_VCS_INSTDONE_VPRDone_bits 1 +#define GEN10_VCS_INSTDONE_VPRDone_bits 1 +#define GEN9_VCS_INSTDONE_VPRDone_bits 1 +#define GEN8_VCS_INSTDONE_VPRDone_bits 1 +#define GEN75_VCS_INSTDONE_VPRDone_bits 1 +#define GEN7_VCS_INSTDONE_VPRDone_bits 1 +#define GEN6_VCS_INSTDONE_VPRDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VPRDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VCS_INSTDONE_VPRDone_start 27 +#define GEN10_VCS_INSTDONE_VPRDone_start 27 +#define GEN9_VCS_INSTDONE_VPRDone_start 27 +#define GEN8_VCS_INSTDONE_VPRDone_start 27 +#define GEN75_VCS_INSTDONE_VPRDone_start 27 +#define GEN7_VCS_INSTDONE_VPRDone_start 27 +#define GEN6_VCS_INSTDONE_VPRDone_start 27 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VPRDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 27; + case 10: return 27; + case 9: return 27; + case 8: return 27; + case 7: + if (devinfo->is_haswell) { + return 27; + } else { + return 27; + } + case 6: return 27; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_INSTDONE::VTQ Done */ + + +#define GEN11_VCS_INSTDONE_VTQDone_bits 1 +#define GEN10_VCS_INSTDONE_VTQDone_bits 1 +#define GEN9_VCS_INSTDONE_VTQDone_bits 1 +#define GEN8_VCS_INSTDONE_VTQDone_bits 1 +#define GEN75_VCS_INSTDONE_VTQDone_bits 1 +#define GEN7_VCS_INSTDONE_VTQDone_bits 1 +#define GEN6_VCS_INSTDONE_VTQDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VTQDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VCS_INSTDONE_VTQDone_start 28 +#define GEN10_VCS_INSTDONE_VTQDone_start 28 +#define GEN9_VCS_INSTDONE_VTQDone_start 28 +#define GEN8_VCS_INSTDONE_VTQDone_start 28 +#define GEN75_VCS_INSTDONE_VTQDone_start 28 +#define GEN7_VCS_INSTDONE_VTQDone_start 28 +#define GEN6_VCS_INSTDONE_VTQDone_start 28 + +static inline uint32_t ATTRIBUTE_PURE +VCS_INSTDONE_VTQDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 28; + case 10: return 28; + case 9: return 28; + case 8: return 28; + case 7: + if (devinfo->is_haswell) { + return 28; + } else { + return 28; + } + case 6: return 28; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_RING_BUFFER_CTL */ + + +#define GEN9_VCS_RING_BUFFER_CTL_length 1 +#define GEN8_VCS_RING_BUFFER_CTL_length 1 +#define GEN75_VCS_RING_BUFFER_CTL_length 1 +#define GEN7_VCS_RING_BUFFER_CTL_length 1 +#define GEN6_VCS_RING_BUFFER_CTL_length 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_RING_BUFFER_CTL_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_RING_BUFFER_CTL::Automatic Report Head Pointer */ + + +#define GEN9_VCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 +#define GEN8_VCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 +#define GEN75_VCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 +#define GEN7_VCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 +#define GEN6_VCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +VCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_VCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 +#define GEN8_VCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 +#define GEN75_VCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 +#define GEN7_VCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 +#define GEN6_VCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_RING_BUFFER_CTL::Buffer Length (in pages - 1) */ + + +#define GEN9_VCS_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 +#define GEN8_VCS_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 +#define GEN75_VCS_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 +#define GEN7_VCS_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 +#define GEN6_VCS_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +VCS_RING_BUFFER_CTL_BufferLengthinpages1_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 9; + } + case 6: return 9; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_VCS_RING_BUFFER_CTL_BufferLengthinpages1_start 12 +#define GEN8_VCS_RING_BUFFER_CTL_BufferLengthinpages1_start 12 +#define GEN75_VCS_RING_BUFFER_CTL_BufferLengthinpages1_start 12 +#define GEN7_VCS_RING_BUFFER_CTL_BufferLengthinpages1_start 12 +#define GEN6_VCS_RING_BUFFER_CTL_BufferLengthinpages1_start 12 + +static inline uint32_t ATTRIBUTE_PURE +VCS_RING_BUFFER_CTL_BufferLengthinpages1_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 12; + case 8: return 12; + case 7: + if (devinfo->is_haswell) { + return 12; + } else { + return 12; + } + case 6: return 12; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_RING_BUFFER_CTL::Disable Register Accesses */ + + +#define GEN9_VCS_RING_BUFFER_CTL_DisableRegisterAccesses_bits 1 +#define GEN8_VCS_RING_BUFFER_CTL_DisableRegisterAccesses_bits 1 +#define GEN75_VCS_RING_BUFFER_CTL_DisableRegisterAccesses_bits 1 +#define GEN7_VCS_RING_BUFFER_CTL_DisableRegisterAccesses_bits 1 +#define GEN6_VCS_RING_BUFFER_CTL_DisableRegisterAccesses_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_RING_BUFFER_CTL_DisableRegisterAccesses_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_VCS_RING_BUFFER_CTL_DisableRegisterAccesses_start 8 +#define GEN8_VCS_RING_BUFFER_CTL_DisableRegisterAccesses_start 8 +#define GEN75_VCS_RING_BUFFER_CTL_DisableRegisterAccesses_start 8 +#define GEN7_VCS_RING_BUFFER_CTL_DisableRegisterAccesses_start 8 +#define GEN6_VCS_RING_BUFFER_CTL_DisableRegisterAccesses_start 8 + +static inline uint32_t ATTRIBUTE_PURE +VCS_RING_BUFFER_CTL_DisableRegisterAccesses_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 8; + } + case 6: return 8; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_RING_BUFFER_CTL::RBWait */ + + +#define GEN9_VCS_RING_BUFFER_CTL_RBWait_bits 1 +#define GEN8_VCS_RING_BUFFER_CTL_RBWait_bits 1 +#define GEN75_VCS_RING_BUFFER_CTL_RBWait_bits 1 +#define GEN7_VCS_RING_BUFFER_CTL_RBWait_bits 1 +#define GEN6_VCS_RING_BUFFER_CTL_RBWait_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_RING_BUFFER_CTL_RBWait_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_VCS_RING_BUFFER_CTL_RBWait_start 11 +#define GEN8_VCS_RING_BUFFER_CTL_RBWait_start 11 +#define GEN75_VCS_RING_BUFFER_CTL_RBWait_start 11 +#define GEN7_VCS_RING_BUFFER_CTL_RBWait_start 11 +#define GEN6_VCS_RING_BUFFER_CTL_RBWait_start 11 + +static inline uint32_t ATTRIBUTE_PURE +VCS_RING_BUFFER_CTL_RBWait_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 11; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 11; + } else { + return 11; + } + case 6: return 11; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_RING_BUFFER_CTL::Ring Buffer Enable */ + + +#define GEN9_VCS_RING_BUFFER_CTL_RingBufferEnable_bits 1 +#define GEN8_VCS_RING_BUFFER_CTL_RingBufferEnable_bits 1 +#define GEN75_VCS_RING_BUFFER_CTL_RingBufferEnable_bits 1 +#define GEN7_VCS_RING_BUFFER_CTL_RingBufferEnable_bits 1 +#define GEN6_VCS_RING_BUFFER_CTL_RingBufferEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_RING_BUFFER_CTL_RingBufferEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_VCS_RING_BUFFER_CTL_RingBufferEnable_start 0 +#define GEN8_VCS_RING_BUFFER_CTL_RingBufferEnable_start 0 +#define GEN75_VCS_RING_BUFFER_CTL_RingBufferEnable_start 0 +#define GEN7_VCS_RING_BUFFER_CTL_RingBufferEnable_start 0 +#define GEN6_VCS_RING_BUFFER_CTL_RingBufferEnable_start 0 + +static inline uint32_t ATTRIBUTE_PURE +VCS_RING_BUFFER_CTL_RingBufferEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VCS_RING_BUFFER_CTL::Semaphore Wait */ + + +#define GEN9_VCS_RING_BUFFER_CTL_SemaphoreWait_bits 1 +#define GEN8_VCS_RING_BUFFER_CTL_SemaphoreWait_bits 1 +#define GEN75_VCS_RING_BUFFER_CTL_SemaphoreWait_bits 1 +#define GEN7_VCS_RING_BUFFER_CTL_SemaphoreWait_bits 1 +#define GEN6_VCS_RING_BUFFER_CTL_SemaphoreWait_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VCS_RING_BUFFER_CTL_SemaphoreWait_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_VCS_RING_BUFFER_CTL_SemaphoreWait_start 10 +#define GEN8_VCS_RING_BUFFER_CTL_SemaphoreWait_start 10 +#define GEN75_VCS_RING_BUFFER_CTL_SemaphoreWait_start 10 +#define GEN7_VCS_RING_BUFFER_CTL_SemaphoreWait_start 10 +#define GEN6_VCS_RING_BUFFER_CTL_SemaphoreWait_start 10 + +static inline uint32_t ATTRIBUTE_PURE +VCS_RING_BUFFER_CTL_SemaphoreWait_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 10; + case 8: return 10; + case 7: + if (devinfo->is_haswell) { + return 10; + } else { + return 10; + } + case 6: return 10; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VECS_ACTHD_UDW */ + + +#define GEN9_VECS_ACTHD_UDW_length 1 +#define GEN8_VECS_ACTHD_UDW_length 1 + +static inline uint32_t ATTRIBUTE_PURE +VECS_ACTHD_UDW_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VECS_ACTHD_UDW::Head Pointer Upper DWORD */ + + +#define GEN9_VECS_ACTHD_UDW_HeadPointerUpperDWORD_bits 16 +#define GEN8_VECS_ACTHD_UDW_HeadPointerUpperDWORD_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +VECS_ACTHD_UDW_HeadPointerUpperDWORD_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_VECS_ACTHD_UDW_HeadPointerUpperDWORD_start 0 +#define GEN8_VECS_ACTHD_UDW_HeadPointerUpperDWORD_start 0 + +static inline uint32_t ATTRIBUTE_PURE +VECS_ACTHD_UDW_HeadPointerUpperDWORD_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VECS_FAULT_REG */ + + +#define GEN75_VECS_FAULT_REG_length 1 + +static inline uint32_t ATTRIBUTE_PURE +VECS_FAULT_REG_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VECS_FAULT_REG::Fault Type */ + + +#define GEN75_VECS_FAULT_REG_FaultType_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +VECS_FAULT_REG_FaultType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_VECS_FAULT_REG_FaultType_start 1 + +static inline uint32_t ATTRIBUTE_PURE +VECS_FAULT_REG_FaultType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VECS_FAULT_REG::GTTSEL */ + + +#define GEN75_VECS_FAULT_REG_GTTSEL_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VECS_FAULT_REG_GTTSEL_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_VECS_FAULT_REG_GTTSEL_start 11 + +static inline uint32_t ATTRIBUTE_PURE +VECS_FAULT_REG_GTTSEL_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 11; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VECS_FAULT_REG::SRCID of Fault */ + + +#define GEN75_VECS_FAULT_REG_SRCIDofFault_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +VECS_FAULT_REG_SRCIDofFault_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_VECS_FAULT_REG_SRCIDofFault_start 3 + +static inline uint32_t ATTRIBUTE_PURE +VECS_FAULT_REG_SRCIDofFault_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VECS_FAULT_REG::Valid Bit */ + + +#define GEN75_VECS_FAULT_REG_ValidBit_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VECS_FAULT_REG_ValidBit_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_VECS_FAULT_REG_ValidBit_start 0 + +static inline uint32_t ATTRIBUTE_PURE +VECS_FAULT_REG_ValidBit_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VECS_FAULT_REG::Virtual Address of Fault */ + + +#define GEN75_VECS_FAULT_REG_VirtualAddressofFault_bits 20 + +static inline uint32_t ATTRIBUTE_PURE +VECS_FAULT_REG_VirtualAddressofFault_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 20; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_VECS_FAULT_REG_VirtualAddressofFault_start 12 + +static inline uint32_t ATTRIBUTE_PURE +VECS_FAULT_REG_VirtualAddressofFault_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 12; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VECS_INSTDONE */ + + +#define GEN10_VECS_INSTDONE_length 1 +#define GEN9_VECS_INSTDONE_length 1 +#define GEN8_VECS_INSTDONE_length 1 +#define GEN75_VECS_INSTDONE_length 1 + +static inline uint32_t ATTRIBUTE_PURE +VECS_INSTDONE_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VECS_INSTDONE::GAM Done */ + + +#define GEN10_VECS_INSTDONE_GAMDone_bits 1 +#define GEN9_VECS_INSTDONE_GAMDone_bits 1 +#define GEN8_VECS_INSTDONE_GAMDone_bits 1 +#define GEN75_VECS_INSTDONE_GAMDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VECS_INSTDONE_GAMDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_VECS_INSTDONE_GAMDone_start 31 +#define GEN9_VECS_INSTDONE_GAMDone_start 31 +#define GEN8_VECS_INSTDONE_GAMDone_start 31 +#define GEN75_VECS_INSTDONE_GAMDone_start 31 + +static inline uint32_t ATTRIBUTE_PURE +VECS_INSTDONE_GAMDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 31; + case 9: return 31; + case 8: return 31; + case 7: + if (devinfo->is_haswell) { + return 31; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VECS_INSTDONE::Ring Enable */ + + +#define GEN10_VECS_INSTDONE_RingEnable_bits 1 +#define GEN9_VECS_INSTDONE_RingEnable_bits 1 +#define GEN8_VECS_INSTDONE_RingEnable_bits 1 +#define GEN75_VECS_INSTDONE_RingEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VECS_INSTDONE_RingEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_VECS_INSTDONE_RingEnable_start 0 +#define GEN9_VECS_INSTDONE_RingEnable_start 0 +#define GEN8_VECS_INSTDONE_RingEnable_start 0 +#define GEN75_VECS_INSTDONE_RingEnable_start 0 + +static inline uint32_t ATTRIBUTE_PURE +VECS_INSTDONE_RingEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VECS_INSTDONE::VECS Done */ + + +#define GEN10_VECS_INSTDONE_VECSDone_bits 1 +#define GEN9_VECS_INSTDONE_VECSDone_bits 1 +#define GEN8_VECS_INSTDONE_VECSDone_bits 1 +#define GEN75_VECS_INSTDONE_VECSDone_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VECS_INSTDONE_VECSDone_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN10_VECS_INSTDONE_VECSDone_start 30 +#define GEN9_VECS_INSTDONE_VECSDone_start 30 +#define GEN8_VECS_INSTDONE_VECSDone_start 30 +#define GEN75_VECS_INSTDONE_VECSDone_start 30 + +static inline uint32_t ATTRIBUTE_PURE +VECS_INSTDONE_VECSDone_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 30; + case 9: return 30; + case 8: return 30; + case 7: + if (devinfo->is_haswell) { + return 30; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VECS_RING_BUFFER_CTL */ + + +#define GEN9_VECS_RING_BUFFER_CTL_length 1 +#define GEN8_VECS_RING_BUFFER_CTL_length 1 +#define GEN75_VECS_RING_BUFFER_CTL_length 1 + +static inline uint32_t ATTRIBUTE_PURE +VECS_RING_BUFFER_CTL_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VECS_RING_BUFFER_CTL::Automatic Report Head Pointer */ + + +#define GEN9_VECS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 +#define GEN8_VECS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 +#define GEN75_VECS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +VECS_RING_BUFFER_CTL_AutomaticReportHeadPointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_VECS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 +#define GEN8_VECS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 +#define GEN75_VECS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start 1 + +static inline uint32_t ATTRIBUTE_PURE +VECS_RING_BUFFER_CTL_AutomaticReportHeadPointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VECS_RING_BUFFER_CTL::Buffer Length (in pages - 1) */ + + +#define GEN9_VECS_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 +#define GEN8_VECS_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 +#define GEN75_VECS_RING_BUFFER_CTL_BufferLengthinpages1_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +VECS_RING_BUFFER_CTL_BufferLengthinpages1_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_VECS_RING_BUFFER_CTL_BufferLengthinpages1_start 12 +#define GEN8_VECS_RING_BUFFER_CTL_BufferLengthinpages1_start 12 +#define GEN75_VECS_RING_BUFFER_CTL_BufferLengthinpages1_start 12 + +static inline uint32_t ATTRIBUTE_PURE +VECS_RING_BUFFER_CTL_BufferLengthinpages1_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 12; + case 8: return 12; + case 7: + if (devinfo->is_haswell) { + return 12; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VECS_RING_BUFFER_CTL::Disable Register Accesses */ + + +#define GEN9_VECS_RING_BUFFER_CTL_DisableRegisterAccesses_bits 1 +#define GEN8_VECS_RING_BUFFER_CTL_DisableRegisterAccesses_bits 1 +#define GEN75_VECS_RING_BUFFER_CTL_DisableRegisterAccesses_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VECS_RING_BUFFER_CTL_DisableRegisterAccesses_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_VECS_RING_BUFFER_CTL_DisableRegisterAccesses_start 8 +#define GEN8_VECS_RING_BUFFER_CTL_DisableRegisterAccesses_start 8 +#define GEN75_VECS_RING_BUFFER_CTL_DisableRegisterAccesses_start 8 + +static inline uint32_t ATTRIBUTE_PURE +VECS_RING_BUFFER_CTL_DisableRegisterAccesses_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 8; + case 8: return 8; + case 7: + if (devinfo->is_haswell) { + return 8; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VECS_RING_BUFFER_CTL::RBWait */ + + +#define GEN9_VECS_RING_BUFFER_CTL_RBWait_bits 1 +#define GEN8_VECS_RING_BUFFER_CTL_RBWait_bits 1 +#define GEN75_VECS_RING_BUFFER_CTL_RBWait_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VECS_RING_BUFFER_CTL_RBWait_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_VECS_RING_BUFFER_CTL_RBWait_start 11 +#define GEN8_VECS_RING_BUFFER_CTL_RBWait_start 11 +#define GEN75_VECS_RING_BUFFER_CTL_RBWait_start 11 + +static inline uint32_t ATTRIBUTE_PURE +VECS_RING_BUFFER_CTL_RBWait_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 11; + case 8: return 11; + case 7: + if (devinfo->is_haswell) { + return 11; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VECS_RING_BUFFER_CTL::Ring Buffer Enable */ + + +#define GEN9_VECS_RING_BUFFER_CTL_RingBufferEnable_bits 1 +#define GEN8_VECS_RING_BUFFER_CTL_RingBufferEnable_bits 1 +#define GEN75_VECS_RING_BUFFER_CTL_RingBufferEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VECS_RING_BUFFER_CTL_RingBufferEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_VECS_RING_BUFFER_CTL_RingBufferEnable_start 0 +#define GEN8_VECS_RING_BUFFER_CTL_RingBufferEnable_start 0 +#define GEN75_VECS_RING_BUFFER_CTL_RingBufferEnable_start 0 + +static inline uint32_t ATTRIBUTE_PURE +VECS_RING_BUFFER_CTL_RingBufferEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VECS_RING_BUFFER_CTL::Semaphore Wait */ + + +#define GEN9_VECS_RING_BUFFER_CTL_SemaphoreWait_bits 1 +#define GEN8_VECS_RING_BUFFER_CTL_SemaphoreWait_bits 1 +#define GEN75_VECS_RING_BUFFER_CTL_SemaphoreWait_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VECS_RING_BUFFER_CTL_SemaphoreWait_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN9_VECS_RING_BUFFER_CTL_SemaphoreWait_start 10 +#define GEN8_VECS_RING_BUFFER_CTL_SemaphoreWait_start 10 +#define GEN75_VECS_RING_BUFFER_CTL_SemaphoreWait_start 10 + +static inline uint32_t ATTRIBUTE_PURE +VECS_RING_BUFFER_CTL_SemaphoreWait_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 10; + case 8: return 10; + case 7: + if (devinfo->is_haswell) { + return 10; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VERTEX_BUFFER_STATE */ + + +#define GEN11_VERTEX_BUFFER_STATE_length 4 +#define GEN10_VERTEX_BUFFER_STATE_length 4 +#define GEN9_VERTEX_BUFFER_STATE_length 4 +#define GEN8_VERTEX_BUFFER_STATE_length 4 +#define GEN75_VERTEX_BUFFER_STATE_length 4 +#define GEN7_VERTEX_BUFFER_STATE_length 4 +#define GEN6_VERTEX_BUFFER_STATE_length 4 +#define GEN5_VERTEX_BUFFER_STATE_length 4 +#define GEN45_VERTEX_BUFFER_STATE_length 4 +#define GEN4_VERTEX_BUFFER_STATE_length 4 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_BUFFER_STATE_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 4; + case 10: return 4; + case 9: return 4; + case 8: return 4; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 4; + case 4: + if (devinfo->is_g4x) { + return 4; + } else { + return 4; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VERTEX_BUFFER_STATE::Address Modify Enable */ + + +#define GEN11_VERTEX_BUFFER_STATE_AddressModifyEnable_bits 1 +#define GEN10_VERTEX_BUFFER_STATE_AddressModifyEnable_bits 1 +#define GEN9_VERTEX_BUFFER_STATE_AddressModifyEnable_bits 1 +#define GEN8_VERTEX_BUFFER_STATE_AddressModifyEnable_bits 1 +#define GEN75_VERTEX_BUFFER_STATE_AddressModifyEnable_bits 1 +#define GEN7_VERTEX_BUFFER_STATE_AddressModifyEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_BUFFER_STATE_AddressModifyEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VERTEX_BUFFER_STATE_AddressModifyEnable_start 14 +#define GEN10_VERTEX_BUFFER_STATE_AddressModifyEnable_start 14 +#define GEN9_VERTEX_BUFFER_STATE_AddressModifyEnable_start 14 +#define GEN8_VERTEX_BUFFER_STATE_AddressModifyEnable_start 14 +#define GEN75_VERTEX_BUFFER_STATE_AddressModifyEnable_start 14 +#define GEN7_VERTEX_BUFFER_STATE_AddressModifyEnable_start 14 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_BUFFER_STATE_AddressModifyEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 14; + case 10: return 14; + case 9: return 14; + case 8: return 14; + case 7: + if (devinfo->is_haswell) { + return 14; + } else { + return 14; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VERTEX_BUFFER_STATE::Buffer Access Type */ + + +#define GEN75_VERTEX_BUFFER_STATE_BufferAccessType_bits 1 +#define GEN7_VERTEX_BUFFER_STATE_BufferAccessType_bits 1 +#define GEN6_VERTEX_BUFFER_STATE_BufferAccessType_bits 1 +#define GEN5_VERTEX_BUFFER_STATE_BufferAccessType_bits 1 +#define GEN45_VERTEX_BUFFER_STATE_BufferAccessType_bits 1 +#define GEN4_VERTEX_BUFFER_STATE_BufferAccessType_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_BUFFER_STATE_BufferAccessType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_VERTEX_BUFFER_STATE_BufferAccessType_start 20 +#define GEN7_VERTEX_BUFFER_STATE_BufferAccessType_start 20 +#define GEN6_VERTEX_BUFFER_STATE_BufferAccessType_start 20 +#define GEN5_VERTEX_BUFFER_STATE_BufferAccessType_start 26 +#define GEN45_VERTEX_BUFFER_STATE_BufferAccessType_start 26 +#define GEN4_VERTEX_BUFFER_STATE_BufferAccessType_start 26 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_BUFFER_STATE_BufferAccessType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 20; + } else { + return 20; + } + case 6: return 20; + case 5: return 26; + case 4: + if (devinfo->is_g4x) { + return 26; + } else { + return 26; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VERTEX_BUFFER_STATE::Buffer Pitch */ + + +#define GEN11_VERTEX_BUFFER_STATE_BufferPitch_bits 12 +#define GEN10_VERTEX_BUFFER_STATE_BufferPitch_bits 12 +#define GEN9_VERTEX_BUFFER_STATE_BufferPitch_bits 12 +#define GEN8_VERTEX_BUFFER_STATE_BufferPitch_bits 12 +#define GEN75_VERTEX_BUFFER_STATE_BufferPitch_bits 12 +#define GEN7_VERTEX_BUFFER_STATE_BufferPitch_bits 12 +#define GEN6_VERTEX_BUFFER_STATE_BufferPitch_bits 12 +#define GEN5_VERTEX_BUFFER_STATE_BufferPitch_bits 12 +#define GEN45_VERTEX_BUFFER_STATE_BufferPitch_bits 11 +#define GEN4_VERTEX_BUFFER_STATE_BufferPitch_bits 11 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_BUFFER_STATE_BufferPitch_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 12; + case 10: return 12; + case 9: return 12; + case 8: return 12; + case 7: + if (devinfo->is_haswell) { + return 12; + } else { + return 12; + } + case 6: return 12; + case 5: return 12; + case 4: + if (devinfo->is_g4x) { + return 11; + } else { + return 11; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VERTEX_BUFFER_STATE_BufferPitch_start 0 +#define GEN10_VERTEX_BUFFER_STATE_BufferPitch_start 0 +#define GEN9_VERTEX_BUFFER_STATE_BufferPitch_start 0 +#define GEN8_VERTEX_BUFFER_STATE_BufferPitch_start 0 +#define GEN75_VERTEX_BUFFER_STATE_BufferPitch_start 0 +#define GEN7_VERTEX_BUFFER_STATE_BufferPitch_start 0 +#define GEN6_VERTEX_BUFFER_STATE_BufferPitch_start 0 +#define GEN5_VERTEX_BUFFER_STATE_BufferPitch_start 0 +#define GEN45_VERTEX_BUFFER_STATE_BufferPitch_start 0 +#define GEN4_VERTEX_BUFFER_STATE_BufferPitch_start 0 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_BUFFER_STATE_BufferPitch_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VERTEX_BUFFER_STATE::Buffer Size */ + + +#define GEN11_VERTEX_BUFFER_STATE_BufferSize_bits 32 +#define GEN10_VERTEX_BUFFER_STATE_BufferSize_bits 32 +#define GEN9_VERTEX_BUFFER_STATE_BufferSize_bits 32 +#define GEN8_VERTEX_BUFFER_STATE_BufferSize_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_BUFFER_STATE_BufferSize_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VERTEX_BUFFER_STATE_BufferSize_start 96 +#define GEN10_VERTEX_BUFFER_STATE_BufferSize_start 96 +#define GEN9_VERTEX_BUFFER_STATE_BufferSize_start 96 +#define GEN8_VERTEX_BUFFER_STATE_BufferSize_start 96 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_BUFFER_STATE_BufferSize_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 96; + case 10: return 96; + case 9: return 96; + case 8: return 96; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VERTEX_BUFFER_STATE::Buffer Starting Address */ + + +#define GEN11_VERTEX_BUFFER_STATE_BufferStartingAddress_bits 64 +#define GEN10_VERTEX_BUFFER_STATE_BufferStartingAddress_bits 64 +#define GEN9_VERTEX_BUFFER_STATE_BufferStartingAddress_bits 64 +#define GEN8_VERTEX_BUFFER_STATE_BufferStartingAddress_bits 64 +#define GEN75_VERTEX_BUFFER_STATE_BufferStartingAddress_bits 32 +#define GEN7_VERTEX_BUFFER_STATE_BufferStartingAddress_bits 32 +#define GEN6_VERTEX_BUFFER_STATE_BufferStartingAddress_bits 32 +#define GEN5_VERTEX_BUFFER_STATE_BufferStartingAddress_bits 32 +#define GEN45_VERTEX_BUFFER_STATE_BufferStartingAddress_bits 32 +#define GEN4_VERTEX_BUFFER_STATE_BufferStartingAddress_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_BUFFER_STATE_BufferStartingAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VERTEX_BUFFER_STATE_BufferStartingAddress_start 32 +#define GEN10_VERTEX_BUFFER_STATE_BufferStartingAddress_start 32 +#define GEN9_VERTEX_BUFFER_STATE_BufferStartingAddress_start 32 +#define GEN8_VERTEX_BUFFER_STATE_BufferStartingAddress_start 32 +#define GEN75_VERTEX_BUFFER_STATE_BufferStartingAddress_start 32 +#define GEN7_VERTEX_BUFFER_STATE_BufferStartingAddress_start 32 +#define GEN6_VERTEX_BUFFER_STATE_BufferStartingAddress_start 32 +#define GEN5_VERTEX_BUFFER_STATE_BufferStartingAddress_start 32 +#define GEN45_VERTEX_BUFFER_STATE_BufferStartingAddress_start 32 +#define GEN4_VERTEX_BUFFER_STATE_BufferStartingAddress_start 32 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_BUFFER_STATE_BufferStartingAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 32; + case 10: return 32; + case 9: return 32; + case 8: return 32; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VERTEX_BUFFER_STATE::End Address */ + + +#define GEN75_VERTEX_BUFFER_STATE_EndAddress_bits 32 +#define GEN7_VERTEX_BUFFER_STATE_EndAddress_bits 32 +#define GEN6_VERTEX_BUFFER_STATE_EndAddress_bits 32 +#define GEN5_VERTEX_BUFFER_STATE_EndAddress_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_BUFFER_STATE_EndAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_VERTEX_BUFFER_STATE_EndAddress_start 64 +#define GEN7_VERTEX_BUFFER_STATE_EndAddress_start 64 +#define GEN6_VERTEX_BUFFER_STATE_EndAddress_start 64 +#define GEN5_VERTEX_BUFFER_STATE_EndAddress_start 64 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_BUFFER_STATE_EndAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 64; + case 5: return 64; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VERTEX_BUFFER_STATE::Instance Data Step Rate */ + + +#define GEN75_VERTEX_BUFFER_STATE_InstanceDataStepRate_bits 32 +#define GEN7_VERTEX_BUFFER_STATE_InstanceDataStepRate_bits 32 +#define GEN6_VERTEX_BUFFER_STATE_InstanceDataStepRate_bits 32 +#define GEN5_VERTEX_BUFFER_STATE_InstanceDataStepRate_bits 32 +#define GEN45_VERTEX_BUFFER_STATE_InstanceDataStepRate_bits 32 +#define GEN4_VERTEX_BUFFER_STATE_InstanceDataStepRate_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_BUFFER_STATE_InstanceDataStepRate_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 32; + } else { + return 32; + } + case 6: return 32; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_VERTEX_BUFFER_STATE_InstanceDataStepRate_start 96 +#define GEN7_VERTEX_BUFFER_STATE_InstanceDataStepRate_start 96 +#define GEN6_VERTEX_BUFFER_STATE_InstanceDataStepRate_start 96 +#define GEN5_VERTEX_BUFFER_STATE_InstanceDataStepRate_start 96 +#define GEN45_VERTEX_BUFFER_STATE_InstanceDataStepRate_start 96 +#define GEN4_VERTEX_BUFFER_STATE_InstanceDataStepRate_start 96 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_BUFFER_STATE_InstanceDataStepRate_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 96; + } else { + return 96; + } + case 6: return 96; + case 5: return 96; + case 4: + if (devinfo->is_g4x) { + return 96; + } else { + return 96; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VERTEX_BUFFER_STATE::MOCS */ + + +#define GEN11_VERTEX_BUFFER_STATE_MOCS_bits 7 +#define GEN10_VERTEX_BUFFER_STATE_MOCS_bits 7 +#define GEN9_VERTEX_BUFFER_STATE_MOCS_bits 7 +#define GEN8_VERTEX_BUFFER_STATE_MOCS_bits 7 +#define GEN75_VERTEX_BUFFER_STATE_MOCS_bits 4 +#define GEN7_VERTEX_BUFFER_STATE_MOCS_bits 4 +#define GEN6_VERTEX_BUFFER_STATE_MOCS_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_BUFFER_STATE_MOCS_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 7; + case 10: return 7; + case 9: return 7; + case 8: return 7; + case 7: + if (devinfo->is_haswell) { + return 4; + } else { + return 4; + } + case 6: return 4; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VERTEX_BUFFER_STATE_MOCS_start 16 +#define GEN10_VERTEX_BUFFER_STATE_MOCS_start 16 +#define GEN9_VERTEX_BUFFER_STATE_MOCS_start 16 +#define GEN8_VERTEX_BUFFER_STATE_MOCS_start 16 +#define GEN75_VERTEX_BUFFER_STATE_MOCS_start 16 +#define GEN7_VERTEX_BUFFER_STATE_MOCS_start 16 +#define GEN6_VERTEX_BUFFER_STATE_MOCS_start 16 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_BUFFER_STATE_MOCS_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VERTEX_BUFFER_STATE::Max Index */ + + +#define GEN45_VERTEX_BUFFER_STATE_MaxIndex_bits 32 +#define GEN4_VERTEX_BUFFER_STATE_MaxIndex_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_BUFFER_STATE_MaxIndex_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN45_VERTEX_BUFFER_STATE_MaxIndex_start 64 +#define GEN4_VERTEX_BUFFER_STATE_MaxIndex_start 64 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_BUFFER_STATE_MaxIndex_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 64; + } else { + return 64; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VERTEX_BUFFER_STATE::Null Vertex Buffer */ + + +#define GEN11_VERTEX_BUFFER_STATE_NullVertexBuffer_bits 1 +#define GEN10_VERTEX_BUFFER_STATE_NullVertexBuffer_bits 1 +#define GEN9_VERTEX_BUFFER_STATE_NullVertexBuffer_bits 1 +#define GEN8_VERTEX_BUFFER_STATE_NullVertexBuffer_bits 1 +#define GEN75_VERTEX_BUFFER_STATE_NullVertexBuffer_bits 1 +#define GEN7_VERTEX_BUFFER_STATE_NullVertexBuffer_bits 1 +#define GEN6_VERTEX_BUFFER_STATE_NullVertexBuffer_bits 1 +#define GEN5_VERTEX_BUFFER_STATE_NullVertexBuffer_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_BUFFER_STATE_NullVertexBuffer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VERTEX_BUFFER_STATE_NullVertexBuffer_start 13 +#define GEN10_VERTEX_BUFFER_STATE_NullVertexBuffer_start 13 +#define GEN9_VERTEX_BUFFER_STATE_NullVertexBuffer_start 13 +#define GEN8_VERTEX_BUFFER_STATE_NullVertexBuffer_start 13 +#define GEN75_VERTEX_BUFFER_STATE_NullVertexBuffer_start 13 +#define GEN7_VERTEX_BUFFER_STATE_NullVertexBuffer_start 13 +#define GEN6_VERTEX_BUFFER_STATE_NullVertexBuffer_start 13 +#define GEN5_VERTEX_BUFFER_STATE_NullVertexBuffer_start 13 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_BUFFER_STATE_NullVertexBuffer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 13; + case 10: return 13; + case 9: return 13; + case 8: return 13; + case 7: + if (devinfo->is_haswell) { + return 13; + } else { + return 13; + } + case 6: return 13; + case 5: return 13; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VERTEX_BUFFER_STATE::Vertex Buffer Index */ + + +#define GEN11_VERTEX_BUFFER_STATE_VertexBufferIndex_bits 6 +#define GEN10_VERTEX_BUFFER_STATE_VertexBufferIndex_bits 6 +#define GEN9_VERTEX_BUFFER_STATE_VertexBufferIndex_bits 6 +#define GEN8_VERTEX_BUFFER_STATE_VertexBufferIndex_bits 6 +#define GEN75_VERTEX_BUFFER_STATE_VertexBufferIndex_bits 6 +#define GEN7_VERTEX_BUFFER_STATE_VertexBufferIndex_bits 6 +#define GEN6_VERTEX_BUFFER_STATE_VertexBufferIndex_bits 6 +#define GEN5_VERTEX_BUFFER_STATE_VertexBufferIndex_bits 5 +#define GEN45_VERTEX_BUFFER_STATE_VertexBufferIndex_bits 5 +#define GEN4_VERTEX_BUFFER_STATE_VertexBufferIndex_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_BUFFER_STATE_VertexBufferIndex_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 6; + case 5: return 5; + case 4: + if (devinfo->is_g4x) { + return 5; + } else { + return 5; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VERTEX_BUFFER_STATE_VertexBufferIndex_start 26 +#define GEN10_VERTEX_BUFFER_STATE_VertexBufferIndex_start 26 +#define GEN9_VERTEX_BUFFER_STATE_VertexBufferIndex_start 26 +#define GEN8_VERTEX_BUFFER_STATE_VertexBufferIndex_start 26 +#define GEN75_VERTEX_BUFFER_STATE_VertexBufferIndex_start 26 +#define GEN7_VERTEX_BUFFER_STATE_VertexBufferIndex_start 26 +#define GEN6_VERTEX_BUFFER_STATE_VertexBufferIndex_start 26 +#define GEN5_VERTEX_BUFFER_STATE_VertexBufferIndex_start 27 +#define GEN45_VERTEX_BUFFER_STATE_VertexBufferIndex_start 27 +#define GEN4_VERTEX_BUFFER_STATE_VertexBufferIndex_start 27 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_BUFFER_STATE_VertexBufferIndex_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 26; + case 10: return 26; + case 9: return 26; + case 8: return 26; + case 7: + if (devinfo->is_haswell) { + return 26; + } else { + return 26; + } + case 6: return 26; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VERTEX_BUFFER_STATE::Vertex Fetch Invalidate */ + + +#define GEN75_VERTEX_BUFFER_STATE_VertexFetchInvalidate_bits 1 +#define GEN7_VERTEX_BUFFER_STATE_VertexFetchInvalidate_bits 1 +#define GEN6_VERTEX_BUFFER_STATE_VertexFetchInvalidate_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_BUFFER_STATE_VertexFetchInvalidate_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN75_VERTEX_BUFFER_STATE_VertexFetchInvalidate_start 12 +#define GEN7_VERTEX_BUFFER_STATE_VertexFetchInvalidate_start 12 +#define GEN6_VERTEX_BUFFER_STATE_VertexFetchInvalidate_start 12 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_BUFFER_STATE_VertexFetchInvalidate_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 12; + } else { + return 12; + } + case 6: return 12; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VERTEX_ELEMENT_STATE */ + + +#define GEN11_VERTEX_ELEMENT_STATE_length 2 +#define GEN10_VERTEX_ELEMENT_STATE_length 2 +#define GEN9_VERTEX_ELEMENT_STATE_length 2 +#define GEN8_VERTEX_ELEMENT_STATE_length 2 +#define GEN75_VERTEX_ELEMENT_STATE_length 2 +#define GEN7_VERTEX_ELEMENT_STATE_length 2 +#define GEN6_VERTEX_ELEMENT_STATE_length 2 +#define GEN5_VERTEX_ELEMENT_STATE_length 2 +#define GEN45_VERTEX_ELEMENT_STATE_length 2 +#define GEN4_VERTEX_ELEMENT_STATE_length 2 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_ELEMENT_STATE_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 2; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VERTEX_ELEMENT_STATE::Component 0 Control */ + + +#define GEN11_VERTEX_ELEMENT_STATE_Component0Control_bits 3 +#define GEN10_VERTEX_ELEMENT_STATE_Component0Control_bits 3 +#define GEN9_VERTEX_ELEMENT_STATE_Component0Control_bits 3 +#define GEN8_VERTEX_ELEMENT_STATE_Component0Control_bits 3 +#define GEN75_VERTEX_ELEMENT_STATE_Component0Control_bits 3 +#define GEN7_VERTEX_ELEMENT_STATE_Component0Control_bits 3 +#define GEN6_VERTEX_ELEMENT_STATE_Component0Control_bits 3 +#define GEN5_VERTEX_ELEMENT_STATE_Component0Control_bits 3 +#define GEN45_VERTEX_ELEMENT_STATE_Component0Control_bits 3 +#define GEN4_VERTEX_ELEMENT_STATE_Component0Control_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_ELEMENT_STATE_Component0Control_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VERTEX_ELEMENT_STATE_Component0Control_start 60 +#define GEN10_VERTEX_ELEMENT_STATE_Component0Control_start 60 +#define GEN9_VERTEX_ELEMENT_STATE_Component0Control_start 60 +#define GEN8_VERTEX_ELEMENT_STATE_Component0Control_start 60 +#define GEN75_VERTEX_ELEMENT_STATE_Component0Control_start 60 +#define GEN7_VERTEX_ELEMENT_STATE_Component0Control_start 60 +#define GEN6_VERTEX_ELEMENT_STATE_Component0Control_start 60 +#define GEN5_VERTEX_ELEMENT_STATE_Component0Control_start 60 +#define GEN45_VERTEX_ELEMENT_STATE_Component0Control_start 60 +#define GEN4_VERTEX_ELEMENT_STATE_Component0Control_start 60 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_ELEMENT_STATE_Component0Control_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 60; + case 10: return 60; + case 9: return 60; + case 8: return 60; + case 7: + if (devinfo->is_haswell) { + return 60; + } else { + return 60; + } + case 6: return 60; + case 5: return 60; + case 4: + if (devinfo->is_g4x) { + return 60; + } else { + return 60; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VERTEX_ELEMENT_STATE::Component 1 Control */ + + +#define GEN11_VERTEX_ELEMENT_STATE_Component1Control_bits 3 +#define GEN10_VERTEX_ELEMENT_STATE_Component1Control_bits 3 +#define GEN9_VERTEX_ELEMENT_STATE_Component1Control_bits 3 +#define GEN8_VERTEX_ELEMENT_STATE_Component1Control_bits 3 +#define GEN75_VERTEX_ELEMENT_STATE_Component1Control_bits 3 +#define GEN7_VERTEX_ELEMENT_STATE_Component1Control_bits 3 +#define GEN6_VERTEX_ELEMENT_STATE_Component1Control_bits 3 +#define GEN5_VERTEX_ELEMENT_STATE_Component1Control_bits 3 +#define GEN45_VERTEX_ELEMENT_STATE_Component1Control_bits 3 +#define GEN4_VERTEX_ELEMENT_STATE_Component1Control_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_ELEMENT_STATE_Component1Control_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VERTEX_ELEMENT_STATE_Component1Control_start 56 +#define GEN10_VERTEX_ELEMENT_STATE_Component1Control_start 56 +#define GEN9_VERTEX_ELEMENT_STATE_Component1Control_start 56 +#define GEN8_VERTEX_ELEMENT_STATE_Component1Control_start 56 +#define GEN75_VERTEX_ELEMENT_STATE_Component1Control_start 56 +#define GEN7_VERTEX_ELEMENT_STATE_Component1Control_start 56 +#define GEN6_VERTEX_ELEMENT_STATE_Component1Control_start 56 +#define GEN5_VERTEX_ELEMENT_STATE_Component1Control_start 56 +#define GEN45_VERTEX_ELEMENT_STATE_Component1Control_start 56 +#define GEN4_VERTEX_ELEMENT_STATE_Component1Control_start 56 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_ELEMENT_STATE_Component1Control_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 56; + case 10: return 56; + case 9: return 56; + case 8: return 56; + case 7: + if (devinfo->is_haswell) { + return 56; + } else { + return 56; + } + case 6: return 56; + case 5: return 56; + case 4: + if (devinfo->is_g4x) { + return 56; + } else { + return 56; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VERTEX_ELEMENT_STATE::Component 2 Control */ + + +#define GEN11_VERTEX_ELEMENT_STATE_Component2Control_bits 3 +#define GEN10_VERTEX_ELEMENT_STATE_Component2Control_bits 3 +#define GEN9_VERTEX_ELEMENT_STATE_Component2Control_bits 3 +#define GEN8_VERTEX_ELEMENT_STATE_Component2Control_bits 3 +#define GEN75_VERTEX_ELEMENT_STATE_Component2Control_bits 3 +#define GEN7_VERTEX_ELEMENT_STATE_Component2Control_bits 3 +#define GEN6_VERTEX_ELEMENT_STATE_Component2Control_bits 3 +#define GEN5_VERTEX_ELEMENT_STATE_Component2Control_bits 3 +#define GEN45_VERTEX_ELEMENT_STATE_Component2Control_bits 3 +#define GEN4_VERTEX_ELEMENT_STATE_Component2Control_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_ELEMENT_STATE_Component2Control_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VERTEX_ELEMENT_STATE_Component2Control_start 52 +#define GEN10_VERTEX_ELEMENT_STATE_Component2Control_start 52 +#define GEN9_VERTEX_ELEMENT_STATE_Component2Control_start 52 +#define GEN8_VERTEX_ELEMENT_STATE_Component2Control_start 52 +#define GEN75_VERTEX_ELEMENT_STATE_Component2Control_start 52 +#define GEN7_VERTEX_ELEMENT_STATE_Component2Control_start 52 +#define GEN6_VERTEX_ELEMENT_STATE_Component2Control_start 52 +#define GEN5_VERTEX_ELEMENT_STATE_Component2Control_start 52 +#define GEN45_VERTEX_ELEMENT_STATE_Component2Control_start 52 +#define GEN4_VERTEX_ELEMENT_STATE_Component2Control_start 52 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_ELEMENT_STATE_Component2Control_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 52; + case 10: return 52; + case 9: return 52; + case 8: return 52; + case 7: + if (devinfo->is_haswell) { + return 52; + } else { + return 52; + } + case 6: return 52; + case 5: return 52; + case 4: + if (devinfo->is_g4x) { + return 52; + } else { + return 52; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VERTEX_ELEMENT_STATE::Component 3 Control */ + + +#define GEN11_VERTEX_ELEMENT_STATE_Component3Control_bits 3 +#define GEN10_VERTEX_ELEMENT_STATE_Component3Control_bits 3 +#define GEN9_VERTEX_ELEMENT_STATE_Component3Control_bits 3 +#define GEN8_VERTEX_ELEMENT_STATE_Component3Control_bits 3 +#define GEN75_VERTEX_ELEMENT_STATE_Component3Control_bits 3 +#define GEN7_VERTEX_ELEMENT_STATE_Component3Control_bits 3 +#define GEN6_VERTEX_ELEMENT_STATE_Component3Control_bits 3 +#define GEN5_VERTEX_ELEMENT_STATE_Component3Control_bits 3 +#define GEN45_VERTEX_ELEMENT_STATE_Component3Control_bits 3 +#define GEN4_VERTEX_ELEMENT_STATE_Component3Control_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_ELEMENT_STATE_Component3Control_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 3; + case 10: return 3; + case 9: return 3; + case 8: return 3; + case 7: + if (devinfo->is_haswell) { + return 3; + } else { + return 3; + } + case 6: return 3; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VERTEX_ELEMENT_STATE_Component3Control_start 48 +#define GEN10_VERTEX_ELEMENT_STATE_Component3Control_start 48 +#define GEN9_VERTEX_ELEMENT_STATE_Component3Control_start 48 +#define GEN8_VERTEX_ELEMENT_STATE_Component3Control_start 48 +#define GEN75_VERTEX_ELEMENT_STATE_Component3Control_start 48 +#define GEN7_VERTEX_ELEMENT_STATE_Component3Control_start 48 +#define GEN6_VERTEX_ELEMENT_STATE_Component3Control_start 48 +#define GEN5_VERTEX_ELEMENT_STATE_Component3Control_start 48 +#define GEN45_VERTEX_ELEMENT_STATE_Component3Control_start 48 +#define GEN4_VERTEX_ELEMENT_STATE_Component3Control_start 48 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_ELEMENT_STATE_Component3Control_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 48; + case 10: return 48; + case 9: return 48; + case 8: return 48; + case 7: + if (devinfo->is_haswell) { + return 48; + } else { + return 48; + } + case 6: return 48; + case 5: return 48; + case 4: + if (devinfo->is_g4x) { + return 48; + } else { + return 48; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VERTEX_ELEMENT_STATE::Destination Element Offset */ + + +#define GEN5_VERTEX_ELEMENT_STATE_DestinationElementOffset_bits 8 +#define GEN45_VERTEX_ELEMENT_STATE_DestinationElementOffset_bits 8 +#define GEN4_VERTEX_ELEMENT_STATE_DestinationElementOffset_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_ELEMENT_STATE_DestinationElementOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_VERTEX_ELEMENT_STATE_DestinationElementOffset_start 32 +#define GEN45_VERTEX_ELEMENT_STATE_DestinationElementOffset_start 32 +#define GEN4_VERTEX_ELEMENT_STATE_DestinationElementOffset_start 32 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_ELEMENT_STATE_DestinationElementOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VERTEX_ELEMENT_STATE::Edge Flag Enable */ + + +#define GEN11_VERTEX_ELEMENT_STATE_EdgeFlagEnable_bits 1 +#define GEN10_VERTEX_ELEMENT_STATE_EdgeFlagEnable_bits 1 +#define GEN9_VERTEX_ELEMENT_STATE_EdgeFlagEnable_bits 1 +#define GEN8_VERTEX_ELEMENT_STATE_EdgeFlagEnable_bits 1 +#define GEN75_VERTEX_ELEMENT_STATE_EdgeFlagEnable_bits 1 +#define GEN7_VERTEX_ELEMENT_STATE_EdgeFlagEnable_bits 1 +#define GEN6_VERTEX_ELEMENT_STATE_EdgeFlagEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_ELEMENT_STATE_EdgeFlagEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VERTEX_ELEMENT_STATE_EdgeFlagEnable_start 15 +#define GEN10_VERTEX_ELEMENT_STATE_EdgeFlagEnable_start 15 +#define GEN9_VERTEX_ELEMENT_STATE_EdgeFlagEnable_start 15 +#define GEN8_VERTEX_ELEMENT_STATE_EdgeFlagEnable_start 15 +#define GEN75_VERTEX_ELEMENT_STATE_EdgeFlagEnable_start 15 +#define GEN7_VERTEX_ELEMENT_STATE_EdgeFlagEnable_start 15 +#define GEN6_VERTEX_ELEMENT_STATE_EdgeFlagEnable_start 15 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_ELEMENT_STATE_EdgeFlagEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 15; + case 10: return 15; + case 9: return 15; + case 8: return 15; + case 7: + if (devinfo->is_haswell) { + return 15; + } else { + return 15; + } + case 6: return 15; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VERTEX_ELEMENT_STATE::Source Element Format */ + + +#define GEN11_VERTEX_ELEMENT_STATE_SourceElementFormat_bits 9 +#define GEN10_VERTEX_ELEMENT_STATE_SourceElementFormat_bits 9 +#define GEN9_VERTEX_ELEMENT_STATE_SourceElementFormat_bits 9 +#define GEN8_VERTEX_ELEMENT_STATE_SourceElementFormat_bits 9 +#define GEN75_VERTEX_ELEMENT_STATE_SourceElementFormat_bits 9 +#define GEN7_VERTEX_ELEMENT_STATE_SourceElementFormat_bits 9 +#define GEN6_VERTEX_ELEMENT_STATE_SourceElementFormat_bits 9 +#define GEN5_VERTEX_ELEMENT_STATE_SourceElementFormat_bits 9 +#define GEN45_VERTEX_ELEMENT_STATE_SourceElementFormat_bits 9 +#define GEN4_VERTEX_ELEMENT_STATE_SourceElementFormat_bits 9 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_ELEMENT_STATE_SourceElementFormat_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 9; + case 10: return 9; + case 9: return 9; + case 8: return 9; + case 7: + if (devinfo->is_haswell) { + return 9; + } else { + return 9; + } + case 6: return 9; + case 5: return 9; + case 4: + if (devinfo->is_g4x) { + return 9; + } else { + return 9; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VERTEX_ELEMENT_STATE_SourceElementFormat_start 16 +#define GEN10_VERTEX_ELEMENT_STATE_SourceElementFormat_start 16 +#define GEN9_VERTEX_ELEMENT_STATE_SourceElementFormat_start 16 +#define GEN8_VERTEX_ELEMENT_STATE_SourceElementFormat_start 16 +#define GEN75_VERTEX_ELEMENT_STATE_SourceElementFormat_start 16 +#define GEN7_VERTEX_ELEMENT_STATE_SourceElementFormat_start 16 +#define GEN6_VERTEX_ELEMENT_STATE_SourceElementFormat_start 16 +#define GEN5_VERTEX_ELEMENT_STATE_SourceElementFormat_start 16 +#define GEN45_VERTEX_ELEMENT_STATE_SourceElementFormat_start 16 +#define GEN4_VERTEX_ELEMENT_STATE_SourceElementFormat_start 16 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_ELEMENT_STATE_SourceElementFormat_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 16; + case 10: return 16; + case 9: return 16; + case 8: return 16; + case 7: + if (devinfo->is_haswell) { + return 16; + } else { + return 16; + } + case 6: return 16; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VERTEX_ELEMENT_STATE::Source Element Offset */ + + +#define GEN11_VERTEX_ELEMENT_STATE_SourceElementOffset_bits 12 +#define GEN10_VERTEX_ELEMENT_STATE_SourceElementOffset_bits 12 +#define GEN9_VERTEX_ELEMENT_STATE_SourceElementOffset_bits 12 +#define GEN8_VERTEX_ELEMENT_STATE_SourceElementOffset_bits 12 +#define GEN75_VERTEX_ELEMENT_STATE_SourceElementOffset_bits 12 +#define GEN7_VERTEX_ELEMENT_STATE_SourceElementOffset_bits 12 +#define GEN6_VERTEX_ELEMENT_STATE_SourceElementOffset_bits 12 +#define GEN5_VERTEX_ELEMENT_STATE_SourceElementOffset_bits 11 +#define GEN45_VERTEX_ELEMENT_STATE_SourceElementOffset_bits 11 +#define GEN4_VERTEX_ELEMENT_STATE_SourceElementOffset_bits 11 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_ELEMENT_STATE_SourceElementOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 12; + case 10: return 12; + case 9: return 12; + case 8: return 12; + case 7: + if (devinfo->is_haswell) { + return 12; + } else { + return 12; + } + case 6: return 12; + case 5: return 11; + case 4: + if (devinfo->is_g4x) { + return 11; + } else { + return 11; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VERTEX_ELEMENT_STATE_SourceElementOffset_start 0 +#define GEN10_VERTEX_ELEMENT_STATE_SourceElementOffset_start 0 +#define GEN9_VERTEX_ELEMENT_STATE_SourceElementOffset_start 0 +#define GEN8_VERTEX_ELEMENT_STATE_SourceElementOffset_start 0 +#define GEN75_VERTEX_ELEMENT_STATE_SourceElementOffset_start 0 +#define GEN7_VERTEX_ELEMENT_STATE_SourceElementOffset_start 0 +#define GEN6_VERTEX_ELEMENT_STATE_SourceElementOffset_start 0 +#define GEN5_VERTEX_ELEMENT_STATE_SourceElementOffset_start 0 +#define GEN45_VERTEX_ELEMENT_STATE_SourceElementOffset_start 0 +#define GEN4_VERTEX_ELEMENT_STATE_SourceElementOffset_start 0 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_ELEMENT_STATE_SourceElementOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VERTEX_ELEMENT_STATE::Valid */ + + +#define GEN11_VERTEX_ELEMENT_STATE_Valid_bits 1 +#define GEN10_VERTEX_ELEMENT_STATE_Valid_bits 1 +#define GEN9_VERTEX_ELEMENT_STATE_Valid_bits 1 +#define GEN8_VERTEX_ELEMENT_STATE_Valid_bits 1 +#define GEN75_VERTEX_ELEMENT_STATE_Valid_bits 1 +#define GEN7_VERTEX_ELEMENT_STATE_Valid_bits 1 +#define GEN6_VERTEX_ELEMENT_STATE_Valid_bits 1 +#define GEN5_VERTEX_ELEMENT_STATE_Valid_bits 1 +#define GEN45_VERTEX_ELEMENT_STATE_Valid_bits 1 +#define GEN4_VERTEX_ELEMENT_STATE_Valid_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_ELEMENT_STATE_Valid_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 1; + case 10: return 1; + case 9: return 1; + case 8: return 1; + case 7: + if (devinfo->is_haswell) { + return 1; + } else { + return 1; + } + case 6: return 1; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VERTEX_ELEMENT_STATE_Valid_start 25 +#define GEN10_VERTEX_ELEMENT_STATE_Valid_start 25 +#define GEN9_VERTEX_ELEMENT_STATE_Valid_start 25 +#define GEN8_VERTEX_ELEMENT_STATE_Valid_start 25 +#define GEN75_VERTEX_ELEMENT_STATE_Valid_start 25 +#define GEN7_VERTEX_ELEMENT_STATE_Valid_start 25 +#define GEN6_VERTEX_ELEMENT_STATE_Valid_start 25 +#define GEN5_VERTEX_ELEMENT_STATE_Valid_start 26 +#define GEN45_VERTEX_ELEMENT_STATE_Valid_start 26 +#define GEN4_VERTEX_ELEMENT_STATE_Valid_start 26 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_ELEMENT_STATE_Valid_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 25; + case 10: return 25; + case 9: return 25; + case 8: return 25; + case 7: + if (devinfo->is_haswell) { + return 25; + } else { + return 25; + } + case 6: return 25; + case 5: return 26; + case 4: + if (devinfo->is_g4x) { + return 26; + } else { + return 26; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VERTEX_ELEMENT_STATE::Vertex Buffer Index */ + + +#define GEN11_VERTEX_ELEMENT_STATE_VertexBufferIndex_bits 6 +#define GEN10_VERTEX_ELEMENT_STATE_VertexBufferIndex_bits 6 +#define GEN9_VERTEX_ELEMENT_STATE_VertexBufferIndex_bits 6 +#define GEN8_VERTEX_ELEMENT_STATE_VertexBufferIndex_bits 6 +#define GEN75_VERTEX_ELEMENT_STATE_VertexBufferIndex_bits 6 +#define GEN7_VERTEX_ELEMENT_STATE_VertexBufferIndex_bits 6 +#define GEN6_VERTEX_ELEMENT_STATE_VertexBufferIndex_bits 6 +#define GEN5_VERTEX_ELEMENT_STATE_VertexBufferIndex_bits 5 +#define GEN45_VERTEX_ELEMENT_STATE_VertexBufferIndex_bits 5 +#define GEN4_VERTEX_ELEMENT_STATE_VertexBufferIndex_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_ELEMENT_STATE_VertexBufferIndex_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 6; + case 10: return 6; + case 9: return 6; + case 8: return 6; + case 7: + if (devinfo->is_haswell) { + return 6; + } else { + return 6; + } + case 6: return 6; + case 5: return 5; + case 4: + if (devinfo->is_g4x) { + return 5; + } else { + return 5; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VERTEX_ELEMENT_STATE_VertexBufferIndex_start 26 +#define GEN10_VERTEX_ELEMENT_STATE_VertexBufferIndex_start 26 +#define GEN9_VERTEX_ELEMENT_STATE_VertexBufferIndex_start 26 +#define GEN8_VERTEX_ELEMENT_STATE_VertexBufferIndex_start 26 +#define GEN75_VERTEX_ELEMENT_STATE_VertexBufferIndex_start 26 +#define GEN7_VERTEX_ELEMENT_STATE_VertexBufferIndex_start 26 +#define GEN6_VERTEX_ELEMENT_STATE_VertexBufferIndex_start 26 +#define GEN5_VERTEX_ELEMENT_STATE_VertexBufferIndex_start 27 +#define GEN45_VERTEX_ELEMENT_STATE_VertexBufferIndex_start 27 +#define GEN4_VERTEX_ELEMENT_STATE_VertexBufferIndex_start 27 + +static inline uint32_t ATTRIBUTE_PURE +VERTEX_ELEMENT_STATE_VertexBufferIndex_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 26; + case 10: return 26; + case 9: return 26; + case 8: return 26; + case 7: + if (devinfo->is_haswell) { + return 26; + } else { + return 26; + } + case 6: return 26; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VS_INVOCATION_COUNT */ + + +#define GEN11_VS_INVOCATION_COUNT_length 2 +#define GEN10_VS_INVOCATION_COUNT_length 2 +#define GEN9_VS_INVOCATION_COUNT_length 2 +#define GEN8_VS_INVOCATION_COUNT_length 2 +#define GEN75_VS_INVOCATION_COUNT_length 2 +#define GEN7_VS_INVOCATION_COUNT_length 2 + +static inline uint32_t ATTRIBUTE_PURE +VS_INVOCATION_COUNT_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 2; + case 10: return 2; + case 9: return 2; + case 8: return 2; + case 7: + if (devinfo->is_haswell) { + return 2; + } else { + return 2; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VS_INVOCATION_COUNT::VS Invocation Count Report */ + + +#define GEN11_VS_INVOCATION_COUNT_VSInvocationCountReport_bits 64 +#define GEN10_VS_INVOCATION_COUNT_VSInvocationCountReport_bits 64 +#define GEN9_VS_INVOCATION_COUNT_VSInvocationCountReport_bits 64 +#define GEN8_VS_INVOCATION_COUNT_VSInvocationCountReport_bits 64 +#define GEN75_VS_INVOCATION_COUNT_VSInvocationCountReport_bits 64 +#define GEN7_VS_INVOCATION_COUNT_VSInvocationCountReport_bits 64 + +static inline uint32_t ATTRIBUTE_PURE +VS_INVOCATION_COUNT_VSInvocationCountReport_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 64; + case 10: return 64; + case 9: return 64; + case 8: return 64; + case 7: + if (devinfo->is_haswell) { + return 64; + } else { + return 64; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN11_VS_INVOCATION_COUNT_VSInvocationCountReport_start 0 +#define GEN10_VS_INVOCATION_COUNT_VSInvocationCountReport_start 0 +#define GEN9_VS_INVOCATION_COUNT_VSInvocationCountReport_start 0 +#define GEN8_VS_INVOCATION_COUNT_VSInvocationCountReport_start 0 +#define GEN75_VS_INVOCATION_COUNT_VSInvocationCountReport_start 0 +#define GEN7_VS_INVOCATION_COUNT_VSInvocationCountReport_start 0 + +static inline uint32_t ATTRIBUTE_PURE +VS_INVOCATION_COUNT_VSInvocationCountReport_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VS_STATE */ + + +#define GEN5_VS_STATE_length 7 +#define GEN45_VS_STATE_length 7 +#define GEN4_VS_STATE_length 7 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 7; + case 4: + if (devinfo->is_g4x) { + return 7; + } else { + return 7; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VS_STATE::Binding Table Entry Count */ + + +#define GEN5_VS_STATE_BindingTableEntryCount_bits 8 +#define GEN45_VS_STATE_BindingTableEntryCount_bits 8 +#define GEN4_VS_STATE_BindingTableEntryCount_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_BindingTableEntryCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_VS_STATE_BindingTableEntryCount_start 50 +#define GEN45_VS_STATE_BindingTableEntryCount_start 50 +#define GEN4_VS_STATE_BindingTableEntryCount_start 50 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_BindingTableEntryCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 50; + case 4: + if (devinfo->is_g4x) { + return 50; + } else { + return 50; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VS_STATE::Constant URB Entry Read Length */ + + +#define GEN5_VS_STATE_ConstantURBEntryReadLength_bits 6 +#define GEN45_VS_STATE_ConstantURBEntryReadLength_bits 6 +#define GEN4_VS_STATE_ConstantURBEntryReadLength_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_ConstantURBEntryReadLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_VS_STATE_ConstantURBEntryReadLength_start 121 +#define GEN45_VS_STATE_ConstantURBEntryReadLength_start 121 +#define GEN4_VS_STATE_ConstantURBEntryReadLength_start 121 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_ConstantURBEntryReadLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 121; + case 4: + if (devinfo->is_g4x) { + return 121; + } else { + return 121; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VS_STATE::Constant URB Entry Read Offset */ + + +#define GEN5_VS_STATE_ConstantURBEntryReadOffset_bits 6 +#define GEN45_VS_STATE_ConstantURBEntryReadOffset_bits 6 +#define GEN4_VS_STATE_ConstantURBEntryReadOffset_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_ConstantURBEntryReadOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_VS_STATE_ConstantURBEntryReadOffset_start 114 +#define GEN45_VS_STATE_ConstantURBEntryReadOffset_start 114 +#define GEN4_VS_STATE_ConstantURBEntryReadOffset_start 114 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_ConstantURBEntryReadOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 114; + case 4: + if (devinfo->is_g4x) { + return 114; + } else { + return 114; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VS_STATE::Dispatch GRF Start Register For URB Data */ + + +#define GEN5_VS_STATE_DispatchGRFStartRegisterForURBData_bits 4 +#define GEN45_VS_STATE_DispatchGRFStartRegisterForURBData_bits 4 +#define GEN4_VS_STATE_DispatchGRFStartRegisterForURBData_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_DispatchGRFStartRegisterForURBData_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 4; + case 4: + if (devinfo->is_g4x) { + return 4; + } else { + return 4; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_VS_STATE_DispatchGRFStartRegisterForURBData_start 96 +#define GEN45_VS_STATE_DispatchGRFStartRegisterForURBData_start 96 +#define GEN4_VS_STATE_DispatchGRFStartRegisterForURBData_start 96 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_DispatchGRFStartRegisterForURBData_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 96; + case 4: + if (devinfo->is_g4x) { + return 96; + } else { + return 96; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VS_STATE::Enable */ + + +#define GEN5_VS_STATE_Enable_bits 1 +#define GEN45_VS_STATE_Enable_bits 1 +#define GEN4_VS_STATE_Enable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_Enable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_VS_STATE_Enable_start 192 +#define GEN45_VS_STATE_Enable_start 192 +#define GEN4_VS_STATE_Enable_start 192 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_Enable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 192; + case 4: + if (devinfo->is_g4x) { + return 192; + } else { + return 192; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VS_STATE::Floating Point Mode */ + + +#define GEN5_VS_STATE_FloatingPointMode_bits 1 +#define GEN45_VS_STATE_FloatingPointMode_bits 1 +#define GEN4_VS_STATE_FloatingPointMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_FloatingPointMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_VS_STATE_FloatingPointMode_start 48 +#define GEN45_VS_STATE_FloatingPointMode_start 48 +#define GEN4_VS_STATE_FloatingPointMode_start 48 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_FloatingPointMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 48; + case 4: + if (devinfo->is_g4x) { + return 48; + } else { + return 48; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VS_STATE::GRF Register Count */ + + +#define GEN5_VS_STATE_GRFRegisterCount_bits 3 +#define GEN45_VS_STATE_GRFRegisterCount_bits 3 +#define GEN4_VS_STATE_GRFRegisterCount_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_GRFRegisterCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_VS_STATE_GRFRegisterCount_start 1 +#define GEN45_VS_STATE_GRFRegisterCount_start 1 +#define GEN4_VS_STATE_GRFRegisterCount_start 1 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_GRFRegisterCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VS_STATE::Illegal Opcode Exception Enable */ + + +#define GEN5_VS_STATE_IllegalOpcodeExceptionEnable_bits 1 +#define GEN45_VS_STATE_IllegalOpcodeExceptionEnable_bits 1 +#define GEN4_VS_STATE_IllegalOpcodeExceptionEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_IllegalOpcodeExceptionEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_VS_STATE_IllegalOpcodeExceptionEnable_start 45 +#define GEN45_VS_STATE_IllegalOpcodeExceptionEnable_start 45 +#define GEN4_VS_STATE_IllegalOpcodeExceptionEnable_start 45 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_IllegalOpcodeExceptionEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 45; + case 4: + if (devinfo->is_g4x) { + return 45; + } else { + return 45; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VS_STATE::Kernel Start Pointer */ + + +#define GEN5_VS_STATE_KernelStartPointer_bits 26 +#define GEN45_VS_STATE_KernelStartPointer_bits 26 +#define GEN4_VS_STATE_KernelStartPointer_bits 26 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_KernelStartPointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 26; + case 4: + if (devinfo->is_g4x) { + return 26; + } else { + return 26; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_VS_STATE_KernelStartPointer_start 6 +#define GEN45_VS_STATE_KernelStartPointer_start 6 +#define GEN4_VS_STATE_KernelStartPointer_start 6 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_KernelStartPointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VS_STATE::Mask Stack Exception Enable */ + + +#define GEN5_VS_STATE_MaskStackExceptionEnable_bits 1 +#define GEN45_VS_STATE_MaskStackExceptionEnable_bits 1 +#define GEN4_VS_STATE_MaskStackExceptionEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_MaskStackExceptionEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_VS_STATE_MaskStackExceptionEnable_start 43 +#define GEN45_VS_STATE_MaskStackExceptionEnable_start 43 +#define GEN4_VS_STATE_MaskStackExceptionEnable_start 43 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_MaskStackExceptionEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 43; + case 4: + if (devinfo->is_g4x) { + return 43; + } else { + return 43; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VS_STATE::Maximum Number of Threads */ + + +#define GEN5_VS_STATE_MaximumNumberofThreads_bits 6 +#define GEN45_VS_STATE_MaximumNumberofThreads_bits 6 +#define GEN4_VS_STATE_MaximumNumberofThreads_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_MaximumNumberofThreads_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_VS_STATE_MaximumNumberofThreads_start 153 +#define GEN45_VS_STATE_MaximumNumberofThreads_start 153 +#define GEN4_VS_STATE_MaximumNumberofThreads_start 153 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_MaximumNumberofThreads_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 153; + case 4: + if (devinfo->is_g4x) { + return 153; + } else { + return 153; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VS_STATE::Number of URB Entries */ + + +#define GEN5_VS_STATE_NumberofURBEntries_bits 8 +#define GEN45_VS_STATE_NumberofURBEntries_bits 8 +#define GEN4_VS_STATE_NumberofURBEntries_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_NumberofURBEntries_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_VS_STATE_NumberofURBEntries_start 139 +#define GEN45_VS_STATE_NumberofURBEntries_start 139 +#define GEN4_VS_STATE_NumberofURBEntries_start 139 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_NumberofURBEntries_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 139; + case 4: + if (devinfo->is_g4x) { + return 139; + } else { + return 139; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VS_STATE::Per-Thread Scratch Space */ + + +#define GEN5_VS_STATE_PerThreadScratchSpace_bits 4 +#define GEN45_VS_STATE_PerThreadScratchSpace_bits 4 +#define GEN4_VS_STATE_PerThreadScratchSpace_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_PerThreadScratchSpace_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 4; + case 4: + if (devinfo->is_g4x) { + return 4; + } else { + return 4; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_VS_STATE_PerThreadScratchSpace_start 64 +#define GEN45_VS_STATE_PerThreadScratchSpace_start 64 +#define GEN4_VS_STATE_PerThreadScratchSpace_start 64 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_PerThreadScratchSpace_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 64; + case 4: + if (devinfo->is_g4x) { + return 64; + } else { + return 64; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VS_STATE::Sampler Count */ + + +#define GEN5_VS_STATE_SamplerCount_bits 3 +#define GEN45_VS_STATE_SamplerCount_bits 3 +#define GEN4_VS_STATE_SamplerCount_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_SamplerCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_VS_STATE_SamplerCount_start 160 +#define GEN45_VS_STATE_SamplerCount_start 160 +#define GEN4_VS_STATE_SamplerCount_start 160 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_SamplerCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 160; + case 4: + if (devinfo->is_g4x) { + return 160; + } else { + return 160; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VS_STATE::Sampler State Pointer */ + + +#define GEN5_VS_STATE_SamplerStatePointer_bits 27 +#define GEN45_VS_STATE_SamplerStatePointer_bits 27 +#define GEN4_VS_STATE_SamplerStatePointer_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_SamplerStatePointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_VS_STATE_SamplerStatePointer_start 165 +#define GEN45_VS_STATE_SamplerStatePointer_start 165 +#define GEN4_VS_STATE_SamplerStatePointer_start 165 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_SamplerStatePointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 165; + case 4: + if (devinfo->is_g4x) { + return 165; + } else { + return 165; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VS_STATE::Scratch Space Base Pointer */ + + +#define GEN5_VS_STATE_ScratchSpaceBasePointer_bits 22 +#define GEN45_VS_STATE_ScratchSpaceBasePointer_bits 22 +#define GEN4_VS_STATE_ScratchSpaceBasePointer_bits 22 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_ScratchSpaceBasePointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 22; + case 4: + if (devinfo->is_g4x) { + return 22; + } else { + return 22; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_VS_STATE_ScratchSpaceBasePointer_start 74 +#define GEN45_VS_STATE_ScratchSpaceBasePointer_start 74 +#define GEN4_VS_STATE_ScratchSpaceBasePointer_start 74 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_ScratchSpaceBasePointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 74; + case 4: + if (devinfo->is_g4x) { + return 74; + } else { + return 74; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VS_STATE::Single Program Flow */ + + +#define GEN5_VS_STATE_SingleProgramFlow_bits 1 +#define GEN45_VS_STATE_SingleProgramFlow_bits 1 +#define GEN4_VS_STATE_SingleProgramFlow_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_SingleProgramFlow_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_VS_STATE_SingleProgramFlow_start 63 +#define GEN45_VS_STATE_SingleProgramFlow_start 63 +#define GEN4_VS_STATE_SingleProgramFlow_start 63 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_SingleProgramFlow_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 63; + case 4: + if (devinfo->is_g4x) { + return 63; + } else { + return 63; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VS_STATE::Software Exception Enable */ + + +#define GEN5_VS_STATE_SoftwareExceptionEnable_bits 1 +#define GEN45_VS_STATE_SoftwareExceptionEnable_bits 1 +#define GEN4_VS_STATE_SoftwareExceptionEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_SoftwareExceptionEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_VS_STATE_SoftwareExceptionEnable_start 39 +#define GEN45_VS_STATE_SoftwareExceptionEnable_start 39 +#define GEN4_VS_STATE_SoftwareExceptionEnable_start 39 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_SoftwareExceptionEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 39; + case 4: + if (devinfo->is_g4x) { + return 39; + } else { + return 39; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VS_STATE::Statistics Enable */ + + +#define GEN5_VS_STATE_StatisticsEnable_bits 1 +#define GEN45_VS_STATE_StatisticsEnable_bits 1 +#define GEN4_VS_STATE_StatisticsEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_StatisticsEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_VS_STATE_StatisticsEnable_start 138 +#define GEN45_VS_STATE_StatisticsEnable_start 138 +#define GEN4_VS_STATE_StatisticsEnable_start 138 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_StatisticsEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 138; + case 4: + if (devinfo->is_g4x) { + return 138; + } else { + return 138; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VS_STATE::Thread Priority */ + + +#define GEN5_VS_STATE_ThreadPriority_bits 1 +#define GEN45_VS_STATE_ThreadPriority_bits 1 +#define GEN4_VS_STATE_ThreadPriority_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_ThreadPriority_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_VS_STATE_ThreadPriority_start 49 +#define GEN45_VS_STATE_ThreadPriority_start 49 +#define GEN4_VS_STATE_ThreadPriority_start 49 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_ThreadPriority_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 49; + case 4: + if (devinfo->is_g4x) { + return 49; + } else { + return 49; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VS_STATE::URB Entry Allocation Size */ + + +#define GEN5_VS_STATE_URBEntryAllocationSize_bits 5 +#define GEN45_VS_STATE_URBEntryAllocationSize_bits 5 +#define GEN4_VS_STATE_URBEntryAllocationSize_bits 5 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_URBEntryAllocationSize_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 5; + case 4: + if (devinfo->is_g4x) { + return 5; + } else { + return 5; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_VS_STATE_URBEntryAllocationSize_start 147 +#define GEN45_VS_STATE_URBEntryAllocationSize_start 147 +#define GEN4_VS_STATE_URBEntryAllocationSize_start 147 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_URBEntryAllocationSize_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 147; + case 4: + if (devinfo->is_g4x) { + return 147; + } else { + return 147; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VS_STATE::Vertex Cache Disable */ + + +#define GEN5_VS_STATE_VertexCacheDisable_bits 1 +#define GEN45_VS_STATE_VertexCacheDisable_bits 1 +#define GEN4_VS_STATE_VertexCacheDisable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_VertexCacheDisable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_VS_STATE_VertexCacheDisable_start 193 +#define GEN45_VS_STATE_VertexCacheDisable_start 193 +#define GEN4_VS_STATE_VertexCacheDisable_start 193 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_VertexCacheDisable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 193; + case 4: + if (devinfo->is_g4x) { + return 193; + } else { + return 193; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VS_STATE::Vertex URB Entry Read Length */ + + +#define GEN5_VS_STATE_VertexURBEntryReadLength_bits 6 +#define GEN45_VS_STATE_VertexURBEntryReadLength_bits 6 +#define GEN4_VS_STATE_VertexURBEntryReadLength_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_VertexURBEntryReadLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_VS_STATE_VertexURBEntryReadLength_start 107 +#define GEN45_VS_STATE_VertexURBEntryReadLength_start 107 +#define GEN4_VS_STATE_VertexURBEntryReadLength_start 107 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_VertexURBEntryReadLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 107; + case 4: + if (devinfo->is_g4x) { + return 107; + } else { + return 107; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* VS_STATE::Vertex URB Entry Read Offset */ + + +#define GEN5_VS_STATE_VertexURBEntryReadOffset_bits 6 +#define GEN45_VS_STATE_VertexURBEntryReadOffset_bits 6 +#define GEN4_VS_STATE_VertexURBEntryReadOffset_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_VertexURBEntryReadOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_VS_STATE_VertexURBEntryReadOffset_start 100 +#define GEN45_VS_STATE_VertexURBEntryReadOffset_start 100 +#define GEN4_VS_STATE_VertexURBEntryReadOffset_start 100 + +static inline uint32_t ATTRIBUTE_PURE +VS_STATE_VertexURBEntryReadOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 100; + case 4: + if (devinfo->is_g4x) { + return 100; + } else { + return 100; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE */ + + +#define GEN5_WM_STATE_length 11 +#define GEN45_WM_STATE_length 8 +#define GEN4_WM_STATE_length 8 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 11; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::16 Pixel Dispatch Enable */ + + +#define GEN5_WM_STATE_16PixelDispatchEnable_bits 1 +#define GEN45_WM_STATE_16PixelDispatchEnable_bits 1 +#define GEN4_WM_STATE_16PixelDispatchEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_16PixelDispatchEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_16PixelDispatchEnable_start 161 +#define GEN45_WM_STATE_16PixelDispatchEnable_start 161 +#define GEN4_WM_STATE_16PixelDispatchEnable_start 161 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_16PixelDispatchEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 161; + case 4: + if (devinfo->is_g4x) { + return 161; + } else { + return 161; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::32 Pixel Dispatch Enable */ + + +#define GEN5_WM_STATE_32PixelDispatchEnable_bits 1 +#define GEN45_WM_STATE_32PixelDispatchEnable_bits 1 +#define GEN4_WM_STATE_32PixelDispatchEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_32PixelDispatchEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_32PixelDispatchEnable_start 162 +#define GEN45_WM_STATE_32PixelDispatchEnable_start 162 +#define GEN4_WM_STATE_32PixelDispatchEnable_start 162 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_32PixelDispatchEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 162; + case 4: + if (devinfo->is_g4x) { + return 162; + } else { + return 162; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::8 Pixel Dispatch Enable */ + + +#define GEN5_WM_STATE_8PixelDispatchEnable_bits 1 +#define GEN45_WM_STATE_8PixelDispatchEnable_bits 1 +#define GEN4_WM_STATE_8PixelDispatchEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_8PixelDispatchEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_8PixelDispatchEnable_start 160 +#define GEN45_WM_STATE_8PixelDispatchEnable_start 160 +#define GEN4_WM_STATE_8PixelDispatchEnable_start 160 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_8PixelDispatchEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 160; + case 4: + if (devinfo->is_g4x) { + return 160; + } else { + return 160; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Binding Table Entry Count */ + + +#define GEN5_WM_STATE_BindingTableEntryCount_bits 8 +#define GEN45_WM_STATE_BindingTableEntryCount_bits 8 +#define GEN4_WM_STATE_BindingTableEntryCount_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_BindingTableEntryCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_BindingTableEntryCount_start 50 +#define GEN45_WM_STATE_BindingTableEntryCount_start 50 +#define GEN4_WM_STATE_BindingTableEntryCount_start 50 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_BindingTableEntryCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 50; + case 4: + if (devinfo->is_g4x) { + return 50; + } else { + return 50; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Constant URB Entry Read Length */ + + +#define GEN5_WM_STATE_ConstantURBEntryReadLength_bits 6 +#define GEN45_WM_STATE_ConstantURBEntryReadLength_bits 6 +#define GEN4_WM_STATE_ConstantURBEntryReadLength_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_ConstantURBEntryReadLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_ConstantURBEntryReadLength_start 121 +#define GEN45_WM_STATE_ConstantURBEntryReadLength_start 121 +#define GEN4_WM_STATE_ConstantURBEntryReadLength_start 121 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_ConstantURBEntryReadLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 121; + case 4: + if (devinfo->is_g4x) { + return 121; + } else { + return 121; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Constant URB Entry Read Offset */ + + +#define GEN5_WM_STATE_ConstantURBEntryReadOffset_bits 6 +#define GEN45_WM_STATE_ConstantURBEntryReadOffset_bits 6 +#define GEN4_WM_STATE_ConstantURBEntryReadOffset_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_ConstantURBEntryReadOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_ConstantURBEntryReadOffset_start 114 +#define GEN45_WM_STATE_ConstantURBEntryReadOffset_start 114 +#define GEN4_WM_STATE_ConstantURBEntryReadOffset_start 114 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_ConstantURBEntryReadOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 114; + case 4: + if (devinfo->is_g4x) { + return 114; + } else { + return 114; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Contiguous 32 Pixel Dispatch Enable */ + + +#define GEN5_WM_STATE_Contiguous32PixelDispatchEnable_bits 1 +#define GEN45_WM_STATE_Contiguous32PixelDispatchEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_Contiguous32PixelDispatchEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_Contiguous32PixelDispatchEnable_start 163 +#define GEN45_WM_STATE_Contiguous32PixelDispatchEnable_start 163 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_Contiguous32PixelDispatchEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 163; + case 4: + if (devinfo->is_g4x) { + return 163; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Contiguous 64 Pixel Dispatch Enable */ + + +#define GEN5_WM_STATE_Contiguous64PixelDispatchEnable_bits 1 +#define GEN45_WM_STATE_Contiguous64PixelDispatchEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_Contiguous64PixelDispatchEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_Contiguous64PixelDispatchEnable_start 164 +#define GEN45_WM_STATE_Contiguous64PixelDispatchEnable_start 164 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_Contiguous64PixelDispatchEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 164; + case 4: + if (devinfo->is_g4x) { + return 164; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Depth Buffer Clear */ + + +#define GEN5_WM_STATE_DepthBufferClear_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_DepthBufferClear_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_DepthBufferClear_start 167 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_DepthBufferClear_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 167; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Depth Buffer Resolve Enable */ + + +#define GEN5_WM_STATE_DepthBufferResolveEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_DepthBufferResolveEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_DepthBufferResolveEnable_start 168 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_DepthBufferResolveEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 168; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Depth Coefficient URB Read Offset */ + + +#define GEN5_WM_STATE_DepthCoefficientURBReadOffset_bits 6 +#define GEN45_WM_STATE_DepthCoefficientURBReadOffset_bits 6 +#define GEN4_WM_STATE_DepthCoefficientURBReadOffset_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_DepthCoefficientURBReadOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_DepthCoefficientURBReadOffset_start 40 +#define GEN45_WM_STATE_DepthCoefficientURBReadOffset_start 40 +#define GEN4_WM_STATE_DepthCoefficientURBReadOffset_start 40 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_DepthCoefficientURBReadOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 40; + case 4: + if (devinfo->is_g4x) { + return 40; + } else { + return 40; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Dispatch GRF Start Register For Constant/Setup Data 0 */ + + +#define GEN5_WM_STATE_DispatchGRFStartRegisterForConstantSetupData0_bits 4 +#define GEN45_WM_STATE_DispatchGRFStartRegisterForConstantSetupData0_bits 4 +#define GEN4_WM_STATE_DispatchGRFStartRegisterForConstantSetupData0_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_DispatchGRFStartRegisterForConstantSetupData0_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 4; + case 4: + if (devinfo->is_g4x) { + return 4; + } else { + return 4; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_DispatchGRFStartRegisterForConstantSetupData0_start 96 +#define GEN45_WM_STATE_DispatchGRFStartRegisterForConstantSetupData0_start 96 +#define GEN4_WM_STATE_DispatchGRFStartRegisterForConstantSetupData0_start 96 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_DispatchGRFStartRegisterForConstantSetupData0_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 96; + case 4: + if (devinfo->is_g4x) { + return 96; + } else { + return 96; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Early Depth Test Enable */ + + +#define GEN5_WM_STATE_EarlyDepthTestEnable_bits 1 +#define GEN45_WM_STATE_EarlyDepthTestEnable_bits 1 +#define GEN4_WM_STATE_EarlyDepthTestEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_EarlyDepthTestEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_EarlyDepthTestEnable_start 178 +#define GEN45_WM_STATE_EarlyDepthTestEnable_start 178 +#define GEN4_WM_STATE_EarlyDepthTestEnable_start 178 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_EarlyDepthTestEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 178; + case 4: + if (devinfo->is_g4x) { + return 178; + } else { + return 178; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Fast Span Coverage Enable */ + + +#define GEN5_WM_STATE_FastSpanCoverageEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_FastSpanCoverageEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_FastSpanCoverageEnable_start 166 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_FastSpanCoverageEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 166; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Floating Point Mode */ + + +#define GEN5_WM_STATE_FloatingPointMode_bits 1 +#define GEN45_WM_STATE_FloatingPointMode_bits 1 +#define GEN4_WM_STATE_FloatingPointMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_FloatingPointMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_FloatingPointMode_start 48 +#define GEN45_WM_STATE_FloatingPointMode_start 48 +#define GEN4_WM_STATE_FloatingPointMode_start 48 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_FloatingPointMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 48; + case 4: + if (devinfo->is_g4x) { + return 48; + } else { + return 48; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::GRF Register Count 0 */ + + +#define GEN5_WM_STATE_GRFRegisterCount0_bits 3 +#define GEN45_WM_STATE_GRFRegisterCount0_bits 3 +#define GEN4_WM_STATE_GRFRegisterCount0_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_GRFRegisterCount0_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_GRFRegisterCount0_start 1 +#define GEN45_WM_STATE_GRFRegisterCount0_start 1 +#define GEN4_WM_STATE_GRFRegisterCount0_start 1 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_GRFRegisterCount0_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::GRF Register Count 1 */ + + +#define GEN5_WM_STATE_GRFRegisterCount1_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_GRFRegisterCount1_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_GRFRegisterCount1_start 257 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_GRFRegisterCount1_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 257; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::GRF Register Count 2 */ + + +#define GEN5_WM_STATE_GRFRegisterCount2_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_GRFRegisterCount2_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_GRFRegisterCount2_start 289 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_GRFRegisterCount2_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 289; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::GRF Register Count 3 */ + + +#define GEN5_WM_STATE_GRFRegisterCount3_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_GRFRegisterCount3_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_GRFRegisterCount3_start 321 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_GRFRegisterCount3_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 321; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Global Depth Offset Constant */ + + +#define GEN5_WM_STATE_GlobalDepthOffsetConstant_bits 32 +#define GEN45_WM_STATE_GlobalDepthOffsetConstant_bits 32 +#define GEN4_WM_STATE_GlobalDepthOffsetConstant_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_GlobalDepthOffsetConstant_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_GlobalDepthOffsetConstant_start 192 +#define GEN45_WM_STATE_GlobalDepthOffsetConstant_start 192 +#define GEN4_WM_STATE_GlobalDepthOffsetConstant_start 192 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_GlobalDepthOffsetConstant_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 192; + case 4: + if (devinfo->is_g4x) { + return 192; + } else { + return 192; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Global Depth Offset Enable */ + + +#define GEN5_WM_STATE_GlobalDepthOffsetEnable_bits 1 +#define GEN45_WM_STATE_GlobalDepthOffsetEnable_bits 1 +#define GEN4_WM_STATE_GlobalDepthOffsetEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_GlobalDepthOffsetEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_GlobalDepthOffsetEnable_start 172 +#define GEN45_WM_STATE_GlobalDepthOffsetEnable_start 172 +#define GEN4_WM_STATE_GlobalDepthOffsetEnable_start 172 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_GlobalDepthOffsetEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 172; + case 4: + if (devinfo->is_g4x) { + return 172; + } else { + return 172; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Global Depth Offset Scale */ + + +#define GEN5_WM_STATE_GlobalDepthOffsetScale_bits 32 +#define GEN45_WM_STATE_GlobalDepthOffsetScale_bits 32 +#define GEN4_WM_STATE_GlobalDepthOffsetScale_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_GlobalDepthOffsetScale_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_GlobalDepthOffsetScale_start 224 +#define GEN45_WM_STATE_GlobalDepthOffsetScale_start 224 +#define GEN4_WM_STATE_GlobalDepthOffsetScale_start 224 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_GlobalDepthOffsetScale_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 224; + case 4: + if (devinfo->is_g4x) { + return 224; + } else { + return 224; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Hierarchical Depth Buffer Resolve Enable */ + + +#define GEN5_WM_STATE_HierarchicalDepthBufferResolveEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_HierarchicalDepthBufferResolveEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_HierarchicalDepthBufferResolveEnable_start 169 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_HierarchicalDepthBufferResolveEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 169; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Illegal Opcode Exception Enable */ + + +#define GEN5_WM_STATE_IllegalOpcodeExceptionEnable_bits 1 +#define GEN45_WM_STATE_IllegalOpcodeExceptionEnable_bits 1 +#define GEN4_WM_STATE_IllegalOpcodeExceptionEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_IllegalOpcodeExceptionEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_IllegalOpcodeExceptionEnable_start 36 +#define GEN45_WM_STATE_IllegalOpcodeExceptionEnable_start 36 +#define GEN4_WM_STATE_IllegalOpcodeExceptionEnable_start 36 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_IllegalOpcodeExceptionEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 36; + case 4: + if (devinfo->is_g4x) { + return 36; + } else { + return 36; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Kernel Start Pointer 0 */ + + +#define GEN5_WM_STATE_KernelStartPointer0_bits 26 +#define GEN45_WM_STATE_KernelStartPointer0_bits 26 +#define GEN4_WM_STATE_KernelStartPointer0_bits 26 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_KernelStartPointer0_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 26; + case 4: + if (devinfo->is_g4x) { + return 26; + } else { + return 26; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_KernelStartPointer0_start 6 +#define GEN45_WM_STATE_KernelStartPointer0_start 6 +#define GEN4_WM_STATE_KernelStartPointer0_start 6 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_KernelStartPointer0_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Kernel Start Pointer 1 */ + + +#define GEN5_WM_STATE_KernelStartPointer1_bits 26 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_KernelStartPointer1_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 26; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_KernelStartPointer1_start 262 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_KernelStartPointer1_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 262; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Kernel Start Pointer 2 */ + + +#define GEN5_WM_STATE_KernelStartPointer2_bits 26 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_KernelStartPointer2_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 26; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_KernelStartPointer2_start 294 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_KernelStartPointer2_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 294; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Kernel Start Pointer 3 */ + + +#define GEN5_WM_STATE_KernelStartPointer3_bits 26 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_KernelStartPointer3_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 26; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_KernelStartPointer3_start 326 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_KernelStartPointer3_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 326; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Legacy Diamond Line Rasterization */ + + +#define GEN5_WM_STATE_LegacyDiamondLineRasterization_bits 1 +#define GEN45_WM_STATE_LegacyDiamondLineRasterization_bits 1 +#define GEN4_WM_STATE_LegacyDiamondLineRasterization_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_LegacyDiamondLineRasterization_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_LegacyDiamondLineRasterization_start 183 +#define GEN45_WM_STATE_LegacyDiamondLineRasterization_start 183 +#define GEN4_WM_STATE_LegacyDiamondLineRasterization_start 183 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_LegacyDiamondLineRasterization_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 183; + case 4: + if (devinfo->is_g4x) { + return 183; + } else { + return 183; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Legacy Global Depth Bias Enable */ + + +#define GEN5_WM_STATE_LegacyGlobalDepthBiasEnable_bits 1 +#define GEN45_WM_STATE_LegacyGlobalDepthBiasEnable_bits 1 +#define GEN4_WM_STATE_LegacyGlobalDepthBiasEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_LegacyGlobalDepthBiasEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_LegacyGlobalDepthBiasEnable_start 170 +#define GEN45_WM_STATE_LegacyGlobalDepthBiasEnable_start 170 +#define GEN4_WM_STATE_LegacyGlobalDepthBiasEnable_start 170 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_LegacyGlobalDepthBiasEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 170; + case 4: + if (devinfo->is_g4x) { + return 170; + } else { + return 170; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Line Antialiasing Region Width */ + + +#define GEN5_WM_STATE_LineAntialiasingRegionWidth_bits 2 +#define GEN45_WM_STATE_LineAntialiasingRegionWidth_bits 2 +#define GEN4_WM_STATE_LineAntialiasingRegionWidth_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_LineAntialiasingRegionWidth_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_LineAntialiasingRegionWidth_start 174 +#define GEN45_WM_STATE_LineAntialiasingRegionWidth_start 174 +#define GEN4_WM_STATE_LineAntialiasingRegionWidth_start 174 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_LineAntialiasingRegionWidth_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 174; + case 4: + if (devinfo->is_g4x) { + return 174; + } else { + return 174; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Line End Cap Antialiasing Region Width */ + + +#define GEN5_WM_STATE_LineEndCapAntialiasingRegionWidth_bits 2 +#define GEN45_WM_STATE_LineEndCapAntialiasingRegionWidth_bits 2 +#define GEN4_WM_STATE_LineEndCapAntialiasingRegionWidth_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_LineEndCapAntialiasingRegionWidth_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_LineEndCapAntialiasingRegionWidth_start 176 +#define GEN45_WM_STATE_LineEndCapAntialiasingRegionWidth_start 176 +#define GEN4_WM_STATE_LineEndCapAntialiasingRegionWidth_start 176 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_LineEndCapAntialiasingRegionWidth_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 176; + case 4: + if (devinfo->is_g4x) { + return 176; + } else { + return 176; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Line Stipple Enable */ + + +#define GEN5_WM_STATE_LineStippleEnable_bits 1 +#define GEN45_WM_STATE_LineStippleEnable_bits 1 +#define GEN4_WM_STATE_LineStippleEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_LineStippleEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_LineStippleEnable_start 171 +#define GEN45_WM_STATE_LineStippleEnable_start 171 +#define GEN4_WM_STATE_LineStippleEnable_start 171 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_LineStippleEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 171; + case 4: + if (devinfo->is_g4x) { + return 171; + } else { + return 171; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Mask Stack Exception Enable */ + + +#define GEN5_WM_STATE_MaskStackExceptionEnable_bits 1 +#define GEN45_WM_STATE_MaskStackExceptionEnable_bits 1 +#define GEN4_WM_STATE_MaskStackExceptionEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_MaskStackExceptionEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_MaskStackExceptionEnable_start 34 +#define GEN45_WM_STATE_MaskStackExceptionEnable_start 34 +#define GEN4_WM_STATE_MaskStackExceptionEnable_start 34 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_MaskStackExceptionEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 34; + case 4: + if (devinfo->is_g4x) { + return 34; + } else { + return 34; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Maximum Number of Threads */ + + +#define GEN5_WM_STATE_MaximumNumberofThreads_bits 7 +#define GEN45_WM_STATE_MaximumNumberofThreads_bits 7 +#define GEN4_WM_STATE_MaximumNumberofThreads_bits 7 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_MaximumNumberofThreads_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 7; + case 4: + if (devinfo->is_g4x) { + return 7; + } else { + return 7; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_MaximumNumberofThreads_start 185 +#define GEN45_WM_STATE_MaximumNumberofThreads_start 185 +#define GEN4_WM_STATE_MaximumNumberofThreads_start 185 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_MaximumNumberofThreads_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 185; + case 4: + if (devinfo->is_g4x) { + return 185; + } else { + return 185; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Per-Thread Scratch Space */ + + +#define GEN5_WM_STATE_PerThreadScratchSpace_bits 4 +#define GEN45_WM_STATE_PerThreadScratchSpace_bits 4 +#define GEN4_WM_STATE_PerThreadScratchSpace_bits 4 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_PerThreadScratchSpace_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 4; + case 4: + if (devinfo->is_g4x) { + return 4; + } else { + return 4; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_PerThreadScratchSpace_start 64 +#define GEN45_WM_STATE_PerThreadScratchSpace_start 64 +#define GEN4_WM_STATE_PerThreadScratchSpace_start 64 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_PerThreadScratchSpace_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 64; + case 4: + if (devinfo->is_g4x) { + return 64; + } else { + return 64; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Pixel Shader Computed Depth */ + + +#define GEN5_WM_STATE_PixelShaderComputedDepth_bits 1 +#define GEN45_WM_STATE_PixelShaderComputedDepth_bits 1 +#define GEN4_WM_STATE_PixelShaderComputedDepth_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_PixelShaderComputedDepth_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_PixelShaderComputedDepth_start 181 +#define GEN45_WM_STATE_PixelShaderComputedDepth_start 181 +#define GEN4_WM_STATE_PixelShaderComputedDepth_start 181 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_PixelShaderComputedDepth_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 181; + case 4: + if (devinfo->is_g4x) { + return 181; + } else { + return 181; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Pixel Shader Kills Pixel */ + + +#define GEN5_WM_STATE_PixelShaderKillsPixel_bits 1 +#define GEN45_WM_STATE_PixelShaderKillsPixel_bits 1 +#define GEN4_WM_STATE_PixelShaderKillsPixel_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_PixelShaderKillsPixel_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_PixelShaderKillsPixel_start 182 +#define GEN45_WM_STATE_PixelShaderKillsPixel_start 182 +#define GEN4_WM_STATE_PixelShaderKillsPixel_start 182 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_PixelShaderKillsPixel_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 182; + case 4: + if (devinfo->is_g4x) { + return 182; + } else { + return 182; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Pixel Shader Uses Source Depth */ + + +#define GEN5_WM_STATE_PixelShaderUsesSourceDepth_bits 1 +#define GEN45_WM_STATE_PixelShaderUsesSourceDepth_bits 1 +#define GEN4_WM_STATE_PixelShaderUsesSourceDepth_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_PixelShaderUsesSourceDepth_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_PixelShaderUsesSourceDepth_start 180 +#define GEN45_WM_STATE_PixelShaderUsesSourceDepth_start 180 +#define GEN4_WM_STATE_PixelShaderUsesSourceDepth_start 180 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_PixelShaderUsesSourceDepth_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 180; + case 4: + if (devinfo->is_g4x) { + return 180; + } else { + return 180; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Polygon Stipple Enable */ + + +#define GEN5_WM_STATE_PolygonStippleEnable_bits 1 +#define GEN45_WM_STATE_PolygonStippleEnable_bits 1 +#define GEN4_WM_STATE_PolygonStippleEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_PolygonStippleEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_PolygonStippleEnable_start 173 +#define GEN45_WM_STATE_PolygonStippleEnable_start 173 +#define GEN4_WM_STATE_PolygonStippleEnable_start 173 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_PolygonStippleEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 173; + case 4: + if (devinfo->is_g4x) { + return 173; + } else { + return 173; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Sampler Count */ + + +#define GEN5_WM_STATE_SamplerCount_bits 3 +#define GEN45_WM_STATE_SamplerCount_bits 3 +#define GEN4_WM_STATE_SamplerCount_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_SamplerCount_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_SamplerCount_start 130 +#define GEN45_WM_STATE_SamplerCount_start 130 +#define GEN4_WM_STATE_SamplerCount_start 130 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_SamplerCount_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 130; + case 4: + if (devinfo->is_g4x) { + return 130; + } else { + return 130; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Sampler State Pointer */ + + +#define GEN5_WM_STATE_SamplerStatePointer_bits 27 +#define GEN45_WM_STATE_SamplerStatePointer_bits 27 +#define GEN4_WM_STATE_SamplerStatePointer_bits 27 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_SamplerStatePointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 27; + case 4: + if (devinfo->is_g4x) { + return 27; + } else { + return 27; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_SamplerStatePointer_start 133 +#define GEN45_WM_STATE_SamplerStatePointer_start 133 +#define GEN4_WM_STATE_SamplerStatePointer_start 133 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_SamplerStatePointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 133; + case 4: + if (devinfo->is_g4x) { + return 133; + } else { + return 133; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Scratch Space Base Pointer */ + + +#define GEN5_WM_STATE_ScratchSpaceBasePointer_bits 22 +#define GEN45_WM_STATE_ScratchSpaceBasePointer_bits 22 +#define GEN4_WM_STATE_ScratchSpaceBasePointer_bits 22 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_ScratchSpaceBasePointer_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 22; + case 4: + if (devinfo->is_g4x) { + return 22; + } else { + return 22; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_ScratchSpaceBasePointer_start 74 +#define GEN45_WM_STATE_ScratchSpaceBasePointer_start 74 +#define GEN4_WM_STATE_ScratchSpaceBasePointer_start 74 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_ScratchSpaceBasePointer_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 74; + case 4: + if (devinfo->is_g4x) { + return 74; + } else { + return 74; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Setup URB Entry Read Length */ + + +#define GEN5_WM_STATE_SetupURBEntryReadLength_bits 6 +#define GEN45_WM_STATE_SetupURBEntryReadLength_bits 6 +#define GEN4_WM_STATE_SetupURBEntryReadLength_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_SetupURBEntryReadLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_SetupURBEntryReadLength_start 107 +#define GEN45_WM_STATE_SetupURBEntryReadLength_start 107 +#define GEN4_WM_STATE_SetupURBEntryReadLength_start 107 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_SetupURBEntryReadLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 107; + case 4: + if (devinfo->is_g4x) { + return 107; + } else { + return 107; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Setup URB Entry Read Offset */ + + +#define GEN5_WM_STATE_SetupURBEntryReadOffset_bits 6 +#define GEN45_WM_STATE_SetupURBEntryReadOffset_bits 6 +#define GEN4_WM_STATE_SetupURBEntryReadOffset_bits 6 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_SetupURBEntryReadOffset_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_SetupURBEntryReadOffset_start 100 +#define GEN45_WM_STATE_SetupURBEntryReadOffset_start 100 +#define GEN4_WM_STATE_SetupURBEntryReadOffset_start 100 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_SetupURBEntryReadOffset_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 100; + case 4: + if (devinfo->is_g4x) { + return 100; + } else { + return 100; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Single Program Flow */ + + +#define GEN5_WM_STATE_SingleProgramFlow_bits 1 +#define GEN45_WM_STATE_SingleProgramFlow_bits 1 +#define GEN4_WM_STATE_SingleProgramFlow_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_SingleProgramFlow_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_SingleProgramFlow_start 63 +#define GEN45_WM_STATE_SingleProgramFlow_start 63 +#define GEN4_WM_STATE_SingleProgramFlow_start 63 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_SingleProgramFlow_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 63; + case 4: + if (devinfo->is_g4x) { + return 63; + } else { + return 63; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Software Exception Enable */ + + +#define GEN5_WM_STATE_SoftwareExceptionEnable_bits 1 +#define GEN45_WM_STATE_SoftwareExceptionEnable_bits 1 +#define GEN4_WM_STATE_SoftwareExceptionEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_SoftwareExceptionEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_SoftwareExceptionEnable_start 33 +#define GEN45_WM_STATE_SoftwareExceptionEnable_start 33 +#define GEN4_WM_STATE_SoftwareExceptionEnable_start 33 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_SoftwareExceptionEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 33; + case 4: + if (devinfo->is_g4x) { + return 33; + } else { + return 33; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Statistics Enable */ + + +#define GEN5_WM_STATE_StatisticsEnable_bits 1 +#define GEN45_WM_STATE_StatisticsEnable_bits 1 +#define GEN4_WM_STATE_StatisticsEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_StatisticsEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_StatisticsEnable_start 128 +#define GEN45_WM_STATE_StatisticsEnable_start 128 +#define GEN4_WM_STATE_StatisticsEnable_start 128 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_StatisticsEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 128; + case 4: + if (devinfo->is_g4x) { + return 128; + } else { + return 128; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Thread Dispatch Enable */ + + +#define GEN5_WM_STATE_ThreadDispatchEnable_bits 1 +#define GEN45_WM_STATE_ThreadDispatchEnable_bits 1 +#define GEN4_WM_STATE_ThreadDispatchEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_ThreadDispatchEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_ThreadDispatchEnable_start 179 +#define GEN45_WM_STATE_ThreadDispatchEnable_start 179 +#define GEN4_WM_STATE_ThreadDispatchEnable_start 179 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_ThreadDispatchEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 179; + case 4: + if (devinfo->is_g4x) { + return 179; + } else { + return 179; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* WM_STATE::Thread Priority */ + + +#define GEN5_WM_STATE_ThreadPriority_bits 1 +#define GEN45_WM_STATE_ThreadPriority_bits 1 +#define GEN4_WM_STATE_ThreadPriority_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_ThreadPriority_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_WM_STATE_ThreadPriority_start 49 +#define GEN45_WM_STATE_ThreadPriority_start 49 +#define GEN4_WM_STATE_ThreadPriority_start 49 + +static inline uint32_t ATTRIBUTE_PURE +WM_STATE_ThreadPriority_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 49; + case 4: + if (devinfo->is_g4x) { + return 49; + } else { + return 49; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_COLOR_BLT */ + + +#define GEN5_XY_COLOR_BLT_length 6 +#define GEN45_XY_COLOR_BLT_length 6 +#define GEN4_XY_COLOR_BLT_length 6 + +static inline uint32_t ATTRIBUTE_PURE +XY_COLOR_BLT_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 6; + case 4: + if (devinfo->is_g4x) { + return 6; + } else { + return 6; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_COLOR_BLT::2D Command Opcode */ + + +#define GEN5_XY_COLOR_BLT_2DCommandOpcode_bits 7 +#define GEN45_XY_COLOR_BLT_2DCommandOpcode_bits 7 +#define GEN4_XY_COLOR_BLT_2DCommandOpcode_bits 7 + +static inline uint32_t ATTRIBUTE_PURE +XY_COLOR_BLT_2DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 7; + case 4: + if (devinfo->is_g4x) { + return 7; + } else { + return 7; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_COLOR_BLT_2DCommandOpcode_start 22 +#define GEN45_XY_COLOR_BLT_2DCommandOpcode_start 22 +#define GEN4_XY_COLOR_BLT_2DCommandOpcode_start 22 + +static inline uint32_t ATTRIBUTE_PURE +XY_COLOR_BLT_2DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 22; + case 4: + if (devinfo->is_g4x) { + return 22; + } else { + return 22; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_COLOR_BLT::32bpp Byte Mask */ + + +#define GEN5_XY_COLOR_BLT_32bppByteMask_bits 2 +#define GEN45_XY_COLOR_BLT_32bppByteMask_bits 2 +#define GEN4_XY_COLOR_BLT_32bppByteMask_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +XY_COLOR_BLT_32bppByteMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_COLOR_BLT_32bppByteMask_start 20 +#define GEN45_XY_COLOR_BLT_32bppByteMask_start 20 +#define GEN4_XY_COLOR_BLT_32bppByteMask_start 20 + +static inline uint32_t ATTRIBUTE_PURE +XY_COLOR_BLT_32bppByteMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 20; + case 4: + if (devinfo->is_g4x) { + return 20; + } else { + return 20; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_COLOR_BLT::Clipping Enabled */ + + +#define GEN5_XY_COLOR_BLT_ClippingEnabled_bits 1 +#define GEN45_XY_COLOR_BLT_ClippingEnabled_bits 1 +#define GEN4_XY_COLOR_BLT_ClippingEnabled_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +XY_COLOR_BLT_ClippingEnabled_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_COLOR_BLT_ClippingEnabled_start 62 +#define GEN45_XY_COLOR_BLT_ClippingEnabled_start 62 +#define GEN4_XY_COLOR_BLT_ClippingEnabled_start 62 + +static inline uint32_t ATTRIBUTE_PURE +XY_COLOR_BLT_ClippingEnabled_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 62; + case 4: + if (devinfo->is_g4x) { + return 62; + } else { + return 62; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_COLOR_BLT::Color Depth */ + + +#define GEN5_XY_COLOR_BLT_ColorDepth_bits 3 +#define GEN45_XY_COLOR_BLT_ColorDepth_bits 2 +#define GEN4_XY_COLOR_BLT_ColorDepth_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +XY_COLOR_BLT_ColorDepth_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_COLOR_BLT_ColorDepth_start 56 +#define GEN45_XY_COLOR_BLT_ColorDepth_start 56 +#define GEN4_XY_COLOR_BLT_ColorDepth_start 56 + +static inline uint32_t ATTRIBUTE_PURE +XY_COLOR_BLT_ColorDepth_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 56; + case 4: + if (devinfo->is_g4x) { + return 56; + } else { + return 56; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_COLOR_BLT::Command Type */ + + +#define GEN5_XY_COLOR_BLT_CommandType_bits 3 +#define GEN45_XY_COLOR_BLT_CommandType_bits 3 +#define GEN4_XY_COLOR_BLT_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +XY_COLOR_BLT_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_COLOR_BLT_CommandType_start 29 +#define GEN45_XY_COLOR_BLT_CommandType_start 29 +#define GEN4_XY_COLOR_BLT_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +XY_COLOR_BLT_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 29; + case 4: + if (devinfo->is_g4x) { + return 29; + } else { + return 29; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_COLOR_BLT::DWord Length */ + + +#define GEN5_XY_COLOR_BLT_DWordLength_bits 8 +#define GEN45_XY_COLOR_BLT_DWordLength_bits 8 +#define GEN4_XY_COLOR_BLT_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +XY_COLOR_BLT_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_COLOR_BLT_DWordLength_start 0 +#define GEN45_XY_COLOR_BLT_DWordLength_start 0 +#define GEN4_XY_COLOR_BLT_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +XY_COLOR_BLT_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_COLOR_BLT::Destination Base Address */ + + +#define GEN5_XY_COLOR_BLT_DestinationBaseAddress_bits 32 +#define GEN45_XY_COLOR_BLT_DestinationBaseAddress_bits 32 +#define GEN4_XY_COLOR_BLT_DestinationBaseAddress_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +XY_COLOR_BLT_DestinationBaseAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_COLOR_BLT_DestinationBaseAddress_start 128 +#define GEN45_XY_COLOR_BLT_DestinationBaseAddress_start 128 +#define GEN4_XY_COLOR_BLT_DestinationBaseAddress_start 128 + +static inline uint32_t ATTRIBUTE_PURE +XY_COLOR_BLT_DestinationBaseAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 128; + case 4: + if (devinfo->is_g4x) { + return 128; + } else { + return 128; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_COLOR_BLT::Destination Pitch */ + + +#define GEN5_XY_COLOR_BLT_DestinationPitch_bits 16 +#define GEN45_XY_COLOR_BLT_DestinationPitch_bits 16 +#define GEN4_XY_COLOR_BLT_DestinationPitch_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +XY_COLOR_BLT_DestinationPitch_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_COLOR_BLT_DestinationPitch_start 32 +#define GEN45_XY_COLOR_BLT_DestinationPitch_start 32 +#define GEN4_XY_COLOR_BLT_DestinationPitch_start 32 + +static inline uint32_t ATTRIBUTE_PURE +XY_COLOR_BLT_DestinationPitch_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_COLOR_BLT::Destination X1 Coordinate */ + + +#define GEN5_XY_COLOR_BLT_DestinationX1Coordinate_bits 16 +#define GEN45_XY_COLOR_BLT_DestinationX1Coordinate_bits 16 +#define GEN4_XY_COLOR_BLT_DestinationX1Coordinate_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +XY_COLOR_BLT_DestinationX1Coordinate_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_COLOR_BLT_DestinationX1Coordinate_start 64 +#define GEN45_XY_COLOR_BLT_DestinationX1Coordinate_start 64 +#define GEN4_XY_COLOR_BLT_DestinationX1Coordinate_start 64 + +static inline uint32_t ATTRIBUTE_PURE +XY_COLOR_BLT_DestinationX1Coordinate_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 64; + case 4: + if (devinfo->is_g4x) { + return 64; + } else { + return 64; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_COLOR_BLT::Destination X2 Coordinate */ + + +#define GEN5_XY_COLOR_BLT_DestinationX2Coordinate_bits 16 +#define GEN45_XY_COLOR_BLT_DestinationX2Coordinate_bits 16 +#define GEN4_XY_COLOR_BLT_DestinationX2Coordinate_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +XY_COLOR_BLT_DestinationX2Coordinate_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_COLOR_BLT_DestinationX2Coordinate_start 96 +#define GEN45_XY_COLOR_BLT_DestinationX2Coordinate_start 96 +#define GEN4_XY_COLOR_BLT_DestinationX2Coordinate_start 96 + +static inline uint32_t ATTRIBUTE_PURE +XY_COLOR_BLT_DestinationX2Coordinate_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 96; + case 4: + if (devinfo->is_g4x) { + return 96; + } else { + return 96; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_COLOR_BLT::Destination Y1 Coordinate */ + + +#define GEN5_XY_COLOR_BLT_DestinationY1Coordinate_bits 16 +#define GEN45_XY_COLOR_BLT_DestinationY1Coordinate_bits 16 +#define GEN4_XY_COLOR_BLT_DestinationY1Coordinate_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +XY_COLOR_BLT_DestinationY1Coordinate_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_COLOR_BLT_DestinationY1Coordinate_start 80 +#define GEN45_XY_COLOR_BLT_DestinationY1Coordinate_start 80 +#define GEN4_XY_COLOR_BLT_DestinationY1Coordinate_start 80 + +static inline uint32_t ATTRIBUTE_PURE +XY_COLOR_BLT_DestinationY1Coordinate_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 80; + case 4: + if (devinfo->is_g4x) { + return 80; + } else { + return 80; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_COLOR_BLT::Destination Y2 Coordinate */ + + +#define GEN5_XY_COLOR_BLT_DestinationY2Coordinate_bits 16 +#define GEN45_XY_COLOR_BLT_DestinationY2Coordinate_bits 16 +#define GEN4_XY_COLOR_BLT_DestinationY2Coordinate_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +XY_COLOR_BLT_DestinationY2Coordinate_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_COLOR_BLT_DestinationY2Coordinate_start 112 +#define GEN45_XY_COLOR_BLT_DestinationY2Coordinate_start 112 +#define GEN4_XY_COLOR_BLT_DestinationY2Coordinate_start 112 + +static inline uint32_t ATTRIBUTE_PURE +XY_COLOR_BLT_DestinationY2Coordinate_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 112; + case 4: + if (devinfo->is_g4x) { + return 112; + } else { + return 112; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_COLOR_BLT::Raster Operation */ + + +#define GEN5_XY_COLOR_BLT_RasterOperation_bits 8 +#define GEN45_XY_COLOR_BLT_RasterOperation_bits 8 +#define GEN4_XY_COLOR_BLT_RasterOperation_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +XY_COLOR_BLT_RasterOperation_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_COLOR_BLT_RasterOperation_start 48 +#define GEN45_XY_COLOR_BLT_RasterOperation_start 48 +#define GEN4_XY_COLOR_BLT_RasterOperation_start 48 + +static inline uint32_t ATTRIBUTE_PURE +XY_COLOR_BLT_RasterOperation_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 48; + case 4: + if (devinfo->is_g4x) { + return 48; + } else { + return 48; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_COLOR_BLT::Solid Pattern Color */ + + +#define GEN5_XY_COLOR_BLT_SolidPatternColor_bits 32 +#define GEN45_XY_COLOR_BLT_SolidPatternColor_bits 32 +#define GEN4_XY_COLOR_BLT_SolidPatternColor_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +XY_COLOR_BLT_SolidPatternColor_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_COLOR_BLT_SolidPatternColor_start 160 +#define GEN45_XY_COLOR_BLT_SolidPatternColor_start 160 +#define GEN4_XY_COLOR_BLT_SolidPatternColor_start 160 + +static inline uint32_t ATTRIBUTE_PURE +XY_COLOR_BLT_SolidPatternColor_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 160; + case 4: + if (devinfo->is_g4x) { + return 160; + } else { + return 160; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_COLOR_BLT::Tiling Enable */ + + +#define GEN5_XY_COLOR_BLT_TilingEnable_bits 1 +#define GEN45_XY_COLOR_BLT_TilingEnable_bits 1 +#define GEN4_XY_COLOR_BLT_TilingEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +XY_COLOR_BLT_TilingEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_COLOR_BLT_TilingEnable_start 11 +#define GEN45_XY_COLOR_BLT_TilingEnable_start 11 +#define GEN4_XY_COLOR_BLT_TilingEnable_start 11 + +static inline uint32_t ATTRIBUTE_PURE +XY_COLOR_BLT_TilingEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 11; + case 4: + if (devinfo->is_g4x) { + return 11; + } else { + return 11; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SETUP_BLT */ + + +#define GEN5_XY_SETUP_BLT_length 8 +#define GEN45_XY_SETUP_BLT_length 8 +#define GEN4_XY_SETUP_BLT_length 8 + +static inline uint32_t ATTRIBUTE_PURE +XY_SETUP_BLT_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SETUP_BLT::2D Command Opcode */ + + +#define GEN5_XY_SETUP_BLT_2DCommandOpcode_bits 7 +#define GEN45_XY_SETUP_BLT_2DCommandOpcode_bits 7 +#define GEN4_XY_SETUP_BLT_2DCommandOpcode_bits 7 + +static inline uint32_t ATTRIBUTE_PURE +XY_SETUP_BLT_2DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 7; + case 4: + if (devinfo->is_g4x) { + return 7; + } else { + return 7; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_SETUP_BLT_2DCommandOpcode_start 22 +#define GEN45_XY_SETUP_BLT_2DCommandOpcode_start 22 +#define GEN4_XY_SETUP_BLT_2DCommandOpcode_start 22 + +static inline uint32_t ATTRIBUTE_PURE +XY_SETUP_BLT_2DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 22; + case 4: + if (devinfo->is_g4x) { + return 22; + } else { + return 22; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SETUP_BLT::32bpp Byte Mask */ + + +#define GEN5_XY_SETUP_BLT_32bppByteMask_bits 2 +#define GEN45_XY_SETUP_BLT_32bppByteMask_bits 2 +#define GEN4_XY_SETUP_BLT_32bppByteMask_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +XY_SETUP_BLT_32bppByteMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_SETUP_BLT_32bppByteMask_start 20 +#define GEN45_XY_SETUP_BLT_32bppByteMask_start 20 +#define GEN4_XY_SETUP_BLT_32bppByteMask_start 20 + +static inline uint32_t ATTRIBUTE_PURE +XY_SETUP_BLT_32bppByteMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 20; + case 4: + if (devinfo->is_g4x) { + return 20; + } else { + return 20; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SETUP_BLT::Background Color */ + + +#define GEN5_XY_SETUP_BLT_BackgroundColor_bits 32 +#define GEN45_XY_SETUP_BLT_BackgroundColor_bits 32 +#define GEN4_XY_SETUP_BLT_BackgroundColor_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +XY_SETUP_BLT_BackgroundColor_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_SETUP_BLT_BackgroundColor_start 160 +#define GEN45_XY_SETUP_BLT_BackgroundColor_start 160 +#define GEN4_XY_SETUP_BLT_BackgroundColor_start 160 + +static inline uint32_t ATTRIBUTE_PURE +XY_SETUP_BLT_BackgroundColor_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 160; + case 4: + if (devinfo->is_g4x) { + return 160; + } else { + return 160; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SETUP_BLT::ClipRect X1 Coordinate */ + + +#define GEN5_XY_SETUP_BLT_ClipRectX1Coordinate_bits 16 +#define GEN45_XY_SETUP_BLT_ClipRectX1Coordinate_bits 16 +#define GEN4_XY_SETUP_BLT_ClipRectX1Coordinate_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +XY_SETUP_BLT_ClipRectX1Coordinate_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_SETUP_BLT_ClipRectX1Coordinate_start 64 +#define GEN45_XY_SETUP_BLT_ClipRectX1Coordinate_start 64 +#define GEN4_XY_SETUP_BLT_ClipRectX1Coordinate_start 64 + +static inline uint32_t ATTRIBUTE_PURE +XY_SETUP_BLT_ClipRectX1Coordinate_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 64; + case 4: + if (devinfo->is_g4x) { + return 64; + } else { + return 64; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SETUP_BLT::ClipRect X2 Coordinate */ + + +#define GEN5_XY_SETUP_BLT_ClipRectX2Coordinate_bits 16 +#define GEN45_XY_SETUP_BLT_ClipRectX2Coordinate_bits 16 +#define GEN4_XY_SETUP_BLT_ClipRectX2Coordinate_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +XY_SETUP_BLT_ClipRectX2Coordinate_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_SETUP_BLT_ClipRectX2Coordinate_start 96 +#define GEN45_XY_SETUP_BLT_ClipRectX2Coordinate_start 96 +#define GEN4_XY_SETUP_BLT_ClipRectX2Coordinate_start 96 + +static inline uint32_t ATTRIBUTE_PURE +XY_SETUP_BLT_ClipRectX2Coordinate_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 96; + case 4: + if (devinfo->is_g4x) { + return 96; + } else { + return 96; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SETUP_BLT::ClipRect Y1 Coordinate */ + + +#define GEN5_XY_SETUP_BLT_ClipRectY1Coordinate_bits 16 +#define GEN45_XY_SETUP_BLT_ClipRectY1Coordinate_bits 16 +#define GEN4_XY_SETUP_BLT_ClipRectY1Coordinate_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +XY_SETUP_BLT_ClipRectY1Coordinate_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_SETUP_BLT_ClipRectY1Coordinate_start 80 +#define GEN45_XY_SETUP_BLT_ClipRectY1Coordinate_start 80 +#define GEN4_XY_SETUP_BLT_ClipRectY1Coordinate_start 80 + +static inline uint32_t ATTRIBUTE_PURE +XY_SETUP_BLT_ClipRectY1Coordinate_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 80; + case 4: + if (devinfo->is_g4x) { + return 80; + } else { + return 80; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SETUP_BLT::ClipRect Y2 Coordinate */ + + +#define GEN5_XY_SETUP_BLT_ClipRectY2Coordinate_bits 16 +#define GEN45_XY_SETUP_BLT_ClipRectY2Coordinate_bits 16 +#define GEN4_XY_SETUP_BLT_ClipRectY2Coordinate_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +XY_SETUP_BLT_ClipRectY2Coordinate_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_SETUP_BLT_ClipRectY2Coordinate_start 112 +#define GEN45_XY_SETUP_BLT_ClipRectY2Coordinate_start 112 +#define GEN4_XY_SETUP_BLT_ClipRectY2Coordinate_start 112 + +static inline uint32_t ATTRIBUTE_PURE +XY_SETUP_BLT_ClipRectY2Coordinate_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 112; + case 4: + if (devinfo->is_g4x) { + return 112; + } else { + return 112; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SETUP_BLT::Clipping Enabled */ + + +#define GEN5_XY_SETUP_BLT_ClippingEnabled_bits 1 +#define GEN45_XY_SETUP_BLT_ClippingEnabled_bits 1 +#define GEN4_XY_SETUP_BLT_ClippingEnabled_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +XY_SETUP_BLT_ClippingEnabled_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_SETUP_BLT_ClippingEnabled_start 62 +#define GEN45_XY_SETUP_BLT_ClippingEnabled_start 62 +#define GEN4_XY_SETUP_BLT_ClippingEnabled_start 62 + +static inline uint32_t ATTRIBUTE_PURE +XY_SETUP_BLT_ClippingEnabled_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 62; + case 4: + if (devinfo->is_g4x) { + return 62; + } else { + return 62; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SETUP_BLT::Color Depth */ + + +#define GEN5_XY_SETUP_BLT_ColorDepth_bits 2 +#define GEN45_XY_SETUP_BLT_ColorDepth_bits 2 +#define GEN4_XY_SETUP_BLT_ColorDepth_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +XY_SETUP_BLT_ColorDepth_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_SETUP_BLT_ColorDepth_start 56 +#define GEN45_XY_SETUP_BLT_ColorDepth_start 56 +#define GEN4_XY_SETUP_BLT_ColorDepth_start 56 + +static inline uint32_t ATTRIBUTE_PURE +XY_SETUP_BLT_ColorDepth_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 56; + case 4: + if (devinfo->is_g4x) { + return 56; + } else { + return 56; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SETUP_BLT::Command Type */ + + +#define GEN5_XY_SETUP_BLT_CommandType_bits 3 +#define GEN45_XY_SETUP_BLT_CommandType_bits 3 +#define GEN4_XY_SETUP_BLT_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +XY_SETUP_BLT_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_SETUP_BLT_CommandType_start 29 +#define GEN45_XY_SETUP_BLT_CommandType_start 29 +#define GEN4_XY_SETUP_BLT_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +XY_SETUP_BLT_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 29; + case 4: + if (devinfo->is_g4x) { + return 29; + } else { + return 29; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SETUP_BLT::DWord Length */ + + +#define GEN5_XY_SETUP_BLT_DWordLength_bits 8 +#define GEN45_XY_SETUP_BLT_DWordLength_bits 8 +#define GEN4_XY_SETUP_BLT_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +XY_SETUP_BLT_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_SETUP_BLT_DWordLength_start 0 +#define GEN45_XY_SETUP_BLT_DWordLength_start 0 +#define GEN4_XY_SETUP_BLT_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +XY_SETUP_BLT_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SETUP_BLT::Destination Base Address */ + + +#define GEN5_XY_SETUP_BLT_DestinationBaseAddress_bits 32 +#define GEN45_XY_SETUP_BLT_DestinationBaseAddress_bits 32 +#define GEN4_XY_SETUP_BLT_DestinationBaseAddress_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +XY_SETUP_BLT_DestinationBaseAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_SETUP_BLT_DestinationBaseAddress_start 128 +#define GEN45_XY_SETUP_BLT_DestinationBaseAddress_start 128 +#define GEN4_XY_SETUP_BLT_DestinationBaseAddress_start 128 + +static inline uint32_t ATTRIBUTE_PURE +XY_SETUP_BLT_DestinationBaseAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 128; + case 4: + if (devinfo->is_g4x) { + return 128; + } else { + return 128; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SETUP_BLT::Destination Pitch */ + + +#define GEN5_XY_SETUP_BLT_DestinationPitch_bits 16 +#define GEN45_XY_SETUP_BLT_DestinationPitch_bits 16 +#define GEN4_XY_SETUP_BLT_DestinationPitch_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +XY_SETUP_BLT_DestinationPitch_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_SETUP_BLT_DestinationPitch_start 32 +#define GEN45_XY_SETUP_BLT_DestinationPitch_start 32 +#define GEN4_XY_SETUP_BLT_DestinationPitch_start 32 + +static inline uint32_t ATTRIBUTE_PURE +XY_SETUP_BLT_DestinationPitch_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SETUP_BLT::Foreground Color */ + + +#define GEN5_XY_SETUP_BLT_ForegroundColor_bits 32 +#define GEN45_XY_SETUP_BLT_ForegroundColor_bits 32 +#define GEN4_XY_SETUP_BLT_ForegroundColor_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +XY_SETUP_BLT_ForegroundColor_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_SETUP_BLT_ForegroundColor_start 192 +#define GEN45_XY_SETUP_BLT_ForegroundColor_start 192 +#define GEN4_XY_SETUP_BLT_ForegroundColor_start 192 + +static inline uint32_t ATTRIBUTE_PURE +XY_SETUP_BLT_ForegroundColor_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 192; + case 4: + if (devinfo->is_g4x) { + return 192; + } else { + return 192; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SETUP_BLT::Mono Source Transparency Mode */ + + +#define GEN5_XY_SETUP_BLT_MonoSourceTransparencyMode_bits 1 +#define GEN45_XY_SETUP_BLT_MonoSourceTransparencyMode_bits 1 +#define GEN4_XY_SETUP_BLT_MonoSourceTransparencyMode_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +XY_SETUP_BLT_MonoSourceTransparencyMode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_SETUP_BLT_MonoSourceTransparencyMode_start 60 +#define GEN45_XY_SETUP_BLT_MonoSourceTransparencyMode_start 61 +#define GEN4_XY_SETUP_BLT_MonoSourceTransparencyMode_start 61 + +static inline uint32_t ATTRIBUTE_PURE +XY_SETUP_BLT_MonoSourceTransparencyMode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 60; + case 4: + if (devinfo->is_g4x) { + return 61; + } else { + return 61; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SETUP_BLT::Pattern Base Address */ + + +#define GEN5_XY_SETUP_BLT_PatternBaseAddress_bits 32 +#define GEN45_XY_SETUP_BLT_PatternBaseAddress_bits 32 +#define GEN4_XY_SETUP_BLT_PatternBaseAddress_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +XY_SETUP_BLT_PatternBaseAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_SETUP_BLT_PatternBaseAddress_start 224 +#define GEN45_XY_SETUP_BLT_PatternBaseAddress_start 224 +#define GEN4_XY_SETUP_BLT_PatternBaseAddress_start 224 + +static inline uint32_t ATTRIBUTE_PURE +XY_SETUP_BLT_PatternBaseAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 224; + case 4: + if (devinfo->is_g4x) { + return 224; + } else { + return 224; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SETUP_BLT::Raster Operation */ + + +#define GEN5_XY_SETUP_BLT_RasterOperation_bits 8 +#define GEN45_XY_SETUP_BLT_RasterOperation_bits 8 +#define GEN4_XY_SETUP_BLT_RasterOperation_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +XY_SETUP_BLT_RasterOperation_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_SETUP_BLT_RasterOperation_start 48 +#define GEN45_XY_SETUP_BLT_RasterOperation_start 48 +#define GEN4_XY_SETUP_BLT_RasterOperation_start 48 + +static inline uint32_t ATTRIBUTE_PURE +XY_SETUP_BLT_RasterOperation_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 48; + case 4: + if (devinfo->is_g4x) { + return 48; + } else { + return 48; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SETUP_BLT::Tiling Enable */ + + +#define GEN5_XY_SETUP_BLT_TilingEnable_bits 1 +#define GEN45_XY_SETUP_BLT_TilingEnable_bits 1 +#define GEN4_XY_SETUP_BLT_TilingEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +XY_SETUP_BLT_TilingEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_SETUP_BLT_TilingEnable_start 11 +#define GEN45_XY_SETUP_BLT_TilingEnable_start 11 +#define GEN4_XY_SETUP_BLT_TilingEnable_start 11 + +static inline uint32_t ATTRIBUTE_PURE +XY_SETUP_BLT_TilingEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 11; + case 4: + if (devinfo->is_g4x) { + return 11; + } else { + return 11; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SRC_COPY_BLT */ + + +#define GEN5_XY_SRC_COPY_BLT_length 8 +#define GEN45_XY_SRC_COPY_BLT_length 8 +#define GEN4_XY_SRC_COPY_BLT_length 8 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SRC_COPY_BLT::2D Command Opcode */ + + +#define GEN5_XY_SRC_COPY_BLT_2DCommandOpcode_bits 7 +#define GEN45_XY_SRC_COPY_BLT_2DCommandOpcode_bits 7 +#define GEN4_XY_SRC_COPY_BLT_2DCommandOpcode_bits 7 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_2DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 7; + case 4: + if (devinfo->is_g4x) { + return 7; + } else { + return 7; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_SRC_COPY_BLT_2DCommandOpcode_start 22 +#define GEN45_XY_SRC_COPY_BLT_2DCommandOpcode_start 22 +#define GEN4_XY_SRC_COPY_BLT_2DCommandOpcode_start 22 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_2DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 22; + case 4: + if (devinfo->is_g4x) { + return 22; + } else { + return 22; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SRC_COPY_BLT::32bpp Byte Mask */ + + +#define GEN5_XY_SRC_COPY_BLT_32bppByteMask_bits 2 +#define GEN45_XY_SRC_COPY_BLT_32bppByteMask_bits 2 +#define GEN4_XY_SRC_COPY_BLT_32bppByteMask_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_32bppByteMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_SRC_COPY_BLT_32bppByteMask_start 20 +#define GEN45_XY_SRC_COPY_BLT_32bppByteMask_start 20 +#define GEN4_XY_SRC_COPY_BLT_32bppByteMask_start 20 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_32bppByteMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 20; + case 4: + if (devinfo->is_g4x) { + return 20; + } else { + return 20; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SRC_COPY_BLT::Clipping Enabled */ + + +#define GEN5_XY_SRC_COPY_BLT_ClippingEnabled_bits 1 +#define GEN45_XY_SRC_COPY_BLT_ClippingEnabled_bits 1 +#define GEN4_XY_SRC_COPY_BLT_ClippingEnabled_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_ClippingEnabled_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_SRC_COPY_BLT_ClippingEnabled_start 62 +#define GEN45_XY_SRC_COPY_BLT_ClippingEnabled_start 62 +#define GEN4_XY_SRC_COPY_BLT_ClippingEnabled_start 62 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_ClippingEnabled_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 62; + case 4: + if (devinfo->is_g4x) { + return 62; + } else { + return 62; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SRC_COPY_BLT::Color Depth */ + + +#define GEN5_XY_SRC_COPY_BLT_ColorDepth_bits 3 +#define GEN45_XY_SRC_COPY_BLT_ColorDepth_bits 2 +#define GEN4_XY_SRC_COPY_BLT_ColorDepth_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_ColorDepth_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_SRC_COPY_BLT_ColorDepth_start 56 +#define GEN45_XY_SRC_COPY_BLT_ColorDepth_start 56 +#define GEN4_XY_SRC_COPY_BLT_ColorDepth_start 56 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_ColorDepth_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 56; + case 4: + if (devinfo->is_g4x) { + return 56; + } else { + return 56; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SRC_COPY_BLT::Command Type */ + + +#define GEN5_XY_SRC_COPY_BLT_CommandType_bits 3 +#define GEN45_XY_SRC_COPY_BLT_CommandType_bits 3 +#define GEN4_XY_SRC_COPY_BLT_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_SRC_COPY_BLT_CommandType_start 29 +#define GEN45_XY_SRC_COPY_BLT_CommandType_start 29 +#define GEN4_XY_SRC_COPY_BLT_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 29; + case 4: + if (devinfo->is_g4x) { + return 29; + } else { + return 29; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SRC_COPY_BLT::DWord Length */ + + +#define GEN5_XY_SRC_COPY_BLT_DWordLength_bits 8 +#define GEN45_XY_SRC_COPY_BLT_DWordLength_bits 8 +#define GEN4_XY_SRC_COPY_BLT_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_SRC_COPY_BLT_DWordLength_start 0 +#define GEN45_XY_SRC_COPY_BLT_DWordLength_start 0 +#define GEN4_XY_SRC_COPY_BLT_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SRC_COPY_BLT::Destination Base Address */ + + +#define GEN5_XY_SRC_COPY_BLT_DestinationBaseAddress_bits 32 +#define GEN45_XY_SRC_COPY_BLT_DestinationBaseAddress_bits 32 +#define GEN4_XY_SRC_COPY_BLT_DestinationBaseAddress_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_DestinationBaseAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_SRC_COPY_BLT_DestinationBaseAddress_start 128 +#define GEN45_XY_SRC_COPY_BLT_DestinationBaseAddress_start 128 +#define GEN4_XY_SRC_COPY_BLT_DestinationBaseAddress_start 128 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_DestinationBaseAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 128; + case 4: + if (devinfo->is_g4x) { + return 128; + } else { + return 128; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SRC_COPY_BLT::Destination Pitch */ + + +#define GEN5_XY_SRC_COPY_BLT_DestinationPitch_bits 16 +#define GEN45_XY_SRC_COPY_BLT_DestinationPitch_bits 16 +#define GEN4_XY_SRC_COPY_BLT_DestinationPitch_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_DestinationPitch_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_SRC_COPY_BLT_DestinationPitch_start 32 +#define GEN45_XY_SRC_COPY_BLT_DestinationPitch_start 32 +#define GEN4_XY_SRC_COPY_BLT_DestinationPitch_start 32 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_DestinationPitch_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SRC_COPY_BLT::Destination Tiling Enable */ + + +#define GEN5_XY_SRC_COPY_BLT_DestinationTilingEnable_bits 1 +#define GEN45_XY_SRC_COPY_BLT_DestinationTilingEnable_bits 1 +#define GEN4_XY_SRC_COPY_BLT_DestinationTilingEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_DestinationTilingEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_SRC_COPY_BLT_DestinationTilingEnable_start 11 +#define GEN45_XY_SRC_COPY_BLT_DestinationTilingEnable_start 11 +#define GEN4_XY_SRC_COPY_BLT_DestinationTilingEnable_start 11 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_DestinationTilingEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 11; + case 4: + if (devinfo->is_g4x) { + return 11; + } else { + return 11; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SRC_COPY_BLT::Destination X1 Coordinate */ + + +#define GEN5_XY_SRC_COPY_BLT_DestinationX1Coordinate_bits 16 +#define GEN45_XY_SRC_COPY_BLT_DestinationX1Coordinate_bits 16 +#define GEN4_XY_SRC_COPY_BLT_DestinationX1Coordinate_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_DestinationX1Coordinate_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_SRC_COPY_BLT_DestinationX1Coordinate_start 64 +#define GEN45_XY_SRC_COPY_BLT_DestinationX1Coordinate_start 64 +#define GEN4_XY_SRC_COPY_BLT_DestinationX1Coordinate_start 64 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_DestinationX1Coordinate_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 64; + case 4: + if (devinfo->is_g4x) { + return 64; + } else { + return 64; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SRC_COPY_BLT::Destination X2 Coordinate */ + + +#define GEN5_XY_SRC_COPY_BLT_DestinationX2Coordinate_bits 16 +#define GEN45_XY_SRC_COPY_BLT_DestinationX2Coordinate_bits 16 +#define GEN4_XY_SRC_COPY_BLT_DestinationX2Coordinate_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_DestinationX2Coordinate_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_SRC_COPY_BLT_DestinationX2Coordinate_start 96 +#define GEN45_XY_SRC_COPY_BLT_DestinationX2Coordinate_start 96 +#define GEN4_XY_SRC_COPY_BLT_DestinationX2Coordinate_start 96 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_DestinationX2Coordinate_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 96; + case 4: + if (devinfo->is_g4x) { + return 96; + } else { + return 96; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SRC_COPY_BLT::Destination Y1 Coordinate */ + + +#define GEN5_XY_SRC_COPY_BLT_DestinationY1Coordinate_bits 16 +#define GEN45_XY_SRC_COPY_BLT_DestinationY1Coordinate_bits 16 +#define GEN4_XY_SRC_COPY_BLT_DestinationY1Coordinate_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_DestinationY1Coordinate_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_SRC_COPY_BLT_DestinationY1Coordinate_start 80 +#define GEN45_XY_SRC_COPY_BLT_DestinationY1Coordinate_start 80 +#define GEN4_XY_SRC_COPY_BLT_DestinationY1Coordinate_start 80 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_DestinationY1Coordinate_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 80; + case 4: + if (devinfo->is_g4x) { + return 80; + } else { + return 80; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SRC_COPY_BLT::Destination Y2 Coordinate */ + + +#define GEN5_XY_SRC_COPY_BLT_DestinationY2Coordinate_bits 16 +#define GEN45_XY_SRC_COPY_BLT_DestinationY2Coordinate_bits 16 +#define GEN4_XY_SRC_COPY_BLT_DestinationY2Coordinate_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_DestinationY2Coordinate_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_SRC_COPY_BLT_DestinationY2Coordinate_start 112 +#define GEN45_XY_SRC_COPY_BLT_DestinationY2Coordinate_start 112 +#define GEN4_XY_SRC_COPY_BLT_DestinationY2Coordinate_start 112 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_DestinationY2Coordinate_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 112; + case 4: + if (devinfo->is_g4x) { + return 112; + } else { + return 112; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SRC_COPY_BLT::Raster Operation */ + + +#define GEN5_XY_SRC_COPY_BLT_RasterOperation_bits 8 +#define GEN45_XY_SRC_COPY_BLT_RasterOperation_bits 8 +#define GEN4_XY_SRC_COPY_BLT_RasterOperation_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_RasterOperation_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_SRC_COPY_BLT_RasterOperation_start 48 +#define GEN45_XY_SRC_COPY_BLT_RasterOperation_start 48 +#define GEN4_XY_SRC_COPY_BLT_RasterOperation_start 48 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_RasterOperation_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 48; + case 4: + if (devinfo->is_g4x) { + return 48; + } else { + return 48; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SRC_COPY_BLT::Source Base Address */ + + +#define GEN5_XY_SRC_COPY_BLT_SourceBaseAddress_bits 32 +#define GEN45_XY_SRC_COPY_BLT_SourceBaseAddress_bits 32 +#define GEN4_XY_SRC_COPY_BLT_SourceBaseAddress_bits 32 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_SourceBaseAddress_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_SRC_COPY_BLT_SourceBaseAddress_start 224 +#define GEN45_XY_SRC_COPY_BLT_SourceBaseAddress_start 224 +#define GEN4_XY_SRC_COPY_BLT_SourceBaseAddress_start 224 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_SourceBaseAddress_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 224; + case 4: + if (devinfo->is_g4x) { + return 224; + } else { + return 224; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SRC_COPY_BLT::Source Pitch */ + + +#define GEN5_XY_SRC_COPY_BLT_SourcePitch_bits 16 +#define GEN45_XY_SRC_COPY_BLT_SourcePitch_bits 16 +#define GEN4_XY_SRC_COPY_BLT_SourcePitch_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_SourcePitch_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_SRC_COPY_BLT_SourcePitch_start 192 +#define GEN45_XY_SRC_COPY_BLT_SourcePitch_start 192 +#define GEN4_XY_SRC_COPY_BLT_SourcePitch_start 192 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_SourcePitch_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 192; + case 4: + if (devinfo->is_g4x) { + return 192; + } else { + return 192; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SRC_COPY_BLT::Source Tiling Enable */ + + +#define GEN5_XY_SRC_COPY_BLT_SourceTilingEnable_bits 1 +#define GEN45_XY_SRC_COPY_BLT_SourceTilingEnable_bits 1 +#define GEN4_XY_SRC_COPY_BLT_SourceTilingEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_SourceTilingEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_SRC_COPY_BLT_SourceTilingEnable_start 15 +#define GEN45_XY_SRC_COPY_BLT_SourceTilingEnable_start 15 +#define GEN4_XY_SRC_COPY_BLT_SourceTilingEnable_start 15 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_SourceTilingEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 15; + case 4: + if (devinfo->is_g4x) { + return 15; + } else { + return 15; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SRC_COPY_BLT::Source X1 Coordinate */ + + +#define GEN5_XY_SRC_COPY_BLT_SourceX1Coordinate_bits 16 +#define GEN45_XY_SRC_COPY_BLT_SourceX1Coordinate_bits 16 +#define GEN4_XY_SRC_COPY_BLT_SourceX1Coordinate_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_SourceX1Coordinate_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_SRC_COPY_BLT_SourceX1Coordinate_start 160 +#define GEN45_XY_SRC_COPY_BLT_SourceX1Coordinate_start 160 +#define GEN4_XY_SRC_COPY_BLT_SourceX1Coordinate_start 160 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_SourceX1Coordinate_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 160; + case 4: + if (devinfo->is_g4x) { + return 160; + } else { + return 160; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_SRC_COPY_BLT::Source Y1 Coordinate */ + + +#define GEN5_XY_SRC_COPY_BLT_SourceY1Coordinate_bits 16 +#define GEN45_XY_SRC_COPY_BLT_SourceY1Coordinate_bits 16 +#define GEN4_XY_SRC_COPY_BLT_SourceY1Coordinate_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_SourceY1Coordinate_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_SRC_COPY_BLT_SourceY1Coordinate_start 176 +#define GEN45_XY_SRC_COPY_BLT_SourceY1Coordinate_start 176 +#define GEN4_XY_SRC_COPY_BLT_SourceY1Coordinate_start 176 + +static inline uint32_t ATTRIBUTE_PURE +XY_SRC_COPY_BLT_SourceY1Coordinate_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 176; + case 4: + if (devinfo->is_g4x) { + return 176; + } else { + return 176; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_TEXT_IMMEDIATE_BLT */ + + +#define GEN5_XY_TEXT_IMMEDIATE_BLT_length 3 +#define GEN45_XY_TEXT_IMMEDIATE_BLT_length 3 +#define GEN4_XY_TEXT_IMMEDIATE_BLT_length 3 + +static inline uint32_t ATTRIBUTE_PURE +XY_TEXT_IMMEDIATE_BLT_length(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_TEXT_IMMEDIATE_BLT::2D Command Opcode */ + + +#define GEN5_XY_TEXT_IMMEDIATE_BLT_2DCommandOpcode_bits 7 +#define GEN45_XY_TEXT_IMMEDIATE_BLT_2DCommandOpcode_bits 7 +#define GEN4_XY_TEXT_IMMEDIATE_BLT_2DCommandOpcode_bits 7 + +static inline uint32_t ATTRIBUTE_PURE +XY_TEXT_IMMEDIATE_BLT_2DCommandOpcode_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 7; + case 4: + if (devinfo->is_g4x) { + return 7; + } else { + return 7; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_TEXT_IMMEDIATE_BLT_2DCommandOpcode_start 22 +#define GEN45_XY_TEXT_IMMEDIATE_BLT_2DCommandOpcode_start 22 +#define GEN4_XY_TEXT_IMMEDIATE_BLT_2DCommandOpcode_start 22 + +static inline uint32_t ATTRIBUTE_PURE +XY_TEXT_IMMEDIATE_BLT_2DCommandOpcode_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 22; + case 4: + if (devinfo->is_g4x) { + return 22; + } else { + return 22; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_TEXT_IMMEDIATE_BLT::32bpp Byte Mask */ + + +#define GEN5_XY_TEXT_IMMEDIATE_BLT_32bppByteMask_bits 2 +#define GEN45_XY_TEXT_IMMEDIATE_BLT_32bppByteMask_bits 2 +#define GEN4_XY_TEXT_IMMEDIATE_BLT_32bppByteMask_bits 2 + +static inline uint32_t ATTRIBUTE_PURE +XY_TEXT_IMMEDIATE_BLT_32bppByteMask_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 2; + case 4: + if (devinfo->is_g4x) { + return 2; + } else { + return 2; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_TEXT_IMMEDIATE_BLT_32bppByteMask_start 20 +#define GEN45_XY_TEXT_IMMEDIATE_BLT_32bppByteMask_start 20 +#define GEN4_XY_TEXT_IMMEDIATE_BLT_32bppByteMask_start 20 + +static inline uint32_t ATTRIBUTE_PURE +XY_TEXT_IMMEDIATE_BLT_32bppByteMask_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 20; + case 4: + if (devinfo->is_g4x) { + return 20; + } else { + return 20; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_TEXT_IMMEDIATE_BLT::Command Type */ + + +#define GEN5_XY_TEXT_IMMEDIATE_BLT_CommandType_bits 3 +#define GEN45_XY_TEXT_IMMEDIATE_BLT_CommandType_bits 3 +#define GEN4_XY_TEXT_IMMEDIATE_BLT_CommandType_bits 3 + +static inline uint32_t ATTRIBUTE_PURE +XY_TEXT_IMMEDIATE_BLT_CommandType_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 3; + case 4: + if (devinfo->is_g4x) { + return 3; + } else { + return 3; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_TEXT_IMMEDIATE_BLT_CommandType_start 29 +#define GEN45_XY_TEXT_IMMEDIATE_BLT_CommandType_start 29 +#define GEN4_XY_TEXT_IMMEDIATE_BLT_CommandType_start 29 + +static inline uint32_t ATTRIBUTE_PURE +XY_TEXT_IMMEDIATE_BLT_CommandType_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 29; + case 4: + if (devinfo->is_g4x) { + return 29; + } else { + return 29; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_TEXT_IMMEDIATE_BLT::DWord Length */ + + +#define GEN5_XY_TEXT_IMMEDIATE_BLT_DWordLength_bits 8 +#define GEN45_XY_TEXT_IMMEDIATE_BLT_DWordLength_bits 8 +#define GEN4_XY_TEXT_IMMEDIATE_BLT_DWordLength_bits 8 + +static inline uint32_t ATTRIBUTE_PURE +XY_TEXT_IMMEDIATE_BLT_DWordLength_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 8; + case 4: + if (devinfo->is_g4x) { + return 8; + } else { + return 8; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_TEXT_IMMEDIATE_BLT_DWordLength_start 0 +#define GEN45_XY_TEXT_IMMEDIATE_BLT_DWordLength_start 0 +#define GEN4_XY_TEXT_IMMEDIATE_BLT_DWordLength_start 0 + +static inline uint32_t ATTRIBUTE_PURE +XY_TEXT_IMMEDIATE_BLT_DWordLength_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 0; + case 4: + if (devinfo->is_g4x) { + return 0; + } else { + return 0; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_TEXT_IMMEDIATE_BLT::Destination Pitch */ + + +#define GEN5_XY_TEXT_IMMEDIATE_BLT_DestinationPitch_bits 16 +#define GEN45_XY_TEXT_IMMEDIATE_BLT_DestinationPitch_bits 16 +#define GEN4_XY_TEXT_IMMEDIATE_BLT_DestinationPitch_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +XY_TEXT_IMMEDIATE_BLT_DestinationPitch_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_TEXT_IMMEDIATE_BLT_DestinationPitch_start 32 +#define GEN45_XY_TEXT_IMMEDIATE_BLT_DestinationPitch_start 32 +#define GEN4_XY_TEXT_IMMEDIATE_BLT_DestinationPitch_start 32 + +static inline uint32_t ATTRIBUTE_PURE +XY_TEXT_IMMEDIATE_BLT_DestinationPitch_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_TEXT_IMMEDIATE_BLT::Destination X1 Coordinate */ + + +#define GEN5_XY_TEXT_IMMEDIATE_BLT_DestinationX1Coordinate_bits 16 +#define GEN45_XY_TEXT_IMMEDIATE_BLT_DestinationX1Coordinate_bits 16 +#define GEN4_XY_TEXT_IMMEDIATE_BLT_DestinationX1Coordinate_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +XY_TEXT_IMMEDIATE_BLT_DestinationX1Coordinate_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_TEXT_IMMEDIATE_BLT_DestinationX1Coordinate_start 32 +#define GEN45_XY_TEXT_IMMEDIATE_BLT_DestinationX1Coordinate_start 32 +#define GEN4_XY_TEXT_IMMEDIATE_BLT_DestinationX1Coordinate_start 32 + +static inline uint32_t ATTRIBUTE_PURE +XY_TEXT_IMMEDIATE_BLT_DestinationX1Coordinate_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 32; + case 4: + if (devinfo->is_g4x) { + return 32; + } else { + return 32; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_TEXT_IMMEDIATE_BLT::Destination X2 Coordinate */ + + +#define GEN5_XY_TEXT_IMMEDIATE_BLT_DestinationX2Coordinate_bits 16 +#define GEN45_XY_TEXT_IMMEDIATE_BLT_DestinationX2Coordinate_bits 16 +#define GEN4_XY_TEXT_IMMEDIATE_BLT_DestinationX2Coordinate_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +XY_TEXT_IMMEDIATE_BLT_DestinationX2Coordinate_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_TEXT_IMMEDIATE_BLT_DestinationX2Coordinate_start 64 +#define GEN45_XY_TEXT_IMMEDIATE_BLT_DestinationX2Coordinate_start 64 +#define GEN4_XY_TEXT_IMMEDIATE_BLT_DestinationX2Coordinate_start 64 + +static inline uint32_t ATTRIBUTE_PURE +XY_TEXT_IMMEDIATE_BLT_DestinationX2Coordinate_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 64; + case 4: + if (devinfo->is_g4x) { + return 64; + } else { + return 64; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_TEXT_IMMEDIATE_BLT::Destination Y1 Coordinate */ + + +#define GEN5_XY_TEXT_IMMEDIATE_BLT_DestinationY1Coordinate_bits 16 +#define GEN45_XY_TEXT_IMMEDIATE_BLT_DestinationY1Coordinate_bits 16 +#define GEN4_XY_TEXT_IMMEDIATE_BLT_DestinationY1Coordinate_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +XY_TEXT_IMMEDIATE_BLT_DestinationY1Coordinate_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_TEXT_IMMEDIATE_BLT_DestinationY1Coordinate_start 48 +#define GEN45_XY_TEXT_IMMEDIATE_BLT_DestinationY1Coordinate_start 48 +#define GEN4_XY_TEXT_IMMEDIATE_BLT_DestinationY1Coordinate_start 48 + +static inline uint32_t ATTRIBUTE_PURE +XY_TEXT_IMMEDIATE_BLT_DestinationY1Coordinate_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 48; + case 4: + if (devinfo->is_g4x) { + return 48; + } else { + return 48; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_TEXT_IMMEDIATE_BLT::Destination Y2 Coordinate */ + + +#define GEN5_XY_TEXT_IMMEDIATE_BLT_DestinationY2Coordinate_bits 16 +#define GEN45_XY_TEXT_IMMEDIATE_BLT_DestinationY2Coordinate_bits 16 +#define GEN4_XY_TEXT_IMMEDIATE_BLT_DestinationY2Coordinate_bits 16 + +static inline uint32_t ATTRIBUTE_PURE +XY_TEXT_IMMEDIATE_BLT_DestinationY2Coordinate_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_TEXT_IMMEDIATE_BLT_DestinationY2Coordinate_start 80 +#define GEN45_XY_TEXT_IMMEDIATE_BLT_DestinationY2Coordinate_start 80 +#define GEN4_XY_TEXT_IMMEDIATE_BLT_DestinationY2Coordinate_start 80 + +static inline uint32_t ATTRIBUTE_PURE +XY_TEXT_IMMEDIATE_BLT_DestinationY2Coordinate_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 80; + case 4: + if (devinfo->is_g4x) { + return 80; + } else { + return 80; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_TEXT_IMMEDIATE_BLT::Packing */ + + +#define GEN5_XY_TEXT_IMMEDIATE_BLT_Packing_bits 1 +#define GEN45_XY_TEXT_IMMEDIATE_BLT_Packing_bits 1 +#define GEN4_XY_TEXT_IMMEDIATE_BLT_Packing_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +XY_TEXT_IMMEDIATE_BLT_Packing_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_TEXT_IMMEDIATE_BLT_Packing_start 16 +#define GEN45_XY_TEXT_IMMEDIATE_BLT_Packing_start 16 +#define GEN4_XY_TEXT_IMMEDIATE_BLT_Packing_start 16 + +static inline uint32_t ATTRIBUTE_PURE +XY_TEXT_IMMEDIATE_BLT_Packing_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 16; + case 4: + if (devinfo->is_g4x) { + return 16; + } else { + return 16; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +/* XY_TEXT_IMMEDIATE_BLT::Tiling Enable */ + + +#define GEN5_XY_TEXT_IMMEDIATE_BLT_TilingEnable_bits 1 +#define GEN45_XY_TEXT_IMMEDIATE_BLT_TilingEnable_bits 1 +#define GEN4_XY_TEXT_IMMEDIATE_BLT_TilingEnable_bits 1 + +static inline uint32_t ATTRIBUTE_PURE +XY_TEXT_IMMEDIATE_BLT_TilingEnable_bits(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 1; + case 4: + if (devinfo->is_g4x) { + return 1; + } else { + return 1; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#define GEN5_XY_TEXT_IMMEDIATE_BLT_TilingEnable_start 11 +#define GEN45_XY_TEXT_IMMEDIATE_BLT_TilingEnable_start 11 +#define GEN4_XY_TEXT_IMMEDIATE_BLT_TilingEnable_start 11 + +static inline uint32_t ATTRIBUTE_PURE +XY_TEXT_IMMEDIATE_BLT_TilingEnable_start(const struct gen_device_info *devinfo) +{ + switch (devinfo->gen) { + case 11: return 0; + case 10: return 0; + case 9: return 0; + case 8: return 0; + case 7: + if (devinfo->is_haswell) { + return 0; + } else { + return 0; + } + case 6: return 0; + case 5: return 11; + case 4: + if (devinfo->is_g4x) { + return 11; + } else { + return 11; + } + default: + unreachable("Invalid hardware generation"); + } +} + + + +#ifdef __cplusplus +} +#endif + +#endif /* GENX_BITS_H */ \ No newline at end of file diff --git a/prebuilt-intermediates/genxml/genX_xml.h b/prebuilt-intermediates/genxml/genX_xml.h new file mode 100644 index 00000000000..4a58e71fafe --- /dev/null +++ b/prebuilt-intermediates/genxml/genX_xml.h @@ -0,0 +1,14476 @@ +static const struct { + uint32_t gen_10; + uint32_t offset; + uint32_t length; +} genxml_files_table[] = { + { 40, 0, 61903 }, + { 45, 61903, 64247 }, + { 50, 126150, 69852 }, + { 60, 196002, 114094 }, + { 70, 310096, 152504 }, + { 75, 462600, 182273 }, + { 80, 644873, 197223 }, + { 90, 842096, 216259 }, + { 100, 1058355, 213111 }, + { 110, 1271466, 213617 }, +}; + +static const uint8_t compress_genxmls[] = { + 0x78, 0x9c, 0xec, 0xbd, 0x5b, 0x97, 0xda, 0x48, 0x96, 0x36, 0x7c, 0xff, + 0xfe, 0x0a, 0x7d, 0x75, 0x33, 0x33, 0x6b, 0xbd, 0x76, 0x21, 0x0e, 0x09, + 0xd9, 0xab, 0x7b, 0x7a, 0x09, 0x10, 0x69, 0xb5, 0x05, 0xa2, 0x25, 0x91, + 0x87, 0xba, 0xd1, 0xc2, 0x99, 0x72, 0xa6, 0xa6, 0x49, 0x60, 0x80, 0x74, + 0x39, 0xeb, 0xd7, 0x7f, 0x11, 0x3a, 0xc4, 0x71, 0x87, 0x22, 0x44, 0xe2, + 0x7a, 0xed, 0x36, 0x7d, 0xd1, 0xe5, 0x72, 0x85, 0x1e, 0xe2, 0xb0, 0x63, + 0xc7, 0x3e, 0xef, 0xbf, 0xfe, 0xfd, 0xeb, 0xf3, 0xca, 0xfa, 0x92, 0xee, + 0xf6, 0xd9, 0x66, 0xfd, 0xb7, 0x5f, 0xec, 0xf7, 0xad, 0x5f, 0xac, 0xbf, + 0xff, 0xf7, 0xff, 0xf9, 0xeb, 0x63, 0xba, 0xc6, 0xff, 0x61, 0xbd, 0x7c, + 0x4e, 0xff, 0xf6, 0xcb, 0x30, 0xbc, 0xf9, 0xc5, 0x42, 0x7f, 0xf3, 0xb7, + 0x5f, 0xba, 0xbf, 0xfc, 0xf7, 0xff, 0xb1, 0xac, 0xbf, 0xa6, 0xeb, 0x97, + 0xe7, 0xf2, 0xbf, 0x75, 0xc6, 0xc9, 0x7c, 0x97, 0x3d, 0x27, 0xf1, 0x66, + 0xbb, 0x49, 0xe2, 0xd7, 0x6d, 0xfa, 0x8b, 0xb5, 0xdd, 0xa5, 0x9f, 0xb3, + 0xaf, 0xf8, 0x3f, 0xcd, 0x43, 0x6f, 0x9a, 0x7f, 0x81, 0xbe, 0xf9, 0xb2, + 0x5c, 0xbd, 0xa4, 0xe5, 0x47, 0xf3, 0xc0, 0x9b, 0xc5, 0xbe, 0x17, 0xc5, + 0xbf, 0x58, 0xf9, 0x5f, 0xa3, 0x1f, 0xfe, 0xe5, 0x57, 0x60, 0x9c, 0xef, + 0xcd, 0x5c, 0x6e, 0x58, 0x5b, 0x39, 0x2c, 0x8a, 0x43, 0x6f, 0x4e, 0xc6, + 0x75, 0xc0, 0x71, 0x68, 0x08, 0x87, 0xd6, 0x55, 0x8d, 0xe2, 0xc1, 0x7a, + 0xaa, 0x61, 0x13, 0x67, 0x46, 0x06, 0x5d, 0x80, 0x83, 0xfe, 0xb9, 0x70, + 0xc6, 0xdc, 0x4f, 0xf6, 0x95, 0xc3, 0xf8, 0xdf, 0x1c, 0xd4, 0xee, 0x47, + 0xe2, 0x8c, 0xff, 0x41, 0x86, 0x5e, 0xd6, 0xef, 0x09, 0x37, 0xd6, 0x6e, + 0xd5, 0x6d, 0x0c, 0x3f, 0x14, 0x3e, 0x92, 0x6a, 0x77, 0xf8, 0xb1, 0xf0, + 0xb9, 0x90, 0xb1, 0xa1, 0x7b, 0xed, 0x86, 0x91, 0x4b, 0xc7, 0xc3, 0xe7, + 0x33, 0x0f, 0xfc, 0xbb, 0xab, 0x80, 0xee, 0xa9, 0x0d, 0x1f, 0x50, 0xe8, + 0x8e, 0x04, 0xe2, 0x81, 0x4f, 0x28, 0xdf, 0xad, 0x20, 0xa0, 0x9b, 0x6a, + 0xc3, 0x87, 0x44, 0xa8, 0xd1, 0x4a, 0x86, 0x13, 0x3a, 0x18, 0x3e, 0x2a, + 0xba, 0xaf, 0xa3, 0x60, 0xc6, 0x4c, 0x41, 0x7d, 0x60, 0xc5, 0x68, 0x16, + 0x59, 0x77, 0x62, 0x18, 0x99, 0xfd, 0xa0, 0xad, 0x3c, 0x35, 0x44, 0x81, + 0xc9, 0x2c, 0x88, 0x62, 0x6f, 0x3e, 0xf7, 0xe9, 0xf6, 0xb6, 0xcb, 0xe3, + 0xf8, 0xeb, 0xaf, 0xf8, 0xa2, 0xfe, 0xf7, 0xff, 0x91, 0xaf, 0xec, 0x75, + 0xba, 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0x47, 0xc4, 0x1a, 0xdc, 0xde, 0x6f, 0x92, 0x78, 0xb7, 0xdc, 0xad, + 0x1e, 0x53, 0xf0, 0xb7, 0x8f, 0x46, 0x60, 0xdf, 0xe6, 0xb0, 0x1d, 0x53, + 0xe4, 0xa3, 0x3c, 0x25, 0x7f, 0x64, 0xc9, 0x9c, 0x3c, 0xda, 0x84, 0xfa, + 0x15, 0x1f, 0xbf, 0x5a, 0xb8, 0x5f, 0x92, 0xa2, 0x9e, 0x61, 0x9d, 0xac, + 0xbe, 0x37, 0xb8, 0xb2, 0xe3, 0x67, 0x1e, 0x7f, 0x6c, 0x97, 0x27, 0xc5, + 0x97, 0x45, 0xa9, 0xdf, 0xe2, 0xf3, 0x02, 0x9d, 0x91, 0x65, 0x04, 0xf1, + 0xbf, 0x5e, 0xe2, 0xfd, 0xc1, 0xb0, 0x77, 0x9f, 0x92, 0x83, 0x52, 0x77, + 0x75, 0xd0, 0xc3, 0x0b, 0x90, 0x8a, 0xba, 0x37, 0x82, 0xed, 0xa7, 0x44, + 0xee, 0x0d, 0x0e, 0xe2, 0xc3, 0xea, 0xd1, 0xc0, 0x38, 0xfe, 0x37, 0xc9, + 0xc3, 0x23, 0xfe, 0x71, 0xa4, 0xf4, 0xb6, 0x88, 0x69, 0xbf, 0x4b, 0x61, + 0x5c, 0x0a, 0x4c, 0x8a, 0x7d, 0xfd, 0xe7, 0x10, 0x1e, 0x98, 0x78, 0x0b, + 0x30, 0x2e, 0x0f, 0x72, 0x4a, 0x3f, 0xa7, 0xd3, 0x6a, 0x8c, 0x15, 0x4a, + 0x8a, 0x9e, 0x62, 0x9c, 0xf4, 0xfb, 0xb4, 0x7c, 0x7e, 0xc6, 0x4c, 0xfa, + 0x19, 0xdd, 0x7f, 0xda, 0xfd, 0x0a, 0xfb, 0xe8, 0x44, 0x03, 0xc6, 0xa1, + 0x6d, 0xe3, 0xca, 0x9d, 0x67, 0x5c, 0xa8, 0x95, 0x32, 0x51, 0x0a, 0x2a, + 0x88, 0xdc, 0x94, 0x4f, 0x18, 0x1a, 0xe6, 0x11, 0xfd, 0xf5, 0xe3, 0x16, + 0x8d, 0xc6, 0x3f, 0x15, 0xb3, 0xb0, 0x57, 0x3a, 0x58, 0x88, 0xcc, 0x76, + 0x54, 0xe6, 0x2a, 0xbe, 0xc0, 0x2b, 0x4a, 0xbc, 0x86, 0xc3, 0xde, 0x54, + 0xf0, 0xb9, 0x9f, 0xd0, 0xb8, 0xf7, 0x6b, 0xc9, 0x3f, 0xf7, 0x33, 0x1a, + 0xd1, 0x01, 0x40, 0x0d, 0x94, 0x89, 0xe9, 0xbc, 0x31, 0xd5, 0x68, 0x03, + 0x8e, 0xa8, 0x4e, 0x5e, 0x5f, 0xad, 0x52, 0xe0, 0xe8, 0x12, 0xfd, 0xa7, + 0xd0, 0x47, 0xad, 0x56, 0xd2, 0x38, 0xba, 0x75, 0xcf, 0x46, 0x0d, 0x04, + 0x8e, 0xa3, 0xae, 0x91, 0x80, 0xa1, 0x2b, 0x75, 0xdc, 0x2f, 0x11, 0x50, + 0x00, 0x79, 0xe0, 0xa5, 0x2a, 0x7a, 0x65, 0x5a, 0xaf, 0x49, 0xa1, 0x60, + 0x0c, 0x37, 0xe8, 0x5e, 0x21, 0xc3, 0x0d, 0xba, 0x57, 0x3e, 0xfa, 0xe5, + 0x04, 0xc9, 0x03, 0x6e, 0x1f, 0xb6, 0xfe, 0x12, 0x93, 0x89, 0x79, 0x1b, + 0x63, 0xee, 0x34, 0x30, 0xb2, 0xf8, 0xd5, 0x1f, 0x33, 0xac, 0xbf, 0xdb, + 0x3e, 0x6d, 0x0f, 0xc8, 0xa5, 0xb5, 0x8c, 0xc9, 0xf6, 0xf0, 0x8e, 0xfc, + 0x2b, 0x0d, 0x8f, 0x60, 0xda, 0x48, 0xf8, 0xb6, 0x75, 0xc6, 0x57, 0x23, + 0x6b, 0xd1, 0x09, 0x73, 0x20, 0x1f, 0x9e, 0x86, 0x06, 0x9e, 0x66, 0xe8, + 0xa4, 0x5a, 0xe1, 0x66, 0xf9, 0xc7, 0x72, 0x87, 0xa6, 0xfa, 0x65, 0x9b, + 0xdc, 0x2f, 0x37, 0xab, 0x18, 0x83, 0x7c, 0x36, 0xb0, 0x13, 0x13, 0xdf, + 0x70, 0x97, 0xbb, 0xf5, 0x77, 0xa4, 0x6b, 0x06, 0xcb, 0x64, 0x5d, 0x05, + 0xb2, 0x02, 0xe2, 0xb5, 0xe2, 0xd2, 0xde, 0x75, 0x9c, 0x16, 0x88, 0x32, + 0x9b, 0x35, 0x40, 0x7a, 0xb7, 0x42, 0x52, 0x23, 0x8a, 0xeb, 0x6c, 0xd7, + 0x69, 0xcc, 0x8e, 0x72, 0xfe, 0xab, 0x0c, 0x42, 0x2d, 0x27, 0x35, 0xd7, + 0xda, 0x47, 0x61, 0x28, 0xee, 0xe7, 0x35, 0x5e, 0xff, 0x2a, 0x7c, 0xd5, + 0x5c, 0xed, 0xd6, 0xb1, 0x57, 0x73, 0xe5, 0x28, 0xe2, 0x32, 0x8e, 0xa2, + 0x46, 0x5e, 0x58, 0x3d, 0xab, 0x71, 0x2a, 0x4b, 0x23, 0x65, 0x4c, 0xc8, + 0x6f, 0x27, 0xd1, 0x82, 0x18, 0xe3, 0xaa, 0xaa, 0x06, 0x5b, 0x71, 0x07, + 0xae, 0x5c, 0x65, 0x6b, 0x91, 0xb3, 0xe8, 0xa5, 0x29, 0xd0, 0x27, 0xea, + 0x97, 0x19, 0x31, 0x4d, 0x5c, 0x9a, 0xed, 0x6d, 0xde, 0x0d, 0xd6, 0xc8, + 0xaf, 0x3d, 0x18, 0xbf, 0xbd, 0xc4, 0x2f, 0x94, 0xbf, 0x1a, 0x28, 0xdd, + 0xc1, 0x7a, 0xbb, 0x3c, 0x18, 0xc0, 0xb9, 0x35, 0x07, 0x01, 0xc6, 0xe6, + 0x36, 0x35, 0x57, 0x94, 0x2c, 0xdd, 0x09, 0x05, 0xe7, 0xb6, 0xc1, 0x0e, + 0x37, 0x77, 0x1e, 0x9b, 0x6d, 0x74, 0x63, 0x95, 0x24, 0xd9, 0xee, 0xe6, + 0xde, 0x5e, 0xdd, 0xae, 0xe7, 0x54, 0x95, 0x3c, 0x1c, 0xf9, 0x9b, 0x42, + 0xdf, 0xed, 0xcd, 0x86, 0xa9, 0xa0, 0x80, 0xe1, 0x0f, 0xab, 0x75, 0x0f, + 0x86, 0x3f, 0x90, 0xbf, 0x95, 0x01, 0x55, 0x62, 0x07, 0x8c, 0xdd, 0xf5, + 0xe6, 0x42, 0x92, 0x81, 0x93, 0xd6, 0xd1, 0x52, 0x97, 0x03, 0x67, 0x3a, + 0x09, 0x23, 0x7b, 0x12, 0x2d, 0x7a, 0xb3, 0xc1, 0xc0, 0x0d, 0x08, 0xe6, + 0x45, 0x16, 0x21, 0xa9, 0x02, 0x49, 0x8a, 0xc4, 0x41, 0x7f, 0xe1, 0xcd, + 0x79, 0x57, 0xb8, 0xfe, 0xe6, 0xfc, 0xa9, 0xb6, 0x0d, 0x1a, 0x6c, 0xaa, + 0x98, 0xc8, 0x81, 0xd9, 0x09, 0x56, 0xba, 0x26, 0x1c, 0xbf, 0xba, 0x89, + 0x97, 0x68, 0x4b, 0x53, 0x24, 0x91, 0x31, 0xfa, 0x1f, 0x1c, 0x08, 0xc5, + 0x5e, 0x36, 0xba, 0x38, 0xbc, 0xc3, 0x0f, 0x47, 0xe9, 0x2c, 0xf3, 0x1e, + 0xc0, 0xfb, 0x06, 0xfe, 0x9c, 0x0e, 0x79, 0x0d, 0xb3, 0x2e, 0x43, 0x29, + 0xb0, 0x47, 0x83, 0x45, 0x38, 0xf2, 0x1c, 0xb7, 0x78, 0xb9, 0xbb, 0x14, + 0x6c, 0xca, 0x35, 0xe8, 0x91, 0x67, 0x4a, 0xe4, 0xde, 0x88, 0x62, 0x7c, + 0xeb, 0xcd, 0xcf, 0x0c, 0xcd, 0x79, 0x95, 0xec, 0x73, 0x53, 0xdc, 0x40, + 0x32, 0xe4, 0x44, 0x35, 0xd8, 0xad, 0xb4, 0x01, 0xff, 0xf1, 0xeb, 0x43, + 0xbc, 0xf9, 0xf6, 0xb4, 0xfe, 0xdf, 0xff, 0xed, 0xff, 0x01, 0x13, 0x84, + 0xdb, 0xf1, +}; diff --git a/prebuilt-intermediates/glsl/ir_expression_operation.h b/prebuilt-intermediates/glsl/ir_expression_operation.h new file mode 100644 index 00000000000..304a87b24b1 --- /dev/null +++ b/prebuilt-intermediates/glsl/ir_expression_operation.h @@ -0,0 +1,172 @@ +/* + * Copyright (C) 2010 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +enum ir_expression_operation { + ir_unop_bit_not, + ir_unop_logic_not, + ir_unop_neg, + ir_unop_abs, + ir_unop_sign, + ir_unop_rcp, + ir_unop_rsq, + ir_unop_sqrt, + ir_unop_exp, + ir_unop_log, + ir_unop_exp2, + ir_unop_log2, + ir_unop_f2i, + ir_unop_f2u, + ir_unop_i2f, + ir_unop_f2b, + ir_unop_b2f, + ir_unop_i2b, + ir_unop_b2i, + ir_unop_u2f, + ir_unop_i2u, + ir_unop_u2i, + ir_unop_d2f, + ir_unop_f2d, + ir_unop_d2i, + ir_unop_i2d, + ir_unop_d2u, + ir_unop_u2d, + ir_unop_d2b, + ir_unop_bitcast_i2f, + ir_unop_bitcast_f2i, + ir_unop_bitcast_u2f, + ir_unop_bitcast_f2u, + ir_unop_bitcast_u642d, + ir_unop_bitcast_i642d, + ir_unop_bitcast_d2u64, + ir_unop_bitcast_d2i64, + ir_unop_i642i, + ir_unop_u642i, + ir_unop_i642u, + ir_unop_u642u, + ir_unop_i642b, + ir_unop_i642f, + ir_unop_u642f, + ir_unop_i642d, + ir_unop_u642d, + ir_unop_i2i64, + ir_unop_u2i64, + ir_unop_b2i64, + ir_unop_f2i64, + ir_unop_d2i64, + ir_unop_i2u64, + ir_unop_u2u64, + ir_unop_f2u64, + ir_unop_d2u64, + ir_unop_u642i64, + ir_unop_i642u64, + ir_unop_trunc, + ir_unop_ceil, + ir_unop_floor, + ir_unop_fract, + ir_unop_round_even, + ir_unop_sin, + ir_unop_cos, + ir_unop_dFdx, + ir_unop_dFdx_coarse, + ir_unop_dFdx_fine, + ir_unop_dFdy, + ir_unop_dFdy_coarse, + ir_unop_dFdy_fine, + ir_unop_pack_snorm_2x16, + ir_unop_pack_snorm_4x8, + ir_unop_pack_unorm_2x16, + ir_unop_pack_unorm_4x8, + ir_unop_pack_half_2x16, + ir_unop_unpack_snorm_2x16, + ir_unop_unpack_snorm_4x8, + ir_unop_unpack_unorm_2x16, + ir_unop_unpack_unorm_4x8, + ir_unop_unpack_half_2x16, + ir_unop_bitfield_reverse, + ir_unop_bit_count, + ir_unop_find_msb, + ir_unop_find_lsb, + ir_unop_saturate, + ir_unop_pack_double_2x32, + ir_unop_unpack_double_2x32, + ir_unop_pack_sampler_2x32, + ir_unop_pack_image_2x32, + ir_unop_unpack_sampler_2x32, + ir_unop_unpack_image_2x32, + ir_unop_frexp_sig, + ir_unop_frexp_exp, + ir_unop_noise, + ir_unop_subroutine_to_int, + ir_unop_interpolate_at_centroid, + ir_unop_get_buffer_size, + ir_unop_ssbo_unsized_array_length, + ir_unop_pack_int_2x32, + ir_unop_pack_uint_2x32, + ir_unop_unpack_int_2x32, + ir_unop_unpack_uint_2x32, + ir_binop_add, + ir_binop_sub, + ir_binop_mul, + ir_binop_imul_high, + ir_binop_div, + ir_binop_carry, + ir_binop_borrow, + ir_binop_mod, + ir_binop_less, + ir_binop_gequal, + ir_binop_equal, + ir_binop_nequal, + ir_binop_all_equal, + ir_binop_any_nequal, + ir_binop_lshift, + ir_binop_rshift, + ir_binop_bit_and, + ir_binop_bit_xor, + ir_binop_bit_or, + ir_binop_logic_and, + ir_binop_logic_xor, + ir_binop_logic_or, + ir_binop_dot, + ir_binop_min, + ir_binop_max, + ir_binop_pow, + ir_binop_ubo_load, + ir_binop_ldexp, + ir_binop_vector_extract, + ir_binop_interpolate_at_offset, + ir_binop_interpolate_at_sample, + ir_triop_fma, + ir_triop_lrp, + ir_triop_csel, + ir_triop_bitfield_extract, + ir_triop_vector_insert, + ir_quadop_bitfield_insert, + ir_quadop_vector, + + /* Sentinels marking the last of each kind of operation. */ + ir_last_unop = ir_unop_unpack_uint_2x32, + ir_last_binop = ir_binop_interpolate_at_sample, + ir_last_triop = ir_triop_vector_insert, + ir_last_quadop = ir_quadop_vector, + ir_last_opcode = ir_quadop_vector +}; diff --git a/prebuilt-intermediates/glsl/ir_expression_operation_constant.h b/prebuilt-intermediates/glsl/ir_expression_operation_constant.h new file mode 100644 index 00000000000..c4730c40f33 --- /dev/null +++ b/prebuilt-intermediates/glsl/ir_expression_operation_constant.h @@ -0,0 +1,1871 @@ + switch (this->operation) { + case ir_unop_bit_not: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_UINT: + data.u[c] = ~ op[0]->value.u[c]; + break; + case GLSL_TYPE_INT: + data.i[c] = ~ op[0]->value.i[c]; + break; + case GLSL_TYPE_UINT64: + data.u64[c] = ~ op[0]->value.u64[c]; + break; + case GLSL_TYPE_INT64: + data.i64[c] = ~ op[0]->value.i64[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_logic_not: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_BOOL: + data.b[c] = !op[0]->value.b[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_neg: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_UINT: + data.u[c] = -((int) op[0]->value.u[c]); + break; + case GLSL_TYPE_INT: + data.i[c] = -op[0]->value.i[c]; + break; + case GLSL_TYPE_FLOAT: + data.f[c] = -op[0]->value.f[c]; + break; + case GLSL_TYPE_DOUBLE: + data.d[c] = -op[0]->value.d[c]; + break; + case GLSL_TYPE_UINT64: + data.u64[c] = -op[0]->value.u64[c]; + break; + case GLSL_TYPE_INT64: + data.i64[c] = -op[0]->value.i64[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_abs: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_INT: + data.i[c] = op[0]->value.i[c] < 0 ? -op[0]->value.i[c] : op[0]->value.i[c]; + break; + case GLSL_TYPE_FLOAT: + data.f[c] = fabsf(op[0]->value.f[c]); + break; + case GLSL_TYPE_DOUBLE: + data.d[c] = fabs(op[0]->value.d[c]); + break; + case GLSL_TYPE_INT64: + data.i64[c] = op[0]->value.i64[c] < 0 ? -op[0]->value.i64[c] : op[0]->value.i64[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_sign: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_INT: + data.i[c] = (op[0]->value.i[c] > 0) - (op[0]->value.i[c] < 0); + break; + case GLSL_TYPE_FLOAT: + data.f[c] = float((op[0]->value.f[c] > 0.0F) - (op[0]->value.f[c] < 0.0F)); + break; + case GLSL_TYPE_DOUBLE: + data.d[c] = double((op[0]->value.d[c] > 0.0) - (op[0]->value.d[c] < 0.0)); + break; + case GLSL_TYPE_INT64: + data.i64[c] = (op[0]->value.i64[c] > 0) - (op[0]->value.i64[c] < 0); + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_rcp: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_FLOAT: + data.f[c] = 1.0F / op[0]->value.f[c]; + break; + case GLSL_TYPE_DOUBLE: + data.d[c] = 1.0 / op[0]->value.d[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_rsq: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_FLOAT: + data.f[c] = 1.0F / sqrtf(op[0]->value.f[c]); + break; + case GLSL_TYPE_DOUBLE: + data.d[c] = 1.0 / sqrt(op[0]->value.d[c]); + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_sqrt: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_FLOAT: + data.f[c] = sqrtf(op[0]->value.f[c]); + break; + case GLSL_TYPE_DOUBLE: + data.d[c] = sqrt(op[0]->value.d[c]); + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_exp: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_FLOAT: + data.f[c] = expf(op[0]->value.f[c]); + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_log: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_FLOAT: + data.f[c] = logf(op[0]->value.f[c]); + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_exp2: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_FLOAT: + data.f[c] = exp2f(op[0]->value.f[c]); + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_log2: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_FLOAT: + data.f[c] = log2f(op[0]->value.f[c]); + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_f2i: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_FLOAT: + data.i[c] = (int) op[0]->value.f[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_f2u: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_FLOAT: + data.u[c] = (unsigned) op[0]->value.f[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_i2f: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_INT: + data.f[c] = (float) op[0]->value.i[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_f2b: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_FLOAT: + data.b[c] = op[0]->value.f[c] != 0.0F ? true : false; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_b2f: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_BOOL: + data.f[c] = op[0]->value.b[c] ? 1.0F : 0.0F; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_i2b: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_UINT: + data.b[c] = op[0]->value.u[c] ? true : false; + break; + case GLSL_TYPE_INT: + data.b[c] = op[0]->value.i[c] ? true : false; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_b2i: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_BOOL: + data.i[c] = op[0]->value.b[c] ? 1 : 0; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_u2f: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_UINT: + data.f[c] = (float) op[0]->value.u[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_i2u: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_INT: + data.u[c] = op[0]->value.i[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_u2i: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_UINT: + data.i[c] = op[0]->value.u[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_d2f: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_DOUBLE: + data.f[c] = op[0]->value.d[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_f2d: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_FLOAT: + data.d[c] = op[0]->value.f[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_d2i: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_DOUBLE: + data.i[c] = op[0]->value.d[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_i2d: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_INT: + data.d[c] = op[0]->value.i[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_d2u: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_DOUBLE: + data.u[c] = op[0]->value.d[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_u2d: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_UINT: + data.d[c] = op[0]->value.u[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_d2b: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_DOUBLE: + data.b[c] = op[0]->value.d[c] != 0.0; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_bitcast_i2f: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_INT: + data.f[c] = bitcast_u2f(op[0]->value.i[c]); + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_bitcast_f2i: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_FLOAT: + data.i[c] = bitcast_f2u(op[0]->value.f[c]); + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_bitcast_u2f: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_UINT: + data.f[c] = bitcast_u2f(op[0]->value.u[c]); + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_bitcast_f2u: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_FLOAT: + data.u[c] = bitcast_f2u(op[0]->value.f[c]); + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_bitcast_u642d: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_UINT64: + data.d[c] = bitcast_u642d(op[0]->value.u64[c]); + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_bitcast_i642d: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_INT64: + data.d[c] = bitcast_i642d(op[0]->value.i64[c]); + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_bitcast_d2u64: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_DOUBLE: + data.u64[c] = bitcast_d2u64(op[0]->value.d[c]); + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_bitcast_d2i64: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_DOUBLE: + data.i64[c] = bitcast_d2i64(op[0]->value.d[c]); + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_i642i: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_INT64: + data.i[c] = op[0]->value.i64[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_u642i: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_UINT64: + data.i[c] = op[0]->value.u64[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_i642u: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_INT64: + data.u[c] = op[0]->value.i64[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_u642u: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_UINT64: + data.u[c] = op[0]->value.u64[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_i642b: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_INT64: + data.b[c] = op[0]->value.i64[c] != 0; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_i642f: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_INT64: + data.f[c] = op[0]->value.i64[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_u642f: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_UINT64: + data.f[c] = op[0]->value.u64[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_i642d: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_INT64: + data.d[c] = op[0]->value.i64[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_u642d: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_UINT64: + data.d[c] = op[0]->value.u64[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_i2i64: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_INT: + data.i64[c] = op[0]->value.i[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_u2i64: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_UINT: + data.i64[c] = op[0]->value.u[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_b2i64: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_BOOL: + data.i64[c] = op[0]->value.b[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_f2i64: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_FLOAT: + data.i64[c] = op[0]->value.f[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_d2i64: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_DOUBLE: + data.i64[c] = op[0]->value.d[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_i2u64: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_INT: + data.u64[c] = op[0]->value.i[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_u2u64: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_UINT: + data.u64[c] = op[0]->value.u[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_f2u64: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_FLOAT: + data.u64[c] = op[0]->value.f[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_d2u64: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_DOUBLE: + data.u64[c] = op[0]->value.d[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_u642i64: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_UINT64: + data.i64[c] = op[0]->value.u64[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_i642u64: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_INT64: + data.u64[c] = op[0]->value.i64[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_trunc: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_FLOAT: + data.f[c] = truncf(op[0]->value.f[c]); + break; + case GLSL_TYPE_DOUBLE: + data.d[c] = trunc(op[0]->value.d[c]); + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_ceil: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_FLOAT: + data.f[c] = ceilf(op[0]->value.f[c]); + break; + case GLSL_TYPE_DOUBLE: + data.d[c] = ceil(op[0]->value.d[c]); + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_floor: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_FLOAT: + data.f[c] = floorf(op[0]->value.f[c]); + break; + case GLSL_TYPE_DOUBLE: + data.d[c] = floor(op[0]->value.d[c]); + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_fract: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_FLOAT: + data.f[c] = op[0]->value.f[c] - floorf(op[0]->value.f[c]); + break; + case GLSL_TYPE_DOUBLE: + data.d[c] = op[0]->value.d[c] - floor(op[0]->value.d[c]); + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_round_even: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_FLOAT: + data.f[c] = _mesa_roundevenf(op[0]->value.f[c]); + break; + case GLSL_TYPE_DOUBLE: + data.d[c] = _mesa_roundeven(op[0]->value.d[c]); + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_sin: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_FLOAT: + data.f[c] = sinf(op[0]->value.f[c]); + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_cos: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_FLOAT: + data.f[c] = cosf(op[0]->value.f[c]); + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_dFdx: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_FLOAT: + data.f[c] = 0.0f; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_dFdx_coarse: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_FLOAT: + data.f[c] = 0.0f; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_dFdx_fine: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_FLOAT: + data.f[c] = 0.0f; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_dFdy: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_FLOAT: + data.f[c] = 0.0f; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_dFdy_coarse: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_FLOAT: + data.f[c] = 0.0f; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_dFdy_fine: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_FLOAT: + data.f[c] = 0.0f; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_pack_snorm_2x16: + switch (op[0]->type->base_type) { + case GLSL_TYPE_FLOAT: + data.u[0] = pack_2x16(pack_snorm_1x16, op[0]->value.f[0], op[0]->value.f[1]); + break; + default: + unreachable("invalid type"); + } + break; + + case ir_unop_pack_snorm_4x8: + switch (op[0]->type->base_type) { + case GLSL_TYPE_FLOAT: + data.u[0] = pack_4x8(pack_snorm_1x8, op[0]->value.f[0], op[0]->value.f[1], op[0]->value.f[2], op[0]->value.f[3]); + break; + default: + unreachable("invalid type"); + } + break; + + case ir_unop_pack_unorm_2x16: + switch (op[0]->type->base_type) { + case GLSL_TYPE_FLOAT: + data.u[0] = pack_2x16(pack_unorm_1x16, op[0]->value.f[0], op[0]->value.f[1]); + break; + default: + unreachable("invalid type"); + } + break; + + case ir_unop_pack_unorm_4x8: + switch (op[0]->type->base_type) { + case GLSL_TYPE_FLOAT: + data.u[0] = pack_4x8(pack_unorm_1x8, op[0]->value.f[0], op[0]->value.f[1], op[0]->value.f[2], op[0]->value.f[3]); + break; + default: + unreachable("invalid type"); + } + break; + + case ir_unop_pack_half_2x16: + switch (op[0]->type->base_type) { + case GLSL_TYPE_FLOAT: + data.u[0] = pack_2x16(pack_half_1x16, op[0]->value.f[0], op[0]->value.f[1]); + break; + default: + unreachable("invalid type"); + } + break; + + case ir_unop_unpack_snorm_2x16: + unpack_2x16(unpack_snorm_1x16, op[0]->value.u[0], &data.f[0], &data.f[1]); + break; + + case ir_unop_unpack_snorm_4x8: + unpack_4x8(unpack_snorm_1x8, op[0]->value.u[0], &data.f[0], &data.f[1], &data.f[2], &data.f[3]); + break; + + case ir_unop_unpack_unorm_2x16: + unpack_2x16(unpack_unorm_1x16, op[0]->value.u[0], &data.f[0], &data.f[1]); + break; + + case ir_unop_unpack_unorm_4x8: + unpack_4x8(unpack_unorm_1x8, op[0]->value.u[0], &data.f[0], &data.f[1], &data.f[2], &data.f[3]); + break; + + case ir_unop_unpack_half_2x16: + unpack_2x16(unpack_half_1x16, op[0]->value.u[0], &data.f[0], &data.f[1]); + break; + + case ir_unop_bitfield_reverse: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_UINT: + data.u[c] = bitfield_reverse(op[0]->value.u[c]); + break; + case GLSL_TYPE_INT: + data.i[c] = bitfield_reverse(op[0]->value.i[c]); + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_bit_count: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_UINT: + data.i[c] = util_bitcount(op[0]->value.u[c]); + break; + case GLSL_TYPE_INT: + data.i[c] = util_bitcount(op[0]->value.i[c]); + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_find_msb: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_UINT: + data.i[c] = find_msb_uint(op[0]->value.u[c]); + break; + case GLSL_TYPE_INT: + data.i[c] = find_msb_int(op[0]->value.i[c]); + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_find_lsb: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_UINT: + data.i[c] = find_msb_uint(op[0]->value.u[c] & -op[0]->value.u[c]); + break; + case GLSL_TYPE_INT: + data.i[c] = find_msb_uint(op[0]->value.i[c] & -op[0]->value.i[c]); + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_saturate: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_FLOAT: + data.f[c] = CLAMP(op[0]->value.f[c], 0.0f, 1.0f); + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_unop_pack_double_2x32: + memcpy(&data.d[0], &op[0]->value.u[0], sizeof(double)); + break; + + case ir_unop_unpack_double_2x32: + memcpy(&data.u[0], &op[0]->value.d[0], sizeof(double)); + break; + + case ir_unop_pack_sampler_2x32: + memcpy(&data.u64[0], &op[0]->value.u[0], sizeof(uint64_t)); + break; + + case ir_unop_pack_image_2x32: + memcpy(&data.u64[0], &op[0]->value.u[0], sizeof(uint64_t)); + break; + + case ir_unop_unpack_sampler_2x32: + memcpy(&data.u[0], &op[0]->value.u64[0], sizeof(uint64_t)); + break; + + case ir_unop_unpack_image_2x32: + memcpy(&data.u[0], &op[0]->value.u64[0], sizeof(uint64_t)); + break; + + case ir_unop_pack_int_2x32: + memcpy(&data.i64[0], &op[0]->value.i[0], sizeof(int64_t)); + break; + + case ir_unop_pack_uint_2x32: + memcpy(&data.u64[0], &op[0]->value.u[0], sizeof(uint64_t)); + break; + + case ir_unop_unpack_int_2x32: + memcpy(&data.i[0], &op[0]->value.i64[0], sizeof(int64_t)); + break; + + case ir_unop_unpack_uint_2x32: + memcpy(&data.u[0], &op[0]->value.u64[0], sizeof(uint64_t)); + break; + + case ir_binop_add: + assert(op[0]->type == op[1]->type || op0_scalar || op1_scalar); + for (unsigned c = 0, c0 = 0, c1 = 0; + c < components; + c0 += c0_inc, c1 += c1_inc, c++) { + + switch (op[0]->type->base_type) { + case GLSL_TYPE_UINT: + data.u[c] = op[0]->value.u[c0] + op[1]->value.u[c1]; + break; + case GLSL_TYPE_INT: + data.i[c] = op[0]->value.i[c0] + op[1]->value.i[c1]; + break; + case GLSL_TYPE_FLOAT: + data.f[c] = op[0]->value.f[c0] + op[1]->value.f[c1]; + break; + case GLSL_TYPE_DOUBLE: + data.d[c] = op[0]->value.d[c0] + op[1]->value.d[c1]; + break; + case GLSL_TYPE_UINT64: + data.u64[c] = op[0]->value.u64[c0] + op[1]->value.u64[c1]; + break; + case GLSL_TYPE_INT64: + data.i64[c] = op[0]->value.i64[c0] + op[1]->value.i64[c1]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_binop_sub: + assert(op[0]->type == op[1]->type || op0_scalar || op1_scalar); + for (unsigned c = 0, c0 = 0, c1 = 0; + c < components; + c0 += c0_inc, c1 += c1_inc, c++) { + + switch (op[0]->type->base_type) { + case GLSL_TYPE_UINT: + data.u[c] = op[0]->value.u[c0] - op[1]->value.u[c1]; + break; + case GLSL_TYPE_INT: + data.i[c] = op[0]->value.i[c0] - op[1]->value.i[c1]; + break; + case GLSL_TYPE_FLOAT: + data.f[c] = op[0]->value.f[c0] - op[1]->value.f[c1]; + break; + case GLSL_TYPE_DOUBLE: + data.d[c] = op[0]->value.d[c0] - op[1]->value.d[c1]; + break; + case GLSL_TYPE_UINT64: + data.u64[c] = op[0]->value.u64[c0] - op[1]->value.u64[c1]; + break; + case GLSL_TYPE_INT64: + data.i64[c] = op[0]->value.i64[c0] - op[1]->value.i64[c1]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_binop_mul: + /* Check for equal types, or unequal types involving scalars */ + if ((op[0]->type == op[1]->type && !op[0]->type->is_matrix()) + || op0_scalar || op1_scalar) { + for (unsigned c = 0, c0 = 0, c1 = 0; + c < components; + c0 += c0_inc, c1 += c1_inc, c++) { + + switch (op[0]->type->base_type) { + case GLSL_TYPE_UINT: + data.u[c] = op[0]->value.u[c0] * op[1]->value.u[c1]; + break; + case GLSL_TYPE_INT: + data.i[c] = op[0]->value.i[c0] * op[1]->value.i[c1]; + break; + case GLSL_TYPE_FLOAT: + data.f[c] = op[0]->value.f[c0] * op[1]->value.f[c1]; + break; + case GLSL_TYPE_DOUBLE: + data.d[c] = op[0]->value.d[c0] * op[1]->value.d[c1]; + break; + case GLSL_TYPE_UINT64: + data.u64[c] = op[0]->value.u64[c0] * op[1]->value.u64[c1]; + break; + case GLSL_TYPE_INT64: + data.i64[c] = op[0]->value.i64[c0] * op[1]->value.i64[c1]; + break; + default: + unreachable("invalid type"); + } + } + } else { + assert(op[0]->type->is_matrix() || op[1]->type->is_matrix()); + + /* Multiply an N-by-M matrix with an M-by-P matrix. Since either + * matrix can be a GLSL vector, either N or P can be 1. + * + * For vec*mat, the vector is treated as a row vector. This + * means the vector is a 1-row x M-column matrix. + * + * For mat*vec, the vector is treated as a column vector. Since + * matrix_columns is 1 for vectors, this just works. + */ + const unsigned n = op[0]->type->is_vector() + ? 1 : op[0]->type->vector_elements; + const unsigned m = op[1]->type->vector_elements; + const unsigned p = op[1]->type->matrix_columns; + for (unsigned j = 0; j < p; j++) { + for (unsigned i = 0; i < n; i++) { + for (unsigned k = 0; k < m; k++) { + if (op[0]->type->is_double()) + data.d[i+n*j] += op[0]->value.d[i+n*k]*op[1]->value.d[k+m*j]; + else + data.f[i+n*j] += op[0]->value.f[i+n*k]*op[1]->value.f[k+m*j]; + } + } + } + } + break; + + case ir_binop_div: + assert(op[0]->type == op[1]->type || op0_scalar || op1_scalar); + for (unsigned c = 0, c0 = 0, c1 = 0; + c < components; + c0 += c0_inc, c1 += c1_inc, c++) { + + switch (op[0]->type->base_type) { + case GLSL_TYPE_UINT: + data.u[c] = op[1]->value.u[c1] == 0 ? 0 : op[0]->value.u[c0] / op[1]->value.u[c1]; + break; + case GLSL_TYPE_INT: + data.i[c] = op[1]->value.i[c1] == 0 ? 0 : op[0]->value.i[c0] / op[1]->value.i[c1]; + break; + case GLSL_TYPE_FLOAT: + data.f[c] = op[0]->value.f[c0] / op[1]->value.f[c1]; + break; + case GLSL_TYPE_DOUBLE: + data.d[c] = op[0]->value.d[c0] / op[1]->value.d[c1]; + break; + case GLSL_TYPE_UINT64: + data.u64[c] = op[1]->value.u64[c1] == 0 ? 0 : op[0]->value.u64[c0] / op[1]->value.u64[c1]; + break; + case GLSL_TYPE_INT64: + data.i64[c] = op[1]->value.i64[c1] == 0 ? 0 : op[0]->value.i64[c0] / op[1]->value.i64[c1]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_binop_mod: + assert(op[0]->type == op[1]->type || op0_scalar || op1_scalar); + for (unsigned c = 0, c0 = 0, c1 = 0; + c < components; + c0 += c0_inc, c1 += c1_inc, c++) { + + switch (op[0]->type->base_type) { + case GLSL_TYPE_UINT: + data.u[c] = op[1]->value.u[c1] == 0 ? 0 : op[0]->value.u[c0] % op[1]->value.u[c1]; + break; + case GLSL_TYPE_INT: + data.i[c] = op[1]->value.i[c1] == 0 ? 0 : op[0]->value.i[c0] % op[1]->value.i[c1]; + break; + case GLSL_TYPE_FLOAT: + data.f[c] = op[0]->value.f[c0] - op[1]->value.f[c1] * floorf(op[0]->value.f[c0] / op[1]->value.f[c1]); + break; + case GLSL_TYPE_DOUBLE: + data.d[c] = op[0]->value.d[c0] - op[1]->value.d[c1] * floor(op[0]->value.d[c0] / op[1]->value.d[c1]); + break; + case GLSL_TYPE_UINT64: + data.u64[c] = op[1]->value.u64[c1] == 0 ? 0 : op[0]->value.u64[c0] % op[1]->value.u64[c1]; + break; + case GLSL_TYPE_INT64: + data.i64[c] = op[1]->value.i64[c1] == 0 ? 0 : op[0]->value.i64[c0] % op[1]->value.i64[c1]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_binop_less: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_UINT: + data.b[c] = op[0]->value.u[c] < op[1]->value.u[c]; + break; + case GLSL_TYPE_INT: + data.b[c] = op[0]->value.i[c] < op[1]->value.i[c]; + break; + case GLSL_TYPE_FLOAT: + data.b[c] = op[0]->value.f[c] < op[1]->value.f[c]; + break; + case GLSL_TYPE_DOUBLE: + data.b[c] = op[0]->value.d[c] < op[1]->value.d[c]; + break; + case GLSL_TYPE_UINT64: + data.b[c] = op[0]->value.u64[c] < op[1]->value.u64[c]; + break; + case GLSL_TYPE_INT64: + data.b[c] = op[0]->value.i64[c] < op[1]->value.i64[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_binop_gequal: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_UINT: + data.b[c] = op[0]->value.u[c] >= op[1]->value.u[c]; + break; + case GLSL_TYPE_INT: + data.b[c] = op[0]->value.i[c] >= op[1]->value.i[c]; + break; + case GLSL_TYPE_FLOAT: + data.b[c] = op[0]->value.f[c] >= op[1]->value.f[c]; + break; + case GLSL_TYPE_DOUBLE: + data.b[c] = op[0]->value.d[c] >= op[1]->value.d[c]; + break; + case GLSL_TYPE_UINT64: + data.b[c] = op[0]->value.u64[c] >= op[1]->value.u64[c]; + break; + case GLSL_TYPE_INT64: + data.b[c] = op[0]->value.i64[c] >= op[1]->value.i64[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_binop_equal: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_UINT: + data.b[c] = op[0]->value.u[c] == op[1]->value.u[c]; + break; + case GLSL_TYPE_INT: + data.b[c] = op[0]->value.i[c] == op[1]->value.i[c]; + break; + case GLSL_TYPE_FLOAT: + data.b[c] = op[0]->value.f[c] == op[1]->value.f[c]; + break; + case GLSL_TYPE_DOUBLE: + data.b[c] = op[0]->value.d[c] == op[1]->value.d[c]; + break; + case GLSL_TYPE_UINT64: + data.b[c] = op[0]->value.u64[c] == op[1]->value.u64[c]; + break; + case GLSL_TYPE_INT64: + data.b[c] = op[0]->value.i64[c] == op[1]->value.i64[c]; + break; + case GLSL_TYPE_BOOL: + data.b[c] = op[0]->value.b[c] == op[1]->value.b[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_binop_nequal: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_UINT: + data.b[c] = op[0]->value.u[c] != op[1]->value.u[c]; + break; + case GLSL_TYPE_INT: + data.b[c] = op[0]->value.i[c] != op[1]->value.i[c]; + break; + case GLSL_TYPE_FLOAT: + data.b[c] = op[0]->value.f[c] != op[1]->value.f[c]; + break; + case GLSL_TYPE_DOUBLE: + data.b[c] = op[0]->value.d[c] != op[1]->value.d[c]; + break; + case GLSL_TYPE_UINT64: + data.b[c] = op[0]->value.u64[c] != op[1]->value.u64[c]; + break; + case GLSL_TYPE_INT64: + data.b[c] = op[0]->value.i64[c] != op[1]->value.i64[c]; + break; + case GLSL_TYPE_BOOL: + data.b[c] = op[0]->value.b[c] != op[1]->value.b[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_binop_all_equal: + data.b[0] = op[0]->has_value(op[1]); + break; + + case ir_binop_any_nequal: + data.b[0] = !op[0]->has_value(op[1]); + break; + + case ir_binop_lshift: + assert(op[0]->type->base_type == GLSL_TYPE_UINT || + op[0]->type->base_type == GLSL_TYPE_INT || + op[0]->type->base_type == GLSL_TYPE_UINT64 || + op[0]->type->base_type == GLSL_TYPE_INT64); + assert(op[1]->type->base_type == GLSL_TYPE_UINT || + op[1]->type->base_type == GLSL_TYPE_INT || + op[1]->type->base_type == GLSL_TYPE_UINT64 || + op[1]->type->base_type == GLSL_TYPE_INT64); + for (unsigned c = 0, c0 = 0, c1 = 0; + c < components; + c0 += c0_inc, c1 += c1_inc, c++) { + + switch (op[0]->type->base_type) { + case GLSL_TYPE_UINT: + data.u[c] = op[0]->value.u[c0] << op[1]->value.u[c1]; + break; + case GLSL_TYPE_INT: + data.i[c] = op[0]->value.i[c0] << op[1]->value.i[c1]; + break; + case GLSL_TYPE_UINT64: + data.u64[c] = op[0]->value.u64[c0] << op[1]->value.u64[c1]; + break; + case GLSL_TYPE_INT64: + data.i64[c] = op[0]->value.i64[c0] << op[1]->value.i64[c1]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_binop_rshift: + assert(op[0]->type->base_type == GLSL_TYPE_UINT || + op[0]->type->base_type == GLSL_TYPE_INT || + op[0]->type->base_type == GLSL_TYPE_UINT64 || + op[0]->type->base_type == GLSL_TYPE_INT64); + assert(op[1]->type->base_type == GLSL_TYPE_UINT || + op[1]->type->base_type == GLSL_TYPE_INT || + op[1]->type->base_type == GLSL_TYPE_UINT64 || + op[1]->type->base_type == GLSL_TYPE_INT64); + for (unsigned c = 0, c0 = 0, c1 = 0; + c < components; + c0 += c0_inc, c1 += c1_inc, c++) { + + switch (op[0]->type->base_type) { + case GLSL_TYPE_UINT: + data.u[c] = op[0]->value.u[c0] >> op[1]->value.u[c1]; + break; + case GLSL_TYPE_INT: + data.i[c] = op[0]->value.i[c0] >> op[1]->value.i[c1]; + break; + case GLSL_TYPE_UINT64: + data.u64[c] = op[0]->value.u64[c0] >> op[1]->value.u64[c1]; + break; + case GLSL_TYPE_INT64: + data.i64[c] = op[0]->value.i64[c0] >> op[1]->value.i64[c1]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_binop_bit_and: + assert(op[0]->type == op[1]->type || op0_scalar || op1_scalar); + for (unsigned c = 0, c0 = 0, c1 = 0; + c < components; + c0 += c0_inc, c1 += c1_inc, c++) { + + switch (op[0]->type->base_type) { + case GLSL_TYPE_UINT: + data.u[c] = op[0]->value.u[c0] & op[1]->value.u[c1]; + break; + case GLSL_TYPE_INT: + data.i[c] = op[0]->value.i[c0] & op[1]->value.i[c1]; + break; + case GLSL_TYPE_UINT64: + data.u64[c] = op[0]->value.u64[c0] & op[1]->value.u64[c1]; + break; + case GLSL_TYPE_INT64: + data.i64[c] = op[0]->value.i64[c0] & op[1]->value.i64[c1]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_binop_bit_xor: + assert(op[0]->type == op[1]->type || op0_scalar || op1_scalar); + for (unsigned c = 0, c0 = 0, c1 = 0; + c < components; + c0 += c0_inc, c1 += c1_inc, c++) { + + switch (op[0]->type->base_type) { + case GLSL_TYPE_UINT: + data.u[c] = op[0]->value.u[c0] ^ op[1]->value.u[c1]; + break; + case GLSL_TYPE_INT: + data.i[c] = op[0]->value.i[c0] ^ op[1]->value.i[c1]; + break; + case GLSL_TYPE_UINT64: + data.u64[c] = op[0]->value.u64[c0] ^ op[1]->value.u64[c1]; + break; + case GLSL_TYPE_INT64: + data.i64[c] = op[0]->value.i64[c0] ^ op[1]->value.i64[c1]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_binop_bit_or: + assert(op[0]->type == op[1]->type || op0_scalar || op1_scalar); + for (unsigned c = 0, c0 = 0, c1 = 0; + c < components; + c0 += c0_inc, c1 += c1_inc, c++) { + + switch (op[0]->type->base_type) { + case GLSL_TYPE_UINT: + data.u[c] = op[0]->value.u[c0] | op[1]->value.u[c1]; + break; + case GLSL_TYPE_INT: + data.i[c] = op[0]->value.i[c0] | op[1]->value.i[c1]; + break; + case GLSL_TYPE_UINT64: + data.u64[c] = op[0]->value.u64[c0] | op[1]->value.u64[c1]; + break; + case GLSL_TYPE_INT64: + data.i64[c] = op[0]->value.i64[c0] | op[1]->value.i64[c1]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_binop_logic_and: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_BOOL: + data.b[c] = op[0]->value.b[c] && op[1]->value.b[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_binop_logic_xor: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_BOOL: + data.b[c] = op[0]->value.b[c] != op[1]->value.b[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_binop_logic_or: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_BOOL: + data.b[c] = op[0]->value.b[c] || op[1]->value.b[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_binop_dot: + switch (op[0]->type->base_type) { + case GLSL_TYPE_FLOAT: + data.f[0] = dot_f(op[0], op[1]); + break; + case GLSL_TYPE_DOUBLE: + data.d[0] = dot_d(op[0], op[1]); + break; + default: + unreachable("invalid type"); + } + break; + + case ir_binop_min: + assert(op[0]->type == op[1]->type || op0_scalar || op1_scalar); + for (unsigned c = 0, c0 = 0, c1 = 0; + c < components; + c0 += c0_inc, c1 += c1_inc, c++) { + + switch (op[0]->type->base_type) { + case GLSL_TYPE_UINT: + data.u[c] = MIN2(op[0]->value.u[c0], op[1]->value.u[c1]); + break; + case GLSL_TYPE_INT: + data.i[c] = MIN2(op[0]->value.i[c0], op[1]->value.i[c1]); + break; + case GLSL_TYPE_FLOAT: + data.f[c] = MIN2(op[0]->value.f[c0], op[1]->value.f[c1]); + break; + case GLSL_TYPE_DOUBLE: + data.d[c] = MIN2(op[0]->value.d[c0], op[1]->value.d[c1]); + break; + case GLSL_TYPE_UINT64: + data.u64[c] = MIN2(op[0]->value.u64[c0], op[1]->value.u64[c1]); + break; + case GLSL_TYPE_INT64: + data.i64[c] = MIN2(op[0]->value.i64[c0], op[1]->value.i64[c1]); + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_binop_max: + assert(op[0]->type == op[1]->type || op0_scalar || op1_scalar); + for (unsigned c = 0, c0 = 0, c1 = 0; + c < components; + c0 += c0_inc, c1 += c1_inc, c++) { + + switch (op[0]->type->base_type) { + case GLSL_TYPE_UINT: + data.u[c] = MAX2(op[0]->value.u[c0], op[1]->value.u[c1]); + break; + case GLSL_TYPE_INT: + data.i[c] = MAX2(op[0]->value.i[c0], op[1]->value.i[c1]); + break; + case GLSL_TYPE_FLOAT: + data.f[c] = MAX2(op[0]->value.f[c0], op[1]->value.f[c1]); + break; + case GLSL_TYPE_DOUBLE: + data.d[c] = MAX2(op[0]->value.d[c0], op[1]->value.d[c1]); + break; + case GLSL_TYPE_UINT64: + data.u64[c] = MAX2(op[0]->value.u64[c0], op[1]->value.u64[c1]); + break; + case GLSL_TYPE_INT64: + data.i64[c] = MAX2(op[0]->value.i64[c0], op[1]->value.i64[c1]); + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_binop_pow: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_FLOAT: + data.f[c] = powf(op[0]->value.f[c], op[1]->value.f[c]); + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_binop_ldexp: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_FLOAT: + data.f[c] = ldexpf_flush_subnormal(op[0]->value.f[c], op[1]->value.i[c]); + break; + case GLSL_TYPE_DOUBLE: + data.d[c] = ldexp_flush_subnormal(op[0]->value.d[c], op[1]->value.i[c]); + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_binop_vector_extract: { + const int c = CLAMP(op[1]->value.i[0], 0, + (int) op[0]->type->vector_elements - 1); + + switch (op[0]->type->base_type) { + case GLSL_TYPE_UINT: + data.u[0] = op[0]->value.u[c]; + break; + case GLSL_TYPE_INT: + data.i[0] = op[0]->value.i[c]; + break; + case GLSL_TYPE_FLOAT: + data.f[0] = op[0]->value.f[c]; + break; + case GLSL_TYPE_DOUBLE: + data.d[0] = op[0]->value.d[c]; + break; + case GLSL_TYPE_UINT64: + data.u64[0] = op[0]->value.u64[c]; + break; + case GLSL_TYPE_INT64: + data.i64[0] = op[0]->value.i64[c]; + break; + case GLSL_TYPE_BOOL: + data.b[0] = op[0]->value.b[c]; + break; + default: + unreachable("invalid type"); + } + break; + } + + case ir_triop_fma: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_FLOAT: + data.f[c] = op[0]->value.f[c] * op[1]->value.f[c] + op[2]->value.f[c]; + break; + case GLSL_TYPE_DOUBLE: + data.d[c] = op[0]->value.d[c] * op[1]->value.d[c] + op[2]->value.d[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_triop_lrp: { + assert(op[0]->type->is_float() || op[0]->type->is_double()); + assert(op[1]->type->is_float() || op[1]->type->is_double()); + assert(op[2]->type->is_float() || op[2]->type->is_double()); + + unsigned c2_inc = op[2]->type->is_scalar() ? 0 : 1; + for (unsigned c = 0, c2 = 0; c < components; c2 += c2_inc, c++) { + switch (this->type->base_type) { + case GLSL_TYPE_FLOAT: + data.f[c] = op[0]->value.f[c] * (1.0f - op[2]->value.f[c2]) + (op[1]->value.f[c] * op[2]->value.f[c2]); + break; + case GLSL_TYPE_DOUBLE: + data.d[c] = op[0]->value.d[c] * (1.0 - op[2]->value.d[c2]) + (op[1]->value.d[c] * op[2]->value.d[c2]); + break; + default: + unreachable("invalid type"); + } + } + break; + } + + case ir_triop_csel: + for (unsigned c = 0; c < components; c++) { + switch (this->type->base_type) { + case GLSL_TYPE_UINT: + data.u[c] = op[0]->value.b[c] ? op[1]->value.u[c] : op[2]->value.u[c]; + break; + case GLSL_TYPE_INT: + data.i[c] = op[0]->value.b[c] ? op[1]->value.i[c] : op[2]->value.i[c]; + break; + case GLSL_TYPE_FLOAT: + data.f[c] = op[0]->value.b[c] ? op[1]->value.f[c] : op[2]->value.f[c]; + break; + case GLSL_TYPE_DOUBLE: + data.d[c] = op[0]->value.b[c] ? op[1]->value.d[c] : op[2]->value.d[c]; + break; + case GLSL_TYPE_UINT64: + data.u64[c] = op[0]->value.b[c] ? op[1]->value.u64[c] : op[2]->value.u64[c]; + break; + case GLSL_TYPE_INT64: + data.i64[c] = op[0]->value.b[c] ? op[1]->value.i64[c] : op[2]->value.i64[c]; + break; + case GLSL_TYPE_BOOL: + data.b[c] = op[0]->value.b[c] ? op[1]->value.b[c] : op[2]->value.b[c]; + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_triop_bitfield_extract: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_UINT: + data.i[c] = bitfield_extract_uint(op[0]->value.u[c], op[1]->value.i[c], op[2]->value.i[c]); + break; + case GLSL_TYPE_INT: + data.i[c] = bitfield_extract_int(op[0]->value.i[c], op[1]->value.i[c], op[2]->value.i[c]); + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_triop_vector_insert: { + const unsigned idx = op[2]->value.u[0]; + + memcpy(&data, &op[0]->value, sizeof(data)); + + switch (this->type->base_type) { + case GLSL_TYPE_UINT: + data.u[idx] = op[1]->value.u[0]; + break; + case GLSL_TYPE_INT: + data.i[idx] = op[1]->value.i[0]; + break; + case GLSL_TYPE_FLOAT: + data.f[idx] = op[1]->value.f[0]; + break; + case GLSL_TYPE_DOUBLE: + data.d[idx] = op[1]->value.d[0]; + break; + case GLSL_TYPE_UINT64: + data.u64[idx] = op[1]->value.u64[0]; + break; + case GLSL_TYPE_INT64: + data.i64[idx] = op[1]->value.i64[0]; + break; + case GLSL_TYPE_BOOL: + data.b[idx] = op[1]->value.b[0]; + break; + default: + unreachable("invalid type"); + } + break; + } + + case ir_quadop_bitfield_insert: + for (unsigned c = 0; c < op[0]->type->components(); c++) { + switch (op[0]->type->base_type) { + case GLSL_TYPE_UINT: + data.u[c] = bitfield_insert(op[0]->value.u[c], op[1]->value.u[c], op[2]->value.i[c], op[3]->value.i[c]); + break; + case GLSL_TYPE_INT: + data.i[c] = bitfield_insert(op[0]->value.i[c], op[1]->value.i[c], op[2]->value.i[c], op[3]->value.i[c]); + break; + default: + unreachable("invalid type"); + } + } + break; + + case ir_quadop_vector: + for (unsigned c = 0; c < this->type->vector_elements; c++) { + switch (this->type->base_type) { + case GLSL_TYPE_UINT: + data.u[c] = op[c]->value.u[0]; + break; + case GLSL_TYPE_INT: + data.i[c] = op[c]->value.i[0]; + break; + case GLSL_TYPE_FLOAT: + data.f[c] = op[c]->value.f[0]; + break; + case GLSL_TYPE_DOUBLE: + data.d[c] = op[c]->value.d[0]; + break; + case GLSL_TYPE_UINT64: + data.u64[c] = op[c]->value.u64[0]; + break; + case GLSL_TYPE_INT64: + data.i64[c] = op[c]->value.i64[0]; + break; + case GLSL_TYPE_BOOL: + data.b[c] = op[c]->value.b[0]; + break; + default: + unreachable("invalid type"); + } + } + break; + + default: + /* FINISHME: Should handle all expression types. */ + return NULL; + } + diff --git a/prebuilt-intermediates/glsl/ir_expression_operation_strings.h b/prebuilt-intermediates/glsl/ir_expression_operation_strings.h new file mode 100644 index 00000000000..65a00e69791 --- /dev/null +++ b/prebuilt-intermediates/glsl/ir_expression_operation_strings.h @@ -0,0 +1,308 @@ +/* + * Copyright (C) 2010 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +const char *const ir_expression_operation_strings[] = { + "~", + "!", + "neg", + "abs", + "sign", + "rcp", + "rsq", + "sqrt", + "exp", + "log", + "exp2", + "log2", + "f2i", + "f2u", + "i2f", + "f2b", + "b2f", + "i2b", + "b2i", + "u2f", + "i2u", + "u2i", + "d2f", + "f2d", + "d2i", + "i2d", + "d2u", + "u2d", + "d2b", + "bitcast_i2f", + "bitcast_f2i", + "bitcast_u2f", + "bitcast_f2u", + "bitcast_u642d", + "bitcast_i642d", + "bitcast_d2u64", + "bitcast_d2i64", + "i642i", + "u642i", + "i642u", + "u642u", + "i642b", + "i642f", + "u642f", + "i642d", + "u642d", + "i2i64", + "u2i64", + "b2i64", + "f2i64", + "d2i64", + "i2u64", + "u2u64", + "f2u64", + "d2u64", + "u642i64", + "i642u64", + "trunc", + "ceil", + "floor", + "fract", + "round_even", + "sin", + "cos", + "dFdx", + "dFdxCoarse", + "dFdxFine", + "dFdy", + "dFdyCoarse", + "dFdyFine", + "packSnorm2x16", + "packSnorm4x8", + "packUnorm2x16", + "packUnorm4x8", + "packHalf2x16", + "unpackSnorm2x16", + "unpackSnorm4x8", + "unpackUnorm2x16", + "unpackUnorm4x8", + "unpackHalf2x16", + "bitfield_reverse", + "bit_count", + "find_msb", + "find_lsb", + "sat", + "packDouble2x32", + "unpackDouble2x32", + "packSampler2x32", + "packImage2x32", + "unpackSampler2x32", + "unpackImage2x32", + "frexp_sig", + "frexp_exp", + "noise", + "subroutine_to_int", + "interpolate_at_centroid", + "get_buffer_size", + "ssbo_unsized_array_length", + "packInt2x32", + "packUint2x32", + "unpackInt2x32", + "unpackUint2x32", + "+", + "-", + "*", + "imul_high", + "/", + "carry", + "borrow", + "%", + "<", + ">=", + "==", + "!=", + "all_equal", + "any_nequal", + "<<", + ">>", + "&", + "^", + "|", + "&&", + "^^", + "||", + "dot", + "min", + "max", + "pow", + "ubo_load", + "ldexp", + "vector_extract", + "interpolate_at_offset", + "interpolate_at_sample", + "fma", + "lrp", + "csel", + "bitfield_extract", + "vector_insert", + "bitfield_insert", + "vector", +}; + +const char *const ir_expression_operation_enum_strings[] = { + "bit_not", + "logic_not", + "neg", + "abs", + "sign", + "rcp", + "rsq", + "sqrt", + "exp", + "log", + "exp2", + "log2", + "f2i", + "f2u", + "i2f", + "f2b", + "b2f", + "i2b", + "b2i", + "u2f", + "i2u", + "u2i", + "d2f", + "f2d", + "d2i", + "i2d", + "d2u", + "u2d", + "d2b", + "bitcast_i2f", + "bitcast_f2i", + "bitcast_u2f", + "bitcast_f2u", + "bitcast_u642d", + "bitcast_i642d", + "bitcast_d2u64", + "bitcast_d2i64", + "i642i", + "u642i", + "i642u", + "u642u", + "i642b", + "i642f", + "u642f", + "i642d", + "u642d", + "i2i64", + "u2i64", + "b2i64", + "f2i64", + "d2i64", + "i2u64", + "u2u64", + "f2u64", + "d2u64", + "u642i64", + "i642u64", + "trunc", + "ceil", + "floor", + "fract", + "round_even", + "sin", + "cos", + "dFdx", + "dFdx_coarse", + "dFdx_fine", + "dFdy", + "dFdy_coarse", + "dFdy_fine", + "pack_snorm_2x16", + "pack_snorm_4x8", + "pack_unorm_2x16", + "pack_unorm_4x8", + "pack_half_2x16", + "unpack_snorm_2x16", + "unpack_snorm_4x8", + "unpack_unorm_2x16", + "unpack_unorm_4x8", + "unpack_half_2x16", + "bitfield_reverse", + "bit_count", + "find_msb", + "find_lsb", + "saturate", + "pack_double_2x32", + "unpack_double_2x32", + "pack_sampler_2x32", + "pack_image_2x32", + "unpack_sampler_2x32", + "unpack_image_2x32", + "frexp_sig", + "frexp_exp", + "noise", + "subroutine_to_int", + "interpolate_at_centroid", + "get_buffer_size", + "ssbo_unsized_array_length", + "pack_int_2x32", + "pack_uint_2x32", + "unpack_int_2x32", + "unpack_uint_2x32", + "add", + "sub", + "mul", + "imul_high", + "div", + "carry", + "borrow", + "mod", + "less", + "gequal", + "equal", + "nequal", + "all_equal", + "any_nequal", + "lshift", + "rshift", + "bit_and", + "bit_xor", + "bit_or", + "logic_and", + "logic_xor", + "logic_or", + "dot", + "min", + "max", + "pow", + "ubo_load", + "ldexp", + "vector_extract", + "interpolate_at_offset", + "interpolate_at_sample", + "fma", + "lrp", + "csel", + "bitfield_extract", + "vector_insert", + "bitfield_insert", + "vector", +}; diff --git a/prebuilt-intermediates/i965_dri_intermediates/brw_oa_metrics.c b/prebuilt-intermediates/i965_dri_intermediates/brw_oa_metrics.c new file mode 100644 index 00000000000..e0221df86fe --- /dev/null +++ b/prebuilt-intermediates/i965_dri_intermediates/brw_oa_metrics.c @@ -0,0 +1,150862 @@ +/* Autogenerated file, DO NOT EDIT manually! generated by brw_oa.py + * + * Copyright (c) 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#include +#include + +#include "util/hash_table.h" + +#include "brw_oa_metrics.h" +#include "brw_context.h" +#include "brw_performance_query_metrics.h" + + +#define MIN(a, b) ((a < b) ? (a) : (b)) +#define MAX(a, b) ((a > b) ? (a) : (b)) + + + +/* Render Metrics Basic Gen7.5 :: GPU Core Clocks */ +static uint64_t +hsw__render_basic__gpu_core_clocks__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 2 READ */ + uint64_t tmp0 = accumulator[query->c_offset + 2]; + + return tmp0; +} + +/* Render Metrics Basic Gen7.5 :: EU Active */ +static float +hsw__render_basic__eu_active__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 0 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 0]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__render_basic__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Render Metrics Basic Gen7.5 :: TES EU Stall */ +static float +hsw__render_basic__ds_eu_stall__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 13 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 13]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__render_basic__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Render Metrics Basic Gen7.5 :: Alpha Test Fails */ +static uint64_t +hsw__render_basic__alpha_test_fails__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 37 READ */ + uint64_t tmp0 = accumulator[query->a_offset + 37]; + + return tmp0; +} + +/* Render Metrics Basic Gen7.5 :: Sampler 1 Bottleneck */ +static float +hsw__render_basic__sampler1_bottleneck__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 3 READ 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->b_offset + 3]; + uint64_t tmp1 = tmp0 * 100; + double tmp2 = tmp1; + double tmp3 = hsw__render_basic__gpu_core_clocks__read(brw, query, accumulator); + double tmp4 = tmp3 ? tmp2 / tmp3 : 0; + + return tmp4; +} + +/* Render Metrics Basic Gen7.5 :: TES Threads Dispatched */ +static uint64_t +hsw__render_basic__ds_threads__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 15 READ */ + uint64_t tmp0 = accumulator[query->a_offset + 15]; + + return tmp0; +} + +/* Render Metrics Basic Gen7.5 :: TES AVG Active per Thread */ +static uint64_t +hsw__render_basic__ds_eu_active_per_thread__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 12 READ $DsThreads UDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 12]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = hsw__render_basic__ds_threads__read(brw, query, accumulator); + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + + return tmp3; +} + +/* Render Metrics Basic Gen7.5 :: GS Threads Dispatched */ +static uint64_t +hsw__render_basic__gs_threads__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 25 READ */ + uint64_t tmp0 = accumulator[query->a_offset + 25]; + + return tmp0; +} + +/* Render Metrics Basic Gen7.5 :: GS EU Stall */ +static float +hsw__render_basic__gs_eu_stall__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 23 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 23]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__render_basic__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Render Metrics Basic Gen7.5 :: CS EU Active */ +static float +hsw__render_basic__cs_eu_active__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 17 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 17]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__render_basic__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Render Metrics Basic Gen7.5 :: VS EU Active */ +static float +hsw__render_basic__vs_eu_active__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 2 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 2]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__render_basic__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Render Metrics Basic Gen7.5 :: TCS EU Active */ +static float +hsw__render_basic__hs_eu_active__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 7 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 7]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__render_basic__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Render Metrics Basic Gen7.5 :: TES EU Active */ +static float +hsw__render_basic__ds_eu_active__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 12 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 12]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__render_basic__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Render Metrics Basic Gen7.5 :: GS EU Active */ +static float +hsw__render_basic__gs_eu_active__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 22 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 22]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__render_basic__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Render Metrics Basic Gen7.5 :: FS EU Active */ +static float +hsw__render_basic__ps_eu_active__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 27 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 27]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__render_basic__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Render Metrics Basic Gen7.5 :: CS EU Stall */ +static float +hsw__render_basic__cs_eu_stall__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 18 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 18]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__render_basic__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Render Metrics Basic Gen7.5 :: EU Stall */ +static float +hsw__render_basic__eu_stall__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 1 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 1]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__render_basic__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Render Metrics Basic Gen7.5 :: VS EU Stall */ +static float +hsw__render_basic__vs_eu_stall__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 3 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 3]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__render_basic__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Render Metrics Basic Gen7.5 :: TCS EU Stall */ +static float +hsw__render_basic__hs_eu_stall__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 8 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 8]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__render_basic__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Render Metrics Basic Gen7.5 :: FS EU Stall */ +static float +hsw__render_basic__ps_eu_stall__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 28 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 28]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__render_basic__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Render Metrics Basic Gen7.5 :: GPU Time Elapsed */ +static uint64_t +hsw__render_basic__gpu_time__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: GPU_TIME 0 READ 1000000000 UMUL $GpuTimestampFrequency UDIV */ + uint64_t tmp0 = accumulator[query->gpu_time_offset + 0]; + uint64_t tmp1 = tmp0 * 1000000000; + uint64_t tmp2 = tmp1; + uint64_t tmp3 = brw->perfquery.sys_vars.timestamp_frequency; + uint64_t tmp4 = tmp3 ? tmp2 / tmp3 : 0; + + return tmp4; +} + +/* Render Metrics Basic Gen7.5 :: CS Duration */ +static uint64_t +hsw__render_basic__cs_duration__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 17 READ A 0 READ UMUL A 2 READ A 7 READ UADD A 12 READ UADD A 17 READ UADD A 22 READ UADD A 27 READ UADD UDIV A 18 READ A 1 READ UMUL A 3 READ A 8 READ UADD A 13 READ UADD A 18 READ UADD A 23 READ UADD A 28 READ UADD UDIV UADD $GpuTime UMUL $GpuCoreClocks $EuCoresTotalCount UMUL 1000 UMUL UDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 17]; + uint64_t tmp1 = accumulator[query->a_offset + 0]; + uint64_t tmp2 = tmp0 * tmp1; + uint64_t tmp3 = accumulator[query->a_offset + 2]; + uint64_t tmp4 = accumulator[query->a_offset + 7]; + uint64_t tmp5 = tmp3 + tmp4; + uint64_t tmp6 = accumulator[query->a_offset + 12]; + uint64_t tmp7 = tmp5 + tmp6; + uint64_t tmp8 = accumulator[query->a_offset + 17]; + uint64_t tmp9 = tmp7 + tmp8; + uint64_t tmp10 = accumulator[query->a_offset + 22]; + uint64_t tmp11 = tmp9 + tmp10; + uint64_t tmp12 = accumulator[query->a_offset + 27]; + uint64_t tmp13 = tmp11 + tmp12; + uint64_t tmp14 = tmp2; + uint64_t tmp15 = tmp13; + uint64_t tmp16 = tmp15 ? tmp14 / tmp15 : 0; + uint64_t tmp17 = accumulator[query->a_offset + 18]; + uint64_t tmp18 = accumulator[query->a_offset + 1]; + uint64_t tmp19 = tmp17 * tmp18; + uint64_t tmp20 = accumulator[query->a_offset + 3]; + uint64_t tmp21 = accumulator[query->a_offset + 8]; + uint64_t tmp22 = tmp20 + tmp21; + uint64_t tmp23 = accumulator[query->a_offset + 13]; + uint64_t tmp24 = tmp22 + tmp23; + uint64_t tmp25 = accumulator[query->a_offset + 18]; + uint64_t tmp26 = tmp24 + tmp25; + uint64_t tmp27 = accumulator[query->a_offset + 23]; + uint64_t tmp28 = tmp26 + tmp27; + uint64_t tmp29 = accumulator[query->a_offset + 28]; + uint64_t tmp30 = tmp28 + tmp29; + uint64_t tmp31 = tmp19; + uint64_t tmp32 = tmp30; + uint64_t tmp33 = tmp32 ? tmp31 / tmp32 : 0; + uint64_t tmp34 = tmp16 + tmp33; + uint64_t tmp35 = tmp34 * hsw__render_basic__gpu_time__read(brw, query, accumulator); + uint64_t tmp36 = hsw__render_basic__gpu_core_clocks__read(brw, query, accumulator) * brw->perfquery.sys_vars.n_eus; + uint64_t tmp37 = tmp36 * 1000; + uint64_t tmp38 = tmp35; + uint64_t tmp39 = tmp37; + uint64_t tmp40 = tmp39 ? tmp38 / tmp39 : 0; + + return tmp40; +} + +/* Render Metrics Basic Gen7.5 :: VS Threads Dispatched */ +static uint64_t +hsw__render_basic__vs_threads__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 5 READ */ + uint64_t tmp0 = accumulator[query->a_offset + 5]; + + return tmp0; +} + +/* Render Metrics Basic Gen7.5 :: FS Threads Dispatched */ +static uint64_t +hsw__render_basic__ps_threads__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 30 READ */ + uint64_t tmp0 = accumulator[query->a_offset + 30]; + + return tmp0; +} + +/* Render Metrics Basic Gen7.5 :: Sampler 0 Busy */ +static float +hsw__render_basic__sampler0_busy__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 0 READ 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->b_offset + 0]; + uint64_t tmp1 = tmp0 * 100; + double tmp2 = tmp1; + double tmp3 = hsw__render_basic__gpu_core_clocks__read(brw, query, accumulator); + double tmp4 = tmp3 ? tmp2 / tmp3 : 0; + + return tmp4; +} + +/* Render Metrics Basic Gen7.5 :: Sampler 1 Busy */ +static float +hsw__render_basic__sampler1_busy__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 1 READ 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->b_offset + 1]; + uint64_t tmp1 = tmp0 * 100; + double tmp2 = tmp1; + double tmp3 = hsw__render_basic__gpu_core_clocks__read(brw, query, accumulator); + double tmp4 = tmp3 ? tmp2 / tmp3 : 0; + + return tmp4; +} + +/* Render Metrics Basic Gen7.5 :: Samplers Busy */ +static float +hsw__render_basic__samplers_busy__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 0 READ B 1 READ UADD $GpuCoreClocks FDIV 2 FDIV 100 FMUL */ + uint64_t tmp0 = accumulator[query->b_offset + 0]; + uint64_t tmp1 = accumulator[query->b_offset + 1]; + uint64_t tmp2 = tmp0 + tmp1; + double tmp3 = tmp2; + double tmp4 = hsw__render_basic__gpu_core_clocks__read(brw, query, accumulator); + double tmp5 = tmp4 ? tmp3 / tmp4 : 0; + double tmp6 = tmp5; + double tmp7 = 2; + double tmp8 = tmp7 ? tmp6 / tmp7 : 0; + double tmp9 = tmp8 * 100; + + return tmp9; +} + +/* Render Metrics Basic Gen7.5 :: TES Duration */ +static uint64_t +hsw__render_basic__ds_duration__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 12 READ A 0 READ UMUL A 2 READ A 7 READ UADD A 12 READ UADD A 17 READ UADD A 22 READ UADD A 27 READ UADD UDIV A 13 READ A 1 READ UMUL A 3 READ A 8 READ UADD A 13 READ UADD A 18 READ UADD A 23 READ UADD A 28 READ UADD UDIV UADD $GpuTime UMUL $GpuCoreClocks $EuCoresTotalCount UMUL 1000 UMUL UDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 12]; + uint64_t tmp1 = accumulator[query->a_offset + 0]; + uint64_t tmp2 = tmp0 * tmp1; + uint64_t tmp3 = accumulator[query->a_offset + 2]; + uint64_t tmp4 = accumulator[query->a_offset + 7]; + uint64_t tmp5 = tmp3 + tmp4; + uint64_t tmp6 = accumulator[query->a_offset + 12]; + uint64_t tmp7 = tmp5 + tmp6; + uint64_t tmp8 = accumulator[query->a_offset + 17]; + uint64_t tmp9 = tmp7 + tmp8; + uint64_t tmp10 = accumulator[query->a_offset + 22]; + uint64_t tmp11 = tmp9 + tmp10; + uint64_t tmp12 = accumulator[query->a_offset + 27]; + uint64_t tmp13 = tmp11 + tmp12; + uint64_t tmp14 = tmp2; + uint64_t tmp15 = tmp13; + uint64_t tmp16 = tmp15 ? tmp14 / tmp15 : 0; + uint64_t tmp17 = accumulator[query->a_offset + 13]; + uint64_t tmp18 = accumulator[query->a_offset + 1]; + uint64_t tmp19 = tmp17 * tmp18; + uint64_t tmp20 = accumulator[query->a_offset + 3]; + uint64_t tmp21 = accumulator[query->a_offset + 8]; + uint64_t tmp22 = tmp20 + tmp21; + uint64_t tmp23 = accumulator[query->a_offset + 13]; + uint64_t tmp24 = tmp22 + tmp23; + uint64_t tmp25 = accumulator[query->a_offset + 18]; + uint64_t tmp26 = tmp24 + tmp25; + uint64_t tmp27 = accumulator[query->a_offset + 23]; + uint64_t tmp28 = tmp26 + tmp27; + uint64_t tmp29 = accumulator[query->a_offset + 28]; + uint64_t tmp30 = tmp28 + tmp29; + uint64_t tmp31 = tmp19; + uint64_t tmp32 = tmp30; + uint64_t tmp33 = tmp32 ? tmp31 / tmp32 : 0; + uint64_t tmp34 = tmp16 + tmp33; + uint64_t tmp35 = tmp34 * hsw__render_basic__gpu_time__read(brw, query, accumulator); + uint64_t tmp36 = hsw__render_basic__gpu_core_clocks__read(brw, query, accumulator) * brw->perfquery.sys_vars.n_eus; + uint64_t tmp37 = tmp36 * 1000; + uint64_t tmp38 = tmp35; + uint64_t tmp39 = tmp37; + uint64_t tmp40 = tmp39 ? tmp38 / tmp39 : 0; + + return tmp40; +} + +/* Render Metrics Basic Gen7.5 :: GTI Fixed Pipe Throughput */ +static uint64_t +hsw__render_basic__gti_vf_throughput__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 1 READ 64 UMUL */ + uint64_t tmp0 = accumulator[query->c_offset + 1]; + uint64_t tmp1 = tmp0 * 64; + + return tmp1; +} + +/* Render Metrics Basic Gen7.5 :: GTI Read Throughput */ +static uint64_t +hsw__render_basic__gti_read_throughput__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 6 READ 128 UMUL */ + uint64_t tmp0 = accumulator[query->c_offset + 6]; + uint64_t tmp1 = tmp0 * 128; + + return tmp1; +} + +/* Render Metrics Basic Gen7.5 :: CS Threads Dispatched */ +static uint64_t +hsw__render_basic__cs_threads__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 20 READ */ + uint64_t tmp0 = accumulator[query->a_offset + 20]; + + return tmp0; +} + +/* Render Metrics Basic Gen7.5 :: CS AVG Active per Thread */ +static uint64_t +hsw__render_basic__cs_eu_active_per_thread__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 17 READ $CsThreads UDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 17]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = hsw__render_basic__cs_threads__read(brw, query, accumulator); + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + + return tmp3; +} + +/* Render Metrics Basic Gen7.5 :: Sampler 0 Bottleneck */ +static float +hsw__render_basic__sampler0_bottleneck__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 2 READ 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->b_offset + 2]; + uint64_t tmp1 = tmp0 * 100; + double tmp2 = tmp1; + double tmp3 = hsw__render_basic__gpu_core_clocks__read(brw, query, accumulator); + double tmp4 = tmp3 ? tmp2 / tmp3 : 0; + + return tmp4; +} + +/* Render Metrics Basic Gen7.5 :: GS AVG Stall per Thread */ +static uint64_t +hsw__render_basic__gs_eu_stall_per_thread__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 23 READ $GsThreads UDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 23]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = hsw__render_basic__gs_threads__read(brw, query, accumulator); + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + + return tmp3; +} + +/* Render Metrics Basic Gen7.5 :: Sampler 0 Texels LOD0 */ +static uint64_t +hsw__render_basic__sampler0_texels__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 4 READ 4 UMUL */ + uint64_t tmp0 = accumulator[query->b_offset + 4]; + uint64_t tmp1 = tmp0 * 4; + + return tmp1; +} + +/* Render Metrics Basic Gen7.5 :: Sampler 1 Texels LOD0 */ +static uint64_t +hsw__render_basic__sampler1_texels__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 5 READ 4 UMUL */ + uint64_t tmp0 = accumulator[query->b_offset + 5]; + uint64_t tmp1 = tmp0 * 4; + + return tmp1; +} + +/* Render Metrics Basic Gen7.5 :: Sampler Texels LOD0 */ +static uint64_t +hsw__render_basic__sampler_texels__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $Sampler0Texels $Sampler1Texels UADD $EuSlicesTotalCount UMUL */ + uint64_t tmp0 = hsw__render_basic__sampler0_texels__read(brw, query, accumulator) + hsw__render_basic__sampler1_texels__read(brw, query, accumulator); + uint64_t tmp1 = tmp0 * brw->perfquery.sys_vars.n_eu_slices; + + return tmp1; +} + +/* Render Metrics Basic Gen7.5 :: GS Duration */ +static uint64_t +hsw__render_basic__gs_duration__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 22 READ A 0 READ UMUL A 2 READ A 7 READ UADD A 12 READ UADD A 17 READ UADD A 22 READ UADD A 27 READ UADD UDIV A 23 READ A 1 READ UMUL A 3 READ A 8 READ UADD A 13 READ UADD A 18 READ UADD A 23 READ UADD A 28 READ UADD UDIV UADD $GpuTime UMUL $GpuCoreClocks $EuCoresTotalCount UMUL 1000 UMUL UDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 22]; + uint64_t tmp1 = accumulator[query->a_offset + 0]; + uint64_t tmp2 = tmp0 * tmp1; + uint64_t tmp3 = accumulator[query->a_offset + 2]; + uint64_t tmp4 = accumulator[query->a_offset + 7]; + uint64_t tmp5 = tmp3 + tmp4; + uint64_t tmp6 = accumulator[query->a_offset + 12]; + uint64_t tmp7 = tmp5 + tmp6; + uint64_t tmp8 = accumulator[query->a_offset + 17]; + uint64_t tmp9 = tmp7 + tmp8; + uint64_t tmp10 = accumulator[query->a_offset + 22]; + uint64_t tmp11 = tmp9 + tmp10; + uint64_t tmp12 = accumulator[query->a_offset + 27]; + uint64_t tmp13 = tmp11 + tmp12; + uint64_t tmp14 = tmp2; + uint64_t tmp15 = tmp13; + uint64_t tmp16 = tmp15 ? tmp14 / tmp15 : 0; + uint64_t tmp17 = accumulator[query->a_offset + 23]; + uint64_t tmp18 = accumulator[query->a_offset + 1]; + uint64_t tmp19 = tmp17 * tmp18; + uint64_t tmp20 = accumulator[query->a_offset + 3]; + uint64_t tmp21 = accumulator[query->a_offset + 8]; + uint64_t tmp22 = tmp20 + tmp21; + uint64_t tmp23 = accumulator[query->a_offset + 13]; + uint64_t tmp24 = tmp22 + tmp23; + uint64_t tmp25 = accumulator[query->a_offset + 18]; + uint64_t tmp26 = tmp24 + tmp25; + uint64_t tmp27 = accumulator[query->a_offset + 23]; + uint64_t tmp28 = tmp26 + tmp27; + uint64_t tmp29 = accumulator[query->a_offset + 28]; + uint64_t tmp30 = tmp28 + tmp29; + uint64_t tmp31 = tmp19; + uint64_t tmp32 = tmp30; + uint64_t tmp33 = tmp32 ? tmp31 / tmp32 : 0; + uint64_t tmp34 = tmp16 + tmp33; + uint64_t tmp35 = tmp34 * hsw__render_basic__gpu_time__read(brw, query, accumulator); + uint64_t tmp36 = hsw__render_basic__gpu_core_clocks__read(brw, query, accumulator) * brw->perfquery.sys_vars.n_eus; + uint64_t tmp37 = tmp36 * 1000; + uint64_t tmp38 = tmp35; + uint64_t tmp39 = tmp37; + uint64_t tmp40 = tmp39 ? tmp38 / tmp39 : 0; + + return tmp40; +} + +/* Render Metrics Basic Gen7.5 :: AVG GPU Core Frequency */ +static uint64_t +hsw__render_basic__avg_gpu_core_frequency__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $GpuCoreClocks 1000000000 UMUL $GpuTime UDIV */ + uint64_t tmp0 = hsw__render_basic__gpu_core_clocks__read(brw, query, accumulator) * 1000000000; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = hsw__render_basic__gpu_time__read(brw, query, accumulator); + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + + return tmp3; +} + +/* Render Metrics Basic Gen7.5 :: AVG GPU Core Frequency */ +static uint64_t +hsw__render_basic__avg_gpu_core_frequency__max(struct brw_context *brw) +{ + /* RPN equation: $GpuMaxFrequency */ + + return brw->perfquery.sys_vars.gt_max_freq; +} + +/* Render Metrics Basic Gen7.5 :: EU Idle */ +static float +hsw__render_basic__eu_idle__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: 100 $EuActive $EuStall FADD FSUB */ + double tmp0 = hsw__render_basic__eu_active__read(brw, query, accumulator) + hsw__render_basic__eu_stall__read(brw, query, accumulator); + double tmp1 = 100 - tmp0; + + return tmp1; +} + +/* Render Metrics Basic Gen7.5 :: GTI Depth Throughput */ +static uint64_t +hsw__render_basic__gti_depth_throughput__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 0 READ 64 UMUL */ + uint64_t tmp0 = accumulator[query->c_offset + 0]; + uint64_t tmp1 = tmp0 * 64; + + return tmp1; +} + +/* Render Metrics Basic Gen7.5 :: GTI Write Throughput */ +static uint64_t +hsw__render_basic__gti_write_throughput__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 7 READ 64 UMUL */ + uint64_t tmp0 = accumulator[query->c_offset + 7]; + uint64_t tmp1 = tmp0 * 64; + + return tmp1; +} + +/* Render Metrics Basic Gen7.5 :: FS AVG Stall per Thread */ +static uint64_t +hsw__render_basic__ps_eu_stall_per_thread__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 28 READ $PsThreads UDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 28]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = hsw__render_basic__ps_threads__read(brw, query, accumulator); + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + + return tmp3; +} + +/* Render Metrics Basic Gen7.5 :: GTI L3 Throughput */ +static uint64_t +hsw__render_basic__gti_l3_throughput__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 4 READ 64 UMUL */ + uint64_t tmp0 = accumulator[query->c_offset + 4]; + uint64_t tmp1 = tmp0 * 64; + + return tmp1; +} + +/* Render Metrics Basic Gen7.5 :: VS AVG Stall per Thread */ +static uint64_t +hsw__render_basic__vs_eu_stall_per_thread__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 3 READ $VsThreads UDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 3]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = hsw__render_basic__vs_threads__read(brw, query, accumulator); + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + + return tmp3; +} + +/* Render Metrics Basic Gen7.5 :: Samples Blended */ +static uint64_t +hsw__render_basic__samples_blended__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 5 READ $EuSlicesTotalCount 4 UMUL UMUL */ + uint64_t tmp0 = accumulator[query->c_offset + 5]; + uint64_t tmp1 = brw->perfquery.sys_vars.n_eu_slices * 4; + uint64_t tmp2 = tmp0 * tmp1; + + return tmp2; +} + +/* Render Metrics Basic Gen7.5 :: GPU Busy */ +static float +hsw__render_basic__gpu_busy__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 41 READ 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 41]; + uint64_t tmp1 = tmp0 * 100; + double tmp2 = tmp1; + double tmp3 = hsw__render_basic__gpu_core_clocks__read(brw, query, accumulator); + double tmp4 = tmp3 ? tmp2 / tmp3 : 0; + + return tmp4; +} + +/* Render Metrics Basic Gen7.5 :: FS AVG Active per Thread */ +static uint64_t +hsw__render_basic__ps_eu_active_per_thread__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 27 READ $PsThreads UDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 27]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = hsw__render_basic__ps_threads__read(brw, query, accumulator); + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + + return tmp3; +} + +/* Render Metrics Basic Gen7.5 :: Early Depth Test Fails */ +static uint64_t +hsw__render_basic__early_depth_test_fails__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 35 READ */ + uint64_t tmp0 = accumulator[query->a_offset + 35]; + + return tmp0; +} + +/* Render Metrics Basic Gen7.5 :: TCS Duration */ +static uint64_t +hsw__render_basic__hs_duration__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 7 READ A 0 READ UMUL A 2 READ A 7 READ UADD A 12 READ UADD A 17 READ UADD A 22 READ UADD A 27 READ UADD UDIV A 8 READ A 1 READ UMUL A 3 READ A 8 READ UADD A 13 READ UADD A 18 READ UADD A 23 READ UADD A 28 READ UADD UDIV UADD $GpuTime UMUL $GpuCoreClocks $EuCoresTotalCount UMUL 1000 UMUL UDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 7]; + uint64_t tmp1 = accumulator[query->a_offset + 0]; + uint64_t tmp2 = tmp0 * tmp1; + uint64_t tmp3 = accumulator[query->a_offset + 2]; + uint64_t tmp4 = accumulator[query->a_offset + 7]; + uint64_t tmp5 = tmp3 + tmp4; + uint64_t tmp6 = accumulator[query->a_offset + 12]; + uint64_t tmp7 = tmp5 + tmp6; + uint64_t tmp8 = accumulator[query->a_offset + 17]; + uint64_t tmp9 = tmp7 + tmp8; + uint64_t tmp10 = accumulator[query->a_offset + 22]; + uint64_t tmp11 = tmp9 + tmp10; + uint64_t tmp12 = accumulator[query->a_offset + 27]; + uint64_t tmp13 = tmp11 + tmp12; + uint64_t tmp14 = tmp2; + uint64_t tmp15 = tmp13; + uint64_t tmp16 = tmp15 ? tmp14 / tmp15 : 0; + uint64_t tmp17 = accumulator[query->a_offset + 8]; + uint64_t tmp18 = accumulator[query->a_offset + 1]; + uint64_t tmp19 = tmp17 * tmp18; + uint64_t tmp20 = accumulator[query->a_offset + 3]; + uint64_t tmp21 = accumulator[query->a_offset + 8]; + uint64_t tmp22 = tmp20 + tmp21; + uint64_t tmp23 = accumulator[query->a_offset + 13]; + uint64_t tmp24 = tmp22 + tmp23; + uint64_t tmp25 = accumulator[query->a_offset + 18]; + uint64_t tmp26 = tmp24 + tmp25; + uint64_t tmp27 = accumulator[query->a_offset + 23]; + uint64_t tmp28 = tmp26 + tmp27; + uint64_t tmp29 = accumulator[query->a_offset + 28]; + uint64_t tmp30 = tmp28 + tmp29; + uint64_t tmp31 = tmp19; + uint64_t tmp32 = tmp30; + uint64_t tmp33 = tmp32 ? tmp31 / tmp32 : 0; + uint64_t tmp34 = tmp16 + tmp33; + uint64_t tmp35 = tmp34 * hsw__render_basic__gpu_time__read(brw, query, accumulator); + uint64_t tmp36 = hsw__render_basic__gpu_core_clocks__read(brw, query, accumulator) * brw->perfquery.sys_vars.n_eus; + uint64_t tmp37 = tmp36 * 1000; + uint64_t tmp38 = tmp35; + uint64_t tmp39 = tmp37; + uint64_t tmp40 = tmp39 ? tmp38 / tmp39 : 0; + + return tmp40; +} + +/* Render Metrics Basic Gen7.5 :: TES AVG Stall per Thread */ +static uint64_t +hsw__render_basic__ds_eu_stall_per_thread__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 13 READ $DsThreads UDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 13]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = hsw__render_basic__ds_threads__read(brw, query, accumulator); + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + + return tmp3; +} + +/* Render Metrics Basic Gen7.5 :: GS AVG Active per Thread */ +static uint64_t +hsw__render_basic__gs_eu_active_per_thread__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 22 READ $GsThreads UDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 22]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = hsw__render_basic__gs_threads__read(brw, query, accumulator); + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + + return tmp3; +} + +/* Render Metrics Basic Gen7.5 :: TCS Threads Dispatched */ +static uint64_t +hsw__render_basic__hs_threads__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 10 READ */ + uint64_t tmp0 = accumulator[query->a_offset + 10]; + + return tmp0; +} + +/* Render Metrics Basic Gen7.5 :: TCS AVG Stall per Thread */ +static uint64_t +hsw__render_basic__hs_eu_stall_per_thread__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 8 READ $HsThreads UDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 8]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = hsw__render_basic__hs_threads__read(brw, query, accumulator); + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + + return tmp3; +} + +/* Render Metrics Basic Gen7.5 :: Samples Killed in FS */ +static uint64_t +hsw__render_basic__samples_killed_in_ps__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 36 READ */ + uint64_t tmp0 = accumulator[query->a_offset + 36]; + + return tmp0; +} + +/* Render Metrics Basic Gen7.5 :: Late Depth Test Fails */ +static uint64_t +hsw__render_basic__post_ps_depth_test_fails__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 39 READ $SamplesKilledInPs USUB */ + uint64_t tmp0 = accumulator[query->a_offset + 39]; + uint64_t tmp1 = tmp0 - hsw__render_basic__samples_killed_in_ps__read(brw, query, accumulator); + + return tmp1; +} + +/* Render Metrics Basic Gen7.5 :: Sampler Bottleneck */ +static float +hsw__render_basic__sampler_bottleneck__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $Sampler0Bottleneck $Sampler1Bottleneck FMAX */ + double tmp0 = hsw__render_basic__sampler0_bottleneck__read(brw, query, accumulator); + double tmp1 = hsw__render_basic__sampler1_bottleneck__read(brw, query, accumulator); + double tmp2 = MAX(tmp0, tmp1); + + return tmp2; +} + +/* Render Metrics Basic Gen7.5 :: TCS AVG Active per Thread */ +static uint64_t +hsw__render_basic__hs_eu_active_per_thread__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 7 READ $HsThreads UDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 7]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = hsw__render_basic__hs_threads__read(brw, query, accumulator); + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + + return tmp3; +} + +/* Render Metrics Basic Gen7.5 :: FS Duration */ +static uint64_t +hsw__render_basic__ps_duration__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 27 READ A 0 READ UMUL A 2 READ A 7 READ UADD A 12 READ UADD A 17 READ UADD A 22 READ UADD A 27 READ UADD UDIV A 28 READ A 1 READ UMUL A 3 READ A 8 READ UADD A 13 READ UADD A 18 READ UADD A 23 READ UADD A 28 READ UADD UDIV UADD $GpuTime UMUL $GpuCoreClocks $EuCoresTotalCount UMUL 1000 UMUL UDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 27]; + uint64_t tmp1 = accumulator[query->a_offset + 0]; + uint64_t tmp2 = tmp0 * tmp1; + uint64_t tmp3 = accumulator[query->a_offset + 2]; + uint64_t tmp4 = accumulator[query->a_offset + 7]; + uint64_t tmp5 = tmp3 + tmp4; + uint64_t tmp6 = accumulator[query->a_offset + 12]; + uint64_t tmp7 = tmp5 + tmp6; + uint64_t tmp8 = accumulator[query->a_offset + 17]; + uint64_t tmp9 = tmp7 + tmp8; + uint64_t tmp10 = accumulator[query->a_offset + 22]; + uint64_t tmp11 = tmp9 + tmp10; + uint64_t tmp12 = accumulator[query->a_offset + 27]; + uint64_t tmp13 = tmp11 + tmp12; + uint64_t tmp14 = tmp2; + uint64_t tmp15 = tmp13; + uint64_t tmp16 = tmp15 ? tmp14 / tmp15 : 0; + uint64_t tmp17 = accumulator[query->a_offset + 28]; + uint64_t tmp18 = accumulator[query->a_offset + 1]; + uint64_t tmp19 = tmp17 * tmp18; + uint64_t tmp20 = accumulator[query->a_offset + 3]; + uint64_t tmp21 = accumulator[query->a_offset + 8]; + uint64_t tmp22 = tmp20 + tmp21; + uint64_t tmp23 = accumulator[query->a_offset + 13]; + uint64_t tmp24 = tmp22 + tmp23; + uint64_t tmp25 = accumulator[query->a_offset + 18]; + uint64_t tmp26 = tmp24 + tmp25; + uint64_t tmp27 = accumulator[query->a_offset + 23]; + uint64_t tmp28 = tmp26 + tmp27; + uint64_t tmp29 = accumulator[query->a_offset + 28]; + uint64_t tmp30 = tmp28 + tmp29; + uint64_t tmp31 = tmp19; + uint64_t tmp32 = tmp30; + uint64_t tmp33 = tmp32 ? tmp31 / tmp32 : 0; + uint64_t tmp34 = tmp16 + tmp33; + uint64_t tmp35 = tmp34 * hsw__render_basic__gpu_time__read(brw, query, accumulator); + uint64_t tmp36 = hsw__render_basic__gpu_core_clocks__read(brw, query, accumulator) * brw->perfquery.sys_vars.n_eus; + uint64_t tmp37 = tmp36 * 1000; + uint64_t tmp38 = tmp35; + uint64_t tmp39 = tmp37; + uint64_t tmp40 = tmp39 ? tmp38 / tmp39 : 0; + + return tmp40; +} + +/* Render Metrics Basic Gen7.5 :: Early Hi-Depth Test Fails */ +static uint64_t +hsw__render_basic__hi_depth_test_fails__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 33 READ */ + uint64_t tmp0 = accumulator[query->a_offset + 33]; + + return tmp0; +} + +/* Render Metrics Basic Gen7.5 :: CS AVG Stall per Thread */ +static uint64_t +hsw__render_basic__cs_eu_stall_per_thread__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 18 READ $CsThreads UDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 18]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = hsw__render_basic__cs_threads__read(brw, query, accumulator); + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + + return tmp3; +} + +/* Render Metrics Basic Gen7.5 :: Late Stencil Test Fails */ +static uint64_t +hsw__render_basic__post_ps_stencil_test_fails__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 38 READ */ + uint64_t tmp0 = accumulator[query->a_offset + 38]; + + return tmp0; +} + +/* Render Metrics Basic Gen7.5 :: GTI RCC Throughput */ +static uint64_t +hsw__render_basic__gti_rcc_throughput__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 3 READ 64 UMUL */ + uint64_t tmp0 = accumulator[query->c_offset + 3]; + uint64_t tmp1 = tmp0 * 64; + + return tmp1; +} + +/* Render Metrics Basic Gen7.5 :: L3 Sampler Throughput */ +static uint64_t +hsw__render_basic__l3_sampler_throughput__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 6 READ B 7 READ UADD 2 UMUL $EuSlicesTotalCount UMUL 64 UMUL */ + uint64_t tmp0 = accumulator[query->b_offset + 6]; + uint64_t tmp1 = accumulator[query->b_offset + 7]; + uint64_t tmp2 = tmp0 + tmp1; + uint64_t tmp3 = tmp2 * 2; + uint64_t tmp4 = tmp3 * brw->perfquery.sys_vars.n_eu_slices; + uint64_t tmp5 = tmp4 * 64; + + return tmp5; +} + +/* Render Metrics Basic Gen7.5 :: VS AVG Active per Thread */ +static uint64_t +hsw__render_basic__vs_eu_active_per_thread__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 2 READ $VsThreads UDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 2]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = hsw__render_basic__vs_threads__read(brw, query, accumulator); + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + + return tmp3; +} + +/* Render Metrics Basic Gen7.5 :: VS Duration */ +static uint64_t +hsw__render_basic__vs_duration__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 2 READ A 0 READ UMUL A 2 READ A 7 READ UADD A 12 READ UADD A 17 READ UADD A 22 READ UADD A 27 READ UADD UDIV A 3 READ A 1 READ UMUL A 3 READ A 8 READ UADD A 13 READ UADD A 18 READ UADD A 23 READ UADD A 28 READ UADD UDIV UADD $GpuTime UMUL $GpuCoreClocks $EuCoresTotalCount UMUL 1000 UMUL UDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 2]; + uint64_t tmp1 = accumulator[query->a_offset + 0]; + uint64_t tmp2 = tmp0 * tmp1; + uint64_t tmp3 = accumulator[query->a_offset + 2]; + uint64_t tmp4 = accumulator[query->a_offset + 7]; + uint64_t tmp5 = tmp3 + tmp4; + uint64_t tmp6 = accumulator[query->a_offset + 12]; + uint64_t tmp7 = tmp5 + tmp6; + uint64_t tmp8 = accumulator[query->a_offset + 17]; + uint64_t tmp9 = tmp7 + tmp8; + uint64_t tmp10 = accumulator[query->a_offset + 22]; + uint64_t tmp11 = tmp9 + tmp10; + uint64_t tmp12 = accumulator[query->a_offset + 27]; + uint64_t tmp13 = tmp11 + tmp12; + uint64_t tmp14 = tmp2; + uint64_t tmp15 = tmp13; + uint64_t tmp16 = tmp15 ? tmp14 / tmp15 : 0; + uint64_t tmp17 = accumulator[query->a_offset + 3]; + uint64_t tmp18 = accumulator[query->a_offset + 1]; + uint64_t tmp19 = tmp17 * tmp18; + uint64_t tmp20 = accumulator[query->a_offset + 3]; + uint64_t tmp21 = accumulator[query->a_offset + 8]; + uint64_t tmp22 = tmp20 + tmp21; + uint64_t tmp23 = accumulator[query->a_offset + 13]; + uint64_t tmp24 = tmp22 + tmp23; + uint64_t tmp25 = accumulator[query->a_offset + 18]; + uint64_t tmp26 = tmp24 + tmp25; + uint64_t tmp27 = accumulator[query->a_offset + 23]; + uint64_t tmp28 = tmp26 + tmp27; + uint64_t tmp29 = accumulator[query->a_offset + 28]; + uint64_t tmp30 = tmp28 + tmp29; + uint64_t tmp31 = tmp19; + uint64_t tmp32 = tmp30; + uint64_t tmp33 = tmp32 ? tmp31 / tmp32 : 0; + uint64_t tmp34 = tmp16 + tmp33; + uint64_t tmp35 = tmp34 * hsw__render_basic__gpu_time__read(brw, query, accumulator); + uint64_t tmp36 = hsw__render_basic__gpu_core_clocks__read(brw, query, accumulator) * brw->perfquery.sys_vars.n_eus; + uint64_t tmp37 = tmp36 * 1000; + uint64_t tmp38 = tmp35; + uint64_t tmp39 = tmp37; + uint64_t tmp40 = tmp39 ? tmp38 / tmp39 : 0; + + return tmp40; +} + +/* Render Metrics Basic Gen7.5 :: Samples Written */ +static uint64_t +hsw__render_basic__samples_written__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 40 READ */ + uint64_t tmp0 = accumulator[query->a_offset + 40]; + + return tmp0; +} + +/* Compute Metrics Basic Gen7.5 :: GPU Core Clocks */ +#define hsw__compute_basic__gpu_core_clocks__read \ + hsw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Basic Gen7.5 :: EU Active */ +#define hsw__compute_basic__eu_active__read \ + hsw__render_basic__eu_active__read + +/* Compute Metrics Basic Gen7.5 :: TES EU Stall */ +#define hsw__compute_basic__ds_eu_stall__read \ + hsw__render_basic__ds_eu_stall__read + +/* Compute Metrics Basic Gen7.5 :: Typed Bytes Written */ +static uint64_t +hsw__compute_basic__typed_bytes_written__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 6 READ B 7 READ UADD $EuSlicesTotalCount 64 UMUL UMUL */ + uint64_t tmp0 = accumulator[query->b_offset + 6]; + uint64_t tmp1 = accumulator[query->b_offset + 7]; + uint64_t tmp2 = tmp0 + tmp1; + uint64_t tmp3 = brw->perfquery.sys_vars.n_eu_slices * 64; + uint64_t tmp4 = tmp2 * tmp3; + + return tmp4; +} + +/* Compute Metrics Basic Gen7.5 :: Alpha Test Fails */ +#define hsw__compute_basic__alpha_test_fails__read \ + hsw__render_basic__alpha_test_fails__read + +/* Compute Metrics Basic Gen7.5 :: TCS Threads Dispatched */ +#define hsw__compute_basic__hs_threads__read \ + hsw__render_basic__hs_threads__read + +/* Compute Metrics Basic Gen7.5 :: TCS AVG Active per Thread */ +#define hsw__compute_basic__hs_eu_active_per_thread__read \ + hsw__render_basic__hs_eu_active_per_thread__read + +/* Compute Metrics Basic Gen7.5 :: GS Threads Dispatched */ +#define hsw__compute_basic__gs_threads__read \ + hsw__render_basic__gs_threads__read + +/* Compute Metrics Basic Gen7.5 :: GS EU Stall */ +#define hsw__compute_basic__gs_eu_stall__read \ + hsw__render_basic__gs_eu_stall__read + +/* Compute Metrics Basic Gen7.5 :: VS Threads Dispatched */ +#define hsw__compute_basic__vs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Compute Metrics Basic Gen7.5 :: FS Threads Dispatched */ +#define hsw__compute_basic__ps_threads__read \ + hsw__render_basic__ps_threads__read + +/* Compute Metrics Basic Gen7.5 :: CS Threads Dispatched */ +#define hsw__compute_basic__cs_threads__read \ + hsw__render_basic__cs_threads__read + +/* Compute Metrics Basic Gen7.5 :: CS AVG Active per Thread */ +#define hsw__compute_basic__cs_eu_active_per_thread__read \ + hsw__render_basic__cs_eu_active_per_thread__read + +/* Compute Metrics Basic Gen7.5 :: Untyped Bytes Read */ +static uint64_t +hsw__compute_basic__untyped_bytes_read__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 0 READ B 1 READ UADD $EuSlicesTotalCount 64 UMUL UMUL */ + uint64_t tmp0 = accumulator[query->b_offset + 0]; + uint64_t tmp1 = accumulator[query->b_offset + 1]; + uint64_t tmp2 = tmp0 + tmp1; + uint64_t tmp3 = brw->perfquery.sys_vars.n_eu_slices * 64; + uint64_t tmp4 = tmp2 * tmp3; + + return tmp4; +} + +/* Compute Metrics Basic Gen7.5 :: GS AVG Stall per Thread */ +#define hsw__compute_basic__gs_eu_stall_per_thread__read \ + hsw__render_basic__gs_eu_stall_per_thread__read + +/* Compute Metrics Basic Gen7.5 :: Typed Atomics */ +static uint64_t +hsw__compute_basic__typed_atomics__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 0 READ C 1 READ UADD $EuSlicesTotalCount UMUL */ + uint64_t tmp0 = accumulator[query->c_offset + 0]; + uint64_t tmp1 = accumulator[query->c_offset + 1]; + uint64_t tmp2 = tmp0 + tmp1; + uint64_t tmp3 = tmp2 * brw->perfquery.sys_vars.n_eu_slices; + + return tmp3; +} + +/* Compute Metrics Basic Gen7.5 :: GPU Time Elapsed */ +#define hsw__compute_basic__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics Basic Gen7.5 :: AVG GPU Core Frequency */ +#define hsw__compute_basic__avg_gpu_core_frequency__read \ + hsw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics Basic Gen7.5 :: AVG GPU Core Frequency */ +#define hsw__compute_basic__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics Basic Gen7.5 :: SLM Bytes Read */ +static uint64_t +hsw__compute_basic__slm_bytes_read__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 6 READ C 7 READ UADD $EuSlicesTotalCount 64 UMUL UMUL */ + uint64_t tmp0 = accumulator[query->c_offset + 6]; + uint64_t tmp1 = accumulator[query->c_offset + 7]; + uint64_t tmp2 = tmp0 + tmp1; + uint64_t tmp3 = brw->perfquery.sys_vars.n_eu_slices * 64; + uint64_t tmp4 = tmp2 * tmp3; + + return tmp4; +} + +/* Compute Metrics Basic Gen7.5 :: FS AVG Stall per Thread */ +#define hsw__compute_basic__ps_eu_stall_per_thread__read \ + hsw__render_basic__ps_eu_stall_per_thread__read + +/* Compute Metrics Basic Gen7.5 :: TES EU Active */ +#define hsw__compute_basic__ds_eu_active__read \ + hsw__render_basic__ds_eu_active__read + +/* Compute Metrics Basic Gen7.5 :: VS AVG Stall per Thread */ +#define hsw__compute_basic__vs_eu_stall_per_thread__read \ + hsw__render_basic__vs_eu_stall_per_thread__read + +/* Compute Metrics Basic Gen7.5 :: TCS EU Stall */ +#define hsw__compute_basic__hs_eu_stall__read \ + hsw__render_basic__hs_eu_stall__read + +/* Compute Metrics Basic Gen7.5 :: GPU Busy */ +#define hsw__compute_basic__gpu_busy__read \ + hsw__render_basic__gpu_busy__read + +/* Compute Metrics Basic Gen7.5 :: FS AVG Active per Thread */ +#define hsw__compute_basic__ps_eu_active_per_thread__read \ + hsw__render_basic__ps_eu_active_per_thread__read + +/* Compute Metrics Basic Gen7.5 :: Early Depth Test Fails */ +#define hsw__compute_basic__early_depth_test_fails__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Compute Metrics Basic Gen7.5 :: TES Threads Dispatched */ +#define hsw__compute_basic__ds_threads__read \ + hsw__render_basic__ds_threads__read + +/* Compute Metrics Basic Gen7.5 :: TES AVG Active per Thread */ +#define hsw__compute_basic__ds_eu_active_per_thread__read \ + hsw__render_basic__ds_eu_active_per_thread__read + +/* Compute Metrics Basic Gen7.5 :: GS EU Active */ +#define hsw__compute_basic__gs_eu_active__read \ + hsw__render_basic__gs_eu_active__read + +/* Compute Metrics Basic Gen7.5 :: FS EU Active */ +#define hsw__compute_basic__ps_eu_active__read \ + hsw__render_basic__ps_eu_active__read + +/* Compute Metrics Basic Gen7.5 :: TES AVG Stall per Thread */ +#define hsw__compute_basic__ds_eu_stall_per_thread__read \ + hsw__render_basic__ds_eu_stall_per_thread__read + +/* Compute Metrics Basic Gen7.5 :: GS AVG Active per Thread */ +#define hsw__compute_basic__gs_eu_active_per_thread__read \ + hsw__render_basic__gs_eu_active_per_thread__read + +/* Compute Metrics Basic Gen7.5 :: Untyped Writes */ +static uint64_t +hsw__compute_basic__untyped_bytes_written__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 2 READ B 3 READ UADD $EuSlicesTotalCount 64 UMUL UMUL */ + uint64_t tmp0 = accumulator[query->b_offset + 2]; + uint64_t tmp1 = accumulator[query->b_offset + 3]; + uint64_t tmp2 = tmp0 + tmp1; + uint64_t tmp3 = brw->perfquery.sys_vars.n_eu_slices * 64; + uint64_t tmp4 = tmp2 * tmp3; + + return tmp4; +} + +/* Compute Metrics Basic Gen7.5 :: SLM Bytes Written */ +static uint64_t +hsw__compute_basic__slm_bytes_written__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 4 READ C 5 READ UADD $EuSlicesTotalCount 64 UMUL UMUL */ + uint64_t tmp0 = accumulator[query->c_offset + 4]; + uint64_t tmp1 = accumulator[query->c_offset + 5]; + uint64_t tmp2 = tmp0 + tmp1; + uint64_t tmp3 = brw->perfquery.sys_vars.n_eu_slices * 64; + uint64_t tmp4 = tmp2 * tmp3; + + return tmp4; +} + +/* Compute Metrics Basic Gen7.5 :: TCS AVG Stall per Thread */ +#define hsw__compute_basic__hs_eu_stall_per_thread__read \ + hsw__render_basic__hs_eu_stall_per_thread__read + +/* Compute Metrics Basic Gen7.5 :: TCS EU Active */ +#define hsw__compute_basic__hs_eu_active__read \ + hsw__render_basic__hs_eu_active__read + +/* Compute Metrics Basic Gen7.5 :: Samples Killed in FS */ +#define hsw__compute_basic__samples_killed_in_ps__read \ + hsw__render_basic__samples_killed_in_ps__read + +/* Compute Metrics Basic Gen7.5 :: Late Depth Test Fails */ +#define hsw__compute_basic__post_ps_depth_test_fails__read \ + hsw__render_basic__post_ps_depth_test_fails__read + +/* Compute Metrics Basic Gen7.5 :: FS EU Stall */ +#define hsw__compute_basic__ps_eu_stall__read \ + hsw__render_basic__ps_eu_stall__read + +/* Compute Metrics Basic Gen7.5 :: EU Stall */ +#define hsw__compute_basic__eu_stall__read \ + hsw__render_basic__eu_stall__read + +/* Compute Metrics Basic Gen7.5 :: Early Hi-Depth Test Fails */ +#define hsw__compute_basic__hi_depth_test_fails__read \ + hsw__render_basic__hi_depth_test_fails__read + +/* Compute Metrics Basic Gen7.5 :: VS EU Active */ +#define hsw__compute_basic__vs_eu_active__read \ + hsw__render_basic__vs_eu_active__read + +/* Compute Metrics Basic Gen7.5 :: CS EU Active */ +#define hsw__compute_basic__cs_eu_active__read \ + hsw__render_basic__cs_eu_active__read + +/* Compute Metrics Basic Gen7.5 :: CS AVG Stall per Thread */ +#define hsw__compute_basic__cs_eu_stall_per_thread__read \ + hsw__render_basic__cs_eu_stall_per_thread__read + +/* Compute Metrics Basic Gen7.5 :: Late Stencil Test Fails */ +#define hsw__compute_basic__post_ps_stencil_test_fails__read \ + hsw__render_basic__post_ps_stencil_test_fails__read + +/* Compute Metrics Basic Gen7.5 :: VS AVG Active per Thread */ +#define hsw__compute_basic__vs_eu_active_per_thread__read \ + hsw__render_basic__vs_eu_active_per_thread__read + +/* Compute Metrics Basic Gen7.5 :: CS EU Stall */ +#define hsw__compute_basic__cs_eu_stall__read \ + hsw__render_basic__cs_eu_stall__read + +/* Compute Metrics Basic Gen7.5 :: Typed Bytes Read */ +static uint64_t +hsw__compute_basic__typed_bytes_read__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 4 READ B 5 READ UADD $EuSlicesTotalCount 64 UMUL UMUL */ + uint64_t tmp0 = accumulator[query->b_offset + 4]; + uint64_t tmp1 = accumulator[query->b_offset + 5]; + uint64_t tmp2 = tmp0 + tmp1; + uint64_t tmp3 = brw->perfquery.sys_vars.n_eu_slices * 64; + uint64_t tmp4 = tmp2 * tmp3; + + return tmp4; +} + +/* Compute Metrics Basic Gen7.5 :: Samples Written */ +#define hsw__compute_basic__samples_written__read \ + hsw__render_basic__samples_written__read + +/* Compute Metrics Basic Gen7.5 :: VS EU Stall */ +#define hsw__compute_basic__vs_eu_stall__read \ + hsw__render_basic__vs_eu_stall__read + +/* Compute Metrics Extended Gen7.5 :: EuUntypedWrites0 */ +static uint64_t +hsw__compute_extended__eu_untyped_writes0__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 1 READ */ + uint64_t tmp0 = accumulator[query->b_offset + 1]; + + return tmp0; +} + +/* Compute Metrics Extended Gen7.5 :: Untyped Writes 0 */ +static uint64_t +hsw__compute_extended__untyped_writes0__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 1 READ */ + uint64_t tmp0 = accumulator[query->c_offset + 1]; + + return tmp0; +} + +/* Compute Metrics Extended Gen7.5 :: UntypedWritesPerCacheLine */ +static float +hsw__compute_extended__untyped_writes_per_cache_line__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $EuUntypedWrites0 $UntypedWrites0 FDIV */ + double tmp0 = hsw__compute_extended__eu_untyped_writes0__read(brw, query, accumulator); + double tmp1 = hsw__compute_extended__untyped_writes0__read(brw, query, accumulator); + double tmp2 = tmp1 ? tmp0 / tmp1 : 0; + + return tmp2; +} + +/* Compute Metrics Extended Gen7.5 :: Typed Reads 0 */ +#define hsw__compute_extended__typed_reads0__read \ + hsw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Extended Gen7.5 :: Typed Writes 0 */ +static uint64_t +hsw__compute_extended__typed_writes0__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 0 READ */ + uint64_t tmp0 = accumulator[query->c_offset + 0]; + + return tmp0; +} + +/* Compute Metrics Extended Gen7.5 :: EuTypedAtomics0 */ +static uint64_t +hsw__compute_extended__eu_typed_atomics0__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 5 READ */ + uint64_t tmp0 = accumulator[query->b_offset + 5]; + + return tmp0; +} + +/* Compute Metrics Extended Gen7.5 :: Typed Atomics 0 */ +static uint64_t +hsw__compute_extended__typed_atomics0__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 4 READ */ + uint64_t tmp0 = accumulator[query->c_offset + 4]; + + return tmp0; +} + +/* Compute Metrics Extended Gen7.5 :: TypedAtomicsPerCacheLine */ +static float +hsw__compute_extended__typed_atomics_per_cache_line__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $EuTypedAtomics0 $TypedAtomics0 FDIV */ + double tmp0 = hsw__compute_extended__eu_typed_atomics0__read(brw, query, accumulator); + double tmp1 = hsw__compute_extended__typed_atomics0__read(brw, query, accumulator); + double tmp2 = tmp1 ? tmp0 / tmp1 : 0; + + return tmp2; +} + +/* Compute Metrics Extended Gen7.5 :: EuUntypedReads0 */ +static uint64_t +hsw__compute_extended__eu_untyped_reads0__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 0 READ */ + uint64_t tmp0 = accumulator[query->b_offset + 0]; + + return tmp0; +} + +/* Compute Metrics Extended Gen7.5 :: EuUntypedAtomics0 */ +static uint64_t +hsw__compute_extended__eu_untyped_atomics0__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 4 READ */ + uint64_t tmp0 = accumulator[query->b_offset + 4]; + + return tmp0; +} + +/* Compute Metrics Extended Gen7.5 :: GPU Core Clocks */ +static uint64_t +hsw__compute_extended__gpu_clocks__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 7 READ */ + uint64_t tmp0 = accumulator[query->b_offset + 7]; + + return tmp0; +} + +/* Compute Metrics Extended Gen7.5 :: CS Threads Dispatched */ +#define hsw__compute_extended__cs_threads__read \ + hsw__render_basic__cs_threads__read + +/* Compute Metrics Extended Gen7.5 :: EuTypedWrites0 */ +static uint64_t +hsw__compute_extended__eu_typed_writes0__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 3 READ */ + uint64_t tmp0 = accumulator[query->b_offset + 3]; + + return tmp0; +} + +/* Compute Metrics Extended Gen7.5 :: TypedWritesPerCacheLine */ +static float +hsw__compute_extended__typed_writes_per_cache_line__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $EuTypedWrites0 $TypedWrites0 FDIV */ + double tmp0 = hsw__compute_extended__eu_typed_writes0__read(brw, query, accumulator); + double tmp1 = hsw__compute_extended__typed_writes0__read(brw, query, accumulator); + double tmp2 = tmp1 ? tmp0 / tmp1 : 0; + + return tmp2; +} + +/* Compute Metrics Extended Gen7.5 :: EuTypedReads0 */ +static uint64_t +hsw__compute_extended__eu_typed_reads0__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 2 READ */ + uint64_t tmp0 = accumulator[query->b_offset + 2]; + + return tmp0; +} + +/* Compute Metrics Extended Gen7.5 :: EuUrbAtomics0 */ +static uint64_t +hsw__compute_extended__eu_urb_atomics0__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 6 READ */ + uint64_t tmp0 = accumulator[query->b_offset + 6]; + + return tmp0; +} + +/* Compute Metrics Extended Gen7.5 :: Untyped Reads 0 */ +static uint64_t +hsw__compute_extended__untyped_reads0__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 3 READ */ + uint64_t tmp0 = accumulator[query->c_offset + 3]; + + return tmp0; +} + +/* Compute Metrics Extended Gen7.5 :: UntypedReadsPerCacheLine */ +static float +hsw__compute_extended__untyped_reads_per_cache_line__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $EuUntypedReads0 $UntypedReads0 FDIV */ + double tmp0 = hsw__compute_extended__eu_untyped_reads0__read(brw, query, accumulator); + double tmp1 = hsw__compute_extended__untyped_reads0__read(brw, query, accumulator); + double tmp2 = tmp1 ? tmp0 / tmp1 : 0; + + return tmp2; +} + +/* Compute Metrics Extended Gen7.5 :: GPU Time Elapsed */ +#define hsw__compute_extended__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics Extended Gen7.5 :: TypedReadsPerCacheLine */ +static float +hsw__compute_extended__typed_reads_per_cache_line__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $EuTypedReads0 $TypedReads0 FDIV */ + double tmp0 = hsw__compute_extended__eu_typed_reads0__read(brw, query, accumulator); + double tmp1 = hsw__compute_extended__typed_reads0__read(brw, query, accumulator); + double tmp2 = tmp1 ? tmp0 / tmp1 : 0; + + return tmp2; +} + +/* Memory Reads Distribution Gen7.5 :: GPU Core Clocks */ +static uint64_t +hsw__memory_reads__gpu_core_clocks__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 7 READ */ + uint64_t tmp0 = accumulator[query->c_offset + 7]; + + return tmp0; +} + +/* Memory Reads Distribution Gen7.5 :: EU Active */ +static float +hsw__memory_reads__eu_active__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 0 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 0]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__memory_reads__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Memory Reads Distribution Gen7.5 :: TES EU Stall */ +static float +hsw__memory_reads__ds_eu_stall__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 13 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 13]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__memory_reads__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Memory Reads Distribution Gen7.5 :: Alpha Test Fails */ +#define hsw__memory_reads__alpha_test_fails__read \ + hsw__render_basic__alpha_test_fails__read + +/* Memory Reads Distribution Gen7.5 :: TES Threads Dispatched */ +#define hsw__memory_reads__ds_threads__read \ + hsw__render_basic__ds_threads__read + +/* Memory Reads Distribution Gen7.5 :: TES AVG Active per Thread */ +#define hsw__memory_reads__ds_eu_active_per_thread__read \ + hsw__render_basic__ds_eu_active_per_thread__read + +/* Memory Reads Distribution Gen7.5 :: GS Threads Dispatched */ +#define hsw__memory_reads__gs_threads__read \ + hsw__render_basic__gs_threads__read + +/* Memory Reads Distribution Gen7.5 :: GS EU Stall */ +static float +hsw__memory_reads__gs_eu_stall__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 23 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 23]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__memory_reads__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Memory Reads Distribution Gen7.5 :: VS Threads Dispatched */ +#define hsw__memory_reads__vs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Memory Reads Distribution Gen7.5 :: LLC GPU Read Accesses */ +static uint64_t +hsw__memory_reads__llc_read_accesses__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 6 READ */ + uint64_t tmp0 = accumulator[query->c_offset + 6]; + + return tmp0; +} + +/* Memory Reads Distribution Gen7.5 :: FS Threads Dispatched */ +#define hsw__memory_reads__ps_threads__read \ + hsw__render_basic__ps_threads__read + +/* Memory Reads Distribution Gen7.5 :: GtiMemoryReads */ +static uint64_t +hsw__memory_reads__gti_memory_reads__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 5 READ */ + uint64_t tmp0 = accumulator[query->c_offset + 5]; + + return tmp0; +} + +/* Memory Reads Distribution Gen7.5 :: CS Threads Dispatched */ +#define hsw__memory_reads__cs_threads__read \ + hsw__render_basic__cs_threads__read + +/* Memory Reads Distribution Gen7.5 :: CS AVG Active per Thread */ +#define hsw__memory_reads__cs_eu_active_per_thread__read \ + hsw__render_basic__cs_eu_active_per_thread__read + +/* Memory Reads Distribution Gen7.5 :: GtiRczMemoryReads */ +#define hsw__memory_reads__gti_rcz_memory_reads__read \ + hsw__compute_extended__gpu_clocks__read + +/* Memory Reads Distribution Gen7.5 :: GS AVG Stall per Thread */ +#define hsw__memory_reads__gs_eu_stall_per_thread__read \ + hsw__render_basic__gs_eu_stall_per_thread__read + +/* Memory Reads Distribution Gen7.5 :: GPU Time Elapsed */ +#define hsw__memory_reads__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Memory Reads Distribution Gen7.5 :: AVG GPU Core Frequency */ +static uint64_t +hsw__memory_reads__avg_gpu_core_frequency__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $GpuCoreClocks 1000000000 UMUL $GpuTime UDIV */ + uint64_t tmp0 = hsw__memory_reads__gpu_core_clocks__read(brw, query, accumulator) * 1000000000; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = hsw__memory_reads__gpu_time__read(brw, query, accumulator); + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + + return tmp3; +} + +/* Memory Reads Distribution Gen7.5 :: AVG GPU Core Frequency */ +#define hsw__memory_reads__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Memory Reads Distribution Gen7.5 :: GtiRccMemoryReads */ +#define hsw__memory_reads__gti_rcc_memory_reads__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* Memory Reads Distribution Gen7.5 :: FS AVG Stall per Thread */ +#define hsw__memory_reads__ps_eu_stall_per_thread__read \ + hsw__render_basic__ps_eu_stall_per_thread__read + +/* Memory Reads Distribution Gen7.5 :: TES EU Active */ +static float +hsw__memory_reads__ds_eu_active__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 12 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 12]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__memory_reads__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Memory Reads Distribution Gen7.5 :: VS AVG Stall per Thread */ +#define hsw__memory_reads__vs_eu_stall_per_thread__read \ + hsw__render_basic__vs_eu_stall_per_thread__read + +/* Memory Reads Distribution Gen7.5 :: TCS EU Stall */ +static float +hsw__memory_reads__hs_eu_stall__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 8 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 8]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__memory_reads__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Memory Reads Distribution Gen7.5 :: GPU Busy */ +static float +hsw__memory_reads__gpu_busy__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 41 READ 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 41]; + uint64_t tmp1 = tmp0 * 100; + double tmp2 = tmp1; + double tmp3 = hsw__memory_reads__gpu_core_clocks__read(brw, query, accumulator); + double tmp4 = tmp3 ? tmp2 / tmp3 : 0; + + return tmp4; +} + +/* Memory Reads Distribution Gen7.5 :: FS AVG Active per Thread */ +#define hsw__memory_reads__ps_eu_active_per_thread__read \ + hsw__render_basic__ps_eu_active_per_thread__read + +/* Memory Reads Distribution Gen7.5 :: GtiCmdStreamerMemoryReads */ +#define hsw__memory_reads__gti_cmd_streamer_memory_reads__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* Memory Reads Distribution Gen7.5 :: Early Depth Test Fails */ +#define hsw__memory_reads__early_depth_test_fails__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Memory Reads Distribution Gen7.5 :: GS EU Active */ +static float +hsw__memory_reads__gs_eu_active__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 22 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 22]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__memory_reads__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Memory Reads Distribution Gen7.5 :: FS EU Active */ +static float +hsw__memory_reads__ps_eu_active__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 27 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 27]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__memory_reads__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Memory Reads Distribution Gen7.5 :: TES AVG Stall per Thread */ +#define hsw__memory_reads__ds_eu_stall_per_thread__read \ + hsw__render_basic__ds_eu_stall_per_thread__read + +/* Memory Reads Distribution Gen7.5 :: GS AVG Active per Thread */ +#define hsw__memory_reads__gs_eu_active_per_thread__read \ + hsw__render_basic__gs_eu_active_per_thread__read + +/* Memory Reads Distribution Gen7.5 :: GtiHiDepthMemoryReads */ +#define hsw__memory_reads__gti_hi_depth_memory_reads__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* Memory Reads Distribution Gen7.5 :: TCS Threads Dispatched */ +#define hsw__memory_reads__hs_threads__read \ + hsw__render_basic__hs_threads__read + +/* Memory Reads Distribution Gen7.5 :: TCS AVG Stall per Thread */ +#define hsw__memory_reads__hs_eu_stall_per_thread__read \ + hsw__render_basic__hs_eu_stall_per_thread__read + +/* Memory Reads Distribution Gen7.5 :: TCS EU Active */ +static float +hsw__memory_reads__hs_eu_active__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 7 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 7]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__memory_reads__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Memory Reads Distribution Gen7.5 :: Samples Killed in FS */ +#define hsw__memory_reads__samples_killed_in_ps__read \ + hsw__render_basic__samples_killed_in_ps__read + +/* Memory Reads Distribution Gen7.5 :: Late Depth Test Fails */ +#define hsw__memory_reads__post_ps_depth_test_fails__read \ + hsw__render_basic__post_ps_depth_test_fails__read + +/* Memory Reads Distribution Gen7.5 :: TCS AVG Active per Thread */ +#define hsw__memory_reads__hs_eu_active_per_thread__read \ + hsw__render_basic__hs_eu_active_per_thread__read + +/* Memory Reads Distribution Gen7.5 :: FS EU Stall */ +static float +hsw__memory_reads__ps_eu_stall__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 28 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 28]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__memory_reads__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Memory Reads Distribution Gen7.5 :: EU Stall */ +static float +hsw__memory_reads__eu_stall__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 1 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 1]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__memory_reads__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Memory Reads Distribution Gen7.5 :: GtiMscMemoryReads */ +#define hsw__memory_reads__gti_msc_memory_reads__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* Memory Reads Distribution Gen7.5 :: Early Hi-Depth Test Fails */ +#define hsw__memory_reads__hi_depth_test_fails__read \ + hsw__render_basic__hi_depth_test_fails__read + +/* Memory Reads Distribution Gen7.5 :: VS EU Active */ +static float +hsw__memory_reads__vs_eu_active__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 2 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 2]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__memory_reads__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Memory Reads Distribution Gen7.5 :: CS EU Active */ +static float +hsw__memory_reads__cs_eu_active__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 17 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 17]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__memory_reads__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Memory Reads Distribution Gen7.5 :: CS AVG Stall per Thread */ +#define hsw__memory_reads__cs_eu_stall_per_thread__read \ + hsw__render_basic__cs_eu_stall_per_thread__read + +/* Memory Reads Distribution Gen7.5 :: GtiVfMemoryReads */ +#define hsw__memory_reads__gti_vf_memory_reads__read \ + hsw__compute_extended__eu_untyped_writes0__read + +/* Memory Reads Distribution Gen7.5 :: Late Stencil Test Fails */ +#define hsw__memory_reads__post_ps_stencil_test_fails__read \ + hsw__render_basic__post_ps_stencil_test_fails__read + +/* Memory Reads Distribution Gen7.5 :: GtiStcMemoryReads */ +#define hsw__memory_reads__gti_stc_memory_reads__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* Memory Reads Distribution Gen7.5 :: VS AVG Active per Thread */ +#define hsw__memory_reads__vs_eu_active_per_thread__read \ + hsw__render_basic__vs_eu_active_per_thread__read + +/* Memory Reads Distribution Gen7.5 :: GtiRsMemoryReads */ +#define hsw__memory_reads__gti_rs_memory_reads__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Memory Reads Distribution Gen7.5 :: CS EU Stall */ +static float +hsw__memory_reads__cs_eu_stall__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 18 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 18]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__memory_reads__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Memory Reads Distribution Gen7.5 :: Samples Written */ +#define hsw__memory_reads__samples_written__read \ + hsw__render_basic__samples_written__read + +/* Memory Reads Distribution Gen7.5 :: GtiL3Reads */ +#define hsw__memory_reads__gti_l3_reads__read \ + hsw__compute_extended__typed_atomics0__read + +/* Memory Reads Distribution Gen7.5 :: VS EU Stall */ +static float +hsw__memory_reads__vs_eu_stall__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 3 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 3]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__memory_reads__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Memory Writes Distribution Gen7.5 :: GPU Core Clocks */ +#define hsw__memory_writes__gpu_core_clocks__read \ + hsw__memory_reads__gpu_core_clocks__read + +/* Memory Writes Distribution Gen7.5 :: EU Active */ +#define hsw__memory_writes__eu_active__read \ + hsw__memory_reads__eu_active__read + +/* Memory Writes Distribution Gen7.5 :: TES EU Stall */ +#define hsw__memory_writes__ds_eu_stall__read \ + hsw__memory_reads__ds_eu_stall__read + +/* Memory Writes Distribution Gen7.5 :: Alpha Test Fails */ +#define hsw__memory_writes__alpha_test_fails__read \ + hsw__render_basic__alpha_test_fails__read + +/* Memory Writes Distribution Gen7.5 :: TES Threads Dispatched */ +#define hsw__memory_writes__ds_threads__read \ + hsw__render_basic__ds_threads__read + +/* Memory Writes Distribution Gen7.5 :: TES AVG Active per Thread */ +#define hsw__memory_writes__ds_eu_active_per_thread__read \ + hsw__render_basic__ds_eu_active_per_thread__read + +/* Memory Writes Distribution Gen7.5 :: GS Threads Dispatched */ +#define hsw__memory_writes__gs_threads__read \ + hsw__render_basic__gs_threads__read + +/* Memory Writes Distribution Gen7.5 :: GS EU Stall */ +#define hsw__memory_writes__gs_eu_stall__read \ + hsw__memory_reads__gs_eu_stall__read + +/* Memory Writes Distribution Gen7.5 :: VS Threads Dispatched */ +#define hsw__memory_writes__vs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Memory Writes Distribution Gen7.5 :: FS Threads Dispatched */ +#define hsw__memory_writes__ps_threads__read \ + hsw__render_basic__ps_threads__read + +/* Memory Writes Distribution Gen7.5 :: GtiMscMemoryWrites */ +#define hsw__memory_writes__gti_msc_memory_writes__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* Memory Writes Distribution Gen7.5 :: CS Threads Dispatched */ +#define hsw__memory_writes__cs_threads__read \ + hsw__render_basic__cs_threads__read + +/* Memory Writes Distribution Gen7.5 :: CS AVG Active per Thread */ +#define hsw__memory_writes__cs_eu_active_per_thread__read \ + hsw__render_basic__cs_eu_active_per_thread__read + +/* Memory Writes Distribution Gen7.5 :: GtiCmdStreamerMemoryWrites */ +#define hsw__memory_writes__gti_cmd_streamer_memory_writes__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* Memory Writes Distribution Gen7.5 :: GS AVG Stall per Thread */ +#define hsw__memory_writes__gs_eu_stall_per_thread__read \ + hsw__render_basic__gs_eu_stall_per_thread__read + +/* Memory Writes Distribution Gen7.5 :: GtiL3Writes */ +#define hsw__memory_writes__gti_l3_writes__read \ + hsw__compute_extended__typed_atomics0__read + +/* Memory Writes Distribution Gen7.5 :: GtiHizMemoryWrites */ +#define hsw__memory_writes__gti_hiz_memory_writes__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* Memory Writes Distribution Gen7.5 :: GPU Time Elapsed */ +#define hsw__memory_writes__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Memory Writes Distribution Gen7.5 :: AVG GPU Core Frequency */ +#define hsw__memory_writes__avg_gpu_core_frequency__read \ + hsw__memory_reads__avg_gpu_core_frequency__read + +/* Memory Writes Distribution Gen7.5 :: AVG GPU Core Frequency */ +#define hsw__memory_writes__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Memory Writes Distribution Gen7.5 :: FS AVG Stall per Thread */ +#define hsw__memory_writes__ps_eu_stall_per_thread__read \ + hsw__render_basic__ps_eu_stall_per_thread__read + +/* Memory Writes Distribution Gen7.5 :: GtiRccMemoryWrites */ +#define hsw__memory_writes__gti_rcc_memory_writes__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* Memory Writes Distribution Gen7.5 :: TES EU Active */ +#define hsw__memory_writes__ds_eu_active__read \ + hsw__memory_reads__ds_eu_active__read + +/* Memory Writes Distribution Gen7.5 :: VS AVG Stall per Thread */ +#define hsw__memory_writes__vs_eu_stall_per_thread__read \ + hsw__render_basic__vs_eu_stall_per_thread__read + +/* Memory Writes Distribution Gen7.5 :: TCS EU Stall */ +#define hsw__memory_writes__hs_eu_stall__read \ + hsw__memory_reads__hs_eu_stall__read + +/* Memory Writes Distribution Gen7.5 :: GPU Busy */ +#define hsw__memory_writes__gpu_busy__read \ + hsw__memory_reads__gpu_busy__read + +/* Memory Writes Distribution Gen7.5 :: FS AVG Active per Thread */ +#define hsw__memory_writes__ps_eu_active_per_thread__read \ + hsw__render_basic__ps_eu_active_per_thread__read + +/* Memory Writes Distribution Gen7.5 :: Early Depth Test Fails */ +#define hsw__memory_writes__early_depth_test_fails__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Memory Writes Distribution Gen7.5 :: LLC GPU Write Accesses */ +static uint64_t +hsw__memory_writes__llc_wr_accesses__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 6 READ 2 UMUL */ + uint64_t tmp0 = accumulator[query->c_offset + 6]; + uint64_t tmp1 = tmp0 * 2; + + return tmp1; +} + +/* Memory Writes Distribution Gen7.5 :: GS EU Active */ +#define hsw__memory_writes__gs_eu_active__read \ + hsw__memory_reads__gs_eu_active__read + +/* Memory Writes Distribution Gen7.5 :: FS EU Active */ +#define hsw__memory_writes__ps_eu_active__read \ + hsw__memory_reads__ps_eu_active__read + +/* Memory Writes Distribution Gen7.5 :: GtiStcMemoryWrites */ +#define hsw__memory_writes__gti_stc_memory_writes__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* Memory Writes Distribution Gen7.5 :: TES AVG Stall per Thread */ +#define hsw__memory_writes__ds_eu_stall_per_thread__read \ + hsw__render_basic__ds_eu_stall_per_thread__read + +/* Memory Writes Distribution Gen7.5 :: GS AVG Active per Thread */ +#define hsw__memory_writes__gs_eu_active_per_thread__read \ + hsw__render_basic__gs_eu_active_per_thread__read + +/* Memory Writes Distribution Gen7.5 :: TCS Threads Dispatched */ +#define hsw__memory_writes__hs_threads__read \ + hsw__render_basic__hs_threads__read + +/* Memory Writes Distribution Gen7.5 :: TCS AVG Stall per Thread */ +#define hsw__memory_writes__hs_eu_stall_per_thread__read \ + hsw__render_basic__hs_eu_stall_per_thread__read + +/* Memory Writes Distribution Gen7.5 :: TCS EU Active */ +#define hsw__memory_writes__hs_eu_active__read \ + hsw__memory_reads__hs_eu_active__read + +/* Memory Writes Distribution Gen7.5 :: Samples Killed in FS */ +#define hsw__memory_writes__samples_killed_in_ps__read \ + hsw__render_basic__samples_killed_in_ps__read + +/* Memory Writes Distribution Gen7.5 :: Late Depth Test Fails */ +#define hsw__memory_writes__post_ps_depth_test_fails__read \ + hsw__render_basic__post_ps_depth_test_fails__read + +/* Memory Writes Distribution Gen7.5 :: TCS AVG Active per Thread */ +#define hsw__memory_writes__hs_eu_active_per_thread__read \ + hsw__render_basic__hs_eu_active_per_thread__read + +/* Memory Writes Distribution Gen7.5 :: FS EU Stall */ +#define hsw__memory_writes__ps_eu_stall__read \ + hsw__memory_reads__ps_eu_stall__read + +/* Memory Writes Distribution Gen7.5 :: EU Stall */ +#define hsw__memory_writes__eu_stall__read \ + hsw__memory_reads__eu_stall__read + +/* Memory Writes Distribution Gen7.5 :: Early Hi-Depth Test Fails */ +#define hsw__memory_writes__hi_depth_test_fails__read \ + hsw__render_basic__hi_depth_test_fails__read + +/* Memory Writes Distribution Gen7.5 :: VS EU Active */ +#define hsw__memory_writes__vs_eu_active__read \ + hsw__memory_reads__vs_eu_active__read + +/* Memory Writes Distribution Gen7.5 :: CS EU Active */ +#define hsw__memory_writes__cs_eu_active__read \ + hsw__memory_reads__cs_eu_active__read + +/* Memory Writes Distribution Gen7.5 :: CS AVG Stall per Thread */ +#define hsw__memory_writes__cs_eu_stall_per_thread__read \ + hsw__render_basic__cs_eu_stall_per_thread__read + +/* Memory Writes Distribution Gen7.5 :: Late Stencil Test Fails */ +#define hsw__memory_writes__post_ps_stencil_test_fails__read \ + hsw__render_basic__post_ps_stencil_test_fails__read + +/* Memory Writes Distribution Gen7.5 :: GtiSoMemoryWrites */ +#define hsw__memory_writes__gti_so_memory_writes__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Memory Writes Distribution Gen7.5 :: VS AVG Active per Thread */ +#define hsw__memory_writes__vs_eu_active_per_thread__read \ + hsw__render_basic__vs_eu_active_per_thread__read + +/* Memory Writes Distribution Gen7.5 :: GtiRczMemoryWrites */ +#define hsw__memory_writes__gti_rcz_memory_writes__read \ + hsw__compute_extended__gpu_clocks__read + +/* Memory Writes Distribution Gen7.5 :: CS EU Stall */ +#define hsw__memory_writes__cs_eu_stall__read \ + hsw__memory_reads__cs_eu_stall__read + +/* Memory Writes Distribution Gen7.5 :: Samples Written */ +#define hsw__memory_writes__samples_written__read \ + hsw__render_basic__samples_written__read + +/* Memory Writes Distribution Gen7.5 :: GtiMemoryWrites */ +#define hsw__memory_writes__gti_memory_writes__read \ + hsw__memory_reads__gti_memory_reads__read + +/* Memory Writes Distribution Gen7.5 :: VS EU Stall */ +#define hsw__memory_writes__vs_eu_stall__read \ + hsw__memory_reads__vs_eu_stall__read + +/* Metric set SamplerBalance :: GPU Core Clocks */ +#define hsw__sampler_balance__gpu_core_clocks__read \ + hsw__compute_extended__gpu_clocks__read + +/* Metric set SamplerBalance :: EU Active */ +static float +hsw__sampler_balance__eu_active__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 0 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 0]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Metric set SamplerBalance :: TES EU Stall */ +static float +hsw__sampler_balance__ds_eu_stall__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 13 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 13]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Metric set SamplerBalance :: Sampler L2 cache misses (ss3) */ +static uint64_t +hsw__sampler_balance__sampler3_l2_cache_misses__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 1 READ C 0 READ UADD */ + uint64_t tmp0 = accumulator[query->c_offset + 1]; + uint64_t tmp1 = accumulator[query->c_offset + 0]; + uint64_t tmp2 = tmp0 + tmp1; + + return tmp2; +} + +/* Metric set SamplerBalance :: Alpha Test Fails */ +#define hsw__sampler_balance__alpha_test_fails__read \ + hsw__render_basic__alpha_test_fails__read + +/* Metric set SamplerBalance :: TES Threads Dispatched */ +#define hsw__sampler_balance__ds_threads__read \ + hsw__render_basic__ds_threads__read + +/* Metric set SamplerBalance :: TES AVG Active per Thread */ +#define hsw__sampler_balance__ds_eu_active_per_thread__read \ + hsw__render_basic__ds_eu_active_per_thread__read + +/* Metric set SamplerBalance :: GS Threads Dispatched */ +#define hsw__sampler_balance__gs_threads__read \ + hsw__render_basic__gs_threads__read + +/* Metric set SamplerBalance :: GS EU Stall */ +static float +hsw__sampler_balance__gs_eu_stall__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 23 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 23]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Metric set SamplerBalance :: CS EU Active */ +static float +hsw__sampler_balance__cs_eu_active__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 17 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 17]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Metric set SamplerBalance :: VS EU Active */ +static float +hsw__sampler_balance__vs_eu_active__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 2 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 2]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Metric set SamplerBalance :: TCS EU Active */ +static float +hsw__sampler_balance__hs_eu_active__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 7 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 7]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Metric set SamplerBalance :: TES EU Active */ +static float +hsw__sampler_balance__ds_eu_active__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 12 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 12]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Metric set SamplerBalance :: GS EU Active */ +static float +hsw__sampler_balance__gs_eu_active__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 22 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 22]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Metric set SamplerBalance :: FS EU Active */ +static float +hsw__sampler_balance__ps_eu_active__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 27 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 27]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Metric set SamplerBalance :: CS EU Stall */ +static float +hsw__sampler_balance__cs_eu_stall__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 18 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 18]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Metric set SamplerBalance :: EU Stall */ +static float +hsw__sampler_balance__eu_stall__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 1 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 1]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Metric set SamplerBalance :: VS EU Stall */ +static float +hsw__sampler_balance__vs_eu_stall__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 3 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 3]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Metric set SamplerBalance :: TCS EU Stall */ +static float +hsw__sampler_balance__hs_eu_stall__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 8 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 8]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Metric set SamplerBalance :: FS EU Stall */ +static float +hsw__sampler_balance__ps_eu_stall__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 28 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 28]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = hsw__sampler_balance__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Metric set SamplerBalance :: GPU Time Elapsed */ +#define hsw__sampler_balance__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set SamplerBalance :: CS Duration */ +static uint64_t +hsw__sampler_balance__cs_duration__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 17 READ A 0 READ UMUL A 2 READ A 7 READ UADD A 12 READ UADD A 17 READ UADD A 22 READ UADD A 27 READ UADD UDIV A 18 READ A 1 READ UMUL A 3 READ A 8 READ UADD A 13 READ UADD A 18 READ UADD A 23 READ UADD A 28 READ UADD UDIV UADD $GpuTime UMUL $GpuCoreClocks $EuCoresTotalCount UMUL 1000 UMUL UDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 17]; + uint64_t tmp1 = accumulator[query->a_offset + 0]; + uint64_t tmp2 = tmp0 * tmp1; + uint64_t tmp3 = accumulator[query->a_offset + 2]; + uint64_t tmp4 = accumulator[query->a_offset + 7]; + uint64_t tmp5 = tmp3 + tmp4; + uint64_t tmp6 = accumulator[query->a_offset + 12]; + uint64_t tmp7 = tmp5 + tmp6; + uint64_t tmp8 = accumulator[query->a_offset + 17]; + uint64_t tmp9 = tmp7 + tmp8; + uint64_t tmp10 = accumulator[query->a_offset + 22]; + uint64_t tmp11 = tmp9 + tmp10; + uint64_t tmp12 = accumulator[query->a_offset + 27]; + uint64_t tmp13 = tmp11 + tmp12; + uint64_t tmp14 = tmp2; + uint64_t tmp15 = tmp13; + uint64_t tmp16 = tmp15 ? tmp14 / tmp15 : 0; + uint64_t tmp17 = accumulator[query->a_offset + 18]; + uint64_t tmp18 = accumulator[query->a_offset + 1]; + uint64_t tmp19 = tmp17 * tmp18; + uint64_t tmp20 = accumulator[query->a_offset + 3]; + uint64_t tmp21 = accumulator[query->a_offset + 8]; + uint64_t tmp22 = tmp20 + tmp21; + uint64_t tmp23 = accumulator[query->a_offset + 13]; + uint64_t tmp24 = tmp22 + tmp23; + uint64_t tmp25 = accumulator[query->a_offset + 18]; + uint64_t tmp26 = tmp24 + tmp25; + uint64_t tmp27 = accumulator[query->a_offset + 23]; + uint64_t tmp28 = tmp26 + tmp27; + uint64_t tmp29 = accumulator[query->a_offset + 28]; + uint64_t tmp30 = tmp28 + tmp29; + uint64_t tmp31 = tmp19; + uint64_t tmp32 = tmp30; + uint64_t tmp33 = tmp32 ? tmp31 / tmp32 : 0; + uint64_t tmp34 = tmp16 + tmp33; + uint64_t tmp35 = tmp34 * hsw__sampler_balance__gpu_time__read(brw, query, accumulator); + uint64_t tmp36 = hsw__sampler_balance__gpu_core_clocks__read(brw, query, accumulator) * brw->perfquery.sys_vars.n_eus; + uint64_t tmp37 = tmp36 * 1000; + uint64_t tmp38 = tmp35; + uint64_t tmp39 = tmp37; + uint64_t tmp40 = tmp39 ? tmp38 / tmp39 : 0; + + return tmp40; +} + +/* Metric set SamplerBalance :: VS Threads Dispatched */ +#define hsw__sampler_balance__vs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set SamplerBalance :: FS Threads Dispatched */ +#define hsw__sampler_balance__ps_threads__read \ + hsw__render_basic__ps_threads__read + +/* Metric set SamplerBalance :: TES Duration */ +static uint64_t +hsw__sampler_balance__ds_duration__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 12 READ A 0 READ UMUL A 2 READ A 7 READ UADD A 12 READ UADD A 17 READ UADD A 22 READ UADD A 27 READ UADD UDIV A 13 READ A 1 READ UMUL A 3 READ A 8 READ UADD A 13 READ UADD A 18 READ UADD A 23 READ UADD A 28 READ UADD UDIV UADD $GpuTime UMUL $GpuCoreClocks $EuCoresTotalCount UMUL 1000 UMUL UDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 12]; + uint64_t tmp1 = accumulator[query->a_offset + 0]; + uint64_t tmp2 = tmp0 * tmp1; + uint64_t tmp3 = accumulator[query->a_offset + 2]; + uint64_t tmp4 = accumulator[query->a_offset + 7]; + uint64_t tmp5 = tmp3 + tmp4; + uint64_t tmp6 = accumulator[query->a_offset + 12]; + uint64_t tmp7 = tmp5 + tmp6; + uint64_t tmp8 = accumulator[query->a_offset + 17]; + uint64_t tmp9 = tmp7 + tmp8; + uint64_t tmp10 = accumulator[query->a_offset + 22]; + uint64_t tmp11 = tmp9 + tmp10; + uint64_t tmp12 = accumulator[query->a_offset + 27]; + uint64_t tmp13 = tmp11 + tmp12; + uint64_t tmp14 = tmp2; + uint64_t tmp15 = tmp13; + uint64_t tmp16 = tmp15 ? tmp14 / tmp15 : 0; + uint64_t tmp17 = accumulator[query->a_offset + 13]; + uint64_t tmp18 = accumulator[query->a_offset + 1]; + uint64_t tmp19 = tmp17 * tmp18; + uint64_t tmp20 = accumulator[query->a_offset + 3]; + uint64_t tmp21 = accumulator[query->a_offset + 8]; + uint64_t tmp22 = tmp20 + tmp21; + uint64_t tmp23 = accumulator[query->a_offset + 13]; + uint64_t tmp24 = tmp22 + tmp23; + uint64_t tmp25 = accumulator[query->a_offset + 18]; + uint64_t tmp26 = tmp24 + tmp25; + uint64_t tmp27 = accumulator[query->a_offset + 23]; + uint64_t tmp28 = tmp26 + tmp27; + uint64_t tmp29 = accumulator[query->a_offset + 28]; + uint64_t tmp30 = tmp28 + tmp29; + uint64_t tmp31 = tmp19; + uint64_t tmp32 = tmp30; + uint64_t tmp33 = tmp32 ? tmp31 / tmp32 : 0; + uint64_t tmp34 = tmp16 + tmp33; + uint64_t tmp35 = tmp34 * hsw__sampler_balance__gpu_time__read(brw, query, accumulator); + uint64_t tmp36 = hsw__sampler_balance__gpu_core_clocks__read(brw, query, accumulator) * brw->perfquery.sys_vars.n_eus; + uint64_t tmp37 = tmp36 * 1000; + uint64_t tmp38 = tmp35; + uint64_t tmp39 = tmp37; + uint64_t tmp40 = tmp39 ? tmp38 / tmp39 : 0; + + return tmp40; +} + +/* Metric set SamplerBalance :: GS Duration */ +static uint64_t +hsw__sampler_balance__gs_duration__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 22 READ A 0 READ UMUL A 2 READ A 7 READ UADD A 12 READ UADD A 17 READ UADD A 22 READ UADD A 27 READ UADD UDIV A 23 READ A 1 READ UMUL A 3 READ A 8 READ UADD A 13 READ UADD A 18 READ UADD A 23 READ UADD A 28 READ UADD UDIV UADD $GpuTime UMUL $GpuCoreClocks $EuCoresTotalCount UMUL 1000 UMUL UDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 22]; + uint64_t tmp1 = accumulator[query->a_offset + 0]; + uint64_t tmp2 = tmp0 * tmp1; + uint64_t tmp3 = accumulator[query->a_offset + 2]; + uint64_t tmp4 = accumulator[query->a_offset + 7]; + uint64_t tmp5 = tmp3 + tmp4; + uint64_t tmp6 = accumulator[query->a_offset + 12]; + uint64_t tmp7 = tmp5 + tmp6; + uint64_t tmp8 = accumulator[query->a_offset + 17]; + uint64_t tmp9 = tmp7 + tmp8; + uint64_t tmp10 = accumulator[query->a_offset + 22]; + uint64_t tmp11 = tmp9 + tmp10; + uint64_t tmp12 = accumulator[query->a_offset + 27]; + uint64_t tmp13 = tmp11 + tmp12; + uint64_t tmp14 = tmp2; + uint64_t tmp15 = tmp13; + uint64_t tmp16 = tmp15 ? tmp14 / tmp15 : 0; + uint64_t tmp17 = accumulator[query->a_offset + 23]; + uint64_t tmp18 = accumulator[query->a_offset + 1]; + uint64_t tmp19 = tmp17 * tmp18; + uint64_t tmp20 = accumulator[query->a_offset + 3]; + uint64_t tmp21 = accumulator[query->a_offset + 8]; + uint64_t tmp22 = tmp20 + tmp21; + uint64_t tmp23 = accumulator[query->a_offset + 13]; + uint64_t tmp24 = tmp22 + tmp23; + uint64_t tmp25 = accumulator[query->a_offset + 18]; + uint64_t tmp26 = tmp24 + tmp25; + uint64_t tmp27 = accumulator[query->a_offset + 23]; + uint64_t tmp28 = tmp26 + tmp27; + uint64_t tmp29 = accumulator[query->a_offset + 28]; + uint64_t tmp30 = tmp28 + tmp29; + uint64_t tmp31 = tmp19; + uint64_t tmp32 = tmp30; + uint64_t tmp33 = tmp32 ? tmp31 / tmp32 : 0; + uint64_t tmp34 = tmp16 + tmp33; + uint64_t tmp35 = tmp34 * hsw__sampler_balance__gpu_time__read(brw, query, accumulator); + uint64_t tmp36 = hsw__sampler_balance__gpu_core_clocks__read(brw, query, accumulator) * brw->perfquery.sys_vars.n_eus; + uint64_t tmp37 = tmp36 * 1000; + uint64_t tmp38 = tmp35; + uint64_t tmp39 = tmp37; + uint64_t tmp40 = tmp39 ? tmp38 / tmp39 : 0; + + return tmp40; +} + +/* Metric set SamplerBalance :: CS Threads Dispatched */ +#define hsw__sampler_balance__cs_threads__read \ + hsw__render_basic__cs_threads__read + +/* Metric set SamplerBalance :: CS AVG Active per Thread */ +#define hsw__sampler_balance__cs_eu_active_per_thread__read \ + hsw__render_basic__cs_eu_active_per_thread__read + +/* Metric set SamplerBalance :: Sampler L2 cache misses */ +static uint64_t +hsw__sampler_balance__sampler_l2_cache_misses__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 7 READ C 6 READ UADD C 5 READ UADD C 4 READ UADD C 3 READ UADD C 2 READ UADD C 1 READ UADD C 0 READ UADD */ + uint64_t tmp0 = accumulator[query->c_offset + 7]; + uint64_t tmp1 = accumulator[query->c_offset + 6]; + uint64_t tmp2 = tmp0 + tmp1; + uint64_t tmp3 = accumulator[query->c_offset + 5]; + uint64_t tmp4 = tmp2 + tmp3; + uint64_t tmp5 = accumulator[query->c_offset + 4]; + uint64_t tmp6 = tmp4 + tmp5; + uint64_t tmp7 = accumulator[query->c_offset + 3]; + uint64_t tmp8 = tmp6 + tmp7; + uint64_t tmp9 = accumulator[query->c_offset + 2]; + uint64_t tmp10 = tmp8 + tmp9; + uint64_t tmp11 = accumulator[query->c_offset + 1]; + uint64_t tmp12 = tmp10 + tmp11; + uint64_t tmp13 = accumulator[query->c_offset + 0]; + uint64_t tmp14 = tmp12 + tmp13; + + return tmp14; +} + +/* Metric set SamplerBalance :: GS AVG Stall per Thread */ +#define hsw__sampler_balance__gs_eu_stall_per_thread__read \ + hsw__render_basic__gs_eu_stall_per_thread__read + +/* Metric set SamplerBalance :: Sampler L2 cache misses (ss2) */ +static uint64_t +hsw__sampler_balance__sampler2_l2_cache_misses__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 3 READ C 2 READ UADD */ + uint64_t tmp0 = accumulator[query->c_offset + 3]; + uint64_t tmp1 = accumulator[query->c_offset + 2]; + uint64_t tmp2 = tmp0 + tmp1; + + return tmp2; +} + +/* Metric set SamplerBalance :: AVG GPU Core Frequency */ +static uint64_t +hsw__sampler_balance__avg_gpu_core_frequency__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $GpuCoreClocks 1000000000 UMUL $GpuTime UDIV */ + uint64_t tmp0 = hsw__sampler_balance__gpu_core_clocks__read(brw, query, accumulator) * 1000000000; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = hsw__sampler_balance__gpu_time__read(brw, query, accumulator); + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + + return tmp3; +} + +/* Metric set SamplerBalance :: AVG GPU Core Frequency */ +#define hsw__sampler_balance__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set SamplerBalance :: EU Idle */ +static float +hsw__sampler_balance__eu_idle__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: 100 $EuActive $EuStall FADD FSUB */ + double tmp0 = hsw__sampler_balance__eu_active__read(brw, query, accumulator) + hsw__sampler_balance__eu_stall__read(brw, query, accumulator); + double tmp1 = 100 - tmp0; + + return tmp1; +} + +/* Metric set SamplerBalance :: FS AVG Stall per Thread */ +#define hsw__sampler_balance__ps_eu_stall_per_thread__read \ + hsw__render_basic__ps_eu_stall_per_thread__read + +/* Metric set SamplerBalance :: VS AVG Stall per Thread */ +#define hsw__sampler_balance__vs_eu_stall_per_thread__read \ + hsw__render_basic__vs_eu_stall_per_thread__read + +/* Metric set SamplerBalance :: GPU Busy */ +static float +hsw__sampler_balance__gpu_busy__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 41 READ 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 41]; + uint64_t tmp1 = tmp0 * 100; + double tmp2 = tmp1; + double tmp3 = hsw__sampler_balance__gpu_core_clocks__read(brw, query, accumulator); + double tmp4 = tmp3 ? tmp2 / tmp3 : 0; + + return tmp4; +} + +/* Metric set SamplerBalance :: FS AVG Active per Thread */ +#define hsw__sampler_balance__ps_eu_active_per_thread__read \ + hsw__render_basic__ps_eu_active_per_thread__read + +/* Metric set SamplerBalance :: Early Depth Test Fails */ +#define hsw__sampler_balance__early_depth_test_fails__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set SamplerBalance :: TCS Duration */ +static uint64_t +hsw__sampler_balance__hs_duration__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 7 READ A 0 READ UMUL A 2 READ A 7 READ UADD A 12 READ UADD A 17 READ UADD A 22 READ UADD A 27 READ UADD UDIV A 8 READ A 1 READ UMUL A 3 READ A 8 READ UADD A 13 READ UADD A 18 READ UADD A 23 READ UADD A 28 READ UADD UDIV UADD $GpuTime UMUL $GpuCoreClocks $EuCoresTotalCount UMUL 1000 UMUL UDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 7]; + uint64_t tmp1 = accumulator[query->a_offset + 0]; + uint64_t tmp2 = tmp0 * tmp1; + uint64_t tmp3 = accumulator[query->a_offset + 2]; + uint64_t tmp4 = accumulator[query->a_offset + 7]; + uint64_t tmp5 = tmp3 + tmp4; + uint64_t tmp6 = accumulator[query->a_offset + 12]; + uint64_t tmp7 = tmp5 + tmp6; + uint64_t tmp8 = accumulator[query->a_offset + 17]; + uint64_t tmp9 = tmp7 + tmp8; + uint64_t tmp10 = accumulator[query->a_offset + 22]; + uint64_t tmp11 = tmp9 + tmp10; + uint64_t tmp12 = accumulator[query->a_offset + 27]; + uint64_t tmp13 = tmp11 + tmp12; + uint64_t tmp14 = tmp2; + uint64_t tmp15 = tmp13; + uint64_t tmp16 = tmp15 ? tmp14 / tmp15 : 0; + uint64_t tmp17 = accumulator[query->a_offset + 8]; + uint64_t tmp18 = accumulator[query->a_offset + 1]; + uint64_t tmp19 = tmp17 * tmp18; + uint64_t tmp20 = accumulator[query->a_offset + 3]; + uint64_t tmp21 = accumulator[query->a_offset + 8]; + uint64_t tmp22 = tmp20 + tmp21; + uint64_t tmp23 = accumulator[query->a_offset + 13]; + uint64_t tmp24 = tmp22 + tmp23; + uint64_t tmp25 = accumulator[query->a_offset + 18]; + uint64_t tmp26 = tmp24 + tmp25; + uint64_t tmp27 = accumulator[query->a_offset + 23]; + uint64_t tmp28 = tmp26 + tmp27; + uint64_t tmp29 = accumulator[query->a_offset + 28]; + uint64_t tmp30 = tmp28 + tmp29; + uint64_t tmp31 = tmp19; + uint64_t tmp32 = tmp30; + uint64_t tmp33 = tmp32 ? tmp31 / tmp32 : 0; + uint64_t tmp34 = tmp16 + tmp33; + uint64_t tmp35 = tmp34 * hsw__sampler_balance__gpu_time__read(brw, query, accumulator); + uint64_t tmp36 = hsw__sampler_balance__gpu_core_clocks__read(brw, query, accumulator) * brw->perfquery.sys_vars.n_eus; + uint64_t tmp37 = tmp36 * 1000; + uint64_t tmp38 = tmp35; + uint64_t tmp39 = tmp37; + uint64_t tmp40 = tmp39 ? tmp38 / tmp39 : 0; + + return tmp40; +} + +/* Metric set SamplerBalance :: TES AVG Stall per Thread */ +#define hsw__sampler_balance__ds_eu_stall_per_thread__read \ + hsw__render_basic__ds_eu_stall_per_thread__read + +/* Metric set SamplerBalance :: GS AVG Active per Thread */ +#define hsw__sampler_balance__gs_eu_active_per_thread__read \ + hsw__render_basic__gs_eu_active_per_thread__read + +/* Metric set SamplerBalance :: TCS Threads Dispatched */ +#define hsw__sampler_balance__hs_threads__read \ + hsw__render_basic__hs_threads__read + +/* Metric set SamplerBalance :: TCS AVG Stall per Thread */ +#define hsw__sampler_balance__hs_eu_stall_per_thread__read \ + hsw__render_basic__hs_eu_stall_per_thread__read + +/* Metric set SamplerBalance :: Samples Killed in FS */ +#define hsw__sampler_balance__samples_killed_in_ps__read \ + hsw__render_basic__samples_killed_in_ps__read + +/* Metric set SamplerBalance :: Late Depth Test Fails */ +#define hsw__sampler_balance__post_ps_depth_test_fails__read \ + hsw__render_basic__post_ps_depth_test_fails__read + +/* Metric set SamplerBalance :: TCS AVG Active per Thread */ +#define hsw__sampler_balance__hs_eu_active_per_thread__read \ + hsw__render_basic__hs_eu_active_per_thread__read + +/* Metric set SamplerBalance :: FS Duration */ +static uint64_t +hsw__sampler_balance__ps_duration__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 27 READ A 0 READ UMUL A 2 READ A 7 READ UADD A 12 READ UADD A 17 READ UADD A 22 READ UADD A 27 READ UADD UDIV A 28 READ A 1 READ UMUL A 3 READ A 8 READ UADD A 13 READ UADD A 18 READ UADD A 23 READ UADD A 28 READ UADD UDIV UADD $GpuTime UMUL $GpuCoreClocks $EuCoresTotalCount UMUL 1000 UMUL UDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 27]; + uint64_t tmp1 = accumulator[query->a_offset + 0]; + uint64_t tmp2 = tmp0 * tmp1; + uint64_t tmp3 = accumulator[query->a_offset + 2]; + uint64_t tmp4 = accumulator[query->a_offset + 7]; + uint64_t tmp5 = tmp3 + tmp4; + uint64_t tmp6 = accumulator[query->a_offset + 12]; + uint64_t tmp7 = tmp5 + tmp6; + uint64_t tmp8 = accumulator[query->a_offset + 17]; + uint64_t tmp9 = tmp7 + tmp8; + uint64_t tmp10 = accumulator[query->a_offset + 22]; + uint64_t tmp11 = tmp9 + tmp10; + uint64_t tmp12 = accumulator[query->a_offset + 27]; + uint64_t tmp13 = tmp11 + tmp12; + uint64_t tmp14 = tmp2; + uint64_t tmp15 = tmp13; + uint64_t tmp16 = tmp15 ? tmp14 / tmp15 : 0; + uint64_t tmp17 = accumulator[query->a_offset + 28]; + uint64_t tmp18 = accumulator[query->a_offset + 1]; + uint64_t tmp19 = tmp17 * tmp18; + uint64_t tmp20 = accumulator[query->a_offset + 3]; + uint64_t tmp21 = accumulator[query->a_offset + 8]; + uint64_t tmp22 = tmp20 + tmp21; + uint64_t tmp23 = accumulator[query->a_offset + 13]; + uint64_t tmp24 = tmp22 + tmp23; + uint64_t tmp25 = accumulator[query->a_offset + 18]; + uint64_t tmp26 = tmp24 + tmp25; + uint64_t tmp27 = accumulator[query->a_offset + 23]; + uint64_t tmp28 = tmp26 + tmp27; + uint64_t tmp29 = accumulator[query->a_offset + 28]; + uint64_t tmp30 = tmp28 + tmp29; + uint64_t tmp31 = tmp19; + uint64_t tmp32 = tmp30; + uint64_t tmp33 = tmp32 ? tmp31 / tmp32 : 0; + uint64_t tmp34 = tmp16 + tmp33; + uint64_t tmp35 = tmp34 * hsw__sampler_balance__gpu_time__read(brw, query, accumulator); + uint64_t tmp36 = hsw__sampler_balance__gpu_core_clocks__read(brw, query, accumulator) * brw->perfquery.sys_vars.n_eus; + uint64_t tmp37 = tmp36 * 1000; + uint64_t tmp38 = tmp35; + uint64_t tmp39 = tmp37; + uint64_t tmp40 = tmp39 ? tmp38 / tmp39 : 0; + + return tmp40; +} + +/* Metric set SamplerBalance :: Sampler L2 cache misses (ss1) */ +static uint64_t +hsw__sampler_balance__sampler1_l2_cache_misses__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 5 READ C 4 READ UADD */ + uint64_t tmp0 = accumulator[query->c_offset + 5]; + uint64_t tmp1 = accumulator[query->c_offset + 4]; + uint64_t tmp2 = tmp0 + tmp1; + + return tmp2; +} + +/* Metric set SamplerBalance :: Early Hi-Depth Test Fails */ +#define hsw__sampler_balance__hi_depth_test_fails__read \ + hsw__render_basic__hi_depth_test_fails__read + +/* Metric set SamplerBalance :: CS AVG Stall per Thread */ +#define hsw__sampler_balance__cs_eu_stall_per_thread__read \ + hsw__render_basic__cs_eu_stall_per_thread__read + +/* Metric set SamplerBalance :: Late Stencil Test Fails */ +#define hsw__sampler_balance__post_ps_stencil_test_fails__read \ + hsw__render_basic__post_ps_stencil_test_fails__read + +/* Metric set SamplerBalance :: Sampler L2 cache misses (ss0) */ +static uint64_t +hsw__sampler_balance__sampler0_l2_cache_misses__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 7 READ C 6 READ UADD */ + uint64_t tmp0 = accumulator[query->c_offset + 7]; + uint64_t tmp1 = accumulator[query->c_offset + 6]; + uint64_t tmp2 = tmp0 + tmp1; + + return tmp2; +} + +/* Metric set SamplerBalance :: VS AVG Active per Thread */ +#define hsw__sampler_balance__vs_eu_active_per_thread__read \ + hsw__render_basic__vs_eu_active_per_thread__read + +/* Metric set SamplerBalance :: VS Duration */ +static uint64_t +hsw__sampler_balance__vs_duration__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 2 READ A 0 READ UMUL A 2 READ A 7 READ UADD A 12 READ UADD A 17 READ UADD A 22 READ UADD A 27 READ UADD UDIV A 3 READ A 1 READ UMUL A 3 READ A 8 READ UADD A 13 READ UADD A 18 READ UADD A 23 READ UADD A 28 READ UADD UDIV UADD $GpuTime UMUL $GpuCoreClocks $EuCoresTotalCount UMUL 1000 UMUL UDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 2]; + uint64_t tmp1 = accumulator[query->a_offset + 0]; + uint64_t tmp2 = tmp0 * tmp1; + uint64_t tmp3 = accumulator[query->a_offset + 2]; + uint64_t tmp4 = accumulator[query->a_offset + 7]; + uint64_t tmp5 = tmp3 + tmp4; + uint64_t tmp6 = accumulator[query->a_offset + 12]; + uint64_t tmp7 = tmp5 + tmp6; + uint64_t tmp8 = accumulator[query->a_offset + 17]; + uint64_t tmp9 = tmp7 + tmp8; + uint64_t tmp10 = accumulator[query->a_offset + 22]; + uint64_t tmp11 = tmp9 + tmp10; + uint64_t tmp12 = accumulator[query->a_offset + 27]; + uint64_t tmp13 = tmp11 + tmp12; + uint64_t tmp14 = tmp2; + uint64_t tmp15 = tmp13; + uint64_t tmp16 = tmp15 ? tmp14 / tmp15 : 0; + uint64_t tmp17 = accumulator[query->a_offset + 3]; + uint64_t tmp18 = accumulator[query->a_offset + 1]; + uint64_t tmp19 = tmp17 * tmp18; + uint64_t tmp20 = accumulator[query->a_offset + 3]; + uint64_t tmp21 = accumulator[query->a_offset + 8]; + uint64_t tmp22 = tmp20 + tmp21; + uint64_t tmp23 = accumulator[query->a_offset + 13]; + uint64_t tmp24 = tmp22 + tmp23; + uint64_t tmp25 = accumulator[query->a_offset + 18]; + uint64_t tmp26 = tmp24 + tmp25; + uint64_t tmp27 = accumulator[query->a_offset + 23]; + uint64_t tmp28 = tmp26 + tmp27; + uint64_t tmp29 = accumulator[query->a_offset + 28]; + uint64_t tmp30 = tmp28 + tmp29; + uint64_t tmp31 = tmp19; + uint64_t tmp32 = tmp30; + uint64_t tmp33 = tmp32 ? tmp31 / tmp32 : 0; + uint64_t tmp34 = tmp16 + tmp33; + uint64_t tmp35 = tmp34 * hsw__sampler_balance__gpu_time__read(brw, query, accumulator); + uint64_t tmp36 = hsw__sampler_balance__gpu_core_clocks__read(brw, query, accumulator) * brw->perfquery.sys_vars.n_eus; + uint64_t tmp37 = tmp36 * 1000; + uint64_t tmp38 = tmp35; + uint64_t tmp39 = tmp37; + uint64_t tmp40 = tmp39 ? tmp38 / tmp39 : 0; + + return tmp40; +} + +/* Metric set SamplerBalance :: Samples Written */ +#define hsw__sampler_balance__samples_written__read \ + hsw__render_basic__samples_written__read + +/* Render Metrics Basic Gen8 :: GPU Core Clocks */ +static uint64_t +bdw__render_basic__gpu_core_clocks__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: GPU_CLOCK 0 READ */ + uint64_t tmp0 = accumulator[query->gpu_clock_offset + 0]; + + return tmp0; +} + +/* Render Metrics Basic Gen8 :: EU Active */ +static float +bdw__render_basic__eu_active__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 7 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 7]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = bdw__render_basic__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Render Metrics Basic Gen8 :: L3 Misses */ +#define bdw__render_basic__l3_misses__read \ + hsw__compute_extended__typed_atomics0__read + +/* Render Metrics Basic Gen8 :: GTI L3 Throughput */ +#define bdw__render_basic__gti_l3_throughput__read \ + hsw__render_basic__gti_l3_throughput__read + +/* Render Metrics Basic Gen8 :: EU Both FPU Pipes Active */ +static float +bdw__render_basic__eu_fpu_both_active__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 9 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 9]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = bdw__render_basic__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Render Metrics Basic Gen8 :: Sampler Cache Misses */ +static uint64_t +bdw__render_basic__sampler_l1_misses__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 4 READ B 5 READ UADD 8 UMUL */ + uint64_t tmp0 = accumulator[query->b_offset + 4]; + uint64_t tmp1 = accumulator[query->b_offset + 5]; + uint64_t tmp2 = tmp0 + tmp1; + uint64_t tmp3 = tmp2 * 8; + + return tmp3; +} + +/* Render Metrics Basic Gen8 :: VS Send Pipe Active */ +static float +bdw__render_basic__vs_send_active__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 12 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 12]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = bdw__render_basic__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Render Metrics Basic Gen8 :: Sampler 1 Bottleneck */ +static float +bdw__render_basic__sampler1_bottleneck__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 3 READ 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->b_offset + 3]; + uint64_t tmp1 = tmp0 * 100; + double tmp2 = tmp1; + double tmp3 = bdw__render_basic__gpu_core_clocks__read(brw, query, accumulator); + double tmp4 = tmp3 ? tmp2 / tmp3 : 0; + + return tmp4; +} + +/* Render Metrics Basic Gen8 :: VS FPU1 Pipe Active */ +static float +bdw__render_basic__vs_fpu1_active__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 11 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 11]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = bdw__render_basic__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Render Metrics Basic Gen8 :: GS Threads Dispatched */ +#define bdw__render_basic__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Render Metrics Basic Gen8 :: L3 Sampler Throughput */ +static uint64_t +bdw__render_basic__l3_sampler_throughput__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $SamplerL1Misses 64 UMUL */ + uint64_t tmp0 = bdw__render_basic__sampler_l1_misses__read(brw, query, accumulator) * 64; + + return tmp0; +} + +/* Render Metrics Basic Gen8 :: Early Hi-Depth Test Fails */ +static uint64_t +bdw__render_basic__hi_depth_test_fails__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 22 READ 4 UMUL */ + uint64_t tmp0 = accumulator[query->a_offset + 22]; + uint64_t tmp1 = tmp0 * 4; + + return tmp1; +} + +/* Render Metrics Basic Gen8 :: FS Both FPU Active */ +static float +bdw__render_basic__ps_eu_both_fpu_active__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 18 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 18]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = bdw__render_basic__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Render Metrics Basic Gen8 :: VS Threads Dispatched */ +static uint64_t +bdw__render_basic__vs_threads__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 1 READ */ + uint64_t tmp0 = accumulator[query->a_offset + 1]; + + return tmp0; +} + +/* Render Metrics Basic Gen8 :: FS Threads Dispatched */ +static uint64_t +bdw__render_basic__ps_threads__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 6 READ */ + uint64_t tmp0 = accumulator[query->a_offset + 6]; + + return tmp0; +} + +/* Render Metrics Basic Gen8 :: Sampler 0 Busy */ +static float +bdw__render_basic__sampler0_busy__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 0 READ 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->b_offset + 0]; + uint64_t tmp1 = tmp0 * 100; + double tmp2 = tmp1; + double tmp3 = bdw__render_basic__gpu_core_clocks__read(brw, query, accumulator); + double tmp4 = tmp3 ? tmp2 / tmp3 : 0; + + return tmp4; +} + +/* Render Metrics Basic Gen8 :: Sampler 1 Busy */ +static float +bdw__render_basic__sampler1_busy__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 1 READ 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->b_offset + 1]; + uint64_t tmp1 = tmp0 * 100; + double tmp2 = tmp1; + double tmp3 = bdw__render_basic__gpu_core_clocks__read(brw, query, accumulator); + double tmp4 = tmp3 ? tmp2 / tmp3 : 0; + + return tmp4; +} + +/* Render Metrics Basic Gen8 :: Samplers Busy */ +static float +bdw__render_basic__samplers_busy__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $Sampler0Busy $Sampler1Busy FMAX */ + double tmp0 = bdw__render_basic__sampler0_busy__read(brw, query, accumulator); + double tmp1 = bdw__render_basic__sampler1_busy__read(brw, query, accumulator); + double tmp2 = MAX(tmp0, tmp1); + + return tmp2; +} + +/* Render Metrics Basic Gen8 :: GTI Fixed Pipe Throughput */ +static uint64_t +bdw__render_basic__gti_vf_throughput__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 6 READ B 7 READ UADD 64 UMUL */ + uint64_t tmp0 = accumulator[query->b_offset + 6]; + uint64_t tmp1 = accumulator[query->b_offset + 7]; + uint64_t tmp2 = tmp0 + tmp1; + uint64_t tmp3 = tmp2 * 64; + + return tmp3; +} + +/* Render Metrics Basic Gen8 :: Shader Barrier Messages */ +#define bdw__render_basic__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Render Metrics Basic Gen8 :: Sampler 0 Bottleneck */ +static float +bdw__render_basic__sampler0_bottleneck__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 2 READ 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->b_offset + 2]; + uint64_t tmp1 = tmp0 * 100; + double tmp2 = tmp1; + double tmp3 = bdw__render_basic__gpu_core_clocks__read(brw, query, accumulator); + double tmp4 = tmp3 ? tmp2 / tmp3 : 0; + + return tmp4; +} + +/* Render Metrics Basic Gen8 :: Sampler Texels */ +static uint64_t +bdw__render_basic__sampler_texels__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 28 READ 4 UMUL */ + uint64_t tmp0 = accumulator[query->a_offset + 28]; + uint64_t tmp1 = tmp0 * 4; + + return tmp1; +} + +/* Render Metrics Basic Gen8 :: Pixels Failing Tests */ +static uint64_t +bdw__render_basic__pixels_failing_post_ps_tests__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 25 READ 4 UMUL */ + uint64_t tmp0 = accumulator[query->a_offset + 25]; + uint64_t tmp1 = tmp0 * 4; + + return tmp1; +} + +/* Render Metrics Basic Gen8 :: GPU Time Elapsed */ +#define bdw__render_basic__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Render Metrics Basic Gen8 :: AVG GPU Core Frequency */ +static uint64_t +bdw__render_basic__avg_gpu_core_frequency__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $GpuCoreClocks 1000000000 UMUL $GpuTime UDIV */ + uint64_t tmp0 = bdw__render_basic__gpu_core_clocks__read(brw, query, accumulator) * 1000000000; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = bdw__render_basic__gpu_time__read(brw, query, accumulator); + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + + return tmp3; +} + +/* Render Metrics Basic Gen8 :: AVG GPU Core Frequency */ +#define bdw__render_basic__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Render Metrics Basic Gen8 :: Sampler Texels Misses */ +static uint64_t +bdw__render_basic__sampler_texel_misses__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 29 READ 4 UMUL */ + uint64_t tmp0 = accumulator[query->a_offset + 29]; + uint64_t tmp1 = tmp0 * 4; + + return tmp1; +} + +/* Render Metrics Basic Gen8 :: CS Threads Dispatched */ +static uint64_t +bdw__render_basic__cs_threads__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 4 READ */ + uint64_t tmp0 = accumulator[query->a_offset + 4]; + + return tmp0; +} + +/* Render Metrics Basic Gen8 :: Shader Memory Accesses */ +static uint64_t +bdw__render_basic__shader_memory_accesses__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 32 READ */ + uint64_t tmp0 = accumulator[query->a_offset + 32]; + + return tmp0; +} + +/* Render Metrics Basic Gen8 :: L3 Lookup Accesses w/o IC */ +static uint64_t +bdw__render_basic__l3_lookups__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $SamplerL1Misses $ShaderMemoryAccesses UADD */ + uint64_t tmp0 = bdw__render_basic__sampler_l1_misses__read(brw, query, accumulator) + bdw__render_basic__shader_memory_accesses__read(brw, query, accumulator); + + return tmp0; +} + +/* Render Metrics Basic Gen8 :: SLM Bytes Read */ +static uint64_t +bdw__render_basic__slm_bytes_read__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 30 READ 64 UMUL */ + uint64_t tmp0 = accumulator[query->a_offset + 30]; + uint64_t tmp1 = tmp0 * 64; + + return tmp1; +} + +/* Render Metrics Basic Gen8 :: GTI Read Throughput */ +static uint64_t +bdw__render_basic__gti_read_throughput__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 6 READ 64 UMUL */ + uint64_t tmp0 = accumulator[query->c_offset + 6]; + uint64_t tmp1 = tmp0 * 64; + + return tmp1; +} + +/* Render Metrics Basic Gen8 :: PS FPU1 Pipe Active */ +static float +bdw__render_basic__ps_fpu1_active__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 16 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 16]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = bdw__render_basic__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Render Metrics Basic Gen8 :: PS Send Pipeline Active */ +static float +bdw__render_basic__ps_send_active__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 17 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 17]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = bdw__render_basic__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Render Metrics Basic Gen8 :: Rasterized Pixels */ +static uint64_t +bdw__render_basic__rasterized_pixels__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 21 READ 4 UMUL */ + uint64_t tmp0 = accumulator[query->a_offset + 21]; + uint64_t tmp1 = tmp0 * 4; + + return tmp1; +} + +/* Render Metrics Basic Gen8 :: GPU Busy */ +static float +bdw__render_basic__gpu_busy__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 0 READ 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 0]; + uint64_t tmp1 = tmp0 * 100; + double tmp2 = tmp1; + double tmp3 = bdw__render_basic__gpu_core_clocks__read(brw, query, accumulator); + double tmp4 = tmp3 ? tmp2 / tmp3 : 0; + + return tmp4; +} + +/* Render Metrics Basic Gen8 :: GTI Depth Throughput */ +static uint64_t +bdw__render_basic__gti_depth_throughput__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 0 READ C 1 READ UADD 64 UMUL */ + uint64_t tmp0 = accumulator[query->c_offset + 0]; + uint64_t tmp1 = accumulator[query->c_offset + 1]; + uint64_t tmp2 = tmp0 + tmp1; + uint64_t tmp3 = tmp2 * 64; + + return tmp3; +} + +/* Render Metrics Basic Gen8 :: VS FPU0 Pipe Active */ +static float +bdw__render_basic__vs_fpu0_active__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 10 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 10]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = bdw__render_basic__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Render Metrics Basic Gen8 :: PS FPU0 Pipe Active */ +static float +bdw__render_basic__ps_fpu0_active__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 15 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 15]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = bdw__render_basic__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Render Metrics Basic Gen8 :: DS Threads Dispatched */ +static uint64_t +bdw__render_basic__ds_threads__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 3 READ */ + uint64_t tmp0 = accumulator[query->a_offset + 3]; + + return tmp0; +} + +/* Render Metrics Basic Gen8 :: Samples Written */ +static uint64_t +bdw__render_basic__samples_written__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 26 READ 4 UMUL */ + uint64_t tmp0 = accumulator[query->a_offset + 26]; + uint64_t tmp1 = tmp0 * 4; + + return tmp1; +} + +/* Render Metrics Basic Gen8 :: EU Stall */ +static float +bdw__render_basic__eu_stall__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 8 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 8]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = bdw__render_basic__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Render Metrics Basic Gen8 :: Samples Blended */ +static uint64_t +bdw__render_basic__samples_blended__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 27 READ 4 UMUL */ + uint64_t tmp0 = accumulator[query->a_offset + 27]; + uint64_t tmp1 = tmp0 * 4; + + return tmp1; +} + +/* Render Metrics Basic Gen8 :: Early Depth Test Fails */ +static uint64_t +bdw__render_basic__early_depth_test_fails__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 23 READ 4 UMUL */ + uint64_t tmp0 = accumulator[query->a_offset + 23]; + uint64_t tmp1 = tmp0 * 4; + + return tmp1; +} + +/* Render Metrics Basic Gen8 :: Samplers Bottleneck */ +static float +bdw__render_basic__sampler_bottleneck__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $Sampler0Bottleneck $Sampler1Bottleneck FMAX */ + double tmp0 = bdw__render_basic__sampler0_bottleneck__read(brw, query, accumulator); + double tmp1 = bdw__render_basic__sampler1_bottleneck__read(brw, query, accumulator); + double tmp2 = MAX(tmp0, tmp1); + + return tmp2; +} + +/* Render Metrics Basic Gen8 :: GTI HDC TLB Lookup Throughput */ +static uint64_t +bdw__render_basic__gti_hdc_lookups_throughput__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 5 READ 64 UMUL */ + uint64_t tmp0 = accumulator[query->c_offset + 5]; + uint64_t tmp1 = tmp0 * 64; + + return tmp1; +} + +/* Render Metrics Basic Gen8 :: GTI RCC Throughput */ +static uint64_t +bdw__render_basic__gti_rcc_throughput__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 2 READ C 3 READ UADD 64 UMUL */ + uint64_t tmp0 = accumulator[query->c_offset + 2]; + uint64_t tmp1 = accumulator[query->c_offset + 3]; + uint64_t tmp2 = tmp0 + tmp1; + uint64_t tmp3 = tmp2 * 64; + + return tmp3; +} + +/* Render Metrics Basic Gen8 :: HS Threads Dispatched */ +static uint64_t +bdw__render_basic__hs_threads__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 2 READ */ + uint64_t tmp0 = accumulator[query->a_offset + 2]; + + return tmp0; +} + +/* Render Metrics Basic Gen8 :: GTI Write Throughput */ +#define bdw__render_basic__gti_write_throughput__read \ + hsw__render_basic__gti_write_throughput__read + +/* Render Metrics Basic Gen8 :: SLM Bytes Written */ +static uint64_t +bdw__render_basic__slm_bytes_written__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 31 READ 64 UMUL */ + uint64_t tmp0 = accumulator[query->a_offset + 31]; + uint64_t tmp1 = tmp0 * 64; + + return tmp1; +} + +/* Render Metrics Basic Gen8 :: L3 Shader Throughput */ +static uint64_t +bdw__render_basic__l3_shader_throughput__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 30 READ A 31 READ $ShaderMemoryAccesses UADD UADD 64 UMUL */ + uint64_t tmp0 = accumulator[query->a_offset + 30]; + uint64_t tmp1 = accumulator[query->a_offset + 31]; + uint64_t tmp2 = tmp1 + bdw__render_basic__shader_memory_accesses__read(brw, query, accumulator); + uint64_t tmp3 = tmp0 + tmp2; + uint64_t tmp4 = tmp3 * 64; + + return tmp4; +} + +/* Render Metrics Basic Gen8 :: Samples Killed in FS */ +static uint64_t +bdw__render_basic__samples_killed_in_ps__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 24 READ 4 UMUL */ + uint64_t tmp0 = accumulator[query->a_offset + 24]; + uint64_t tmp1 = tmp0 * 4; + + return tmp1; +} + +/* Render Metrics Basic Gen8 :: Shader Atomic Memory Accesses */ +static uint64_t +bdw__render_basic__shader_atomics__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 34 READ */ + uint64_t tmp0 = accumulator[query->a_offset + 34]; + + return tmp0; +} + +/* Compute Metrics Basic Gen8 :: GPU Core Clocks */ +#define bdw__compute_basic__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Basic Gen8 :: EU Active */ +#define bdw__compute_basic__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Compute Metrics Basic Gen8 :: Untyped Bytes Read */ +static uint64_t +bdw__compute_basic__untyped_bytes_read__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 6 READ B 7 READ C 0 READ UADD UADD $EuSlicesTotalCount 64 UMUL UMUL */ + uint64_t tmp0 = accumulator[query->b_offset + 6]; + uint64_t tmp1 = accumulator[query->b_offset + 7]; + uint64_t tmp2 = accumulator[query->c_offset + 0]; + uint64_t tmp3 = tmp1 + tmp2; + uint64_t tmp4 = tmp0 + tmp3; + uint64_t tmp5 = brw->perfquery.sys_vars.n_eu_slices * 64; + uint64_t tmp6 = tmp4 * tmp5; + + return tmp6; +} + +/* Compute Metrics Basic Gen8 :: EU Both FPU Pipes Active */ +#define bdw__compute_basic__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Compute Metrics Basic Gen8 :: Typed Bytes Written */ +static uint64_t +bdw__compute_basic__typed_bytes_written__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 3 READ B 4 READ B 5 READ UADD UADD $EuSlicesTotalCount 64 UMUL UMUL */ + uint64_t tmp0 = accumulator[query->b_offset + 3]; + uint64_t tmp1 = accumulator[query->b_offset + 4]; + uint64_t tmp2 = accumulator[query->b_offset + 5]; + uint64_t tmp3 = tmp1 + tmp2; + uint64_t tmp4 = tmp0 + tmp3; + uint64_t tmp5 = brw->perfquery.sys_vars.n_eu_slices * 64; + uint64_t tmp6 = tmp4 * tmp5; + + return tmp6; +} + +/* Compute Metrics Basic Gen8 :: EU FPU0 Pipe Active */ +#define bdw__compute_basic__fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Compute Metrics Basic Gen8 :: EU FPU1 Pipe Active */ +#define bdw__compute_basic__fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Compute Metrics Basic Gen8 :: EU AVG IPC Rate */ +static float +bdw__compute_basic__eu_avg_ipc_rate__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 9 READ A 10 READ A 11 READ UADD A 9 READ USUB FDIV 1 FADD */ + uint64_t tmp0 = accumulator[query->a_offset + 9]; + uint64_t tmp1 = accumulator[query->a_offset + 10]; + uint64_t tmp2 = accumulator[query->a_offset + 11]; + uint64_t tmp3 = tmp1 + tmp2; + uint64_t tmp4 = accumulator[query->a_offset + 9]; + uint64_t tmp5 = tmp3 - tmp4; + double tmp6 = tmp0; + double tmp7 = tmp5; + double tmp8 = tmp7 ? tmp6 / tmp7 : 0; + double tmp9 = tmp8 + 1; + + return tmp9; +} + +/* Compute Metrics Basic Gen8 :: GS Threads Dispatched */ +#define bdw__compute_basic__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Compute Metrics Basic Gen8 :: Early Hi-Depth Test Fails */ +#define bdw__compute_basic__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Compute Metrics Basic Gen8 :: VS Threads Dispatched */ +#define bdw__compute_basic__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Compute Metrics Basic Gen8 :: FS Threads Dispatched */ +#define bdw__compute_basic__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Compute Metrics Basic Gen8 :: Shader Barrier Messages */ +#define bdw__compute_basic__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Compute Metrics Basic Gen8 :: Sampler Texels */ +#define bdw__compute_basic__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Compute Metrics Basic Gen8 :: Pixels Failing Tests */ +#define bdw__compute_basic__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Compute Metrics Basic Gen8 :: GPU Time Elapsed */ +#define bdw__compute_basic__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics Basic Gen8 :: AVG GPU Core Frequency */ +#define bdw__compute_basic__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics Basic Gen8 :: AVG GPU Core Frequency */ +#define bdw__compute_basic__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics Basic Gen8 :: Sampler Texels Misses */ +#define bdw__compute_basic__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Compute Metrics Basic Gen8 :: CS Threads Dispatched */ +#define bdw__compute_basic__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Compute Metrics Basic Gen8 :: SLM Bytes Read */ +#define bdw__compute_basic__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Compute Metrics Basic Gen8 :: GTI Read Throughput */ +#define bdw__compute_basic__gti_read_throughput__read \ + hsw__render_basic__gti_l3_throughput__read + +/* Compute Metrics Basic Gen8 :: Untyped Writes */ +static uint64_t +bdw__compute_basic__untyped_bytes_written__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 1 READ C 2 READ C 3 READ UADD UADD $EuSlicesTotalCount 64 UMUL UMUL */ + uint64_t tmp0 = accumulator[query->c_offset + 1]; + uint64_t tmp1 = accumulator[query->c_offset + 2]; + uint64_t tmp2 = accumulator[query->c_offset + 3]; + uint64_t tmp3 = tmp1 + tmp2; + uint64_t tmp4 = tmp0 + tmp3; + uint64_t tmp5 = brw->perfquery.sys_vars.n_eu_slices * 64; + uint64_t tmp6 = tmp4 * tmp5; + + return tmp6; +} + +/* Compute Metrics Basic Gen8 :: GPU Busy */ +#define bdw__compute_basic__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Compute Metrics Basic Gen8 :: Rasterized Pixels */ +#define bdw__compute_basic__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Compute Metrics Basic Gen8 :: Typed Bytes Read */ +static uint64_t +bdw__compute_basic__typed_bytes_read__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 0 READ B 1 READ B 2 READ UADD UADD $EuSlicesTotalCount 64 UMUL UMUL */ + uint64_t tmp0 = accumulator[query->b_offset + 0]; + uint64_t tmp1 = accumulator[query->b_offset + 1]; + uint64_t tmp2 = accumulator[query->b_offset + 2]; + uint64_t tmp3 = tmp1 + tmp2; + uint64_t tmp4 = tmp0 + tmp3; + uint64_t tmp5 = brw->perfquery.sys_vars.n_eu_slices * 64; + uint64_t tmp6 = tmp4 * tmp5; + + return tmp6; +} + +/* Compute Metrics Basic Gen8 :: DS Threads Dispatched */ +#define bdw__compute_basic__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Compute Metrics Basic Gen8 :: EU Thread Occupancy */ +static float +bdw__compute_basic__eu_thread_occupancy__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 13 READ 8 UMUL $EuCoresTotalCount UDIV $EuThreadsCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 13]; + uint64_t tmp1 = tmp0 * 8; + uint64_t tmp2 = tmp1; + uint64_t tmp3 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp4 = tmp3 ? tmp2 / tmp3 : 0; + uint64_t tmp5 = tmp4; + uint64_t tmp6 = brw->perfquery.sys_vars.eu_threads_count; + uint64_t tmp7 = tmp6 ? tmp5 / tmp6 : 0; + uint64_t tmp8 = tmp7 * 100; + double tmp9 = tmp8; + double tmp10 = bdw__compute_basic__gpu_core_clocks__read(brw, query, accumulator); + double tmp11 = tmp10 ? tmp9 / tmp10 : 0; + + return tmp11; +} + +/* Compute Metrics Basic Gen8 :: EU Stall */ +#define bdw__compute_basic__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics Basic Gen8 :: Samples Blended */ +#define bdw__compute_basic__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Compute Metrics Basic Gen8 :: Early Depth Test Fails */ +#define bdw__compute_basic__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Compute Metrics Basic Gen8 :: Shader Memory Accesses */ +#define bdw__compute_basic__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Compute Metrics Basic Gen8 :: HS Threads Dispatched */ +#define bdw__compute_basic__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Compute Metrics Basic Gen8 :: GTI Write Throughput */ +#define bdw__compute_basic__gti_write_throughput__read \ + bdw__render_basic__gti_hdc_lookups_throughput__read + +/* Compute Metrics Basic Gen8 :: SLM Bytes Written */ +#define bdw__compute_basic__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Compute Metrics Basic Gen8 :: L3 Shader Throughput */ +#define bdw__compute_basic__l3_shader_throughput__read \ + bdw__render_basic__l3_shader_throughput__read + +/* Compute Metrics Basic Gen8 :: Samples Killed in FS */ +#define bdw__compute_basic__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Compute Metrics Basic Gen8 :: Samples Written */ +#define bdw__compute_basic__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Compute Metrics Basic Gen8 :: Shader Atomic Memory Accesses */ +#define bdw__compute_basic__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Basic Gen8 :: EU Send Pipe Active */ +#define bdw__compute_basic__eu_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Render Metrics for 3D Pipeline Profile :: GPU Core Clocks */ +#define bdw__render_pipe_profile__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Render Metrics for 3D Pipeline Profile :: EU Active */ +#define bdw__render_pipe_profile__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Render Metrics for 3D Pipeline Profile :: VS Bottleneck */ +#define bdw__render_pipe_profile__vs_bottleneck__read \ + bdw__render_basic__sampler0_busy__read + +/* Render Metrics for 3D Pipeline Profile :: Hi-Depth Bottleneck */ +static float +bdw__render_pipe_profile__hi_depth_bottleneck__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 6 READ 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->c_offset + 6]; + uint64_t tmp1 = tmp0 * 100; + double tmp2 = tmp1; + double tmp3 = bdw__render_pipe_profile__gpu_core_clocks__read(brw, query, accumulator); + double tmp4 = tmp3 ? tmp2 / tmp3 : 0; + + return tmp4; +} + +/* Render Metrics for 3D Pipeline Profile :: GS Bottleneck */ +#define bdw__render_pipe_profile__gs_bottleneck__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile :: GS Threads Dispatched */ +#define bdw__render_pipe_profile__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Render Metrics for 3D Pipeline Profile :: Early Hi-Depth Test Fails */ +#define bdw__render_pipe_profile__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Render Metrics for 3D Pipeline Profile :: VS Threads Dispatched */ +#define bdw__render_pipe_profile__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Render Metrics for 3D Pipeline Profile :: FS Threads Dispatched */ +#define bdw__render_pipe_profile__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Render Metrics for 3D Pipeline Profile :: BC Bottleneck */ +static float +bdw__render_pipe_profile__bc_bottleneck__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 7 READ 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->c_offset + 7]; + uint64_t tmp1 = tmp0 * 100; + double tmp2 = tmp1; + double tmp3 = bdw__render_pipe_profile__gpu_core_clocks__read(brw, query, accumulator); + double tmp4 = tmp3 ? tmp2 / tmp3 : 0; + + return tmp4; +} + +/* Render Metrics for 3D Pipeline Profile :: HS Stall */ +static float +bdw__render_pipe_profile__hs_stall__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 1 READ 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->c_offset + 1]; + uint64_t tmp1 = tmp0 * 100; + double tmp2 = tmp1; + double tmp3 = bdw__render_pipe_profile__gpu_core_clocks__read(brw, query, accumulator); + double tmp4 = tmp3 ? tmp2 / tmp3 : 0; + + return tmp4; +} + +/* Render Metrics for 3D Pipeline Profile :: Shader Barrier Messages */ +#define bdw__render_pipe_profile__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Render Metrics for 3D Pipeline Profile :: Sampler Texels */ +#define bdw__render_pipe_profile__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Render Metrics for 3D Pipeline Profile :: Pixels Failing Tests */ +#define bdw__render_pipe_profile__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Render Metrics for 3D Pipeline Profile :: GPU Time Elapsed */ +#define bdw__render_pipe_profile__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */ +#define bdw__render_pipe_profile__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */ +#define bdw__render_pipe_profile__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Render Metrics for 3D Pipeline Profile :: Sampler Texels Misses */ +#define bdw__render_pipe_profile__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Render Metrics for 3D Pipeline Profile :: CS Threads Dispatched */ +#define bdw__render_pipe_profile__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Render Metrics for 3D Pipeline Profile :: VF Bottleneck */ +static float +bdw__render_pipe_profile__vf_bottleneck__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 0 READ 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->c_offset + 0]; + uint64_t tmp1 = tmp0 * 100; + double tmp2 = tmp1; + double tmp3 = bdw__render_pipe_profile__gpu_core_clocks__read(brw, query, accumulator); + double tmp4 = tmp3 ? tmp2 / tmp3 : 0; + + return tmp4; +} + +/* Render Metrics for 3D Pipeline Profile :: SLM Bytes Read */ +#define bdw__render_pipe_profile__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Render Metrics for 3D Pipeline Profile :: Strip-Fans Bottleneck */ +static float +bdw__render_pipe_profile__sf_bottleneck__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 6 READ 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->b_offset + 6]; + uint64_t tmp1 = tmp0 * 100; + double tmp2 = tmp1; + double tmp3 = bdw__render_pipe_profile__gpu_core_clocks__read(brw, query, accumulator); + double tmp4 = tmp3 ? tmp2 / tmp3 : 0; + + return tmp4; +} + +/* Render Metrics for 3D Pipeline Profile :: Sampler Accesses */ +static uint64_t +bdw__render_pipe_profile__sampler_accesses__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 28 READ */ + uint64_t tmp0 = accumulator[query->a_offset + 28]; + + return tmp0; +} + +/* Render Metrics for 3D Pipeline Profile :: SF Stall */ +static float +bdw__render_pipe_profile__sf_stall__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 5 READ 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->c_offset + 5]; + uint64_t tmp1 = tmp0 * 100; + double tmp2 = tmp1; + double tmp3 = bdw__render_pipe_profile__gpu_core_clocks__read(brw, query, accumulator); + double tmp4 = tmp3 ? tmp2 / tmp3 : 0; + + return tmp4; +} + +/* Render Metrics for 3D Pipeline Profile :: GPU Busy */ +#define bdw__render_pipe_profile__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Render Metrics for 3D Pipeline Profile :: HS Bottleneck */ +#define bdw__render_pipe_profile__hs_bottleneck__read \ + bdw__render_basic__sampler1_busy__read + +/* Render Metrics for 3D Pipeline Profile :: CL Stall */ +static float +bdw__render_pipe_profile__cl_stall__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 4 READ 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->c_offset + 4]; + uint64_t tmp1 = tmp0 * 100; + double tmp2 = tmp1; + double tmp3 = bdw__render_pipe_profile__gpu_core_clocks__read(brw, query, accumulator); + double tmp4 = tmp3 ? tmp2 / tmp3 : 0; + + return tmp4; +} + +/* Render Metrics for 3D Pipeline Profile :: SO Bottleneck */ +static float +bdw__render_pipe_profile__so_bottleneck__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 4 READ 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->b_offset + 4]; + uint64_t tmp1 = tmp0 * 100; + double tmp2 = tmp1; + double tmp3 = bdw__render_pipe_profile__gpu_core_clocks__read(brw, query, accumulator); + double tmp4 = tmp3 ? tmp2 / tmp3 : 0; + + return tmp4; +} + +/* Render Metrics for 3D Pipeline Profile :: Rasterized Pixels */ +#define bdw__render_pipe_profile__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Render Metrics for 3D Pipeline Profile :: DS Threads Dispatched */ +#define bdw__render_pipe_profile__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Render Metrics for 3D Pipeline Profile :: Samples Written */ +#define bdw__render_pipe_profile__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Render Metrics for 3D Pipeline Profile :: DS Bottleneck */ +#define bdw__render_pipe_profile__ds_bottleneck__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile :: EU Stall */ +#define bdw__render_pipe_profile__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Render Metrics for 3D Pipeline Profile :: Clipper Bottleneck */ +static float +bdw__render_pipe_profile__cl_bottleneck__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 5 READ 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->b_offset + 5]; + uint64_t tmp1 = tmp0 * 100; + double tmp2 = tmp1; + double tmp3 = bdw__render_pipe_profile__gpu_core_clocks__read(brw, query, accumulator); + double tmp4 = tmp3 ? tmp2 / tmp3 : 0; + + return tmp4; +} + +/* Render Metrics for 3D Pipeline Profile :: DS Stall */ +static float +bdw__render_pipe_profile__ds_stall__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 2 READ 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->c_offset + 2]; + uint64_t tmp1 = tmp0 * 100; + double tmp2 = tmp1; + double tmp3 = bdw__render_pipe_profile__gpu_core_clocks__read(brw, query, accumulator); + double tmp4 = tmp3 ? tmp2 / tmp3 : 0; + + return tmp4; +} + +/* Render Metrics for 3D Pipeline Profile :: Early Depth Bottleneck */ +static float +bdw__render_pipe_profile__early_depth_bottleneck__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 7 READ 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->b_offset + 7]; + uint64_t tmp1 = tmp0 * 100; + double tmp2 = tmp1; + double tmp3 = bdw__render_pipe_profile__gpu_core_clocks__read(brw, query, accumulator); + double tmp4 = tmp3 ? tmp2 / tmp3 : 0; + + return tmp4; +} + +/* Render Metrics for 3D Pipeline Profile :: Samples Blended */ +#define bdw__render_pipe_profile__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Render Metrics for 3D Pipeline Profile :: Early Depth Test Fails */ +#define bdw__render_pipe_profile__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Render Metrics for 3D Pipeline Profile :: Shader Memory Accesses */ +#define bdw__render_pipe_profile__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Render Metrics for 3D Pipeline Profile :: HS Threads Dispatched */ +#define bdw__render_pipe_profile__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Render Metrics for 3D Pipeline Profile :: SLM Bytes Written */ +#define bdw__render_pipe_profile__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Render Metrics for 3D Pipeline Profile :: L3 Shader Throughput */ +#define bdw__render_pipe_profile__l3_shader_throughput__read \ + bdw__render_basic__l3_shader_throughput__read + +/* Render Metrics for 3D Pipeline Profile :: Samples Killed in FS */ +#define bdw__render_pipe_profile__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Render Metrics for 3D Pipeline Profile :: SO Stall */ +static float +bdw__render_pipe_profile__so_stall__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 3 READ 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->c_offset + 3]; + uint64_t tmp1 = tmp0 * 100; + double tmp2 = tmp1; + double tmp3 = bdw__render_pipe_profile__gpu_core_clocks__read(brw, query, accumulator); + double tmp4 = tmp3 ? tmp2 / tmp3 : 0; + + return tmp4; +} + +/* Render Metrics for 3D Pipeline Profile :: Shader Atomic Memory Accesses */ +#define bdw__render_pipe_profile__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Memory Reads Distribution Gen8 :: GPU Core Clocks */ +#define bdw__memory_reads__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Memory Reads Distribution Gen8 :: EU Active */ +#define bdw__memory_reads__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Memory Reads Distribution Gen8 :: GtiL3Bank0Reads */ +#define bdw__memory_reads__gti_l3_bank0_reads__read \ + hsw__compute_extended__typed_atomics0__read + +/* Memory Reads Distribution Gen8 :: GS Threads Dispatched */ +#define bdw__memory_reads__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Memory Reads Distribution Gen8 :: GtiRingAccesses */ +static uint64_t +bdw__memory_reads__gti_ring_accesses__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 3 READ 2 UMUL */ + uint64_t tmp0 = accumulator[query->c_offset + 3]; + uint64_t tmp1 = tmp0 * 2; + + return tmp1; +} + +/* Memory Reads Distribution Gen8 :: Early Hi-Depth Test Fails */ +#define bdw__memory_reads__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Memory Reads Distribution Gen8 :: VS Threads Dispatched */ +#define bdw__memory_reads__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Memory Reads Distribution Gen8 :: FS Threads Dispatched */ +#define bdw__memory_reads__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Memory Reads Distribution Gen8 :: GtiL3Bank3Reads */ +#define bdw__memory_reads__gti_l3_bank3_reads__read \ + hsw__memory_reads__gpu_core_clocks__read + +/* Memory Reads Distribution Gen8 :: Shader Barrier Messages */ +#define bdw__memory_reads__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Memory Reads Distribution Gen8 :: GtiRsMemoryReads */ +#define bdw__memory_reads__gti_rs_memory_reads__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Memory Reads Distribution Gen8 :: Sampler Texels */ +#define bdw__memory_reads__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Memory Reads Distribution Gen8 :: Pixels Failing Tests */ +#define bdw__memory_reads__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Memory Reads Distribution Gen8 :: GtiHizMemoryReads */ +#define bdw__memory_reads__gti_hiz_memory_reads__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* Memory Reads Distribution Gen8 :: GPU Time Elapsed */ +#define bdw__memory_reads__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Memory Reads Distribution Gen8 :: AVG GPU Core Frequency */ +#define bdw__memory_reads__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Memory Reads Distribution Gen8 :: AVG GPU Core Frequency */ +#define bdw__memory_reads__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Memory Reads Distribution Gen8 :: Sampler Texels Misses */ +#define bdw__memory_reads__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Memory Reads Distribution Gen8 :: GtiRccMemoryReads */ +#define bdw__memory_reads__gti_rcc_memory_reads__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* Memory Reads Distribution Gen8 :: CS Threads Dispatched */ +#define bdw__memory_reads__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Memory Reads Distribution Gen8 :: SLM Bytes Read */ +#define bdw__memory_reads__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Memory Reads Distribution Gen8 :: GtiL3Bank1Reads */ +#define bdw__memory_reads__gti_l3_bank1_reads__read \ + hsw__memory_reads__gti_memory_reads__read + +/* Memory Reads Distribution Gen8 :: GPU Busy */ +#define bdw__memory_reads__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Memory Reads Distribution Gen8 :: GtiCmdStreamerMemoryReads */ +#define bdw__memory_reads__gti_cmd_streamer_memory_reads__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* Memory Reads Distribution Gen8 :: GtiL3Bank2Reads */ +#define bdw__memory_reads__gti_l3_bank2_reads__read \ + hsw__memory_reads__llc_read_accesses__read + +/* Memory Reads Distribution Gen8 :: GtiMemoryReads */ +#define bdw__memory_reads__gti_memory_reads__read \ + hsw__compute_extended__typed_writes0__read + +/* Memory Reads Distribution Gen8 :: Rasterized Pixels */ +#define bdw__memory_reads__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Memory Reads Distribution Gen8 :: GtiRczMemoryReads */ +#define bdw__memory_reads__gti_rcz_memory_reads__read \ + hsw__compute_extended__gpu_clocks__read + +/* Memory Reads Distribution Gen8 :: DS Threads Dispatched */ +#define bdw__memory_reads__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Memory Reads Distribution Gen8 :: Samples Written */ +#define bdw__memory_reads__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Memory Reads Distribution Gen8 :: EU Stall */ +#define bdw__memory_reads__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Memory Reads Distribution Gen8 :: Samples Blended */ +#define bdw__memory_reads__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Memory Reads Distribution Gen8 :: Early Depth Test Fails */ +#define bdw__memory_reads__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Memory Reads Distribution Gen8 :: GtiMscMemoryReads */ +#define bdw__memory_reads__gti_msc_memory_reads__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* Memory Reads Distribution Gen8 :: GtiVfMemoryReads */ +#define bdw__memory_reads__gti_vf_memory_reads__read \ + hsw__compute_extended__eu_untyped_writes0__read + +/* Memory Reads Distribution Gen8 :: GtiStcMemoryReads */ +#define bdw__memory_reads__gti_stc_memory_reads__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* Memory Reads Distribution Gen8 :: Shader Memory Accesses */ +#define bdw__memory_reads__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Memory Reads Distribution Gen8 :: HS Threads Dispatched */ +#define bdw__memory_reads__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Memory Reads Distribution Gen8 :: SLM Bytes Written */ +#define bdw__memory_reads__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Memory Reads Distribution Gen8 :: L3 Shader Throughput */ +#define bdw__memory_reads__l3_shader_throughput__read \ + bdw__render_basic__l3_shader_throughput__read + +/* Memory Reads Distribution Gen8 :: Samples Killed in FS */ +#define bdw__memory_reads__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Memory Reads Distribution Gen8 :: GtiL3Reads */ +static uint64_t +bdw__memory_reads__gti_l3_reads__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $GtiL3Bank0Reads $GtiL3Bank1Reads $GtiL3Bank2Reads $GtiL3Bank3Reads UADD UADD UADD */ + uint64_t tmp0 = bdw__memory_reads__gti_l3_bank2_reads__read(brw, query, accumulator) + bdw__memory_reads__gti_l3_bank3_reads__read(brw, query, accumulator); + uint64_t tmp1 = bdw__memory_reads__gti_l3_bank1_reads__read(brw, query, accumulator) + tmp0; + uint64_t tmp2 = bdw__memory_reads__gti_l3_bank0_reads__read(brw, query, accumulator) + tmp1; + + return tmp2; +} + +/* Memory Reads Distribution Gen8 :: Shader Atomic Memory Accesses */ +#define bdw__memory_reads__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Memory Writes Distribution Gen8 :: GPU Core Clocks */ +#define bdw__memory_writes__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Memory Writes Distribution Gen8 :: EU Active */ +#define bdw__memory_writes__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Memory Writes Distribution Gen8 :: GtiMemoryWrites */ +#define bdw__memory_writes__gti_memory_writes__read \ + hsw__compute_extended__typed_writes0__read + +/* Memory Writes Distribution Gen8 :: GS Threads Dispatched */ +#define bdw__memory_writes__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Memory Writes Distribution Gen8 :: GtiRingAccesses */ +#define bdw__memory_writes__gti_ring_accesses__read \ + bdw__memory_reads__gti_ring_accesses__read + +/* Memory Writes Distribution Gen8 :: Early Hi-Depth Test Fails */ +#define bdw__memory_writes__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Memory Writes Distribution Gen8 :: VS Threads Dispatched */ +#define bdw__memory_writes__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Memory Writes Distribution Gen8 :: FS Threads Dispatched */ +#define bdw__memory_writes__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Memory Writes Distribution Gen8 :: GtiMscMemoryWrites */ +#define bdw__memory_writes__gti_msc_memory_writes__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* Memory Writes Distribution Gen8 :: Shader Barrier Messages */ +#define bdw__memory_writes__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Memory Writes Distribution Gen8 :: GtiCmdStreamerMemoryWrites */ +#define bdw__memory_writes__gti_cmd_streamer_memory_writes__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* Memory Writes Distribution Gen8 :: Sampler Texels */ +#define bdw__memory_writes__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Memory Writes Distribution Gen8 :: Pixels Failing Tests */ +#define bdw__memory_writes__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Memory Writes Distribution Gen8 :: GtiL3Bank0Writes */ +#define bdw__memory_writes__gti_l3_bank0_writes__read \ + hsw__compute_extended__typed_atomics0__read + +/* Memory Writes Distribution Gen8 :: GtiL3Bank1Writes */ +#define bdw__memory_writes__gti_l3_bank1_writes__read \ + hsw__memory_reads__gti_memory_reads__read + +/* Memory Writes Distribution Gen8 :: GtiL3Bank2Writes */ +#define bdw__memory_writes__gti_l3_bank2_writes__read \ + hsw__memory_reads__llc_read_accesses__read + +/* Memory Writes Distribution Gen8 :: GtiL3Bank3Writes */ +#define bdw__memory_writes__gti_l3_bank3_writes__read \ + hsw__memory_reads__gpu_core_clocks__read + +/* Memory Writes Distribution Gen8 :: GtiL3Writes */ +#define bdw__memory_writes__gti_l3_writes__read \ + bdw__memory_reads__gti_l3_reads__read + +/* Memory Writes Distribution Gen8 :: GPU Time Elapsed */ +#define bdw__memory_writes__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Memory Writes Distribution Gen8 :: AVG GPU Core Frequency */ +#define bdw__memory_writes__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Memory Writes Distribution Gen8 :: AVG GPU Core Frequency */ +#define bdw__memory_writes__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Memory Writes Distribution Gen8 :: Sampler Texels Misses */ +#define bdw__memory_writes__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Memory Writes Distribution Gen8 :: CS Threads Dispatched */ +#define bdw__memory_writes__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Memory Writes Distribution Gen8 :: SLM Bytes Read */ +#define bdw__memory_writes__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Memory Writes Distribution Gen8 :: GtiRccMemoryWrites */ +#define bdw__memory_writes__gti_rcc_memory_writes__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* Memory Writes Distribution Gen8 :: GtiSoMemoryWrites */ +#define bdw__memory_writes__gti_so_memory_writes__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Memory Writes Distribution Gen8 :: GPU Busy */ +#define bdw__memory_writes__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Memory Writes Distribution Gen8 :: GtiStcMemoryWrites */ +#define bdw__memory_writes__gti_stc_memory_writes__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* Memory Writes Distribution Gen8 :: Rasterized Pixels */ +#define bdw__memory_writes__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Memory Writes Distribution Gen8 :: DS Threads Dispatched */ +#define bdw__memory_writes__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Memory Writes Distribution Gen8 :: Samples Written */ +#define bdw__memory_writes__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Memory Writes Distribution Gen8 :: EU Stall */ +#define bdw__memory_writes__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Memory Writes Distribution Gen8 :: Samples Blended */ +#define bdw__memory_writes__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Memory Writes Distribution Gen8 :: Early Depth Test Fails */ +#define bdw__memory_writes__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Memory Writes Distribution Gen8 :: Shader Memory Accesses */ +#define bdw__memory_writes__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Memory Writes Distribution Gen8 :: HS Threads Dispatched */ +#define bdw__memory_writes__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Memory Writes Distribution Gen8 :: GtiRczMemoryWrites */ +#define bdw__memory_writes__gti_rcz_memory_writes__read \ + hsw__compute_extended__gpu_clocks__read + +/* Memory Writes Distribution Gen8 :: SLM Bytes Written */ +#define bdw__memory_writes__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Memory Writes Distribution Gen8 :: L3 Shader Throughput */ +#define bdw__memory_writes__l3_shader_throughput__read \ + bdw__render_basic__l3_shader_throughput__read + +/* Memory Writes Distribution Gen8 :: Samples Killed in FS */ +#define bdw__memory_writes__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Memory Writes Distribution Gen8 :: GtiHizMemoryWrites */ +#define bdw__memory_writes__gti_hiz_memory_writes__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* Memory Writes Distribution Gen8 :: Shader Atomic Memory Accesses */ +#define bdw__memory_writes__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Extended Gen8 :: GPU Core Clocks */ +#define bdw__compute_extended__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Extended Gen8 :: EU Active */ +#define bdw__compute_extended__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Compute Metrics Extended Gen8 :: EU Both FPU Pipes Active */ +#define bdw__compute_extended__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Compute Metrics Extended Gen8 :: EU FPU0 Pipe Active */ +#define bdw__compute_extended__fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Compute Metrics Extended Gen8 :: EU FPU1 Pipe Active */ +#define bdw__compute_extended__fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Compute Metrics Extended Gen8 :: EU AVG IPC Rate */ +#define bdw__compute_extended__eu_avg_ipc_rate__read \ + bdw__compute_basic__eu_avg_ipc_rate__read + +/* Compute Metrics Extended Gen8 :: Typed Writes 0 */ +#define bdw__compute_extended__typed_writes0__read \ + hsw__compute_extended__typed_writes0__read + +/* Compute Metrics Extended Gen8 :: EuTypedAtomics0 */ +#define bdw__compute_extended__eu_typed_atomics0__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* Compute Metrics Extended Gen8 :: Typed Atomics 0 */ +#define bdw__compute_extended__typed_atomics0__read \ + hsw__compute_extended__typed_atomics0__read + +/* Compute Metrics Extended Gen8 :: TypedAtomicsPerCacheLine */ +#define bdw__compute_extended__typed_atomics_per_cache_line__read \ + hsw__compute_extended__typed_atomics_per_cache_line__read + +/* Compute Metrics Extended Gen8 :: EuUntypedReads0 */ +#define bdw__compute_extended__eu_untyped_reads0__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* Compute Metrics Extended Gen8 :: Untyped Writes 0 */ +#define bdw__compute_extended__untyped_writes0__read \ + hsw__compute_extended__untyped_writes0__read + +/* Compute Metrics Extended Gen8 :: EuUntypedAtomics0 */ +#define bdw__compute_extended__eu_untyped_atomics0__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* Compute Metrics Extended Gen8 :: EuUntypedWrites0 */ +#define bdw__compute_extended__eu_untyped_writes0__read \ + hsw__compute_extended__eu_untyped_writes0__read + +/* Compute Metrics Extended Gen8 :: EuA64UntypedWrites0 */ +#define bdw__compute_extended__eu_a64_untyped_writes0__read \ + hsw__compute_extended__gpu_clocks__read + +/* Compute Metrics Extended Gen8 :: UntypedWritesPerCacheLine */ +static float +bdw__compute_extended__untyped_writes_per_cache_line__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $EuUntypedWrites0 $EuA64UntypedWrites0 UADD $UntypedWrites0 FDIV */ + uint64_t tmp0 = bdw__compute_extended__eu_untyped_writes0__read(brw, query, accumulator) + bdw__compute_extended__eu_a64_untyped_writes0__read(brw, query, accumulator); + double tmp1 = tmp0; + double tmp2 = bdw__compute_extended__untyped_writes0__read(brw, query, accumulator); + double tmp3 = tmp2 ? tmp1 / tmp2 : 0; + + return tmp3; +} + +/* Compute Metrics Extended Gen8 :: Shader Barrier Messages */ +#define bdw__compute_extended__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Compute Metrics Extended Gen8 :: Sampler Texels */ +#define bdw__compute_extended__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Compute Metrics Extended Gen8 :: GPU Time Elapsed */ +#define bdw__compute_extended__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics Extended Gen8 :: AVG GPU Core Frequency */ +#define bdw__compute_extended__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics Extended Gen8 :: AVG GPU Core Frequency */ +#define bdw__compute_extended__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics Extended Gen8 :: Sampler Texels Misses */ +#define bdw__compute_extended__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Compute Metrics Extended Gen8 :: CS Threads Dispatched */ +#define bdw__compute_extended__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Compute Metrics Extended Gen8 :: SLM Bytes Read */ +#define bdw__compute_extended__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Compute Metrics Extended Gen8 :: EuTypedWrites0 */ +#define bdw__compute_extended__eu_typed_writes0__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* Compute Metrics Extended Gen8 :: TypedWritesPerCacheLine */ +#define bdw__compute_extended__typed_writes_per_cache_line__read \ + hsw__compute_extended__typed_writes_per_cache_line__read + +/* Compute Metrics Extended Gen8 :: Typed Reads 0 */ +#define bdw__compute_extended__typed_reads0__read \ + hsw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Extended Gen8 :: Untyped Reads 0 */ +#define bdw__compute_extended__untyped_reads0__read \ + hsw__compute_extended__untyped_reads0__read + +/* Compute Metrics Extended Gen8 :: EuA64UntypedReads0 */ +#define bdw__compute_extended__eu_a64_untyped_reads0__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* Compute Metrics Extended Gen8 :: EU Thread Occupancy */ +#define bdw__compute_extended__eu_thread_occupancy__read \ + bdw__compute_basic__eu_thread_occupancy__read + +/* Compute Metrics Extended Gen8 :: EU Stall */ +#define bdw__compute_extended__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics Extended Gen8 :: EuTypedReads0 */ +#define bdw__compute_extended__eu_typed_reads0__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Compute Metrics Extended Gen8 :: UntypedReadsPerCacheLine */ +static float +bdw__compute_extended__untyped_reads_per_cache_line__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $EuUntypedReads0 $EuA64UntypedReads0 UADD $UntypedReads0 FDIV */ + uint64_t tmp0 = bdw__compute_extended__eu_untyped_reads0__read(brw, query, accumulator) + bdw__compute_extended__eu_a64_untyped_reads0__read(brw, query, accumulator); + double tmp1 = tmp0; + double tmp2 = bdw__compute_extended__untyped_reads0__read(brw, query, accumulator); + double tmp3 = tmp2 ? tmp1 / tmp2 : 0; + + return tmp3; +} + +/* Compute Metrics Extended Gen8 :: Shader Memory Accesses */ +#define bdw__compute_extended__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Compute Metrics Extended Gen8 :: TypedReadsPerCacheLine */ +#define bdw__compute_extended__typed_reads_per_cache_line__read \ + hsw__compute_extended__typed_reads_per_cache_line__read + +/* Compute Metrics Extended Gen8 :: SLM Bytes Written */ +#define bdw__compute_extended__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Compute Metrics Extended Gen8 :: L3 Shader Throughput */ +#define bdw__compute_extended__l3_shader_throughput__read \ + bdw__render_basic__l3_shader_throughput__read + +/* Compute Metrics Extended Gen8 :: Shader Atomic Memory Accesses */ +#define bdw__compute_extended__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Extended Gen8 :: EU Send Pipe Active */ +#define bdw__compute_extended__eu_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Compute Metrics L3 Cache Gen8 :: GPU Core Clocks */ +#define bdw__compute_l3_cache__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics L3 Cache Gen8 :: EU Active */ +#define bdw__compute_l3_cache__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Compute Metrics L3 Cache Gen8 :: L3 Bank 03 Accesses */ +static uint64_t +bdw__compute_l3_cache__l3_bank03_accesses__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 3 READ 2 UMUL */ + uint64_t tmp0 = accumulator[query->b_offset + 3]; + uint64_t tmp1 = tmp0 * 2; + + return tmp1; +} + +/* Compute Metrics L3 Cache Gen8 :: L3 Accesses */ +static uint64_t +bdw__compute_l3_cache__l3_accesses__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 0 READ C 1 READ B 2 READ B 3 READ C 2 READ C 3 READ B 6 READ B 7 READ UADD UADD UADD UADD UADD UADD UADD 2 UMUL */ + uint64_t tmp0 = accumulator[query->c_offset + 0]; + uint64_t tmp1 = accumulator[query->c_offset + 1]; + uint64_t tmp2 = accumulator[query->b_offset + 2]; + uint64_t tmp3 = accumulator[query->b_offset + 3]; + uint64_t tmp4 = accumulator[query->c_offset + 2]; + uint64_t tmp5 = accumulator[query->c_offset + 3]; + uint64_t tmp6 = accumulator[query->b_offset + 6]; + uint64_t tmp7 = accumulator[query->b_offset + 7]; + uint64_t tmp8 = tmp6 + tmp7; + uint64_t tmp9 = tmp5 + tmp8; + uint64_t tmp10 = tmp4 + tmp9; + uint64_t tmp11 = tmp3 + tmp10; + uint64_t tmp12 = tmp2 + tmp11; + uint64_t tmp13 = tmp1 + tmp12; + uint64_t tmp14 = tmp0 + tmp13; + uint64_t tmp15 = tmp14 * 2; + + return tmp15; +} + +/* Compute Metrics L3 Cache Gen8 :: EU Both FPU Pipes Active */ +#define bdw__compute_l3_cache__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Compute Metrics L3 Cache Gen8 :: L3 Total Throughput */ +static uint64_t +bdw__compute_l3_cache__l3_total_throughput__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $L3Accesses 64 UMUL */ + uint64_t tmp0 = bdw__compute_l3_cache__l3_accesses__read(brw, query, accumulator) * 64; + + return tmp0; +} + +/* Compute Metrics L3 Cache Gen8 :: EU FPU0 Pipe Active */ +#define bdw__compute_l3_cache__fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Compute Metrics L3 Cache Gen8 :: EU FPU1 Pipe Active */ +#define bdw__compute_l3_cache__fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Compute Metrics L3 Cache Gen8 :: EU AVG IPC Rate */ +#define bdw__compute_l3_cache__eu_avg_ipc_rate__read \ + bdw__compute_basic__eu_avg_ipc_rate__read + +/* Compute Metrics L3 Cache Gen8 :: EU FPU0 Binary Instruction */ +#define bdw__compute_l3_cache__eu_binary_fpu0_instruction__read \ + bdw__render_basic__ps_send_active__read + +/* Compute Metrics L3 Cache Gen8 :: GS Threads Dispatched */ +#define bdw__compute_l3_cache__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Compute Metrics L3 Cache Gen8 :: Early Hi-Depth Test Fails */ +#define bdw__compute_l3_cache__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Compute Metrics L3 Cache Gen8 :: VS Threads Dispatched */ +#define bdw__compute_l3_cache__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Compute Metrics L3 Cache Gen8 :: FS Threads Dispatched */ +#define bdw__compute_l3_cache__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Compute Metrics L3 Cache Gen8 :: EU FPU0 Hybrid Instruction */ +static float +bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 13 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 13]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = bdw__compute_l3_cache__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Compute Metrics L3 Cache Gen8 :: L3 Misses */ +static uint64_t +bdw__compute_l3_cache__l3_misses__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 4 READ C 5 READ UADD */ + uint64_t tmp0 = accumulator[query->c_offset + 4]; + uint64_t tmp1 = accumulator[query->c_offset + 5]; + uint64_t tmp2 = tmp0 + tmp1; + + return tmp2; +} + +/* Compute Metrics L3 Cache Gen8 :: Shader Barrier Messages */ +#define bdw__compute_l3_cache__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Compute Metrics L3 Cache Gen8 :: L3 Bank 00 Accesses */ +static uint64_t +bdw__compute_l3_cache__l3_bank00_accesses__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 0 READ 2 UMUL */ + uint64_t tmp0 = accumulator[query->c_offset + 0]; + uint64_t tmp1 = tmp0 * 2; + + return tmp1; +} + +/* Compute Metrics L3 Cache Gen8 :: EU FPU0 Move Instruction */ +static float +bdw__compute_l3_cache__eu_move_fpu0_instruction__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 19 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 19]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = bdw__compute_l3_cache__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Compute Metrics L3 Cache Gen8 :: Sampler Texels */ +#define bdw__compute_l3_cache__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Compute Metrics L3 Cache Gen8 :: Pixels Failing Tests */ +#define bdw__compute_l3_cache__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Compute Metrics L3 Cache Gen8 :: L3 Bank 10 Accesses */ +static uint64_t +bdw__compute_l3_cache__l3_bank10_accesses__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 2 READ 2 UMUL */ + uint64_t tmp0 = accumulator[query->c_offset + 2]; + uint64_t tmp1 = tmp0 * 2; + + return tmp1; +} + +/* Compute Metrics L3 Cache Gen8 :: EU FPU1 Hybrid Instruction */ +static float +bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 14 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 14]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = bdw__compute_l3_cache__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Compute Metrics L3 Cache Gen8 :: GPU Time Elapsed */ +#define bdw__compute_l3_cache__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics L3 Cache Gen8 :: AVG GPU Core Frequency */ +#define bdw__compute_l3_cache__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics L3 Cache Gen8 :: AVG GPU Core Frequency */ +#define bdw__compute_l3_cache__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics L3 Cache Gen8 :: Sampler Texels Misses */ +#define bdw__compute_l3_cache__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Compute Metrics L3 Cache Gen8 :: CS Threads Dispatched */ +#define bdw__compute_l3_cache__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Compute Metrics L3 Cache Gen8 :: SLM Bytes Read */ +#define bdw__compute_l3_cache__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Compute Metrics L3 Cache Gen8 :: L3 Bank 10 IC Accesses */ +static uint64_t +bdw__compute_l3_cache__l3_bank10_ic_accesses__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 4 READ B 5 READ UADD 2 UMUL $L3Bank10Accesses UMIN */ + uint64_t tmp0 = accumulator[query->b_offset + 4]; + uint64_t tmp1 = accumulator[query->b_offset + 5]; + uint64_t tmp2 = tmp0 + tmp1; + uint64_t tmp3 = tmp2 * 2; + uint64_t tmp4 = MIN(tmp3, bdw__compute_l3_cache__l3_bank10_accesses__read(brw, query, accumulator)); + + return tmp4; +} + +/* Compute Metrics L3 Cache Gen8 :: L3 Bank 10 IC Hits */ +static uint64_t +bdw__compute_l3_cache__l3_bank10_ic_hits__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 5 READ 2 UMUL $L3Bank10IcAccesses UMIN */ + uint64_t tmp0 = accumulator[query->b_offset + 5]; + uint64_t tmp1 = tmp0 * 2; + uint64_t tmp2 = MIN(tmp1, bdw__compute_l3_cache__l3_bank10_ic_accesses__read(brw, query, accumulator)); + + return tmp2; +} + +/* Compute Metrics L3 Cache Gen8 :: GTI Read Throughput */ +#define bdw__compute_l3_cache__gti_read_throughput__read \ + bdw__render_basic__gti_read_throughput__read + +/* Compute Metrics L3 Cache Gen8 :: GTI L3 Throughput */ +static uint64_t +bdw__compute_l3_cache__gti_l3_throughput__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 4 READ C 5 READ UADD 64 UMUL */ + uint64_t tmp0 = accumulator[query->c_offset + 4]; + uint64_t tmp1 = accumulator[query->c_offset + 5]; + uint64_t tmp2 = tmp0 + tmp1; + uint64_t tmp3 = tmp2 * 64; + + return tmp3; +} + +/* Compute Metrics L3 Cache Gen8 :: L3 Bank 00 IC Accesses */ +static uint64_t +bdw__compute_l3_cache__l3_bank00_ic_accesses__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 0 READ B 1 READ UADD 2 UMUL $L3Bank00Accesses UMIN */ + uint64_t tmp0 = accumulator[query->b_offset + 0]; + uint64_t tmp1 = accumulator[query->b_offset + 1]; + uint64_t tmp2 = tmp0 + tmp1; + uint64_t tmp3 = tmp2 * 2; + uint64_t tmp4 = MIN(tmp3, bdw__compute_l3_cache__l3_bank00_accesses__read(brw, query, accumulator)); + + return tmp4; +} + +/* Compute Metrics L3 Cache Gen8 :: L3 Bank 00 IC Hits */ +static uint64_t +bdw__compute_l3_cache__l3_bank00_ic_hits__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 1 READ 2 UMUL $L3Bank00IcAccesses UMIN */ + uint64_t tmp0 = accumulator[query->b_offset + 1]; + uint64_t tmp1 = tmp0 * 2; + uint64_t tmp2 = MIN(tmp1, bdw__compute_l3_cache__l3_bank00_ic_accesses__read(brw, query, accumulator)); + + return tmp2; +} + +/* Compute Metrics L3 Cache Gen8 :: L3 Bank 01 Accesses */ +static uint64_t +bdw__compute_l3_cache__l3_bank01_accesses__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 1 READ 2 UMUL */ + uint64_t tmp0 = accumulator[query->c_offset + 1]; + uint64_t tmp1 = tmp0 * 2; + + return tmp1; +} + +/* Compute Metrics L3 Cache Gen8 :: GPU Busy */ +#define bdw__compute_l3_cache__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Compute Metrics L3 Cache Gen8 :: EU FPU0 Ternary Instruction */ +#define bdw__compute_l3_cache__eu_ternary_fpu0_instruction__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Compute Metrics L3 Cache Gen8 :: Shader Atomic Memory Accesses */ +#define bdw__compute_l3_cache__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics L3 Cache Gen8 :: Rasterized Pixels */ +#define bdw__compute_l3_cache__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Compute Metrics L3 Cache Gen8 :: DS Threads Dispatched */ +#define bdw__compute_l3_cache__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Compute Metrics L3 Cache Gen8 :: Samples Written */ +#define bdw__compute_l3_cache__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Compute Metrics L3 Cache Gen8 :: EU FPU1 Move Instruction */ +static float +bdw__compute_l3_cache__eu_move_fpu1_instruction__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 20 READ $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 20]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + uint64_t tmp4 = tmp3 * 100; + double tmp5 = tmp4; + double tmp6 = bdw__compute_l3_cache__gpu_core_clocks__read(brw, query, accumulator); + double tmp7 = tmp6 ? tmp5 / tmp6 : 0; + + return tmp7; +} + +/* Compute Metrics L3 Cache Gen8 :: EU Stall */ +#define bdw__compute_l3_cache__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics L3 Cache Gen8 :: Samples Blended */ +#define bdw__compute_l3_cache__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Compute Metrics L3 Cache Gen8 :: Early Depth Test Fails */ +#define bdw__compute_l3_cache__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Compute Metrics L3 Cache Gen8 :: L3 Bank 11 Accesses */ +#define bdw__compute_l3_cache__l3_bank11_accesses__read \ + bdw__memory_reads__gti_ring_accesses__read + +/* Compute Metrics L3 Cache Gen8 :: L3 Bank 02 Accesses */ +static uint64_t +bdw__compute_l3_cache__l3_bank02_accesses__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 2 READ 2 UMUL */ + uint64_t tmp0 = accumulator[query->b_offset + 2]; + uint64_t tmp1 = tmp0 * 2; + + return tmp1; +} + +/* Compute Metrics L3 Cache Gen8 :: L3 Bank 13 Accesses */ +static uint64_t +bdw__compute_l3_cache__l3_bank13_accesses__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 7 READ 2 UMUL */ + uint64_t tmp0 = accumulator[query->b_offset + 7]; + uint64_t tmp1 = tmp0 * 2; + + return tmp1; +} + +/* Compute Metrics L3 Cache Gen8 :: Shader Memory Accesses */ +#define bdw__compute_l3_cache__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Compute Metrics L3 Cache Gen8 :: HS Threads Dispatched */ +#define bdw__compute_l3_cache__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Compute Metrics L3 Cache Gen8 :: GTI Write Throughput */ +#define bdw__compute_l3_cache__gti_write_throughput__read \ + hsw__render_basic__gti_write_throughput__read + +/* Compute Metrics L3 Cache Gen8 :: SLM Bytes Written */ +#define bdw__compute_l3_cache__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Compute Metrics L3 Cache Gen8 :: L3 Shader Throughput */ +#define bdw__compute_l3_cache__l3_shader_throughput__read \ + bdw__render_basic__l3_shader_throughput__read + +/* Compute Metrics L3 Cache Gen8 :: Samples Killed in FS */ +#define bdw__compute_l3_cache__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Compute Metrics L3 Cache Gen8 :: L3 Bank 12 Accesses */ +static uint64_t +bdw__compute_l3_cache__l3_bank12_accesses__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 6 READ 2 UMUL */ + uint64_t tmp0 = accumulator[query->b_offset + 6]; + uint64_t tmp1 = tmp0 * 2; + + return tmp1; +} + +/* Compute Metrics L3 Cache Gen8 :: EU FPU1 Binary Instruction */ +#define bdw__compute_l3_cache__eu_binary_fpu1_instruction__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Compute Metrics L3 Cache Gen8 :: EU FPU1 Ternary Instruction */ +#define bdw__compute_l3_cache__eu_ternary_fpu1_instruction__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Compute Metrics L3 Cache Gen8 :: EU Send Pipe Active */ +#define bdw__compute_l3_cache__eu_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Data Port Reads Coalescing Gen8 :: GPU Core Clocks */ +#define bdw__data_port_reads_coalescing__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Data Port Reads Coalescing Gen8 :: EU Active */ +#define bdw__data_port_reads_coalescing__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Data Port Reads Coalescing Gen8 :: EU Both FPU Pipes Active */ +#define bdw__data_port_reads_coalescing__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Data Port Reads Coalescing Gen8 :: EU FPU0 Pipe Active */ +#define bdw__data_port_reads_coalescing__fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Data Port Reads Coalescing Gen8 :: EU FPU1 Pipe Active */ +#define bdw__data_port_reads_coalescing__fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Data Port Reads Coalescing Gen8 :: EU AVG IPC Rate */ +#define bdw__data_port_reads_coalescing__eu_avg_ipc_rate__read \ + bdw__compute_basic__eu_avg_ipc_rate__read + +/* Data Port Reads Coalescing Gen8 :: GS Threads Dispatched */ +#define bdw__data_port_reads_coalescing__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Data Port Reads Coalescing Gen8 :: VS Threads Dispatched */ +#define bdw__data_port_reads_coalescing__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Data Port Reads Coalescing Gen8 :: FS Threads Dispatched */ +#define bdw__data_port_reads_coalescing__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Data Port Reads Coalescing Gen8 :: Shader Barrier Messages */ +#define bdw__data_port_reads_coalescing__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Data Port Reads Coalescing Gen8 :: Sampler Texels */ +#define bdw__data_port_reads_coalescing__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Data Port Reads Coalescing Gen8 :: GPU Time Elapsed */ +#define bdw__data_port_reads_coalescing__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Data Port Reads Coalescing Gen8 :: AVG GPU Core Frequency */ +#define bdw__data_port_reads_coalescing__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Data Port Reads Coalescing Gen8 :: AVG GPU Core Frequency */ +#define bdw__data_port_reads_coalescing__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Data Port Reads Coalescing Gen8 :: Sampler Texels Misses */ +#define bdw__data_port_reads_coalescing__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Data Port Reads Coalescing Gen8 :: CS Threads Dispatched */ +#define bdw__data_port_reads_coalescing__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Data Port Reads Coalescing Gen8 :: SLM Bytes Read */ +#define bdw__data_port_reads_coalescing__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Data Port Reads Coalescing Gen8 :: EU to Data Port 0 Reads 64 */ +#define bdw__data_port_reads_coalescing__eu_hdc0_reads64_b__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* Data Port Reads Coalescing Gen8 :: Data Port 0 to L3 Data Reads */ +#define bdw__data_port_reads_coalescing__hdc0_l3_data_reads__read \ + hsw__compute_extended__typed_atomics0__read + +/* Data Port Reads Coalescing Gen8 :: Data Port 0 to L3 Data Writes */ +#define bdw__data_port_reads_coalescing__hdc0_l3_data_writes__read \ + hsw__memory_reads__gti_memory_reads__read + +/* Data Port Reads Coalescing Gen8 :: EU to Data Port 0 Reads 128 */ +#define bdw__data_port_reads_coalescing__eu_hdc0_reads128_b__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* Data Port Reads Coalescing Gen8 :: DS Threads Dispatched */ +#define bdw__data_port_reads_coalescing__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Data Port Reads Coalescing Gen8 :: EU Thread Occupancy */ +#define bdw__data_port_reads_coalescing__eu_thread_occupancy__read \ + bdw__compute_basic__eu_thread_occupancy__read + +/* Data Port Reads Coalescing Gen8 :: All Data Port 0 Writes to L3 */ +#define bdw__data_port_reads_coalescing__hdc0_l3_writes__read \ + hsw__render_basic__gpu_core_clocks__read + +/* Data Port Reads Coalescing Gen8 :: EU Stall */ +#define bdw__data_port_reads_coalescing__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Data Port Reads Coalescing Gen8 :: EU to Data Port 0 Reads 32 */ +#define bdw__data_port_reads_coalescing__eu_hdc0_reads32_b__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* Data Port Reads Coalescing Gen8 :: EU to Data Port 0 Reads 256 */ +#define bdw__data_port_reads_coalescing__eu_hdc0_reads256_b__read \ + hsw__compute_extended__gpu_clocks__read + +/* Data Port Reads Coalescing Gen8 :: EuBytesReadPerCacheLine */ +static float +bdw__data_port_reads_coalescing__eu_bytes_read_per_cache_line__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $EuHdc0Reads32B 32 UMUL $EuHdc0Reads64B 64 UMUL $EuHdc0Reads128B 128 UMUL $EuHdc0Reads256B 256 UMUL UADD UADD UADD $Hdc0L3DataReads FDIV */ + uint64_t tmp0 = bdw__data_port_reads_coalescing__eu_hdc0_reads32_b__read(brw, query, accumulator) * 32; + uint64_t tmp1 = bdw__data_port_reads_coalescing__eu_hdc0_reads64_b__read(brw, query, accumulator) * 64; + uint64_t tmp2 = bdw__data_port_reads_coalescing__eu_hdc0_reads128_b__read(brw, query, accumulator) * 128; + uint64_t tmp3 = bdw__data_port_reads_coalescing__eu_hdc0_reads256_b__read(brw, query, accumulator) * 256; + uint64_t tmp4 = tmp2 + tmp3; + uint64_t tmp5 = tmp1 + tmp4; + uint64_t tmp6 = tmp0 + tmp5; + double tmp7 = tmp6; + double tmp8 = bdw__data_port_reads_coalescing__hdc0_l3_data_reads__read(brw, query, accumulator); + double tmp9 = tmp8 ? tmp7 / tmp8 : 0; + + return tmp9; +} + +/* Data Port Reads Coalescing Gen8 :: EuDataReadsPerCacheLine */ +static float +bdw__data_port_reads_coalescing__eu_data_reads_per_cache_line__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $EuBytesReadPerCacheLine 64 FDIV */ + double tmp0 = bdw__data_port_reads_coalescing__eu_bytes_read_per_cache_line__read(brw, query, accumulator); + double tmp1 = 64; + double tmp2 = tmp1 ? tmp0 / tmp1 : 0; + + return tmp2; +} + +/* Data Port Reads Coalescing Gen8 :: Shader Memory Accesses */ +#define bdw__data_port_reads_coalescing__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Data Port Reads Coalescing Gen8 :: HS Threads Dispatched */ +#define bdw__data_port_reads_coalescing__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Data Port Reads Coalescing Gen8 :: SLM Bytes Written */ +#define bdw__data_port_reads_coalescing__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Data Port Reads Coalescing Gen8 :: L3 Shader Throughput */ +#define bdw__data_port_reads_coalescing__l3_shader_throughput__read \ + bdw__render_basic__l3_shader_throughput__read + +/* Data Port Reads Coalescing Gen8 :: All Data Port 0 Reads from L3 */ +static uint64_t +bdw__data_port_reads_coalescing__hdc0_l3_reads__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 3 READ C 2 READ USUB */ + uint64_t tmp0 = accumulator[query->c_offset + 3]; + uint64_t tmp1 = accumulator[query->c_offset + 2]; + uint64_t tmp2 = tmp0 - tmp1; + + return tmp2; +} + +/* Data Port Reads Coalescing Gen8 :: Shader Atomic Memory Accesses */ +#define bdw__data_port_reads_coalescing__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Data Port Reads Coalescing Gen8 :: EU Send Pipe Active */ +#define bdw__data_port_reads_coalescing__eu_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Data Port Writes Coalescing Gen8 :: GPU Core Clocks */ +#define bdw__data_port_writes_coalescing__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Data Port Writes Coalescing Gen8 :: EU Active */ +#define bdw__data_port_writes_coalescing__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Data Port Writes Coalescing Gen8 :: EU to Data Port 0 Writes 128 */ +static uint64_t +bdw__data_port_writes_coalescing__eu_hdc0_writes192_b__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 6 READ 2 UDIV */ + uint64_t tmp0 = accumulator[query->b_offset + 6]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = 2; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + + return tmp3; +} + +/* Data Port Writes Coalescing Gen8 :: EU Both FPU Pipes Active */ +#define bdw__data_port_writes_coalescing__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Data Port Writes Coalescing Gen8 :: EU FPU0 Pipe Active */ +#define bdw__data_port_writes_coalescing__fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Data Port Writes Coalescing Gen8 :: EU FPU1 Pipe Active */ +#define bdw__data_port_writes_coalescing__fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Data Port Writes Coalescing Gen8 :: EU AVG IPC Rate */ +#define bdw__data_port_writes_coalescing__eu_avg_ipc_rate__read \ + bdw__compute_basic__eu_avg_ipc_rate__read + +/* Data Port Writes Coalescing Gen8 :: GS Threads Dispatched */ +#define bdw__data_port_writes_coalescing__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Data Port Writes Coalescing Gen8 :: VS Threads Dispatched */ +#define bdw__data_port_writes_coalescing__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Data Port Writes Coalescing Gen8 :: FS Threads Dispatched */ +#define bdw__data_port_writes_coalescing__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Data Port Writes Coalescing Gen8 :: Shader Barrier Messages */ +#define bdw__data_port_writes_coalescing__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Data Port Writes Coalescing Gen8 :: Sampler Texels */ +#define bdw__data_port_writes_coalescing__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Data Port Writes Coalescing Gen8 :: EU to Data Port 0 Writes 32B */ +#define bdw__data_port_writes_coalescing__eu_hdc0_writes32_b__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* Data Port Writes Coalescing Gen8 :: GPU Time Elapsed */ +#define bdw__data_port_writes_coalescing__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Data Port Writes Coalescing Gen8 :: AVG GPU Core Frequency */ +#define bdw__data_port_writes_coalescing__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Data Port Writes Coalescing Gen8 :: AVG GPU Core Frequency */ +#define bdw__data_port_writes_coalescing__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Data Port Writes Coalescing Gen8 :: Sampler Texels Misses */ +#define bdw__data_port_writes_coalescing__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Data Port Writes Coalescing Gen8 :: CS Threads Dispatched */ +#define bdw__data_port_writes_coalescing__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Data Port Writes Coalescing Gen8 :: SLM Bytes Read */ +#define bdw__data_port_writes_coalescing__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Data Port Writes Coalescing Gen8 :: EU to Data Port 0 Writes 256B */ +static uint64_t +bdw__data_port_writes_coalescing__eu_hdc0_writes256_b_simd16__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 7 READ 2 UDIV */ + uint64_t tmp0 = accumulator[query->b_offset + 7]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = 2; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + + return tmp3; +} + +/* Data Port Writes Coalescing Gen8 :: Data Port 0 to L3 Data Reads */ +#define bdw__data_port_writes_coalescing__hdc0_l3_data_reads__read \ + hsw__compute_extended__typed_atomics0__read + +/* Data Port Writes Coalescing Gen8 :: Data Port 0 to L3 Data Writes */ +#define bdw__data_port_writes_coalescing__hdc0_l3_data_writes__read \ + hsw__memory_reads__gti_memory_reads__read + +/* Data Port Writes Coalescing Gen8 :: EU to Data Port 0 Writes 64B */ +#define bdw__data_port_writes_coalescing__eu_hdc0_writes128_b_simd16__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* Data Port Writes Coalescing Gen8 :: EU to Data Port 0 Writes 64B */ +static uint64_t +bdw__data_port_writes_coalescing__eu_hdc0_writes96_b__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 2 READ 2 UDIV */ + uint64_t tmp0 = accumulator[query->b_offset + 2]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = 2; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + + return tmp3; +} + +/* Data Port Writes Coalescing Gen8 :: DS Threads Dispatched */ +#define bdw__data_port_writes_coalescing__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Data Port Writes Coalescing Gen8 :: EU Thread Occupancy */ +#define bdw__data_port_writes_coalescing__eu_thread_occupancy__read \ + bdw__compute_basic__eu_thread_occupancy__read + +/* Data Port Writes Coalescing Gen8 :: All Data Port 0 Writes to L3 */ +#define bdw__data_port_writes_coalescing__hdc0_l3_writes__read \ + hsw__render_basic__gpu_core_clocks__read + +/* Data Port Writes Coalescing Gen8 :: EU Stall */ +#define bdw__data_port_writes_coalescing__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Data Port Writes Coalescing Gen8 :: EU to Data Port 0 Writes 64B */ +static uint64_t +bdw__data_port_writes_coalescing__eu_hdc0_writes64_b__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 1 READ B 4 READ UADD */ + uint64_t tmp0 = accumulator[query->b_offset + 1]; + uint64_t tmp1 = accumulator[query->b_offset + 4]; + uint64_t tmp2 = tmp0 + tmp1; + + return tmp2; +} + +/* Data Port Writes Coalescing Gen8 :: EU to Data Port 0 Writes 128 */ +static uint64_t +bdw__data_port_writes_coalescing__eu_hdc0_writes128_b__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 3 READ 2 UDIV */ + uint64_t tmp0 = accumulator[query->b_offset + 3]; + uint64_t tmp1 = tmp0; + uint64_t tmp2 = 2; + uint64_t tmp3 = tmp2 ? tmp1 / tmp2 : 0; + + return tmp3; +} + +/* Data Port Writes Coalescing Gen8 :: EuBytesWrittenPerCacheLine */ +static float +bdw__data_port_writes_coalescing__eu_bytes_written_per_cache_line__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $EuHdc0Writes32B 32 UMUL $EuHdc0Writes64B 64 UMUL $EuHdc0Writes96B 96 UMUL $EuHdc0Writes128B 128 UMUL $EuHdc0Writes128BSimd16 128 UMUL $EuHdc0Writes256BSimd16 256 UMUL $EuHdc0Writes192B 192 UMUL UADD UADD UADD UADD UADD UADD $Hdc0L3DataWrites FDIV */ + uint64_t tmp0 = bdw__data_port_writes_coalescing__eu_hdc0_writes32_b__read(brw, query, accumulator) * 32; + uint64_t tmp1 = bdw__data_port_writes_coalescing__eu_hdc0_writes64_b__read(brw, query, accumulator) * 64; + uint64_t tmp2 = bdw__data_port_writes_coalescing__eu_hdc0_writes96_b__read(brw, query, accumulator) * 96; + uint64_t tmp3 = bdw__data_port_writes_coalescing__eu_hdc0_writes128_b__read(brw, query, accumulator) * 128; + uint64_t tmp4 = bdw__data_port_writes_coalescing__eu_hdc0_writes128_b_simd16__read(brw, query, accumulator) * 128; + uint64_t tmp5 = bdw__data_port_writes_coalescing__eu_hdc0_writes256_b_simd16__read(brw, query, accumulator) * 256; + uint64_t tmp6 = bdw__data_port_writes_coalescing__eu_hdc0_writes192_b__read(brw, query, accumulator) * 192; + uint64_t tmp7 = tmp5 + tmp6; + uint64_t tmp8 = tmp4 + tmp7; + uint64_t tmp9 = tmp3 + tmp8; + uint64_t tmp10 = tmp2 + tmp9; + uint64_t tmp11 = tmp1 + tmp10; + uint64_t tmp12 = tmp0 + tmp11; + double tmp13 = tmp12; + double tmp14 = bdw__data_port_writes_coalescing__hdc0_l3_data_writes__read(brw, query, accumulator); + double tmp15 = tmp14 ? tmp13 / tmp14 : 0; + + return tmp15; +} + +/* Data Port Writes Coalescing Gen8 :: EuDataWritesPerCacheLine */ +static float +bdw__data_port_writes_coalescing__eu_data_writes_per_cache_line__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $EuBytesWrittenPerCacheLine 64 FDIV */ + double tmp0 = bdw__data_port_writes_coalescing__eu_bytes_written_per_cache_line__read(brw, query, accumulator); + double tmp1 = 64; + double tmp2 = tmp1 ? tmp0 / tmp1 : 0; + + return tmp2; +} + +/* Data Port Writes Coalescing Gen8 :: Shader Memory Accesses */ +#define bdw__data_port_writes_coalescing__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Data Port Writes Coalescing Gen8 :: HS Threads Dispatched */ +#define bdw__data_port_writes_coalescing__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Data Port Writes Coalescing Gen8 :: SLM Bytes Written */ +#define bdw__data_port_writes_coalescing__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Data Port Writes Coalescing Gen8 :: L3 Shader Throughput */ +#define bdw__data_port_writes_coalescing__l3_shader_throughput__read \ + bdw__render_basic__l3_shader_throughput__read + +/* Data Port Writes Coalescing Gen8 :: All Data Port 0 Reads from L3 */ +#define bdw__data_port_writes_coalescing__hdc0_l3_reads__read \ + bdw__data_port_reads_coalescing__hdc0_l3_reads__read + +/* Data Port Writes Coalescing Gen8 :: Shader Atomic Memory Accesses */ +#define bdw__data_port_writes_coalescing__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Data Port Writes Coalescing Gen8 :: EU Send Pipe Active */ +#define bdw__data_port_writes_coalescing__eu_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set HDCAndSF :: GPU Core Clocks */ +#define bdw__hdc_and_sf__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set HDCAndSF :: EU Active */ +#define bdw__hdc_and_sf__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set HDCAndSF :: EU Both FPU Pipes Active */ +#define bdw__hdc_and_sf__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set HDCAndSF :: VS Send Pipe Active */ +#define bdw__hdc_and_sf__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set HDCAndSF :: VS FPU1 Pipe Active */ +#define bdw__hdc_and_sf__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set HDCAndSF :: GS Threads Dispatched */ +#define bdw__hdc_and_sf__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set HDCAndSF :: Early Hi-Depth Test Fails */ +#define bdw__hdc_and_sf__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set HDCAndSF :: FS Both FPU Active */ +#define bdw__hdc_and_sf__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set HDCAndSF :: VS Threads Dispatched */ +#define bdw__hdc_and_sf__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set HDCAndSF :: Polygon Data Ready */ +#define bdw__hdc_and_sf__poly_data_ready__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set HDCAndSF :: FS Threads Dispatched */ +#define bdw__hdc_and_sf__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss2) */ +static float +bdw__hdc_and_sf__non_sampler_shader12_access_stalled_on_l3__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 1 READ C 0 READ USUB 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->c_offset + 1]; + uint64_t tmp1 = accumulator[query->c_offset + 0]; + uint64_t tmp2 = tmp0 - tmp1; + uint64_t tmp3 = tmp2 * 100; + double tmp4 = tmp3; + double tmp5 = bdw__hdc_and_sf__gpu_core_clocks__read(brw, query, accumulator); + double tmp6 = tmp5 ? tmp4 / tmp5 : 0; + + return tmp6; +} + +/* Metric set HDCAndSF :: Shader Barrier Messages */ +#define bdw__hdc_and_sf__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set HDCAndSF :: Sampler Texels */ +#define bdw__hdc_and_sf__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set HDCAndSF :: Pixels Failing Tests */ +#define bdw__hdc_and_sf__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set HDCAndSF :: GPU Time Elapsed */ +#define bdw__hdc_and_sf__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set HDCAndSF :: AVG GPU Core Frequency */ +#define bdw__hdc_and_sf__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set HDCAndSF :: AVG GPU Core Frequency */ +#define bdw__hdc_and_sf__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set HDCAndSF :: Sampler Texels Misses */ +#define bdw__hdc_and_sf__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */ +static float +bdw__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 5 READ C 4 READ USUB 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->c_offset + 5]; + uint64_t tmp1 = accumulator[query->c_offset + 4]; + uint64_t tmp2 = tmp0 - tmp1; + uint64_t tmp3 = tmp2 * 100; + double tmp4 = tmp3; + double tmp5 = bdw__hdc_and_sf__gpu_core_clocks__read(brw, query, accumulator); + double tmp6 = tmp5 ? tmp4 / tmp5 : 0; + + return tmp6; +} + +/* Metric set HDCAndSF :: CS Threads Dispatched */ +#define bdw__hdc_and_sf__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss2) */ +static float +bdw__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 7 READ C 6 READ USUB 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->c_offset + 7]; + uint64_t tmp1 = accumulator[query->c_offset + 6]; + uint64_t tmp2 = tmp0 - tmp1; + uint64_t tmp3 = tmp2 * 100; + double tmp4 = tmp3; + double tmp5 = bdw__hdc_and_sf__gpu_core_clocks__read(brw, query, accumulator); + double tmp6 = tmp5 ? tmp4 / tmp5 : 0; + + return tmp6; +} + +/* Metric set HDCAndSF :: SLM Bytes Read */ +#define bdw__hdc_and_sf__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set HDCAndSF :: PS FPU1 Pipe Active */ +#define bdw__hdc_and_sf__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set HDCAndSF :: PS Send Pipeline Active */ +#define bdw__hdc_and_sf__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set HDCAndSF :: VS FPU0 Pipe Active */ +#define bdw__hdc_and_sf__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set HDCAndSF :: GPU Busy */ +#define bdw__hdc_and_sf__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */ +static float +bdw__hdc_and_sf__non_sampler_shader10_access_stalled_on_l3__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 5 READ B 4 READ USUB 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->b_offset + 5]; + uint64_t tmp1 = accumulator[query->b_offset + 4]; + uint64_t tmp2 = tmp0 - tmp1; + uint64_t tmp3 = tmp2 * 100; + double tmp4 = tmp3; + double tmp5 = bdw__hdc_and_sf__gpu_core_clocks__read(brw, query, accumulator); + double tmp6 = tmp5 ? tmp4 / tmp5 : 0; + + return tmp6; +} + +/* Metric set HDCAndSF :: Rasterized Pixels */ +#define bdw__hdc_and_sf__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set HDCAndSF :: PS FPU0 Pipe Active */ +#define bdw__hdc_and_sf__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set HDCAndSF :: DS Threads Dispatched */ +#define bdw__hdc_and_sf__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set HDCAndSF :: Samples Written */ +#define bdw__hdc_and_sf__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set HDCAndSF :: EU Stall */ +#define bdw__hdc_and_sf__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set HDCAndSF :: Samples Blended */ +#define bdw__hdc_and_sf__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set HDCAndSF :: Early Depth Test Fails */ +#define bdw__hdc_and_sf__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set HDCAndSF :: Shader Memory Accesses */ +#define bdw__hdc_and_sf__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set HDCAndSF :: HS Threads Dispatched */ +#define bdw__hdc_and_sf__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */ +static float +bdw__hdc_and_sf__non_sampler_shader11_access_stalled_on_l3__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 7 READ B 6 READ USUB 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->b_offset + 7]; + uint64_t tmp1 = accumulator[query->b_offset + 6]; + uint64_t tmp2 = tmp0 - tmp1; + uint64_t tmp3 = tmp2 * 100; + double tmp4 = tmp3; + double tmp5 = bdw__hdc_and_sf__gpu_core_clocks__read(brw, query, accumulator); + double tmp6 = tmp5 ? tmp4 / tmp5 : 0; + + return tmp6; +} + +/* Metric set HDCAndSF :: SLM Bytes Written */ +#define bdw__hdc_and_sf__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set HDCAndSF :: L3 Shader Throughput */ +static uint64_t +bdw__hdc_and_sf__l3_shader_throughput__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 30 READ A 31 READ $ShaderMemoryAccesses 64 UMUL UADD UADD */ + uint64_t tmp0 = accumulator[query->a_offset + 30]; + uint64_t tmp1 = accumulator[query->a_offset + 31]; + uint64_t tmp2 = bdw__hdc_and_sf__shader_memory_accesses__read(brw, query, accumulator) * 64; + uint64_t tmp3 = tmp1 + tmp2; + uint64_t tmp4 = tmp0 + tmp3; + + return tmp4; +} + +/* Metric set HDCAndSF :: Samples Killed in FS */ +#define bdw__hdc_and_sf__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */ +static float +bdw__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 3 READ C 2 READ USUB 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->c_offset + 3]; + uint64_t tmp1 = accumulator[query->c_offset + 2]; + uint64_t tmp2 = tmp0 - tmp1; + uint64_t tmp3 = tmp2 * 100; + double tmp4 = tmp3; + double tmp5 = bdw__hdc_and_sf__gpu_core_clocks__read(brw, query, accumulator); + double tmp6 = tmp5 ? tmp4 / tmp5 : 0; + + return tmp6; +} + +/* Metric set HDCAndSF :: Shader Atomic Memory Accesses */ +#define bdw__hdc_and_sf__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set L3_1 :: GPU Core Clocks */ +#define bdw__l3_1__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set L3_1 :: EU Active */ +#define bdw__l3_1__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set L3_1 :: Slice1 L3 Bank1 Stalled */ +#define bdw__l3_1__l31_bank1_stalled__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Metric set L3_1 :: EU Both FPU Pipes Active */ +#define bdw__l3_1__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set L3_1 :: VS Send Pipe Active */ +#define bdw__l3_1__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set L3_1 :: VS FPU1 Pipe Active */ +#define bdw__l3_1__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set L3_1 :: GS Threads Dispatched */ +#define bdw__l3_1__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set L3_1 :: Early Hi-Depth Test Fails */ +#define bdw__l3_1__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set L3_1 :: FS Both FPU Active */ +#define bdw__l3_1__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set L3_1 :: VS Threads Dispatched */ +#define bdw__l3_1__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set L3_1 :: FS Threads Dispatched */ +#define bdw__l3_1__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set L3_1 :: Shader Barrier Messages */ +#define bdw__l3_1__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set L3_1 :: Slice1 L3 Bank0 Stalled */ +#define bdw__l3_1__l31_bank0_stalled__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set L3_1 :: Sampler Texels */ +#define bdw__l3_1__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set L3_1 :: Pixels Failing Tests */ +#define bdw__l3_1__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set L3_1 :: GPU Time Elapsed */ +#define bdw__l3_1__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set L3_1 :: AVG GPU Core Frequency */ +#define bdw__l3_1__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set L3_1 :: AVG GPU Core Frequency */ +#define bdw__l3_1__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set L3_1 :: Sampler Texels Misses */ +#define bdw__l3_1__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set L3_1 :: CS Threads Dispatched */ +#define bdw__l3_1__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set L3_1 :: SLM Bytes Read */ +#define bdw__l3_1__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set L3_1 :: PS FPU1 Pipe Active */ +#define bdw__l3_1__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set L3_1 :: PS Send Pipeline Active */ +#define bdw__l3_1__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set L3_1 :: VS FPU0 Pipe Active */ +#define bdw__l3_1__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set L3_1 :: GPU Busy */ +#define bdw__l3_1__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set L3_1 :: Rasterized Pixels */ +#define bdw__l3_1__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set L3_1 :: Slice1 L3 Bank1 Active */ +#define bdw__l3_1__l31_bank1_active__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set L3_1 :: PS FPU0 Pipe Active */ +#define bdw__l3_1__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set L3_1 :: DS Threads Dispatched */ +#define bdw__l3_1__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set L3_1 :: Samples Written */ +#define bdw__l3_1__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set L3_1 :: EU Stall */ +#define bdw__l3_1__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set L3_1 :: Slice1 L3 Bank0 Active */ +#define bdw__l3_1__l31_bank0_active__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set L3_1 :: Samples Blended */ +#define bdw__l3_1__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set L3_1 :: Early Depth Test Fails */ +#define bdw__l3_1__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set L3_1 :: Shader Memory Accesses */ +#define bdw__l3_1__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set L3_1 :: HS Threads Dispatched */ +#define bdw__l3_1__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set L3_1 :: SLM Bytes Written */ +#define bdw__l3_1__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set L3_1 :: L3 Shader Throughput */ +#define bdw__l3_1__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set L3_1 :: Samples Killed in FS */ +#define bdw__l3_1__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set L3_1 :: Shader Atomic Memory Accesses */ +#define bdw__l3_1__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set L3_2 :: GPU Core Clocks */ +#define bdw__l3_2__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set L3_2 :: EU Active */ +#define bdw__l3_2__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set L3_2 :: Slice0 L3 Bank1 Active */ +#define bdw__l3_2__l30_bank1_active__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set L3_2 :: EU Both FPU Pipes Active */ +#define bdw__l3_2__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set L3_2 :: VS Send Pipe Active */ +#define bdw__l3_2__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set L3_2 :: VS FPU1 Pipe Active */ +#define bdw__l3_2__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set L3_2 :: GS Threads Dispatched */ +#define bdw__l3_2__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set L3_2 :: Early Hi-Depth Test Fails */ +#define bdw__l3_2__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set L3_2 :: FS Both FPU Active */ +#define bdw__l3_2__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set L3_2 :: VS Threads Dispatched */ +#define bdw__l3_2__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set L3_2 :: Slice0 L3 Bank1 Stalled */ +#define bdw__l3_2__l30_bank1_stalled__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Metric set L3_2 :: FS Threads Dispatched */ +#define bdw__l3_2__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set L3_2 :: Shader Barrier Messages */ +#define bdw__l3_2__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set L3_2 :: Sampler Texels */ +#define bdw__l3_2__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set L3_2 :: Pixels Failing Tests */ +#define bdw__l3_2__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set L3_2 :: GPU Time Elapsed */ +#define bdw__l3_2__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set L3_2 :: AVG GPU Core Frequency */ +#define bdw__l3_2__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set L3_2 :: AVG GPU Core Frequency */ +#define bdw__l3_2__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set L3_2 :: Sampler Texels Misses */ +#define bdw__l3_2__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set L3_2 :: CS Threads Dispatched */ +#define bdw__l3_2__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set L3_2 :: SLM Bytes Read */ +#define bdw__l3_2__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set L3_2 :: PS FPU1 Pipe Active */ +#define bdw__l3_2__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set L3_2 :: PS Send Pipeline Active */ +#define bdw__l3_2__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set L3_2 :: VS FPU0 Pipe Active */ +#define bdw__l3_2__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set L3_2 :: GPU Busy */ +#define bdw__l3_2__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set L3_2 :: Slice0 L3 Bank0 Active */ +#define bdw__l3_2__l30_bank0_active__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set L3_2 :: Rasterized Pixels */ +#define bdw__l3_2__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set L3_2 :: PS FPU0 Pipe Active */ +#define bdw__l3_2__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set L3_2 :: Slice0 L3 Bank0 Stalled */ +#define bdw__l3_2__l30_bank0_stalled__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set L3_2 :: DS Threads Dispatched */ +#define bdw__l3_2__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set L3_2 :: Samples Written */ +#define bdw__l3_2__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set L3_2 :: EU Stall */ +#define bdw__l3_2__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set L3_2 :: Samples Blended */ +#define bdw__l3_2__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set L3_2 :: Early Depth Test Fails */ +#define bdw__l3_2__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set L3_2 :: Shader Memory Accesses */ +#define bdw__l3_2__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set L3_2 :: HS Threads Dispatched */ +#define bdw__l3_2__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set L3_2 :: SLM Bytes Written */ +#define bdw__l3_2__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set L3_2 :: L3 Shader Throughput */ +#define bdw__l3_2__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set L3_2 :: Samples Killed in FS */ +#define bdw__l3_2__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set L3_2 :: Shader Atomic Memory Accesses */ +#define bdw__l3_2__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set L3_3 :: GPU Core Clocks */ +#define bdw__l3_3__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set L3_3 :: EU Active */ +#define bdw__l3_3__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set L3_3 :: EU Both FPU Pipes Active */ +#define bdw__l3_3__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set L3_3 :: VS Send Pipe Active */ +#define bdw__l3_3__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set L3_3 :: VS FPU1 Pipe Active */ +#define bdw__l3_3__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set L3_3 :: GS Threads Dispatched */ +#define bdw__l3_3__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set L3_3 :: Early Hi-Depth Test Fails */ +#define bdw__l3_3__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set L3_3 :: FS Both FPU Active */ +#define bdw__l3_3__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set L3_3 :: VS Threads Dispatched */ +#define bdw__l3_3__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set L3_3 :: FS Threads Dispatched */ +#define bdw__l3_3__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set L3_3 :: Slice0 L3 Bank3 Stalled */ +#define bdw__l3_3__l30_bank3_stalled__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set L3_3 :: Shader Barrier Messages */ +#define bdw__l3_3__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set L3_3 :: Sampler Texels */ +#define bdw__l3_3__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set L3_3 :: Pixels Failing Tests */ +#define bdw__l3_3__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set L3_3 :: GPU Time Elapsed */ +#define bdw__l3_3__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set L3_3 :: AVG GPU Core Frequency */ +#define bdw__l3_3__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set L3_3 :: AVG GPU Core Frequency */ +#define bdw__l3_3__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set L3_3 :: Sampler Texels Misses */ +#define bdw__l3_3__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set L3_3 :: CS Threads Dispatched */ +#define bdw__l3_3__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set L3_3 :: SLM Bytes Read */ +#define bdw__l3_3__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set L3_3 :: PS FPU1 Pipe Active */ +#define bdw__l3_3__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set L3_3 :: Slice0 L3 Bank3 Active */ +#define bdw__l3_3__l30_bank3_active__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set L3_3 :: PS Send Pipeline Active */ +#define bdw__l3_3__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set L3_3 :: VS FPU0 Pipe Active */ +#define bdw__l3_3__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set L3_3 :: GPU Busy */ +#define bdw__l3_3__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set L3_3 :: Slice1 L3 Bank3 Active */ +#define bdw__l3_3__l31_bank3_active__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set L3_3 :: Slice1 L3 Bank3 Stalled */ +#define bdw__l3_3__l31_bank3_stalled__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Metric set L3_3 :: Rasterized Pixels */ +#define bdw__l3_3__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set L3_3 :: PS FPU0 Pipe Active */ +#define bdw__l3_3__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set L3_3 :: DS Threads Dispatched */ +#define bdw__l3_3__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set L3_3 :: Samples Written */ +#define bdw__l3_3__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set L3_3 :: EU Stall */ +#define bdw__l3_3__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set L3_3 :: Samples Blended */ +#define bdw__l3_3__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set L3_3 :: Early Depth Test Fails */ +#define bdw__l3_3__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set L3_3 :: Shader Memory Accesses */ +#define bdw__l3_3__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set L3_3 :: HS Threads Dispatched */ +#define bdw__l3_3__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set L3_3 :: SLM Bytes Written */ +#define bdw__l3_3__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set L3_3 :: L3 Shader Throughput */ +#define bdw__l3_3__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set L3_3 :: Samples Killed in FS */ +#define bdw__l3_3__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set L3_3 :: Shader Atomic Memory Accesses */ +#define bdw__l3_3__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set L3_4 :: GPU Core Clocks */ +#define bdw__l3_4__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set L3_4 :: EU Active */ +#define bdw__l3_4__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set L3_4 :: EU Both FPU Pipes Active */ +#define bdw__l3_4__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set L3_4 :: VS Send Pipe Active */ +#define bdw__l3_4__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set L3_4 :: VS FPU1 Pipe Active */ +#define bdw__l3_4__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set L3_4 :: GS Threads Dispatched */ +#define bdw__l3_4__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set L3_4 :: Early Hi-Depth Test Fails */ +#define bdw__l3_4__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set L3_4 :: FS Both FPU Active */ +#define bdw__l3_4__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set L3_4 :: VS Threads Dispatched */ +#define bdw__l3_4__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set L3_4 :: FS Threads Dispatched */ +#define bdw__l3_4__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set L3_4 :: Shader Barrier Messages */ +#define bdw__l3_4__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set L3_4 :: Sampler Texels */ +#define bdw__l3_4__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set L3_4 :: Pixels Failing Tests */ +#define bdw__l3_4__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set L3_4 :: GPU Time Elapsed */ +#define bdw__l3_4__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set L3_4 :: AVG GPU Core Frequency */ +#define bdw__l3_4__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set L3_4 :: AVG GPU Core Frequency */ +#define bdw__l3_4__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set L3_4 :: Sampler Texels Misses */ +#define bdw__l3_4__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set L3_4 :: CS Threads Dispatched */ +#define bdw__l3_4__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set L3_4 :: SLM Bytes Read */ +#define bdw__l3_4__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set L3_4 :: PS FPU1 Pipe Active */ +#define bdw__l3_4__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set L3_4 :: Slice0 L3 Bank2 Stalled */ +#define bdw__l3_4__l30_bank2_stalled__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set L3_4 :: PS Send Pipeline Active */ +#define bdw__l3_4__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set L3_4 :: VS FPU0 Pipe Active */ +#define bdw__l3_4__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set L3_4 :: GPU Busy */ +#define bdw__l3_4__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set L3_4 :: Slice1 L3 Bank2 Active */ +#define bdw__l3_4__l31_bank2_active__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set L3_4 :: Slice0 L3 Bank2 Active */ +#define bdw__l3_4__l30_bank2_active__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set L3_4 :: Rasterized Pixels */ +#define bdw__l3_4__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set L3_4 :: Slice1 L3 Bank2 Stalled */ +#define bdw__l3_4__l31_bank2_stalled__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Metric set L3_4 :: PS FPU0 Pipe Active */ +#define bdw__l3_4__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set L3_4 :: DS Threads Dispatched */ +#define bdw__l3_4__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set L3_4 :: Samples Written */ +#define bdw__l3_4__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set L3_4 :: EU Stall */ +#define bdw__l3_4__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set L3_4 :: Samples Blended */ +#define bdw__l3_4__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set L3_4 :: Early Depth Test Fails */ +#define bdw__l3_4__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set L3_4 :: Shader Memory Accesses */ +#define bdw__l3_4__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set L3_4 :: HS Threads Dispatched */ +#define bdw__l3_4__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set L3_4 :: SLM Bytes Written */ +#define bdw__l3_4__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set L3_4 :: L3 Shader Throughput */ +#define bdw__l3_4__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set L3_4 :: Samples Killed in FS */ +#define bdw__l3_4__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set L3_4 :: Shader Atomic Memory Accesses */ +#define bdw__l3_4__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */ +#define bdw__rasterizer_and_pixel_backend__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set RasterizerAndPixelBackend :: EU Active */ +#define bdw__rasterizer_and_pixel_backend__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set RasterizerAndPixelBackend :: EU Both FPU Pipes Active */ +#define bdw__rasterizer_and_pixel_backend__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set RasterizerAndPixelBackend :: Slice1 Rasterizer Input Available */ +#define bdw__rasterizer_and_pixel_backend__rasterizer1_input_available__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Metric set RasterizerAndPixelBackend :: VS Send Pipe Active */ +#define bdw__rasterizer_and_pixel_backend__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set RasterizerAndPixelBackend :: VS FPU1 Pipe Active */ +#define bdw__rasterizer_and_pixel_backend__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */ +#define bdw__rasterizer_and_pixel_backend__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */ +#define bdw__rasterizer_and_pixel_backend__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set RasterizerAndPixelBackend :: FS Both FPU Active */ +#define bdw__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */ +#define bdw__rasterizer_and_pixel_backend__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */ +#define bdw__rasterizer_and_pixel_backend__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Pixel Values Ready */ +#define bdw__rasterizer_and_pixel_backend__pixel_values0_ready__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */ +#define bdw__rasterizer_and_pixel_backend__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set RasterizerAndPixelBackend :: Sampler Texels */ +#define bdw__rasterizer_and_pixel_backend__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */ +#define bdw__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */ +#define bdw__rasterizer_and_pixel_backend__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ +#define bdw__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ +#define bdw__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */ +#define bdw__rasterizer_and_pixel_backend__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */ +#define bdw__rasterizer_and_pixel_backend__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */ +#define bdw__rasterizer_and_pixel_backend__rasterizer0_input_available__read \ + bdw__render_pipe_profile__cl_bottleneck__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Post-EarlyZ Pixel Data Ready */ +#define bdw__rasterizer_and_pixel_backend__pixel_data0_ready__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */ +#define bdw__rasterizer_and_pixel_backend__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set RasterizerAndPixelBackend :: PS FPU1 Pipe Active */ +#define bdw__rasterizer_and_pixel_backend__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set RasterizerAndPixelBackend :: PS Send Pipeline Active */ +#define bdw__rasterizer_and_pixel_backend__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set RasterizerAndPixelBackend :: VS FPU0 Pipe Active */ +#define bdw__rasterizer_and_pixel_backend__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set RasterizerAndPixelBackend :: GPU Busy */ +#define bdw__rasterizer_and_pixel_backend__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set RasterizerAndPixelBackend :: Slice1 Pixel Values Ready */ +#define bdw__rasterizer_and_pixel_backend__pixel_values1_ready__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set RasterizerAndPixelBackend :: Slice1 PS Output Available */ +#define bdw__rasterizer_and_pixel_backend__ps_output1_available__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */ +#define bdw__rasterizer_and_pixel_backend__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set RasterizerAndPixelBackend :: PS FPU0 Pipe Active */ +#define bdw__rasterizer_and_pixel_backend__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */ +#define bdw__rasterizer_and_pixel_backend__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set RasterizerAndPixelBackend :: Samples Written */ +#define bdw__rasterizer_and_pixel_backend__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set RasterizerAndPixelBackend :: EU Stall */ +#define bdw__rasterizer_and_pixel_backend__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */ +#define bdw__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set RasterizerAndPixelBackend :: Samples Blended */ +#define bdw__rasterizer_and_pixel_backend__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */ +#define bdw__rasterizer_and_pixel_backend__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set RasterizerAndPixelBackend :: Slice1 Rasterizer Output Ready */ +#define bdw__rasterizer_and_pixel_backend__rasterizer1_output_ready__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Metric set RasterizerAndPixelBackend :: Slice1 Post-EarlyZ Pixel Data Ready */ +#define bdw__rasterizer_and_pixel_backend__pixel_data1_ready__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */ +#define bdw__rasterizer_and_pixel_backend__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */ +#define bdw__rasterizer_and_pixel_backend__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */ +#define bdw__rasterizer_and_pixel_backend__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */ +#define bdw__rasterizer_and_pixel_backend__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */ +#define bdw__rasterizer_and_pixel_backend__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 PS Output Available */ +#define bdw__rasterizer_and_pixel_backend__ps_output0_available__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */ +#define bdw__rasterizer_and_pixel_backend__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set Sampler_1 :: GPU Core Clocks */ +#define bdw__sampler_1__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set Sampler_1 :: EU Active */ +#define bdw__sampler_1__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set Sampler_1 :: EU Both FPU Pipes Active */ +#define bdw__sampler_1__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set Sampler_1 :: VS Send Pipe Active */ +#define bdw__sampler_1__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set Sampler_1 :: VS FPU1 Pipe Active */ +#define bdw__sampler_1__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set Sampler_1 :: GS Threads Dispatched */ +#define bdw__sampler_1__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set Sampler_1 :: Slice1 Subslice0 Input Available */ +#define bdw__sampler_1__sampler10_input_available__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Metric set Sampler_1 :: Early Hi-Depth Test Fails */ +#define bdw__sampler_1__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set Sampler_1 :: FS Both FPU Active */ +#define bdw__sampler_1__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set Sampler_1 :: VS Threads Dispatched */ +#define bdw__sampler_1__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set Sampler_1 :: FS Threads Dispatched */ +#define bdw__sampler_1__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set Sampler_1 :: Shader Barrier Messages */ +#define bdw__sampler_1__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set Sampler_1 :: Sampler Texels */ +#define bdw__sampler_1__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set Sampler_1 :: Pixels Failing Tests */ +#define bdw__sampler_1__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set Sampler_1 :: Slice1 Subslice2 Sampler Output Ready */ +#define bdw__sampler_1__sampler12_output_ready__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set Sampler_1 :: GPU Time Elapsed */ +#define bdw__sampler_1__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set Sampler_1 :: AVG GPU Core Frequency */ +#define bdw__sampler_1__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set Sampler_1 :: AVG GPU Core Frequency */ +#define bdw__sampler_1__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set Sampler_1 :: Sampler Texels Misses */ +#define bdw__sampler_1__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set Sampler_1 :: CS Threads Dispatched */ +#define bdw__sampler_1__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set Sampler_1 :: SLM Bytes Read */ +#define bdw__sampler_1__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set Sampler_1 :: PS FPU1 Pipe Active */ +#define bdw__sampler_1__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set Sampler_1 :: PS Send Pipeline Active */ +#define bdw__sampler_1__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set Sampler_1 :: VS FPU0 Pipe Active */ +#define bdw__sampler_1__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set Sampler_1 :: GPU Busy */ +#define bdw__sampler_1__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set Sampler_1 :: Slice1 Subslice1 Input Available */ +#define bdw__sampler_1__sampler11_input_available__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set Sampler_1 :: Rasterized Pixels */ +#define bdw__sampler_1__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set Sampler_1 :: PS FPU0 Pipe Active */ +#define bdw__sampler_1__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set Sampler_1 :: DS Threads Dispatched */ +#define bdw__sampler_1__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set Sampler_1 :: Samples Written */ +#define bdw__sampler_1__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set Sampler_1 :: EU Stall */ +#define bdw__sampler_1__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set Sampler_1 :: Samples Blended */ +#define bdw__sampler_1__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set Sampler_1 :: Early Depth Test Fails */ +#define bdw__sampler_1__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set Sampler_1 :: Slice1 Subslice2 Input Available */ +#define bdw__sampler_1__sampler12_input_available__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set Sampler_1 :: Slice1 Subslice0 Sampler Output Ready */ +#define bdw__sampler_1__sampler10_output_ready__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set Sampler_1 :: Shader Memory Accesses */ +#define bdw__sampler_1__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set Sampler_1 :: Slice1 Subslice1 Sampler Output Ready */ +#define bdw__sampler_1__sampler11_output_ready__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set Sampler_1 :: HS Threads Dispatched */ +#define bdw__sampler_1__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set Sampler_1 :: SLM Bytes Written */ +#define bdw__sampler_1__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set Sampler_1 :: L3 Shader Throughput */ +#define bdw__sampler_1__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set Sampler_1 :: Samples Killed in FS */ +#define bdw__sampler_1__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set Sampler_1 :: Shader Atomic Memory Accesses */ +#define bdw__sampler_1__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set Sampler_2 :: GPU Core Clocks */ +#define bdw__sampler_2__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set Sampler_2 :: EU Active */ +#define bdw__sampler_2__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set Sampler_2 :: Slice0 Subslice2 Input Available */ +#define bdw__sampler_2__sampler02_input_available__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set Sampler_2 :: EU Both FPU Pipes Active */ +#define bdw__sampler_2__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set Sampler_2 :: VS Send Pipe Active */ +#define bdw__sampler_2__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set Sampler_2 :: Slice0 Subslice0 Input Available */ +#define bdw__sampler_2__sampler00_input_available__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Metric set Sampler_2 :: VS FPU1 Pipe Active */ +#define bdw__sampler_2__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set Sampler_2 :: GS Threads Dispatched */ +#define bdw__sampler_2__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set Sampler_2 :: Early Hi-Depth Test Fails */ +#define bdw__sampler_2__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set Sampler_2 :: FS Both FPU Active */ +#define bdw__sampler_2__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set Sampler_2 :: VS Threads Dispatched */ +#define bdw__sampler_2__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set Sampler_2 :: Slice0 Subslice2 Sampler Output Ready */ +#define bdw__sampler_2__sampler02_output_ready__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set Sampler_2 :: FS Threads Dispatched */ +#define bdw__sampler_2__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set Sampler_2 :: Shader Barrier Messages */ +#define bdw__sampler_2__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set Sampler_2 :: Slice0 Subslice1 Input Available */ +#define bdw__sampler_2__sampler01_input_available__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set Sampler_2 :: Sampler Texels */ +#define bdw__sampler_2__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set Sampler_2 :: Pixels Failing Tests */ +#define bdw__sampler_2__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set Sampler_2 :: GPU Time Elapsed */ +#define bdw__sampler_2__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set Sampler_2 :: AVG GPU Core Frequency */ +#define bdw__sampler_2__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set Sampler_2 :: AVG GPU Core Frequency */ +#define bdw__sampler_2__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set Sampler_2 :: Sampler Texels Misses */ +#define bdw__sampler_2__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set Sampler_2 :: CS Threads Dispatched */ +#define bdw__sampler_2__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set Sampler_2 :: SLM Bytes Read */ +#define bdw__sampler_2__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set Sampler_2 :: PS FPU1 Pipe Active */ +#define bdw__sampler_2__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set Sampler_2 :: PS Send Pipeline Active */ +#define bdw__sampler_2__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set Sampler_2 :: VS FPU0 Pipe Active */ +#define bdw__sampler_2__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set Sampler_2 :: GPU Busy */ +#define bdw__sampler_2__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set Sampler_2 :: Rasterized Pixels */ +#define bdw__sampler_2__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set Sampler_2 :: PS FPU0 Pipe Active */ +#define bdw__sampler_2__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set Sampler_2 :: DS Threads Dispatched */ +#define bdw__sampler_2__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set Sampler_2 :: Samples Written */ +#define bdw__sampler_2__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set Sampler_2 :: EU Stall */ +#define bdw__sampler_2__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set Sampler_2 :: Samples Blended */ +#define bdw__sampler_2__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set Sampler_2 :: Early Depth Test Fails */ +#define bdw__sampler_2__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set Sampler_2 :: Slice0 Subslice0 Sampler Output Ready */ +#define bdw__sampler_2__sampler00_output_ready__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set Sampler_2 :: Slice0 Subslice1 Sampler Output Ready */ +#define bdw__sampler_2__sampler01_output_ready__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set Sampler_2 :: Shader Memory Accesses */ +#define bdw__sampler_2__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set Sampler_2 :: HS Threads Dispatched */ +#define bdw__sampler_2__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set Sampler_2 :: SLM Bytes Written */ +#define bdw__sampler_2__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set Sampler_2 :: L3 Shader Throughput */ +#define bdw__sampler_2__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set Sampler_2 :: Samples Killed in FS */ +#define bdw__sampler_2__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set Sampler_2 :: Shader Atomic Memory Accesses */ +#define bdw__sampler_2__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set TDL_1 :: GPU Core Clocks */ +#define bdw__tdl_1__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set TDL_1 :: EU Active */ +#define bdw__tdl_1__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set TDL_1 :: EU Both FPU Pipes Active */ +#define bdw__tdl_1__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set TDL_1 :: VS Send Pipe Active */ +#define bdw__tdl_1__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set TDL_1 :: VS FPU1 Pipe Active */ +#define bdw__tdl_1__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set TDL_1 :: GS Threads Dispatched */ +#define bdw__tdl_1__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set TDL_1 :: Early Hi-Depth Test Fails */ +#define bdw__tdl_1__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set TDL_1 :: FS Both FPU Active */ +#define bdw__tdl_1__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set TDL_1 :: VS Threads Dispatched */ +#define bdw__tdl_1__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice1 Subslice1 */ +#define bdw__tdl_1__ps_thread11_ready_for_dispatch__read \ + bdw__render_pipe_profile__cl_bottleneck__read + +/* Metric set TDL_1 :: FS Threads Dispatched */ +#define bdw__tdl_1__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice1 Subslice2 */ +#define bdw__tdl_1__non_ps_thread12_ready_for_dispatch__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Metric set TDL_1 :: Shader Barrier Messages */ +#define bdw__tdl_1__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_1 :: Sampler Texels */ +#define bdw__tdl_1__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set TDL_1 :: Pixels Failing Tests */ +#define bdw__tdl_1__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice1 Subslice0 */ +#define bdw__tdl_1__non_ps_thread10_ready_for_dispatch__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Metric set TDL_1 :: Thread Header Ready on Slice0 Subslice1 Port 0 */ +#define bdw__tdl_1__thread_header01_ready_port0__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set TDL_1 :: Thread Header Ready on Slice0 Subslice1 Port 1 */ +#define bdw__tdl_1__thread_header01_ready_port1__read \ + bdw__render_pipe_profile__ds_stall__read + +/* Metric set TDL_1 :: GPU Time Elapsed */ +#define bdw__tdl_1__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set TDL_1 :: AVG GPU Core Frequency */ +#define bdw__tdl_1__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set TDL_1 :: AVG GPU Core Frequency */ +#define bdw__tdl_1__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set TDL_1 :: Sampler Texels Misses */ +#define bdw__tdl_1__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set TDL_1 :: CS Threads Dispatched */ +#define bdw__tdl_1__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set TDL_1 :: SLM Bytes Read */ +#define bdw__tdl_1__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set TDL_1 :: PS FPU1 Pipe Active */ +#define bdw__tdl_1__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set TDL_1 :: PS Send Pipeline Active */ +#define bdw__tdl_1__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set TDL_1 :: VS FPU0 Pipe Active */ +#define bdw__tdl_1__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set TDL_1 :: GPU Busy */ +#define bdw__tdl_1__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set TDL_1 :: Thread Header Ready on Slice0 Subslice2 Port 1 */ +#define bdw__tdl_1__thread_header02_ready_port1__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Metric set TDL_1 :: Thread Header Ready on Slice0 Subslice2 Port 0 */ +#define bdw__tdl_1__thread_header02_ready_port0__read \ + bdw__render_pipe_profile__so_stall__read + +/* Metric set TDL_1 :: Rasterized Pixels */ +#define bdw__tdl_1__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set TDL_1 :: PS FPU0 Pipe Active */ +#define bdw__tdl_1__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set TDL_1 :: DS Threads Dispatched */ +#define bdw__tdl_1__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set TDL_1 :: Samples Written */ +#define bdw__tdl_1__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set TDL_1 :: EU Stall */ +#define bdw__tdl_1__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set TDL_1 :: Samples Blended */ +#define bdw__tdl_1__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set TDL_1 :: Early Depth Test Fails */ +#define bdw__tdl_1__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice1 Subslice2 */ +#define bdw__tdl_1__ps_thread12_ready_for_dispatch__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice1 Subslice0 */ +#define bdw__tdl_1__ps_thread10_ready_for_dispatch__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice1 Subslice1 */ +#define bdw__tdl_1__non_ps_thread11_ready_for_dispatch__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set TDL_1 :: Shader Memory Accesses */ +#define bdw__tdl_1__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set TDL_1 :: HS Threads Dispatched */ +#define bdw__tdl_1__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set TDL_1 :: SLM Bytes Written */ +#define bdw__tdl_1__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set TDL_1 :: L3 Shader Throughput */ +#define bdw__tdl_1__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set TDL_1 :: Samples Killed in FS */ +#define bdw__tdl_1__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set TDL_1 :: Thread Header Ready on Slice0 Subslice0 Port 0 */ +#define bdw__tdl_1__thread_header00_ready_port0__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set TDL_1 :: Shader Atomic Memory Accesses */ +#define bdw__tdl_1__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set TDL_1 :: Thread Header Ready on Slice0 Subslice0 Port 1 */ +#define bdw__tdl_1__thread_header00_ready_port1__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set TDL_2 :: GPU Core Clocks */ +#define bdw__tdl_2__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set TDL_2 :: EU Active */ +#define bdw__tdl_2__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set TDL_2 :: EU Both FPU Pipes Active */ +#define bdw__tdl_2__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice1 Port 1 */ +#define bdw__tdl_2__thread_header11_ready_port1__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set TDL_2 :: VS Send Pipe Active */ +#define bdw__tdl_2__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set TDL_2 :: VS FPU1 Pipe Active */ +#define bdw__tdl_2__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set TDL_2 :: GS Threads Dispatched */ +#define bdw__tdl_2__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set TDL_2 :: Early Hi-Depth Test Fails */ +#define bdw__tdl_2__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set TDL_2 :: FS Both FPU Active */ +#define bdw__tdl_2__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set TDL_2 :: VS Threads Dispatched */ +#define bdw__tdl_2__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set TDL_2 :: FS Threads Dispatched */ +#define bdw__tdl_2__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set TDL_2 :: NonPS Thread Ready For Dispatch on Slice0 Subslice2 */ +#define bdw__tdl_2__non_ps_thread02_ready_for_dispatch__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set TDL_2 :: Shader Barrier Messages */ +#define bdw__tdl_2__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_2 :: Sampler Texels */ +#define bdw__tdl_2__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set TDL_2 :: Pixels Failing Tests */ +#define bdw__tdl_2__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set TDL_2 :: GPU Time Elapsed */ +#define bdw__tdl_2__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set TDL_2 :: AVG GPU Core Frequency */ +#define bdw__tdl_2__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set TDL_2 :: AVG GPU Core Frequency */ +#define bdw__tdl_2__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set TDL_2 :: Sampler Texels Misses */ +#define bdw__tdl_2__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set TDL_2 :: NonPS Thread Ready For Dispatch on Slice0 Subslice0 */ +#define bdw__tdl_2__non_ps_thread00_ready_for_dispatch__read \ + bdw__render_pipe_profile__cl_bottleneck__read + +/* Metric set TDL_2 :: CS Threads Dispatched */ +#define bdw__tdl_2__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set TDL_2 :: SLM Bytes Read */ +#define bdw__tdl_2__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice1 Port 0 */ +#define bdw__tdl_2__thread_header11_ready_port0__read \ + bdw__render_pipe_profile__ds_stall__read + +/* Metric set TDL_2 :: PS FPU1 Pipe Active */ +#define bdw__tdl_2__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set TDL_2 :: PS Send Pipeline Active */ +#define bdw__tdl_2__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set TDL_2 :: VS FPU0 Pipe Active */ +#define bdw__tdl_2__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set TDL_2 :: GPU Busy */ +#define bdw__tdl_2__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice2 Port 0 */ +#define bdw__tdl_2__thread_header12_ready_port0__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set TDL_2 :: PS Thread Ready For Dispatch on Slice0 Subslice0 */ +#define bdw__tdl_2__ps_thread00_ready_for_dispatch__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Metric set TDL_2 :: Rasterized Pixels */ +#define bdw__tdl_2__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set TDL_2 :: PS FPU0 Pipe Active */ +#define bdw__tdl_2__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set TDL_2 :: DS Threads Dispatched */ +#define bdw__tdl_2__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set TDL_2 :: Samples Written */ +#define bdw__tdl_2__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice0 Port 1 */ +#define bdw__tdl_2__thread_header10_ready_port1__read \ + bdw__render_pipe_profile__so_stall__read + +/* Metric set TDL_2 :: EU Stall */ +#define bdw__tdl_2__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set TDL_2 :: Samples Blended */ +#define bdw__tdl_2__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set TDL_2 :: Early Depth Test Fails */ +#define bdw__tdl_2__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_2 :: PS Thread Ready For Dispatch on Slice0 Subslice1 */ +#define bdw__tdl_2__ps_thread01_ready_for_dispatch__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice2 Port 1 */ +#define bdw__tdl_2__thread_header12_ready_port1__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set TDL_2 :: Shader Memory Accesses */ +#define bdw__tdl_2__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set TDL_2 :: HS Threads Dispatched */ +#define bdw__tdl_2__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set TDL_2 :: PS Thread Ready For Dispatch on Slice0 Subslice2 */ +#define bdw__tdl_2__ps_thread02_ready_for_dispatch__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set TDL_2 :: SLM Bytes Written */ +#define bdw__tdl_2__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set TDL_2 :: L3 Shader Throughput */ +#define bdw__tdl_2__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set TDL_2 :: Samples Killed in FS */ +#define bdw__tdl_2__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice0 Port 0 */ +#define bdw__tdl_2__thread_header10_ready_port0__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Metric set TDL_2 :: Shader Atomic Memory Accesses */ +#define bdw__tdl_2__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set TDL_2 :: NonPS Thread Ready For Dispatch on Slice0 Subslice1 */ +#define bdw__tdl_2__non_ps_thread01_ready_for_dispatch__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Compute Metrics Extra Gen8 :: GPU Core Clocks */ +#define bdw__compute_extra__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Extra Gen8 :: EU FPU1 Pipe Active */ +#define bdw__compute_extra__fpu1_active__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics Extra Gen8 :: GPU Time Elapsed */ +#define bdw__compute_extra__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics Extra Gen8 :: AVG GPU Core Frequency */ +#define bdw__compute_extra__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics Extra Gen8 :: AVG GPU Core Frequency */ +#define bdw__compute_extra__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics Extra Gen8 :: EU FPU1 Pipe Active including Ext Math */ +static float +bdw__compute_extra__fpu1_active_adjusted__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 8 READ C 5 READ C 6 READ FADD C 7 READ FADD C 2 READ FADD C 3 READ FADD C 4 READ FADD 8 FMUL FADD 100 FMUL $EuCoresTotalCount FDIV $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 8]; + uint64_t tmp1 = accumulator[query->c_offset + 5]; + uint64_t tmp2 = accumulator[query->c_offset + 6]; + double tmp3 = tmp1 + tmp2; + uint64_t tmp4 = accumulator[query->c_offset + 7]; + double tmp5 = tmp3 + tmp4; + uint64_t tmp6 = accumulator[query->c_offset + 2]; + double tmp7 = tmp5 + tmp6; + uint64_t tmp8 = accumulator[query->c_offset + 3]; + double tmp9 = tmp7 + tmp8; + uint64_t tmp10 = accumulator[query->c_offset + 4]; + double tmp11 = tmp9 + tmp10; + double tmp12 = tmp11 * 8; + double tmp13 = tmp0 + tmp12; + double tmp14 = tmp13 * 100; + double tmp15 = tmp14; + double tmp16 = brw->perfquery.sys_vars.n_eus; + double tmp17 = tmp16 ? tmp15 / tmp16 : 0; + double tmp18 = tmp17; + double tmp19 = bdw__compute_extra__gpu_core_clocks__read(brw, query, accumulator); + double tmp20 = tmp19 ? tmp18 / tmp19 : 0; + + return tmp20; +} + +/* Media Vme Pipe Gen8 :: GPU Core Clocks */ +#define bdw__vme_pipe__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Media Vme Pipe Gen8 :: EU Active */ +#define bdw__vme_pipe__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Media Vme Pipe Gen8 :: EU Both FPU Pipes Active */ +#define bdw__vme_pipe__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Media Vme Pipe Gen8 :: GPU Time Elapsed */ +#define bdw__vme_pipe__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Media Vme Pipe Gen8 :: AVG GPU Core Frequency */ +#define bdw__vme_pipe__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Media Vme Pipe Gen8 :: AVG GPU Core Frequency */ +#define bdw__vme_pipe__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Media Vme Pipe Gen8 :: CS Threads Dispatched */ +#define bdw__vme_pipe__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Media Vme Pipe Gen8 :: EU Thread Occupancy */ +static float +bdw__vme_pipe__eu_thread_occupancy__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: 8 A 10 READ FMUL $EuThreadsCount FDIV $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 10]; + double tmp1 = 8 * tmp0; + double tmp2 = tmp1; + double tmp3 = brw->perfquery.sys_vars.eu_threads_count; + double tmp4 = tmp3 ? tmp2 / tmp3 : 0; + uint64_t tmp5 = tmp4; + uint64_t tmp6 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp7 = tmp6 ? tmp5 / tmp6 : 0; + uint64_t tmp8 = tmp7 * 100; + double tmp9 = tmp8; + double tmp10 = bdw__vme_pipe__gpu_core_clocks__read(brw, query, accumulator); + double tmp11 = tmp10 ? tmp9 / tmp10 : 0; + + return tmp11; +} + +/* Media Vme Pipe Gen8 :: EU Stall */ +#define bdw__vme_pipe__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Media Vme Pipe Gen8 :: VME Busy */ +static float +bdw__vme_pipe__vme_busy__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 0 READ B 3 READ FADD 2 FDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->b_offset + 0]; + uint64_t tmp1 = accumulator[query->b_offset + 3]; + double tmp2 = tmp0 + tmp1; + double tmp3 = tmp2; + double tmp4 = 2; + double tmp5 = tmp4 ? tmp3 / tmp4 : 0; + uint64_t tmp6 = tmp5 * 100; + double tmp7 = tmp6; + double tmp8 = bdw__vme_pipe__gpu_core_clocks__read(brw, query, accumulator); + double tmp9 = tmp8 ? tmp7 / tmp8 : 0; + + return tmp9; +} + +/* Media Vme Pipe Gen8 :: GPU Busy */ +#define bdw__vme_pipe__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Gpu Rings Busyness :: GPU Core Clocks */ +#define bdw__gpu_busyness__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Gpu Rings Busyness :: Vebox Ring Busy */ +#define bdw__gpu_busyness__vebox_busy__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Gpu Rings Busyness :: GPU Time Elapsed */ +#define bdw__gpu_busyness__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Gpu Rings Busyness :: AVG GPU Core Frequency */ +#define bdw__gpu_busyness__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Gpu Rings Busyness :: AVG GPU Core Frequency */ +#define bdw__gpu_busyness__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Gpu Rings Busyness :: Render Ring Busy */ +#define bdw__gpu_busyness__render_busy__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Gpu Rings Busyness :: Vdbox0 Ring Busy */ +#define bdw__gpu_busyness__vdbox0_busy__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Gpu Rings Busyness :: Blitter Ring Busy */ +#define bdw__gpu_busyness__blitter_busy__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Gpu Rings Busyness :: AnyRingBusy */ +#define bdw__gpu_busyness__any_ring_busy__read \ + bdw__render_basic__sampler0_busy__read + +/* Gpu Rings Busyness :: Vdbox1 Ring Busy */ +#define bdw__gpu_busyness__vdbox1_busy__read \ + bdw__render_pipe_profile__so_stall__read + +/* MDAPI testing set Gen8 :: TestCounter7 */ +#define bdw__test_oa__counter7__read \ + hsw__compute_extended__gpu_clocks__read + +/* MDAPI testing set Gen8 :: GPU Time Elapsed */ +#define bdw__test_oa__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* MDAPI testing set Gen8 :: GPU Core Clocks */ +#define bdw__test_oa__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* MDAPI testing set Gen8 :: AVG GPU Core Frequency */ +#define bdw__test_oa__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* MDAPI testing set Gen8 :: AVG GPU Core Frequency */ +#define bdw__test_oa__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* MDAPI testing set Gen8 :: TestCounter8 */ +#define bdw__test_oa__counter8__read \ + hsw__memory_reads__gpu_core_clocks__read + +/* MDAPI testing set Gen8 :: TestCounter4 */ +#define bdw__test_oa__counter4__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* MDAPI testing set Gen8 :: TestCounter5 */ +#define bdw__test_oa__counter5__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* MDAPI testing set Gen8 :: TestCounter6 */ +#define bdw__test_oa__counter6__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* MDAPI testing set Gen8 :: TestCounter3 */ +#define bdw__test_oa__counter3__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* MDAPI testing set Gen8 :: TestCounter0 */ +#define bdw__test_oa__counter0__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* MDAPI testing set Gen8 :: TestCounter1 */ +#define bdw__test_oa__counter1__read \ + hsw__compute_extended__eu_untyped_writes0__read + +/* MDAPI testing set Gen8 :: TestCounter2 */ +#define bdw__test_oa__counter2__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Render Metrics Basic Gen8LP :: GPU Core Clocks */ +#define chv__render_basic__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Render Metrics Basic Gen8LP :: EU Active */ +#define chv__render_basic__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Render Metrics Basic Gen8LP :: L3 Misses */ +#define chv__render_basic__l3_misses__read \ + hsw__compute_extended__typed_atomics0__read + +/* Render Metrics Basic Gen8LP :: GTI L3 Throughput */ +#define chv__render_basic__gti_l3_throughput__read \ + hsw__render_basic__gti_l3_throughput__read + +/* Render Metrics Basic Gen8LP :: EU Both FPU Pipes Active */ +#define chv__render_basic__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Render Metrics Basic Gen8LP :: VS Send Pipe Active */ +#define chv__render_basic__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Render Metrics Basic Gen8LP :: Sampler 1 Bottleneck */ +#define chv__render_basic__sampler1_bottleneck__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Render Metrics Basic Gen8LP :: VS FPU1 Pipe Active */ +#define chv__render_basic__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Render Metrics Basic Gen8LP :: GS Threads Dispatched */ +#define chv__render_basic__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Render Metrics Basic Gen8LP :: L3 Sampler Throughput */ +static uint64_t +chv__render_basic__l3_sampler_throughput__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 29 READ 64 UMUL */ + uint64_t tmp0 = accumulator[query->a_offset + 29]; + uint64_t tmp1 = tmp0 * 64; + + return tmp1; +} + +/* Render Metrics Basic Gen8LP :: Early Hi-Depth Test Fails */ +#define chv__render_basic__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Render Metrics Basic Gen8LP :: FS Both FPU Active */ +#define chv__render_basic__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Render Metrics Basic Gen8LP :: VS Threads Dispatched */ +#define chv__render_basic__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Render Metrics Basic Gen8LP :: FS Threads Dispatched */ +#define chv__render_basic__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Render Metrics Basic Gen8LP :: Sampler 0 Busy */ +#define chv__render_basic__sampler0_busy__read \ + bdw__render_basic__sampler0_busy__read + +/* Render Metrics Basic Gen8LP :: Sampler 1 Busy */ +#define chv__render_basic__sampler1_busy__read \ + bdw__render_basic__sampler1_busy__read + +/* Render Metrics Basic Gen8LP :: Samplers Busy */ +static float +chv__render_basic__samplers_busy__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 0 READ B 1 READ UADD $GpuCoreClocks FDIV 2 FDIV 100 FMUL */ + uint64_t tmp0 = accumulator[query->b_offset + 0]; + uint64_t tmp1 = accumulator[query->b_offset + 1]; + uint64_t tmp2 = tmp0 + tmp1; + double tmp3 = tmp2; + double tmp4 = chv__render_basic__gpu_core_clocks__read(brw, query, accumulator); + double tmp5 = tmp4 ? tmp3 / tmp4 : 0; + double tmp6 = tmp5; + double tmp7 = 2; + double tmp8 = tmp7 ? tmp6 / tmp7 : 0; + double tmp9 = tmp8 * 100; + + return tmp9; +} + +/* Render Metrics Basic Gen8LP :: GTI Fixed Pipe Throughput */ +#define chv__render_basic__gti_vf_throughput__read \ + bdw__render_basic__gti_vf_throughput__read + +/* Render Metrics Basic Gen8LP :: Shader Barrier Messages */ +#define chv__render_basic__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Render Metrics Basic Gen8LP :: Sampler 0 Bottleneck */ +#define chv__render_basic__sampler0_bottleneck__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Render Metrics Basic Gen8LP :: Sampler Texels */ +#define chv__render_basic__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Render Metrics Basic Gen8LP :: Pixels Failing Tests */ +#define chv__render_basic__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Render Metrics Basic Gen8LP :: GPU Time Elapsed */ +#define chv__render_basic__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Render Metrics Basic Gen8LP :: AVG GPU Core Frequency */ +#define chv__render_basic__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Render Metrics Basic Gen8LP :: AVG GPU Core Frequency */ +#define chv__render_basic__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Render Metrics Basic Gen8LP :: Sampler Texels Misses */ +#define chv__render_basic__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Render Metrics Basic Gen8LP :: CS Threads Dispatched */ +#define chv__render_basic__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Render Metrics Basic Gen8LP :: Shader Memory Accesses */ +#define chv__render_basic__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Render Metrics Basic Gen8LP :: SLM Bytes Read */ +#define chv__render_basic__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Render Metrics Basic Gen8LP :: GTI Read Throughput */ +#define chv__render_basic__gti_read_throughput__read \ + bdw__render_basic__gti_read_throughput__read + +/* Render Metrics Basic Gen8LP :: PS FPU1 Pipe Active */ +#define chv__render_basic__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Render Metrics Basic Gen8LP :: PS Send Pipeline Active */ +#define chv__render_basic__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Render Metrics Basic Gen8LP :: Rasterized Pixels */ +#define chv__render_basic__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Render Metrics Basic Gen8LP :: GPU Busy */ +#define chv__render_basic__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Render Metrics Basic Gen8LP :: GTI Depth Throughput */ +#define chv__render_basic__gti_depth_throughput__read \ + bdw__render_basic__gti_depth_throughput__read + +/* Render Metrics Basic Gen8LP :: VS FPU0 Pipe Active */ +#define chv__render_basic__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Render Metrics Basic Gen8LP :: PS FPU0 Pipe Active */ +#define chv__render_basic__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Render Metrics Basic Gen8LP :: DS Threads Dispatched */ +#define chv__render_basic__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Render Metrics Basic Gen8LP :: Samples Written */ +#define chv__render_basic__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Render Metrics Basic Gen8LP :: EU Stall */ +#define chv__render_basic__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Render Metrics Basic Gen8LP :: Samples Blended */ +#define chv__render_basic__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Render Metrics Basic Gen8LP :: Early Depth Test Fails */ +#define chv__render_basic__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Render Metrics Basic Gen8LP :: Samplers Bottleneck */ +#define chv__render_basic__sampler_bottleneck__read \ + bdw__render_basic__sampler_bottleneck__read + +/* Render Metrics Basic Gen8LP :: GTI HDC TLB Lookup Throughput */ +#define chv__render_basic__gti_hdc_lookups_throughput__read \ + bdw__render_basic__gti_hdc_lookups_throughput__read + +/* Render Metrics Basic Gen8LP :: GTI RCC Throughput */ +#define chv__render_basic__gti_rcc_throughput__read \ + bdw__render_basic__gti_rcc_throughput__read + +/* Render Metrics Basic Gen8LP :: HS Threads Dispatched */ +#define chv__render_basic__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Render Metrics Basic Gen8LP :: GTI Write Throughput */ +#define chv__render_basic__gti_write_throughput__read \ + hsw__render_basic__gti_write_throughput__read + +/* Render Metrics Basic Gen8LP :: SLM Bytes Written */ +#define chv__render_basic__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Render Metrics Basic Gen8LP :: L3 Shader Throughput */ +#define chv__render_basic__l3_shader_throughput__read \ + bdw__render_basic__l3_shader_throughput__read + +/* Render Metrics Basic Gen8LP :: Samples Killed in FS */ +#define chv__render_basic__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Render Metrics Basic Gen8LP :: Shader Atomic Memory Accesses */ +#define chv__render_basic__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Basic Gen8LP :: GPU Core Clocks */ +#define chv__compute_basic__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Basic Gen8LP :: EU Active */ +#define chv__compute_basic__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Compute Metrics Basic Gen8LP :: Untyped Bytes Read */ +static uint64_t +chv__compute_basic__untyped_bytes_read__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 4 READ B 5 READ UADD 64 UMUL */ + uint64_t tmp0 = accumulator[query->b_offset + 4]; + uint64_t tmp1 = accumulator[query->b_offset + 5]; + uint64_t tmp2 = tmp0 + tmp1; + uint64_t tmp3 = tmp2 * 64; + + return tmp3; +} + +/* Compute Metrics Basic Gen8LP :: EU Both FPU Pipes Active */ +#define chv__compute_basic__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Compute Metrics Basic Gen8LP :: Typed Bytes Written */ +static uint64_t +chv__compute_basic__typed_bytes_written__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 2 READ B 3 READ UADD 64 UMUL */ + uint64_t tmp0 = accumulator[query->b_offset + 2]; + uint64_t tmp1 = accumulator[query->b_offset + 3]; + uint64_t tmp2 = tmp0 + tmp1; + uint64_t tmp3 = tmp2 * 64; + + return tmp3; +} + +/* Compute Metrics Basic Gen8LP :: EU FPU0 Pipe Active */ +#define chv__compute_basic__fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Compute Metrics Basic Gen8LP :: EU FPU1 Pipe Active */ +#define chv__compute_basic__fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Compute Metrics Basic Gen8LP :: EU AVG IPC Rate */ +#define chv__compute_basic__eu_avg_ipc_rate__read \ + bdw__compute_basic__eu_avg_ipc_rate__read + +/* Compute Metrics Basic Gen8LP :: GS Threads Dispatched */ +#define chv__compute_basic__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Compute Metrics Basic Gen8LP :: Early Hi-Depth Test Fails */ +#define chv__compute_basic__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Compute Metrics Basic Gen8LP :: VS Threads Dispatched */ +#define chv__compute_basic__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Compute Metrics Basic Gen8LP :: FS Threads Dispatched */ +#define chv__compute_basic__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Compute Metrics Basic Gen8LP :: Shader Barrier Messages */ +#define chv__compute_basic__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Compute Metrics Basic Gen8LP :: Sampler Texels */ +#define chv__compute_basic__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Compute Metrics Basic Gen8LP :: Pixels Failing Tests */ +#define chv__compute_basic__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Compute Metrics Basic Gen8LP :: GPU Time Elapsed */ +#define chv__compute_basic__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics Basic Gen8LP :: AVG GPU Core Frequency */ +#define chv__compute_basic__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics Basic Gen8LP :: AVG GPU Core Frequency */ +#define chv__compute_basic__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics Basic Gen8LP :: Sampler Texels Misses */ +#define chv__compute_basic__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Compute Metrics Basic Gen8LP :: CS Threads Dispatched */ +#define chv__compute_basic__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Compute Metrics Basic Gen8LP :: Shader Memory Accesses */ +#define chv__compute_basic__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Compute Metrics Basic Gen8LP :: SLM Bytes Read */ +#define chv__compute_basic__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Compute Metrics Basic Gen8LP :: GTI Read Throughput */ +#define chv__compute_basic__gti_read_throughput__read \ + hsw__render_basic__gti_depth_throughput__read + +/* Compute Metrics Basic Gen8LP :: GTI Ring Throughput */ +static uint64_t +chv__compute_basic__gti_ring_throughput__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 2 READ 128 UMUL */ + uint64_t tmp0 = accumulator[query->c_offset + 2]; + uint64_t tmp1 = tmp0 * 128; + + return tmp1; +} + +/* Compute Metrics Basic Gen8LP :: Untyped Writes */ +#define chv__compute_basic__untyped_bytes_written__read \ + hsw__compute_basic__typed_bytes_written__read + +/* Compute Metrics Basic Gen8LP :: GPU Busy */ +#define chv__compute_basic__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Compute Metrics Basic Gen8LP :: Rasterized Pixels */ +#define chv__compute_basic__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Compute Metrics Basic Gen8LP :: Typed Bytes Read */ +static uint64_t +chv__compute_basic__typed_bytes_read__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 0 READ B 1 READ UADD 64 UMUL */ + uint64_t tmp0 = accumulator[query->b_offset + 0]; + uint64_t tmp1 = accumulator[query->b_offset + 1]; + uint64_t tmp2 = tmp0 + tmp1; + uint64_t tmp3 = tmp2 * 64; + + return tmp3; +} + +/* Compute Metrics Basic Gen8LP :: GTI Read-Only Stall */ +#define chv__compute_basic__gti_ro_stall__read \ + bdw__render_pipe_profile__so_stall__read + +/* Compute Metrics Basic Gen8LP :: DS Threads Dispatched */ +#define chv__compute_basic__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Compute Metrics Basic Gen8LP :: EU Thread Occupancy */ +#define chv__compute_basic__eu_thread_occupancy__read \ + bdw__compute_basic__eu_thread_occupancy__read + +/* Compute Metrics Basic Gen8LP :: GTI Read-Write Stall */ +#define chv__compute_basic__gti_rw_stall__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Compute Metrics Basic Gen8LP :: EU Stall */ +#define chv__compute_basic__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics Basic Gen8LP :: Samples Blended */ +#define chv__compute_basic__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Compute Metrics Basic Gen8LP :: Early Depth Test Fails */ +#define chv__compute_basic__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Compute Metrics Basic Gen8LP :: HS Threads Dispatched */ +#define chv__compute_basic__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Compute Metrics Basic Gen8LP :: GTI Write Throughput */ +#define chv__compute_basic__gti_write_throughput__read \ + hsw__render_basic__gti_vf_throughput__read + +/* Compute Metrics Basic Gen8LP :: SLM Bytes Written */ +#define chv__compute_basic__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Compute Metrics Basic Gen8LP :: L3 Shader Throughput */ +#define chv__compute_basic__l3_shader_throughput__read \ + bdw__render_basic__l3_shader_throughput__read + +/* Compute Metrics Basic Gen8LP :: Samples Killed in FS */ +#define chv__compute_basic__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Compute Metrics Basic Gen8LP :: Samples Written */ +#define chv__compute_basic__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Compute Metrics Basic Gen8LP :: Shader Atomic Memory Accesses */ +#define chv__compute_basic__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Basic Gen8LP :: EU Send Pipe Active */ +#define chv__compute_basic__eu_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Render Metrics for 3D Pipeline Profile :: GPU Core Clocks */ +#define chv__render_pipe_profile__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Render Metrics for 3D Pipeline Profile :: EU Active */ +#define chv__render_pipe_profile__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Render Metrics for 3D Pipeline Profile :: VS Bottleneck */ +#define chv__render_pipe_profile__vs_bottleneck__read \ + bdw__render_basic__sampler0_busy__read + +/* Render Metrics for 3D Pipeline Profile :: Hi-Depth Bottleneck */ +#define chv__render_pipe_profile__hi_depth_bottleneck__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile :: GS Bottleneck */ +#define chv__render_pipe_profile__gs_bottleneck__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile :: GS Threads Dispatched */ +#define chv__render_pipe_profile__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Render Metrics for 3D Pipeline Profile :: Early Hi-Depth Test Fails */ +#define chv__render_pipe_profile__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Render Metrics for 3D Pipeline Profile :: VS Threads Dispatched */ +#define chv__render_pipe_profile__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Render Metrics for 3D Pipeline Profile :: FS Threads Dispatched */ +#define chv__render_pipe_profile__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Render Metrics for 3D Pipeline Profile :: BC Bottleneck */ +#define chv__render_pipe_profile__bc_bottleneck__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile :: HS Stall */ +#define chv__render_pipe_profile__hs_stall__read \ + bdw__render_pipe_profile__hs_stall__read + +/* Render Metrics for 3D Pipeline Profile :: Shader Barrier Messages */ +#define chv__render_pipe_profile__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Render Metrics for 3D Pipeline Profile :: Sampler Texels */ +#define chv__render_pipe_profile__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Render Metrics for 3D Pipeline Profile :: Pixels Failing Tests */ +#define chv__render_pipe_profile__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Render Metrics for 3D Pipeline Profile :: GPU Time Elapsed */ +#define chv__render_pipe_profile__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */ +#define chv__render_pipe_profile__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Render Metrics for 3D Pipeline Profile :: AVG GPU Core Frequency */ +#define chv__render_pipe_profile__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Render Metrics for 3D Pipeline Profile :: Sampler Texels Misses */ +#define chv__render_pipe_profile__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Render Metrics for 3D Pipeline Profile :: CS Threads Dispatched */ +#define chv__render_pipe_profile__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Render Metrics for 3D Pipeline Profile :: VF Bottleneck */ +#define chv__render_pipe_profile__vf_bottleneck__read \ + bdw__render_pipe_profile__vf_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile :: SLM Bytes Read */ +#define chv__render_pipe_profile__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Render Metrics for 3D Pipeline Profile :: Strip-Fans Bottleneck */ +#define chv__render_pipe_profile__sf_bottleneck__read \ + bdw__render_pipe_profile__sf_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile :: Sampler Accesses */ +#define chv__render_pipe_profile__sampler_accesses__read \ + bdw__render_pipe_profile__sampler_accesses__read + +/* Render Metrics for 3D Pipeline Profile :: SF Stall */ +#define chv__render_pipe_profile__sf_stall__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Render Metrics for 3D Pipeline Profile :: GPU Busy */ +#define chv__render_pipe_profile__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Render Metrics for 3D Pipeline Profile :: HS Bottleneck */ +#define chv__render_pipe_profile__hs_bottleneck__read \ + bdw__render_basic__sampler1_busy__read + +/* Render Metrics for 3D Pipeline Profile :: CL Stall */ +#define chv__render_pipe_profile__cl_stall__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Render Metrics for 3D Pipeline Profile :: SO Bottleneck */ +#define chv__render_pipe_profile__so_bottleneck__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile :: Rasterized Pixels */ +#define chv__render_pipe_profile__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Render Metrics for 3D Pipeline Profile :: DS Threads Dispatched */ +#define chv__render_pipe_profile__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Render Metrics for 3D Pipeline Profile :: Samples Written */ +#define chv__render_pipe_profile__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Render Metrics for 3D Pipeline Profile :: DS Bottleneck */ +#define chv__render_pipe_profile__ds_bottleneck__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile :: EU Stall */ +#define chv__render_pipe_profile__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Render Metrics for 3D Pipeline Profile :: Clipper Bottleneck */ +#define chv__render_pipe_profile__cl_bottleneck__read \ + bdw__render_pipe_profile__cl_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile :: DS Stall */ +#define chv__render_pipe_profile__ds_stall__read \ + bdw__render_pipe_profile__ds_stall__read + +/* Render Metrics for 3D Pipeline Profile :: Early Depth Bottleneck */ +#define chv__render_pipe_profile__early_depth_bottleneck__read \ + bdw__render_pipe_profile__early_depth_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile :: Samples Blended */ +#define chv__render_pipe_profile__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Render Metrics for 3D Pipeline Profile :: Early Depth Test Fails */ +#define chv__render_pipe_profile__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Render Metrics for 3D Pipeline Profile :: Shader Memory Accesses */ +#define chv__render_pipe_profile__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Render Metrics for 3D Pipeline Profile :: HS Threads Dispatched */ +#define chv__render_pipe_profile__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Render Metrics for 3D Pipeline Profile :: SLM Bytes Written */ +#define chv__render_pipe_profile__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Render Metrics for 3D Pipeline Profile :: L3 Shader Throughput */ +#define chv__render_pipe_profile__l3_shader_throughput__read \ + bdw__render_basic__l3_shader_throughput__read + +/* Render Metrics for 3D Pipeline Profile :: Samples Killed in FS */ +#define chv__render_pipe_profile__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Render Metrics for 3D Pipeline Profile :: SO Stall */ +#define chv__render_pipe_profile__so_stall__read \ + bdw__render_pipe_profile__so_stall__read + +/* Render Metrics for 3D Pipeline Profile :: Shader Atomic Memory Accesses */ +#define chv__render_pipe_profile__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set HDCAndSF :: GPU Core Clocks */ +#define chv__hdc_and_sf__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set HDCAndSF :: EU Active */ +#define chv__hdc_and_sf__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set HDCAndSF :: EU Both FPU Pipes Active */ +#define chv__hdc_and_sf__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set HDCAndSF :: VS Send Pipe Active */ +#define chv__hdc_and_sf__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set HDCAndSF :: VS FPU1 Pipe Active */ +#define chv__hdc_and_sf__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set HDCAndSF :: GS Threads Dispatched */ +#define chv__hdc_and_sf__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set HDCAndSF :: Early Hi-Depth Test Fails */ +#define chv__hdc_and_sf__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set HDCAndSF :: FS Both FPU Active */ +#define chv__hdc_and_sf__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set HDCAndSF :: VS Threads Dispatched */ +#define chv__hdc_and_sf__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set HDCAndSF :: Polygon Data Ready */ +#define chv__hdc_and_sf__poly_data_ready__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set HDCAndSF :: FS Threads Dispatched */ +#define chv__hdc_and_sf__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss2) */ +#define chv__hdc_and_sf__non_sampler_shader12_access_stalled_on_l3__read \ + bdw__hdc_and_sf__non_sampler_shader12_access_stalled_on_l3__read + +/* Metric set HDCAndSF :: Shader Barrier Messages */ +#define chv__hdc_and_sf__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set HDCAndSF :: Sampler Texels */ +#define chv__hdc_and_sf__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set HDCAndSF :: Pixels Failing Tests */ +#define chv__hdc_and_sf__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set HDCAndSF :: GPU Time Elapsed */ +#define chv__hdc_and_sf__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set HDCAndSF :: AVG GPU Core Frequency */ +#define chv__hdc_and_sf__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set HDCAndSF :: AVG GPU Core Frequency */ +#define chv__hdc_and_sf__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set HDCAndSF :: Sampler Texels Misses */ +#define chv__hdc_and_sf__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */ +#define chv__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read \ + bdw__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read + +/* Metric set HDCAndSF :: CS Threads Dispatched */ +#define chv__hdc_and_sf__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss2) */ +#define chv__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read \ + bdw__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read + +/* Metric set HDCAndSF :: SLM Bytes Read */ +#define chv__hdc_and_sf__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set HDCAndSF :: PS FPU1 Pipe Active */ +#define chv__hdc_and_sf__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set HDCAndSF :: PS Send Pipeline Active */ +#define chv__hdc_and_sf__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set HDCAndSF :: VS FPU0 Pipe Active */ +#define chv__hdc_and_sf__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set HDCAndSF :: GPU Busy */ +#define chv__hdc_and_sf__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */ +#define chv__hdc_and_sf__non_sampler_shader10_access_stalled_on_l3__read \ + bdw__hdc_and_sf__non_sampler_shader10_access_stalled_on_l3__read + +/* Metric set HDCAndSF :: Rasterized Pixels */ +#define chv__hdc_and_sf__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set HDCAndSF :: PS FPU0 Pipe Active */ +#define chv__hdc_and_sf__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set HDCAndSF :: DS Threads Dispatched */ +#define chv__hdc_and_sf__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set HDCAndSF :: Samples Written */ +#define chv__hdc_and_sf__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set HDCAndSF :: EU Stall */ +#define chv__hdc_and_sf__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set HDCAndSF :: Samples Blended */ +#define chv__hdc_and_sf__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set HDCAndSF :: Early Depth Test Fails */ +#define chv__hdc_and_sf__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set HDCAndSF :: Shader Memory Accesses */ +#define chv__hdc_and_sf__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set HDCAndSF :: HS Threads Dispatched */ +#define chv__hdc_and_sf__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */ +#define chv__hdc_and_sf__non_sampler_shader11_access_stalled_on_l3__read \ + bdw__hdc_and_sf__non_sampler_shader11_access_stalled_on_l3__read + +/* Metric set HDCAndSF :: SLM Bytes Written */ +#define chv__hdc_and_sf__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set HDCAndSF :: L3 Shader Throughput */ +#define chv__hdc_and_sf__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set HDCAndSF :: Samples Killed in FS */ +#define chv__hdc_and_sf__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */ +#define chv__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read \ + bdw__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read + +/* Metric set HDCAndSF :: Shader Atomic Memory Accesses */ +#define chv__hdc_and_sf__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set L3_1 :: GPU Core Clocks */ +#define chv__l3_1__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set L3_1 :: EU Active */ +#define chv__l3_1__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set L3_1 :: Slice1 L3 Bank1 Stalled */ +#define chv__l3_1__l31_bank1_stalled__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Metric set L3_1 :: EU Both FPU Pipes Active */ +#define chv__l3_1__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set L3_1 :: VS Send Pipe Active */ +#define chv__l3_1__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set L3_1 :: VS FPU1 Pipe Active */ +#define chv__l3_1__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set L3_1 :: GS Threads Dispatched */ +#define chv__l3_1__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set L3_1 :: Early Hi-Depth Test Fails */ +#define chv__l3_1__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set L3_1 :: FS Both FPU Active */ +#define chv__l3_1__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set L3_1 :: VS Threads Dispatched */ +#define chv__l3_1__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set L3_1 :: FS Threads Dispatched */ +#define chv__l3_1__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set L3_1 :: Shader Barrier Messages */ +#define chv__l3_1__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set L3_1 :: Slice1 L3 Bank0 Stalled */ +#define chv__l3_1__l31_bank0_stalled__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set L3_1 :: Sampler Texels */ +#define chv__l3_1__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set L3_1 :: Pixels Failing Tests */ +#define chv__l3_1__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set L3_1 :: GPU Time Elapsed */ +#define chv__l3_1__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set L3_1 :: AVG GPU Core Frequency */ +#define chv__l3_1__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set L3_1 :: AVG GPU Core Frequency */ +#define chv__l3_1__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set L3_1 :: Sampler Texels Misses */ +#define chv__l3_1__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set L3_1 :: CS Threads Dispatched */ +#define chv__l3_1__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set L3_1 :: SLM Bytes Read */ +#define chv__l3_1__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set L3_1 :: PS FPU1 Pipe Active */ +#define chv__l3_1__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set L3_1 :: PS Send Pipeline Active */ +#define chv__l3_1__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set L3_1 :: VS FPU0 Pipe Active */ +#define chv__l3_1__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set L3_1 :: GPU Busy */ +#define chv__l3_1__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set L3_1 :: Rasterized Pixels */ +#define chv__l3_1__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set L3_1 :: Slice1 L3 Bank1 Active */ +#define chv__l3_1__l31_bank1_active__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set L3_1 :: PS FPU0 Pipe Active */ +#define chv__l3_1__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set L3_1 :: DS Threads Dispatched */ +#define chv__l3_1__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set L3_1 :: Samples Written */ +#define chv__l3_1__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set L3_1 :: EU Stall */ +#define chv__l3_1__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set L3_1 :: Slice1 L3 Bank0 Active */ +#define chv__l3_1__l31_bank0_active__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set L3_1 :: Samples Blended */ +#define chv__l3_1__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set L3_1 :: Early Depth Test Fails */ +#define chv__l3_1__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set L3_1 :: Shader Memory Accesses */ +#define chv__l3_1__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set L3_1 :: HS Threads Dispatched */ +#define chv__l3_1__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set L3_1 :: SLM Bytes Written */ +#define chv__l3_1__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set L3_1 :: L3 Shader Throughput */ +#define chv__l3_1__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set L3_1 :: Samples Killed in FS */ +#define chv__l3_1__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set L3_1 :: Shader Atomic Memory Accesses */ +#define chv__l3_1__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set L3_2 :: GPU Core Clocks */ +#define chv__l3_2__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set L3_2 :: EU Active */ +#define chv__l3_2__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set L3_2 :: Slice0 L3 Bank1 Active */ +#define chv__l3_2__l30_bank1_active__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set L3_2 :: EU Both FPU Pipes Active */ +#define chv__l3_2__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set L3_2 :: VS Send Pipe Active */ +#define chv__l3_2__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set L3_2 :: VS FPU1 Pipe Active */ +#define chv__l3_2__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set L3_2 :: GS Threads Dispatched */ +#define chv__l3_2__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set L3_2 :: Early Hi-Depth Test Fails */ +#define chv__l3_2__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set L3_2 :: FS Both FPU Active */ +#define chv__l3_2__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set L3_2 :: VS Threads Dispatched */ +#define chv__l3_2__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set L3_2 :: Slice0 L3 Bank1 Stalled */ +#define chv__l3_2__l30_bank1_stalled__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Metric set L3_2 :: FS Threads Dispatched */ +#define chv__l3_2__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set L3_2 :: Shader Barrier Messages */ +#define chv__l3_2__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set L3_2 :: Sampler Texels */ +#define chv__l3_2__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set L3_2 :: Pixels Failing Tests */ +#define chv__l3_2__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set L3_2 :: GPU Time Elapsed */ +#define chv__l3_2__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set L3_2 :: AVG GPU Core Frequency */ +#define chv__l3_2__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set L3_2 :: AVG GPU Core Frequency */ +#define chv__l3_2__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set L3_2 :: Sampler Texels Misses */ +#define chv__l3_2__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set L3_2 :: CS Threads Dispatched */ +#define chv__l3_2__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set L3_2 :: SLM Bytes Read */ +#define chv__l3_2__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set L3_2 :: PS FPU1 Pipe Active */ +#define chv__l3_2__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set L3_2 :: PS Send Pipeline Active */ +#define chv__l3_2__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set L3_2 :: VS FPU0 Pipe Active */ +#define chv__l3_2__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set L3_2 :: GPU Busy */ +#define chv__l3_2__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set L3_2 :: Slice0 L3 Bank0 Active */ +#define chv__l3_2__l30_bank0_active__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set L3_2 :: Rasterized Pixels */ +#define chv__l3_2__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set L3_2 :: PS FPU0 Pipe Active */ +#define chv__l3_2__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set L3_2 :: Slice0 L3 Bank0 Stalled */ +#define chv__l3_2__l30_bank0_stalled__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set L3_2 :: DS Threads Dispatched */ +#define chv__l3_2__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set L3_2 :: Samples Written */ +#define chv__l3_2__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set L3_2 :: EU Stall */ +#define chv__l3_2__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set L3_2 :: Samples Blended */ +#define chv__l3_2__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set L3_2 :: Early Depth Test Fails */ +#define chv__l3_2__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set L3_2 :: Shader Memory Accesses */ +#define chv__l3_2__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set L3_2 :: HS Threads Dispatched */ +#define chv__l3_2__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set L3_2 :: SLM Bytes Written */ +#define chv__l3_2__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set L3_2 :: L3 Shader Throughput */ +#define chv__l3_2__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set L3_2 :: Samples Killed in FS */ +#define chv__l3_2__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set L3_2 :: Shader Atomic Memory Accesses */ +#define chv__l3_2__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set L3_3 :: GPU Core Clocks */ +#define chv__l3_3__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set L3_3 :: EU Active */ +#define chv__l3_3__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set L3_3 :: EU Both FPU Pipes Active */ +#define chv__l3_3__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set L3_3 :: VS Send Pipe Active */ +#define chv__l3_3__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set L3_3 :: VS FPU1 Pipe Active */ +#define chv__l3_3__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set L3_3 :: GS Threads Dispatched */ +#define chv__l3_3__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set L3_3 :: Early Hi-Depth Test Fails */ +#define chv__l3_3__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set L3_3 :: FS Both FPU Active */ +#define chv__l3_3__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set L3_3 :: VS Threads Dispatched */ +#define chv__l3_3__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set L3_3 :: FS Threads Dispatched */ +#define chv__l3_3__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set L3_3 :: Slice0 L3 Bank3 Stalled */ +#define chv__l3_3__l30_bank3_stalled__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set L3_3 :: Shader Barrier Messages */ +#define chv__l3_3__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set L3_3 :: Sampler Texels */ +#define chv__l3_3__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set L3_3 :: Pixels Failing Tests */ +#define chv__l3_3__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set L3_3 :: GPU Time Elapsed */ +#define chv__l3_3__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set L3_3 :: AVG GPU Core Frequency */ +#define chv__l3_3__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set L3_3 :: AVG GPU Core Frequency */ +#define chv__l3_3__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set L3_3 :: Sampler Texels Misses */ +#define chv__l3_3__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set L3_3 :: CS Threads Dispatched */ +#define chv__l3_3__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set L3_3 :: SLM Bytes Read */ +#define chv__l3_3__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set L3_3 :: PS FPU1 Pipe Active */ +#define chv__l3_3__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set L3_3 :: Slice0 L3 Bank3 Active */ +#define chv__l3_3__l30_bank3_active__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set L3_3 :: PS Send Pipeline Active */ +#define chv__l3_3__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set L3_3 :: VS FPU0 Pipe Active */ +#define chv__l3_3__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set L3_3 :: GPU Busy */ +#define chv__l3_3__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set L3_3 :: Slice1 L3 Bank3 Active */ +#define chv__l3_3__l31_bank3_active__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set L3_3 :: Slice1 L3 Bank3 Stalled */ +#define chv__l3_3__l31_bank3_stalled__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Metric set L3_3 :: Rasterized Pixels */ +#define chv__l3_3__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set L3_3 :: PS FPU0 Pipe Active */ +#define chv__l3_3__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set L3_3 :: DS Threads Dispatched */ +#define chv__l3_3__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set L3_3 :: Samples Written */ +#define chv__l3_3__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set L3_3 :: EU Stall */ +#define chv__l3_3__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set L3_3 :: Samples Blended */ +#define chv__l3_3__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set L3_3 :: Early Depth Test Fails */ +#define chv__l3_3__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set L3_3 :: Shader Memory Accesses */ +#define chv__l3_3__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set L3_3 :: HS Threads Dispatched */ +#define chv__l3_3__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set L3_3 :: SLM Bytes Written */ +#define chv__l3_3__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set L3_3 :: L3 Shader Throughput */ +#define chv__l3_3__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set L3_3 :: Samples Killed in FS */ +#define chv__l3_3__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set L3_3 :: Shader Atomic Memory Accesses */ +#define chv__l3_3__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set L3_4 :: GPU Core Clocks */ +#define chv__l3_4__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set L3_4 :: EU Active */ +#define chv__l3_4__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set L3_4 :: EU Both FPU Pipes Active */ +#define chv__l3_4__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set L3_4 :: VS Send Pipe Active */ +#define chv__l3_4__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set L3_4 :: VS FPU1 Pipe Active */ +#define chv__l3_4__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set L3_4 :: GS Threads Dispatched */ +#define chv__l3_4__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set L3_4 :: Early Hi-Depth Test Fails */ +#define chv__l3_4__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set L3_4 :: FS Both FPU Active */ +#define chv__l3_4__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set L3_4 :: VS Threads Dispatched */ +#define chv__l3_4__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set L3_4 :: FS Threads Dispatched */ +#define chv__l3_4__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set L3_4 :: Shader Barrier Messages */ +#define chv__l3_4__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set L3_4 :: Sampler Texels */ +#define chv__l3_4__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set L3_4 :: Pixels Failing Tests */ +#define chv__l3_4__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set L3_4 :: GPU Time Elapsed */ +#define chv__l3_4__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set L3_4 :: AVG GPU Core Frequency */ +#define chv__l3_4__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set L3_4 :: AVG GPU Core Frequency */ +#define chv__l3_4__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set L3_4 :: Sampler Texels Misses */ +#define chv__l3_4__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set L3_4 :: CS Threads Dispatched */ +#define chv__l3_4__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set L3_4 :: SLM Bytes Read */ +#define chv__l3_4__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set L3_4 :: PS FPU1 Pipe Active */ +#define chv__l3_4__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set L3_4 :: Slice0 L3 Bank2 Stalled */ +#define chv__l3_4__l30_bank2_stalled__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set L3_4 :: PS Send Pipeline Active */ +#define chv__l3_4__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set L3_4 :: VS FPU0 Pipe Active */ +#define chv__l3_4__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set L3_4 :: GPU Busy */ +#define chv__l3_4__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set L3_4 :: Slice1 L3 Bank2 Active */ +#define chv__l3_4__l31_bank2_active__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set L3_4 :: Slice0 L3 Bank2 Active */ +#define chv__l3_4__l30_bank2_active__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set L3_4 :: Rasterized Pixels */ +#define chv__l3_4__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set L3_4 :: Slice1 L3 Bank2 Stalled */ +#define chv__l3_4__l31_bank2_stalled__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Metric set L3_4 :: PS FPU0 Pipe Active */ +#define chv__l3_4__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set L3_4 :: DS Threads Dispatched */ +#define chv__l3_4__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set L3_4 :: Samples Written */ +#define chv__l3_4__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set L3_4 :: EU Stall */ +#define chv__l3_4__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set L3_4 :: Samples Blended */ +#define chv__l3_4__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set L3_4 :: Early Depth Test Fails */ +#define chv__l3_4__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set L3_4 :: Shader Memory Accesses */ +#define chv__l3_4__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set L3_4 :: HS Threads Dispatched */ +#define chv__l3_4__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set L3_4 :: SLM Bytes Written */ +#define chv__l3_4__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set L3_4 :: L3 Shader Throughput */ +#define chv__l3_4__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set L3_4 :: Samples Killed in FS */ +#define chv__l3_4__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set L3_4 :: Shader Atomic Memory Accesses */ +#define chv__l3_4__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */ +#define chv__rasterizer_and_pixel_backend__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set RasterizerAndPixelBackend :: EU Active */ +#define chv__rasterizer_and_pixel_backend__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set RasterizerAndPixelBackend :: EU Both FPU Pipes Active */ +#define chv__rasterizer_and_pixel_backend__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set RasterizerAndPixelBackend :: Slice1 Rasterizer Input Available */ +#define chv__rasterizer_and_pixel_backend__rasterizer1_input_available__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Metric set RasterizerAndPixelBackend :: VS Send Pipe Active */ +#define chv__rasterizer_and_pixel_backend__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set RasterizerAndPixelBackend :: VS FPU1 Pipe Active */ +#define chv__rasterizer_and_pixel_backend__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */ +#define chv__rasterizer_and_pixel_backend__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */ +#define chv__rasterizer_and_pixel_backend__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set RasterizerAndPixelBackend :: FS Both FPU Active */ +#define chv__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */ +#define chv__rasterizer_and_pixel_backend__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */ +#define chv__rasterizer_and_pixel_backend__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Pixel Values Ready */ +#define chv__rasterizer_and_pixel_backend__pixel_values0_ready__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */ +#define chv__rasterizer_and_pixel_backend__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set RasterizerAndPixelBackend :: Sampler Texels */ +#define chv__rasterizer_and_pixel_backend__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */ +#define chv__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */ +#define chv__rasterizer_and_pixel_backend__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ +#define chv__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ +#define chv__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */ +#define chv__rasterizer_and_pixel_backend__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */ +#define chv__rasterizer_and_pixel_backend__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */ +#define chv__rasterizer_and_pixel_backend__rasterizer0_input_available__read \ + bdw__render_pipe_profile__cl_bottleneck__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Post-EarlyZ Pixel Data Ready */ +#define chv__rasterizer_and_pixel_backend__pixel_data0_ready__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */ +#define chv__rasterizer_and_pixel_backend__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set RasterizerAndPixelBackend :: PS FPU1 Pipe Active */ +#define chv__rasterizer_and_pixel_backend__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set RasterizerAndPixelBackend :: PS Send Pipeline Active */ +#define chv__rasterizer_and_pixel_backend__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set RasterizerAndPixelBackend :: VS FPU0 Pipe Active */ +#define chv__rasterizer_and_pixel_backend__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set RasterizerAndPixelBackend :: GPU Busy */ +#define chv__rasterizer_and_pixel_backend__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set RasterizerAndPixelBackend :: Slice1 Pixel Values Ready */ +#define chv__rasterizer_and_pixel_backend__pixel_values1_ready__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set RasterizerAndPixelBackend :: Slice1 PS Output Available */ +#define chv__rasterizer_and_pixel_backend__ps_output1_available__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */ +#define chv__rasterizer_and_pixel_backend__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set RasterizerAndPixelBackend :: PS FPU0 Pipe Active */ +#define chv__rasterizer_and_pixel_backend__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */ +#define chv__rasterizer_and_pixel_backend__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set RasterizerAndPixelBackend :: Samples Written */ +#define chv__rasterizer_and_pixel_backend__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set RasterizerAndPixelBackend :: EU Stall */ +#define chv__rasterizer_and_pixel_backend__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */ +#define chv__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set RasterizerAndPixelBackend :: Samples Blended */ +#define chv__rasterizer_and_pixel_backend__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */ +#define chv__rasterizer_and_pixel_backend__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set RasterizerAndPixelBackend :: Slice1 Rasterizer Output Ready */ +#define chv__rasterizer_and_pixel_backend__rasterizer1_output_ready__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Metric set RasterizerAndPixelBackend :: Slice1 Post-EarlyZ Pixel Data Ready */ +#define chv__rasterizer_and_pixel_backend__pixel_data1_ready__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */ +#define chv__rasterizer_and_pixel_backend__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */ +#define chv__rasterizer_and_pixel_backend__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */ +#define chv__rasterizer_and_pixel_backend__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */ +#define chv__rasterizer_and_pixel_backend__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */ +#define chv__rasterizer_and_pixel_backend__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 PS Output Available */ +#define chv__rasterizer_and_pixel_backend__ps_output0_available__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */ +#define chv__rasterizer_and_pixel_backend__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set Sampler_1 :: GPU Core Clocks */ +#define chv__sampler_1__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set Sampler_1 :: EU Active */ +#define chv__sampler_1__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set Sampler_1 :: EU Both FPU Pipes Active */ +#define chv__sampler_1__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set Sampler_1 :: VS Send Pipe Active */ +#define chv__sampler_1__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set Sampler_1 :: VS FPU1 Pipe Active */ +#define chv__sampler_1__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set Sampler_1 :: GS Threads Dispatched */ +#define chv__sampler_1__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set Sampler_1 :: Slice1 Subslice0 Input Available */ +#define chv__sampler_1__sampler10_input_available__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Metric set Sampler_1 :: Early Hi-Depth Test Fails */ +#define chv__sampler_1__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set Sampler_1 :: FS Both FPU Active */ +#define chv__sampler_1__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set Sampler_1 :: VS Threads Dispatched */ +#define chv__sampler_1__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set Sampler_1 :: FS Threads Dispatched */ +#define chv__sampler_1__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set Sampler_1 :: Shader Barrier Messages */ +#define chv__sampler_1__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set Sampler_1 :: Sampler Texels */ +#define chv__sampler_1__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set Sampler_1 :: Pixels Failing Tests */ +#define chv__sampler_1__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set Sampler_1 :: Slice1 Subslice2 Sampler Output Ready */ +#define chv__sampler_1__sampler12_output_ready__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set Sampler_1 :: GPU Time Elapsed */ +#define chv__sampler_1__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set Sampler_1 :: AVG GPU Core Frequency */ +#define chv__sampler_1__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set Sampler_1 :: AVG GPU Core Frequency */ +#define chv__sampler_1__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set Sampler_1 :: Sampler Texels Misses */ +#define chv__sampler_1__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set Sampler_1 :: CS Threads Dispatched */ +#define chv__sampler_1__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set Sampler_1 :: SLM Bytes Read */ +#define chv__sampler_1__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set Sampler_1 :: PS FPU1 Pipe Active */ +#define chv__sampler_1__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set Sampler_1 :: PS Send Pipeline Active */ +#define chv__sampler_1__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set Sampler_1 :: VS FPU0 Pipe Active */ +#define chv__sampler_1__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set Sampler_1 :: GPU Busy */ +#define chv__sampler_1__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set Sampler_1 :: Slice1 Subslice1 Input Available */ +#define chv__sampler_1__sampler11_input_available__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set Sampler_1 :: Rasterized Pixels */ +#define chv__sampler_1__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set Sampler_1 :: PS FPU0 Pipe Active */ +#define chv__sampler_1__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set Sampler_1 :: DS Threads Dispatched */ +#define chv__sampler_1__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set Sampler_1 :: Samples Written */ +#define chv__sampler_1__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set Sampler_1 :: EU Stall */ +#define chv__sampler_1__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set Sampler_1 :: Samples Blended */ +#define chv__sampler_1__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set Sampler_1 :: Early Depth Test Fails */ +#define chv__sampler_1__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set Sampler_1 :: Slice1 Subslice2 Input Available */ +#define chv__sampler_1__sampler12_input_available__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set Sampler_1 :: Slice1 Subslice0 Sampler Output Ready */ +#define chv__sampler_1__sampler10_output_ready__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set Sampler_1 :: Shader Memory Accesses */ +#define chv__sampler_1__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set Sampler_1 :: Slice1 Subslice1 Sampler Output Ready */ +#define chv__sampler_1__sampler11_output_ready__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set Sampler_1 :: HS Threads Dispatched */ +#define chv__sampler_1__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set Sampler_1 :: SLM Bytes Written */ +#define chv__sampler_1__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set Sampler_1 :: L3 Shader Throughput */ +#define chv__sampler_1__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set Sampler_1 :: Samples Killed in FS */ +#define chv__sampler_1__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set Sampler_1 :: Shader Atomic Memory Accesses */ +#define chv__sampler_1__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set Sampler_2 :: GPU Core Clocks */ +#define chv__sampler_2__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set Sampler_2 :: EU Active */ +#define chv__sampler_2__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set Sampler_2 :: Slice0 Subslice2 Input Available */ +#define chv__sampler_2__sampler02_input_available__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set Sampler_2 :: EU Both FPU Pipes Active */ +#define chv__sampler_2__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set Sampler_2 :: VS Send Pipe Active */ +#define chv__sampler_2__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set Sampler_2 :: Slice0 Subslice0 Input Available */ +#define chv__sampler_2__sampler00_input_available__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Metric set Sampler_2 :: VS FPU1 Pipe Active */ +#define chv__sampler_2__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set Sampler_2 :: GS Threads Dispatched */ +#define chv__sampler_2__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set Sampler_2 :: Early Hi-Depth Test Fails */ +#define chv__sampler_2__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set Sampler_2 :: FS Both FPU Active */ +#define chv__sampler_2__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set Sampler_2 :: VS Threads Dispatched */ +#define chv__sampler_2__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set Sampler_2 :: Slice0 Subslice2 Sampler Output Ready */ +#define chv__sampler_2__sampler02_output_ready__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set Sampler_2 :: FS Threads Dispatched */ +#define chv__sampler_2__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set Sampler_2 :: Shader Barrier Messages */ +#define chv__sampler_2__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set Sampler_2 :: Slice0 Subslice1 Input Available */ +#define chv__sampler_2__sampler01_input_available__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set Sampler_2 :: Sampler Texels */ +#define chv__sampler_2__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set Sampler_2 :: Pixels Failing Tests */ +#define chv__sampler_2__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set Sampler_2 :: GPU Time Elapsed */ +#define chv__sampler_2__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set Sampler_2 :: AVG GPU Core Frequency */ +#define chv__sampler_2__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set Sampler_2 :: AVG GPU Core Frequency */ +#define chv__sampler_2__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set Sampler_2 :: Sampler Texels Misses */ +#define chv__sampler_2__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set Sampler_2 :: CS Threads Dispatched */ +#define chv__sampler_2__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set Sampler_2 :: SLM Bytes Read */ +#define chv__sampler_2__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set Sampler_2 :: PS FPU1 Pipe Active */ +#define chv__sampler_2__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set Sampler_2 :: PS Send Pipeline Active */ +#define chv__sampler_2__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set Sampler_2 :: VS FPU0 Pipe Active */ +#define chv__sampler_2__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set Sampler_2 :: GPU Busy */ +#define chv__sampler_2__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set Sampler_2 :: Rasterized Pixels */ +#define chv__sampler_2__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set Sampler_2 :: PS FPU0 Pipe Active */ +#define chv__sampler_2__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set Sampler_2 :: DS Threads Dispatched */ +#define chv__sampler_2__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set Sampler_2 :: Samples Written */ +#define chv__sampler_2__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set Sampler_2 :: EU Stall */ +#define chv__sampler_2__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set Sampler_2 :: Samples Blended */ +#define chv__sampler_2__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set Sampler_2 :: Early Depth Test Fails */ +#define chv__sampler_2__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set Sampler_2 :: Slice0 Subslice0 Sampler Output Ready */ +#define chv__sampler_2__sampler00_output_ready__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set Sampler_2 :: Slice0 Subslice1 Sampler Output Ready */ +#define chv__sampler_2__sampler01_output_ready__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set Sampler_2 :: Shader Memory Accesses */ +#define chv__sampler_2__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set Sampler_2 :: HS Threads Dispatched */ +#define chv__sampler_2__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set Sampler_2 :: SLM Bytes Written */ +#define chv__sampler_2__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set Sampler_2 :: L3 Shader Throughput */ +#define chv__sampler_2__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set Sampler_2 :: Samples Killed in FS */ +#define chv__sampler_2__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set Sampler_2 :: Shader Atomic Memory Accesses */ +#define chv__sampler_2__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set TDL_1 :: GPU Core Clocks */ +#define chv__tdl_1__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set TDL_1 :: EU Active */ +#define chv__tdl_1__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set TDL_1 :: EU Both FPU Pipes Active */ +#define chv__tdl_1__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set TDL_1 :: VS Send Pipe Active */ +#define chv__tdl_1__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set TDL_1 :: VS FPU1 Pipe Active */ +#define chv__tdl_1__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set TDL_1 :: GS Threads Dispatched */ +#define chv__tdl_1__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set TDL_1 :: Early Hi-Depth Test Fails */ +#define chv__tdl_1__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set TDL_1 :: FS Both FPU Active */ +#define chv__tdl_1__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set TDL_1 :: VS Threads Dispatched */ +#define chv__tdl_1__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice1 Subslice1 Thread Dispatcher */ +#define chv__tdl_1__ps_thread11_ready_for_dispatch__read \ + bdw__render_pipe_profile__cl_bottleneck__read + +/* Metric set TDL_1 :: FS Threads Dispatched */ +#define chv__tdl_1__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set TDL_1 :: Non-PS Thread Ready For Dispatch on Slice1 Subslice2 Thread Dispatcher */ +#define chv__tdl_1__non_ps_thread12_ready_for_dispatch__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Metric set TDL_1 :: Shader Barrier Messages */ +#define chv__tdl_1__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_1 :: Sampler Texels */ +#define chv__tdl_1__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set TDL_1 :: Pixels Failing Tests */ +#define chv__tdl_1__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set TDL_1 :: Non-PS Thread Ready For Dispatch on Slice1 Subslice0 Thread Dispatcher */ +#define chv__tdl_1__non_ps_thread10_ready_for_dispatch__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Metric set TDL_1 :: Thread Header Ready on Slice0 Subslice1 Thread Dispatcher Port 0 */ +#define chv__tdl_1__thread_header01_ready_port0__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set TDL_1 :: Thread Header Ready on Slice0 Subslice1 Thread Dispatcher Port 1 */ +#define chv__tdl_1__thread_header01_ready_port1__read \ + bdw__render_pipe_profile__ds_stall__read + +/* Metric set TDL_1 :: GPU Time Elapsed */ +#define chv__tdl_1__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set TDL_1 :: AVG GPU Core Frequency */ +#define chv__tdl_1__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set TDL_1 :: AVG GPU Core Frequency */ +#define chv__tdl_1__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set TDL_1 :: Sampler Texels Misses */ +#define chv__tdl_1__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set TDL_1 :: CS Threads Dispatched */ +#define chv__tdl_1__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set TDL_1 :: SLM Bytes Read */ +#define chv__tdl_1__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set TDL_1 :: PS FPU1 Pipe Active */ +#define chv__tdl_1__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set TDL_1 :: PS Send Pipeline Active */ +#define chv__tdl_1__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set TDL_1 :: VS FPU0 Pipe Active */ +#define chv__tdl_1__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set TDL_1 :: GPU Busy */ +#define chv__tdl_1__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set TDL_1 :: Thread Header Ready on Slice0 Subslice2 Thread Dispatcher Port 1 */ +#define chv__tdl_1__thread_header02_ready_port1__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Metric set TDL_1 :: Thread Header Ready on Slice0 Subslice2 Thread Dispatcher Port 0 */ +#define chv__tdl_1__thread_header02_ready_port0__read \ + bdw__render_pipe_profile__so_stall__read + +/* Metric set TDL_1 :: Rasterized Pixels */ +#define chv__tdl_1__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set TDL_1 :: PS FPU0 Pipe Active */ +#define chv__tdl_1__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set TDL_1 :: DS Threads Dispatched */ +#define chv__tdl_1__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set TDL_1 :: Samples Written */ +#define chv__tdl_1__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set TDL_1 :: EU Stall */ +#define chv__tdl_1__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set TDL_1 :: Samples Blended */ +#define chv__tdl_1__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set TDL_1 :: Early Depth Test Fails */ +#define chv__tdl_1__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice1 Subslice2 Thread Dispatcher */ +#define chv__tdl_1__ps_thread12_ready_for_dispatch__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice1 Subslice0 Thread Dispatcher */ +#define chv__tdl_1__ps_thread10_ready_for_dispatch__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set TDL_1 :: Non-PS Thread Ready For Dispatch on Slice1 Subslice1 Thread Dispatcher */ +#define chv__tdl_1__non_ps_thread11_ready_for_dispatch__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set TDL_1 :: Shader Memory Accesses */ +#define chv__tdl_1__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set TDL_1 :: HS Threads Dispatched */ +#define chv__tdl_1__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set TDL_1 :: SLM Bytes Written */ +#define chv__tdl_1__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set TDL_1 :: L3 Shader Throughput */ +#define chv__tdl_1__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set TDL_1 :: Samples Killed in FS */ +#define chv__tdl_1__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set TDL_1 :: Thread Header Ready on Slice0 Subslice0 Thread Dispatcher Port 0 */ +#define chv__tdl_1__thread_header00_ready_port0__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set TDL_1 :: Shader Atomic Memory Accesses */ +#define chv__tdl_1__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set TDL_1 :: Thread Header Ready on Slice0 Subslice0 Thread Dispatcher Port 1 */ +#define chv__tdl_1__thread_header00_ready_port1__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set TDL_2 :: GPU Core Clocks */ +#define chv__tdl_2__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set TDL_2 :: EU Active */ +#define chv__tdl_2__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set TDL_2 :: EU Both FPU Pipes Active */ +#define chv__tdl_2__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice1 Thread Dispatcher Port 1 */ +#define chv__tdl_2__thread_header11_ready_port1__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set TDL_2 :: VS Send Pipe Active */ +#define chv__tdl_2__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set TDL_2 :: VS FPU1 Pipe Active */ +#define chv__tdl_2__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set TDL_2 :: GS Threads Dispatched */ +#define chv__tdl_2__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set TDL_2 :: Early Hi-Depth Test Fails */ +#define chv__tdl_2__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set TDL_2 :: FS Both FPU Active */ +#define chv__tdl_2__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set TDL_2 :: VS Threads Dispatched */ +#define chv__tdl_2__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set TDL_2 :: FS Threads Dispatched */ +#define chv__tdl_2__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set TDL_2 :: Non-PS Thread Ready For Dispatch on Slice0 Subslice2 Thread Dispatcher */ +#define chv__tdl_2__non_ps_thread02_ready_for_dispatch__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set TDL_2 :: Shader Barrier Messages */ +#define chv__tdl_2__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_2 :: Sampler Texels */ +#define chv__tdl_2__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set TDL_2 :: Pixels Failing Tests */ +#define chv__tdl_2__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set TDL_2 :: GPU Time Elapsed */ +#define chv__tdl_2__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set TDL_2 :: AVG GPU Core Frequency */ +#define chv__tdl_2__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set TDL_2 :: AVG GPU Core Frequency */ +#define chv__tdl_2__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set TDL_2 :: Sampler Texels Misses */ +#define chv__tdl_2__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set TDL_2 :: Non-PS Thread Ready For Dispatch on Slice0 Subslice0 Thread Dispatcher */ +#define chv__tdl_2__non_ps_thread00_ready_for_dispatch__read \ + bdw__render_pipe_profile__cl_bottleneck__read + +/* Metric set TDL_2 :: CS Threads Dispatched */ +#define chv__tdl_2__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set TDL_2 :: SLM Bytes Read */ +#define chv__tdl_2__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice1 Thread Dispatcher Port 0 */ +#define chv__tdl_2__thread_header11_ready_port0__read \ + bdw__render_pipe_profile__ds_stall__read + +/* Metric set TDL_2 :: PS FPU1 Pipe Active */ +#define chv__tdl_2__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set TDL_2 :: PS Send Pipeline Active */ +#define chv__tdl_2__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set TDL_2 :: VS FPU0 Pipe Active */ +#define chv__tdl_2__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set TDL_2 :: GPU Busy */ +#define chv__tdl_2__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice2 Thread Dispatcher Port 0 */ +#define chv__tdl_2__thread_header12_ready_port0__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set TDL_2 :: PS Thread Ready For Dispatch on Slice0 Subslice0 Thread Dispatcher */ +#define chv__tdl_2__ps_thread00_ready_for_dispatch__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Metric set TDL_2 :: Rasterized Pixels */ +#define chv__tdl_2__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set TDL_2 :: PS FPU0 Pipe Active */ +#define chv__tdl_2__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set TDL_2 :: DS Threads Dispatched */ +#define chv__tdl_2__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set TDL_2 :: Samples Written */ +#define chv__tdl_2__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice0 Thread Dispatcher Port 1 */ +#define chv__tdl_2__thread_header10_ready_port1__read \ + bdw__render_pipe_profile__so_stall__read + +/* Metric set TDL_2 :: EU Stall */ +#define chv__tdl_2__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set TDL_2 :: Samples Blended */ +#define chv__tdl_2__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set TDL_2 :: Early Depth Test Fails */ +#define chv__tdl_2__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_2 :: PS Thread Ready For Dispatch on Slice0 Subslice1 Thread Dispatcher */ +#define chv__tdl_2__ps_thread01_ready_for_dispatch__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice2 Thread Dispatcher Port 1 */ +#define chv__tdl_2__thread_header12_ready_port1__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set TDL_2 :: Shader Memory Accesses */ +#define chv__tdl_2__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set TDL_2 :: HS Threads Dispatched */ +#define chv__tdl_2__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set TDL_2 :: PS Thread Ready For Dispatch on Slice0 Subslice2 Thread Dispatcher */ +#define chv__tdl_2__ps_thread02_ready_for_dispatch__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set TDL_2 :: SLM Bytes Written */ +#define chv__tdl_2__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set TDL_2 :: L3 Shader Throughput */ +#define chv__tdl_2__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set TDL_2 :: Samples Killed in FS */ +#define chv__tdl_2__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice0 Thread Dispatcher Port 0 */ +#define chv__tdl_2__thread_header10_ready_port0__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Metric set TDL_2 :: Shader Atomic Memory Accesses */ +#define chv__tdl_2__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set TDL_2 :: Non-PS Thread Ready For Dispatch on Slice0 Subslice1 Thread Dispatcher */ +#define chv__tdl_2__non_ps_thread01_ready_for_dispatch__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* MDAPI testing set Gen8LP :: TestCounter7 */ +#define chv__test_oa__counter7__read \ + hsw__compute_extended__gpu_clocks__read + +/* MDAPI testing set Gen8LP :: GPU Time Elapsed */ +#define chv__test_oa__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* MDAPI testing set Gen8LP :: GPU Core Clocks */ +#define chv__test_oa__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* MDAPI testing set Gen8LP :: AVG GPU Core Frequency */ +#define chv__test_oa__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* MDAPI testing set Gen8LP :: AVG GPU Core Frequency */ +#define chv__test_oa__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* MDAPI testing set Gen8LP :: TestCounter8 */ +#define chv__test_oa__counter8__read \ + hsw__memory_reads__gpu_core_clocks__read + +/* MDAPI testing set Gen8LP :: TestCounter4 */ +#define chv__test_oa__counter4__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* MDAPI testing set Gen8LP :: TestCounter5 */ +#define chv__test_oa__counter5__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* MDAPI testing set Gen8LP :: TestCounter6 */ +#define chv__test_oa__counter6__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* MDAPI testing set Gen8LP :: TestCounter3 */ +#define chv__test_oa__counter3__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* MDAPI testing set Gen8LP :: TestCounter0 */ +#define chv__test_oa__counter0__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* MDAPI testing set Gen8LP :: TestCounter1 */ +#define chv__test_oa__counter1__read \ + hsw__compute_extended__eu_untyped_writes0__read + +/* MDAPI testing set Gen8LP :: TestCounter2 */ +#define chv__test_oa__counter2__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Render Metrics Basic Gen9 :: GPU Core Clocks */ +#define sklgt2__render_basic__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Render Metrics Basic Gen9 :: EU Active */ +#define sklgt2__render_basic__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Render Metrics Basic Gen9 :: L3 Misses */ +#define sklgt2__render_basic__l3_misses__read \ + hsw__compute_extended__typed_atomics0__read + +/* Render Metrics Basic Gen9 :: GTI L3 Throughput */ +#define sklgt2__render_basic__gti_l3_throughput__read \ + hsw__render_basic__gti_l3_throughput__read + +/* Render Metrics Basic Gen9 :: EU Both FPU Pipes Active */ +#define sklgt2__render_basic__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Render Metrics Basic Gen9 :: Sampler Cache Misses */ +static uint64_t +sklgt2__render_basic__sampler_l1_misses__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 4 READ 8 UMUL */ + uint64_t tmp0 = accumulator[query->b_offset + 4]; + uint64_t tmp1 = tmp0 * 8; + + return tmp1; +} + +/* Render Metrics Basic Gen9 :: VS Send Pipe Active */ +#define sklgt2__render_basic__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Render Metrics Basic Gen9 :: Sampler 1 Bottleneck */ +#define sklgt2__render_basic__sampler1_bottleneck__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Render Metrics Basic Gen9 :: VS FPU1 Pipe Active */ +#define sklgt2__render_basic__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Render Metrics Basic Gen9 :: GS Threads Dispatched */ +#define sklgt2__render_basic__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Render Metrics Basic Gen9 :: L3 Sampler Throughput */ +static uint64_t +sklgt2__render_basic__l3_sampler_throughput__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $SamplerL1Misses 64 UMUL */ + uint64_t tmp0 = sklgt2__render_basic__sampler_l1_misses__read(brw, query, accumulator) * 64; + + return tmp0; +} + +/* Render Metrics Basic Gen9 :: Early Hi-Depth Test Fails */ +#define sklgt2__render_basic__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Render Metrics Basic Gen9 :: FS Both FPU Active */ +#define sklgt2__render_basic__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Render Metrics Basic Gen9 :: VS Threads Dispatched */ +#define sklgt2__render_basic__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Render Metrics Basic Gen9 :: FS Threads Dispatched */ +#define sklgt2__render_basic__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Render Metrics Basic Gen9 :: Sampler 0 Busy */ +#define sklgt2__render_basic__sampler0_busy__read \ + bdw__render_basic__sampler0_busy__read + +/* Render Metrics Basic Gen9 :: Sampler 1 Busy */ +#define sklgt2__render_basic__sampler1_busy__read \ + bdw__render_basic__sampler1_busy__read + +/* Render Metrics Basic Gen9 :: Samplers Busy */ +#define sklgt2__render_basic__samplers_busy__read \ + bdw__render_basic__samplers_busy__read + +/* Render Metrics Basic Gen9 :: GTI Fixed Pipe Throughput */ +#define sklgt2__render_basic__gti_vf_throughput__read \ + bdw__render_basic__gti_vf_throughput__read + +/* Render Metrics Basic Gen9 :: Shader Barrier Messages */ +#define sklgt2__render_basic__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Render Metrics Basic Gen9 :: Sampler 0 Bottleneck */ +#define sklgt2__render_basic__sampler0_bottleneck__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Render Metrics Basic Gen9 :: Sampler Texels */ +#define sklgt2__render_basic__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Render Metrics Basic Gen9 :: Pixels Failing Tests */ +#define sklgt2__render_basic__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Render Metrics Basic Gen9 :: GPU Time Elapsed */ +#define sklgt2__render_basic__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Render Metrics Basic Gen9 :: AVG GPU Core Frequency */ +#define sklgt2__render_basic__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Render Metrics Basic Gen9 :: AVG GPU Core Frequency */ +#define sklgt2__render_basic__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Render Metrics Basic Gen9 :: Sampler Texels Misses */ +#define sklgt2__render_basic__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Render Metrics Basic Gen9 :: CS Threads Dispatched */ +#define sklgt2__render_basic__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Render Metrics Basic Gen9 :: Shader Memory Accesses */ +#define sklgt2__render_basic__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Render Metrics Basic Gen9 :: L3 Lookup Accesses w/o IC */ +static uint64_t +sklgt2__render_basic__l3_lookups__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $SamplerL1Misses $ShaderMemoryAccesses UADD */ + uint64_t tmp0 = sklgt2__render_basic__sampler_l1_misses__read(brw, query, accumulator) + sklgt2__render_basic__shader_memory_accesses__read(brw, query, accumulator); + + return tmp0; +} + +/* Render Metrics Basic Gen9 :: SLM Bytes Read */ +#define sklgt2__render_basic__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Render Metrics Basic Gen9 :: GTI Read Throughput */ +#define sklgt2__render_basic__gti_read_throughput__read \ + bdw__render_basic__gti_read_throughput__read + +/* Render Metrics Basic Gen9 :: PS FPU1 Pipe Active */ +#define sklgt2__render_basic__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Render Metrics Basic Gen9 :: PS Send Pipeline Active */ +#define sklgt2__render_basic__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Render Metrics Basic Gen9 :: Rasterized Pixels */ +#define sklgt2__render_basic__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Render Metrics Basic Gen9 :: GPU Busy */ +#define sklgt2__render_basic__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Render Metrics Basic Gen9 :: GTI Depth Throughput */ +#define sklgt2__render_basic__gti_depth_throughput__read \ + bdw__render_basic__gti_depth_throughput__read + +/* Render Metrics Basic Gen9 :: VS FPU0 Pipe Active */ +#define sklgt2__render_basic__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Render Metrics Basic Gen9 :: PS FPU0 Pipe Active */ +#define sklgt2__render_basic__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Render Metrics Basic Gen9 :: DS Threads Dispatched */ +#define sklgt2__render_basic__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Render Metrics Basic Gen9 :: Samples Written */ +#define sklgt2__render_basic__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Render Metrics Basic Gen9 :: EU Stall */ +#define sklgt2__render_basic__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Render Metrics Basic Gen9 :: Samples Blended */ +#define sklgt2__render_basic__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Render Metrics Basic Gen9 :: Early Depth Test Fails */ +#define sklgt2__render_basic__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Render Metrics Basic Gen9 :: Samplers Bottleneck */ +#define sklgt2__render_basic__sampler_bottleneck__read \ + bdw__render_basic__sampler_bottleneck__read + +/* Render Metrics Basic Gen9 :: GTI HDC TLB Lookup Throughput */ +#define sklgt2__render_basic__gti_hdc_lookups_throughput__read \ + bdw__render_basic__gti_hdc_lookups_throughput__read + +/* Render Metrics Basic Gen9 :: GTI RCC Throughput */ +#define sklgt2__render_basic__gti_rcc_throughput__read \ + bdw__render_basic__gti_rcc_throughput__read + +/* Render Metrics Basic Gen9 :: HS Threads Dispatched */ +#define sklgt2__render_basic__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Render Metrics Basic Gen9 :: GTI Write Throughput */ +#define sklgt2__render_basic__gti_write_throughput__read \ + hsw__render_basic__gti_write_throughput__read + +/* Render Metrics Basic Gen9 :: SLM Bytes Written */ +#define sklgt2__render_basic__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Render Metrics Basic Gen9 :: L3 Shader Throughput */ +#define sklgt2__render_basic__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Render Metrics Basic Gen9 :: Samples Killed in FS */ +#define sklgt2__render_basic__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Render Metrics Basic Gen9 :: Shader Atomic Memory Accesses */ +#define sklgt2__render_basic__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Basic Gen9 :: GPU Core Clocks */ +#define sklgt2__compute_basic__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Basic Gen9 :: EU Active */ +#define sklgt2__compute_basic__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Compute Metrics Basic Gen9 :: Untyped Bytes Read */ +#define sklgt2__compute_basic__untyped_bytes_read__read \ + bdw__compute_basic__untyped_bytes_read__read + +/* Compute Metrics Basic Gen9 :: EU Both FPU Pipes Active */ +#define sklgt2__compute_basic__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Compute Metrics Basic Gen9 :: Typed Bytes Written */ +#define sklgt2__compute_basic__typed_bytes_written__read \ + bdw__compute_basic__typed_bytes_written__read + +/* Compute Metrics Basic Gen9 :: EU FPU0 Pipe Active */ +#define sklgt2__compute_basic__fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Compute Metrics Basic Gen9 :: EU FPU1 Pipe Active */ +#define sklgt2__compute_basic__fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Compute Metrics Basic Gen9 :: EU AVG IPC Rate */ +#define sklgt2__compute_basic__eu_avg_ipc_rate__read \ + bdw__compute_basic__eu_avg_ipc_rate__read + +/* Compute Metrics Basic Gen9 :: GS Threads Dispatched */ +#define sklgt2__compute_basic__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Compute Metrics Basic Gen9 :: Early Hi-Depth Test Fails */ +#define sklgt2__compute_basic__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Compute Metrics Basic Gen9 :: VS Threads Dispatched */ +#define sklgt2__compute_basic__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Compute Metrics Basic Gen9 :: FS Threads Dispatched */ +#define sklgt2__compute_basic__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Compute Metrics Basic Gen9 :: Shader Barrier Messages */ +#define sklgt2__compute_basic__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Compute Metrics Basic Gen9 :: Sampler Texels */ +#define sklgt2__compute_basic__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Compute Metrics Basic Gen9 :: Pixels Failing Tests */ +#define sklgt2__compute_basic__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Compute Metrics Basic Gen9 :: GPU Time Elapsed */ +#define sklgt2__compute_basic__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics Basic Gen9 :: AVG GPU Core Frequency */ +#define sklgt2__compute_basic__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics Basic Gen9 :: AVG GPU Core Frequency */ +#define sklgt2__compute_basic__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics Basic Gen9 :: Sampler Texels Misses */ +#define sklgt2__compute_basic__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Compute Metrics Basic Gen9 :: CS Threads Dispatched */ +#define sklgt2__compute_basic__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Compute Metrics Basic Gen9 :: SLM Bytes Read */ +#define sklgt2__compute_basic__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Compute Metrics Basic Gen9 :: GTI Read Throughput */ +#define sklgt2__compute_basic__gti_read_throughput__read \ + hsw__render_basic__gti_l3_throughput__read + +/* Compute Metrics Basic Gen9 :: Untyped Writes */ +#define sklgt2__compute_basic__untyped_bytes_written__read \ + bdw__compute_basic__untyped_bytes_written__read + +/* Compute Metrics Basic Gen9 :: GPU Busy */ +#define sklgt2__compute_basic__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Compute Metrics Basic Gen9 :: Rasterized Pixels */ +#define sklgt2__compute_basic__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Compute Metrics Basic Gen9 :: Typed Bytes Read */ +#define sklgt2__compute_basic__typed_bytes_read__read \ + bdw__compute_basic__typed_bytes_read__read + +/* Compute Metrics Basic Gen9 :: DS Threads Dispatched */ +#define sklgt2__compute_basic__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Compute Metrics Basic Gen9 :: EU Thread Occupancy */ +#define sklgt2__compute_basic__eu_thread_occupancy__read \ + bdw__compute_basic__eu_thread_occupancy__read + +/* Compute Metrics Basic Gen9 :: EU Stall */ +#define sklgt2__compute_basic__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics Basic Gen9 :: Samples Blended */ +#define sklgt2__compute_basic__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Compute Metrics Basic Gen9 :: Early Depth Test Fails */ +#define sklgt2__compute_basic__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Compute Metrics Basic Gen9 :: Shader Memory Accesses */ +#define sklgt2__compute_basic__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Compute Metrics Basic Gen9 :: HS Threads Dispatched */ +#define sklgt2__compute_basic__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Compute Metrics Basic Gen9 :: GTI Write Throughput */ +#define sklgt2__compute_basic__gti_write_throughput__read \ + bdw__render_basic__gti_hdc_lookups_throughput__read + +/* Compute Metrics Basic Gen9 :: SLM Bytes Written */ +#define sklgt2__compute_basic__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Compute Metrics Basic Gen9 :: L3 Shader Throughput */ +#define sklgt2__compute_basic__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Compute Metrics Basic Gen9 :: Samples Killed in FS */ +#define sklgt2__compute_basic__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Compute Metrics Basic Gen9 :: Samples Written */ +#define sklgt2__compute_basic__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Compute Metrics Basic Gen9 :: Shader Atomic Memory Accesses */ +#define sklgt2__compute_basic__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Basic Gen9 :: EU Send Pipe Active */ +#define sklgt2__compute_basic__eu_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Core Clocks */ +#define sklgt2__render_pipe_profile__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: EU Active */ +#define sklgt2__render_pipe_profile__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: VS Bottleneck */ +#define sklgt2__render_pipe_profile__vs_bottleneck__read \ + bdw__render_basic__sampler0_busy__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Hi-Depth Bottleneck */ +#define sklgt2__render_pipe_profile__hi_depth_bottleneck__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GS Bottleneck */ +#define sklgt2__render_pipe_profile__gs_bottleneck__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GS Threads Dispatched */ +#define sklgt2__render_pipe_profile__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Early Hi-Depth Test Fails */ +#define sklgt2__render_pipe_profile__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: VS Threads Dispatched */ +#define sklgt2__render_pipe_profile__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: FS Threads Dispatched */ +#define sklgt2__render_pipe_profile__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: BC Bottleneck */ +#define sklgt2__render_pipe_profile__bc_bottleneck__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: HS Stall */ +#define sklgt2__render_pipe_profile__hs_stall__read \ + bdw__render_pipe_profile__hs_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Barrier Messages */ +#define sklgt2__render_pipe_profile__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Sampler Texels */ +#define sklgt2__render_pipe_profile__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Pixels Failing Tests */ +#define sklgt2__render_pipe_profile__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Time Elapsed */ +#define sklgt2__render_pipe_profile__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: AVG GPU Core Frequency */ +#define sklgt2__render_pipe_profile__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: AVG GPU Core Frequency */ +#define sklgt2__render_pipe_profile__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Sampler Texels Misses */ +#define sklgt2__render_pipe_profile__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: CS Threads Dispatched */ +#define sklgt2__render_pipe_profile__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: VF Bottleneck */ +#define sklgt2__render_pipe_profile__vf_bottleneck__read \ + bdw__render_pipe_profile__vf_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SLM Bytes Read */ +#define sklgt2__render_pipe_profile__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Strip-Fans Bottleneck */ +#define sklgt2__render_pipe_profile__sf_bottleneck__read \ + bdw__render_pipe_profile__sf_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SF Stall */ +#define sklgt2__render_pipe_profile__sf_stall__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Busy */ +#define sklgt2__render_pipe_profile__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: HS Bottleneck */ +#define sklgt2__render_pipe_profile__hs_bottleneck__read \ + bdw__render_basic__sampler1_busy__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: CL Stall */ +#define sklgt2__render_pipe_profile__cl_stall__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SO Bottleneck */ +#define sklgt2__render_pipe_profile__so_bottleneck__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Rasterized Pixels */ +#define sklgt2__render_pipe_profile__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: DS Threads Dispatched */ +#define sklgt2__render_pipe_profile__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Written */ +#define sklgt2__render_pipe_profile__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: DS Bottleneck */ +#define sklgt2__render_pipe_profile__ds_bottleneck__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: EU Stall */ +#define sklgt2__render_pipe_profile__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Clipper Bottleneck */ +#define sklgt2__render_pipe_profile__cl_bottleneck__read \ + bdw__render_pipe_profile__cl_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: DS Stall */ +#define sklgt2__render_pipe_profile__ds_stall__read \ + bdw__render_pipe_profile__ds_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Early Depth Bottleneck */ +#define sklgt2__render_pipe_profile__early_depth_bottleneck__read \ + bdw__render_pipe_profile__early_depth_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Blended */ +#define sklgt2__render_pipe_profile__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Early Depth Test Fails */ +#define sklgt2__render_pipe_profile__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Memory Accesses */ +#define sklgt2__render_pipe_profile__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: HS Threads Dispatched */ +#define sklgt2__render_pipe_profile__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SLM Bytes Written */ +#define sklgt2__render_pipe_profile__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: L3 Shader Throughput */ +#define sklgt2__render_pipe_profile__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Killed in FS */ +#define sklgt2__render_pipe_profile__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SO Stall */ +#define sklgt2__render_pipe_profile__so_stall__read \ + bdw__render_pipe_profile__so_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Atomic Memory Accesses */ +#define sklgt2__render_pipe_profile__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Memory Reads Distribution Gen9 :: GPU Core Clocks */ +#define sklgt2__memory_reads__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Memory Reads Distribution Gen9 :: EU Active */ +#define sklgt2__memory_reads__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Memory Reads Distribution Gen9 :: GtiL3Bank0Reads */ +#define sklgt2__memory_reads__gti_l3_bank0_reads__read \ + hsw__compute_extended__typed_atomics0__read + +/* Memory Reads Distribution Gen9 :: GS Threads Dispatched */ +#define sklgt2__memory_reads__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Memory Reads Distribution Gen9 :: GtiRingAccesses */ +#define sklgt2__memory_reads__gti_ring_accesses__read \ + bdw__memory_reads__gti_ring_accesses__read + +/* Memory Reads Distribution Gen9 :: Early Hi-Depth Test Fails */ +#define sklgt2__memory_reads__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Memory Reads Distribution Gen9 :: VS Threads Dispatched */ +#define sklgt2__memory_reads__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Memory Reads Distribution Gen9 :: FS Threads Dispatched */ +#define sklgt2__memory_reads__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Memory Reads Distribution Gen9 :: GtiL3Bank3Reads */ +#define sklgt2__memory_reads__gti_l3_bank3_reads__read \ + hsw__memory_reads__gpu_core_clocks__read + +/* Memory Reads Distribution Gen9 :: Shader Barrier Messages */ +#define sklgt2__memory_reads__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Memory Reads Distribution Gen9 :: GtiRsMemoryReads */ +#define sklgt2__memory_reads__gti_rs_memory_reads__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Memory Reads Distribution Gen9 :: Sampler Texels */ +#define sklgt2__memory_reads__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Memory Reads Distribution Gen9 :: Pixels Failing Tests */ +#define sklgt2__memory_reads__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Memory Reads Distribution Gen9 :: GtiHizMemoryReads */ +#define sklgt2__memory_reads__gti_hiz_memory_reads__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* Memory Reads Distribution Gen9 :: GPU Time Elapsed */ +#define sklgt2__memory_reads__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Memory Reads Distribution Gen9 :: AVG GPU Core Frequency */ +#define sklgt2__memory_reads__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Memory Reads Distribution Gen9 :: AVG GPU Core Frequency */ +#define sklgt2__memory_reads__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Memory Reads Distribution Gen9 :: Sampler Texels Misses */ +#define sklgt2__memory_reads__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Memory Reads Distribution Gen9 :: GtiRccMemoryReads */ +#define sklgt2__memory_reads__gti_rcc_memory_reads__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* Memory Reads Distribution Gen9 :: CS Threads Dispatched */ +#define sklgt2__memory_reads__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Memory Reads Distribution Gen9 :: SLM Bytes Read */ +#define sklgt2__memory_reads__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Memory Reads Distribution Gen9 :: GtiL3Bank1Reads */ +#define sklgt2__memory_reads__gti_l3_bank1_reads__read \ + hsw__memory_reads__gti_memory_reads__read + +/* Memory Reads Distribution Gen9 :: GPU Busy */ +#define sklgt2__memory_reads__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Memory Reads Distribution Gen9 :: GtiCmdStreamerMemoryReads */ +#define sklgt2__memory_reads__gti_cmd_streamer_memory_reads__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* Memory Reads Distribution Gen9 :: GtiL3Bank2Reads */ +#define sklgt2__memory_reads__gti_l3_bank2_reads__read \ + hsw__memory_reads__llc_read_accesses__read + +/* Memory Reads Distribution Gen9 :: GtiMemoryReads */ +#define sklgt2__memory_reads__gti_memory_reads__read \ + hsw__compute_extended__typed_writes0__read + +/* Memory Reads Distribution Gen9 :: Rasterized Pixels */ +#define sklgt2__memory_reads__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Memory Reads Distribution Gen9 :: GtiRczMemoryReads */ +#define sklgt2__memory_reads__gti_rcz_memory_reads__read \ + hsw__compute_extended__gpu_clocks__read + +/* Memory Reads Distribution Gen9 :: DS Threads Dispatched */ +#define sklgt2__memory_reads__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Memory Reads Distribution Gen9 :: Samples Written */ +#define sklgt2__memory_reads__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Memory Reads Distribution Gen9 :: EU Stall */ +#define sklgt2__memory_reads__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Memory Reads Distribution Gen9 :: Samples Blended */ +#define sklgt2__memory_reads__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Memory Reads Distribution Gen9 :: Early Depth Test Fails */ +#define sklgt2__memory_reads__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Memory Reads Distribution Gen9 :: GtiMscMemoryReads */ +#define sklgt2__memory_reads__gti_msc_memory_reads__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* Memory Reads Distribution Gen9 :: GtiVfMemoryReads */ +#define sklgt2__memory_reads__gti_vf_memory_reads__read \ + hsw__compute_extended__eu_untyped_writes0__read + +/* Memory Reads Distribution Gen9 :: GtiStcMemoryReads */ +#define sklgt2__memory_reads__gti_stc_memory_reads__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* Memory Reads Distribution Gen9 :: Shader Memory Accesses */ +#define sklgt2__memory_reads__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Memory Reads Distribution Gen9 :: HS Threads Dispatched */ +#define sklgt2__memory_reads__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Memory Reads Distribution Gen9 :: Samples Killed in FS */ +#define sklgt2__memory_reads__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Memory Reads Distribution Gen9 :: SLM Bytes Written */ +#define sklgt2__memory_reads__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Memory Reads Distribution Gen9 :: GtiL3Reads */ +#define sklgt2__memory_reads__gti_l3_reads__read \ + bdw__memory_reads__gti_l3_reads__read + +/* Memory Reads Distribution Gen9 :: Shader Atomic Memory Accesses */ +#define sklgt2__memory_reads__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Memory Writes Distribution Gen9 :: GPU Core Clocks */ +#define sklgt2__memory_writes__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Memory Writes Distribution Gen9 :: EU Active */ +#define sklgt2__memory_writes__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Memory Writes Distribution Gen9 :: GtiMemoryWrites */ +#define sklgt2__memory_writes__gti_memory_writes__read \ + hsw__compute_extended__typed_writes0__read + +/* Memory Writes Distribution Gen9 :: GS Threads Dispatched */ +#define sklgt2__memory_writes__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Memory Writes Distribution Gen9 :: GtiRingAccesses */ +#define sklgt2__memory_writes__gti_ring_accesses__read \ + bdw__memory_reads__gti_ring_accesses__read + +/* Memory Writes Distribution Gen9 :: Early Hi-Depth Test Fails */ +#define sklgt2__memory_writes__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Memory Writes Distribution Gen9 :: VS Threads Dispatched */ +#define sklgt2__memory_writes__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Memory Writes Distribution Gen9 :: FS Threads Dispatched */ +#define sklgt2__memory_writes__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Memory Writes Distribution Gen9 :: GtiMscMemoryWrites */ +#define sklgt2__memory_writes__gti_msc_memory_writes__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* Memory Writes Distribution Gen9 :: Shader Barrier Messages */ +#define sklgt2__memory_writes__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Memory Writes Distribution Gen9 :: GtiCmdStreamerMemoryWrites */ +#define sklgt2__memory_writes__gti_cmd_streamer_memory_writes__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* Memory Writes Distribution Gen9 :: Sampler Texels */ +#define sklgt2__memory_writes__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Memory Writes Distribution Gen9 :: Pixels Failing Tests */ +#define sklgt2__memory_writes__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Memory Writes Distribution Gen9 :: GtiL3Bank0Writes */ +#define sklgt2__memory_writes__gti_l3_bank0_writes__read \ + hsw__compute_extended__typed_atomics0__read + +/* Memory Writes Distribution Gen9 :: GtiL3Bank1Writes */ +#define sklgt2__memory_writes__gti_l3_bank1_writes__read \ + hsw__memory_reads__gti_memory_reads__read + +/* Memory Writes Distribution Gen9 :: GtiL3Bank2Writes */ +#define sklgt2__memory_writes__gti_l3_bank2_writes__read \ + hsw__memory_reads__llc_read_accesses__read + +/* Memory Writes Distribution Gen9 :: GtiL3Bank3Writes */ +#define sklgt2__memory_writes__gti_l3_bank3_writes__read \ + hsw__memory_reads__gpu_core_clocks__read + +/* Memory Writes Distribution Gen9 :: GtiL3Writes */ +#define sklgt2__memory_writes__gti_l3_writes__read \ + bdw__memory_reads__gti_l3_reads__read + +/* Memory Writes Distribution Gen9 :: GPU Time Elapsed */ +#define sklgt2__memory_writes__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Memory Writes Distribution Gen9 :: AVG GPU Core Frequency */ +#define sklgt2__memory_writes__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Memory Writes Distribution Gen9 :: AVG GPU Core Frequency */ +#define sklgt2__memory_writes__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Memory Writes Distribution Gen9 :: Sampler Texels Misses */ +#define sklgt2__memory_writes__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Memory Writes Distribution Gen9 :: CS Threads Dispatched */ +#define sklgt2__memory_writes__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Memory Writes Distribution Gen9 :: SLM Bytes Read */ +#define sklgt2__memory_writes__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Memory Writes Distribution Gen9 :: GtiRccMemoryWrites */ +#define sklgt2__memory_writes__gti_rcc_memory_writes__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* Memory Writes Distribution Gen9 :: GtiSoMemoryWrites */ +#define sklgt2__memory_writes__gti_so_memory_writes__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Memory Writes Distribution Gen9 :: GPU Busy */ +#define sklgt2__memory_writes__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Memory Writes Distribution Gen9 :: GtiStcMemoryWrites */ +#define sklgt2__memory_writes__gti_stc_memory_writes__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* Memory Writes Distribution Gen9 :: Rasterized Pixels */ +#define sklgt2__memory_writes__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Memory Writes Distribution Gen9 :: DS Threads Dispatched */ +#define sklgt2__memory_writes__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Memory Writes Distribution Gen9 :: Samples Written */ +#define sklgt2__memory_writes__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Memory Writes Distribution Gen9 :: EU Stall */ +#define sklgt2__memory_writes__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Memory Writes Distribution Gen9 :: Samples Blended */ +#define sklgt2__memory_writes__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Memory Writes Distribution Gen9 :: Early Depth Test Fails */ +#define sklgt2__memory_writes__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Memory Writes Distribution Gen9 :: Shader Memory Accesses */ +#define sklgt2__memory_writes__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Memory Writes Distribution Gen9 :: HS Threads Dispatched */ +#define sklgt2__memory_writes__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Memory Writes Distribution Gen9 :: GtiRczMemoryWrites */ +#define sklgt2__memory_writes__gti_rcz_memory_writes__read \ + hsw__compute_extended__gpu_clocks__read + +/* Memory Writes Distribution Gen9 :: SLM Bytes Written */ +#define sklgt2__memory_writes__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Memory Writes Distribution Gen9 :: L3 Shader Throughput */ +#define sklgt2__memory_writes__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Memory Writes Distribution Gen9 :: Samples Killed in FS */ +#define sklgt2__memory_writes__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Memory Writes Distribution Gen9 :: GtiHizMemoryWrites */ +#define sklgt2__memory_writes__gti_hiz_memory_writes__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* Memory Writes Distribution Gen9 :: Shader Atomic Memory Accesses */ +#define sklgt2__memory_writes__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Extended Gen9 :: GPU Core Clocks */ +#define sklgt2__compute_extended__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Extended Gen9 :: EU Active */ +#define sklgt2__compute_extended__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Compute Metrics Extended Gen9 :: EU Both FPU Pipes Active */ +#define sklgt2__compute_extended__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Compute Metrics Extended Gen9 :: EU FPU0 Pipe Active */ +#define sklgt2__compute_extended__fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Compute Metrics Extended Gen9 :: EU FPU1 Pipe Active */ +#define sklgt2__compute_extended__fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Compute Metrics Extended Gen9 :: EU AVG IPC Rate */ +#define sklgt2__compute_extended__eu_avg_ipc_rate__read \ + bdw__compute_basic__eu_avg_ipc_rate__read + +/* Compute Metrics Extended Gen9 :: Typed Writes 0 */ +#define sklgt2__compute_extended__typed_writes0__read \ + hsw__compute_extended__typed_writes0__read + +/* Compute Metrics Extended Gen9 :: EuTypedAtomics0 */ +#define sklgt2__compute_extended__eu_typed_atomics0__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* Compute Metrics Extended Gen9 :: Typed Atomics 0 */ +#define sklgt2__compute_extended__typed_atomics0__read \ + hsw__compute_extended__typed_atomics0__read + +/* Compute Metrics Extended Gen9 :: TypedAtomicsPerCacheLine */ +#define sklgt2__compute_extended__typed_atomics_per_cache_line__read \ + hsw__compute_extended__typed_atomics_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: EuUntypedReads0 */ +#define sklgt2__compute_extended__eu_untyped_reads0__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* Compute Metrics Extended Gen9 :: Untyped Writes 0 */ +#define sklgt2__compute_extended__untyped_writes0__read \ + hsw__compute_extended__untyped_writes0__read + +/* Compute Metrics Extended Gen9 :: EuUntypedAtomics0 */ +#define sklgt2__compute_extended__eu_untyped_atomics0__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* Compute Metrics Extended Gen9 :: EuUntypedWrites0 */ +#define sklgt2__compute_extended__eu_untyped_writes0__read \ + hsw__compute_extended__eu_untyped_writes0__read + +/* Compute Metrics Extended Gen9 :: EuA64UntypedWrites0 */ +#define sklgt2__compute_extended__eu_a64_untyped_writes0__read \ + hsw__compute_extended__gpu_clocks__read + +/* Compute Metrics Extended Gen9 :: UntypedWritesPerCacheLine */ +#define sklgt2__compute_extended__untyped_writes_per_cache_line__read \ + bdw__compute_extended__untyped_writes_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: Shader Barrier Messages */ +#define sklgt2__compute_extended__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Compute Metrics Extended Gen9 :: Sampler Texels */ +#define sklgt2__compute_extended__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Compute Metrics Extended Gen9 :: GPU Time Elapsed */ +#define sklgt2__compute_extended__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics Extended Gen9 :: AVG GPU Core Frequency */ +#define sklgt2__compute_extended__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics Extended Gen9 :: AVG GPU Core Frequency */ +#define sklgt2__compute_extended__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics Extended Gen9 :: Sampler Texels Misses */ +#define sklgt2__compute_extended__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Compute Metrics Extended Gen9 :: CS Threads Dispatched */ +#define sklgt2__compute_extended__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Compute Metrics Extended Gen9 :: SLM Bytes Read */ +#define sklgt2__compute_extended__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Compute Metrics Extended Gen9 :: EuTypedWrites0 */ +#define sklgt2__compute_extended__eu_typed_writes0__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* Compute Metrics Extended Gen9 :: TypedWritesPerCacheLine */ +#define sklgt2__compute_extended__typed_writes_per_cache_line__read \ + hsw__compute_extended__typed_writes_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: Typed Reads 0 */ +#define sklgt2__compute_extended__typed_reads0__read \ + hsw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Extended Gen9 :: Untyped Reads 0 */ +#define sklgt2__compute_extended__untyped_reads0__read \ + hsw__compute_extended__untyped_reads0__read + +/* Compute Metrics Extended Gen9 :: EuA64UntypedReads0 */ +#define sklgt2__compute_extended__eu_a64_untyped_reads0__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* Compute Metrics Extended Gen9 :: EU Thread Occupancy */ +#define sklgt2__compute_extended__eu_thread_occupancy__read \ + bdw__compute_basic__eu_thread_occupancy__read + +/* Compute Metrics Extended Gen9 :: EU Stall */ +#define sklgt2__compute_extended__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics Extended Gen9 :: EuTypedReads0 */ +#define sklgt2__compute_extended__eu_typed_reads0__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Compute Metrics Extended Gen9 :: UntypedReadsPerCacheLine */ +#define sklgt2__compute_extended__untyped_reads_per_cache_line__read \ + bdw__compute_extended__untyped_reads_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: Shader Memory Accesses */ +#define sklgt2__compute_extended__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Compute Metrics Extended Gen9 :: TypedReadsPerCacheLine */ +#define sklgt2__compute_extended__typed_reads_per_cache_line__read \ + hsw__compute_extended__typed_reads_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: SLM Bytes Written */ +#define sklgt2__compute_extended__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Compute Metrics Extended Gen9 :: L3 Shader Throughput */ +#define sklgt2__compute_extended__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Compute Metrics Extended Gen9 :: Shader Atomic Memory Accesses */ +#define sklgt2__compute_extended__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Extended Gen9 :: EU Send Pipe Active */ +#define sklgt2__compute_extended__eu_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Compute Metrics L3 Cache Gen9 :: GPU Core Clocks */ +#define sklgt2__compute_l3_cache__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics L3 Cache Gen9 :: EU Active */ +#define sklgt2__compute_l3_cache__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 03 Accesses */ +#define sklgt2__compute_l3_cache__l3_bank03_accesses__read \ + bdw__compute_l3_cache__l3_bank03_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Accesses */ +static uint64_t +sklgt2__compute_l3_cache__l3_accesses__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 0 READ C 1 READ B 2 READ B 3 READ UADD UADD UADD 2 UMUL */ + uint64_t tmp0 = accumulator[query->c_offset + 0]; + uint64_t tmp1 = accumulator[query->c_offset + 1]; + uint64_t tmp2 = accumulator[query->b_offset + 2]; + uint64_t tmp3 = accumulator[query->b_offset + 3]; + uint64_t tmp4 = tmp2 + tmp3; + uint64_t tmp5 = tmp1 + tmp4; + uint64_t tmp6 = tmp0 + tmp5; + uint64_t tmp7 = tmp6 * 2; + + return tmp7; +} + +/* Compute Metrics L3 Cache Gen9 :: EU Both FPU Pipes Active */ +#define sklgt2__compute_l3_cache__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Sampler Throughput */ +#define sklgt2__compute_l3_cache__l3_sampler_throughput__read \ + chv__render_basic__l3_sampler_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Pipe Active */ +#define sklgt2__compute_l3_cache__fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Pipe Active */ +#define sklgt2__compute_l3_cache__fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Compute Metrics L3 Cache Gen9 :: EU AVG IPC Rate */ +#define sklgt2__compute_l3_cache__eu_avg_ipc_rate__read \ + bdw__compute_basic__eu_avg_ipc_rate__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Binary Instruction */ +#define sklgt2__compute_l3_cache__eu_binary_fpu0_instruction__read \ + bdw__render_basic__ps_send_active__read + +/* Compute Metrics L3 Cache Gen9 :: GS Threads Dispatched */ +#define sklgt2__compute_l3_cache__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Compute Metrics L3 Cache Gen9 :: Shader Memory Accesses */ +#define sklgt2__compute_l3_cache__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: Early Hi-Depth Test Fails */ +#define sklgt2__compute_l3_cache__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Compute Metrics L3 Cache Gen9 :: VS Threads Dispatched */ +#define sklgt2__compute_l3_cache__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Compute Metrics L3 Cache Gen9 :: FS Threads Dispatched */ +#define sklgt2__compute_l3_cache__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Hybrid Instruction */ +#define sklgt2__compute_l3_cache__eu_hybrid_fpu0_instruction__read \ + bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Misses */ +#define sklgt2__compute_l3_cache__l3_misses__read \ + bdw__compute_l3_cache__l3_misses__read + +/* Compute Metrics L3 Cache Gen9 :: Shader Barrier Messages */ +#define sklgt2__compute_l3_cache__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 Accesses */ +#define sklgt2__compute_l3_cache__l3_bank00_accesses__read \ + bdw__compute_l3_cache__l3_bank00_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Move Instruction */ +#define sklgt2__compute_l3_cache__eu_move_fpu0_instruction__read \ + bdw__compute_l3_cache__eu_move_fpu0_instruction__read + +/* Compute Metrics L3 Cache Gen9 :: Sampler Texels */ +#define sklgt2__compute_l3_cache__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Compute Metrics L3 Cache Gen9 :: Pixels Failing Tests */ +#define sklgt2__compute_l3_cache__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Hybrid Instruction */ +#define sklgt2__compute_l3_cache__eu_hybrid_fpu1_instruction__read \ + bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read + +/* Compute Metrics L3 Cache Gen9 :: GPU Time Elapsed */ +#define sklgt2__compute_l3_cache__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics L3 Cache Gen9 :: AVG GPU Core Frequency */ +#define sklgt2__compute_l3_cache__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics L3 Cache Gen9 :: AVG GPU Core Frequency */ +#define sklgt2__compute_l3_cache__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics L3 Cache Gen9 :: Sampler Texels Misses */ +#define sklgt2__compute_l3_cache__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Compute Metrics L3 Cache Gen9 :: CS Threads Dispatched */ +#define sklgt2__compute_l3_cache__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Compute Metrics L3 Cache Gen9 :: SLM Bytes Read */ +#define sklgt2__compute_l3_cache__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Compute Metrics L3 Cache Gen9 :: GTI Read Throughput */ +#define sklgt2__compute_l3_cache__gti_read_throughput__read \ + bdw__render_basic__gti_read_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: GTI L3 Throughput */ +#define sklgt2__compute_l3_cache__gti_l3_throughput__read \ + bdw__compute_l3_cache__gti_l3_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 IC Accesses */ +#define sklgt2__compute_l3_cache__l3_bank00_ic_accesses__read \ + bdw__compute_l3_cache__l3_bank00_ic_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 IC Hits */ +#define sklgt2__compute_l3_cache__l3_bank00_ic_hits__read \ + bdw__compute_l3_cache__l3_bank00_ic_hits__read + +/* Compute Metrics L3 Cache Gen9 :: Sampler Accesses */ +#define sklgt2__compute_l3_cache__sampler_accesses__read \ + bdw__render_pipe_profile__sampler_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 01 Accesses */ +#define sklgt2__compute_l3_cache__l3_bank01_accesses__read \ + bdw__compute_l3_cache__l3_bank01_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: GPU Busy */ +#define sklgt2__compute_l3_cache__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Ternary Instruction */ +#define sklgt2__compute_l3_cache__eu_ternary_fpu0_instruction__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Compute Metrics L3 Cache Gen9 :: Shader Atomic Memory Accesses */ +#define sklgt2__compute_l3_cache__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics L3 Cache Gen9 :: Rasterized Pixels */ +#define sklgt2__compute_l3_cache__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Compute Metrics L3 Cache Gen9 :: DS Threads Dispatched */ +#define sklgt2__compute_l3_cache__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Compute Metrics L3 Cache Gen9 :: Samples Written */ +#define sklgt2__compute_l3_cache__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Move Instruction */ +#define sklgt2__compute_l3_cache__eu_move_fpu1_instruction__read \ + bdw__compute_l3_cache__eu_move_fpu1_instruction__read + +/* Compute Metrics L3 Cache Gen9 :: EU Stall */ +#define sklgt2__compute_l3_cache__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics L3 Cache Gen9 :: Samples Blended */ +#define sklgt2__compute_l3_cache__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Compute Metrics L3 Cache Gen9 :: Early Depth Test Fails */ +#define sklgt2__compute_l3_cache__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 02 Accesses */ +#define sklgt2__compute_l3_cache__l3_bank02_accesses__read \ + bdw__compute_l3_cache__l3_bank02_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: HS Threads Dispatched */ +#define sklgt2__compute_l3_cache__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Total Throughput */ +static uint64_t +sklgt2__compute_l3_cache__l3_total_throughput__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $L3Accesses 64 UMUL */ + uint64_t tmp0 = sklgt2__compute_l3_cache__l3_accesses__read(brw, query, accumulator) * 64; + + return tmp0; +} + +/* Compute Metrics L3 Cache Gen9 :: GTI Write Throughput */ +#define sklgt2__compute_l3_cache__gti_write_throughput__read \ + hsw__render_basic__gti_write_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: SLM Bytes Written */ +#define sklgt2__compute_l3_cache__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Shader Throughput */ +#define sklgt2__compute_l3_cache__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: Samples Killed in FS */ +#define sklgt2__compute_l3_cache__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Binary Instruction */ +#define sklgt2__compute_l3_cache__eu_binary_fpu1_instruction__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Ternary Instruction */ +#define sklgt2__compute_l3_cache__eu_ternary_fpu1_instruction__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Compute Metrics L3 Cache Gen9 :: EU Send Pipe Active */ +#define sklgt2__compute_l3_cache__eu_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set HDCAndSF :: GPU Core Clocks */ +#define sklgt2__hdc_and_sf__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set HDCAndSF :: EU Active */ +#define sklgt2__hdc_and_sf__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set HDCAndSF :: EU Both FPU Pipes Active */ +#define sklgt2__hdc_and_sf__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set HDCAndSF :: VS Send Pipe Active */ +#define sklgt2__hdc_and_sf__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set HDCAndSF :: VS FPU1 Pipe Active */ +#define sklgt2__hdc_and_sf__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set HDCAndSF :: GS Threads Dispatched */ +#define sklgt2__hdc_and_sf__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set HDCAndSF :: Early Hi-Depth Test Fails */ +#define sklgt2__hdc_and_sf__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set HDCAndSF :: FS Both FPU Active */ +#define sklgt2__hdc_and_sf__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set HDCAndSF :: VS Threads Dispatched */ +#define sklgt2__hdc_and_sf__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set HDCAndSF :: Polygon Data Ready */ +#define sklgt2__hdc_and_sf__poly_data_ready__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set HDCAndSF :: FS Threads Dispatched */ +#define sklgt2__hdc_and_sf__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set HDCAndSF :: Shader Barrier Messages */ +#define sklgt2__hdc_and_sf__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set HDCAndSF :: Sampler Texels */ +#define sklgt2__hdc_and_sf__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set HDCAndSF :: Pixels Failing Tests */ +#define sklgt2__hdc_and_sf__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set HDCAndSF :: GPU Time Elapsed */ +#define sklgt2__hdc_and_sf__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set HDCAndSF :: AVG GPU Core Frequency */ +#define sklgt2__hdc_and_sf__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set HDCAndSF :: AVG GPU Core Frequency */ +#define sklgt2__hdc_and_sf__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set HDCAndSF :: Sampler Texels Misses */ +#define sklgt2__hdc_and_sf__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */ +#define sklgt2__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read \ + bdw__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read + +/* Metric set HDCAndSF :: CS Threads Dispatched */ +#define sklgt2__hdc_and_sf__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss2) */ +#define sklgt2__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read \ + bdw__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read + +/* Metric set HDCAndSF :: SLM Bytes Read */ +#define sklgt2__hdc_and_sf__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set HDCAndSF :: PS FPU1 Pipe Active */ +#define sklgt2__hdc_and_sf__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set HDCAndSF :: PS Send Pipeline Active */ +#define sklgt2__hdc_and_sf__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set HDCAndSF :: VS FPU0 Pipe Active */ +#define sklgt2__hdc_and_sf__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set HDCAndSF :: GPU Busy */ +#define sklgt2__hdc_and_sf__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set HDCAndSF :: Rasterized Pixels */ +#define sklgt2__hdc_and_sf__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set HDCAndSF :: PS FPU0 Pipe Active */ +#define sklgt2__hdc_and_sf__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set HDCAndSF :: DS Threads Dispatched */ +#define sklgt2__hdc_and_sf__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set HDCAndSF :: Samples Written */ +#define sklgt2__hdc_and_sf__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set HDCAndSF :: EU Stall */ +#define sklgt2__hdc_and_sf__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set HDCAndSF :: Samples Blended */ +#define sklgt2__hdc_and_sf__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set HDCAndSF :: Early Depth Test Fails */ +#define sklgt2__hdc_and_sf__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set HDCAndSF :: Shader Memory Accesses */ +#define sklgt2__hdc_and_sf__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set HDCAndSF :: HS Threads Dispatched */ +#define sklgt2__hdc_and_sf__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set HDCAndSF :: SLM Bytes Written */ +#define sklgt2__hdc_and_sf__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set HDCAndSF :: L3 Shader Throughput */ +#define sklgt2__hdc_and_sf__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set HDCAndSF :: Samples Killed in FS */ +#define sklgt2__hdc_and_sf__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */ +#define sklgt2__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read \ + bdw__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read + +/* Metric set HDCAndSF :: Shader Atomic Memory Accesses */ +#define sklgt2__hdc_and_sf__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set L3_1 :: GPU Core Clocks */ +#define sklgt2__l3_1__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set L3_1 :: EU Active */ +#define sklgt2__l3_1__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set L3_1 :: Slice0 L3 Bank1 Active */ +#define sklgt2__l3_1__l30_bank1_active__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set L3_1 :: EU Both FPU Pipes Active */ +#define sklgt2__l3_1__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set L3_1 :: VS Send Pipe Active */ +#define sklgt2__l3_1__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set L3_1 :: VS FPU1 Pipe Active */ +#define sklgt2__l3_1__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set L3_1 :: GS Threads Dispatched */ +#define sklgt2__l3_1__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set L3_1 :: Early Hi-Depth Test Fails */ +#define sklgt2__l3_1__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set L3_1 :: FS Both FPU Active */ +#define sklgt2__l3_1__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set L3_1 :: VS Threads Dispatched */ +#define sklgt2__l3_1__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set L3_1 :: Slice0 L3 Bank1 Stalled */ +#define sklgt2__l3_1__l30_bank1_stalled__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Metric set L3_1 :: FS Threads Dispatched */ +#define sklgt2__l3_1__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set L3_1 :: Shader Barrier Messages */ +#define sklgt2__l3_1__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set L3_1 :: Sampler Texels */ +#define sklgt2__l3_1__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set L3_1 :: Pixels Failing Tests */ +#define sklgt2__l3_1__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set L3_1 :: GPU Time Elapsed */ +#define sklgt2__l3_1__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set L3_1 :: AVG GPU Core Frequency */ +#define sklgt2__l3_1__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set L3_1 :: AVG GPU Core Frequency */ +#define sklgt2__l3_1__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set L3_1 :: Sampler Texels Misses */ +#define sklgt2__l3_1__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set L3_1 :: CS Threads Dispatched */ +#define sklgt2__l3_1__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set L3_1 :: SLM Bytes Read */ +#define sklgt2__l3_1__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set L3_1 :: PS FPU1 Pipe Active */ +#define sklgt2__l3_1__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set L3_1 :: PS Send Pipeline Active */ +#define sklgt2__l3_1__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set L3_1 :: VS FPU0 Pipe Active */ +#define sklgt2__l3_1__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set L3_1 :: GPU Busy */ +#define sklgt2__l3_1__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set L3_1 :: Slice0 L3 Bank0 Active */ +#define sklgt2__l3_1__l30_bank0_active__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set L3_1 :: Rasterized Pixels */ +#define sklgt2__l3_1__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set L3_1 :: PS FPU0 Pipe Active */ +#define sklgt2__l3_1__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set L3_1 :: Slice0 L3 Bank0 Stalled */ +#define sklgt2__l3_1__l30_bank0_stalled__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set L3_1 :: DS Threads Dispatched */ +#define sklgt2__l3_1__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set L3_1 :: Samples Written */ +#define sklgt2__l3_1__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set L3_1 :: EU Stall */ +#define sklgt2__l3_1__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set L3_1 :: Samples Blended */ +#define sklgt2__l3_1__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set L3_1 :: Early Depth Test Fails */ +#define sklgt2__l3_1__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set L3_1 :: Shader Memory Accesses */ +#define sklgt2__l3_1__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set L3_1 :: HS Threads Dispatched */ +#define sklgt2__l3_1__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set L3_1 :: SLM Bytes Written */ +#define sklgt2__l3_1__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set L3_1 :: L3 Shader Throughput */ +#define sklgt2__l3_1__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set L3_1 :: Samples Killed in FS */ +#define sklgt2__l3_1__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set L3_1 :: Shader Atomic Memory Accesses */ +#define sklgt2__l3_1__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set L3_2 :: GPU Core Clocks */ +#define sklgt2__l3_2__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set L3_2 :: EU Active */ +#define sklgt2__l3_2__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set L3_2 :: EU Both FPU Pipes Active */ +#define sklgt2__l3_2__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set L3_2 :: VS Send Pipe Active */ +#define sklgt2__l3_2__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set L3_2 :: VS FPU1 Pipe Active */ +#define sklgt2__l3_2__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set L3_2 :: GS Threads Dispatched */ +#define sklgt2__l3_2__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set L3_2 :: Early Hi-Depth Test Fails */ +#define sklgt2__l3_2__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set L3_2 :: FS Both FPU Active */ +#define sklgt2__l3_2__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set L3_2 :: VS Threads Dispatched */ +#define sklgt2__l3_2__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set L3_2 :: FS Threads Dispatched */ +#define sklgt2__l3_2__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set L3_2 :: Shader Barrier Messages */ +#define sklgt2__l3_2__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set L3_2 :: Sampler Texels */ +#define sklgt2__l3_2__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set L3_2 :: Pixels Failing Tests */ +#define sklgt2__l3_2__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set L3_2 :: GPU Time Elapsed */ +#define sklgt2__l3_2__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set L3_2 :: AVG GPU Core Frequency */ +#define sklgt2__l3_2__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set L3_2 :: AVG GPU Core Frequency */ +#define sklgt2__l3_2__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set L3_2 :: Sampler Texels Misses */ +#define sklgt2__l3_2__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set L3_2 :: CS Threads Dispatched */ +#define sklgt2__l3_2__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set L3_2 :: SLM Bytes Read */ +#define sklgt2__l3_2__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set L3_2 :: PS FPU1 Pipe Active */ +#define sklgt2__l3_2__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set L3_2 :: Slice0 L3 Bank2 Stalled */ +#define sklgt2__l3_2__l30_bank2_stalled__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set L3_2 :: PS Send Pipeline Active */ +#define sklgt2__l3_2__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set L3_2 :: VS FPU0 Pipe Active */ +#define sklgt2__l3_2__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set L3_2 :: GPU Busy */ +#define sklgt2__l3_2__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set L3_2 :: Slice0 L3 Bank2 Active */ +#define sklgt2__l3_2__l30_bank2_active__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set L3_2 :: Rasterized Pixels */ +#define sklgt2__l3_2__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set L3_2 :: PS FPU0 Pipe Active */ +#define sklgt2__l3_2__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set L3_2 :: DS Threads Dispatched */ +#define sklgt2__l3_2__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set L3_2 :: Samples Written */ +#define sklgt2__l3_2__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set L3_2 :: EU Stall */ +#define sklgt2__l3_2__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set L3_2 :: Samples Blended */ +#define sklgt2__l3_2__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set L3_2 :: Early Depth Test Fails */ +#define sklgt2__l3_2__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set L3_2 :: Shader Memory Accesses */ +#define sklgt2__l3_2__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set L3_2 :: HS Threads Dispatched */ +#define sklgt2__l3_2__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set L3_2 :: SLM Bytes Written */ +#define sklgt2__l3_2__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set L3_2 :: L3 Shader Throughput */ +#define sklgt2__l3_2__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set L3_2 :: Samples Killed in FS */ +#define sklgt2__l3_2__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set L3_2 :: Shader Atomic Memory Accesses */ +#define sklgt2__l3_2__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set L3_3 :: GPU Core Clocks */ +#define sklgt2__l3_3__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set L3_3 :: EU Active */ +#define sklgt2__l3_3__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set L3_3 :: EU Both FPU Pipes Active */ +#define sklgt2__l3_3__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set L3_3 :: VS Send Pipe Active */ +#define sklgt2__l3_3__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set L3_3 :: VS FPU1 Pipe Active */ +#define sklgt2__l3_3__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set L3_3 :: GS Threads Dispatched */ +#define sklgt2__l3_3__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set L3_3 :: Early Hi-Depth Test Fails */ +#define sklgt2__l3_3__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set L3_3 :: FS Both FPU Active */ +#define sklgt2__l3_3__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set L3_3 :: VS Threads Dispatched */ +#define sklgt2__l3_3__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set L3_3 :: FS Threads Dispatched */ +#define sklgt2__l3_3__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set L3_3 :: Slice0 L3 Bank3 Stalled */ +#define sklgt2__l3_3__l30_bank3_stalled__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set L3_3 :: Shader Barrier Messages */ +#define sklgt2__l3_3__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set L3_3 :: Sampler Texels */ +#define sklgt2__l3_3__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set L3_3 :: Pixels Failing Tests */ +#define sklgt2__l3_3__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set L3_3 :: GPU Time Elapsed */ +#define sklgt2__l3_3__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set L3_3 :: AVG GPU Core Frequency */ +#define sklgt2__l3_3__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set L3_3 :: AVG GPU Core Frequency */ +#define sklgt2__l3_3__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set L3_3 :: Sampler Texels Misses */ +#define sklgt2__l3_3__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set L3_3 :: CS Threads Dispatched */ +#define sklgt2__l3_3__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set L3_3 :: SLM Bytes Read */ +#define sklgt2__l3_3__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set L3_3 :: PS FPU1 Pipe Active */ +#define sklgt2__l3_3__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set L3_3 :: Slice0 L3 Bank3 Active */ +#define sklgt2__l3_3__l30_bank3_active__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set L3_3 :: PS Send Pipeline Active */ +#define sklgt2__l3_3__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set L3_3 :: VS FPU0 Pipe Active */ +#define sklgt2__l3_3__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set L3_3 :: GPU Busy */ +#define sklgt2__l3_3__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set L3_3 :: Rasterized Pixels */ +#define sklgt2__l3_3__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set L3_3 :: PS FPU0 Pipe Active */ +#define sklgt2__l3_3__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set L3_3 :: DS Threads Dispatched */ +#define sklgt2__l3_3__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set L3_3 :: Samples Written */ +#define sklgt2__l3_3__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set L3_3 :: EU Stall */ +#define sklgt2__l3_3__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set L3_3 :: Samples Blended */ +#define sklgt2__l3_3__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set L3_3 :: Early Depth Test Fails */ +#define sklgt2__l3_3__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set L3_3 :: Shader Memory Accesses */ +#define sklgt2__l3_3__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set L3_3 :: HS Threads Dispatched */ +#define sklgt2__l3_3__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set L3_3 :: SLM Bytes Written */ +#define sklgt2__l3_3__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set L3_3 :: L3 Shader Throughput */ +#define sklgt2__l3_3__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set L3_3 :: Samples Killed in FS */ +#define sklgt2__l3_3__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set L3_3 :: Shader Atomic Memory Accesses */ +#define sklgt2__l3_3__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */ +#define sklgt2__rasterizer_and_pixel_backend__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set RasterizerAndPixelBackend :: EU Active */ +#define sklgt2__rasterizer_and_pixel_backend__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set RasterizerAndPixelBackend :: EU Both FPU Pipes Active */ +#define sklgt2__rasterizer_and_pixel_backend__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set RasterizerAndPixelBackend :: VS Send Pipe Active */ +#define sklgt2__rasterizer_and_pixel_backend__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set RasterizerAndPixelBackend :: VS FPU1 Pipe Active */ +#define sklgt2__rasterizer_and_pixel_backend__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */ +#define sklgt2__rasterizer_and_pixel_backend__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */ +#define sklgt2__rasterizer_and_pixel_backend__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set RasterizerAndPixelBackend :: FS Both FPU Active */ +#define sklgt2__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */ +#define sklgt2__rasterizer_and_pixel_backend__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */ +#define sklgt2__rasterizer_and_pixel_backend__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Pixel Values Ready */ +#define sklgt2__rasterizer_and_pixel_backend__pixel_values0_ready__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */ +#define sklgt2__rasterizer_and_pixel_backend__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set RasterizerAndPixelBackend :: Sampler Texels */ +#define sklgt2__rasterizer_and_pixel_backend__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */ +#define sklgt2__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */ +#define sklgt2__rasterizer_and_pixel_backend__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ +#define sklgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ +#define sklgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */ +#define sklgt2__rasterizer_and_pixel_backend__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */ +#define sklgt2__rasterizer_and_pixel_backend__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */ +#define sklgt2__rasterizer_and_pixel_backend__rasterizer0_input_available__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Post-EarlyZ Pixel Data Ready */ +#define sklgt2__rasterizer_and_pixel_backend__pixel_data0_ready__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */ +#define sklgt2__rasterizer_and_pixel_backend__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set RasterizerAndPixelBackend :: PS FPU1 Pipe Active */ +#define sklgt2__rasterizer_and_pixel_backend__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set RasterizerAndPixelBackend :: PS Send Pipeline Active */ +#define sklgt2__rasterizer_and_pixel_backend__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set RasterizerAndPixelBackend :: VS FPU0 Pipe Active */ +#define sklgt2__rasterizer_and_pixel_backend__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set RasterizerAndPixelBackend :: GPU Busy */ +#define sklgt2__rasterizer_and_pixel_backend__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */ +#define sklgt2__rasterizer_and_pixel_backend__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set RasterizerAndPixelBackend :: PS FPU0 Pipe Active */ +#define sklgt2__rasterizer_and_pixel_backend__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */ +#define sklgt2__rasterizer_and_pixel_backend__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set RasterizerAndPixelBackend :: Samples Written */ +#define sklgt2__rasterizer_and_pixel_backend__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set RasterizerAndPixelBackend :: EU Stall */ +#define sklgt2__rasterizer_and_pixel_backend__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */ +#define sklgt2__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set RasterizerAndPixelBackend :: Samples Blended */ +#define sklgt2__rasterizer_and_pixel_backend__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */ +#define sklgt2__rasterizer_and_pixel_backend__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */ +#define sklgt2__rasterizer_and_pixel_backend__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */ +#define sklgt2__rasterizer_and_pixel_backend__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */ +#define sklgt2__rasterizer_and_pixel_backend__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */ +#define sklgt2__rasterizer_and_pixel_backend__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */ +#define sklgt2__rasterizer_and_pixel_backend__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 PS Output Available */ +#define sklgt2__rasterizer_and_pixel_backend__ps_output0_available__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */ +#define sklgt2__rasterizer_and_pixel_backend__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set Sampler :: GPU Core Clocks */ +#define sklgt2__sampler__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set Sampler :: EU Active */ +#define sklgt2__sampler__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set Sampler :: Slice0 Subslice2 Input Available */ +#define sklgt2__sampler__sampler02_input_available__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set Sampler :: EU Both FPU Pipes Active */ +#define sklgt2__sampler__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set Sampler :: VS Send Pipe Active */ +#define sklgt2__sampler__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set Sampler :: Slice0 Subslice0 Input Available */ +#define sklgt2__sampler__sampler00_input_available__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Metric set Sampler :: VS FPU1 Pipe Active */ +#define sklgt2__sampler__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set Sampler :: GS Threads Dispatched */ +#define sklgt2__sampler__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set Sampler :: Early Hi-Depth Test Fails */ +#define sklgt2__sampler__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set Sampler :: FS Both FPU Active */ +#define sklgt2__sampler__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set Sampler :: VS Threads Dispatched */ +#define sklgt2__sampler__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set Sampler :: Slice0 Subslice2 Sampler Output Ready */ +#define sklgt2__sampler__sampler02_output_ready__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set Sampler :: FS Threads Dispatched */ +#define sklgt2__sampler__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set Sampler :: Shader Barrier Messages */ +#define sklgt2__sampler__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set Sampler :: Slice0 Subslice1 Input Available */ +#define sklgt2__sampler__sampler01_input_available__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set Sampler :: Sampler Texels */ +#define sklgt2__sampler__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set Sampler :: Pixels Failing Tests */ +#define sklgt2__sampler__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set Sampler :: GPU Time Elapsed */ +#define sklgt2__sampler__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set Sampler :: AVG GPU Core Frequency */ +#define sklgt2__sampler__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set Sampler :: AVG GPU Core Frequency */ +#define sklgt2__sampler__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set Sampler :: Sampler Texels Misses */ +#define sklgt2__sampler__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set Sampler :: CS Threads Dispatched */ +#define sklgt2__sampler__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set Sampler :: SLM Bytes Read */ +#define sklgt2__sampler__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set Sampler :: PS FPU1 Pipe Active */ +#define sklgt2__sampler__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set Sampler :: PS Send Pipeline Active */ +#define sklgt2__sampler__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set Sampler :: VS FPU0 Pipe Active */ +#define sklgt2__sampler__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set Sampler :: GPU Busy */ +#define sklgt2__sampler__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set Sampler :: Rasterized Pixels */ +#define sklgt2__sampler__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set Sampler :: PS FPU0 Pipe Active */ +#define sklgt2__sampler__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set Sampler :: DS Threads Dispatched */ +#define sklgt2__sampler__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set Sampler :: Samples Written */ +#define sklgt2__sampler__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set Sampler :: EU Stall */ +#define sklgt2__sampler__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set Sampler :: Samples Blended */ +#define sklgt2__sampler__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set Sampler :: Early Depth Test Fails */ +#define sklgt2__sampler__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set Sampler :: Slice0 Subslice0 Sampler Output Ready */ +#define sklgt2__sampler__sampler00_output_ready__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set Sampler :: Slice0 Subslice1 Sampler Output Ready */ +#define sklgt2__sampler__sampler01_output_ready__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set Sampler :: Shader Memory Accesses */ +#define sklgt2__sampler__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set Sampler :: HS Threads Dispatched */ +#define sklgt2__sampler__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set Sampler :: SLM Bytes Written */ +#define sklgt2__sampler__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set Sampler :: L3 Shader Throughput */ +#define sklgt2__sampler__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set Sampler :: Samples Killed in FS */ +#define sklgt2__sampler__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set Sampler :: Shader Atomic Memory Accesses */ +#define sklgt2__sampler__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set TDL_1 :: GPU Core Clocks */ +#define sklgt2__tdl_1__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set TDL_1 :: EU Active */ +#define sklgt2__tdl_1__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set TDL_1 :: EU Both FPU Pipes Active */ +#define sklgt2__tdl_1__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set TDL_1 :: VS Send Pipe Active */ +#define sklgt2__tdl_1__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set TDL_1 :: VS FPU1 Pipe Active */ +#define sklgt2__tdl_1__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set TDL_1 :: GS Threads Dispatched */ +#define sklgt2__tdl_1__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set TDL_1 :: Early Hi-Depth Test Fails */ +#define sklgt2__tdl_1__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set TDL_1 :: FS Both FPU Active */ +#define sklgt2__tdl_1__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set TDL_1 :: VS Threads Dispatched */ +#define sklgt2__tdl_1__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set TDL_1 :: FS Threads Dispatched */ +#define sklgt2__tdl_1__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice2 */ +#define sklgt2__tdl_1__non_ps_thread02_ready_for_dispatch__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Metric set TDL_1 :: Shader Barrier Messages */ +#define sklgt2__tdl_1__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_1 :: Sampler Texels */ +#define sklgt2__tdl_1__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set TDL_1 :: Pixels Failing Tests */ +#define sklgt2__tdl_1__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set TDL_1 :: GPU Time Elapsed */ +#define sklgt2__tdl_1__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set TDL_1 :: AVG GPU Core Frequency */ +#define sklgt2__tdl_1__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set TDL_1 :: AVG GPU Core Frequency */ +#define sklgt2__tdl_1__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set TDL_1 :: Sampler Texels Misses */ +#define sklgt2__tdl_1__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice0 */ +#define sklgt2__tdl_1__non_ps_thread00_ready_for_dispatch__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Metric set TDL_1 :: CS Threads Dispatched */ +#define sklgt2__tdl_1__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set TDL_1 :: SLM Bytes Read */ +#define sklgt2__tdl_1__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set TDL_1 :: PS FPU1 Pipe Active */ +#define sklgt2__tdl_1__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set TDL_1 :: PS Send Pipeline Active */ +#define sklgt2__tdl_1__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set TDL_1 :: VS FPU0 Pipe Active */ +#define sklgt2__tdl_1__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set TDL_1 :: GPU Busy */ +#define sklgt2__tdl_1__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice0 */ +#define sklgt2__tdl_1__ps_thread00_ready_for_dispatch__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set TDL_1 :: Rasterized Pixels */ +#define sklgt2__tdl_1__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set TDL_1 :: PS FPU0 Pipe Active */ +#define sklgt2__tdl_1__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set TDL_1 :: DS Threads Dispatched */ +#define sklgt2__tdl_1__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set TDL_1 :: Samples Written */ +#define sklgt2__tdl_1__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set TDL_1 :: EU Stall */ +#define sklgt2__tdl_1__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set TDL_1 :: Samples Blended */ +#define sklgt2__tdl_1__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set TDL_1 :: Early Depth Test Fails */ +#define sklgt2__tdl_1__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice1 */ +#define sklgt2__tdl_1__ps_thread01_ready_for_dispatch__read \ + bdw__render_pipe_profile__cl_bottleneck__read + +/* Metric set TDL_1 :: Shader Memory Accesses */ +#define sklgt2__tdl_1__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set TDL_1 :: HS Threads Dispatched */ +#define sklgt2__tdl_1__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice2 */ +#define sklgt2__tdl_1__ps_thread02_ready_for_dispatch__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Metric set TDL_1 :: SLM Bytes Written */ +#define sklgt2__tdl_1__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set TDL_1 :: L3 Shader Throughput */ +#define sklgt2__tdl_1__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set TDL_1 :: Samples Killed in FS */ +#define sklgt2__tdl_1__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set TDL_1 :: Shader Atomic Memory Accesses */ +#define sklgt2__tdl_1__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice1 */ +#define sklgt2__tdl_1__non_ps_thread01_ready_for_dispatch__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set TDL_2 :: GPU Core Clocks */ +#define sklgt2__tdl_2__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set TDL_2 :: EU Active */ +#define sklgt2__tdl_2__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set TDL_2 :: EU Both FPU Pipes Active */ +#define sklgt2__tdl_2__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set TDL_2 :: VS Send Pipe Active */ +#define sklgt2__tdl_2__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set TDL_2 :: VS FPU1 Pipe Active */ +#define sklgt2__tdl_2__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set TDL_2 :: GS Threads Dispatched */ +#define sklgt2__tdl_2__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set TDL_2 :: Early Hi-Depth Test Fails */ +#define sklgt2__tdl_2__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set TDL_2 :: FS Both FPU Active */ +#define sklgt2__tdl_2__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set TDL_2 :: VS Threads Dispatched */ +#define sklgt2__tdl_2__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set TDL_2 :: FS Threads Dispatched */ +#define sklgt2__tdl_2__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set TDL_2 :: Shader Barrier Messages */ +#define sklgt2__tdl_2__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_2 :: Sampler Texels */ +#define sklgt2__tdl_2__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set TDL_2 :: Pixels Failing Tests */ +#define sklgt2__tdl_2__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 0 */ +#define sklgt2__tdl_2__thread_header01_ready_port0__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 1 */ +#define sklgt2__tdl_2__thread_header01_ready_port1__read \ + bdw__render_pipe_profile__ds_stall__read + +/* Metric set TDL_2 :: GPU Time Elapsed */ +#define sklgt2__tdl_2__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set TDL_2 :: AVG GPU Core Frequency */ +#define sklgt2__tdl_2__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set TDL_2 :: AVG GPU Core Frequency */ +#define sklgt2__tdl_2__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set TDL_2 :: Sampler Texels Misses */ +#define sklgt2__tdl_2__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set TDL_2 :: CS Threads Dispatched */ +#define sklgt2__tdl_2__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set TDL_2 :: SLM Bytes Read */ +#define sklgt2__tdl_2__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set TDL_2 :: PS FPU1 Pipe Active */ +#define sklgt2__tdl_2__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set TDL_2 :: PS Send Pipeline Active */ +#define sklgt2__tdl_2__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set TDL_2 :: VS FPU0 Pipe Active */ +#define sklgt2__tdl_2__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set TDL_2 :: GPU Busy */ +#define sklgt2__tdl_2__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 1 */ +#define sklgt2__tdl_2__thread_header02_ready_port1__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 0 */ +#define sklgt2__tdl_2__thread_header02_ready_port0__read \ + bdw__render_pipe_profile__so_stall__read + +/* Metric set TDL_2 :: Rasterized Pixels */ +#define sklgt2__tdl_2__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set TDL_2 :: PS FPU0 Pipe Active */ +#define sklgt2__tdl_2__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set TDL_2 :: DS Threads Dispatched */ +#define sklgt2__tdl_2__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set TDL_2 :: Samples Written */ +#define sklgt2__tdl_2__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set TDL_2 :: EU Stall */ +#define sklgt2__tdl_2__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set TDL_2 :: Samples Blended */ +#define sklgt2__tdl_2__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set TDL_2 :: Early Depth Test Fails */ +#define sklgt2__tdl_2__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_2 :: Shader Memory Accesses */ +#define sklgt2__tdl_2__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set TDL_2 :: HS Threads Dispatched */ +#define sklgt2__tdl_2__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set TDL_2 :: SLM Bytes Written */ +#define sklgt2__tdl_2__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set TDL_2 :: L3 Shader Throughput */ +#define sklgt2__tdl_2__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set TDL_2 :: Samples Killed in FS */ +#define sklgt2__tdl_2__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 0 */ +#define sklgt2__tdl_2__thread_header00_ready_port0__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set TDL_2 :: Shader Atomic Memory Accesses */ +#define sklgt2__tdl_2__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 1 */ +#define sklgt2__tdl_2__thread_header00_ready_port1__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Compute Metrics Extra Gen9 :: GPU Core Clocks */ +#define sklgt2__compute_extra__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Extra Gen9 :: EU FPU1 Pipe Active */ +#define sklgt2__compute_extra__fpu1_active__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics Extra Gen9 :: GPU Time Elapsed */ +#define sklgt2__compute_extra__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics Extra Gen9 :: AVG GPU Core Frequency */ +#define sklgt2__compute_extra__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics Extra Gen9 :: AVG GPU Core Frequency */ +#define sklgt2__compute_extra__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics Extra Gen9 :: EU FPU1 Pipe Active including Ext Math */ +static float +sklgt2__compute_extra__fpu1_active_adjusted__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 8 READ C 7 READ C 6 READ FADD C 5 READ FADD 8 FMUL FADD 100 FMUL $EuCoresTotalCount FDIV $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 8]; + uint64_t tmp1 = accumulator[query->c_offset + 7]; + uint64_t tmp2 = accumulator[query->c_offset + 6]; + double tmp3 = tmp1 + tmp2; + uint64_t tmp4 = accumulator[query->c_offset + 5]; + double tmp5 = tmp3 + tmp4; + double tmp6 = tmp5 * 8; + double tmp7 = tmp0 + tmp6; + double tmp8 = tmp7 * 100; + double tmp9 = tmp8; + double tmp10 = brw->perfquery.sys_vars.n_eus; + double tmp11 = tmp10 ? tmp9 / tmp10 : 0; + double tmp12 = tmp11; + double tmp13 = sklgt2__compute_extra__gpu_core_clocks__read(brw, query, accumulator); + double tmp14 = tmp13 ? tmp12 / tmp13 : 0; + + return tmp14; +} + +/* Media Vme Pipe Gen9 :: GPU Core Clocks */ +#define sklgt2__vme_pipe__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Media Vme Pipe Gen9 :: EU Active */ +#define sklgt2__vme_pipe__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Media Vme Pipe Gen9 :: EU Both FPU Pipes Active */ +#define sklgt2__vme_pipe__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Media Vme Pipe Gen9 :: GPU Time Elapsed */ +#define sklgt2__vme_pipe__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Media Vme Pipe Gen9 :: AVG GPU Core Frequency */ +#define sklgt2__vme_pipe__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Media Vme Pipe Gen9 :: AVG GPU Core Frequency */ +#define sklgt2__vme_pipe__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Media Vme Pipe Gen9 :: CS Threads Dispatched */ +#define sklgt2__vme_pipe__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Media Vme Pipe Gen9 :: EU Thread Occupancy */ +#define sklgt2__vme_pipe__eu_thread_occupancy__read \ + bdw__vme_pipe__eu_thread_occupancy__read + +/* Media Vme Pipe Gen9 :: EU Stall */ +#define sklgt2__vme_pipe__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Media Vme Pipe Gen9 :: VME Busy */ +#define sklgt2__vme_pipe__vme_busy__read \ + bdw__vme_pipe__vme_busy__read + +/* Media Vme Pipe Gen9 :: GPU Busy */ +#define sklgt2__vme_pipe__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Gpu Rings Busyness :: GPU Core Clocks */ +#define sklgt2__gpu_busyness__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Gpu Rings Busyness :: Vebox Ring Busy */ +#define sklgt2__gpu_busyness__vebox_busy__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Gpu Rings Busyness :: GPU Time Elapsed */ +#define sklgt2__gpu_busyness__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Gpu Rings Busyness :: AVG GPU Core Frequency */ +#define sklgt2__gpu_busyness__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Gpu Rings Busyness :: AVG GPU Core Frequency */ +#define sklgt2__gpu_busyness__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Gpu Rings Busyness :: Render Ring Busy */ +#define sklgt2__gpu_busyness__render_busy__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Gpu Rings Busyness :: Vdbox0 Ring Busy */ +#define sklgt2__gpu_busyness__vdbox0_busy__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Gpu Rings Busyness :: Blitter Ring Busy */ +#define sklgt2__gpu_busyness__blitter_busy__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Gpu Rings Busyness :: AnyRingBusy */ +#define sklgt2__gpu_busyness__any_ring_busy__read \ + bdw__render_basic__sampler0_busy__read + +/* MDAPI testing set Gen9 :: TestCounter7 */ +#define sklgt2__test_oa__counter7__read \ + hsw__compute_extended__gpu_clocks__read + +/* MDAPI testing set Gen9 :: GPU Time Elapsed */ +#define sklgt2__test_oa__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* MDAPI testing set Gen9 :: GPU Core Clocks */ +#define sklgt2__test_oa__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* MDAPI testing set Gen9 :: AVG GPU Core Frequency */ +#define sklgt2__test_oa__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* MDAPI testing set Gen9 :: AVG GPU Core Frequency */ +#define sklgt2__test_oa__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* MDAPI testing set Gen9 :: TestCounter8 */ +#define sklgt2__test_oa__counter8__read \ + hsw__memory_reads__gpu_core_clocks__read + +/* MDAPI testing set Gen9 :: TestCounter4 */ +#define sklgt2__test_oa__counter4__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* MDAPI testing set Gen9 :: TestCounter5 */ +#define sklgt2__test_oa__counter5__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* MDAPI testing set Gen9 :: TestCounter6 */ +#define sklgt2__test_oa__counter6__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* MDAPI testing set Gen9 :: TestCounter3 */ +#define sklgt2__test_oa__counter3__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* MDAPI testing set Gen9 :: TestCounter0 */ +#define sklgt2__test_oa__counter0__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* MDAPI testing set Gen9 :: TestCounter1 */ +#define sklgt2__test_oa__counter1__read \ + hsw__compute_extended__eu_untyped_writes0__read + +/* MDAPI testing set Gen9 :: TestCounter2 */ +#define sklgt2__test_oa__counter2__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Render Metrics Basic Gen9 :: GPU Core Clocks */ +#define sklgt3__render_basic__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Render Metrics Basic Gen9 :: EU Active */ +#define sklgt3__render_basic__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Render Metrics Basic Gen9 :: L3 Misses */ +#define sklgt3__render_basic__l3_misses__read \ + hsw__compute_extended__typed_atomics0__read + +/* Render Metrics Basic Gen9 :: GTI L3 Throughput */ +#define sklgt3__render_basic__gti_l3_throughput__read \ + hsw__render_basic__gti_l3_throughput__read + +/* Render Metrics Basic Gen9 :: EU Both FPU Pipes Active */ +#define sklgt3__render_basic__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Render Metrics Basic Gen9 :: Sampler Cache Misses */ +#define sklgt3__render_basic__sampler_l1_misses__read \ + bdw__render_basic__sampler_l1_misses__read + +/* Render Metrics Basic Gen9 :: VS Send Pipe Active */ +#define sklgt3__render_basic__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Render Metrics Basic Gen9 :: Sampler 1 Bottleneck */ +#define sklgt3__render_basic__sampler1_bottleneck__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Render Metrics Basic Gen9 :: VS FPU1 Pipe Active */ +#define sklgt3__render_basic__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Render Metrics Basic Gen9 :: GS Threads Dispatched */ +#define sklgt3__render_basic__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Render Metrics Basic Gen9 :: L3 Sampler Throughput */ +#define sklgt3__render_basic__l3_sampler_throughput__read \ + bdw__render_basic__l3_sampler_throughput__read + +/* Render Metrics Basic Gen9 :: Early Hi-Depth Test Fails */ +#define sklgt3__render_basic__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Render Metrics Basic Gen9 :: FS Both FPU Active */ +#define sklgt3__render_basic__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Render Metrics Basic Gen9 :: VS Threads Dispatched */ +#define sklgt3__render_basic__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Render Metrics Basic Gen9 :: FS Threads Dispatched */ +#define sklgt3__render_basic__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Render Metrics Basic Gen9 :: Sampler 0 Busy */ +#define sklgt3__render_basic__sampler0_busy__read \ + bdw__render_basic__sampler0_busy__read + +/* Render Metrics Basic Gen9 :: Sampler 1 Busy */ +#define sklgt3__render_basic__sampler1_busy__read \ + bdw__render_basic__sampler1_busy__read + +/* Render Metrics Basic Gen9 :: Samplers Busy */ +#define sklgt3__render_basic__samplers_busy__read \ + bdw__render_basic__samplers_busy__read + +/* Render Metrics Basic Gen9 :: GTI Fixed Pipe Throughput */ +#define sklgt3__render_basic__gti_vf_throughput__read \ + bdw__render_basic__gti_vf_throughput__read + +/* Render Metrics Basic Gen9 :: Shader Barrier Messages */ +#define sklgt3__render_basic__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Render Metrics Basic Gen9 :: Sampler 0 Bottleneck */ +#define sklgt3__render_basic__sampler0_bottleneck__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Render Metrics Basic Gen9 :: Sampler Texels */ +#define sklgt3__render_basic__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Render Metrics Basic Gen9 :: Pixels Failing Tests */ +#define sklgt3__render_basic__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Render Metrics Basic Gen9 :: GPU Time Elapsed */ +#define sklgt3__render_basic__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Render Metrics Basic Gen9 :: AVG GPU Core Frequency */ +#define sklgt3__render_basic__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Render Metrics Basic Gen9 :: AVG GPU Core Frequency */ +#define sklgt3__render_basic__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Render Metrics Basic Gen9 :: Sampler Texels Misses */ +#define sklgt3__render_basic__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Render Metrics Basic Gen9 :: CS Threads Dispatched */ +#define sklgt3__render_basic__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Render Metrics Basic Gen9 :: Shader Memory Accesses */ +#define sklgt3__render_basic__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Render Metrics Basic Gen9 :: L3 Lookup Accesses w/o IC */ +#define sklgt3__render_basic__l3_lookups__read \ + bdw__render_basic__l3_lookups__read + +/* Render Metrics Basic Gen9 :: SLM Bytes Read */ +#define sklgt3__render_basic__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Render Metrics Basic Gen9 :: GTI Read Throughput */ +#define sklgt3__render_basic__gti_read_throughput__read \ + bdw__render_basic__gti_read_throughput__read + +/* Render Metrics Basic Gen9 :: PS FPU1 Pipe Active */ +#define sklgt3__render_basic__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Render Metrics Basic Gen9 :: PS Send Pipeline Active */ +#define sklgt3__render_basic__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Render Metrics Basic Gen9 :: Rasterized Pixels */ +#define sklgt3__render_basic__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Render Metrics Basic Gen9 :: GPU Busy */ +#define sklgt3__render_basic__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Render Metrics Basic Gen9 :: GTI Depth Throughput */ +#define sklgt3__render_basic__gti_depth_throughput__read \ + bdw__render_basic__gti_depth_throughput__read + +/* Render Metrics Basic Gen9 :: VS FPU0 Pipe Active */ +#define sklgt3__render_basic__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Render Metrics Basic Gen9 :: PS FPU0 Pipe Active */ +#define sklgt3__render_basic__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Render Metrics Basic Gen9 :: DS Threads Dispatched */ +#define sklgt3__render_basic__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Render Metrics Basic Gen9 :: Samples Written */ +#define sklgt3__render_basic__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Render Metrics Basic Gen9 :: EU Stall */ +#define sklgt3__render_basic__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Render Metrics Basic Gen9 :: Samples Blended */ +#define sklgt3__render_basic__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Render Metrics Basic Gen9 :: Early Depth Test Fails */ +#define sklgt3__render_basic__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Render Metrics Basic Gen9 :: Samplers Bottleneck */ +#define sklgt3__render_basic__sampler_bottleneck__read \ + bdw__render_basic__sampler_bottleneck__read + +/* Render Metrics Basic Gen9 :: GTI HDC TLB Lookup Throughput */ +#define sklgt3__render_basic__gti_hdc_lookups_throughput__read \ + bdw__render_basic__gti_hdc_lookups_throughput__read + +/* Render Metrics Basic Gen9 :: GTI RCC Throughput */ +#define sklgt3__render_basic__gti_rcc_throughput__read \ + bdw__render_basic__gti_rcc_throughput__read + +/* Render Metrics Basic Gen9 :: HS Threads Dispatched */ +#define sklgt3__render_basic__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Render Metrics Basic Gen9 :: GTI Write Throughput */ +#define sklgt3__render_basic__gti_write_throughput__read \ + hsw__render_basic__gti_write_throughput__read + +/* Render Metrics Basic Gen9 :: SLM Bytes Written */ +#define sklgt3__render_basic__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Render Metrics Basic Gen9 :: L3 Shader Throughput */ +#define sklgt3__render_basic__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Render Metrics Basic Gen9 :: Samples Killed in FS */ +#define sklgt3__render_basic__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Render Metrics Basic Gen9 :: Shader Atomic Memory Accesses */ +#define sklgt3__render_basic__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Basic Gen9 :: GPU Core Clocks */ +#define sklgt3__compute_basic__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Basic Gen9 :: EU Active */ +#define sklgt3__compute_basic__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Compute Metrics Basic Gen9 :: Untyped Bytes Read */ +#define sklgt3__compute_basic__untyped_bytes_read__read \ + bdw__compute_basic__untyped_bytes_read__read + +/* Compute Metrics Basic Gen9 :: EU Both FPU Pipes Active */ +#define sklgt3__compute_basic__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Compute Metrics Basic Gen9 :: Typed Bytes Written */ +#define sklgt3__compute_basic__typed_bytes_written__read \ + bdw__compute_basic__typed_bytes_written__read + +/* Compute Metrics Basic Gen9 :: EU FPU0 Pipe Active */ +#define sklgt3__compute_basic__fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Compute Metrics Basic Gen9 :: EU FPU1 Pipe Active */ +#define sklgt3__compute_basic__fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Compute Metrics Basic Gen9 :: EU AVG IPC Rate */ +#define sklgt3__compute_basic__eu_avg_ipc_rate__read \ + bdw__compute_basic__eu_avg_ipc_rate__read + +/* Compute Metrics Basic Gen9 :: GS Threads Dispatched */ +#define sklgt3__compute_basic__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Compute Metrics Basic Gen9 :: Early Hi-Depth Test Fails */ +#define sklgt3__compute_basic__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Compute Metrics Basic Gen9 :: VS Threads Dispatched */ +#define sklgt3__compute_basic__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Compute Metrics Basic Gen9 :: FS Threads Dispatched */ +#define sklgt3__compute_basic__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Compute Metrics Basic Gen9 :: Shader Barrier Messages */ +#define sklgt3__compute_basic__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Compute Metrics Basic Gen9 :: Sampler Texels */ +#define sklgt3__compute_basic__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Compute Metrics Basic Gen9 :: Pixels Failing Tests */ +#define sklgt3__compute_basic__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Compute Metrics Basic Gen9 :: GPU Time Elapsed */ +#define sklgt3__compute_basic__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics Basic Gen9 :: AVG GPU Core Frequency */ +#define sklgt3__compute_basic__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics Basic Gen9 :: AVG GPU Core Frequency */ +#define sklgt3__compute_basic__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics Basic Gen9 :: Sampler Texels Misses */ +#define sklgt3__compute_basic__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Compute Metrics Basic Gen9 :: CS Threads Dispatched */ +#define sklgt3__compute_basic__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Compute Metrics Basic Gen9 :: SLM Bytes Read */ +#define sklgt3__compute_basic__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Compute Metrics Basic Gen9 :: GTI Read Throughput */ +#define sklgt3__compute_basic__gti_read_throughput__read \ + hsw__render_basic__gti_l3_throughput__read + +/* Compute Metrics Basic Gen9 :: Untyped Writes */ +#define sklgt3__compute_basic__untyped_bytes_written__read \ + bdw__compute_basic__untyped_bytes_written__read + +/* Compute Metrics Basic Gen9 :: GPU Busy */ +#define sklgt3__compute_basic__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Compute Metrics Basic Gen9 :: Rasterized Pixels */ +#define sklgt3__compute_basic__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Compute Metrics Basic Gen9 :: Typed Bytes Read */ +#define sklgt3__compute_basic__typed_bytes_read__read \ + bdw__compute_basic__typed_bytes_read__read + +/* Compute Metrics Basic Gen9 :: DS Threads Dispatched */ +#define sklgt3__compute_basic__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Compute Metrics Basic Gen9 :: EU Thread Occupancy */ +#define sklgt3__compute_basic__eu_thread_occupancy__read \ + bdw__compute_basic__eu_thread_occupancy__read + +/* Compute Metrics Basic Gen9 :: EU Stall */ +#define sklgt3__compute_basic__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics Basic Gen9 :: Samples Blended */ +#define sklgt3__compute_basic__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Compute Metrics Basic Gen9 :: Early Depth Test Fails */ +#define sklgt3__compute_basic__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Compute Metrics Basic Gen9 :: Shader Memory Accesses */ +#define sklgt3__compute_basic__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Compute Metrics Basic Gen9 :: HS Threads Dispatched */ +#define sklgt3__compute_basic__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Compute Metrics Basic Gen9 :: GTI Write Throughput */ +#define sklgt3__compute_basic__gti_write_throughput__read \ + bdw__render_basic__gti_hdc_lookups_throughput__read + +/* Compute Metrics Basic Gen9 :: SLM Bytes Written */ +#define sklgt3__compute_basic__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Compute Metrics Basic Gen9 :: L3 Shader Throughput */ +#define sklgt3__compute_basic__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Compute Metrics Basic Gen9 :: Samples Killed in FS */ +#define sklgt3__compute_basic__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Compute Metrics Basic Gen9 :: Samples Written */ +#define sklgt3__compute_basic__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Compute Metrics Basic Gen9 :: Shader Atomic Memory Accesses */ +#define sklgt3__compute_basic__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Basic Gen9 :: EU Send Pipe Active */ +#define sklgt3__compute_basic__eu_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Core Clocks */ +#define sklgt3__render_pipe_profile__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: EU Active */ +#define sklgt3__render_pipe_profile__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: VS Bottleneck */ +#define sklgt3__render_pipe_profile__vs_bottleneck__read \ + bdw__render_basic__sampler0_busy__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Hi-Depth Bottleneck */ +#define sklgt3__render_pipe_profile__hi_depth_bottleneck__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GS Bottleneck */ +#define sklgt3__render_pipe_profile__gs_bottleneck__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GS Threads Dispatched */ +#define sklgt3__render_pipe_profile__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Early Hi-Depth Test Fails */ +#define sklgt3__render_pipe_profile__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: VS Threads Dispatched */ +#define sklgt3__render_pipe_profile__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: FS Threads Dispatched */ +#define sklgt3__render_pipe_profile__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: BC Bottleneck */ +#define sklgt3__render_pipe_profile__bc_bottleneck__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: HS Stall */ +#define sklgt3__render_pipe_profile__hs_stall__read \ + bdw__render_pipe_profile__hs_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Barrier Messages */ +#define sklgt3__render_pipe_profile__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Sampler Texels */ +#define sklgt3__render_pipe_profile__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Pixels Failing Tests */ +#define sklgt3__render_pipe_profile__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Time Elapsed */ +#define sklgt3__render_pipe_profile__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: AVG GPU Core Frequency */ +#define sklgt3__render_pipe_profile__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: AVG GPU Core Frequency */ +#define sklgt3__render_pipe_profile__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Sampler Texels Misses */ +#define sklgt3__render_pipe_profile__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: CS Threads Dispatched */ +#define sklgt3__render_pipe_profile__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: VF Bottleneck */ +#define sklgt3__render_pipe_profile__vf_bottleneck__read \ + bdw__render_pipe_profile__vf_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SLM Bytes Read */ +#define sklgt3__render_pipe_profile__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Strip-Fans Bottleneck */ +#define sklgt3__render_pipe_profile__sf_bottleneck__read \ + bdw__render_pipe_profile__sf_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SF Stall */ +#define sklgt3__render_pipe_profile__sf_stall__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Busy */ +#define sklgt3__render_pipe_profile__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: HS Bottleneck */ +#define sklgt3__render_pipe_profile__hs_bottleneck__read \ + bdw__render_basic__sampler1_busy__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: CL Stall */ +#define sklgt3__render_pipe_profile__cl_stall__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SO Bottleneck */ +#define sklgt3__render_pipe_profile__so_bottleneck__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Rasterized Pixels */ +#define sklgt3__render_pipe_profile__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: DS Threads Dispatched */ +#define sklgt3__render_pipe_profile__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Written */ +#define sklgt3__render_pipe_profile__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: DS Bottleneck */ +#define sklgt3__render_pipe_profile__ds_bottleneck__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: EU Stall */ +#define sklgt3__render_pipe_profile__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Clipper Bottleneck */ +#define sklgt3__render_pipe_profile__cl_bottleneck__read \ + bdw__render_pipe_profile__cl_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: DS Stall */ +#define sklgt3__render_pipe_profile__ds_stall__read \ + bdw__render_pipe_profile__ds_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Early Depth Bottleneck */ +#define sklgt3__render_pipe_profile__early_depth_bottleneck__read \ + bdw__render_pipe_profile__early_depth_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Blended */ +#define sklgt3__render_pipe_profile__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Early Depth Test Fails */ +#define sklgt3__render_pipe_profile__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Memory Accesses */ +#define sklgt3__render_pipe_profile__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: HS Threads Dispatched */ +#define sklgt3__render_pipe_profile__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SLM Bytes Written */ +#define sklgt3__render_pipe_profile__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: L3 Shader Throughput */ +#define sklgt3__render_pipe_profile__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Killed in FS */ +#define sklgt3__render_pipe_profile__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SO Stall */ +#define sklgt3__render_pipe_profile__so_stall__read \ + bdw__render_pipe_profile__so_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Atomic Memory Accesses */ +#define sklgt3__render_pipe_profile__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Memory Reads Distribution Gen9 :: GPU Core Clocks */ +#define sklgt3__memory_reads__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Memory Reads Distribution Gen9 :: EU Active */ +#define sklgt3__memory_reads__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Memory Reads Distribution Gen9 :: GtiL3Bank0Reads */ +#define sklgt3__memory_reads__gti_l3_bank0_reads__read \ + hsw__compute_extended__typed_atomics0__read + +/* Memory Reads Distribution Gen9 :: GS Threads Dispatched */ +#define sklgt3__memory_reads__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Memory Reads Distribution Gen9 :: GtiRingAccesses */ +#define sklgt3__memory_reads__gti_ring_accesses__read \ + bdw__memory_reads__gti_ring_accesses__read + +/* Memory Reads Distribution Gen9 :: Early Hi-Depth Test Fails */ +#define sklgt3__memory_reads__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Memory Reads Distribution Gen9 :: VS Threads Dispatched */ +#define sklgt3__memory_reads__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Memory Reads Distribution Gen9 :: FS Threads Dispatched */ +#define sklgt3__memory_reads__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Memory Reads Distribution Gen9 :: GtiL3Bank3Reads */ +#define sklgt3__memory_reads__gti_l3_bank3_reads__read \ + hsw__memory_reads__gpu_core_clocks__read + +/* Memory Reads Distribution Gen9 :: Shader Barrier Messages */ +#define sklgt3__memory_reads__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Memory Reads Distribution Gen9 :: GtiRsMemoryReads */ +#define sklgt3__memory_reads__gti_rs_memory_reads__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Memory Reads Distribution Gen9 :: Sampler Texels */ +#define sklgt3__memory_reads__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Memory Reads Distribution Gen9 :: Pixels Failing Tests */ +#define sklgt3__memory_reads__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Memory Reads Distribution Gen9 :: GtiHizMemoryReads */ +#define sklgt3__memory_reads__gti_hiz_memory_reads__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* Memory Reads Distribution Gen9 :: GPU Time Elapsed */ +#define sklgt3__memory_reads__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Memory Reads Distribution Gen9 :: AVG GPU Core Frequency */ +#define sklgt3__memory_reads__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Memory Reads Distribution Gen9 :: AVG GPU Core Frequency */ +#define sklgt3__memory_reads__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Memory Reads Distribution Gen9 :: Sampler Texels Misses */ +#define sklgt3__memory_reads__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Memory Reads Distribution Gen9 :: GtiRccMemoryReads */ +#define sklgt3__memory_reads__gti_rcc_memory_reads__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* Memory Reads Distribution Gen9 :: CS Threads Dispatched */ +#define sklgt3__memory_reads__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Memory Reads Distribution Gen9 :: SLM Bytes Read */ +#define sklgt3__memory_reads__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Memory Reads Distribution Gen9 :: GtiL3Bank1Reads */ +#define sklgt3__memory_reads__gti_l3_bank1_reads__read \ + hsw__memory_reads__gti_memory_reads__read + +/* Memory Reads Distribution Gen9 :: GPU Busy */ +#define sklgt3__memory_reads__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Memory Reads Distribution Gen9 :: GtiCmdStreamerMemoryReads */ +#define sklgt3__memory_reads__gti_cmd_streamer_memory_reads__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* Memory Reads Distribution Gen9 :: GtiL3Bank2Reads */ +#define sklgt3__memory_reads__gti_l3_bank2_reads__read \ + hsw__memory_reads__llc_read_accesses__read + +/* Memory Reads Distribution Gen9 :: GtiMemoryReads */ +#define sklgt3__memory_reads__gti_memory_reads__read \ + hsw__compute_extended__typed_writes0__read + +/* Memory Reads Distribution Gen9 :: Rasterized Pixels */ +#define sklgt3__memory_reads__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Memory Reads Distribution Gen9 :: GtiRczMemoryReads */ +#define sklgt3__memory_reads__gti_rcz_memory_reads__read \ + hsw__compute_extended__gpu_clocks__read + +/* Memory Reads Distribution Gen9 :: DS Threads Dispatched */ +#define sklgt3__memory_reads__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Memory Reads Distribution Gen9 :: Samples Written */ +#define sklgt3__memory_reads__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Memory Reads Distribution Gen9 :: EU Stall */ +#define sklgt3__memory_reads__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Memory Reads Distribution Gen9 :: Samples Blended */ +#define sklgt3__memory_reads__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Memory Reads Distribution Gen9 :: Early Depth Test Fails */ +#define sklgt3__memory_reads__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Memory Reads Distribution Gen9 :: GtiMscMemoryReads */ +#define sklgt3__memory_reads__gti_msc_memory_reads__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* Memory Reads Distribution Gen9 :: GtiVfMemoryReads */ +#define sklgt3__memory_reads__gti_vf_memory_reads__read \ + hsw__compute_extended__eu_untyped_writes0__read + +/* Memory Reads Distribution Gen9 :: GtiStcMemoryReads */ +#define sklgt3__memory_reads__gti_stc_memory_reads__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* Memory Reads Distribution Gen9 :: Shader Memory Accesses */ +#define sklgt3__memory_reads__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Memory Reads Distribution Gen9 :: HS Threads Dispatched */ +#define sklgt3__memory_reads__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Memory Reads Distribution Gen9 :: Samples Killed in FS */ +#define sklgt3__memory_reads__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Memory Reads Distribution Gen9 :: SLM Bytes Written */ +#define sklgt3__memory_reads__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Memory Reads Distribution Gen9 :: GtiL3Reads */ +#define sklgt3__memory_reads__gti_l3_reads__read \ + bdw__memory_reads__gti_l3_reads__read + +/* Memory Reads Distribution Gen9 :: Shader Atomic Memory Accesses */ +#define sklgt3__memory_reads__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Memory Writes Distribution Gen9 :: GPU Core Clocks */ +#define sklgt3__memory_writes__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Memory Writes Distribution Gen9 :: EU Active */ +#define sklgt3__memory_writes__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Memory Writes Distribution Gen9 :: GtiMemoryWrites */ +#define sklgt3__memory_writes__gti_memory_writes__read \ + hsw__compute_extended__typed_writes0__read + +/* Memory Writes Distribution Gen9 :: GS Threads Dispatched */ +#define sklgt3__memory_writes__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Memory Writes Distribution Gen9 :: GtiRingAccesses */ +#define sklgt3__memory_writes__gti_ring_accesses__read \ + bdw__memory_reads__gti_ring_accesses__read + +/* Memory Writes Distribution Gen9 :: Early Hi-Depth Test Fails */ +#define sklgt3__memory_writes__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Memory Writes Distribution Gen9 :: VS Threads Dispatched */ +#define sklgt3__memory_writes__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Memory Writes Distribution Gen9 :: FS Threads Dispatched */ +#define sklgt3__memory_writes__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Memory Writes Distribution Gen9 :: GtiMscMemoryWrites */ +#define sklgt3__memory_writes__gti_msc_memory_writes__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* Memory Writes Distribution Gen9 :: Shader Barrier Messages */ +#define sklgt3__memory_writes__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Memory Writes Distribution Gen9 :: GtiCmdStreamerMemoryWrites */ +#define sklgt3__memory_writes__gti_cmd_streamer_memory_writes__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* Memory Writes Distribution Gen9 :: Sampler Texels */ +#define sklgt3__memory_writes__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Memory Writes Distribution Gen9 :: Pixels Failing Tests */ +#define sklgt3__memory_writes__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Memory Writes Distribution Gen9 :: GtiL3Bank0Writes */ +#define sklgt3__memory_writes__gti_l3_bank0_writes__read \ + hsw__compute_extended__typed_atomics0__read + +/* Memory Writes Distribution Gen9 :: GtiL3Bank1Writes */ +#define sklgt3__memory_writes__gti_l3_bank1_writes__read \ + hsw__memory_reads__gti_memory_reads__read + +/* Memory Writes Distribution Gen9 :: GtiL3Bank2Writes */ +#define sklgt3__memory_writes__gti_l3_bank2_writes__read \ + hsw__memory_reads__llc_read_accesses__read + +/* Memory Writes Distribution Gen9 :: GtiL3Bank3Writes */ +#define sklgt3__memory_writes__gti_l3_bank3_writes__read \ + hsw__memory_reads__gpu_core_clocks__read + +/* Memory Writes Distribution Gen9 :: GtiL3Writes */ +#define sklgt3__memory_writes__gti_l3_writes__read \ + bdw__memory_reads__gti_l3_reads__read + +/* Memory Writes Distribution Gen9 :: GPU Time Elapsed */ +#define sklgt3__memory_writes__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Memory Writes Distribution Gen9 :: AVG GPU Core Frequency */ +#define sklgt3__memory_writes__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Memory Writes Distribution Gen9 :: AVG GPU Core Frequency */ +#define sklgt3__memory_writes__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Memory Writes Distribution Gen9 :: Sampler Texels Misses */ +#define sklgt3__memory_writes__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Memory Writes Distribution Gen9 :: CS Threads Dispatched */ +#define sklgt3__memory_writes__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Memory Writes Distribution Gen9 :: SLM Bytes Read */ +#define sklgt3__memory_writes__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Memory Writes Distribution Gen9 :: GtiRccMemoryWrites */ +#define sklgt3__memory_writes__gti_rcc_memory_writes__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* Memory Writes Distribution Gen9 :: GtiSoMemoryWrites */ +#define sklgt3__memory_writes__gti_so_memory_writes__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Memory Writes Distribution Gen9 :: GPU Busy */ +#define sklgt3__memory_writes__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Memory Writes Distribution Gen9 :: GtiStcMemoryWrites */ +#define sklgt3__memory_writes__gti_stc_memory_writes__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* Memory Writes Distribution Gen9 :: Rasterized Pixels */ +#define sklgt3__memory_writes__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Memory Writes Distribution Gen9 :: DS Threads Dispatched */ +#define sklgt3__memory_writes__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Memory Writes Distribution Gen9 :: Samples Written */ +#define sklgt3__memory_writes__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Memory Writes Distribution Gen9 :: EU Stall */ +#define sklgt3__memory_writes__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Memory Writes Distribution Gen9 :: Samples Blended */ +#define sklgt3__memory_writes__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Memory Writes Distribution Gen9 :: Early Depth Test Fails */ +#define sklgt3__memory_writes__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Memory Writes Distribution Gen9 :: Shader Memory Accesses */ +#define sklgt3__memory_writes__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Memory Writes Distribution Gen9 :: HS Threads Dispatched */ +#define sklgt3__memory_writes__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Memory Writes Distribution Gen9 :: GtiRczMemoryWrites */ +#define sklgt3__memory_writes__gti_rcz_memory_writes__read \ + hsw__compute_extended__gpu_clocks__read + +/* Memory Writes Distribution Gen9 :: SLM Bytes Written */ +#define sklgt3__memory_writes__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Memory Writes Distribution Gen9 :: L3 Shader Throughput */ +#define sklgt3__memory_writes__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Memory Writes Distribution Gen9 :: Samples Killed in FS */ +#define sklgt3__memory_writes__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Memory Writes Distribution Gen9 :: GtiHizMemoryWrites */ +#define sklgt3__memory_writes__gti_hiz_memory_writes__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* Memory Writes Distribution Gen9 :: Shader Atomic Memory Accesses */ +#define sklgt3__memory_writes__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Extended Gen9 :: GPU Core Clocks */ +#define sklgt3__compute_extended__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Extended Gen9 :: EU Active */ +#define sklgt3__compute_extended__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Compute Metrics Extended Gen9 :: EU Both FPU Pipes Active */ +#define sklgt3__compute_extended__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Compute Metrics Extended Gen9 :: EU FPU0 Pipe Active */ +#define sklgt3__compute_extended__fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Compute Metrics Extended Gen9 :: EU FPU1 Pipe Active */ +#define sklgt3__compute_extended__fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Compute Metrics Extended Gen9 :: EU AVG IPC Rate */ +#define sklgt3__compute_extended__eu_avg_ipc_rate__read \ + bdw__compute_basic__eu_avg_ipc_rate__read + +/* Compute Metrics Extended Gen9 :: Typed Writes 0 */ +#define sklgt3__compute_extended__typed_writes0__read \ + hsw__compute_extended__typed_writes0__read + +/* Compute Metrics Extended Gen9 :: EuTypedAtomics0 */ +#define sklgt3__compute_extended__eu_typed_atomics0__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* Compute Metrics Extended Gen9 :: Typed Atomics 0 */ +#define sklgt3__compute_extended__typed_atomics0__read \ + hsw__compute_extended__typed_atomics0__read + +/* Compute Metrics Extended Gen9 :: TypedAtomicsPerCacheLine */ +#define sklgt3__compute_extended__typed_atomics_per_cache_line__read \ + hsw__compute_extended__typed_atomics_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: EuUntypedReads0 */ +#define sklgt3__compute_extended__eu_untyped_reads0__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* Compute Metrics Extended Gen9 :: Untyped Writes 0 */ +#define sklgt3__compute_extended__untyped_writes0__read \ + hsw__compute_extended__untyped_writes0__read + +/* Compute Metrics Extended Gen9 :: EuUntypedAtomics0 */ +#define sklgt3__compute_extended__eu_untyped_atomics0__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* Compute Metrics Extended Gen9 :: EuUntypedWrites0 */ +#define sklgt3__compute_extended__eu_untyped_writes0__read \ + hsw__compute_extended__eu_untyped_writes0__read + +/* Compute Metrics Extended Gen9 :: EuA64UntypedWrites0 */ +#define sklgt3__compute_extended__eu_a64_untyped_writes0__read \ + hsw__compute_extended__gpu_clocks__read + +/* Compute Metrics Extended Gen9 :: UntypedWritesPerCacheLine */ +#define sklgt3__compute_extended__untyped_writes_per_cache_line__read \ + bdw__compute_extended__untyped_writes_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: Shader Barrier Messages */ +#define sklgt3__compute_extended__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Compute Metrics Extended Gen9 :: Sampler Texels */ +#define sklgt3__compute_extended__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Compute Metrics Extended Gen9 :: GPU Time Elapsed */ +#define sklgt3__compute_extended__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics Extended Gen9 :: AVG GPU Core Frequency */ +#define sklgt3__compute_extended__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics Extended Gen9 :: AVG GPU Core Frequency */ +#define sklgt3__compute_extended__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics Extended Gen9 :: Sampler Texels Misses */ +#define sklgt3__compute_extended__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Compute Metrics Extended Gen9 :: CS Threads Dispatched */ +#define sklgt3__compute_extended__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Compute Metrics Extended Gen9 :: SLM Bytes Read */ +#define sklgt3__compute_extended__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Compute Metrics Extended Gen9 :: EuTypedWrites0 */ +#define sklgt3__compute_extended__eu_typed_writes0__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* Compute Metrics Extended Gen9 :: TypedWritesPerCacheLine */ +#define sklgt3__compute_extended__typed_writes_per_cache_line__read \ + hsw__compute_extended__typed_writes_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: Typed Reads 0 */ +#define sklgt3__compute_extended__typed_reads0__read \ + hsw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Extended Gen9 :: Untyped Reads 0 */ +#define sklgt3__compute_extended__untyped_reads0__read \ + hsw__compute_extended__untyped_reads0__read + +/* Compute Metrics Extended Gen9 :: EuA64UntypedReads0 */ +#define sklgt3__compute_extended__eu_a64_untyped_reads0__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* Compute Metrics Extended Gen9 :: EU Thread Occupancy */ +#define sklgt3__compute_extended__eu_thread_occupancy__read \ + bdw__compute_basic__eu_thread_occupancy__read + +/* Compute Metrics Extended Gen9 :: EU Stall */ +#define sklgt3__compute_extended__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics Extended Gen9 :: EuTypedReads0 */ +#define sklgt3__compute_extended__eu_typed_reads0__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Compute Metrics Extended Gen9 :: UntypedReadsPerCacheLine */ +#define sklgt3__compute_extended__untyped_reads_per_cache_line__read \ + bdw__compute_extended__untyped_reads_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: Shader Memory Accesses */ +#define sklgt3__compute_extended__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Compute Metrics Extended Gen9 :: TypedReadsPerCacheLine */ +#define sklgt3__compute_extended__typed_reads_per_cache_line__read \ + hsw__compute_extended__typed_reads_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: SLM Bytes Written */ +#define sklgt3__compute_extended__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Compute Metrics Extended Gen9 :: L3 Shader Throughput */ +#define sklgt3__compute_extended__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Compute Metrics Extended Gen9 :: Shader Atomic Memory Accesses */ +#define sklgt3__compute_extended__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Extended Gen9 :: EU Send Pipe Active */ +#define sklgt3__compute_extended__eu_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Compute Metrics L3 Cache Gen9 :: GPU Core Clocks */ +#define sklgt3__compute_l3_cache__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics L3 Cache Gen9 :: EU Active */ +#define sklgt3__compute_l3_cache__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 03 Accesses */ +#define sklgt3__compute_l3_cache__l3_bank03_accesses__read \ + bdw__compute_l3_cache__l3_bank03_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Accesses */ +#define sklgt3__compute_l3_cache__l3_accesses__read \ + sklgt2__compute_l3_cache__l3_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: EU Both FPU Pipes Active */ +#define sklgt3__compute_l3_cache__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Sampler Throughput */ +#define sklgt3__compute_l3_cache__l3_sampler_throughput__read \ + chv__render_basic__l3_sampler_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Pipe Active */ +#define sklgt3__compute_l3_cache__fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Pipe Active */ +#define sklgt3__compute_l3_cache__fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Compute Metrics L3 Cache Gen9 :: EU AVG IPC Rate */ +#define sklgt3__compute_l3_cache__eu_avg_ipc_rate__read \ + bdw__compute_basic__eu_avg_ipc_rate__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Binary Instruction */ +#define sklgt3__compute_l3_cache__eu_binary_fpu0_instruction__read \ + bdw__render_basic__ps_send_active__read + +/* Compute Metrics L3 Cache Gen9 :: GS Threads Dispatched */ +#define sklgt3__compute_l3_cache__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Compute Metrics L3 Cache Gen9 :: Shader Memory Accesses */ +#define sklgt3__compute_l3_cache__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: Early Hi-Depth Test Fails */ +#define sklgt3__compute_l3_cache__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Compute Metrics L3 Cache Gen9 :: VS Threads Dispatched */ +#define sklgt3__compute_l3_cache__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Compute Metrics L3 Cache Gen9 :: FS Threads Dispatched */ +#define sklgt3__compute_l3_cache__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Hybrid Instruction */ +#define sklgt3__compute_l3_cache__eu_hybrid_fpu0_instruction__read \ + bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Misses */ +#define sklgt3__compute_l3_cache__l3_misses__read \ + bdw__compute_l3_cache__l3_misses__read + +/* Compute Metrics L3 Cache Gen9 :: Shader Barrier Messages */ +#define sklgt3__compute_l3_cache__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 Accesses */ +#define sklgt3__compute_l3_cache__l3_bank00_accesses__read \ + bdw__compute_l3_cache__l3_bank00_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Move Instruction */ +#define sklgt3__compute_l3_cache__eu_move_fpu0_instruction__read \ + bdw__compute_l3_cache__eu_move_fpu0_instruction__read + +/* Compute Metrics L3 Cache Gen9 :: Sampler Texels */ +#define sklgt3__compute_l3_cache__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Compute Metrics L3 Cache Gen9 :: Pixels Failing Tests */ +#define sklgt3__compute_l3_cache__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Hybrid Instruction */ +#define sklgt3__compute_l3_cache__eu_hybrid_fpu1_instruction__read \ + bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read + +/* Compute Metrics L3 Cache Gen9 :: GPU Time Elapsed */ +#define sklgt3__compute_l3_cache__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics L3 Cache Gen9 :: AVG GPU Core Frequency */ +#define sklgt3__compute_l3_cache__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics L3 Cache Gen9 :: AVG GPU Core Frequency */ +#define sklgt3__compute_l3_cache__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics L3 Cache Gen9 :: Sampler Texels Misses */ +#define sklgt3__compute_l3_cache__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Compute Metrics L3 Cache Gen9 :: CS Threads Dispatched */ +#define sklgt3__compute_l3_cache__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Compute Metrics L3 Cache Gen9 :: SLM Bytes Read */ +#define sklgt3__compute_l3_cache__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Compute Metrics L3 Cache Gen9 :: GTI Read Throughput */ +#define sklgt3__compute_l3_cache__gti_read_throughput__read \ + bdw__render_basic__gti_read_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: GTI L3 Throughput */ +#define sklgt3__compute_l3_cache__gti_l3_throughput__read \ + bdw__compute_l3_cache__gti_l3_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 IC Accesses */ +#define sklgt3__compute_l3_cache__l3_bank00_ic_accesses__read \ + bdw__compute_l3_cache__l3_bank00_ic_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 IC Hits */ +#define sklgt3__compute_l3_cache__l3_bank00_ic_hits__read \ + bdw__compute_l3_cache__l3_bank00_ic_hits__read + +/* Compute Metrics L3 Cache Gen9 :: Sampler Accesses */ +#define sklgt3__compute_l3_cache__sampler_accesses__read \ + bdw__render_pipe_profile__sampler_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 01 Accesses */ +#define sklgt3__compute_l3_cache__l3_bank01_accesses__read \ + bdw__compute_l3_cache__l3_bank01_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: GPU Busy */ +#define sklgt3__compute_l3_cache__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Ternary Instruction */ +#define sklgt3__compute_l3_cache__eu_ternary_fpu0_instruction__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Compute Metrics L3 Cache Gen9 :: Shader Atomic Memory Accesses */ +#define sklgt3__compute_l3_cache__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics L3 Cache Gen9 :: Rasterized Pixels */ +#define sklgt3__compute_l3_cache__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Compute Metrics L3 Cache Gen9 :: DS Threads Dispatched */ +#define sklgt3__compute_l3_cache__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Compute Metrics L3 Cache Gen9 :: Samples Written */ +#define sklgt3__compute_l3_cache__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Move Instruction */ +#define sklgt3__compute_l3_cache__eu_move_fpu1_instruction__read \ + bdw__compute_l3_cache__eu_move_fpu1_instruction__read + +/* Compute Metrics L3 Cache Gen9 :: EU Stall */ +#define sklgt3__compute_l3_cache__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics L3 Cache Gen9 :: Samples Blended */ +#define sklgt3__compute_l3_cache__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Compute Metrics L3 Cache Gen9 :: Early Depth Test Fails */ +#define sklgt3__compute_l3_cache__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 02 Accesses */ +#define sklgt3__compute_l3_cache__l3_bank02_accesses__read \ + bdw__compute_l3_cache__l3_bank02_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: HS Threads Dispatched */ +#define sklgt3__compute_l3_cache__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Total Throughput */ +#define sklgt3__compute_l3_cache__l3_total_throughput__read \ + sklgt2__compute_l3_cache__l3_total_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: GTI Write Throughput */ +#define sklgt3__compute_l3_cache__gti_write_throughput__read \ + hsw__render_basic__gti_write_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: SLM Bytes Written */ +#define sklgt3__compute_l3_cache__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Shader Throughput */ +#define sklgt3__compute_l3_cache__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: Samples Killed in FS */ +#define sklgt3__compute_l3_cache__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Binary Instruction */ +#define sklgt3__compute_l3_cache__eu_binary_fpu1_instruction__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Ternary Instruction */ +#define sklgt3__compute_l3_cache__eu_ternary_fpu1_instruction__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Compute Metrics L3 Cache Gen9 :: EU Send Pipe Active */ +#define sklgt3__compute_l3_cache__eu_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set HDCAndSF :: GPU Core Clocks */ +#define sklgt3__hdc_and_sf__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set HDCAndSF :: EU Active */ +#define sklgt3__hdc_and_sf__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set HDCAndSF :: EU Both FPU Pipes Active */ +#define sklgt3__hdc_and_sf__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set HDCAndSF :: VS Send Pipe Active */ +#define sklgt3__hdc_and_sf__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set HDCAndSF :: VS FPU1 Pipe Active */ +#define sklgt3__hdc_and_sf__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set HDCAndSF :: GS Threads Dispatched */ +#define sklgt3__hdc_and_sf__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set HDCAndSF :: Early Hi-Depth Test Fails */ +#define sklgt3__hdc_and_sf__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set HDCAndSF :: FS Both FPU Active */ +#define sklgt3__hdc_and_sf__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set HDCAndSF :: VS Threads Dispatched */ +#define sklgt3__hdc_and_sf__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set HDCAndSF :: Polygon Data Ready */ +#define sklgt3__hdc_and_sf__poly_data_ready__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set HDCAndSF :: FS Threads Dispatched */ +#define sklgt3__hdc_and_sf__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set HDCAndSF :: Shader Barrier Messages */ +#define sklgt3__hdc_and_sf__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set HDCAndSF :: Sampler Texels */ +#define sklgt3__hdc_and_sf__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set HDCAndSF :: Pixels Failing Tests */ +#define sklgt3__hdc_and_sf__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set HDCAndSF :: GPU Time Elapsed */ +#define sklgt3__hdc_and_sf__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set HDCAndSF :: AVG GPU Core Frequency */ +#define sklgt3__hdc_and_sf__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set HDCAndSF :: AVG GPU Core Frequency */ +#define sklgt3__hdc_and_sf__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set HDCAndSF :: Sampler Texels Misses */ +#define sklgt3__hdc_and_sf__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */ +#define sklgt3__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read \ + bdw__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read + +/* Metric set HDCAndSF :: CS Threads Dispatched */ +#define sklgt3__hdc_and_sf__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss2) */ +#define sklgt3__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read \ + bdw__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read + +/* Metric set HDCAndSF :: SLM Bytes Read */ +#define sklgt3__hdc_and_sf__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set HDCAndSF :: PS FPU1 Pipe Active */ +#define sklgt3__hdc_and_sf__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set HDCAndSF :: PS Send Pipeline Active */ +#define sklgt3__hdc_and_sf__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set HDCAndSF :: VS FPU0 Pipe Active */ +#define sklgt3__hdc_and_sf__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set HDCAndSF :: GPU Busy */ +#define sklgt3__hdc_and_sf__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set HDCAndSF :: Rasterized Pixels */ +#define sklgt3__hdc_and_sf__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set HDCAndSF :: PS FPU0 Pipe Active */ +#define sklgt3__hdc_and_sf__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set HDCAndSF :: DS Threads Dispatched */ +#define sklgt3__hdc_and_sf__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set HDCAndSF :: Samples Written */ +#define sklgt3__hdc_and_sf__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set HDCAndSF :: EU Stall */ +#define sklgt3__hdc_and_sf__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set HDCAndSF :: Samples Blended */ +#define sklgt3__hdc_and_sf__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set HDCAndSF :: Early Depth Test Fails */ +#define sklgt3__hdc_and_sf__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set HDCAndSF :: Shader Memory Accesses */ +#define sklgt3__hdc_and_sf__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set HDCAndSF :: HS Threads Dispatched */ +#define sklgt3__hdc_and_sf__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set HDCAndSF :: SLM Bytes Written */ +#define sklgt3__hdc_and_sf__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set HDCAndSF :: L3 Shader Throughput */ +#define sklgt3__hdc_and_sf__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set HDCAndSF :: Samples Killed in FS */ +#define sklgt3__hdc_and_sf__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */ +#define sklgt3__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read \ + bdw__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read + +/* Metric set HDCAndSF :: Shader Atomic Memory Accesses */ +#define sklgt3__hdc_and_sf__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set L3_1 :: GPU Core Clocks */ +#define sklgt3__l3_1__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set L3_1 :: EU Active */ +#define sklgt3__l3_1__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set L3_1 :: Slice0 L3 Bank1 Active */ +#define sklgt3__l3_1__l30_bank1_active__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set L3_1 :: EU Both FPU Pipes Active */ +#define sklgt3__l3_1__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set L3_1 :: VS Send Pipe Active */ +#define sklgt3__l3_1__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set L3_1 :: VS FPU1 Pipe Active */ +#define sklgt3__l3_1__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set L3_1 :: GS Threads Dispatched */ +#define sklgt3__l3_1__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set L3_1 :: Early Hi-Depth Test Fails */ +#define sklgt3__l3_1__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set L3_1 :: FS Both FPU Active */ +#define sklgt3__l3_1__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set L3_1 :: VS Threads Dispatched */ +#define sklgt3__l3_1__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set L3_1 :: Slice0 L3 Bank1 Stalled */ +#define sklgt3__l3_1__l30_bank1_stalled__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Metric set L3_1 :: FS Threads Dispatched */ +#define sklgt3__l3_1__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set L3_1 :: Shader Barrier Messages */ +#define sklgt3__l3_1__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set L3_1 :: Sampler Texels */ +#define sklgt3__l3_1__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set L3_1 :: Pixels Failing Tests */ +#define sklgt3__l3_1__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set L3_1 :: GPU Time Elapsed */ +#define sklgt3__l3_1__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set L3_1 :: AVG GPU Core Frequency */ +#define sklgt3__l3_1__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set L3_1 :: AVG GPU Core Frequency */ +#define sklgt3__l3_1__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set L3_1 :: Sampler Texels Misses */ +#define sklgt3__l3_1__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set L3_1 :: CS Threads Dispatched */ +#define sklgt3__l3_1__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set L3_1 :: SLM Bytes Read */ +#define sklgt3__l3_1__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set L3_1 :: PS FPU1 Pipe Active */ +#define sklgt3__l3_1__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set L3_1 :: PS Send Pipeline Active */ +#define sklgt3__l3_1__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set L3_1 :: VS FPU0 Pipe Active */ +#define sklgt3__l3_1__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set L3_1 :: GPU Busy */ +#define sklgt3__l3_1__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set L3_1 :: Slice0 L3 Bank0 Active */ +#define sklgt3__l3_1__l30_bank0_active__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set L3_1 :: Rasterized Pixels */ +#define sklgt3__l3_1__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set L3_1 :: PS FPU0 Pipe Active */ +#define sklgt3__l3_1__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set L3_1 :: Slice0 L3 Bank0 Stalled */ +#define sklgt3__l3_1__l30_bank0_stalled__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set L3_1 :: DS Threads Dispatched */ +#define sklgt3__l3_1__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set L3_1 :: Samples Written */ +#define sklgt3__l3_1__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set L3_1 :: EU Stall */ +#define sklgt3__l3_1__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set L3_1 :: Samples Blended */ +#define sklgt3__l3_1__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set L3_1 :: Early Depth Test Fails */ +#define sklgt3__l3_1__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set L3_1 :: Shader Memory Accesses */ +#define sklgt3__l3_1__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set L3_1 :: HS Threads Dispatched */ +#define sklgt3__l3_1__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set L3_1 :: SLM Bytes Written */ +#define sklgt3__l3_1__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set L3_1 :: L3 Shader Throughput */ +#define sklgt3__l3_1__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set L3_1 :: Samples Killed in FS */ +#define sklgt3__l3_1__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set L3_1 :: Shader Atomic Memory Accesses */ +#define sklgt3__l3_1__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set L3_2 :: GPU Core Clocks */ +#define sklgt3__l3_2__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set L3_2 :: EU Active */ +#define sklgt3__l3_2__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set L3_2 :: EU Both FPU Pipes Active */ +#define sklgt3__l3_2__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set L3_2 :: VS Send Pipe Active */ +#define sklgt3__l3_2__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set L3_2 :: VS FPU1 Pipe Active */ +#define sklgt3__l3_2__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set L3_2 :: GS Threads Dispatched */ +#define sklgt3__l3_2__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set L3_2 :: Early Hi-Depth Test Fails */ +#define sklgt3__l3_2__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set L3_2 :: FS Both FPU Active */ +#define sklgt3__l3_2__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set L3_2 :: VS Threads Dispatched */ +#define sklgt3__l3_2__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set L3_2 :: FS Threads Dispatched */ +#define sklgt3__l3_2__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set L3_2 :: Shader Barrier Messages */ +#define sklgt3__l3_2__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set L3_2 :: Sampler Texels */ +#define sklgt3__l3_2__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set L3_2 :: Pixels Failing Tests */ +#define sklgt3__l3_2__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set L3_2 :: GPU Time Elapsed */ +#define sklgt3__l3_2__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set L3_2 :: AVG GPU Core Frequency */ +#define sklgt3__l3_2__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set L3_2 :: AVG GPU Core Frequency */ +#define sklgt3__l3_2__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set L3_2 :: Sampler Texels Misses */ +#define sklgt3__l3_2__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set L3_2 :: CS Threads Dispatched */ +#define sklgt3__l3_2__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set L3_2 :: SLM Bytes Read */ +#define sklgt3__l3_2__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set L3_2 :: PS FPU1 Pipe Active */ +#define sklgt3__l3_2__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set L3_2 :: Slice0 L3 Bank2 Stalled */ +#define sklgt3__l3_2__l30_bank2_stalled__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set L3_2 :: PS Send Pipeline Active */ +#define sklgt3__l3_2__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set L3_2 :: VS FPU0 Pipe Active */ +#define sklgt3__l3_2__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set L3_2 :: GPU Busy */ +#define sklgt3__l3_2__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set L3_2 :: Slice0 L3 Bank2 Active */ +#define sklgt3__l3_2__l30_bank2_active__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set L3_2 :: Rasterized Pixels */ +#define sklgt3__l3_2__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set L3_2 :: PS FPU0 Pipe Active */ +#define sklgt3__l3_2__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set L3_2 :: DS Threads Dispatched */ +#define sklgt3__l3_2__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set L3_2 :: Samples Written */ +#define sklgt3__l3_2__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set L3_2 :: EU Stall */ +#define sklgt3__l3_2__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set L3_2 :: Samples Blended */ +#define sklgt3__l3_2__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set L3_2 :: Early Depth Test Fails */ +#define sklgt3__l3_2__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set L3_2 :: Shader Memory Accesses */ +#define sklgt3__l3_2__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set L3_2 :: HS Threads Dispatched */ +#define sklgt3__l3_2__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set L3_2 :: SLM Bytes Written */ +#define sklgt3__l3_2__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set L3_2 :: L3 Shader Throughput */ +#define sklgt3__l3_2__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set L3_2 :: Samples Killed in FS */ +#define sklgt3__l3_2__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set L3_2 :: Shader Atomic Memory Accesses */ +#define sklgt3__l3_2__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set L3_3 :: GPU Core Clocks */ +#define sklgt3__l3_3__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set L3_3 :: EU Active */ +#define sklgt3__l3_3__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set L3_3 :: EU Both FPU Pipes Active */ +#define sklgt3__l3_3__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set L3_3 :: VS Send Pipe Active */ +#define sklgt3__l3_3__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set L3_3 :: VS FPU1 Pipe Active */ +#define sklgt3__l3_3__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set L3_3 :: GS Threads Dispatched */ +#define sklgt3__l3_3__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set L3_3 :: Early Hi-Depth Test Fails */ +#define sklgt3__l3_3__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set L3_3 :: FS Both FPU Active */ +#define sklgt3__l3_3__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set L3_3 :: VS Threads Dispatched */ +#define sklgt3__l3_3__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set L3_3 :: FS Threads Dispatched */ +#define sklgt3__l3_3__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set L3_3 :: Slice0 L3 Bank3 Stalled */ +#define sklgt3__l3_3__l30_bank3_stalled__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set L3_3 :: Shader Barrier Messages */ +#define sklgt3__l3_3__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set L3_3 :: Sampler Texels */ +#define sklgt3__l3_3__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set L3_3 :: Pixels Failing Tests */ +#define sklgt3__l3_3__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set L3_3 :: GPU Time Elapsed */ +#define sklgt3__l3_3__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set L3_3 :: AVG GPU Core Frequency */ +#define sklgt3__l3_3__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set L3_3 :: AVG GPU Core Frequency */ +#define sklgt3__l3_3__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set L3_3 :: Sampler Texels Misses */ +#define sklgt3__l3_3__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set L3_3 :: CS Threads Dispatched */ +#define sklgt3__l3_3__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set L3_3 :: SLM Bytes Read */ +#define sklgt3__l3_3__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set L3_3 :: PS FPU1 Pipe Active */ +#define sklgt3__l3_3__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set L3_3 :: Slice0 L3 Bank3 Active */ +#define sklgt3__l3_3__l30_bank3_active__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set L3_3 :: PS Send Pipeline Active */ +#define sklgt3__l3_3__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set L3_3 :: VS FPU0 Pipe Active */ +#define sklgt3__l3_3__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set L3_3 :: GPU Busy */ +#define sklgt3__l3_3__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set L3_3 :: Rasterized Pixels */ +#define sklgt3__l3_3__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set L3_3 :: PS FPU0 Pipe Active */ +#define sklgt3__l3_3__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set L3_3 :: DS Threads Dispatched */ +#define sklgt3__l3_3__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set L3_3 :: Samples Written */ +#define sklgt3__l3_3__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set L3_3 :: EU Stall */ +#define sklgt3__l3_3__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set L3_3 :: Samples Blended */ +#define sklgt3__l3_3__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set L3_3 :: Early Depth Test Fails */ +#define sklgt3__l3_3__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set L3_3 :: Shader Memory Accesses */ +#define sklgt3__l3_3__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set L3_3 :: HS Threads Dispatched */ +#define sklgt3__l3_3__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set L3_3 :: SLM Bytes Written */ +#define sklgt3__l3_3__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set L3_3 :: L3 Shader Throughput */ +#define sklgt3__l3_3__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set L3_3 :: Samples Killed in FS */ +#define sklgt3__l3_3__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set L3_3 :: Shader Atomic Memory Accesses */ +#define sklgt3__l3_3__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */ +#define sklgt3__rasterizer_and_pixel_backend__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set RasterizerAndPixelBackend :: EU Active */ +#define sklgt3__rasterizer_and_pixel_backend__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set RasterizerAndPixelBackend :: EU Both FPU Pipes Active */ +#define sklgt3__rasterizer_and_pixel_backend__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set RasterizerAndPixelBackend :: VS Send Pipe Active */ +#define sklgt3__rasterizer_and_pixel_backend__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set RasterizerAndPixelBackend :: VS FPU1 Pipe Active */ +#define sklgt3__rasterizer_and_pixel_backend__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */ +#define sklgt3__rasterizer_and_pixel_backend__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */ +#define sklgt3__rasterizer_and_pixel_backend__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set RasterizerAndPixelBackend :: FS Both FPU Active */ +#define sklgt3__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */ +#define sklgt3__rasterizer_and_pixel_backend__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */ +#define sklgt3__rasterizer_and_pixel_backend__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Pixel Values Ready */ +#define sklgt3__rasterizer_and_pixel_backend__pixel_values0_ready__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */ +#define sklgt3__rasterizer_and_pixel_backend__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set RasterizerAndPixelBackend :: Sampler Texels */ +#define sklgt3__rasterizer_and_pixel_backend__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */ +#define sklgt3__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */ +#define sklgt3__rasterizer_and_pixel_backend__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ +#define sklgt3__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ +#define sklgt3__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */ +#define sklgt3__rasterizer_and_pixel_backend__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */ +#define sklgt3__rasterizer_and_pixel_backend__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */ +#define sklgt3__rasterizer_and_pixel_backend__rasterizer0_input_available__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Post-EarlyZ Pixel Data Ready */ +#define sklgt3__rasterizer_and_pixel_backend__pixel_data0_ready__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */ +#define sklgt3__rasterizer_and_pixel_backend__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set RasterizerAndPixelBackend :: PS FPU1 Pipe Active */ +#define sklgt3__rasterizer_and_pixel_backend__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set RasterizerAndPixelBackend :: PS Send Pipeline Active */ +#define sklgt3__rasterizer_and_pixel_backend__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set RasterizerAndPixelBackend :: VS FPU0 Pipe Active */ +#define sklgt3__rasterizer_and_pixel_backend__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set RasterizerAndPixelBackend :: GPU Busy */ +#define sklgt3__rasterizer_and_pixel_backend__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */ +#define sklgt3__rasterizer_and_pixel_backend__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set RasterizerAndPixelBackend :: PS FPU0 Pipe Active */ +#define sklgt3__rasterizer_and_pixel_backend__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */ +#define sklgt3__rasterizer_and_pixel_backend__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set RasterizerAndPixelBackend :: Samples Written */ +#define sklgt3__rasterizer_and_pixel_backend__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set RasterizerAndPixelBackend :: EU Stall */ +#define sklgt3__rasterizer_and_pixel_backend__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */ +#define sklgt3__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set RasterizerAndPixelBackend :: Samples Blended */ +#define sklgt3__rasterizer_and_pixel_backend__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */ +#define sklgt3__rasterizer_and_pixel_backend__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */ +#define sklgt3__rasterizer_and_pixel_backend__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */ +#define sklgt3__rasterizer_and_pixel_backend__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */ +#define sklgt3__rasterizer_and_pixel_backend__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */ +#define sklgt3__rasterizer_and_pixel_backend__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */ +#define sklgt3__rasterizer_and_pixel_backend__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 PS Output Available */ +#define sklgt3__rasterizer_and_pixel_backend__ps_output0_available__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */ +#define sklgt3__rasterizer_and_pixel_backend__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set Sampler :: GPU Core Clocks */ +#define sklgt3__sampler__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set Sampler :: EU Active */ +#define sklgt3__sampler__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set Sampler :: Slice0 Subslice2 Input Available */ +#define sklgt3__sampler__sampler02_input_available__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set Sampler :: EU Both FPU Pipes Active */ +#define sklgt3__sampler__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set Sampler :: VS Send Pipe Active */ +#define sklgt3__sampler__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set Sampler :: Slice0 Subslice0 Input Available */ +#define sklgt3__sampler__sampler00_input_available__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Metric set Sampler :: VS FPU1 Pipe Active */ +#define sklgt3__sampler__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set Sampler :: GS Threads Dispatched */ +#define sklgt3__sampler__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set Sampler :: Early Hi-Depth Test Fails */ +#define sklgt3__sampler__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set Sampler :: FS Both FPU Active */ +#define sklgt3__sampler__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set Sampler :: VS Threads Dispatched */ +#define sklgt3__sampler__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set Sampler :: Slice0 Subslice2 Sampler Output Ready */ +#define sklgt3__sampler__sampler02_output_ready__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set Sampler :: FS Threads Dispatched */ +#define sklgt3__sampler__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set Sampler :: Shader Barrier Messages */ +#define sklgt3__sampler__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set Sampler :: Slice0 Subslice1 Input Available */ +#define sklgt3__sampler__sampler01_input_available__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set Sampler :: Sampler Texels */ +#define sklgt3__sampler__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set Sampler :: Pixels Failing Tests */ +#define sklgt3__sampler__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set Sampler :: GPU Time Elapsed */ +#define sklgt3__sampler__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set Sampler :: AVG GPU Core Frequency */ +#define sklgt3__sampler__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set Sampler :: AVG GPU Core Frequency */ +#define sklgt3__sampler__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set Sampler :: Sampler Texels Misses */ +#define sklgt3__sampler__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set Sampler :: CS Threads Dispatched */ +#define sklgt3__sampler__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set Sampler :: SLM Bytes Read */ +#define sklgt3__sampler__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set Sampler :: PS FPU1 Pipe Active */ +#define sklgt3__sampler__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set Sampler :: PS Send Pipeline Active */ +#define sklgt3__sampler__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set Sampler :: VS FPU0 Pipe Active */ +#define sklgt3__sampler__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set Sampler :: GPU Busy */ +#define sklgt3__sampler__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set Sampler :: Rasterized Pixels */ +#define sklgt3__sampler__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set Sampler :: PS FPU0 Pipe Active */ +#define sklgt3__sampler__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set Sampler :: DS Threads Dispatched */ +#define sklgt3__sampler__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set Sampler :: Samples Written */ +#define sklgt3__sampler__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set Sampler :: EU Stall */ +#define sklgt3__sampler__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set Sampler :: Samples Blended */ +#define sklgt3__sampler__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set Sampler :: Early Depth Test Fails */ +#define sklgt3__sampler__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set Sampler :: Slice0 Subslice0 Sampler Output Ready */ +#define sklgt3__sampler__sampler00_output_ready__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set Sampler :: Slice0 Subslice1 Sampler Output Ready */ +#define sklgt3__sampler__sampler01_output_ready__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set Sampler :: Shader Memory Accesses */ +#define sklgt3__sampler__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set Sampler :: HS Threads Dispatched */ +#define sklgt3__sampler__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set Sampler :: SLM Bytes Written */ +#define sklgt3__sampler__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set Sampler :: L3 Shader Throughput */ +#define sklgt3__sampler__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set Sampler :: Samples Killed in FS */ +#define sklgt3__sampler__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set Sampler :: Shader Atomic Memory Accesses */ +#define sklgt3__sampler__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set TDL_1 :: GPU Core Clocks */ +#define sklgt3__tdl_1__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set TDL_1 :: EU Active */ +#define sklgt3__tdl_1__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set TDL_1 :: EU Both FPU Pipes Active */ +#define sklgt3__tdl_1__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set TDL_1 :: VS Send Pipe Active */ +#define sklgt3__tdl_1__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set TDL_1 :: VS FPU1 Pipe Active */ +#define sklgt3__tdl_1__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set TDL_1 :: GS Threads Dispatched */ +#define sklgt3__tdl_1__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set TDL_1 :: Early Hi-Depth Test Fails */ +#define sklgt3__tdl_1__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set TDL_1 :: FS Both FPU Active */ +#define sklgt3__tdl_1__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set TDL_1 :: VS Threads Dispatched */ +#define sklgt3__tdl_1__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set TDL_1 :: FS Threads Dispatched */ +#define sklgt3__tdl_1__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice2 */ +#define sklgt3__tdl_1__non_ps_thread02_ready_for_dispatch__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Metric set TDL_1 :: Shader Barrier Messages */ +#define sklgt3__tdl_1__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_1 :: Sampler Texels */ +#define sklgt3__tdl_1__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set TDL_1 :: Pixels Failing Tests */ +#define sklgt3__tdl_1__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set TDL_1 :: GPU Time Elapsed */ +#define sklgt3__tdl_1__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set TDL_1 :: AVG GPU Core Frequency */ +#define sklgt3__tdl_1__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set TDL_1 :: AVG GPU Core Frequency */ +#define sklgt3__tdl_1__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set TDL_1 :: Sampler Texels Misses */ +#define sklgt3__tdl_1__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice0 */ +#define sklgt3__tdl_1__non_ps_thread00_ready_for_dispatch__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Metric set TDL_1 :: CS Threads Dispatched */ +#define sklgt3__tdl_1__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set TDL_1 :: SLM Bytes Read */ +#define sklgt3__tdl_1__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set TDL_1 :: PS FPU1 Pipe Active */ +#define sklgt3__tdl_1__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set TDL_1 :: PS Send Pipeline Active */ +#define sklgt3__tdl_1__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set TDL_1 :: VS FPU0 Pipe Active */ +#define sklgt3__tdl_1__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set TDL_1 :: GPU Busy */ +#define sklgt3__tdl_1__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice0 */ +#define sklgt3__tdl_1__ps_thread00_ready_for_dispatch__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set TDL_1 :: Rasterized Pixels */ +#define sklgt3__tdl_1__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set TDL_1 :: PS FPU0 Pipe Active */ +#define sklgt3__tdl_1__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set TDL_1 :: DS Threads Dispatched */ +#define sklgt3__tdl_1__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set TDL_1 :: Samples Written */ +#define sklgt3__tdl_1__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set TDL_1 :: EU Stall */ +#define sklgt3__tdl_1__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set TDL_1 :: Samples Blended */ +#define sklgt3__tdl_1__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set TDL_1 :: Early Depth Test Fails */ +#define sklgt3__tdl_1__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice1 */ +#define sklgt3__tdl_1__ps_thread01_ready_for_dispatch__read \ + bdw__render_pipe_profile__cl_bottleneck__read + +/* Metric set TDL_1 :: Shader Memory Accesses */ +#define sklgt3__tdl_1__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set TDL_1 :: HS Threads Dispatched */ +#define sklgt3__tdl_1__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice2 */ +#define sklgt3__tdl_1__ps_thread02_ready_for_dispatch__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Metric set TDL_1 :: SLM Bytes Written */ +#define sklgt3__tdl_1__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set TDL_1 :: L3 Shader Throughput */ +#define sklgt3__tdl_1__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set TDL_1 :: Samples Killed in FS */ +#define sklgt3__tdl_1__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set TDL_1 :: Shader Atomic Memory Accesses */ +#define sklgt3__tdl_1__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice1 */ +#define sklgt3__tdl_1__non_ps_thread01_ready_for_dispatch__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set TDL_2 :: GPU Core Clocks */ +#define sklgt3__tdl_2__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set TDL_2 :: EU Active */ +#define sklgt3__tdl_2__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set TDL_2 :: EU Both FPU Pipes Active */ +#define sklgt3__tdl_2__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set TDL_2 :: VS Send Pipe Active */ +#define sklgt3__tdl_2__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set TDL_2 :: VS FPU1 Pipe Active */ +#define sklgt3__tdl_2__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set TDL_2 :: GS Threads Dispatched */ +#define sklgt3__tdl_2__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set TDL_2 :: Early Hi-Depth Test Fails */ +#define sklgt3__tdl_2__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set TDL_2 :: FS Both FPU Active */ +#define sklgt3__tdl_2__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set TDL_2 :: VS Threads Dispatched */ +#define sklgt3__tdl_2__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set TDL_2 :: FS Threads Dispatched */ +#define sklgt3__tdl_2__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set TDL_2 :: Shader Barrier Messages */ +#define sklgt3__tdl_2__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_2 :: Sampler Texels */ +#define sklgt3__tdl_2__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set TDL_2 :: Pixels Failing Tests */ +#define sklgt3__tdl_2__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 0 */ +#define sklgt3__tdl_2__thread_header01_ready_port0__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 1 */ +#define sklgt3__tdl_2__thread_header01_ready_port1__read \ + bdw__render_pipe_profile__ds_stall__read + +/* Metric set TDL_2 :: GPU Time Elapsed */ +#define sklgt3__tdl_2__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set TDL_2 :: AVG GPU Core Frequency */ +#define sklgt3__tdl_2__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set TDL_2 :: AVG GPU Core Frequency */ +#define sklgt3__tdl_2__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set TDL_2 :: Sampler Texels Misses */ +#define sklgt3__tdl_2__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set TDL_2 :: CS Threads Dispatched */ +#define sklgt3__tdl_2__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set TDL_2 :: SLM Bytes Read */ +#define sklgt3__tdl_2__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set TDL_2 :: PS FPU1 Pipe Active */ +#define sklgt3__tdl_2__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set TDL_2 :: PS Send Pipeline Active */ +#define sklgt3__tdl_2__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set TDL_2 :: VS FPU0 Pipe Active */ +#define sklgt3__tdl_2__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set TDL_2 :: GPU Busy */ +#define sklgt3__tdl_2__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 1 */ +#define sklgt3__tdl_2__thread_header02_ready_port1__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 0 */ +#define sklgt3__tdl_2__thread_header02_ready_port0__read \ + bdw__render_pipe_profile__so_stall__read + +/* Metric set TDL_2 :: Rasterized Pixels */ +#define sklgt3__tdl_2__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set TDL_2 :: PS FPU0 Pipe Active */ +#define sklgt3__tdl_2__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set TDL_2 :: DS Threads Dispatched */ +#define sklgt3__tdl_2__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set TDL_2 :: Samples Written */ +#define sklgt3__tdl_2__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set TDL_2 :: EU Stall */ +#define sklgt3__tdl_2__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set TDL_2 :: Samples Blended */ +#define sklgt3__tdl_2__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set TDL_2 :: Early Depth Test Fails */ +#define sklgt3__tdl_2__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_2 :: Shader Memory Accesses */ +#define sklgt3__tdl_2__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set TDL_2 :: HS Threads Dispatched */ +#define sklgt3__tdl_2__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set TDL_2 :: SLM Bytes Written */ +#define sklgt3__tdl_2__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set TDL_2 :: L3 Shader Throughput */ +#define sklgt3__tdl_2__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set TDL_2 :: Samples Killed in FS */ +#define sklgt3__tdl_2__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 0 */ +#define sklgt3__tdl_2__thread_header00_ready_port0__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set TDL_2 :: Shader Atomic Memory Accesses */ +#define sklgt3__tdl_2__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 1 */ +#define sklgt3__tdl_2__thread_header00_ready_port1__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Compute Metrics Extra Gen9 :: GPU Core Clocks */ +#define sklgt3__compute_extra__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Extra Gen9 :: EU FPU1 Pipe Active */ +#define sklgt3__compute_extra__fpu1_active__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics Extra Gen9 :: GPU Time Elapsed */ +#define sklgt3__compute_extra__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics Extra Gen9 :: AVG GPU Core Frequency */ +#define sklgt3__compute_extra__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics Extra Gen9 :: AVG GPU Core Frequency */ +#define sklgt3__compute_extra__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics Extra Gen9 :: EU FPU1 Pipe Active including Ext Math */ +#define sklgt3__compute_extra__fpu1_active_adjusted__read \ + bdw__compute_extra__fpu1_active_adjusted__read + +/* Media Vme Pipe Gen9 :: GPU Core Clocks */ +#define sklgt3__vme_pipe__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Media Vme Pipe Gen9 :: EU Active */ +#define sklgt3__vme_pipe__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Media Vme Pipe Gen9 :: EU Both FPU Pipes Active */ +#define sklgt3__vme_pipe__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Media Vme Pipe Gen9 :: GPU Time Elapsed */ +#define sklgt3__vme_pipe__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Media Vme Pipe Gen9 :: AVG GPU Core Frequency */ +#define sklgt3__vme_pipe__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Media Vme Pipe Gen9 :: AVG GPU Core Frequency */ +#define sklgt3__vme_pipe__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Media Vme Pipe Gen9 :: CS Threads Dispatched */ +#define sklgt3__vme_pipe__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Media Vme Pipe Gen9 :: EU Thread Occupancy */ +#define sklgt3__vme_pipe__eu_thread_occupancy__read \ + bdw__vme_pipe__eu_thread_occupancy__read + +/* Media Vme Pipe Gen9 :: EU Stall */ +#define sklgt3__vme_pipe__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Media Vme Pipe Gen9 :: VME Busy */ +#define sklgt3__vme_pipe__vme_busy__read \ + bdw__vme_pipe__vme_busy__read + +/* Media Vme Pipe Gen9 :: GPU Busy */ +#define sklgt3__vme_pipe__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Gpu Rings Busyness :: GPU Core Clocks */ +#define sklgt3__gpu_busyness__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Gpu Rings Busyness :: Vebox Ring Busy */ +#define sklgt3__gpu_busyness__vebox_busy__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Gpu Rings Busyness :: GPU Time Elapsed */ +#define sklgt3__gpu_busyness__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Gpu Rings Busyness :: AVG GPU Core Frequency */ +#define sklgt3__gpu_busyness__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Gpu Rings Busyness :: AVG GPU Core Frequency */ +#define sklgt3__gpu_busyness__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Gpu Rings Busyness :: Render Ring Busy */ +#define sklgt3__gpu_busyness__render_busy__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Gpu Rings Busyness :: Vdbox0 Ring Busy */ +#define sklgt3__gpu_busyness__vdbox0_busy__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Gpu Rings Busyness :: Blitter Ring Busy */ +#define sklgt3__gpu_busyness__blitter_busy__read \ + bdw__render_pipe_profile__so_stall__read + +/* Gpu Rings Busyness :: AnyRingBusy */ +#define sklgt3__gpu_busyness__any_ring_busy__read \ + bdw__render_basic__sampler0_busy__read + +/* Gpu Rings Busyness :: Vdbox1 Ring Busy */ +#define sklgt3__gpu_busyness__vdbox1_busy__read \ + bdw__render_pipe_profile__sf_stall__read + +/* MDAPI testing set Gen9 :: TestCounter7 */ +#define sklgt3__test_oa__counter7__read \ + hsw__compute_extended__gpu_clocks__read + +/* MDAPI testing set Gen9 :: GPU Time Elapsed */ +#define sklgt3__test_oa__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* MDAPI testing set Gen9 :: GPU Core Clocks */ +#define sklgt3__test_oa__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* MDAPI testing set Gen9 :: AVG GPU Core Frequency */ +#define sklgt3__test_oa__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* MDAPI testing set Gen9 :: AVG GPU Core Frequency */ +#define sklgt3__test_oa__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* MDAPI testing set Gen9 :: TestCounter8 */ +#define sklgt3__test_oa__counter8__read \ + hsw__memory_reads__gpu_core_clocks__read + +/* MDAPI testing set Gen9 :: TestCounter4 */ +#define sklgt3__test_oa__counter4__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* MDAPI testing set Gen9 :: TestCounter5 */ +#define sklgt3__test_oa__counter5__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* MDAPI testing set Gen9 :: TestCounter6 */ +#define sklgt3__test_oa__counter6__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* MDAPI testing set Gen9 :: TestCounter3 */ +#define sklgt3__test_oa__counter3__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* MDAPI testing set Gen9 :: TestCounter0 */ +#define sklgt3__test_oa__counter0__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* MDAPI testing set Gen9 :: TestCounter1 */ +#define sklgt3__test_oa__counter1__read \ + hsw__compute_extended__eu_untyped_writes0__read + +/* MDAPI testing set Gen9 :: TestCounter2 */ +#define sklgt3__test_oa__counter2__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Render Metrics Basic Gen9 :: GPU Core Clocks */ +#define sklgt4__render_basic__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Render Metrics Basic Gen9 :: EU Active */ +#define sklgt4__render_basic__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Render Metrics Basic Gen9 :: L3 Misses */ +#define sklgt4__render_basic__l3_misses__read \ + hsw__compute_extended__typed_atomics0__read + +/* Render Metrics Basic Gen9 :: GTI L3 Throughput */ +#define sklgt4__render_basic__gti_l3_throughput__read \ + hsw__render_basic__gti_l3_throughput__read + +/* Render Metrics Basic Gen9 :: EU Both FPU Pipes Active */ +#define sklgt4__render_basic__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Render Metrics Basic Gen9 :: Sampler Cache Misses */ +static uint64_t +sklgt4__render_basic__sampler_l1_misses__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 4 READ B 5 READ UADD B 3 READ UADD 8 UMUL */ + uint64_t tmp0 = accumulator[query->b_offset + 4]; + uint64_t tmp1 = accumulator[query->b_offset + 5]; + uint64_t tmp2 = tmp0 + tmp1; + uint64_t tmp3 = accumulator[query->b_offset + 3]; + uint64_t tmp4 = tmp2 + tmp3; + uint64_t tmp5 = tmp4 * 8; + + return tmp5; +} + +/* Render Metrics Basic Gen9 :: VS Send Pipe Active */ +#define sklgt4__render_basic__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Render Metrics Basic Gen9 :: VS FPU1 Pipe Active */ +#define sklgt4__render_basic__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Render Metrics Basic Gen9 :: GS Threads Dispatched */ +#define sklgt4__render_basic__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Render Metrics Basic Gen9 :: L3 Sampler Throughput */ +static uint64_t +sklgt4__render_basic__l3_sampler_throughput__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $SamplerL1Misses 64 UMUL */ + uint64_t tmp0 = sklgt4__render_basic__sampler_l1_misses__read(brw, query, accumulator) * 64; + + return tmp0; +} + +/* Render Metrics Basic Gen9 :: Early Hi-Depth Test Fails */ +#define sklgt4__render_basic__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Render Metrics Basic Gen9 :: FS Both FPU Active */ +#define sklgt4__render_basic__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Render Metrics Basic Gen9 :: VS Threads Dispatched */ +#define sklgt4__render_basic__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Render Metrics Basic Gen9 :: FS Threads Dispatched */ +#define sklgt4__render_basic__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Render Metrics Basic Gen9 :: Sampler 0 Busy */ +#define sklgt4__render_basic__sampler0_busy__read \ + bdw__render_basic__sampler0_busy__read + +/* Render Metrics Basic Gen9 :: Sampler 1 Busy */ +#define sklgt4__render_basic__sampler1_busy__read \ + bdw__render_basic__sampler1_busy__read + +/* Render Metrics Basic Gen9 :: Samplers Busy */ +#define sklgt4__render_basic__samplers_busy__read \ + bdw__render_basic__samplers_busy__read + +/* Render Metrics Basic Gen9 :: GTI Fixed Pipe Throughput */ +#define sklgt4__render_basic__gti_vf_throughput__read \ + bdw__render_basic__gti_vf_throughput__read + +/* Render Metrics Basic Gen9 :: Shader Barrier Messages */ +#define sklgt4__render_basic__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Render Metrics Basic Gen9 :: Sampler 0 Bottleneck */ +#define sklgt4__render_basic__sampler0_bottleneck__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Render Metrics Basic Gen9 :: Sampler Texels */ +#define sklgt4__render_basic__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Render Metrics Basic Gen9 :: Pixels Failing Tests */ +#define sklgt4__render_basic__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Render Metrics Basic Gen9 :: GPU Time Elapsed */ +#define sklgt4__render_basic__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Render Metrics Basic Gen9 :: AVG GPU Core Frequency */ +#define sklgt4__render_basic__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Render Metrics Basic Gen9 :: AVG GPU Core Frequency */ +#define sklgt4__render_basic__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Render Metrics Basic Gen9 :: Sampler Texels Misses */ +#define sklgt4__render_basic__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Render Metrics Basic Gen9 :: CS Threads Dispatched */ +#define sklgt4__render_basic__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Render Metrics Basic Gen9 :: Shader Memory Accesses */ +#define sklgt4__render_basic__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Render Metrics Basic Gen9 :: L3 Lookup Accesses w/o IC */ +static uint64_t +sklgt4__render_basic__l3_lookups__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $SamplerL1Misses $ShaderMemoryAccesses UADD */ + uint64_t tmp0 = sklgt4__render_basic__sampler_l1_misses__read(brw, query, accumulator) + sklgt4__render_basic__shader_memory_accesses__read(brw, query, accumulator); + + return tmp0; +} + +/* Render Metrics Basic Gen9 :: SLM Bytes Read */ +#define sklgt4__render_basic__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Render Metrics Basic Gen9 :: GTI Read Throughput */ +#define sklgt4__render_basic__gti_read_throughput__read \ + bdw__render_basic__gti_read_throughput__read + +/* Render Metrics Basic Gen9 :: PS FPU1 Pipe Active */ +#define sklgt4__render_basic__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Render Metrics Basic Gen9 :: PS Send Pipeline Active */ +#define sklgt4__render_basic__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Render Metrics Basic Gen9 :: Rasterized Pixels */ +#define sklgt4__render_basic__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Render Metrics Basic Gen9 :: GPU Busy */ +#define sklgt4__render_basic__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Render Metrics Basic Gen9 :: GTI Depth Throughput */ +#define sklgt4__render_basic__gti_depth_throughput__read \ + bdw__render_basic__gti_depth_throughput__read + +/* Render Metrics Basic Gen9 :: VS FPU0 Pipe Active */ +#define sklgt4__render_basic__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Render Metrics Basic Gen9 :: PS FPU0 Pipe Active */ +#define sklgt4__render_basic__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Render Metrics Basic Gen9 :: DS Threads Dispatched */ +#define sklgt4__render_basic__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Render Metrics Basic Gen9 :: Samples Written */ +#define sklgt4__render_basic__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Render Metrics Basic Gen9 :: EU Stall */ +#define sklgt4__render_basic__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Render Metrics Basic Gen9 :: Samples Blended */ +#define sklgt4__render_basic__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Render Metrics Basic Gen9 :: Early Depth Test Fails */ +#define sklgt4__render_basic__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Render Metrics Basic Gen9 :: Samplers Bottleneck */ +#define sklgt4__render_basic__sampler_bottleneck__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Render Metrics Basic Gen9 :: GTI HDC TLB Lookup Throughput */ +#define sklgt4__render_basic__gti_hdc_lookups_throughput__read \ + bdw__render_basic__gti_hdc_lookups_throughput__read + +/* Render Metrics Basic Gen9 :: GTI RCC Throughput */ +#define sklgt4__render_basic__gti_rcc_throughput__read \ + bdw__render_basic__gti_rcc_throughput__read + +/* Render Metrics Basic Gen9 :: HS Threads Dispatched */ +#define sklgt4__render_basic__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Render Metrics Basic Gen9 :: GTI Write Throughput */ +#define sklgt4__render_basic__gti_write_throughput__read \ + hsw__render_basic__gti_write_throughput__read + +/* Render Metrics Basic Gen9 :: SLM Bytes Written */ +#define sklgt4__render_basic__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Render Metrics Basic Gen9 :: L3 Shader Throughput */ +#define sklgt4__render_basic__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Render Metrics Basic Gen9 :: Samples Killed in FS */ +#define sklgt4__render_basic__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Render Metrics Basic Gen9 :: Shader Atomic Memory Accesses */ +#define sklgt4__render_basic__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Basic Gen9 :: GPU Core Clocks */ +#define sklgt4__compute_basic__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Basic Gen9 :: EU Active */ +#define sklgt4__compute_basic__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Compute Metrics Basic Gen9 :: Untyped Bytes Read */ +#define sklgt4__compute_basic__untyped_bytes_read__read \ + bdw__compute_basic__untyped_bytes_read__read + +/* Compute Metrics Basic Gen9 :: EU Both FPU Pipes Active */ +#define sklgt4__compute_basic__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Compute Metrics Basic Gen9 :: Typed Bytes Written */ +#define sklgt4__compute_basic__typed_bytes_written__read \ + bdw__compute_basic__typed_bytes_written__read + +/* Compute Metrics Basic Gen9 :: EU FPU0 Pipe Active */ +#define sklgt4__compute_basic__fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Compute Metrics Basic Gen9 :: EU FPU1 Pipe Active */ +#define sklgt4__compute_basic__fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Compute Metrics Basic Gen9 :: EU AVG IPC Rate */ +#define sklgt4__compute_basic__eu_avg_ipc_rate__read \ + bdw__compute_basic__eu_avg_ipc_rate__read + +/* Compute Metrics Basic Gen9 :: GS Threads Dispatched */ +#define sklgt4__compute_basic__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Compute Metrics Basic Gen9 :: Early Hi-Depth Test Fails */ +#define sklgt4__compute_basic__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Compute Metrics Basic Gen9 :: VS Threads Dispatched */ +#define sklgt4__compute_basic__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Compute Metrics Basic Gen9 :: FS Threads Dispatched */ +#define sklgt4__compute_basic__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Compute Metrics Basic Gen9 :: Shader Barrier Messages */ +#define sklgt4__compute_basic__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Compute Metrics Basic Gen9 :: Sampler Texels */ +#define sklgt4__compute_basic__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Compute Metrics Basic Gen9 :: Pixels Failing Tests */ +#define sklgt4__compute_basic__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Compute Metrics Basic Gen9 :: GPU Time Elapsed */ +#define sklgt4__compute_basic__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics Basic Gen9 :: AVG GPU Core Frequency */ +#define sklgt4__compute_basic__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics Basic Gen9 :: AVG GPU Core Frequency */ +#define sklgt4__compute_basic__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics Basic Gen9 :: Sampler Texels Misses */ +#define sklgt4__compute_basic__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Compute Metrics Basic Gen9 :: CS Threads Dispatched */ +#define sklgt4__compute_basic__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Compute Metrics Basic Gen9 :: SLM Bytes Read */ +#define sklgt4__compute_basic__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Compute Metrics Basic Gen9 :: GTI Read Throughput */ +#define sklgt4__compute_basic__gti_read_throughput__read \ + hsw__render_basic__gti_l3_throughput__read + +/* Compute Metrics Basic Gen9 :: Untyped Writes */ +#define sklgt4__compute_basic__untyped_bytes_written__read \ + bdw__compute_basic__untyped_bytes_written__read + +/* Compute Metrics Basic Gen9 :: GPU Busy */ +#define sklgt4__compute_basic__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Compute Metrics Basic Gen9 :: Rasterized Pixels */ +#define sklgt4__compute_basic__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Compute Metrics Basic Gen9 :: Typed Bytes Read */ +#define sklgt4__compute_basic__typed_bytes_read__read \ + bdw__compute_basic__typed_bytes_read__read + +/* Compute Metrics Basic Gen9 :: DS Threads Dispatched */ +#define sklgt4__compute_basic__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Compute Metrics Basic Gen9 :: EU Thread Occupancy */ +#define sklgt4__compute_basic__eu_thread_occupancy__read \ + bdw__compute_basic__eu_thread_occupancy__read + +/* Compute Metrics Basic Gen9 :: EU Stall */ +#define sklgt4__compute_basic__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics Basic Gen9 :: Samples Blended */ +#define sklgt4__compute_basic__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Compute Metrics Basic Gen9 :: Early Depth Test Fails */ +#define sklgt4__compute_basic__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Compute Metrics Basic Gen9 :: Shader Memory Accesses */ +#define sklgt4__compute_basic__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Compute Metrics Basic Gen9 :: HS Threads Dispatched */ +#define sklgt4__compute_basic__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Compute Metrics Basic Gen9 :: GTI Write Throughput */ +#define sklgt4__compute_basic__gti_write_throughput__read \ + bdw__render_basic__gti_hdc_lookups_throughput__read + +/* Compute Metrics Basic Gen9 :: SLM Bytes Written */ +#define sklgt4__compute_basic__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Compute Metrics Basic Gen9 :: L3 Shader Throughput */ +#define sklgt4__compute_basic__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Compute Metrics Basic Gen9 :: Samples Killed in FS */ +#define sklgt4__compute_basic__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Compute Metrics Basic Gen9 :: Samples Written */ +#define sklgt4__compute_basic__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Compute Metrics Basic Gen9 :: Shader Atomic Memory Accesses */ +#define sklgt4__compute_basic__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Basic Gen9 :: EU Send Pipe Active */ +#define sklgt4__compute_basic__eu_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Core Clocks */ +#define sklgt4__render_pipe_profile__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: EU Active */ +#define sklgt4__render_pipe_profile__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: VS Bottleneck */ +#define sklgt4__render_pipe_profile__vs_bottleneck__read \ + bdw__render_basic__sampler0_busy__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Hi-Depth Bottleneck */ +#define sklgt4__render_pipe_profile__hi_depth_bottleneck__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GS Bottleneck */ +#define sklgt4__render_pipe_profile__gs_bottleneck__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GS Threads Dispatched */ +#define sklgt4__render_pipe_profile__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Early Hi-Depth Test Fails */ +#define sklgt4__render_pipe_profile__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: VS Threads Dispatched */ +#define sklgt4__render_pipe_profile__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: FS Threads Dispatched */ +#define sklgt4__render_pipe_profile__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: BC Bottleneck */ +#define sklgt4__render_pipe_profile__bc_bottleneck__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: HS Stall */ +#define sklgt4__render_pipe_profile__hs_stall__read \ + bdw__render_pipe_profile__hs_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Barrier Messages */ +#define sklgt4__render_pipe_profile__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Sampler Texels */ +#define sklgt4__render_pipe_profile__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Pixels Failing Tests */ +#define sklgt4__render_pipe_profile__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Time Elapsed */ +#define sklgt4__render_pipe_profile__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: AVG GPU Core Frequency */ +#define sklgt4__render_pipe_profile__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: AVG GPU Core Frequency */ +#define sklgt4__render_pipe_profile__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Sampler Texels Misses */ +#define sklgt4__render_pipe_profile__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: CS Threads Dispatched */ +#define sklgt4__render_pipe_profile__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: VF Bottleneck */ +#define sklgt4__render_pipe_profile__vf_bottleneck__read \ + bdw__render_pipe_profile__vf_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SLM Bytes Read */ +#define sklgt4__render_pipe_profile__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Strip-Fans Bottleneck */ +#define sklgt4__render_pipe_profile__sf_bottleneck__read \ + bdw__render_pipe_profile__sf_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SF Stall */ +#define sklgt4__render_pipe_profile__sf_stall__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Busy */ +#define sklgt4__render_pipe_profile__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: HS Bottleneck */ +#define sklgt4__render_pipe_profile__hs_bottleneck__read \ + bdw__render_basic__sampler1_busy__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: CL Stall */ +#define sklgt4__render_pipe_profile__cl_stall__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SO Bottleneck */ +#define sklgt4__render_pipe_profile__so_bottleneck__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Rasterized Pixels */ +#define sklgt4__render_pipe_profile__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: DS Threads Dispatched */ +#define sklgt4__render_pipe_profile__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Written */ +#define sklgt4__render_pipe_profile__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: DS Bottleneck */ +#define sklgt4__render_pipe_profile__ds_bottleneck__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: EU Stall */ +#define sklgt4__render_pipe_profile__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Clipper Bottleneck */ +#define sklgt4__render_pipe_profile__cl_bottleneck__read \ + bdw__render_pipe_profile__cl_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: DS Stall */ +#define sklgt4__render_pipe_profile__ds_stall__read \ + bdw__render_pipe_profile__ds_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Early Depth Bottleneck */ +#define sklgt4__render_pipe_profile__early_depth_bottleneck__read \ + bdw__render_pipe_profile__early_depth_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Blended */ +#define sklgt4__render_pipe_profile__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Early Depth Test Fails */ +#define sklgt4__render_pipe_profile__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Memory Accesses */ +#define sklgt4__render_pipe_profile__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: HS Threads Dispatched */ +#define sklgt4__render_pipe_profile__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SLM Bytes Written */ +#define sklgt4__render_pipe_profile__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: L3 Shader Throughput */ +#define sklgt4__render_pipe_profile__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Killed in FS */ +#define sklgt4__render_pipe_profile__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SO Stall */ +#define sklgt4__render_pipe_profile__so_stall__read \ + bdw__render_pipe_profile__so_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Atomic Memory Accesses */ +#define sklgt4__render_pipe_profile__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Memory Reads Distribution Gen9 :: GPU Core Clocks */ +#define sklgt4__memory_reads__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Memory Reads Distribution Gen9 :: EU Active */ +#define sklgt4__memory_reads__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Memory Reads Distribution Gen9 :: GtiL3Bank0Reads */ +#define sklgt4__memory_reads__gti_l3_bank0_reads__read \ + hsw__compute_extended__typed_atomics0__read + +/* Memory Reads Distribution Gen9 :: GS Threads Dispatched */ +#define sklgt4__memory_reads__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Memory Reads Distribution Gen9 :: GtiRingAccesses */ +#define sklgt4__memory_reads__gti_ring_accesses__read \ + bdw__memory_reads__gti_ring_accesses__read + +/* Memory Reads Distribution Gen9 :: Early Hi-Depth Test Fails */ +#define sklgt4__memory_reads__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Memory Reads Distribution Gen9 :: VS Threads Dispatched */ +#define sklgt4__memory_reads__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Memory Reads Distribution Gen9 :: FS Threads Dispatched */ +#define sklgt4__memory_reads__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Memory Reads Distribution Gen9 :: GtiL3Bank3Reads */ +#define sklgt4__memory_reads__gti_l3_bank3_reads__read \ + hsw__memory_reads__gpu_core_clocks__read + +/* Memory Reads Distribution Gen9 :: Shader Barrier Messages */ +#define sklgt4__memory_reads__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Memory Reads Distribution Gen9 :: GtiRsMemoryReads */ +#define sklgt4__memory_reads__gti_rs_memory_reads__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Memory Reads Distribution Gen9 :: Sampler Texels */ +#define sklgt4__memory_reads__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Memory Reads Distribution Gen9 :: Pixels Failing Tests */ +#define sklgt4__memory_reads__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Memory Reads Distribution Gen9 :: GtiHizMemoryReads */ +#define sklgt4__memory_reads__gti_hiz_memory_reads__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* Memory Reads Distribution Gen9 :: GPU Time Elapsed */ +#define sklgt4__memory_reads__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Memory Reads Distribution Gen9 :: AVG GPU Core Frequency */ +#define sklgt4__memory_reads__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Memory Reads Distribution Gen9 :: AVG GPU Core Frequency */ +#define sklgt4__memory_reads__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Memory Reads Distribution Gen9 :: Sampler Texels Misses */ +#define sklgt4__memory_reads__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Memory Reads Distribution Gen9 :: GtiRccMemoryReads */ +#define sklgt4__memory_reads__gti_rcc_memory_reads__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* Memory Reads Distribution Gen9 :: CS Threads Dispatched */ +#define sklgt4__memory_reads__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Memory Reads Distribution Gen9 :: SLM Bytes Read */ +#define sklgt4__memory_reads__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Memory Reads Distribution Gen9 :: GtiL3Bank1Reads */ +#define sklgt4__memory_reads__gti_l3_bank1_reads__read \ + hsw__memory_reads__gti_memory_reads__read + +/* Memory Reads Distribution Gen9 :: GPU Busy */ +#define sklgt4__memory_reads__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Memory Reads Distribution Gen9 :: GtiCmdStreamerMemoryReads */ +#define sklgt4__memory_reads__gti_cmd_streamer_memory_reads__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* Memory Reads Distribution Gen9 :: GtiL3Bank2Reads */ +#define sklgt4__memory_reads__gti_l3_bank2_reads__read \ + hsw__memory_reads__llc_read_accesses__read + +/* Memory Reads Distribution Gen9 :: GtiMemoryReads */ +#define sklgt4__memory_reads__gti_memory_reads__read \ + hsw__compute_extended__typed_writes0__read + +/* Memory Reads Distribution Gen9 :: Rasterized Pixels */ +#define sklgt4__memory_reads__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Memory Reads Distribution Gen9 :: GtiRczMemoryReads */ +#define sklgt4__memory_reads__gti_rcz_memory_reads__read \ + hsw__compute_extended__gpu_clocks__read + +/* Memory Reads Distribution Gen9 :: DS Threads Dispatched */ +#define sklgt4__memory_reads__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Memory Reads Distribution Gen9 :: Samples Written */ +#define sklgt4__memory_reads__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Memory Reads Distribution Gen9 :: EU Stall */ +#define sklgt4__memory_reads__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Memory Reads Distribution Gen9 :: Samples Blended */ +#define sklgt4__memory_reads__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Memory Reads Distribution Gen9 :: Early Depth Test Fails */ +#define sklgt4__memory_reads__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Memory Reads Distribution Gen9 :: GtiMscMemoryReads */ +#define sklgt4__memory_reads__gti_msc_memory_reads__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* Memory Reads Distribution Gen9 :: GtiVfMemoryReads */ +#define sklgt4__memory_reads__gti_vf_memory_reads__read \ + hsw__compute_extended__eu_untyped_writes0__read + +/* Memory Reads Distribution Gen9 :: GtiStcMemoryReads */ +#define sklgt4__memory_reads__gti_stc_memory_reads__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* Memory Reads Distribution Gen9 :: Shader Memory Accesses */ +#define sklgt4__memory_reads__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Memory Reads Distribution Gen9 :: HS Threads Dispatched */ +#define sklgt4__memory_reads__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Memory Reads Distribution Gen9 :: Samples Killed in FS */ +#define sklgt4__memory_reads__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Memory Reads Distribution Gen9 :: SLM Bytes Written */ +#define sklgt4__memory_reads__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Memory Reads Distribution Gen9 :: GtiL3Reads */ +#define sklgt4__memory_reads__gti_l3_reads__read \ + bdw__memory_reads__gti_l3_reads__read + +/* Memory Reads Distribution Gen9 :: Shader Atomic Memory Accesses */ +#define sklgt4__memory_reads__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Memory Writes Distribution Gen9 :: GPU Core Clocks */ +#define sklgt4__memory_writes__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Memory Writes Distribution Gen9 :: EU Active */ +#define sklgt4__memory_writes__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Memory Writes Distribution Gen9 :: GtiMemoryWrites */ +#define sklgt4__memory_writes__gti_memory_writes__read \ + hsw__compute_extended__typed_writes0__read + +/* Memory Writes Distribution Gen9 :: GS Threads Dispatched */ +#define sklgt4__memory_writes__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Memory Writes Distribution Gen9 :: GtiRingAccesses */ +#define sklgt4__memory_writes__gti_ring_accesses__read \ + bdw__memory_reads__gti_ring_accesses__read + +/* Memory Writes Distribution Gen9 :: Early Hi-Depth Test Fails */ +#define sklgt4__memory_writes__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Memory Writes Distribution Gen9 :: VS Threads Dispatched */ +#define sklgt4__memory_writes__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Memory Writes Distribution Gen9 :: FS Threads Dispatched */ +#define sklgt4__memory_writes__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Memory Writes Distribution Gen9 :: GtiMscMemoryWrites */ +#define sklgt4__memory_writes__gti_msc_memory_writes__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* Memory Writes Distribution Gen9 :: Shader Barrier Messages */ +#define sklgt4__memory_writes__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Memory Writes Distribution Gen9 :: GtiCmdStreamerMemoryWrites */ +#define sklgt4__memory_writes__gti_cmd_streamer_memory_writes__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* Memory Writes Distribution Gen9 :: Sampler Texels */ +#define sklgt4__memory_writes__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Memory Writes Distribution Gen9 :: Pixels Failing Tests */ +#define sklgt4__memory_writes__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Memory Writes Distribution Gen9 :: GtiL3Bank0Writes */ +#define sklgt4__memory_writes__gti_l3_bank0_writes__read \ + hsw__compute_extended__typed_atomics0__read + +/* Memory Writes Distribution Gen9 :: GtiL3Bank1Writes */ +#define sklgt4__memory_writes__gti_l3_bank1_writes__read \ + hsw__memory_reads__gti_memory_reads__read + +/* Memory Writes Distribution Gen9 :: GtiL3Bank2Writes */ +#define sklgt4__memory_writes__gti_l3_bank2_writes__read \ + hsw__memory_reads__llc_read_accesses__read + +/* Memory Writes Distribution Gen9 :: GtiL3Bank3Writes */ +#define sklgt4__memory_writes__gti_l3_bank3_writes__read \ + hsw__memory_reads__gpu_core_clocks__read + +/* Memory Writes Distribution Gen9 :: GtiL3Writes */ +#define sklgt4__memory_writes__gti_l3_writes__read \ + bdw__memory_reads__gti_l3_reads__read + +/* Memory Writes Distribution Gen9 :: GPU Time Elapsed */ +#define sklgt4__memory_writes__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Memory Writes Distribution Gen9 :: AVG GPU Core Frequency */ +#define sklgt4__memory_writes__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Memory Writes Distribution Gen9 :: AVG GPU Core Frequency */ +#define sklgt4__memory_writes__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Memory Writes Distribution Gen9 :: Sampler Texels Misses */ +#define sklgt4__memory_writes__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Memory Writes Distribution Gen9 :: CS Threads Dispatched */ +#define sklgt4__memory_writes__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Memory Writes Distribution Gen9 :: SLM Bytes Read */ +#define sklgt4__memory_writes__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Memory Writes Distribution Gen9 :: GtiRccMemoryWrites */ +#define sklgt4__memory_writes__gti_rcc_memory_writes__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* Memory Writes Distribution Gen9 :: GtiSoMemoryWrites */ +#define sklgt4__memory_writes__gti_so_memory_writes__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Memory Writes Distribution Gen9 :: GPU Busy */ +#define sklgt4__memory_writes__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Memory Writes Distribution Gen9 :: GtiStcMemoryWrites */ +#define sklgt4__memory_writes__gti_stc_memory_writes__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* Memory Writes Distribution Gen9 :: Rasterized Pixels */ +#define sklgt4__memory_writes__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Memory Writes Distribution Gen9 :: DS Threads Dispatched */ +#define sklgt4__memory_writes__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Memory Writes Distribution Gen9 :: Samples Written */ +#define sklgt4__memory_writes__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Memory Writes Distribution Gen9 :: EU Stall */ +#define sklgt4__memory_writes__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Memory Writes Distribution Gen9 :: Samples Blended */ +#define sklgt4__memory_writes__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Memory Writes Distribution Gen9 :: Early Depth Test Fails */ +#define sklgt4__memory_writes__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Memory Writes Distribution Gen9 :: Shader Memory Accesses */ +#define sklgt4__memory_writes__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Memory Writes Distribution Gen9 :: HS Threads Dispatched */ +#define sklgt4__memory_writes__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Memory Writes Distribution Gen9 :: GtiRczMemoryWrites */ +#define sklgt4__memory_writes__gti_rcz_memory_writes__read \ + hsw__compute_extended__gpu_clocks__read + +/* Memory Writes Distribution Gen9 :: SLM Bytes Written */ +#define sklgt4__memory_writes__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Memory Writes Distribution Gen9 :: L3 Shader Throughput */ +#define sklgt4__memory_writes__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Memory Writes Distribution Gen9 :: Samples Killed in FS */ +#define sklgt4__memory_writes__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Memory Writes Distribution Gen9 :: GtiHizMemoryWrites */ +#define sklgt4__memory_writes__gti_hiz_memory_writes__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* Memory Writes Distribution Gen9 :: Shader Atomic Memory Accesses */ +#define sklgt4__memory_writes__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Extended Gen9 :: GPU Core Clocks */ +#define sklgt4__compute_extended__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Extended Gen9 :: EU Active */ +#define sklgt4__compute_extended__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Compute Metrics Extended Gen9 :: EU Both FPU Pipes Active */ +#define sklgt4__compute_extended__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Compute Metrics Extended Gen9 :: EU FPU0 Pipe Active */ +#define sklgt4__compute_extended__fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Compute Metrics Extended Gen9 :: EU FPU1 Pipe Active */ +#define sklgt4__compute_extended__fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Compute Metrics Extended Gen9 :: EU AVG IPC Rate */ +#define sklgt4__compute_extended__eu_avg_ipc_rate__read \ + bdw__compute_basic__eu_avg_ipc_rate__read + +/* Compute Metrics Extended Gen9 :: Typed Writes 0 */ +#define sklgt4__compute_extended__typed_writes0__read \ + hsw__compute_extended__typed_writes0__read + +/* Compute Metrics Extended Gen9 :: EuTypedAtomics0 */ +#define sklgt4__compute_extended__eu_typed_atomics0__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* Compute Metrics Extended Gen9 :: Typed Atomics 0 */ +#define sklgt4__compute_extended__typed_atomics0__read \ + hsw__compute_extended__typed_atomics0__read + +/* Compute Metrics Extended Gen9 :: TypedAtomicsPerCacheLine */ +#define sklgt4__compute_extended__typed_atomics_per_cache_line__read \ + hsw__compute_extended__typed_atomics_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: EuUntypedReads0 */ +#define sklgt4__compute_extended__eu_untyped_reads0__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* Compute Metrics Extended Gen9 :: Untyped Writes 0 */ +#define sklgt4__compute_extended__untyped_writes0__read \ + hsw__compute_extended__untyped_writes0__read + +/* Compute Metrics Extended Gen9 :: EuUntypedAtomics0 */ +#define sklgt4__compute_extended__eu_untyped_atomics0__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* Compute Metrics Extended Gen9 :: EuUntypedWrites0 */ +#define sklgt4__compute_extended__eu_untyped_writes0__read \ + hsw__compute_extended__eu_untyped_writes0__read + +/* Compute Metrics Extended Gen9 :: EuA64UntypedWrites0 */ +#define sklgt4__compute_extended__eu_a64_untyped_writes0__read \ + hsw__compute_extended__gpu_clocks__read + +/* Compute Metrics Extended Gen9 :: UntypedWritesPerCacheLine */ +#define sklgt4__compute_extended__untyped_writes_per_cache_line__read \ + bdw__compute_extended__untyped_writes_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: Shader Barrier Messages */ +#define sklgt4__compute_extended__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Compute Metrics Extended Gen9 :: Sampler Texels */ +#define sklgt4__compute_extended__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Compute Metrics Extended Gen9 :: GPU Time Elapsed */ +#define sklgt4__compute_extended__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics Extended Gen9 :: AVG GPU Core Frequency */ +#define sklgt4__compute_extended__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics Extended Gen9 :: AVG GPU Core Frequency */ +#define sklgt4__compute_extended__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics Extended Gen9 :: Sampler Texels Misses */ +#define sklgt4__compute_extended__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Compute Metrics Extended Gen9 :: CS Threads Dispatched */ +#define sklgt4__compute_extended__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Compute Metrics Extended Gen9 :: SLM Bytes Read */ +#define sklgt4__compute_extended__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Compute Metrics Extended Gen9 :: EuTypedWrites0 */ +#define sklgt4__compute_extended__eu_typed_writes0__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* Compute Metrics Extended Gen9 :: TypedWritesPerCacheLine */ +#define sklgt4__compute_extended__typed_writes_per_cache_line__read \ + hsw__compute_extended__typed_writes_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: Typed Reads 0 */ +#define sklgt4__compute_extended__typed_reads0__read \ + hsw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Extended Gen9 :: Untyped Reads 0 */ +#define sklgt4__compute_extended__untyped_reads0__read \ + hsw__compute_extended__untyped_reads0__read + +/* Compute Metrics Extended Gen9 :: EuA64UntypedReads0 */ +#define sklgt4__compute_extended__eu_a64_untyped_reads0__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* Compute Metrics Extended Gen9 :: EU Thread Occupancy */ +#define sklgt4__compute_extended__eu_thread_occupancy__read \ + bdw__compute_basic__eu_thread_occupancy__read + +/* Compute Metrics Extended Gen9 :: EU Stall */ +#define sklgt4__compute_extended__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics Extended Gen9 :: EuTypedReads0 */ +#define sklgt4__compute_extended__eu_typed_reads0__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Compute Metrics Extended Gen9 :: UntypedReadsPerCacheLine */ +#define sklgt4__compute_extended__untyped_reads_per_cache_line__read \ + bdw__compute_extended__untyped_reads_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: Shader Memory Accesses */ +#define sklgt4__compute_extended__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Compute Metrics Extended Gen9 :: TypedReadsPerCacheLine */ +#define sklgt4__compute_extended__typed_reads_per_cache_line__read \ + hsw__compute_extended__typed_reads_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: SLM Bytes Written */ +#define sklgt4__compute_extended__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Compute Metrics Extended Gen9 :: L3 Shader Throughput */ +#define sklgt4__compute_extended__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Compute Metrics Extended Gen9 :: Shader Atomic Memory Accesses */ +#define sklgt4__compute_extended__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Extended Gen9 :: EU Send Pipe Active */ +#define sklgt4__compute_extended__eu_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Compute Metrics L3 Cache Gen9 :: GPU Core Clocks */ +#define sklgt4__compute_l3_cache__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics L3 Cache Gen9 :: EU Active */ +#define sklgt4__compute_l3_cache__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 03 Accesses */ +#define sklgt4__compute_l3_cache__l3_bank03_accesses__read \ + bdw__compute_l3_cache__l3_bank03_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Accesses */ +#define sklgt4__compute_l3_cache__l3_accesses__read \ + sklgt2__compute_l3_cache__l3_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: EU Both FPU Pipes Active */ +#define sklgt4__compute_l3_cache__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Sampler Throughput */ +#define sklgt4__compute_l3_cache__l3_sampler_throughput__read \ + chv__render_basic__l3_sampler_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Pipe Active */ +#define sklgt4__compute_l3_cache__fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Pipe Active */ +#define sklgt4__compute_l3_cache__fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Compute Metrics L3 Cache Gen9 :: EU AVG IPC Rate */ +#define sklgt4__compute_l3_cache__eu_avg_ipc_rate__read \ + bdw__compute_basic__eu_avg_ipc_rate__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Binary Instruction */ +#define sklgt4__compute_l3_cache__eu_binary_fpu0_instruction__read \ + bdw__render_basic__ps_send_active__read + +/* Compute Metrics L3 Cache Gen9 :: GS Threads Dispatched */ +#define sklgt4__compute_l3_cache__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Compute Metrics L3 Cache Gen9 :: Shader Memory Accesses */ +#define sklgt4__compute_l3_cache__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: Early Hi-Depth Test Fails */ +#define sklgt4__compute_l3_cache__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Compute Metrics L3 Cache Gen9 :: VS Threads Dispatched */ +#define sklgt4__compute_l3_cache__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Compute Metrics L3 Cache Gen9 :: FS Threads Dispatched */ +#define sklgt4__compute_l3_cache__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Hybrid Instruction */ +#define sklgt4__compute_l3_cache__eu_hybrid_fpu0_instruction__read \ + bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Misses */ +#define sklgt4__compute_l3_cache__l3_misses__read \ + bdw__compute_l3_cache__l3_misses__read + +/* Compute Metrics L3 Cache Gen9 :: Shader Barrier Messages */ +#define sklgt4__compute_l3_cache__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 Accesses */ +#define sklgt4__compute_l3_cache__l3_bank00_accesses__read \ + bdw__compute_l3_cache__l3_bank00_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Move Instruction */ +#define sklgt4__compute_l3_cache__eu_move_fpu0_instruction__read \ + bdw__compute_l3_cache__eu_move_fpu0_instruction__read + +/* Compute Metrics L3 Cache Gen9 :: Sampler Texels */ +#define sklgt4__compute_l3_cache__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Compute Metrics L3 Cache Gen9 :: Pixels Failing Tests */ +#define sklgt4__compute_l3_cache__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Hybrid Instruction */ +#define sklgt4__compute_l3_cache__eu_hybrid_fpu1_instruction__read \ + bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read + +/* Compute Metrics L3 Cache Gen9 :: GPU Time Elapsed */ +#define sklgt4__compute_l3_cache__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics L3 Cache Gen9 :: AVG GPU Core Frequency */ +#define sklgt4__compute_l3_cache__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics L3 Cache Gen9 :: AVG GPU Core Frequency */ +#define sklgt4__compute_l3_cache__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics L3 Cache Gen9 :: Sampler Texels Misses */ +#define sklgt4__compute_l3_cache__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Compute Metrics L3 Cache Gen9 :: CS Threads Dispatched */ +#define sklgt4__compute_l3_cache__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Compute Metrics L3 Cache Gen9 :: SLM Bytes Read */ +#define sklgt4__compute_l3_cache__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Compute Metrics L3 Cache Gen9 :: GTI Read Throughput */ +#define sklgt4__compute_l3_cache__gti_read_throughput__read \ + bdw__render_basic__gti_read_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: GTI L3 Throughput */ +#define sklgt4__compute_l3_cache__gti_l3_throughput__read \ + bdw__compute_l3_cache__gti_l3_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 IC Accesses */ +#define sklgt4__compute_l3_cache__l3_bank00_ic_accesses__read \ + bdw__compute_l3_cache__l3_bank00_ic_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 IC Hits */ +#define sklgt4__compute_l3_cache__l3_bank00_ic_hits__read \ + bdw__compute_l3_cache__l3_bank00_ic_hits__read + +/* Compute Metrics L3 Cache Gen9 :: Sampler Accesses */ +#define sklgt4__compute_l3_cache__sampler_accesses__read \ + bdw__render_pipe_profile__sampler_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 01 Accesses */ +#define sklgt4__compute_l3_cache__l3_bank01_accesses__read \ + bdw__compute_l3_cache__l3_bank01_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: GPU Busy */ +#define sklgt4__compute_l3_cache__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Ternary Instruction */ +#define sklgt4__compute_l3_cache__eu_ternary_fpu0_instruction__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Compute Metrics L3 Cache Gen9 :: Shader Atomic Memory Accesses */ +#define sklgt4__compute_l3_cache__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics L3 Cache Gen9 :: Rasterized Pixels */ +#define sklgt4__compute_l3_cache__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Compute Metrics L3 Cache Gen9 :: DS Threads Dispatched */ +#define sklgt4__compute_l3_cache__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Compute Metrics L3 Cache Gen9 :: Samples Written */ +#define sklgt4__compute_l3_cache__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Move Instruction */ +#define sklgt4__compute_l3_cache__eu_move_fpu1_instruction__read \ + bdw__compute_l3_cache__eu_move_fpu1_instruction__read + +/* Compute Metrics L3 Cache Gen9 :: EU Stall */ +#define sklgt4__compute_l3_cache__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics L3 Cache Gen9 :: Samples Blended */ +#define sklgt4__compute_l3_cache__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Compute Metrics L3 Cache Gen9 :: Early Depth Test Fails */ +#define sklgt4__compute_l3_cache__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 02 Accesses */ +#define sklgt4__compute_l3_cache__l3_bank02_accesses__read \ + bdw__compute_l3_cache__l3_bank02_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: HS Threads Dispatched */ +#define sklgt4__compute_l3_cache__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Total Throughput */ +#define sklgt4__compute_l3_cache__l3_total_throughput__read \ + sklgt2__compute_l3_cache__l3_total_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: GTI Write Throughput */ +#define sklgt4__compute_l3_cache__gti_write_throughput__read \ + hsw__render_basic__gti_write_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: SLM Bytes Written */ +#define sklgt4__compute_l3_cache__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Shader Throughput */ +#define sklgt4__compute_l3_cache__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: Samples Killed in FS */ +#define sklgt4__compute_l3_cache__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Binary Instruction */ +#define sklgt4__compute_l3_cache__eu_binary_fpu1_instruction__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Ternary Instruction */ +#define sklgt4__compute_l3_cache__eu_ternary_fpu1_instruction__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Compute Metrics L3 Cache Gen9 :: EU Send Pipe Active */ +#define sklgt4__compute_l3_cache__eu_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set HDCAndSF :: GPU Core Clocks */ +#define sklgt4__hdc_and_sf__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set HDCAndSF :: EU Active */ +#define sklgt4__hdc_and_sf__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set HDCAndSF :: EU Both FPU Pipes Active */ +#define sklgt4__hdc_and_sf__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set HDCAndSF :: VS Send Pipe Active */ +#define sklgt4__hdc_and_sf__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set HDCAndSF :: VS FPU1 Pipe Active */ +#define sklgt4__hdc_and_sf__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set HDCAndSF :: GS Threads Dispatched */ +#define sklgt4__hdc_and_sf__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set HDCAndSF :: Early Hi-Depth Test Fails */ +#define sklgt4__hdc_and_sf__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set HDCAndSF :: FS Both FPU Active */ +#define sklgt4__hdc_and_sf__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set HDCAndSF :: VS Threads Dispatched */ +#define sklgt4__hdc_and_sf__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set HDCAndSF :: Polygon Data Ready */ +#define sklgt4__hdc_and_sf__poly_data_ready__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set HDCAndSF :: FS Threads Dispatched */ +#define sklgt4__hdc_and_sf__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set HDCAndSF :: Shader Barrier Messages */ +#define sklgt4__hdc_and_sf__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set HDCAndSF :: Sampler Texels */ +#define sklgt4__hdc_and_sf__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set HDCAndSF :: Pixels Failing Tests */ +#define sklgt4__hdc_and_sf__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set HDCAndSF :: GPU Time Elapsed */ +#define sklgt4__hdc_and_sf__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set HDCAndSF :: AVG GPU Core Frequency */ +#define sklgt4__hdc_and_sf__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set HDCAndSF :: AVG GPU Core Frequency */ +#define sklgt4__hdc_and_sf__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set HDCAndSF :: Sampler Texels Misses */ +#define sklgt4__hdc_and_sf__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */ +#define sklgt4__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read \ + bdw__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read + +/* Metric set HDCAndSF :: CS Threads Dispatched */ +#define sklgt4__hdc_and_sf__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss2) */ +#define sklgt4__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read \ + bdw__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read + +/* Metric set HDCAndSF :: SLM Bytes Read */ +#define sklgt4__hdc_and_sf__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set HDCAndSF :: PS FPU1 Pipe Active */ +#define sklgt4__hdc_and_sf__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set HDCAndSF :: PS Send Pipeline Active */ +#define sklgt4__hdc_and_sf__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set HDCAndSF :: VS FPU0 Pipe Active */ +#define sklgt4__hdc_and_sf__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set HDCAndSF :: GPU Busy */ +#define sklgt4__hdc_and_sf__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set HDCAndSF :: Rasterized Pixels */ +#define sklgt4__hdc_and_sf__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set HDCAndSF :: PS FPU0 Pipe Active */ +#define sklgt4__hdc_and_sf__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set HDCAndSF :: DS Threads Dispatched */ +#define sklgt4__hdc_and_sf__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set HDCAndSF :: Samples Written */ +#define sklgt4__hdc_and_sf__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set HDCAndSF :: EU Stall */ +#define sklgt4__hdc_and_sf__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set HDCAndSF :: Samples Blended */ +#define sklgt4__hdc_and_sf__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set HDCAndSF :: Early Depth Test Fails */ +#define sklgt4__hdc_and_sf__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set HDCAndSF :: Shader Memory Accesses */ +#define sklgt4__hdc_and_sf__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set HDCAndSF :: HS Threads Dispatched */ +#define sklgt4__hdc_and_sf__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set HDCAndSF :: SLM Bytes Written */ +#define sklgt4__hdc_and_sf__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set HDCAndSF :: L3 Shader Throughput */ +#define sklgt4__hdc_and_sf__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set HDCAndSF :: Samples Killed in FS */ +#define sklgt4__hdc_and_sf__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */ +#define sklgt4__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read \ + bdw__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read + +/* Metric set HDCAndSF :: Shader Atomic Memory Accesses */ +#define sklgt4__hdc_and_sf__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set L3_1 :: GPU Core Clocks */ +#define sklgt4__l3_1__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set L3_1 :: EU Active */ +#define sklgt4__l3_1__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set L3_1 :: Slice0 L3 Bank1 Active */ +#define sklgt4__l3_1__l30_bank1_active__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set L3_1 :: EU Both FPU Pipes Active */ +#define sklgt4__l3_1__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set L3_1 :: VS Send Pipe Active */ +#define sklgt4__l3_1__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set L3_1 :: VS FPU1 Pipe Active */ +#define sklgt4__l3_1__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set L3_1 :: GS Threads Dispatched */ +#define sklgt4__l3_1__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set L3_1 :: Early Hi-Depth Test Fails */ +#define sklgt4__l3_1__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set L3_1 :: FS Both FPU Active */ +#define sklgt4__l3_1__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set L3_1 :: VS Threads Dispatched */ +#define sklgt4__l3_1__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set L3_1 :: Slice0 L3 Bank1 Stalled */ +#define sklgt4__l3_1__l30_bank1_stalled__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Metric set L3_1 :: FS Threads Dispatched */ +#define sklgt4__l3_1__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set L3_1 :: Shader Barrier Messages */ +#define sklgt4__l3_1__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set L3_1 :: Sampler Texels */ +#define sklgt4__l3_1__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set L3_1 :: Pixels Failing Tests */ +#define sklgt4__l3_1__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set L3_1 :: GPU Time Elapsed */ +#define sklgt4__l3_1__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set L3_1 :: AVG GPU Core Frequency */ +#define sklgt4__l3_1__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set L3_1 :: AVG GPU Core Frequency */ +#define sklgt4__l3_1__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set L3_1 :: Sampler Texels Misses */ +#define sklgt4__l3_1__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set L3_1 :: CS Threads Dispatched */ +#define sklgt4__l3_1__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set L3_1 :: SLM Bytes Read */ +#define sklgt4__l3_1__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set L3_1 :: PS FPU1 Pipe Active */ +#define sklgt4__l3_1__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set L3_1 :: PS Send Pipeline Active */ +#define sklgt4__l3_1__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set L3_1 :: VS FPU0 Pipe Active */ +#define sklgt4__l3_1__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set L3_1 :: GPU Busy */ +#define sklgt4__l3_1__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set L3_1 :: Slice0 L3 Bank0 Active */ +#define sklgt4__l3_1__l30_bank0_active__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set L3_1 :: Rasterized Pixels */ +#define sklgt4__l3_1__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set L3_1 :: PS FPU0 Pipe Active */ +#define sklgt4__l3_1__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set L3_1 :: Slice0 L3 Bank0 Stalled */ +#define sklgt4__l3_1__l30_bank0_stalled__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set L3_1 :: DS Threads Dispatched */ +#define sklgt4__l3_1__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set L3_1 :: Samples Written */ +#define sklgt4__l3_1__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set L3_1 :: EU Stall */ +#define sklgt4__l3_1__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set L3_1 :: Samples Blended */ +#define sklgt4__l3_1__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set L3_1 :: Early Depth Test Fails */ +#define sklgt4__l3_1__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set L3_1 :: Shader Memory Accesses */ +#define sklgt4__l3_1__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set L3_1 :: HS Threads Dispatched */ +#define sklgt4__l3_1__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set L3_1 :: SLM Bytes Written */ +#define sklgt4__l3_1__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set L3_1 :: L3 Shader Throughput */ +#define sklgt4__l3_1__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set L3_1 :: Samples Killed in FS */ +#define sklgt4__l3_1__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set L3_1 :: Shader Atomic Memory Accesses */ +#define sklgt4__l3_1__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set L3_2 :: GPU Core Clocks */ +#define sklgt4__l3_2__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set L3_2 :: EU Active */ +#define sklgt4__l3_2__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set L3_2 :: EU Both FPU Pipes Active */ +#define sklgt4__l3_2__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set L3_2 :: VS Send Pipe Active */ +#define sklgt4__l3_2__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set L3_2 :: VS FPU1 Pipe Active */ +#define sklgt4__l3_2__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set L3_2 :: GS Threads Dispatched */ +#define sklgt4__l3_2__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set L3_2 :: Early Hi-Depth Test Fails */ +#define sklgt4__l3_2__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set L3_2 :: FS Both FPU Active */ +#define sklgt4__l3_2__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set L3_2 :: VS Threads Dispatched */ +#define sklgt4__l3_2__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set L3_2 :: FS Threads Dispatched */ +#define sklgt4__l3_2__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set L3_2 :: Shader Barrier Messages */ +#define sklgt4__l3_2__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set L3_2 :: Sampler Texels */ +#define sklgt4__l3_2__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set L3_2 :: Pixels Failing Tests */ +#define sklgt4__l3_2__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set L3_2 :: GPU Time Elapsed */ +#define sklgt4__l3_2__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set L3_2 :: AVG GPU Core Frequency */ +#define sklgt4__l3_2__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set L3_2 :: AVG GPU Core Frequency */ +#define sklgt4__l3_2__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set L3_2 :: Sampler Texels Misses */ +#define sklgt4__l3_2__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set L3_2 :: CS Threads Dispatched */ +#define sklgt4__l3_2__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set L3_2 :: SLM Bytes Read */ +#define sklgt4__l3_2__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set L3_2 :: PS FPU1 Pipe Active */ +#define sklgt4__l3_2__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set L3_2 :: Slice0 L3 Bank2 Stalled */ +#define sklgt4__l3_2__l30_bank2_stalled__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set L3_2 :: PS Send Pipeline Active */ +#define sklgt4__l3_2__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set L3_2 :: VS FPU0 Pipe Active */ +#define sklgt4__l3_2__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set L3_2 :: GPU Busy */ +#define sklgt4__l3_2__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set L3_2 :: Slice0 L3 Bank2 Active */ +#define sklgt4__l3_2__l30_bank2_active__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set L3_2 :: Rasterized Pixels */ +#define sklgt4__l3_2__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set L3_2 :: PS FPU0 Pipe Active */ +#define sklgt4__l3_2__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set L3_2 :: DS Threads Dispatched */ +#define sklgt4__l3_2__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set L3_2 :: Samples Written */ +#define sklgt4__l3_2__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set L3_2 :: EU Stall */ +#define sklgt4__l3_2__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set L3_2 :: Samples Blended */ +#define sklgt4__l3_2__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set L3_2 :: Early Depth Test Fails */ +#define sklgt4__l3_2__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set L3_2 :: Shader Memory Accesses */ +#define sklgt4__l3_2__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set L3_2 :: HS Threads Dispatched */ +#define sklgt4__l3_2__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set L3_2 :: SLM Bytes Written */ +#define sklgt4__l3_2__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set L3_2 :: L3 Shader Throughput */ +#define sklgt4__l3_2__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set L3_2 :: Samples Killed in FS */ +#define sklgt4__l3_2__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set L3_2 :: Shader Atomic Memory Accesses */ +#define sklgt4__l3_2__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set L3_3 :: GPU Core Clocks */ +#define sklgt4__l3_3__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set L3_3 :: EU Active */ +#define sklgt4__l3_3__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set L3_3 :: EU Both FPU Pipes Active */ +#define sklgt4__l3_3__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set L3_3 :: VS Send Pipe Active */ +#define sklgt4__l3_3__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set L3_3 :: VS FPU1 Pipe Active */ +#define sklgt4__l3_3__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set L3_3 :: GS Threads Dispatched */ +#define sklgt4__l3_3__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set L3_3 :: Early Hi-Depth Test Fails */ +#define sklgt4__l3_3__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set L3_3 :: FS Both FPU Active */ +#define sklgt4__l3_3__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set L3_3 :: VS Threads Dispatched */ +#define sklgt4__l3_3__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set L3_3 :: FS Threads Dispatched */ +#define sklgt4__l3_3__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set L3_3 :: Slice0 L3 Bank3 Stalled */ +#define sklgt4__l3_3__l30_bank3_stalled__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set L3_3 :: Shader Barrier Messages */ +#define sklgt4__l3_3__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set L3_3 :: Sampler Texels */ +#define sklgt4__l3_3__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set L3_3 :: Pixels Failing Tests */ +#define sklgt4__l3_3__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set L3_3 :: GPU Time Elapsed */ +#define sklgt4__l3_3__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set L3_3 :: AVG GPU Core Frequency */ +#define sklgt4__l3_3__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set L3_3 :: AVG GPU Core Frequency */ +#define sklgt4__l3_3__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set L3_3 :: Sampler Texels Misses */ +#define sklgt4__l3_3__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set L3_3 :: CS Threads Dispatched */ +#define sklgt4__l3_3__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set L3_3 :: SLM Bytes Read */ +#define sklgt4__l3_3__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set L3_3 :: PS FPU1 Pipe Active */ +#define sklgt4__l3_3__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set L3_3 :: Slice0 L3 Bank3 Active */ +#define sklgt4__l3_3__l30_bank3_active__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set L3_3 :: PS Send Pipeline Active */ +#define sklgt4__l3_3__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set L3_3 :: VS FPU0 Pipe Active */ +#define sklgt4__l3_3__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set L3_3 :: GPU Busy */ +#define sklgt4__l3_3__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set L3_3 :: Rasterized Pixels */ +#define sklgt4__l3_3__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set L3_3 :: PS FPU0 Pipe Active */ +#define sklgt4__l3_3__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set L3_3 :: DS Threads Dispatched */ +#define sklgt4__l3_3__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set L3_3 :: Samples Written */ +#define sklgt4__l3_3__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set L3_3 :: EU Stall */ +#define sklgt4__l3_3__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set L3_3 :: Samples Blended */ +#define sklgt4__l3_3__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set L3_3 :: Early Depth Test Fails */ +#define sklgt4__l3_3__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set L3_3 :: Shader Memory Accesses */ +#define sklgt4__l3_3__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set L3_3 :: HS Threads Dispatched */ +#define sklgt4__l3_3__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set L3_3 :: SLM Bytes Written */ +#define sklgt4__l3_3__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set L3_3 :: L3 Shader Throughput */ +#define sklgt4__l3_3__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set L3_3 :: Samples Killed in FS */ +#define sklgt4__l3_3__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set L3_3 :: Shader Atomic Memory Accesses */ +#define sklgt4__l3_3__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */ +#define sklgt4__rasterizer_and_pixel_backend__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set RasterizerAndPixelBackend :: EU Active */ +#define sklgt4__rasterizer_and_pixel_backend__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set RasterizerAndPixelBackend :: EU Both FPU Pipes Active */ +#define sklgt4__rasterizer_and_pixel_backend__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set RasterizerAndPixelBackend :: VS Send Pipe Active */ +#define sklgt4__rasterizer_and_pixel_backend__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set RasterizerAndPixelBackend :: VS FPU1 Pipe Active */ +#define sklgt4__rasterizer_and_pixel_backend__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */ +#define sklgt4__rasterizer_and_pixel_backend__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */ +#define sklgt4__rasterizer_and_pixel_backend__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set RasterizerAndPixelBackend :: FS Both FPU Active */ +#define sklgt4__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */ +#define sklgt4__rasterizer_and_pixel_backend__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */ +#define sklgt4__rasterizer_and_pixel_backend__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Pixel Values Ready */ +#define sklgt4__rasterizer_and_pixel_backend__pixel_values0_ready__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */ +#define sklgt4__rasterizer_and_pixel_backend__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set RasterizerAndPixelBackend :: Sampler Texels */ +#define sklgt4__rasterizer_and_pixel_backend__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */ +#define sklgt4__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */ +#define sklgt4__rasterizer_and_pixel_backend__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ +#define sklgt4__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ +#define sklgt4__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */ +#define sklgt4__rasterizer_and_pixel_backend__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */ +#define sklgt4__rasterizer_and_pixel_backend__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */ +#define sklgt4__rasterizer_and_pixel_backend__rasterizer0_input_available__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Post-EarlyZ Pixel Data Ready */ +#define sklgt4__rasterizer_and_pixel_backend__pixel_data0_ready__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */ +#define sklgt4__rasterizer_and_pixel_backend__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set RasterizerAndPixelBackend :: PS FPU1 Pipe Active */ +#define sklgt4__rasterizer_and_pixel_backend__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set RasterizerAndPixelBackend :: PS Send Pipeline Active */ +#define sklgt4__rasterizer_and_pixel_backend__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set RasterizerAndPixelBackend :: VS FPU0 Pipe Active */ +#define sklgt4__rasterizer_and_pixel_backend__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set RasterizerAndPixelBackend :: GPU Busy */ +#define sklgt4__rasterizer_and_pixel_backend__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */ +#define sklgt4__rasterizer_and_pixel_backend__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set RasterizerAndPixelBackend :: PS FPU0 Pipe Active */ +#define sklgt4__rasterizer_and_pixel_backend__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */ +#define sklgt4__rasterizer_and_pixel_backend__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set RasterizerAndPixelBackend :: Samples Written */ +#define sklgt4__rasterizer_and_pixel_backend__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set RasterizerAndPixelBackend :: EU Stall */ +#define sklgt4__rasterizer_and_pixel_backend__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */ +#define sklgt4__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set RasterizerAndPixelBackend :: Samples Blended */ +#define sklgt4__rasterizer_and_pixel_backend__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */ +#define sklgt4__rasterizer_and_pixel_backend__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */ +#define sklgt4__rasterizer_and_pixel_backend__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */ +#define sklgt4__rasterizer_and_pixel_backend__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */ +#define sklgt4__rasterizer_and_pixel_backend__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */ +#define sklgt4__rasterizer_and_pixel_backend__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */ +#define sklgt4__rasterizer_and_pixel_backend__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 PS Output Available */ +#define sklgt4__rasterizer_and_pixel_backend__ps_output0_available__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */ +#define sklgt4__rasterizer_and_pixel_backend__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set Sampler :: GPU Core Clocks */ +#define sklgt4__sampler__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set Sampler :: EU Active */ +#define sklgt4__sampler__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set Sampler :: Slice0 Subslice2 Input Available */ +#define sklgt4__sampler__sampler02_input_available__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set Sampler :: EU Both FPU Pipes Active */ +#define sklgt4__sampler__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set Sampler :: VS Send Pipe Active */ +#define sklgt4__sampler__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set Sampler :: Slice0 Subslice0 Input Available */ +#define sklgt4__sampler__sampler00_input_available__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Metric set Sampler :: VS FPU1 Pipe Active */ +#define sklgt4__sampler__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set Sampler :: GS Threads Dispatched */ +#define sklgt4__sampler__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set Sampler :: Early Hi-Depth Test Fails */ +#define sklgt4__sampler__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set Sampler :: FS Both FPU Active */ +#define sklgt4__sampler__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set Sampler :: VS Threads Dispatched */ +#define sklgt4__sampler__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set Sampler :: Slice0 Subslice2 Sampler Output Ready */ +#define sklgt4__sampler__sampler02_output_ready__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set Sampler :: FS Threads Dispatched */ +#define sklgt4__sampler__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set Sampler :: Shader Barrier Messages */ +#define sklgt4__sampler__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set Sampler :: Slice0 Subslice1 Input Available */ +#define sklgt4__sampler__sampler01_input_available__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set Sampler :: Sampler Texels */ +#define sklgt4__sampler__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set Sampler :: Pixels Failing Tests */ +#define sklgt4__sampler__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set Sampler :: GPU Time Elapsed */ +#define sklgt4__sampler__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set Sampler :: AVG GPU Core Frequency */ +#define sklgt4__sampler__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set Sampler :: AVG GPU Core Frequency */ +#define sklgt4__sampler__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set Sampler :: Sampler Texels Misses */ +#define sklgt4__sampler__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set Sampler :: CS Threads Dispatched */ +#define sklgt4__sampler__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set Sampler :: SLM Bytes Read */ +#define sklgt4__sampler__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set Sampler :: PS FPU1 Pipe Active */ +#define sklgt4__sampler__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set Sampler :: PS Send Pipeline Active */ +#define sklgt4__sampler__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set Sampler :: VS FPU0 Pipe Active */ +#define sklgt4__sampler__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set Sampler :: GPU Busy */ +#define sklgt4__sampler__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set Sampler :: Rasterized Pixels */ +#define sklgt4__sampler__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set Sampler :: PS FPU0 Pipe Active */ +#define sklgt4__sampler__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set Sampler :: DS Threads Dispatched */ +#define sklgt4__sampler__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set Sampler :: Samples Written */ +#define sklgt4__sampler__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set Sampler :: EU Stall */ +#define sklgt4__sampler__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set Sampler :: Samples Blended */ +#define sklgt4__sampler__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set Sampler :: Early Depth Test Fails */ +#define sklgt4__sampler__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set Sampler :: Slice0 Subslice0 Sampler Output Ready */ +#define sklgt4__sampler__sampler00_output_ready__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set Sampler :: Slice0 Subslice1 Sampler Output Ready */ +#define sklgt4__sampler__sampler01_output_ready__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set Sampler :: Shader Memory Accesses */ +#define sklgt4__sampler__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set Sampler :: HS Threads Dispatched */ +#define sklgt4__sampler__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set Sampler :: SLM Bytes Written */ +#define sklgt4__sampler__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set Sampler :: L3 Shader Throughput */ +#define sklgt4__sampler__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set Sampler :: Samples Killed in FS */ +#define sklgt4__sampler__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set Sampler :: Shader Atomic Memory Accesses */ +#define sklgt4__sampler__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set TDL_1 :: GPU Core Clocks */ +#define sklgt4__tdl_1__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set TDL_1 :: EU Active */ +#define sklgt4__tdl_1__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set TDL_1 :: EU Both FPU Pipes Active */ +#define sklgt4__tdl_1__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set TDL_1 :: VS Send Pipe Active */ +#define sklgt4__tdl_1__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set TDL_1 :: VS FPU1 Pipe Active */ +#define sklgt4__tdl_1__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set TDL_1 :: GS Threads Dispatched */ +#define sklgt4__tdl_1__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set TDL_1 :: Early Hi-Depth Test Fails */ +#define sklgt4__tdl_1__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set TDL_1 :: FS Both FPU Active */ +#define sklgt4__tdl_1__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set TDL_1 :: VS Threads Dispatched */ +#define sklgt4__tdl_1__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set TDL_1 :: FS Threads Dispatched */ +#define sklgt4__tdl_1__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice2 */ +#define sklgt4__tdl_1__non_ps_thread02_ready_for_dispatch__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Metric set TDL_1 :: Shader Barrier Messages */ +#define sklgt4__tdl_1__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_1 :: Sampler Texels */ +#define sklgt4__tdl_1__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set TDL_1 :: Pixels Failing Tests */ +#define sklgt4__tdl_1__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set TDL_1 :: GPU Time Elapsed */ +#define sklgt4__tdl_1__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set TDL_1 :: AVG GPU Core Frequency */ +#define sklgt4__tdl_1__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set TDL_1 :: AVG GPU Core Frequency */ +#define sklgt4__tdl_1__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set TDL_1 :: Sampler Texels Misses */ +#define sklgt4__tdl_1__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice0 */ +#define sklgt4__tdl_1__non_ps_thread00_ready_for_dispatch__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Metric set TDL_1 :: CS Threads Dispatched */ +#define sklgt4__tdl_1__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set TDL_1 :: SLM Bytes Read */ +#define sklgt4__tdl_1__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set TDL_1 :: PS FPU1 Pipe Active */ +#define sklgt4__tdl_1__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set TDL_1 :: PS Send Pipeline Active */ +#define sklgt4__tdl_1__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set TDL_1 :: VS FPU0 Pipe Active */ +#define sklgt4__tdl_1__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set TDL_1 :: GPU Busy */ +#define sklgt4__tdl_1__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice0 */ +#define sklgt4__tdl_1__ps_thread00_ready_for_dispatch__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set TDL_1 :: Rasterized Pixels */ +#define sklgt4__tdl_1__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set TDL_1 :: PS FPU0 Pipe Active */ +#define sklgt4__tdl_1__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set TDL_1 :: DS Threads Dispatched */ +#define sklgt4__tdl_1__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set TDL_1 :: Samples Written */ +#define sklgt4__tdl_1__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set TDL_1 :: EU Stall */ +#define sklgt4__tdl_1__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set TDL_1 :: Samples Blended */ +#define sklgt4__tdl_1__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set TDL_1 :: Early Depth Test Fails */ +#define sklgt4__tdl_1__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice1 */ +#define sklgt4__tdl_1__ps_thread01_ready_for_dispatch__read \ + bdw__render_pipe_profile__cl_bottleneck__read + +/* Metric set TDL_1 :: Shader Memory Accesses */ +#define sklgt4__tdl_1__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set TDL_1 :: HS Threads Dispatched */ +#define sklgt4__tdl_1__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice2 */ +#define sklgt4__tdl_1__ps_thread02_ready_for_dispatch__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Metric set TDL_1 :: SLM Bytes Written */ +#define sklgt4__tdl_1__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set TDL_1 :: L3 Shader Throughput */ +#define sklgt4__tdl_1__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set TDL_1 :: Samples Killed in FS */ +#define sklgt4__tdl_1__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set TDL_1 :: Shader Atomic Memory Accesses */ +#define sklgt4__tdl_1__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice1 */ +#define sklgt4__tdl_1__non_ps_thread01_ready_for_dispatch__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set TDL_2 :: GPU Core Clocks */ +#define sklgt4__tdl_2__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set TDL_2 :: EU Active */ +#define sklgt4__tdl_2__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set TDL_2 :: EU Both FPU Pipes Active */ +#define sklgt4__tdl_2__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set TDL_2 :: VS Send Pipe Active */ +#define sklgt4__tdl_2__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set TDL_2 :: VS FPU1 Pipe Active */ +#define sklgt4__tdl_2__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set TDL_2 :: GS Threads Dispatched */ +#define sklgt4__tdl_2__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set TDL_2 :: Early Hi-Depth Test Fails */ +#define sklgt4__tdl_2__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set TDL_2 :: FS Both FPU Active */ +#define sklgt4__tdl_2__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set TDL_2 :: VS Threads Dispatched */ +#define sklgt4__tdl_2__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set TDL_2 :: FS Threads Dispatched */ +#define sklgt4__tdl_2__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set TDL_2 :: Shader Barrier Messages */ +#define sklgt4__tdl_2__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_2 :: Sampler Texels */ +#define sklgt4__tdl_2__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set TDL_2 :: Pixels Failing Tests */ +#define sklgt4__tdl_2__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 0 */ +#define sklgt4__tdl_2__thread_header01_ready_port0__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 1 */ +#define sklgt4__tdl_2__thread_header01_ready_port1__read \ + bdw__render_pipe_profile__ds_stall__read + +/* Metric set TDL_2 :: GPU Time Elapsed */ +#define sklgt4__tdl_2__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set TDL_2 :: AVG GPU Core Frequency */ +#define sklgt4__tdl_2__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set TDL_2 :: AVG GPU Core Frequency */ +#define sklgt4__tdl_2__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set TDL_2 :: Sampler Texels Misses */ +#define sklgt4__tdl_2__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set TDL_2 :: CS Threads Dispatched */ +#define sklgt4__tdl_2__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set TDL_2 :: SLM Bytes Read */ +#define sklgt4__tdl_2__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set TDL_2 :: PS FPU1 Pipe Active */ +#define sklgt4__tdl_2__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set TDL_2 :: PS Send Pipeline Active */ +#define sklgt4__tdl_2__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set TDL_2 :: VS FPU0 Pipe Active */ +#define sklgt4__tdl_2__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set TDL_2 :: GPU Busy */ +#define sklgt4__tdl_2__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 1 */ +#define sklgt4__tdl_2__thread_header02_ready_port1__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 0 */ +#define sklgt4__tdl_2__thread_header02_ready_port0__read \ + bdw__render_pipe_profile__so_stall__read + +/* Metric set TDL_2 :: Rasterized Pixels */ +#define sklgt4__tdl_2__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set TDL_2 :: PS FPU0 Pipe Active */ +#define sklgt4__tdl_2__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set TDL_2 :: DS Threads Dispatched */ +#define sklgt4__tdl_2__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set TDL_2 :: Samples Written */ +#define sklgt4__tdl_2__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set TDL_2 :: EU Stall */ +#define sklgt4__tdl_2__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set TDL_2 :: Samples Blended */ +#define sklgt4__tdl_2__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set TDL_2 :: Early Depth Test Fails */ +#define sklgt4__tdl_2__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_2 :: Shader Memory Accesses */ +#define sklgt4__tdl_2__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set TDL_2 :: HS Threads Dispatched */ +#define sklgt4__tdl_2__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set TDL_2 :: SLM Bytes Written */ +#define sklgt4__tdl_2__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set TDL_2 :: L3 Shader Throughput */ +#define sklgt4__tdl_2__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set TDL_2 :: Samples Killed in FS */ +#define sklgt4__tdl_2__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 0 */ +#define sklgt4__tdl_2__thread_header00_ready_port0__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set TDL_2 :: Shader Atomic Memory Accesses */ +#define sklgt4__tdl_2__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 1 */ +#define sklgt4__tdl_2__thread_header00_ready_port1__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Compute Metrics Extra Gen9 :: GPU Core Clocks */ +#define sklgt4__compute_extra__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Extra Gen9 :: EU FPU1 Pipe Active */ +#define sklgt4__compute_extra__fpu1_active__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics Extra Gen9 :: GPU Time Elapsed */ +#define sklgt4__compute_extra__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics Extra Gen9 :: AVG GPU Core Frequency */ +#define sklgt4__compute_extra__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics Extra Gen9 :: AVG GPU Core Frequency */ +#define sklgt4__compute_extra__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Media Vme Pipe Gen9 :: GPU Core Clocks */ +#define sklgt4__vme_pipe__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Media Vme Pipe Gen9 :: EU Active */ +#define sklgt4__vme_pipe__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Media Vme Pipe Gen9 :: EU Both FPU Pipes Active */ +#define sklgt4__vme_pipe__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Media Vme Pipe Gen9 :: GPU Time Elapsed */ +#define sklgt4__vme_pipe__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Media Vme Pipe Gen9 :: AVG GPU Core Frequency */ +#define sklgt4__vme_pipe__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Media Vme Pipe Gen9 :: AVG GPU Core Frequency */ +#define sklgt4__vme_pipe__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Media Vme Pipe Gen9 :: CS Threads Dispatched */ +#define sklgt4__vme_pipe__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Media Vme Pipe Gen9 :: EU Thread Occupancy */ +#define sklgt4__vme_pipe__eu_thread_occupancy__read \ + bdw__vme_pipe__eu_thread_occupancy__read + +/* Media Vme Pipe Gen9 :: EU Stall */ +#define sklgt4__vme_pipe__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Media Vme Pipe Gen9 :: VME Busy */ +#define sklgt4__vme_pipe__vme_busy__read \ + bdw__vme_pipe__vme_busy__read + +/* Media Vme Pipe Gen9 :: GPU Busy */ +#define sklgt4__vme_pipe__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Gpu Rings Busyness :: GPU Core Clocks */ +#define sklgt4__gpu_busyness__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Gpu Rings Busyness :: Vebox Ring Busy */ +#define sklgt4__gpu_busyness__vebox_busy__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Gpu Rings Busyness :: GPU Time Elapsed */ +#define sklgt4__gpu_busyness__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Gpu Rings Busyness :: AVG GPU Core Frequency */ +#define sklgt4__gpu_busyness__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Gpu Rings Busyness :: AVG GPU Core Frequency */ +#define sklgt4__gpu_busyness__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Gpu Rings Busyness :: Render Ring Busy */ +#define sklgt4__gpu_busyness__render_busy__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Gpu Rings Busyness :: Vdbox0 Ring Busy */ +#define sklgt4__gpu_busyness__vdbox0_busy__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Gpu Rings Busyness :: Blitter Ring Busy */ +#define sklgt4__gpu_busyness__blitter_busy__read \ + bdw__render_pipe_profile__so_stall__read + +/* Gpu Rings Busyness :: AnyRingBusy */ +#define sklgt4__gpu_busyness__any_ring_busy__read \ + bdw__render_basic__sampler0_busy__read + +/* Gpu Rings Busyness :: Vdbox1 Ring Busy */ +#define sklgt4__gpu_busyness__vdbox1_busy__read \ + bdw__render_pipe_profile__sf_stall__read + +/* MDAPI testing set Gen9 :: TestCounter7 */ +#define sklgt4__test_oa__counter7__read \ + hsw__compute_extended__gpu_clocks__read + +/* MDAPI testing set Gen9 :: GPU Time Elapsed */ +#define sklgt4__test_oa__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* MDAPI testing set Gen9 :: GPU Core Clocks */ +#define sklgt4__test_oa__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* MDAPI testing set Gen9 :: AVG GPU Core Frequency */ +#define sklgt4__test_oa__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* MDAPI testing set Gen9 :: AVG GPU Core Frequency */ +#define sklgt4__test_oa__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* MDAPI testing set Gen9 :: TestCounter8 */ +#define sklgt4__test_oa__counter8__read \ + hsw__memory_reads__gpu_core_clocks__read + +/* MDAPI testing set Gen9 :: TestCounter4 */ +#define sklgt4__test_oa__counter4__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* MDAPI testing set Gen9 :: TestCounter5 */ +#define sklgt4__test_oa__counter5__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* MDAPI testing set Gen9 :: TestCounter6 */ +#define sklgt4__test_oa__counter6__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* MDAPI testing set Gen9 :: TestCounter3 */ +#define sklgt4__test_oa__counter3__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* MDAPI testing set Gen9 :: TestCounter0 */ +#define sklgt4__test_oa__counter0__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* MDAPI testing set Gen9 :: TestCounter1 */ +#define sklgt4__test_oa__counter1__read \ + hsw__compute_extended__eu_untyped_writes0__read + +/* MDAPI testing set Gen9 :: TestCounter2 */ +#define sklgt4__test_oa__counter2__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Render Metrics Basic Gen9 :: GPU Core Clocks */ +#define bxt__render_basic__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Render Metrics Basic Gen9 :: EU Active */ +#define bxt__render_basic__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Render Metrics Basic Gen9 :: L3 Misses */ +#define bxt__render_basic__l3_misses__read \ + hsw__compute_extended__typed_atomics0__read + +/* Render Metrics Basic Gen9 :: GTI L3 Throughput */ +#define bxt__render_basic__gti_l3_throughput__read \ + hsw__render_basic__gti_l3_throughput__read + +/* Render Metrics Basic Gen9 :: EU Both FPU Pipes Active */ +#define bxt__render_basic__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Render Metrics Basic Gen9 :: Sampler Cache Misses */ +#define bxt__render_basic__sampler_l1_misses__read \ + sklgt2__render_basic__sampler_l1_misses__read + +/* Render Metrics Basic Gen9 :: VS Send Pipe Active */ +#define bxt__render_basic__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Render Metrics Basic Gen9 :: Sampler 1 Bottleneck */ +#define bxt__render_basic__sampler1_bottleneck__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Render Metrics Basic Gen9 :: VS FPU1 Pipe Active */ +#define bxt__render_basic__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Render Metrics Basic Gen9 :: GS Threads Dispatched */ +#define bxt__render_basic__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Render Metrics Basic Gen9 :: L3 Sampler Throughput */ +#define bxt__render_basic__l3_sampler_throughput__read \ + sklgt2__render_basic__l3_sampler_throughput__read + +/* Render Metrics Basic Gen9 :: Early Hi-Depth Test Fails */ +#define bxt__render_basic__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Render Metrics Basic Gen9 :: FS Both FPU Active */ +#define bxt__render_basic__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Render Metrics Basic Gen9 :: VS Threads Dispatched */ +#define bxt__render_basic__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Render Metrics Basic Gen9 :: FS Threads Dispatched */ +#define bxt__render_basic__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Render Metrics Basic Gen9 :: Sampler 0 Busy */ +#define bxt__render_basic__sampler0_busy__read \ + bdw__render_basic__sampler0_busy__read + +/* Render Metrics Basic Gen9 :: Sampler 1 Busy */ +#define bxt__render_basic__sampler1_busy__read \ + bdw__render_basic__sampler1_busy__read + +/* Render Metrics Basic Gen9 :: Samplers Busy */ +#define bxt__render_basic__samplers_busy__read \ + bdw__render_basic__samplers_busy__read + +/* Render Metrics Basic Gen9 :: GTI Fixed Pipe Throughput */ +#define bxt__render_basic__gti_vf_throughput__read \ + bdw__render_basic__gti_vf_throughput__read + +/* Render Metrics Basic Gen9 :: Shader Barrier Messages */ +#define bxt__render_basic__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Render Metrics Basic Gen9 :: Sampler 0 Bottleneck */ +#define bxt__render_basic__sampler0_bottleneck__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Render Metrics Basic Gen9 :: Sampler Texels */ +#define bxt__render_basic__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Render Metrics Basic Gen9 :: Pixels Failing Tests */ +#define bxt__render_basic__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Render Metrics Basic Gen9 :: GPU Time Elapsed */ +#define bxt__render_basic__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Render Metrics Basic Gen9 :: AVG GPU Core Frequency */ +#define bxt__render_basic__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Render Metrics Basic Gen9 :: AVG GPU Core Frequency */ +#define bxt__render_basic__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Render Metrics Basic Gen9 :: Sampler Texels Misses */ +#define bxt__render_basic__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Render Metrics Basic Gen9 :: CS Threads Dispatched */ +#define bxt__render_basic__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Render Metrics Basic Gen9 :: Shader Memory Accesses */ +#define bxt__render_basic__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Render Metrics Basic Gen9 :: L3 Lookup Accesses w/o IC */ +#define bxt__render_basic__l3_lookups__read \ + sklgt2__render_basic__l3_lookups__read + +/* Render Metrics Basic Gen9 :: SLM Bytes Read */ +#define bxt__render_basic__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Render Metrics Basic Gen9 :: GTI Read Throughput */ +#define bxt__render_basic__gti_read_throughput__read \ + bdw__render_basic__gti_read_throughput__read + +/* Render Metrics Basic Gen9 :: PS FPU1 Pipe Active */ +#define bxt__render_basic__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Render Metrics Basic Gen9 :: PS Send Pipeline Active */ +#define bxt__render_basic__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Render Metrics Basic Gen9 :: Rasterized Pixels */ +#define bxt__render_basic__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Render Metrics Basic Gen9 :: GPU Busy */ +#define bxt__render_basic__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Render Metrics Basic Gen9 :: GTI Depth Throughput */ +#define bxt__render_basic__gti_depth_throughput__read \ + bdw__render_basic__gti_depth_throughput__read + +/* Render Metrics Basic Gen9 :: VS FPU0 Pipe Active */ +#define bxt__render_basic__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Render Metrics Basic Gen9 :: PS FPU0 Pipe Active */ +#define bxt__render_basic__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Render Metrics Basic Gen9 :: DS Threads Dispatched */ +#define bxt__render_basic__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Render Metrics Basic Gen9 :: Samples Written */ +#define bxt__render_basic__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Render Metrics Basic Gen9 :: EU Stall */ +#define bxt__render_basic__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Render Metrics Basic Gen9 :: Samples Blended */ +#define bxt__render_basic__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Render Metrics Basic Gen9 :: Early Depth Test Fails */ +#define bxt__render_basic__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Render Metrics Basic Gen9 :: Samplers Bottleneck */ +#define bxt__render_basic__sampler_bottleneck__read \ + bdw__render_basic__sampler_bottleneck__read + +/* Render Metrics Basic Gen9 :: GTI HDC TLB Lookup Throughput */ +#define bxt__render_basic__gti_hdc_lookups_throughput__read \ + bdw__render_basic__gti_hdc_lookups_throughput__read + +/* Render Metrics Basic Gen9 :: GTI RCC Throughput */ +#define bxt__render_basic__gti_rcc_throughput__read \ + bdw__render_basic__gti_rcc_throughput__read + +/* Render Metrics Basic Gen9 :: HS Threads Dispatched */ +#define bxt__render_basic__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Render Metrics Basic Gen9 :: GTI Write Throughput */ +#define bxt__render_basic__gti_write_throughput__read \ + hsw__render_basic__gti_write_throughput__read + +/* Render Metrics Basic Gen9 :: SLM Bytes Written */ +#define bxt__render_basic__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Render Metrics Basic Gen9 :: L3 Shader Throughput */ +#define bxt__render_basic__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Render Metrics Basic Gen9 :: Samples Killed in FS */ +#define bxt__render_basic__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Render Metrics Basic Gen9 :: Shader Atomic Memory Accesses */ +#define bxt__render_basic__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Basic Gen9 :: GPU Core Clocks */ +#define bxt__compute_basic__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Basic Gen9 :: EU Active */ +#define bxt__compute_basic__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Compute Metrics Basic Gen9 :: Untyped Bytes Read */ +#define bxt__compute_basic__untyped_bytes_read__read \ + hsw__compute_basic__typed_bytes_written__read + +/* Compute Metrics Basic Gen9 :: EU Both FPU Pipes Active */ +#define bxt__compute_basic__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Compute Metrics Basic Gen9 :: Typed Bytes Written */ +static uint64_t +bxt__compute_basic__typed_bytes_written__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 3 READ B 4 READ UADD $EuSlicesTotalCount 64 UMUL UMUL */ + uint64_t tmp0 = accumulator[query->b_offset + 3]; + uint64_t tmp1 = accumulator[query->b_offset + 4]; + uint64_t tmp2 = tmp0 + tmp1; + uint64_t tmp3 = brw->perfquery.sys_vars.n_eu_slices * 64; + uint64_t tmp4 = tmp2 * tmp3; + + return tmp4; +} + +/* Compute Metrics Basic Gen9 :: EU FPU0 Pipe Active */ +#define bxt__compute_basic__fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Compute Metrics Basic Gen9 :: EU FPU1 Pipe Active */ +#define bxt__compute_basic__fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Compute Metrics Basic Gen9 :: EU AVG IPC Rate */ +#define bxt__compute_basic__eu_avg_ipc_rate__read \ + bdw__compute_basic__eu_avg_ipc_rate__read + +/* Compute Metrics Basic Gen9 :: GS Threads Dispatched */ +#define bxt__compute_basic__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Compute Metrics Basic Gen9 :: Early Hi-Depth Test Fails */ +#define bxt__compute_basic__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Compute Metrics Basic Gen9 :: VS Threads Dispatched */ +#define bxt__compute_basic__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Compute Metrics Basic Gen9 :: FS Threads Dispatched */ +#define bxt__compute_basic__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Compute Metrics Basic Gen9 :: Shader Barrier Messages */ +#define bxt__compute_basic__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Compute Metrics Basic Gen9 :: Sampler Texels */ +#define bxt__compute_basic__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Compute Metrics Basic Gen9 :: Pixels Failing Tests */ +#define bxt__compute_basic__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Compute Metrics Basic Gen9 :: GPU Time Elapsed */ +#define bxt__compute_basic__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics Basic Gen9 :: AVG GPU Core Frequency */ +#define bxt__compute_basic__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics Basic Gen9 :: AVG GPU Core Frequency */ +#define bxt__compute_basic__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics Basic Gen9 :: Sampler Texels Misses */ +#define bxt__compute_basic__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Compute Metrics Basic Gen9 :: CS Threads Dispatched */ +#define bxt__compute_basic__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Compute Metrics Basic Gen9 :: SLM Bytes Read */ +#define bxt__compute_basic__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Compute Metrics Basic Gen9 :: GTI Read Throughput */ +#define bxt__compute_basic__gti_read_throughput__read \ + hsw__render_basic__gti_l3_throughput__read + +/* Compute Metrics Basic Gen9 :: Untyped Writes */ +static uint64_t +bxt__compute_basic__untyped_bytes_written__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 1 READ C 2 READ UADD $EuSlicesTotalCount 64 UMUL UMUL */ + uint64_t tmp0 = accumulator[query->c_offset + 1]; + uint64_t tmp1 = accumulator[query->c_offset + 2]; + uint64_t tmp2 = tmp0 + tmp1; + uint64_t tmp3 = brw->perfquery.sys_vars.n_eu_slices * 64; + uint64_t tmp4 = tmp2 * tmp3; + + return tmp4; +} + +/* Compute Metrics Basic Gen9 :: GPU Busy */ +#define bxt__compute_basic__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Compute Metrics Basic Gen9 :: Rasterized Pixels */ +#define bxt__compute_basic__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Compute Metrics Basic Gen9 :: Typed Bytes Read */ +#define bxt__compute_basic__typed_bytes_read__read \ + hsw__compute_basic__untyped_bytes_read__read + +/* Compute Metrics Basic Gen9 :: DS Threads Dispatched */ +#define bxt__compute_basic__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Compute Metrics Basic Gen9 :: EU Thread Occupancy */ +#define bxt__compute_basic__eu_thread_occupancy__read \ + bdw__compute_basic__eu_thread_occupancy__read + +/* Compute Metrics Basic Gen9 :: EU Stall */ +#define bxt__compute_basic__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics Basic Gen9 :: Samples Blended */ +#define bxt__compute_basic__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Compute Metrics Basic Gen9 :: Early Depth Test Fails */ +#define bxt__compute_basic__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Compute Metrics Basic Gen9 :: Shader Memory Accesses */ +#define bxt__compute_basic__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Compute Metrics Basic Gen9 :: HS Threads Dispatched */ +#define bxt__compute_basic__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Compute Metrics Basic Gen9 :: GTI Write Throughput */ +#define bxt__compute_basic__gti_write_throughput__read \ + bdw__render_basic__gti_hdc_lookups_throughput__read + +/* Compute Metrics Basic Gen9 :: SLM Bytes Written */ +#define bxt__compute_basic__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Compute Metrics Basic Gen9 :: L3 Shader Throughput */ +#define bxt__compute_basic__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Compute Metrics Basic Gen9 :: Samples Killed in FS */ +#define bxt__compute_basic__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Compute Metrics Basic Gen9 :: Samples Written */ +#define bxt__compute_basic__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Compute Metrics Basic Gen9 :: Shader Atomic Memory Accesses */ +#define bxt__compute_basic__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Basic Gen9 :: EU Send Pipe Active */ +#define bxt__compute_basic__eu_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Core Clocks */ +#define bxt__render_pipe_profile__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: EU Active */ +#define bxt__render_pipe_profile__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: VS Bottleneck */ +#define bxt__render_pipe_profile__vs_bottleneck__read \ + bdw__render_basic__sampler0_busy__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Hi-Depth Bottleneck */ +#define bxt__render_pipe_profile__hi_depth_bottleneck__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GS Bottleneck */ +#define bxt__render_pipe_profile__gs_bottleneck__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GS Threads Dispatched */ +#define bxt__render_pipe_profile__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Early Hi-Depth Test Fails */ +#define bxt__render_pipe_profile__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: VS Threads Dispatched */ +#define bxt__render_pipe_profile__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: FS Threads Dispatched */ +#define bxt__render_pipe_profile__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: BC Bottleneck */ +#define bxt__render_pipe_profile__bc_bottleneck__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: HS Stall */ +#define bxt__render_pipe_profile__hs_stall__read \ + bdw__render_pipe_profile__hs_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Barrier Messages */ +#define bxt__render_pipe_profile__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Sampler Texels */ +#define bxt__render_pipe_profile__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Pixels Failing Tests */ +#define bxt__render_pipe_profile__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Time Elapsed */ +#define bxt__render_pipe_profile__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: AVG GPU Core Frequency */ +#define bxt__render_pipe_profile__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: AVG GPU Core Frequency */ +#define bxt__render_pipe_profile__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Sampler Texels Misses */ +#define bxt__render_pipe_profile__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: CS Threads Dispatched */ +#define bxt__render_pipe_profile__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: VF Bottleneck */ +#define bxt__render_pipe_profile__vf_bottleneck__read \ + bdw__render_pipe_profile__vf_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SLM Bytes Read */ +#define bxt__render_pipe_profile__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Strip-Fans Bottleneck */ +#define bxt__render_pipe_profile__sf_bottleneck__read \ + bdw__render_pipe_profile__sf_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SF Stall */ +#define bxt__render_pipe_profile__sf_stall__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Busy */ +#define bxt__render_pipe_profile__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: HS Bottleneck */ +#define bxt__render_pipe_profile__hs_bottleneck__read \ + bdw__render_basic__sampler1_busy__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: CL Stall */ +#define bxt__render_pipe_profile__cl_stall__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SO Bottleneck */ +#define bxt__render_pipe_profile__so_bottleneck__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Rasterized Pixels */ +#define bxt__render_pipe_profile__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: DS Threads Dispatched */ +#define bxt__render_pipe_profile__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Written */ +#define bxt__render_pipe_profile__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: DS Bottleneck */ +#define bxt__render_pipe_profile__ds_bottleneck__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: EU Stall */ +#define bxt__render_pipe_profile__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Clipper Bottleneck */ +#define bxt__render_pipe_profile__cl_bottleneck__read \ + bdw__render_pipe_profile__cl_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: DS Stall */ +#define bxt__render_pipe_profile__ds_stall__read \ + bdw__render_pipe_profile__ds_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Early Depth Bottleneck */ +#define bxt__render_pipe_profile__early_depth_bottleneck__read \ + bdw__render_pipe_profile__early_depth_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Blended */ +#define bxt__render_pipe_profile__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Early Depth Test Fails */ +#define bxt__render_pipe_profile__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Memory Accesses */ +#define bxt__render_pipe_profile__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: HS Threads Dispatched */ +#define bxt__render_pipe_profile__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SLM Bytes Written */ +#define bxt__render_pipe_profile__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: L3 Shader Throughput */ +#define bxt__render_pipe_profile__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Killed in FS */ +#define bxt__render_pipe_profile__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SO Stall */ +#define bxt__render_pipe_profile__so_stall__read \ + bdw__render_pipe_profile__so_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Atomic Memory Accesses */ +#define bxt__render_pipe_profile__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Memory Reads Distribution Gen9 :: GPU Core Clocks */ +#define bxt__memory_reads__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Memory Reads Distribution Gen9 :: EU Active */ +#define bxt__memory_reads__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Memory Reads Distribution Gen9 :: GtiL3Bank0Reads */ +#define bxt__memory_reads__gti_l3_bank0_reads__read \ + hsw__compute_extended__typed_atomics0__read + +/* Memory Reads Distribution Gen9 :: GS Threads Dispatched */ +#define bxt__memory_reads__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Memory Reads Distribution Gen9 :: GtiRingAccesses */ +#define bxt__memory_reads__gti_ring_accesses__read \ + bdw__memory_reads__gti_ring_accesses__read + +/* Memory Reads Distribution Gen9 :: Early Hi-Depth Test Fails */ +#define bxt__memory_reads__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Memory Reads Distribution Gen9 :: VS Threads Dispatched */ +#define bxt__memory_reads__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Memory Reads Distribution Gen9 :: FS Threads Dispatched */ +#define bxt__memory_reads__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Memory Reads Distribution Gen9 :: GtiL3Bank3Reads */ +#define bxt__memory_reads__gti_l3_bank3_reads__read \ + hsw__memory_reads__gpu_core_clocks__read + +/* Memory Reads Distribution Gen9 :: Shader Barrier Messages */ +#define bxt__memory_reads__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Memory Reads Distribution Gen9 :: GtiRsMemoryReads */ +#define bxt__memory_reads__gti_rs_memory_reads__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Memory Reads Distribution Gen9 :: Sampler Texels */ +#define bxt__memory_reads__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Memory Reads Distribution Gen9 :: Pixels Failing Tests */ +#define bxt__memory_reads__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Memory Reads Distribution Gen9 :: GtiHizMemoryReads */ +#define bxt__memory_reads__gti_hiz_memory_reads__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* Memory Reads Distribution Gen9 :: GPU Time Elapsed */ +#define bxt__memory_reads__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Memory Reads Distribution Gen9 :: AVG GPU Core Frequency */ +#define bxt__memory_reads__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Memory Reads Distribution Gen9 :: AVG GPU Core Frequency */ +#define bxt__memory_reads__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Memory Reads Distribution Gen9 :: Sampler Texels Misses */ +#define bxt__memory_reads__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Memory Reads Distribution Gen9 :: GtiRccMemoryReads */ +#define bxt__memory_reads__gti_rcc_memory_reads__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* Memory Reads Distribution Gen9 :: CS Threads Dispatched */ +#define bxt__memory_reads__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Memory Reads Distribution Gen9 :: SLM Bytes Read */ +#define bxt__memory_reads__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Memory Reads Distribution Gen9 :: GtiL3Bank1Reads */ +#define bxt__memory_reads__gti_l3_bank1_reads__read \ + hsw__memory_reads__gti_memory_reads__read + +/* Memory Reads Distribution Gen9 :: GPU Busy */ +#define bxt__memory_reads__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Memory Reads Distribution Gen9 :: GtiCmdStreamerMemoryReads */ +#define bxt__memory_reads__gti_cmd_streamer_memory_reads__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* Memory Reads Distribution Gen9 :: GtiL3Bank2Reads */ +#define bxt__memory_reads__gti_l3_bank2_reads__read \ + hsw__memory_reads__llc_read_accesses__read + +/* Memory Reads Distribution Gen9 :: GtiMemoryReads */ +#define bxt__memory_reads__gti_memory_reads__read \ + hsw__compute_extended__typed_writes0__read + +/* Memory Reads Distribution Gen9 :: Rasterized Pixels */ +#define bxt__memory_reads__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Memory Reads Distribution Gen9 :: GtiRczMemoryReads */ +#define bxt__memory_reads__gti_rcz_memory_reads__read \ + hsw__compute_extended__gpu_clocks__read + +/* Memory Reads Distribution Gen9 :: DS Threads Dispatched */ +#define bxt__memory_reads__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Memory Reads Distribution Gen9 :: Samples Written */ +#define bxt__memory_reads__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Memory Reads Distribution Gen9 :: EU Stall */ +#define bxt__memory_reads__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Memory Reads Distribution Gen9 :: Samples Blended */ +#define bxt__memory_reads__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Memory Reads Distribution Gen9 :: Early Depth Test Fails */ +#define bxt__memory_reads__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Memory Reads Distribution Gen9 :: GtiMscMemoryReads */ +#define bxt__memory_reads__gti_msc_memory_reads__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* Memory Reads Distribution Gen9 :: GtiVfMemoryReads */ +#define bxt__memory_reads__gti_vf_memory_reads__read \ + hsw__compute_extended__eu_untyped_writes0__read + +/* Memory Reads Distribution Gen9 :: GtiStcMemoryReads */ +#define bxt__memory_reads__gti_stc_memory_reads__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* Memory Reads Distribution Gen9 :: Shader Memory Accesses */ +#define bxt__memory_reads__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Memory Reads Distribution Gen9 :: HS Threads Dispatched */ +#define bxt__memory_reads__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Memory Reads Distribution Gen9 :: Samples Killed in FS */ +#define bxt__memory_reads__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Memory Reads Distribution Gen9 :: SLM Bytes Written */ +#define bxt__memory_reads__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Memory Reads Distribution Gen9 :: GtiL3Reads */ +#define bxt__memory_reads__gti_l3_reads__read \ + bdw__memory_reads__gti_l3_reads__read + +/* Memory Reads Distribution Gen9 :: Shader Atomic Memory Accesses */ +#define bxt__memory_reads__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Memory Writes Distribution Gen9 :: GPU Core Clocks */ +#define bxt__memory_writes__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Memory Writes Distribution Gen9 :: EU Active */ +#define bxt__memory_writes__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Memory Writes Distribution Gen9 :: GtiMemoryWrites */ +#define bxt__memory_writes__gti_memory_writes__read \ + hsw__compute_extended__typed_writes0__read + +/* Memory Writes Distribution Gen9 :: GS Threads Dispatched */ +#define bxt__memory_writes__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Memory Writes Distribution Gen9 :: GtiRingAccesses */ +#define bxt__memory_writes__gti_ring_accesses__read \ + bdw__memory_reads__gti_ring_accesses__read + +/* Memory Writes Distribution Gen9 :: Early Hi-Depth Test Fails */ +#define bxt__memory_writes__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Memory Writes Distribution Gen9 :: VS Threads Dispatched */ +#define bxt__memory_writes__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Memory Writes Distribution Gen9 :: FS Threads Dispatched */ +#define bxt__memory_writes__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Memory Writes Distribution Gen9 :: GtiMscMemoryWrites */ +#define bxt__memory_writes__gti_msc_memory_writes__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* Memory Writes Distribution Gen9 :: Shader Barrier Messages */ +#define bxt__memory_writes__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Memory Writes Distribution Gen9 :: GtiCmdStreamerMemoryWrites */ +#define bxt__memory_writes__gti_cmd_streamer_memory_writes__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* Memory Writes Distribution Gen9 :: Sampler Texels */ +#define bxt__memory_writes__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Memory Writes Distribution Gen9 :: Pixels Failing Tests */ +#define bxt__memory_writes__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Memory Writes Distribution Gen9 :: GtiL3Bank0Writes */ +#define bxt__memory_writes__gti_l3_bank0_writes__read \ + hsw__compute_extended__typed_atomics0__read + +/* Memory Writes Distribution Gen9 :: GtiL3Bank1Writes */ +#define bxt__memory_writes__gti_l3_bank1_writes__read \ + hsw__memory_reads__gti_memory_reads__read + +/* Memory Writes Distribution Gen9 :: GtiL3Bank2Writes */ +#define bxt__memory_writes__gti_l3_bank2_writes__read \ + hsw__memory_reads__llc_read_accesses__read + +/* Memory Writes Distribution Gen9 :: GtiL3Bank3Writes */ +#define bxt__memory_writes__gti_l3_bank3_writes__read \ + hsw__memory_reads__gpu_core_clocks__read + +/* Memory Writes Distribution Gen9 :: GtiL3Writes */ +#define bxt__memory_writes__gti_l3_writes__read \ + bdw__memory_reads__gti_l3_reads__read + +/* Memory Writes Distribution Gen9 :: GPU Time Elapsed */ +#define bxt__memory_writes__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Memory Writes Distribution Gen9 :: AVG GPU Core Frequency */ +#define bxt__memory_writes__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Memory Writes Distribution Gen9 :: AVG GPU Core Frequency */ +#define bxt__memory_writes__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Memory Writes Distribution Gen9 :: Sampler Texels Misses */ +#define bxt__memory_writes__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Memory Writes Distribution Gen9 :: CS Threads Dispatched */ +#define bxt__memory_writes__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Memory Writes Distribution Gen9 :: SLM Bytes Read */ +#define bxt__memory_writes__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Memory Writes Distribution Gen9 :: GtiRccMemoryWrites */ +#define bxt__memory_writes__gti_rcc_memory_writes__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* Memory Writes Distribution Gen9 :: GtiSoMemoryWrites */ +#define bxt__memory_writes__gti_so_memory_writes__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Memory Writes Distribution Gen9 :: GPU Busy */ +#define bxt__memory_writes__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Memory Writes Distribution Gen9 :: GtiStcMemoryWrites */ +#define bxt__memory_writes__gti_stc_memory_writes__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* Memory Writes Distribution Gen9 :: Rasterized Pixels */ +#define bxt__memory_writes__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Memory Writes Distribution Gen9 :: DS Threads Dispatched */ +#define bxt__memory_writes__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Memory Writes Distribution Gen9 :: Samples Written */ +#define bxt__memory_writes__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Memory Writes Distribution Gen9 :: EU Stall */ +#define bxt__memory_writes__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Memory Writes Distribution Gen9 :: Samples Blended */ +#define bxt__memory_writes__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Memory Writes Distribution Gen9 :: Early Depth Test Fails */ +#define bxt__memory_writes__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Memory Writes Distribution Gen9 :: Shader Memory Accesses */ +#define bxt__memory_writes__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Memory Writes Distribution Gen9 :: HS Threads Dispatched */ +#define bxt__memory_writes__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Memory Writes Distribution Gen9 :: GtiRczMemoryWrites */ +#define bxt__memory_writes__gti_rcz_memory_writes__read \ + hsw__compute_extended__gpu_clocks__read + +/* Memory Writes Distribution Gen9 :: SLM Bytes Written */ +#define bxt__memory_writes__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Memory Writes Distribution Gen9 :: L3 Shader Throughput */ +#define bxt__memory_writes__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Memory Writes Distribution Gen9 :: Samples Killed in FS */ +#define bxt__memory_writes__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Memory Writes Distribution Gen9 :: GtiHizMemoryWrites */ +#define bxt__memory_writes__gti_hiz_memory_writes__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* Memory Writes Distribution Gen9 :: Shader Atomic Memory Accesses */ +#define bxt__memory_writes__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Extended Gen9 :: GPU Core Clocks */ +#define bxt__compute_extended__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Extended Gen9 :: EU Active */ +#define bxt__compute_extended__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Compute Metrics Extended Gen9 :: EU Both FPU Pipes Active */ +#define bxt__compute_extended__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Compute Metrics Extended Gen9 :: EU FPU0 Pipe Active */ +#define bxt__compute_extended__fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Compute Metrics Extended Gen9 :: EU FPU1 Pipe Active */ +#define bxt__compute_extended__fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Compute Metrics Extended Gen9 :: EU AVG IPC Rate */ +#define bxt__compute_extended__eu_avg_ipc_rate__read \ + bdw__compute_basic__eu_avg_ipc_rate__read + +/* Compute Metrics Extended Gen9 :: Typed Writes 0 */ +#define bxt__compute_extended__typed_writes0__read \ + hsw__compute_extended__typed_writes0__read + +/* Compute Metrics Extended Gen9 :: EuTypedAtomics0 */ +#define bxt__compute_extended__eu_typed_atomics0__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* Compute Metrics Extended Gen9 :: Typed Atomics 0 */ +#define bxt__compute_extended__typed_atomics0__read \ + hsw__compute_extended__typed_atomics0__read + +/* Compute Metrics Extended Gen9 :: TypedAtomicsPerCacheLine */ +#define bxt__compute_extended__typed_atomics_per_cache_line__read \ + hsw__compute_extended__typed_atomics_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: EuUntypedReads0 */ +#define bxt__compute_extended__eu_untyped_reads0__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* Compute Metrics Extended Gen9 :: Untyped Writes 0 */ +#define bxt__compute_extended__untyped_writes0__read \ + hsw__compute_extended__untyped_writes0__read + +/* Compute Metrics Extended Gen9 :: EuUntypedAtomics0 */ +#define bxt__compute_extended__eu_untyped_atomics0__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* Compute Metrics Extended Gen9 :: EuUntypedWrites0 */ +#define bxt__compute_extended__eu_untyped_writes0__read \ + hsw__compute_extended__eu_untyped_writes0__read + +/* Compute Metrics Extended Gen9 :: EuA64UntypedWrites0 */ +#define bxt__compute_extended__eu_a64_untyped_writes0__read \ + hsw__compute_extended__gpu_clocks__read + +/* Compute Metrics Extended Gen9 :: UntypedWritesPerCacheLine */ +#define bxt__compute_extended__untyped_writes_per_cache_line__read \ + bdw__compute_extended__untyped_writes_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: Shader Barrier Messages */ +#define bxt__compute_extended__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Compute Metrics Extended Gen9 :: Sampler Texels */ +#define bxt__compute_extended__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Compute Metrics Extended Gen9 :: GPU Time Elapsed */ +#define bxt__compute_extended__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics Extended Gen9 :: AVG GPU Core Frequency */ +#define bxt__compute_extended__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics Extended Gen9 :: AVG GPU Core Frequency */ +#define bxt__compute_extended__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics Extended Gen9 :: Sampler Texels Misses */ +#define bxt__compute_extended__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Compute Metrics Extended Gen9 :: CS Threads Dispatched */ +#define bxt__compute_extended__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Compute Metrics Extended Gen9 :: SLM Bytes Read */ +#define bxt__compute_extended__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Compute Metrics Extended Gen9 :: EuTypedWrites0 */ +#define bxt__compute_extended__eu_typed_writes0__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* Compute Metrics Extended Gen9 :: TypedWritesPerCacheLine */ +#define bxt__compute_extended__typed_writes_per_cache_line__read \ + hsw__compute_extended__typed_writes_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: Typed Reads 0 */ +#define bxt__compute_extended__typed_reads0__read \ + hsw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Extended Gen9 :: Untyped Reads 0 */ +#define bxt__compute_extended__untyped_reads0__read \ + hsw__compute_extended__untyped_reads0__read + +/* Compute Metrics Extended Gen9 :: EuA64UntypedReads0 */ +#define bxt__compute_extended__eu_a64_untyped_reads0__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* Compute Metrics Extended Gen9 :: EU Thread Occupancy */ +#define bxt__compute_extended__eu_thread_occupancy__read \ + bdw__compute_basic__eu_thread_occupancy__read + +/* Compute Metrics Extended Gen9 :: EU Stall */ +#define bxt__compute_extended__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics Extended Gen9 :: EuTypedReads0 */ +#define bxt__compute_extended__eu_typed_reads0__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Compute Metrics Extended Gen9 :: UntypedReadsPerCacheLine */ +#define bxt__compute_extended__untyped_reads_per_cache_line__read \ + bdw__compute_extended__untyped_reads_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: Shader Memory Accesses */ +#define bxt__compute_extended__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Compute Metrics Extended Gen9 :: TypedReadsPerCacheLine */ +#define bxt__compute_extended__typed_reads_per_cache_line__read \ + hsw__compute_extended__typed_reads_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: SLM Bytes Written */ +#define bxt__compute_extended__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Compute Metrics Extended Gen9 :: L3 Shader Throughput */ +#define bxt__compute_extended__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Compute Metrics Extended Gen9 :: Shader Atomic Memory Accesses */ +#define bxt__compute_extended__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Extended Gen9 :: EU Send Pipe Active */ +#define bxt__compute_extended__eu_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Compute Metrics L3 Cache Gen9 :: GPU Core Clocks */ +#define bxt__compute_l3_cache__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics L3 Cache Gen9 :: EU Active */ +#define bxt__compute_l3_cache__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 03 Accesses */ +#define bxt__compute_l3_cache__l3_bank03_accesses__read \ + bdw__compute_l3_cache__l3_bank03_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Accesses */ +#define bxt__compute_l3_cache__l3_accesses__read \ + sklgt2__compute_l3_cache__l3_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: EU Both FPU Pipes Active */ +#define bxt__compute_l3_cache__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Sampler Throughput */ +#define bxt__compute_l3_cache__l3_sampler_throughput__read \ + chv__render_basic__l3_sampler_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Pipe Active */ +#define bxt__compute_l3_cache__fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Pipe Active */ +#define bxt__compute_l3_cache__fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Compute Metrics L3 Cache Gen9 :: EU AVG IPC Rate */ +#define bxt__compute_l3_cache__eu_avg_ipc_rate__read \ + bdw__compute_basic__eu_avg_ipc_rate__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Binary Instruction */ +#define bxt__compute_l3_cache__eu_binary_fpu0_instruction__read \ + bdw__render_basic__ps_send_active__read + +/* Compute Metrics L3 Cache Gen9 :: GS Threads Dispatched */ +#define bxt__compute_l3_cache__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Compute Metrics L3 Cache Gen9 :: Shader Memory Accesses */ +#define bxt__compute_l3_cache__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: Early Hi-Depth Test Fails */ +#define bxt__compute_l3_cache__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Compute Metrics L3 Cache Gen9 :: VS Threads Dispatched */ +#define bxt__compute_l3_cache__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Compute Metrics L3 Cache Gen9 :: FS Threads Dispatched */ +#define bxt__compute_l3_cache__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Hybrid Instruction */ +#define bxt__compute_l3_cache__eu_hybrid_fpu0_instruction__read \ + bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Misses */ +#define bxt__compute_l3_cache__l3_misses__read \ + bdw__compute_l3_cache__l3_misses__read + +/* Compute Metrics L3 Cache Gen9 :: Shader Barrier Messages */ +#define bxt__compute_l3_cache__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 Accesses */ +#define bxt__compute_l3_cache__l3_bank00_accesses__read \ + bdw__compute_l3_cache__l3_bank00_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Move Instruction */ +#define bxt__compute_l3_cache__eu_move_fpu0_instruction__read \ + bdw__compute_l3_cache__eu_move_fpu0_instruction__read + +/* Compute Metrics L3 Cache Gen9 :: Sampler Texels */ +#define bxt__compute_l3_cache__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Compute Metrics L3 Cache Gen9 :: Pixels Failing Tests */ +#define bxt__compute_l3_cache__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Hybrid Instruction */ +#define bxt__compute_l3_cache__eu_hybrid_fpu1_instruction__read \ + bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read + +/* Compute Metrics L3 Cache Gen9 :: GPU Time Elapsed */ +#define bxt__compute_l3_cache__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics L3 Cache Gen9 :: AVG GPU Core Frequency */ +#define bxt__compute_l3_cache__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics L3 Cache Gen9 :: AVG GPU Core Frequency */ +#define bxt__compute_l3_cache__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics L3 Cache Gen9 :: Sampler Texels Misses */ +#define bxt__compute_l3_cache__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Compute Metrics L3 Cache Gen9 :: CS Threads Dispatched */ +#define bxt__compute_l3_cache__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Compute Metrics L3 Cache Gen9 :: SLM Bytes Read */ +#define bxt__compute_l3_cache__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Compute Metrics L3 Cache Gen9 :: GTI Read Throughput */ +#define bxt__compute_l3_cache__gti_read_throughput__read \ + bdw__render_basic__gti_read_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: GTI L3 Throughput */ +#define bxt__compute_l3_cache__gti_l3_throughput__read \ + bdw__compute_l3_cache__gti_l3_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 IC Accesses */ +#define bxt__compute_l3_cache__l3_bank00_ic_accesses__read \ + bdw__compute_l3_cache__l3_bank00_ic_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 IC Hits */ +#define bxt__compute_l3_cache__l3_bank00_ic_hits__read \ + bdw__compute_l3_cache__l3_bank00_ic_hits__read + +/* Compute Metrics L3 Cache Gen9 :: Sampler Accesses */ +#define bxt__compute_l3_cache__sampler_accesses__read \ + bdw__render_pipe_profile__sampler_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 01 Accesses */ +#define bxt__compute_l3_cache__l3_bank01_accesses__read \ + bdw__compute_l3_cache__l3_bank01_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: GPU Busy */ +#define bxt__compute_l3_cache__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Ternary Instruction */ +#define bxt__compute_l3_cache__eu_ternary_fpu0_instruction__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Compute Metrics L3 Cache Gen9 :: Shader Atomic Memory Accesses */ +#define bxt__compute_l3_cache__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics L3 Cache Gen9 :: Rasterized Pixels */ +#define bxt__compute_l3_cache__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Compute Metrics L3 Cache Gen9 :: DS Threads Dispatched */ +#define bxt__compute_l3_cache__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Compute Metrics L3 Cache Gen9 :: Samples Written */ +#define bxt__compute_l3_cache__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Move Instruction */ +#define bxt__compute_l3_cache__eu_move_fpu1_instruction__read \ + bdw__compute_l3_cache__eu_move_fpu1_instruction__read + +/* Compute Metrics L3 Cache Gen9 :: EU Stall */ +#define bxt__compute_l3_cache__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics L3 Cache Gen9 :: Samples Blended */ +#define bxt__compute_l3_cache__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Compute Metrics L3 Cache Gen9 :: Early Depth Test Fails */ +#define bxt__compute_l3_cache__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 02 Accesses */ +#define bxt__compute_l3_cache__l3_bank02_accesses__read \ + bdw__compute_l3_cache__l3_bank02_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: HS Threads Dispatched */ +#define bxt__compute_l3_cache__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Total Throughput */ +#define bxt__compute_l3_cache__l3_total_throughput__read \ + sklgt2__compute_l3_cache__l3_total_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: GTI Write Throughput */ +#define bxt__compute_l3_cache__gti_write_throughput__read \ + hsw__render_basic__gti_write_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: SLM Bytes Written */ +#define bxt__compute_l3_cache__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Shader Throughput */ +#define bxt__compute_l3_cache__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: Samples Killed in FS */ +#define bxt__compute_l3_cache__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Binary Instruction */ +#define bxt__compute_l3_cache__eu_binary_fpu1_instruction__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Ternary Instruction */ +#define bxt__compute_l3_cache__eu_ternary_fpu1_instruction__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Compute Metrics L3 Cache Gen9 :: EU Send Pipe Active */ +#define bxt__compute_l3_cache__eu_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set HDCAndSF :: GPU Core Clocks */ +#define bxt__hdc_and_sf__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set HDCAndSF :: EU Active */ +#define bxt__hdc_and_sf__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set HDCAndSF :: EU Both FPU Pipes Active */ +#define bxt__hdc_and_sf__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set HDCAndSF :: VS Send Pipe Active */ +#define bxt__hdc_and_sf__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set HDCAndSF :: VS FPU1 Pipe Active */ +#define bxt__hdc_and_sf__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set HDCAndSF :: GS Threads Dispatched */ +#define bxt__hdc_and_sf__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set HDCAndSF :: Early Hi-Depth Test Fails */ +#define bxt__hdc_and_sf__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set HDCAndSF :: FS Both FPU Active */ +#define bxt__hdc_and_sf__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set HDCAndSF :: VS Threads Dispatched */ +#define bxt__hdc_and_sf__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set HDCAndSF :: Polygon Data Ready */ +#define bxt__hdc_and_sf__poly_data_ready__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set HDCAndSF :: FS Threads Dispatched */ +#define bxt__hdc_and_sf__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set HDCAndSF :: Shader Barrier Messages */ +#define bxt__hdc_and_sf__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set HDCAndSF :: Sampler Texels */ +#define bxt__hdc_and_sf__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set HDCAndSF :: Pixels Failing Tests */ +#define bxt__hdc_and_sf__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set HDCAndSF :: GPU Time Elapsed */ +#define bxt__hdc_and_sf__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set HDCAndSF :: AVG GPU Core Frequency */ +#define bxt__hdc_and_sf__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set HDCAndSF :: AVG GPU Core Frequency */ +#define bxt__hdc_and_sf__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set HDCAndSF :: Sampler Texels Misses */ +#define bxt__hdc_and_sf__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */ +#define bxt__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read \ + bdw__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read + +/* Metric set HDCAndSF :: CS Threads Dispatched */ +#define bxt__hdc_and_sf__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set HDCAndSF :: SLM Bytes Read */ +#define bxt__hdc_and_sf__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set HDCAndSF :: PS FPU1 Pipe Active */ +#define bxt__hdc_and_sf__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set HDCAndSF :: PS Send Pipeline Active */ +#define bxt__hdc_and_sf__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set HDCAndSF :: VS FPU0 Pipe Active */ +#define bxt__hdc_and_sf__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set HDCAndSF :: GPU Busy */ +#define bxt__hdc_and_sf__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set HDCAndSF :: Rasterized Pixels */ +#define bxt__hdc_and_sf__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set HDCAndSF :: PS FPU0 Pipe Active */ +#define bxt__hdc_and_sf__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set HDCAndSF :: DS Threads Dispatched */ +#define bxt__hdc_and_sf__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set HDCAndSF :: Samples Written */ +#define bxt__hdc_and_sf__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set HDCAndSF :: EU Stall */ +#define bxt__hdc_and_sf__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set HDCAndSF :: Samples Blended */ +#define bxt__hdc_and_sf__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set HDCAndSF :: Early Depth Test Fails */ +#define bxt__hdc_and_sf__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set HDCAndSF :: Shader Memory Accesses */ +#define bxt__hdc_and_sf__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set HDCAndSF :: HS Threads Dispatched */ +#define bxt__hdc_and_sf__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set HDCAndSF :: SLM Bytes Written */ +#define bxt__hdc_and_sf__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set HDCAndSF :: L3 Shader Throughput */ +#define bxt__hdc_and_sf__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set HDCAndSF :: Samples Killed in FS */ +#define bxt__hdc_and_sf__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */ +#define bxt__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read \ + bdw__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read + +/* Metric set HDCAndSF :: Shader Atomic Memory Accesses */ +#define bxt__hdc_and_sf__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set L3_1 :: GPU Core Clocks */ +#define bxt__l3_1__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set L3_1 :: EU Active */ +#define bxt__l3_1__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set L3_1 :: Slice0 L3 Bank1 Active */ +#define bxt__l3_1__l30_bank1_active__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set L3_1 :: EU Both FPU Pipes Active */ +#define bxt__l3_1__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set L3_1 :: VS Send Pipe Active */ +#define bxt__l3_1__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set L3_1 :: VS FPU1 Pipe Active */ +#define bxt__l3_1__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set L3_1 :: GS Threads Dispatched */ +#define bxt__l3_1__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set L3_1 :: Early Hi-Depth Test Fails */ +#define bxt__l3_1__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set L3_1 :: FS Both FPU Active */ +#define bxt__l3_1__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set L3_1 :: VS Threads Dispatched */ +#define bxt__l3_1__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set L3_1 :: Slice0 L3 Bank1 Stalled */ +#define bxt__l3_1__l30_bank1_stalled__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Metric set L3_1 :: FS Threads Dispatched */ +#define bxt__l3_1__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set L3_1 :: Shader Barrier Messages */ +#define bxt__l3_1__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set L3_1 :: Sampler Texels */ +#define bxt__l3_1__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set L3_1 :: Pixels Failing Tests */ +#define bxt__l3_1__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set L3_1 :: GPU Time Elapsed */ +#define bxt__l3_1__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set L3_1 :: AVG GPU Core Frequency */ +#define bxt__l3_1__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set L3_1 :: AVG GPU Core Frequency */ +#define bxt__l3_1__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set L3_1 :: Sampler Texels Misses */ +#define bxt__l3_1__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set L3_1 :: CS Threads Dispatched */ +#define bxt__l3_1__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set L3_1 :: SLM Bytes Read */ +#define bxt__l3_1__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set L3_1 :: PS FPU1 Pipe Active */ +#define bxt__l3_1__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set L3_1 :: PS Send Pipeline Active */ +#define bxt__l3_1__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set L3_1 :: VS FPU0 Pipe Active */ +#define bxt__l3_1__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set L3_1 :: GPU Busy */ +#define bxt__l3_1__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set L3_1 :: Slice0 L3 Bank0 Active */ +#define bxt__l3_1__l30_bank0_active__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set L3_1 :: Rasterized Pixels */ +#define bxt__l3_1__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set L3_1 :: PS FPU0 Pipe Active */ +#define bxt__l3_1__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set L3_1 :: Slice0 L3 Bank0 Stalled */ +#define bxt__l3_1__l30_bank0_stalled__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set L3_1 :: DS Threads Dispatched */ +#define bxt__l3_1__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set L3_1 :: Samples Written */ +#define bxt__l3_1__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set L3_1 :: EU Stall */ +#define bxt__l3_1__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set L3_1 :: Samples Blended */ +#define bxt__l3_1__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set L3_1 :: Early Depth Test Fails */ +#define bxt__l3_1__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set L3_1 :: Shader Memory Accesses */ +#define bxt__l3_1__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set L3_1 :: HS Threads Dispatched */ +#define bxt__l3_1__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set L3_1 :: SLM Bytes Written */ +#define bxt__l3_1__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set L3_1 :: L3 Shader Throughput */ +#define bxt__l3_1__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set L3_1 :: Samples Killed in FS */ +#define bxt__l3_1__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set L3_1 :: Shader Atomic Memory Accesses */ +#define bxt__l3_1__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */ +#define bxt__rasterizer_and_pixel_backend__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set RasterizerAndPixelBackend :: EU Active */ +#define bxt__rasterizer_and_pixel_backend__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set RasterizerAndPixelBackend :: EU Both FPU Pipes Active */ +#define bxt__rasterizer_and_pixel_backend__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set RasterizerAndPixelBackend :: VS Send Pipe Active */ +#define bxt__rasterizer_and_pixel_backend__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set RasterizerAndPixelBackend :: VS FPU1 Pipe Active */ +#define bxt__rasterizer_and_pixel_backend__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */ +#define bxt__rasterizer_and_pixel_backend__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */ +#define bxt__rasterizer_and_pixel_backend__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set RasterizerAndPixelBackend :: FS Both FPU Active */ +#define bxt__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */ +#define bxt__rasterizer_and_pixel_backend__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */ +#define bxt__rasterizer_and_pixel_backend__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Pixel Values Ready */ +#define bxt__rasterizer_and_pixel_backend__pixel_values0_ready__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */ +#define bxt__rasterizer_and_pixel_backend__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set RasterizerAndPixelBackend :: Sampler Texels */ +#define bxt__rasterizer_and_pixel_backend__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */ +#define bxt__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */ +#define bxt__rasterizer_and_pixel_backend__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ +#define bxt__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ +#define bxt__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */ +#define bxt__rasterizer_and_pixel_backend__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */ +#define bxt__rasterizer_and_pixel_backend__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */ +#define bxt__rasterizer_and_pixel_backend__rasterizer0_input_available__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Post-EarlyZ Pixel Data Ready */ +#define bxt__rasterizer_and_pixel_backend__pixel_data0_ready__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */ +#define bxt__rasterizer_and_pixel_backend__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set RasterizerAndPixelBackend :: PS FPU1 Pipe Active */ +#define bxt__rasterizer_and_pixel_backend__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set RasterizerAndPixelBackend :: PS Send Pipeline Active */ +#define bxt__rasterizer_and_pixel_backend__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set RasterizerAndPixelBackend :: VS FPU0 Pipe Active */ +#define bxt__rasterizer_and_pixel_backend__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set RasterizerAndPixelBackend :: GPU Busy */ +#define bxt__rasterizer_and_pixel_backend__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */ +#define bxt__rasterizer_and_pixel_backend__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set RasterizerAndPixelBackend :: PS FPU0 Pipe Active */ +#define bxt__rasterizer_and_pixel_backend__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */ +#define bxt__rasterizer_and_pixel_backend__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set RasterizerAndPixelBackend :: Samples Written */ +#define bxt__rasterizer_and_pixel_backend__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set RasterizerAndPixelBackend :: EU Stall */ +#define bxt__rasterizer_and_pixel_backend__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */ +#define bxt__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set RasterizerAndPixelBackend :: Samples Blended */ +#define bxt__rasterizer_and_pixel_backend__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */ +#define bxt__rasterizer_and_pixel_backend__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */ +#define bxt__rasterizer_and_pixel_backend__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */ +#define bxt__rasterizer_and_pixel_backend__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */ +#define bxt__rasterizer_and_pixel_backend__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */ +#define bxt__rasterizer_and_pixel_backend__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */ +#define bxt__rasterizer_and_pixel_backend__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 PS Output Available */ +#define bxt__rasterizer_and_pixel_backend__ps_output0_available__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */ +#define bxt__rasterizer_and_pixel_backend__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set Sampler :: GPU Core Clocks */ +#define bxt__sampler__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set Sampler :: EU Active */ +#define bxt__sampler__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set Sampler :: Slice0 Subslice2 Input Available */ +#define bxt__sampler__sampler02_input_available__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set Sampler :: EU Both FPU Pipes Active */ +#define bxt__sampler__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set Sampler :: VS Send Pipe Active */ +#define bxt__sampler__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set Sampler :: Slice0 Subslice0 Input Available */ +#define bxt__sampler__sampler00_input_available__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Metric set Sampler :: VS FPU1 Pipe Active */ +#define bxt__sampler__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set Sampler :: GS Threads Dispatched */ +#define bxt__sampler__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set Sampler :: Early Hi-Depth Test Fails */ +#define bxt__sampler__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set Sampler :: FS Both FPU Active */ +#define bxt__sampler__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set Sampler :: VS Threads Dispatched */ +#define bxt__sampler__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set Sampler :: Slice0 Subslice2 Sampler Output Ready */ +#define bxt__sampler__sampler02_output_ready__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set Sampler :: FS Threads Dispatched */ +#define bxt__sampler__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set Sampler :: Shader Barrier Messages */ +#define bxt__sampler__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set Sampler :: Slice0 Subslice1 Input Available */ +#define bxt__sampler__sampler01_input_available__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set Sampler :: Sampler Texels */ +#define bxt__sampler__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set Sampler :: Pixels Failing Tests */ +#define bxt__sampler__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set Sampler :: GPU Time Elapsed */ +#define bxt__sampler__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set Sampler :: AVG GPU Core Frequency */ +#define bxt__sampler__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set Sampler :: AVG GPU Core Frequency */ +#define bxt__sampler__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set Sampler :: Sampler Texels Misses */ +#define bxt__sampler__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set Sampler :: CS Threads Dispatched */ +#define bxt__sampler__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set Sampler :: SLM Bytes Read */ +#define bxt__sampler__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set Sampler :: PS FPU1 Pipe Active */ +#define bxt__sampler__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set Sampler :: PS Send Pipeline Active */ +#define bxt__sampler__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set Sampler :: VS FPU0 Pipe Active */ +#define bxt__sampler__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set Sampler :: GPU Busy */ +#define bxt__sampler__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set Sampler :: Rasterized Pixels */ +#define bxt__sampler__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set Sampler :: PS FPU0 Pipe Active */ +#define bxt__sampler__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set Sampler :: DS Threads Dispatched */ +#define bxt__sampler__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set Sampler :: Samples Written */ +#define bxt__sampler__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set Sampler :: EU Stall */ +#define bxt__sampler__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set Sampler :: Samples Blended */ +#define bxt__sampler__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set Sampler :: Early Depth Test Fails */ +#define bxt__sampler__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set Sampler :: Slice0 Subslice0 Sampler Output Ready */ +#define bxt__sampler__sampler00_output_ready__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set Sampler :: Slice0 Subslice1 Sampler Output Ready */ +#define bxt__sampler__sampler01_output_ready__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set Sampler :: Shader Memory Accesses */ +#define bxt__sampler__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set Sampler :: HS Threads Dispatched */ +#define bxt__sampler__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set Sampler :: SLM Bytes Written */ +#define bxt__sampler__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set Sampler :: L3 Shader Throughput */ +#define bxt__sampler__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set Sampler :: Samples Killed in FS */ +#define bxt__sampler__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set Sampler :: Shader Atomic Memory Accesses */ +#define bxt__sampler__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set TDL_1 :: GPU Core Clocks */ +#define bxt__tdl_1__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set TDL_1 :: EU Active */ +#define bxt__tdl_1__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set TDL_1 :: EU Both FPU Pipes Active */ +#define bxt__tdl_1__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set TDL_1 :: VS Send Pipe Active */ +#define bxt__tdl_1__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set TDL_1 :: VS FPU1 Pipe Active */ +#define bxt__tdl_1__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set TDL_1 :: GS Threads Dispatched */ +#define bxt__tdl_1__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set TDL_1 :: Early Hi-Depth Test Fails */ +#define bxt__tdl_1__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set TDL_1 :: FS Both FPU Active */ +#define bxt__tdl_1__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set TDL_1 :: VS Threads Dispatched */ +#define bxt__tdl_1__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set TDL_1 :: FS Threads Dispatched */ +#define bxt__tdl_1__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice2 */ +#define bxt__tdl_1__non_ps_thread02_ready_for_dispatch__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Metric set TDL_1 :: Shader Barrier Messages */ +#define bxt__tdl_1__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_1 :: Sampler Texels */ +#define bxt__tdl_1__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set TDL_1 :: Pixels Failing Tests */ +#define bxt__tdl_1__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set TDL_1 :: GPU Time Elapsed */ +#define bxt__tdl_1__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set TDL_1 :: AVG GPU Core Frequency */ +#define bxt__tdl_1__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set TDL_1 :: AVG GPU Core Frequency */ +#define bxt__tdl_1__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set TDL_1 :: Sampler Texels Misses */ +#define bxt__tdl_1__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice0 */ +#define bxt__tdl_1__non_ps_thread00_ready_for_dispatch__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Metric set TDL_1 :: CS Threads Dispatched */ +#define bxt__tdl_1__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set TDL_1 :: SLM Bytes Read */ +#define bxt__tdl_1__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set TDL_1 :: PS FPU1 Pipe Active */ +#define bxt__tdl_1__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set TDL_1 :: PS Send Pipeline Active */ +#define bxt__tdl_1__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set TDL_1 :: VS FPU0 Pipe Active */ +#define bxt__tdl_1__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set TDL_1 :: GPU Busy */ +#define bxt__tdl_1__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice0 */ +#define bxt__tdl_1__ps_thread00_ready_for_dispatch__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set TDL_1 :: Rasterized Pixels */ +#define bxt__tdl_1__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set TDL_1 :: PS FPU0 Pipe Active */ +#define bxt__tdl_1__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set TDL_1 :: DS Threads Dispatched */ +#define bxt__tdl_1__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set TDL_1 :: Samples Written */ +#define bxt__tdl_1__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set TDL_1 :: EU Stall */ +#define bxt__tdl_1__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set TDL_1 :: Samples Blended */ +#define bxt__tdl_1__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set TDL_1 :: Early Depth Test Fails */ +#define bxt__tdl_1__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice1 */ +#define bxt__tdl_1__ps_thread01_ready_for_dispatch__read \ + bdw__render_pipe_profile__cl_bottleneck__read + +/* Metric set TDL_1 :: Shader Memory Accesses */ +#define bxt__tdl_1__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set TDL_1 :: HS Threads Dispatched */ +#define bxt__tdl_1__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice2 */ +#define bxt__tdl_1__ps_thread02_ready_for_dispatch__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Metric set TDL_1 :: SLM Bytes Written */ +#define bxt__tdl_1__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set TDL_1 :: L3 Shader Throughput */ +#define bxt__tdl_1__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set TDL_1 :: Samples Killed in FS */ +#define bxt__tdl_1__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set TDL_1 :: Shader Atomic Memory Accesses */ +#define bxt__tdl_1__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice1 */ +#define bxt__tdl_1__non_ps_thread01_ready_for_dispatch__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set TDL_2 :: GPU Core Clocks */ +#define bxt__tdl_2__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set TDL_2 :: EU Active */ +#define bxt__tdl_2__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set TDL_2 :: EU Both FPU Pipes Active */ +#define bxt__tdl_2__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set TDL_2 :: VS Send Pipe Active */ +#define bxt__tdl_2__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set TDL_2 :: VS FPU1 Pipe Active */ +#define bxt__tdl_2__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set TDL_2 :: GS Threads Dispatched */ +#define bxt__tdl_2__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set TDL_2 :: Early Hi-Depth Test Fails */ +#define bxt__tdl_2__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set TDL_2 :: FS Both FPU Active */ +#define bxt__tdl_2__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set TDL_2 :: VS Threads Dispatched */ +#define bxt__tdl_2__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set TDL_2 :: FS Threads Dispatched */ +#define bxt__tdl_2__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set TDL_2 :: Shader Barrier Messages */ +#define bxt__tdl_2__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_2 :: Sampler Texels */ +#define bxt__tdl_2__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set TDL_2 :: Pixels Failing Tests */ +#define bxt__tdl_2__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 0 */ +#define bxt__tdl_2__thread_header01_ready_port0__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 1 */ +#define bxt__tdl_2__thread_header01_ready_port1__read \ + bdw__render_pipe_profile__ds_stall__read + +/* Metric set TDL_2 :: GPU Time Elapsed */ +#define bxt__tdl_2__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set TDL_2 :: AVG GPU Core Frequency */ +#define bxt__tdl_2__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set TDL_2 :: AVG GPU Core Frequency */ +#define bxt__tdl_2__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set TDL_2 :: Sampler Texels Misses */ +#define bxt__tdl_2__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set TDL_2 :: CS Threads Dispatched */ +#define bxt__tdl_2__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set TDL_2 :: SLM Bytes Read */ +#define bxt__tdl_2__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set TDL_2 :: PS FPU1 Pipe Active */ +#define bxt__tdl_2__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set TDL_2 :: PS Send Pipeline Active */ +#define bxt__tdl_2__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set TDL_2 :: VS FPU0 Pipe Active */ +#define bxt__tdl_2__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set TDL_2 :: GPU Busy */ +#define bxt__tdl_2__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 1 */ +#define bxt__tdl_2__thread_header02_ready_port1__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 0 */ +#define bxt__tdl_2__thread_header02_ready_port0__read \ + bdw__render_pipe_profile__so_stall__read + +/* Metric set TDL_2 :: Rasterized Pixels */ +#define bxt__tdl_2__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set TDL_2 :: PS FPU0 Pipe Active */ +#define bxt__tdl_2__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set TDL_2 :: DS Threads Dispatched */ +#define bxt__tdl_2__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set TDL_2 :: Samples Written */ +#define bxt__tdl_2__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set TDL_2 :: EU Stall */ +#define bxt__tdl_2__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set TDL_2 :: Samples Blended */ +#define bxt__tdl_2__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set TDL_2 :: Early Depth Test Fails */ +#define bxt__tdl_2__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_2 :: Shader Memory Accesses */ +#define bxt__tdl_2__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set TDL_2 :: HS Threads Dispatched */ +#define bxt__tdl_2__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set TDL_2 :: SLM Bytes Written */ +#define bxt__tdl_2__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set TDL_2 :: L3 Shader Throughput */ +#define bxt__tdl_2__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set TDL_2 :: Samples Killed in FS */ +#define bxt__tdl_2__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 0 */ +#define bxt__tdl_2__thread_header00_ready_port0__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set TDL_2 :: Shader Atomic Memory Accesses */ +#define bxt__tdl_2__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 1 */ +#define bxt__tdl_2__thread_header00_ready_port1__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Compute Metrics Extra Gen9 :: GPU Core Clocks */ +#define bxt__compute_extra__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Extra Gen9 :: EU FPU1 Pipe Active */ +#define bxt__compute_extra__fpu1_active__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics Extra Gen9 :: GPU Time Elapsed */ +#define bxt__compute_extra__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics Extra Gen9 :: AVG GPU Core Frequency */ +#define bxt__compute_extra__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics Extra Gen9 :: AVG GPU Core Frequency */ +#define bxt__compute_extra__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics Extra Gen9 :: EU FPU1 Pipe Active including Ext Math */ +#define bxt__compute_extra__fpu1_active_adjusted__read \ + sklgt2__compute_extra__fpu1_active_adjusted__read + +/* Gpu Rings Busyness :: GPU Core Clocks */ +#define bxt__gpu_busyness__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Gpu Rings Busyness :: Vebox Ring Busy */ +#define bxt__gpu_busyness__vebox_busy__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Gpu Rings Busyness :: GPU Time Elapsed */ +#define bxt__gpu_busyness__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Gpu Rings Busyness :: AVG GPU Core Frequency */ +#define bxt__gpu_busyness__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Gpu Rings Busyness :: AVG GPU Core Frequency */ +#define bxt__gpu_busyness__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Gpu Rings Busyness :: Render Ring Busy */ +#define bxt__gpu_busyness__render_busy__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Gpu Rings Busyness :: Vdbox0 Ring Busy */ +#define bxt__gpu_busyness__vdbox0_busy__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Gpu Rings Busyness :: Blitter Ring Busy */ +#define bxt__gpu_busyness__blitter_busy__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Gpu Rings Busyness :: AnyRingBusy */ +#define bxt__gpu_busyness__any_ring_busy__read \ + bdw__render_basic__sampler0_busy__read + +/* MDAPI testing set Gen9 :: TestCounter7 */ +#define bxt__test_oa__counter7__read \ + hsw__compute_extended__gpu_clocks__read + +/* MDAPI testing set Gen9 :: GPU Time Elapsed */ +#define bxt__test_oa__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* MDAPI testing set Gen9 :: GPU Core Clocks */ +#define bxt__test_oa__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* MDAPI testing set Gen9 :: AVG GPU Core Frequency */ +#define bxt__test_oa__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* MDAPI testing set Gen9 :: AVG GPU Core Frequency */ +#define bxt__test_oa__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* MDAPI testing set Gen9 :: TestCounter8 */ +#define bxt__test_oa__counter8__read \ + hsw__memory_reads__gpu_core_clocks__read + +/* MDAPI testing set Gen9 :: TestCounter4 */ +#define bxt__test_oa__counter4__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* MDAPI testing set Gen9 :: TestCounter5 */ +#define bxt__test_oa__counter5__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* MDAPI testing set Gen9 :: TestCounter6 */ +#define bxt__test_oa__counter6__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* MDAPI testing set Gen9 :: TestCounter3 */ +#define bxt__test_oa__counter3__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* MDAPI testing set Gen9 :: TestCounter0 */ +#define bxt__test_oa__counter0__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* MDAPI testing set Gen9 :: TestCounter1 */ +#define bxt__test_oa__counter1__read \ + hsw__compute_extended__eu_untyped_writes0__read + +/* MDAPI testing set Gen9 :: TestCounter2 */ +#define bxt__test_oa__counter2__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Render Metrics Basic Gen9 :: GPU Core Clocks */ +#define kblgt2__render_basic__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Render Metrics Basic Gen9 :: EU Active */ +#define kblgt2__render_basic__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Render Metrics Basic Gen9 :: L3 Misses */ +#define kblgt2__render_basic__l3_misses__read \ + hsw__compute_extended__typed_atomics0__read + +/* Render Metrics Basic Gen9 :: GTI L3 Throughput */ +#define kblgt2__render_basic__gti_l3_throughput__read \ + hsw__render_basic__gti_l3_throughput__read + +/* Render Metrics Basic Gen9 :: EU Both FPU Pipes Active */ +#define kblgt2__render_basic__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Render Metrics Basic Gen9 :: Sampler Cache Misses */ +#define kblgt2__render_basic__sampler_l1_misses__read \ + sklgt2__render_basic__sampler_l1_misses__read + +/* Render Metrics Basic Gen9 :: VS Send Pipe Active */ +#define kblgt2__render_basic__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Render Metrics Basic Gen9 :: Sampler 1 Bottleneck */ +#define kblgt2__render_basic__sampler1_bottleneck__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Render Metrics Basic Gen9 :: VS FPU1 Pipe Active */ +#define kblgt2__render_basic__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Render Metrics Basic Gen9 :: GS Threads Dispatched */ +#define kblgt2__render_basic__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Render Metrics Basic Gen9 :: L3 Sampler Throughput */ +#define kblgt2__render_basic__l3_sampler_throughput__read \ + sklgt2__render_basic__l3_sampler_throughput__read + +/* Render Metrics Basic Gen9 :: Early Hi-Depth Test Fails */ +#define kblgt2__render_basic__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Render Metrics Basic Gen9 :: FS Both FPU Active */ +#define kblgt2__render_basic__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Render Metrics Basic Gen9 :: VS Threads Dispatched */ +#define kblgt2__render_basic__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Render Metrics Basic Gen9 :: FS Threads Dispatched */ +#define kblgt2__render_basic__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Render Metrics Basic Gen9 :: Sampler 0 Busy */ +#define kblgt2__render_basic__sampler0_busy__read \ + bdw__render_basic__sampler0_busy__read + +/* Render Metrics Basic Gen9 :: Sampler 1 Busy */ +#define kblgt2__render_basic__sampler1_busy__read \ + bdw__render_basic__sampler1_busy__read + +/* Render Metrics Basic Gen9 :: Samplers Busy */ +#define kblgt2__render_basic__samplers_busy__read \ + bdw__render_basic__samplers_busy__read + +/* Render Metrics Basic Gen9 :: GTI Fixed Pipe Throughput */ +#define kblgt2__render_basic__gti_vf_throughput__read \ + bdw__render_basic__gti_vf_throughput__read + +/* Render Metrics Basic Gen9 :: Shader Barrier Messages */ +#define kblgt2__render_basic__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Render Metrics Basic Gen9 :: Sampler 0 Bottleneck */ +#define kblgt2__render_basic__sampler0_bottleneck__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Render Metrics Basic Gen9 :: Sampler Texels */ +#define kblgt2__render_basic__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Render Metrics Basic Gen9 :: Pixels Failing Tests */ +#define kblgt2__render_basic__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Render Metrics Basic Gen9 :: GPU Time Elapsed */ +#define kblgt2__render_basic__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Render Metrics Basic Gen9 :: AVG GPU Core Frequency */ +#define kblgt2__render_basic__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Render Metrics Basic Gen9 :: AVG GPU Core Frequency */ +#define kblgt2__render_basic__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Render Metrics Basic Gen9 :: Sampler Texels Misses */ +#define kblgt2__render_basic__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Render Metrics Basic Gen9 :: CS Threads Dispatched */ +#define kblgt2__render_basic__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Render Metrics Basic Gen9 :: Shader Memory Accesses */ +#define kblgt2__render_basic__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Render Metrics Basic Gen9 :: L3 Lookup Accesses w/o IC */ +#define kblgt2__render_basic__l3_lookups__read \ + sklgt2__render_basic__l3_lookups__read + +/* Render Metrics Basic Gen9 :: SLM Bytes Read */ +#define kblgt2__render_basic__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Render Metrics Basic Gen9 :: GTI Read Throughput */ +#define kblgt2__render_basic__gti_read_throughput__read \ + bdw__render_basic__gti_read_throughput__read + +/* Render Metrics Basic Gen9 :: PS FPU1 Pipe Active */ +#define kblgt2__render_basic__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Render Metrics Basic Gen9 :: PS Send Pipeline Active */ +#define kblgt2__render_basic__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Render Metrics Basic Gen9 :: Rasterized Pixels */ +#define kblgt2__render_basic__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Render Metrics Basic Gen9 :: GPU Busy */ +#define kblgt2__render_basic__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Render Metrics Basic Gen9 :: GTI Depth Throughput */ +#define kblgt2__render_basic__gti_depth_throughput__read \ + bdw__render_basic__gti_depth_throughput__read + +/* Render Metrics Basic Gen9 :: VS FPU0 Pipe Active */ +#define kblgt2__render_basic__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Render Metrics Basic Gen9 :: PS FPU0 Pipe Active */ +#define kblgt2__render_basic__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Render Metrics Basic Gen9 :: DS Threads Dispatched */ +#define kblgt2__render_basic__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Render Metrics Basic Gen9 :: Samples Written */ +#define kblgt2__render_basic__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Render Metrics Basic Gen9 :: EU Stall */ +#define kblgt2__render_basic__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Render Metrics Basic Gen9 :: Samples Blended */ +#define kblgt2__render_basic__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Render Metrics Basic Gen9 :: Early Depth Test Fails */ +#define kblgt2__render_basic__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Render Metrics Basic Gen9 :: Samplers Bottleneck */ +#define kblgt2__render_basic__sampler_bottleneck__read \ + bdw__render_basic__sampler_bottleneck__read + +/* Render Metrics Basic Gen9 :: GTI HDC TLB Lookup Throughput */ +#define kblgt2__render_basic__gti_hdc_lookups_throughput__read \ + bdw__render_basic__gti_hdc_lookups_throughput__read + +/* Render Metrics Basic Gen9 :: GTI RCC Throughput */ +#define kblgt2__render_basic__gti_rcc_throughput__read \ + bdw__render_basic__gti_rcc_throughput__read + +/* Render Metrics Basic Gen9 :: HS Threads Dispatched */ +#define kblgt2__render_basic__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Render Metrics Basic Gen9 :: GTI Write Throughput */ +#define kblgt2__render_basic__gti_write_throughput__read \ + hsw__render_basic__gti_write_throughput__read + +/* Render Metrics Basic Gen9 :: SLM Bytes Written */ +#define kblgt2__render_basic__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Render Metrics Basic Gen9 :: L3 Shader Throughput */ +#define kblgt2__render_basic__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Render Metrics Basic Gen9 :: Samples Killed in FS */ +#define kblgt2__render_basic__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Render Metrics Basic Gen9 :: Shader Atomic Memory Accesses */ +#define kblgt2__render_basic__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Basic Gen9 :: GPU Core Clocks */ +#define kblgt2__compute_basic__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Basic Gen9 :: EU Active */ +#define kblgt2__compute_basic__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Compute Metrics Basic Gen9 :: Untyped Bytes Read */ +#define kblgt2__compute_basic__untyped_bytes_read__read \ + bdw__compute_basic__untyped_bytes_read__read + +/* Compute Metrics Basic Gen9 :: EU Both FPU Pipes Active */ +#define kblgt2__compute_basic__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Compute Metrics Basic Gen9 :: Typed Bytes Written */ +#define kblgt2__compute_basic__typed_bytes_written__read \ + bdw__compute_basic__typed_bytes_written__read + +/* Compute Metrics Basic Gen9 :: EU FPU0 Pipe Active */ +#define kblgt2__compute_basic__fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Compute Metrics Basic Gen9 :: EU FPU1 Pipe Active */ +#define kblgt2__compute_basic__fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Compute Metrics Basic Gen9 :: EU AVG IPC Rate */ +#define kblgt2__compute_basic__eu_avg_ipc_rate__read \ + bdw__compute_basic__eu_avg_ipc_rate__read + +/* Compute Metrics Basic Gen9 :: GS Threads Dispatched */ +#define kblgt2__compute_basic__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Compute Metrics Basic Gen9 :: Early Hi-Depth Test Fails */ +#define kblgt2__compute_basic__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Compute Metrics Basic Gen9 :: VS Threads Dispatched */ +#define kblgt2__compute_basic__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Compute Metrics Basic Gen9 :: FS Threads Dispatched */ +#define kblgt2__compute_basic__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Compute Metrics Basic Gen9 :: Shader Barrier Messages */ +#define kblgt2__compute_basic__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Compute Metrics Basic Gen9 :: Sampler Texels */ +#define kblgt2__compute_basic__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Compute Metrics Basic Gen9 :: Pixels Failing Tests */ +#define kblgt2__compute_basic__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Compute Metrics Basic Gen9 :: GPU Time Elapsed */ +#define kblgt2__compute_basic__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics Basic Gen9 :: AVG GPU Core Frequency */ +#define kblgt2__compute_basic__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics Basic Gen9 :: AVG GPU Core Frequency */ +#define kblgt2__compute_basic__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics Basic Gen9 :: Sampler Texels Misses */ +#define kblgt2__compute_basic__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Compute Metrics Basic Gen9 :: CS Threads Dispatched */ +#define kblgt2__compute_basic__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Compute Metrics Basic Gen9 :: SLM Bytes Read */ +#define kblgt2__compute_basic__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Compute Metrics Basic Gen9 :: GTI Read Throughput */ +#define kblgt2__compute_basic__gti_read_throughput__read \ + hsw__render_basic__gti_l3_throughput__read + +/* Compute Metrics Basic Gen9 :: Untyped Writes */ +#define kblgt2__compute_basic__untyped_bytes_written__read \ + bdw__compute_basic__untyped_bytes_written__read + +/* Compute Metrics Basic Gen9 :: GPU Busy */ +#define kblgt2__compute_basic__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Compute Metrics Basic Gen9 :: Rasterized Pixels */ +#define kblgt2__compute_basic__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Compute Metrics Basic Gen9 :: Typed Bytes Read */ +#define kblgt2__compute_basic__typed_bytes_read__read \ + bdw__compute_basic__typed_bytes_read__read + +/* Compute Metrics Basic Gen9 :: DS Threads Dispatched */ +#define kblgt2__compute_basic__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Compute Metrics Basic Gen9 :: EU Thread Occupancy */ +#define kblgt2__compute_basic__eu_thread_occupancy__read \ + bdw__compute_basic__eu_thread_occupancy__read + +/* Compute Metrics Basic Gen9 :: EU Stall */ +#define kblgt2__compute_basic__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics Basic Gen9 :: Samples Blended */ +#define kblgt2__compute_basic__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Compute Metrics Basic Gen9 :: Early Depth Test Fails */ +#define kblgt2__compute_basic__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Compute Metrics Basic Gen9 :: Shader Memory Accesses */ +#define kblgt2__compute_basic__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Compute Metrics Basic Gen9 :: HS Threads Dispatched */ +#define kblgt2__compute_basic__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Compute Metrics Basic Gen9 :: GTI Write Throughput */ +#define kblgt2__compute_basic__gti_write_throughput__read \ + bdw__render_basic__gti_hdc_lookups_throughput__read + +/* Compute Metrics Basic Gen9 :: SLM Bytes Written */ +#define kblgt2__compute_basic__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Compute Metrics Basic Gen9 :: L3 Shader Throughput */ +#define kblgt2__compute_basic__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Compute Metrics Basic Gen9 :: Samples Killed in FS */ +#define kblgt2__compute_basic__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Compute Metrics Basic Gen9 :: Samples Written */ +#define kblgt2__compute_basic__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Compute Metrics Basic Gen9 :: Shader Atomic Memory Accesses */ +#define kblgt2__compute_basic__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Basic Gen9 :: EU Send Pipe Active */ +#define kblgt2__compute_basic__eu_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Core Clocks */ +#define kblgt2__render_pipe_profile__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: EU Active */ +#define kblgt2__render_pipe_profile__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: VS Bottleneck */ +#define kblgt2__render_pipe_profile__vs_bottleneck__read \ + bdw__render_basic__sampler0_busy__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Hi-Depth Bottleneck */ +#define kblgt2__render_pipe_profile__hi_depth_bottleneck__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GS Bottleneck */ +#define kblgt2__render_pipe_profile__gs_bottleneck__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GS Threads Dispatched */ +#define kblgt2__render_pipe_profile__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Early Hi-Depth Test Fails */ +#define kblgt2__render_pipe_profile__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: VS Threads Dispatched */ +#define kblgt2__render_pipe_profile__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: FS Threads Dispatched */ +#define kblgt2__render_pipe_profile__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: BC Bottleneck */ +#define kblgt2__render_pipe_profile__bc_bottleneck__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: HS Stall */ +#define kblgt2__render_pipe_profile__hs_stall__read \ + bdw__render_pipe_profile__hs_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Barrier Messages */ +#define kblgt2__render_pipe_profile__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Sampler Texels */ +#define kblgt2__render_pipe_profile__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Pixels Failing Tests */ +#define kblgt2__render_pipe_profile__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Time Elapsed */ +#define kblgt2__render_pipe_profile__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: AVG GPU Core Frequency */ +#define kblgt2__render_pipe_profile__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: AVG GPU Core Frequency */ +#define kblgt2__render_pipe_profile__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Sampler Texels Misses */ +#define kblgt2__render_pipe_profile__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: CS Threads Dispatched */ +#define kblgt2__render_pipe_profile__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: VF Bottleneck */ +#define kblgt2__render_pipe_profile__vf_bottleneck__read \ + bdw__render_pipe_profile__vf_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SLM Bytes Read */ +#define kblgt2__render_pipe_profile__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Strip-Fans Bottleneck */ +#define kblgt2__render_pipe_profile__sf_bottleneck__read \ + bdw__render_pipe_profile__sf_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SF Stall */ +#define kblgt2__render_pipe_profile__sf_stall__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Busy */ +#define kblgt2__render_pipe_profile__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: HS Bottleneck */ +#define kblgt2__render_pipe_profile__hs_bottleneck__read \ + bdw__render_basic__sampler1_busy__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: CL Stall */ +#define kblgt2__render_pipe_profile__cl_stall__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SO Bottleneck */ +#define kblgt2__render_pipe_profile__so_bottleneck__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Rasterized Pixels */ +#define kblgt2__render_pipe_profile__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: DS Threads Dispatched */ +#define kblgt2__render_pipe_profile__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Written */ +#define kblgt2__render_pipe_profile__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: DS Bottleneck */ +#define kblgt2__render_pipe_profile__ds_bottleneck__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: EU Stall */ +#define kblgt2__render_pipe_profile__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Clipper Bottleneck */ +#define kblgt2__render_pipe_profile__cl_bottleneck__read \ + bdw__render_pipe_profile__cl_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: DS Stall */ +#define kblgt2__render_pipe_profile__ds_stall__read \ + bdw__render_pipe_profile__ds_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Early Depth Bottleneck */ +#define kblgt2__render_pipe_profile__early_depth_bottleneck__read \ + bdw__render_pipe_profile__early_depth_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Blended */ +#define kblgt2__render_pipe_profile__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Early Depth Test Fails */ +#define kblgt2__render_pipe_profile__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Memory Accesses */ +#define kblgt2__render_pipe_profile__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: HS Threads Dispatched */ +#define kblgt2__render_pipe_profile__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SLM Bytes Written */ +#define kblgt2__render_pipe_profile__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: L3 Shader Throughput */ +#define kblgt2__render_pipe_profile__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Killed in FS */ +#define kblgt2__render_pipe_profile__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SO Stall */ +#define kblgt2__render_pipe_profile__so_stall__read \ + bdw__render_pipe_profile__so_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Atomic Memory Accesses */ +#define kblgt2__render_pipe_profile__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Memory Reads Distribution Gen9 :: GPU Core Clocks */ +#define kblgt2__memory_reads__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Memory Reads Distribution Gen9 :: EU Active */ +#define kblgt2__memory_reads__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Memory Reads Distribution Gen9 :: GtiL3Bank0Reads */ +#define kblgt2__memory_reads__gti_l3_bank0_reads__read \ + hsw__compute_extended__typed_atomics0__read + +/* Memory Reads Distribution Gen9 :: GS Threads Dispatched */ +#define kblgt2__memory_reads__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Memory Reads Distribution Gen9 :: GtiRingAccesses */ +#define kblgt2__memory_reads__gti_ring_accesses__read \ + bdw__memory_reads__gti_ring_accesses__read + +/* Memory Reads Distribution Gen9 :: Early Hi-Depth Test Fails */ +#define kblgt2__memory_reads__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Memory Reads Distribution Gen9 :: VS Threads Dispatched */ +#define kblgt2__memory_reads__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Memory Reads Distribution Gen9 :: FS Threads Dispatched */ +#define kblgt2__memory_reads__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Memory Reads Distribution Gen9 :: GtiL3Bank3Reads */ +#define kblgt2__memory_reads__gti_l3_bank3_reads__read \ + hsw__memory_reads__gpu_core_clocks__read + +/* Memory Reads Distribution Gen9 :: Shader Barrier Messages */ +#define kblgt2__memory_reads__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Memory Reads Distribution Gen9 :: GtiRsMemoryReads */ +#define kblgt2__memory_reads__gti_rs_memory_reads__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Memory Reads Distribution Gen9 :: Sampler Texels */ +#define kblgt2__memory_reads__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Memory Reads Distribution Gen9 :: Pixels Failing Tests */ +#define kblgt2__memory_reads__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Memory Reads Distribution Gen9 :: GtiHizMemoryReads */ +#define kblgt2__memory_reads__gti_hiz_memory_reads__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* Memory Reads Distribution Gen9 :: GPU Time Elapsed */ +#define kblgt2__memory_reads__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Memory Reads Distribution Gen9 :: AVG GPU Core Frequency */ +#define kblgt2__memory_reads__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Memory Reads Distribution Gen9 :: AVG GPU Core Frequency */ +#define kblgt2__memory_reads__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Memory Reads Distribution Gen9 :: Sampler Texels Misses */ +#define kblgt2__memory_reads__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Memory Reads Distribution Gen9 :: GtiRccMemoryReads */ +#define kblgt2__memory_reads__gti_rcc_memory_reads__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* Memory Reads Distribution Gen9 :: CS Threads Dispatched */ +#define kblgt2__memory_reads__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Memory Reads Distribution Gen9 :: SLM Bytes Read */ +#define kblgt2__memory_reads__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Memory Reads Distribution Gen9 :: GtiL3Bank1Reads */ +#define kblgt2__memory_reads__gti_l3_bank1_reads__read \ + hsw__memory_reads__gti_memory_reads__read + +/* Memory Reads Distribution Gen9 :: GPU Busy */ +#define kblgt2__memory_reads__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Memory Reads Distribution Gen9 :: GtiCmdStreamerMemoryReads */ +#define kblgt2__memory_reads__gti_cmd_streamer_memory_reads__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* Memory Reads Distribution Gen9 :: GtiL3Bank2Reads */ +#define kblgt2__memory_reads__gti_l3_bank2_reads__read \ + hsw__memory_reads__llc_read_accesses__read + +/* Memory Reads Distribution Gen9 :: GtiMemoryReads */ +#define kblgt2__memory_reads__gti_memory_reads__read \ + hsw__compute_extended__typed_writes0__read + +/* Memory Reads Distribution Gen9 :: Rasterized Pixels */ +#define kblgt2__memory_reads__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Memory Reads Distribution Gen9 :: GtiRczMemoryReads */ +#define kblgt2__memory_reads__gti_rcz_memory_reads__read \ + hsw__compute_extended__gpu_clocks__read + +/* Memory Reads Distribution Gen9 :: DS Threads Dispatched */ +#define kblgt2__memory_reads__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Memory Reads Distribution Gen9 :: Samples Written */ +#define kblgt2__memory_reads__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Memory Reads Distribution Gen9 :: EU Stall */ +#define kblgt2__memory_reads__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Memory Reads Distribution Gen9 :: Samples Blended */ +#define kblgt2__memory_reads__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Memory Reads Distribution Gen9 :: Early Depth Test Fails */ +#define kblgt2__memory_reads__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Memory Reads Distribution Gen9 :: GtiMscMemoryReads */ +#define kblgt2__memory_reads__gti_msc_memory_reads__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* Memory Reads Distribution Gen9 :: GtiVfMemoryReads */ +#define kblgt2__memory_reads__gti_vf_memory_reads__read \ + hsw__compute_extended__eu_untyped_writes0__read + +/* Memory Reads Distribution Gen9 :: GtiStcMemoryReads */ +#define kblgt2__memory_reads__gti_stc_memory_reads__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* Memory Reads Distribution Gen9 :: Shader Memory Accesses */ +#define kblgt2__memory_reads__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Memory Reads Distribution Gen9 :: HS Threads Dispatched */ +#define kblgt2__memory_reads__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Memory Reads Distribution Gen9 :: Samples Killed in FS */ +#define kblgt2__memory_reads__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Memory Reads Distribution Gen9 :: SLM Bytes Written */ +#define kblgt2__memory_reads__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Memory Reads Distribution Gen9 :: GtiL3Reads */ +#define kblgt2__memory_reads__gti_l3_reads__read \ + bdw__memory_reads__gti_l3_reads__read + +/* Memory Reads Distribution Gen9 :: Shader Atomic Memory Accesses */ +#define kblgt2__memory_reads__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Memory Writes Distribution Gen9 :: GPU Core Clocks */ +#define kblgt2__memory_writes__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Memory Writes Distribution Gen9 :: EU Active */ +#define kblgt2__memory_writes__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Memory Writes Distribution Gen9 :: GtiMemoryWrites */ +#define kblgt2__memory_writes__gti_memory_writes__read \ + hsw__compute_extended__typed_writes0__read + +/* Memory Writes Distribution Gen9 :: GS Threads Dispatched */ +#define kblgt2__memory_writes__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Memory Writes Distribution Gen9 :: GtiRingAccesses */ +#define kblgt2__memory_writes__gti_ring_accesses__read \ + bdw__memory_reads__gti_ring_accesses__read + +/* Memory Writes Distribution Gen9 :: Early Hi-Depth Test Fails */ +#define kblgt2__memory_writes__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Memory Writes Distribution Gen9 :: VS Threads Dispatched */ +#define kblgt2__memory_writes__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Memory Writes Distribution Gen9 :: FS Threads Dispatched */ +#define kblgt2__memory_writes__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Memory Writes Distribution Gen9 :: GtiMscMemoryWrites */ +#define kblgt2__memory_writes__gti_msc_memory_writes__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* Memory Writes Distribution Gen9 :: Shader Barrier Messages */ +#define kblgt2__memory_writes__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Memory Writes Distribution Gen9 :: GtiCmdStreamerMemoryWrites */ +#define kblgt2__memory_writes__gti_cmd_streamer_memory_writes__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* Memory Writes Distribution Gen9 :: Sampler Texels */ +#define kblgt2__memory_writes__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Memory Writes Distribution Gen9 :: Pixels Failing Tests */ +#define kblgt2__memory_writes__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Memory Writes Distribution Gen9 :: GtiL3Bank0Writes */ +#define kblgt2__memory_writes__gti_l3_bank0_writes__read \ + hsw__compute_extended__typed_atomics0__read + +/* Memory Writes Distribution Gen9 :: GtiL3Bank1Writes */ +#define kblgt2__memory_writes__gti_l3_bank1_writes__read \ + hsw__memory_reads__gti_memory_reads__read + +/* Memory Writes Distribution Gen9 :: GtiL3Bank2Writes */ +#define kblgt2__memory_writes__gti_l3_bank2_writes__read \ + hsw__memory_reads__llc_read_accesses__read + +/* Memory Writes Distribution Gen9 :: GtiL3Bank3Writes */ +#define kblgt2__memory_writes__gti_l3_bank3_writes__read \ + hsw__memory_reads__gpu_core_clocks__read + +/* Memory Writes Distribution Gen9 :: GtiL3Writes */ +#define kblgt2__memory_writes__gti_l3_writes__read \ + bdw__memory_reads__gti_l3_reads__read + +/* Memory Writes Distribution Gen9 :: GPU Time Elapsed */ +#define kblgt2__memory_writes__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Memory Writes Distribution Gen9 :: AVG GPU Core Frequency */ +#define kblgt2__memory_writes__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Memory Writes Distribution Gen9 :: AVG GPU Core Frequency */ +#define kblgt2__memory_writes__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Memory Writes Distribution Gen9 :: Sampler Texels Misses */ +#define kblgt2__memory_writes__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Memory Writes Distribution Gen9 :: CS Threads Dispatched */ +#define kblgt2__memory_writes__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Memory Writes Distribution Gen9 :: SLM Bytes Read */ +#define kblgt2__memory_writes__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Memory Writes Distribution Gen9 :: GtiRccMemoryWrites */ +#define kblgt2__memory_writes__gti_rcc_memory_writes__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* Memory Writes Distribution Gen9 :: GtiSoMemoryWrites */ +#define kblgt2__memory_writes__gti_so_memory_writes__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Memory Writes Distribution Gen9 :: GPU Busy */ +#define kblgt2__memory_writes__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Memory Writes Distribution Gen9 :: GtiStcMemoryWrites */ +#define kblgt2__memory_writes__gti_stc_memory_writes__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* Memory Writes Distribution Gen9 :: Rasterized Pixels */ +#define kblgt2__memory_writes__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Memory Writes Distribution Gen9 :: DS Threads Dispatched */ +#define kblgt2__memory_writes__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Memory Writes Distribution Gen9 :: Samples Written */ +#define kblgt2__memory_writes__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Memory Writes Distribution Gen9 :: EU Stall */ +#define kblgt2__memory_writes__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Memory Writes Distribution Gen9 :: Samples Blended */ +#define kblgt2__memory_writes__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Memory Writes Distribution Gen9 :: Early Depth Test Fails */ +#define kblgt2__memory_writes__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Memory Writes Distribution Gen9 :: Shader Memory Accesses */ +#define kblgt2__memory_writes__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Memory Writes Distribution Gen9 :: HS Threads Dispatched */ +#define kblgt2__memory_writes__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Memory Writes Distribution Gen9 :: GtiRczMemoryWrites */ +#define kblgt2__memory_writes__gti_rcz_memory_writes__read \ + hsw__compute_extended__gpu_clocks__read + +/* Memory Writes Distribution Gen9 :: SLM Bytes Written */ +#define kblgt2__memory_writes__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Memory Writes Distribution Gen9 :: L3 Shader Throughput */ +#define kblgt2__memory_writes__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Memory Writes Distribution Gen9 :: Samples Killed in FS */ +#define kblgt2__memory_writes__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Memory Writes Distribution Gen9 :: GtiHizMemoryWrites */ +#define kblgt2__memory_writes__gti_hiz_memory_writes__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* Memory Writes Distribution Gen9 :: Shader Atomic Memory Accesses */ +#define kblgt2__memory_writes__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Extended Gen9 :: GPU Core Clocks */ +#define kblgt2__compute_extended__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Extended Gen9 :: EU Active */ +#define kblgt2__compute_extended__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Compute Metrics Extended Gen9 :: EU Both FPU Pipes Active */ +#define kblgt2__compute_extended__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Compute Metrics Extended Gen9 :: EU FPU0 Pipe Active */ +#define kblgt2__compute_extended__fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Compute Metrics Extended Gen9 :: EU FPU1 Pipe Active */ +#define kblgt2__compute_extended__fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Compute Metrics Extended Gen9 :: EU AVG IPC Rate */ +#define kblgt2__compute_extended__eu_avg_ipc_rate__read \ + bdw__compute_basic__eu_avg_ipc_rate__read + +/* Compute Metrics Extended Gen9 :: Typed Writes 0 */ +#define kblgt2__compute_extended__typed_writes0__read \ + hsw__compute_extended__typed_writes0__read + +/* Compute Metrics Extended Gen9 :: EuTypedAtomics0 */ +#define kblgt2__compute_extended__eu_typed_atomics0__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* Compute Metrics Extended Gen9 :: Typed Atomics 0 */ +#define kblgt2__compute_extended__typed_atomics0__read \ + hsw__compute_extended__typed_atomics0__read + +/* Compute Metrics Extended Gen9 :: TypedAtomicsPerCacheLine */ +#define kblgt2__compute_extended__typed_atomics_per_cache_line__read \ + hsw__compute_extended__typed_atomics_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: EuUntypedReads0 */ +#define kblgt2__compute_extended__eu_untyped_reads0__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* Compute Metrics Extended Gen9 :: Untyped Writes 0 */ +#define kblgt2__compute_extended__untyped_writes0__read \ + hsw__compute_extended__untyped_writes0__read + +/* Compute Metrics Extended Gen9 :: EuUntypedAtomics0 */ +#define kblgt2__compute_extended__eu_untyped_atomics0__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* Compute Metrics Extended Gen9 :: EuUntypedWrites0 */ +#define kblgt2__compute_extended__eu_untyped_writes0__read \ + hsw__compute_extended__eu_untyped_writes0__read + +/* Compute Metrics Extended Gen9 :: EuA64UntypedWrites0 */ +#define kblgt2__compute_extended__eu_a64_untyped_writes0__read \ + hsw__compute_extended__gpu_clocks__read + +/* Compute Metrics Extended Gen9 :: UntypedWritesPerCacheLine */ +#define kblgt2__compute_extended__untyped_writes_per_cache_line__read \ + bdw__compute_extended__untyped_writes_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: Shader Barrier Messages */ +#define kblgt2__compute_extended__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Compute Metrics Extended Gen9 :: Sampler Texels */ +#define kblgt2__compute_extended__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Compute Metrics Extended Gen9 :: GPU Time Elapsed */ +#define kblgt2__compute_extended__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics Extended Gen9 :: AVG GPU Core Frequency */ +#define kblgt2__compute_extended__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics Extended Gen9 :: AVG GPU Core Frequency */ +#define kblgt2__compute_extended__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics Extended Gen9 :: Sampler Texels Misses */ +#define kblgt2__compute_extended__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Compute Metrics Extended Gen9 :: CS Threads Dispatched */ +#define kblgt2__compute_extended__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Compute Metrics Extended Gen9 :: SLM Bytes Read */ +#define kblgt2__compute_extended__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Compute Metrics Extended Gen9 :: EuTypedWrites0 */ +#define kblgt2__compute_extended__eu_typed_writes0__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* Compute Metrics Extended Gen9 :: TypedWritesPerCacheLine */ +#define kblgt2__compute_extended__typed_writes_per_cache_line__read \ + hsw__compute_extended__typed_writes_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: Typed Reads 0 */ +#define kblgt2__compute_extended__typed_reads0__read \ + hsw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Extended Gen9 :: Untyped Reads 0 */ +#define kblgt2__compute_extended__untyped_reads0__read \ + hsw__compute_extended__untyped_reads0__read + +/* Compute Metrics Extended Gen9 :: EuA64UntypedReads0 */ +#define kblgt2__compute_extended__eu_a64_untyped_reads0__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* Compute Metrics Extended Gen9 :: EU Thread Occupancy */ +#define kblgt2__compute_extended__eu_thread_occupancy__read \ + bdw__compute_basic__eu_thread_occupancy__read + +/* Compute Metrics Extended Gen9 :: EU Stall */ +#define kblgt2__compute_extended__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics Extended Gen9 :: EuTypedReads0 */ +#define kblgt2__compute_extended__eu_typed_reads0__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Compute Metrics Extended Gen9 :: UntypedReadsPerCacheLine */ +#define kblgt2__compute_extended__untyped_reads_per_cache_line__read \ + bdw__compute_extended__untyped_reads_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: Shader Memory Accesses */ +#define kblgt2__compute_extended__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Compute Metrics Extended Gen9 :: TypedReadsPerCacheLine */ +#define kblgt2__compute_extended__typed_reads_per_cache_line__read \ + hsw__compute_extended__typed_reads_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: SLM Bytes Written */ +#define kblgt2__compute_extended__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Compute Metrics Extended Gen9 :: L3 Shader Throughput */ +#define kblgt2__compute_extended__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Compute Metrics Extended Gen9 :: Shader Atomic Memory Accesses */ +#define kblgt2__compute_extended__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Extended Gen9 :: EU Send Pipe Active */ +#define kblgt2__compute_extended__eu_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Compute Metrics L3 Cache Gen9 :: GPU Core Clocks */ +#define kblgt2__compute_l3_cache__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics L3 Cache Gen9 :: EU Active */ +#define kblgt2__compute_l3_cache__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 03 Accesses */ +#define kblgt2__compute_l3_cache__l3_bank03_accesses__read \ + bdw__compute_l3_cache__l3_bank03_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Accesses */ +#define kblgt2__compute_l3_cache__l3_accesses__read \ + sklgt2__compute_l3_cache__l3_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: EU Both FPU Pipes Active */ +#define kblgt2__compute_l3_cache__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Sampler Throughput */ +#define kblgt2__compute_l3_cache__l3_sampler_throughput__read \ + chv__render_basic__l3_sampler_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Pipe Active */ +#define kblgt2__compute_l3_cache__fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Pipe Active */ +#define kblgt2__compute_l3_cache__fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Compute Metrics L3 Cache Gen9 :: EU AVG IPC Rate */ +#define kblgt2__compute_l3_cache__eu_avg_ipc_rate__read \ + bdw__compute_basic__eu_avg_ipc_rate__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Binary Instruction */ +#define kblgt2__compute_l3_cache__eu_binary_fpu0_instruction__read \ + bdw__render_basic__ps_send_active__read + +/* Compute Metrics L3 Cache Gen9 :: GS Threads Dispatched */ +#define kblgt2__compute_l3_cache__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Compute Metrics L3 Cache Gen9 :: Shader Memory Accesses */ +#define kblgt2__compute_l3_cache__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: Early Hi-Depth Test Fails */ +#define kblgt2__compute_l3_cache__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Compute Metrics L3 Cache Gen9 :: VS Threads Dispatched */ +#define kblgt2__compute_l3_cache__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Compute Metrics L3 Cache Gen9 :: FS Threads Dispatched */ +#define kblgt2__compute_l3_cache__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Hybrid Instruction */ +#define kblgt2__compute_l3_cache__eu_hybrid_fpu0_instruction__read \ + bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Misses */ +#define kblgt2__compute_l3_cache__l3_misses__read \ + bdw__compute_l3_cache__l3_misses__read + +/* Compute Metrics L3 Cache Gen9 :: Shader Barrier Messages */ +#define kblgt2__compute_l3_cache__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 Accesses */ +#define kblgt2__compute_l3_cache__l3_bank00_accesses__read \ + bdw__compute_l3_cache__l3_bank00_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Move Instruction */ +#define kblgt2__compute_l3_cache__eu_move_fpu0_instruction__read \ + bdw__compute_l3_cache__eu_move_fpu0_instruction__read + +/* Compute Metrics L3 Cache Gen9 :: Sampler Texels */ +#define kblgt2__compute_l3_cache__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Compute Metrics L3 Cache Gen9 :: Pixels Failing Tests */ +#define kblgt2__compute_l3_cache__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Hybrid Instruction */ +#define kblgt2__compute_l3_cache__eu_hybrid_fpu1_instruction__read \ + bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read + +/* Compute Metrics L3 Cache Gen9 :: GPU Time Elapsed */ +#define kblgt2__compute_l3_cache__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics L3 Cache Gen9 :: AVG GPU Core Frequency */ +#define kblgt2__compute_l3_cache__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics L3 Cache Gen9 :: AVG GPU Core Frequency */ +#define kblgt2__compute_l3_cache__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics L3 Cache Gen9 :: Sampler Texels Misses */ +#define kblgt2__compute_l3_cache__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Compute Metrics L3 Cache Gen9 :: CS Threads Dispatched */ +#define kblgt2__compute_l3_cache__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Compute Metrics L3 Cache Gen9 :: SLM Bytes Read */ +#define kblgt2__compute_l3_cache__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Compute Metrics L3 Cache Gen9 :: GTI Read Throughput */ +#define kblgt2__compute_l3_cache__gti_read_throughput__read \ + bdw__render_basic__gti_read_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: GTI L3 Throughput */ +#define kblgt2__compute_l3_cache__gti_l3_throughput__read \ + bdw__compute_l3_cache__gti_l3_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 IC Accesses */ +#define kblgt2__compute_l3_cache__l3_bank00_ic_accesses__read \ + bdw__compute_l3_cache__l3_bank00_ic_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 IC Hits */ +#define kblgt2__compute_l3_cache__l3_bank00_ic_hits__read \ + bdw__compute_l3_cache__l3_bank00_ic_hits__read + +/* Compute Metrics L3 Cache Gen9 :: Sampler Accesses */ +#define kblgt2__compute_l3_cache__sampler_accesses__read \ + bdw__render_pipe_profile__sampler_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 01 Accesses */ +#define kblgt2__compute_l3_cache__l3_bank01_accesses__read \ + bdw__compute_l3_cache__l3_bank01_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: GPU Busy */ +#define kblgt2__compute_l3_cache__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Ternary Instruction */ +#define kblgt2__compute_l3_cache__eu_ternary_fpu0_instruction__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Compute Metrics L3 Cache Gen9 :: Shader Atomic Memory Accesses */ +#define kblgt2__compute_l3_cache__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics L3 Cache Gen9 :: Rasterized Pixels */ +#define kblgt2__compute_l3_cache__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Compute Metrics L3 Cache Gen9 :: DS Threads Dispatched */ +#define kblgt2__compute_l3_cache__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Compute Metrics L3 Cache Gen9 :: Samples Written */ +#define kblgt2__compute_l3_cache__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Move Instruction */ +#define kblgt2__compute_l3_cache__eu_move_fpu1_instruction__read \ + bdw__compute_l3_cache__eu_move_fpu1_instruction__read + +/* Compute Metrics L3 Cache Gen9 :: EU Stall */ +#define kblgt2__compute_l3_cache__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics L3 Cache Gen9 :: Samples Blended */ +#define kblgt2__compute_l3_cache__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Compute Metrics L3 Cache Gen9 :: Early Depth Test Fails */ +#define kblgt2__compute_l3_cache__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 02 Accesses */ +#define kblgt2__compute_l3_cache__l3_bank02_accesses__read \ + bdw__compute_l3_cache__l3_bank02_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: HS Threads Dispatched */ +#define kblgt2__compute_l3_cache__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Total Throughput */ +#define kblgt2__compute_l3_cache__l3_total_throughput__read \ + sklgt2__compute_l3_cache__l3_total_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: GTI Write Throughput */ +#define kblgt2__compute_l3_cache__gti_write_throughput__read \ + hsw__render_basic__gti_write_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: SLM Bytes Written */ +#define kblgt2__compute_l3_cache__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Shader Throughput */ +#define kblgt2__compute_l3_cache__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: Samples Killed in FS */ +#define kblgt2__compute_l3_cache__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Binary Instruction */ +#define kblgt2__compute_l3_cache__eu_binary_fpu1_instruction__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Ternary Instruction */ +#define kblgt2__compute_l3_cache__eu_ternary_fpu1_instruction__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Compute Metrics L3 Cache Gen9 :: EU Send Pipe Active */ +#define kblgt2__compute_l3_cache__eu_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set HDCAndSF :: GPU Core Clocks */ +#define kblgt2__hdc_and_sf__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set HDCAndSF :: EU Active */ +#define kblgt2__hdc_and_sf__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set HDCAndSF :: EU Both FPU Pipes Active */ +#define kblgt2__hdc_and_sf__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set HDCAndSF :: VS Send Pipe Active */ +#define kblgt2__hdc_and_sf__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set HDCAndSF :: VS FPU1 Pipe Active */ +#define kblgt2__hdc_and_sf__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set HDCAndSF :: GS Threads Dispatched */ +#define kblgt2__hdc_and_sf__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set HDCAndSF :: Early Hi-Depth Test Fails */ +#define kblgt2__hdc_and_sf__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set HDCAndSF :: FS Both FPU Active */ +#define kblgt2__hdc_and_sf__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set HDCAndSF :: VS Threads Dispatched */ +#define kblgt2__hdc_and_sf__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set HDCAndSF :: Polygon Data Ready */ +#define kblgt2__hdc_and_sf__poly_data_ready__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set HDCAndSF :: FS Threads Dispatched */ +#define kblgt2__hdc_and_sf__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set HDCAndSF :: Shader Barrier Messages */ +#define kblgt2__hdc_and_sf__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set HDCAndSF :: Sampler Texels */ +#define kblgt2__hdc_and_sf__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set HDCAndSF :: Pixels Failing Tests */ +#define kblgt2__hdc_and_sf__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set HDCAndSF :: GPU Time Elapsed */ +#define kblgt2__hdc_and_sf__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set HDCAndSF :: AVG GPU Core Frequency */ +#define kblgt2__hdc_and_sf__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set HDCAndSF :: AVG GPU Core Frequency */ +#define kblgt2__hdc_and_sf__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set HDCAndSF :: Sampler Texels Misses */ +#define kblgt2__hdc_and_sf__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */ +#define kblgt2__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read \ + bdw__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read + +/* Metric set HDCAndSF :: CS Threads Dispatched */ +#define kblgt2__hdc_and_sf__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss2) */ +#define kblgt2__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read \ + bdw__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read + +/* Metric set HDCAndSF :: SLM Bytes Read */ +#define kblgt2__hdc_and_sf__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set HDCAndSF :: PS FPU1 Pipe Active */ +#define kblgt2__hdc_and_sf__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set HDCAndSF :: PS Send Pipeline Active */ +#define kblgt2__hdc_and_sf__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set HDCAndSF :: VS FPU0 Pipe Active */ +#define kblgt2__hdc_and_sf__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set HDCAndSF :: GPU Busy */ +#define kblgt2__hdc_and_sf__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set HDCAndSF :: Rasterized Pixels */ +#define kblgt2__hdc_and_sf__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set HDCAndSF :: PS FPU0 Pipe Active */ +#define kblgt2__hdc_and_sf__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set HDCAndSF :: DS Threads Dispatched */ +#define kblgt2__hdc_and_sf__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set HDCAndSF :: Samples Written */ +#define kblgt2__hdc_and_sf__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set HDCAndSF :: EU Stall */ +#define kblgt2__hdc_and_sf__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set HDCAndSF :: Samples Blended */ +#define kblgt2__hdc_and_sf__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set HDCAndSF :: Early Depth Test Fails */ +#define kblgt2__hdc_and_sf__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set HDCAndSF :: Shader Memory Accesses */ +#define kblgt2__hdc_and_sf__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set HDCAndSF :: HS Threads Dispatched */ +#define kblgt2__hdc_and_sf__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set HDCAndSF :: SLM Bytes Written */ +#define kblgt2__hdc_and_sf__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set HDCAndSF :: L3 Shader Throughput */ +#define kblgt2__hdc_and_sf__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set HDCAndSF :: Samples Killed in FS */ +#define kblgt2__hdc_and_sf__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */ +#define kblgt2__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read \ + bdw__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read + +/* Metric set HDCAndSF :: Shader Atomic Memory Accesses */ +#define kblgt2__hdc_and_sf__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set L3_1 :: GPU Core Clocks */ +#define kblgt2__l3_1__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set L3_1 :: EU Active */ +#define kblgt2__l3_1__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set L3_1 :: Slice0 L3 Bank1 Active */ +#define kblgt2__l3_1__l30_bank1_active__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set L3_1 :: EU Both FPU Pipes Active */ +#define kblgt2__l3_1__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set L3_1 :: VS Send Pipe Active */ +#define kblgt2__l3_1__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set L3_1 :: VS FPU1 Pipe Active */ +#define kblgt2__l3_1__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set L3_1 :: GS Threads Dispatched */ +#define kblgt2__l3_1__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set L3_1 :: Early Hi-Depth Test Fails */ +#define kblgt2__l3_1__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set L3_1 :: FS Both FPU Active */ +#define kblgt2__l3_1__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set L3_1 :: VS Threads Dispatched */ +#define kblgt2__l3_1__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set L3_1 :: Slice0 L3 Bank1 Stalled */ +#define kblgt2__l3_1__l30_bank1_stalled__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Metric set L3_1 :: FS Threads Dispatched */ +#define kblgt2__l3_1__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set L3_1 :: Shader Barrier Messages */ +#define kblgt2__l3_1__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set L3_1 :: Sampler Texels */ +#define kblgt2__l3_1__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set L3_1 :: Pixels Failing Tests */ +#define kblgt2__l3_1__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set L3_1 :: GPU Time Elapsed */ +#define kblgt2__l3_1__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set L3_1 :: AVG GPU Core Frequency */ +#define kblgt2__l3_1__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set L3_1 :: AVG GPU Core Frequency */ +#define kblgt2__l3_1__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set L3_1 :: Sampler Texels Misses */ +#define kblgt2__l3_1__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set L3_1 :: CS Threads Dispatched */ +#define kblgt2__l3_1__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set L3_1 :: SLM Bytes Read */ +#define kblgt2__l3_1__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set L3_1 :: PS FPU1 Pipe Active */ +#define kblgt2__l3_1__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set L3_1 :: PS Send Pipeline Active */ +#define kblgt2__l3_1__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set L3_1 :: VS FPU0 Pipe Active */ +#define kblgt2__l3_1__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set L3_1 :: GPU Busy */ +#define kblgt2__l3_1__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set L3_1 :: Slice0 L3 Bank0 Active */ +#define kblgt2__l3_1__l30_bank0_active__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set L3_1 :: Rasterized Pixels */ +#define kblgt2__l3_1__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set L3_1 :: PS FPU0 Pipe Active */ +#define kblgt2__l3_1__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set L3_1 :: Slice0 L3 Bank0 Stalled */ +#define kblgt2__l3_1__l30_bank0_stalled__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set L3_1 :: DS Threads Dispatched */ +#define kblgt2__l3_1__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set L3_1 :: Samples Written */ +#define kblgt2__l3_1__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set L3_1 :: EU Stall */ +#define kblgt2__l3_1__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set L3_1 :: Samples Blended */ +#define kblgt2__l3_1__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set L3_1 :: Early Depth Test Fails */ +#define kblgt2__l3_1__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set L3_1 :: Shader Memory Accesses */ +#define kblgt2__l3_1__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set L3_1 :: HS Threads Dispatched */ +#define kblgt2__l3_1__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set L3_1 :: SLM Bytes Written */ +#define kblgt2__l3_1__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set L3_1 :: L3 Shader Throughput */ +#define kblgt2__l3_1__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set L3_1 :: Samples Killed in FS */ +#define kblgt2__l3_1__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set L3_1 :: Shader Atomic Memory Accesses */ +#define kblgt2__l3_1__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set L3_2 :: GPU Core Clocks */ +#define kblgt2__l3_2__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set L3_2 :: EU Active */ +#define kblgt2__l3_2__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set L3_2 :: EU Both FPU Pipes Active */ +#define kblgt2__l3_2__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set L3_2 :: VS Send Pipe Active */ +#define kblgt2__l3_2__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set L3_2 :: VS FPU1 Pipe Active */ +#define kblgt2__l3_2__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set L3_2 :: GS Threads Dispatched */ +#define kblgt2__l3_2__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set L3_2 :: Early Hi-Depth Test Fails */ +#define kblgt2__l3_2__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set L3_2 :: FS Both FPU Active */ +#define kblgt2__l3_2__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set L3_2 :: VS Threads Dispatched */ +#define kblgt2__l3_2__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set L3_2 :: FS Threads Dispatched */ +#define kblgt2__l3_2__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set L3_2 :: Shader Barrier Messages */ +#define kblgt2__l3_2__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set L3_2 :: Sampler Texels */ +#define kblgt2__l3_2__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set L3_2 :: Pixels Failing Tests */ +#define kblgt2__l3_2__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set L3_2 :: GPU Time Elapsed */ +#define kblgt2__l3_2__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set L3_2 :: AVG GPU Core Frequency */ +#define kblgt2__l3_2__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set L3_2 :: AVG GPU Core Frequency */ +#define kblgt2__l3_2__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set L3_2 :: Sampler Texels Misses */ +#define kblgt2__l3_2__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set L3_2 :: CS Threads Dispatched */ +#define kblgt2__l3_2__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set L3_2 :: SLM Bytes Read */ +#define kblgt2__l3_2__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set L3_2 :: PS FPU1 Pipe Active */ +#define kblgt2__l3_2__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set L3_2 :: Slice0 L3 Bank2 Stalled */ +#define kblgt2__l3_2__l30_bank2_stalled__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set L3_2 :: PS Send Pipeline Active */ +#define kblgt2__l3_2__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set L3_2 :: VS FPU0 Pipe Active */ +#define kblgt2__l3_2__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set L3_2 :: GPU Busy */ +#define kblgt2__l3_2__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set L3_2 :: Slice0 L3 Bank2 Active */ +#define kblgt2__l3_2__l30_bank2_active__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set L3_2 :: Rasterized Pixels */ +#define kblgt2__l3_2__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set L3_2 :: PS FPU0 Pipe Active */ +#define kblgt2__l3_2__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set L3_2 :: DS Threads Dispatched */ +#define kblgt2__l3_2__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set L3_2 :: Samples Written */ +#define kblgt2__l3_2__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set L3_2 :: EU Stall */ +#define kblgt2__l3_2__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set L3_2 :: Samples Blended */ +#define kblgt2__l3_2__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set L3_2 :: Early Depth Test Fails */ +#define kblgt2__l3_2__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set L3_2 :: Shader Memory Accesses */ +#define kblgt2__l3_2__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set L3_2 :: HS Threads Dispatched */ +#define kblgt2__l3_2__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set L3_2 :: SLM Bytes Written */ +#define kblgt2__l3_2__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set L3_2 :: L3 Shader Throughput */ +#define kblgt2__l3_2__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set L3_2 :: Samples Killed in FS */ +#define kblgt2__l3_2__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set L3_2 :: Shader Atomic Memory Accesses */ +#define kblgt2__l3_2__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set L3_3 :: GPU Core Clocks */ +#define kblgt2__l3_3__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set L3_3 :: EU Active */ +#define kblgt2__l3_3__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set L3_3 :: EU Both FPU Pipes Active */ +#define kblgt2__l3_3__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set L3_3 :: VS Send Pipe Active */ +#define kblgt2__l3_3__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set L3_3 :: VS FPU1 Pipe Active */ +#define kblgt2__l3_3__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set L3_3 :: GS Threads Dispatched */ +#define kblgt2__l3_3__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set L3_3 :: Early Hi-Depth Test Fails */ +#define kblgt2__l3_3__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set L3_3 :: FS Both FPU Active */ +#define kblgt2__l3_3__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set L3_3 :: VS Threads Dispatched */ +#define kblgt2__l3_3__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set L3_3 :: FS Threads Dispatched */ +#define kblgt2__l3_3__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set L3_3 :: Slice0 L3 Bank3 Stalled */ +#define kblgt2__l3_3__l30_bank3_stalled__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set L3_3 :: Shader Barrier Messages */ +#define kblgt2__l3_3__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set L3_3 :: Sampler Texels */ +#define kblgt2__l3_3__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set L3_3 :: Pixels Failing Tests */ +#define kblgt2__l3_3__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set L3_3 :: GPU Time Elapsed */ +#define kblgt2__l3_3__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set L3_3 :: AVG GPU Core Frequency */ +#define kblgt2__l3_3__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set L3_3 :: AVG GPU Core Frequency */ +#define kblgt2__l3_3__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set L3_3 :: Sampler Texels Misses */ +#define kblgt2__l3_3__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set L3_3 :: CS Threads Dispatched */ +#define kblgt2__l3_3__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set L3_3 :: SLM Bytes Read */ +#define kblgt2__l3_3__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set L3_3 :: PS FPU1 Pipe Active */ +#define kblgt2__l3_3__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set L3_3 :: Slice0 L3 Bank3 Active */ +#define kblgt2__l3_3__l30_bank3_active__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set L3_3 :: PS Send Pipeline Active */ +#define kblgt2__l3_3__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set L3_3 :: VS FPU0 Pipe Active */ +#define kblgt2__l3_3__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set L3_3 :: GPU Busy */ +#define kblgt2__l3_3__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set L3_3 :: Rasterized Pixels */ +#define kblgt2__l3_3__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set L3_3 :: PS FPU0 Pipe Active */ +#define kblgt2__l3_3__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set L3_3 :: DS Threads Dispatched */ +#define kblgt2__l3_3__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set L3_3 :: Samples Written */ +#define kblgt2__l3_3__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set L3_3 :: EU Stall */ +#define kblgt2__l3_3__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set L3_3 :: Samples Blended */ +#define kblgt2__l3_3__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set L3_3 :: Early Depth Test Fails */ +#define kblgt2__l3_3__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set L3_3 :: Shader Memory Accesses */ +#define kblgt2__l3_3__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set L3_3 :: HS Threads Dispatched */ +#define kblgt2__l3_3__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set L3_3 :: SLM Bytes Written */ +#define kblgt2__l3_3__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set L3_3 :: L3 Shader Throughput */ +#define kblgt2__l3_3__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set L3_3 :: Samples Killed in FS */ +#define kblgt2__l3_3__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set L3_3 :: Shader Atomic Memory Accesses */ +#define kblgt2__l3_3__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */ +#define kblgt2__rasterizer_and_pixel_backend__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set RasterizerAndPixelBackend :: EU Active */ +#define kblgt2__rasterizer_and_pixel_backend__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set RasterizerAndPixelBackend :: EU Both FPU Pipes Active */ +#define kblgt2__rasterizer_and_pixel_backend__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set RasterizerAndPixelBackend :: VS Send Pipe Active */ +#define kblgt2__rasterizer_and_pixel_backend__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set RasterizerAndPixelBackend :: VS FPU1 Pipe Active */ +#define kblgt2__rasterizer_and_pixel_backend__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */ +#define kblgt2__rasterizer_and_pixel_backend__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */ +#define kblgt2__rasterizer_and_pixel_backend__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set RasterizerAndPixelBackend :: FS Both FPU Active */ +#define kblgt2__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */ +#define kblgt2__rasterizer_and_pixel_backend__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */ +#define kblgt2__rasterizer_and_pixel_backend__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Pixel Values Ready */ +#define kblgt2__rasterizer_and_pixel_backend__pixel_values0_ready__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */ +#define kblgt2__rasterizer_and_pixel_backend__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set RasterizerAndPixelBackend :: Sampler Texels */ +#define kblgt2__rasterizer_and_pixel_backend__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */ +#define kblgt2__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */ +#define kblgt2__rasterizer_and_pixel_backend__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ +#define kblgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ +#define kblgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */ +#define kblgt2__rasterizer_and_pixel_backend__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */ +#define kblgt2__rasterizer_and_pixel_backend__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */ +#define kblgt2__rasterizer_and_pixel_backend__rasterizer0_input_available__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Post-EarlyZ Pixel Data Ready */ +#define kblgt2__rasterizer_and_pixel_backend__pixel_data0_ready__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */ +#define kblgt2__rasterizer_and_pixel_backend__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set RasterizerAndPixelBackend :: PS FPU1 Pipe Active */ +#define kblgt2__rasterizer_and_pixel_backend__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set RasterizerAndPixelBackend :: PS Send Pipeline Active */ +#define kblgt2__rasterizer_and_pixel_backend__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set RasterizerAndPixelBackend :: VS FPU0 Pipe Active */ +#define kblgt2__rasterizer_and_pixel_backend__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set RasterizerAndPixelBackend :: GPU Busy */ +#define kblgt2__rasterizer_and_pixel_backend__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */ +#define kblgt2__rasterizer_and_pixel_backend__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set RasterizerAndPixelBackend :: PS FPU0 Pipe Active */ +#define kblgt2__rasterizer_and_pixel_backend__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */ +#define kblgt2__rasterizer_and_pixel_backend__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set RasterizerAndPixelBackend :: Samples Written */ +#define kblgt2__rasterizer_and_pixel_backend__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set RasterizerAndPixelBackend :: EU Stall */ +#define kblgt2__rasterizer_and_pixel_backend__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */ +#define kblgt2__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set RasterizerAndPixelBackend :: Samples Blended */ +#define kblgt2__rasterizer_and_pixel_backend__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */ +#define kblgt2__rasterizer_and_pixel_backend__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */ +#define kblgt2__rasterizer_and_pixel_backend__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */ +#define kblgt2__rasterizer_and_pixel_backend__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */ +#define kblgt2__rasterizer_and_pixel_backend__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */ +#define kblgt2__rasterizer_and_pixel_backend__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */ +#define kblgt2__rasterizer_and_pixel_backend__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 PS Output Available */ +#define kblgt2__rasterizer_and_pixel_backend__ps_output0_available__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */ +#define kblgt2__rasterizer_and_pixel_backend__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set Sampler :: GPU Core Clocks */ +#define kblgt2__sampler__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set Sampler :: EU Active */ +#define kblgt2__sampler__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set Sampler :: Slice0 Subslice2 Input Available */ +#define kblgt2__sampler__sampler02_input_available__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set Sampler :: EU Both FPU Pipes Active */ +#define kblgt2__sampler__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set Sampler :: VS Send Pipe Active */ +#define kblgt2__sampler__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set Sampler :: Slice0 Subslice0 Input Available */ +#define kblgt2__sampler__sampler00_input_available__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Metric set Sampler :: VS FPU1 Pipe Active */ +#define kblgt2__sampler__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set Sampler :: GS Threads Dispatched */ +#define kblgt2__sampler__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set Sampler :: Early Hi-Depth Test Fails */ +#define kblgt2__sampler__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set Sampler :: FS Both FPU Active */ +#define kblgt2__sampler__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set Sampler :: VS Threads Dispatched */ +#define kblgt2__sampler__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set Sampler :: Slice0 Subslice2 Sampler Output Ready */ +#define kblgt2__sampler__sampler02_output_ready__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set Sampler :: FS Threads Dispatched */ +#define kblgt2__sampler__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set Sampler :: Shader Barrier Messages */ +#define kblgt2__sampler__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set Sampler :: Slice0 Subslice1 Input Available */ +#define kblgt2__sampler__sampler01_input_available__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set Sampler :: Sampler Texels */ +#define kblgt2__sampler__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set Sampler :: Pixels Failing Tests */ +#define kblgt2__sampler__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set Sampler :: GPU Time Elapsed */ +#define kblgt2__sampler__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set Sampler :: AVG GPU Core Frequency */ +#define kblgt2__sampler__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set Sampler :: AVG GPU Core Frequency */ +#define kblgt2__sampler__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set Sampler :: Sampler Texels Misses */ +#define kblgt2__sampler__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set Sampler :: CS Threads Dispatched */ +#define kblgt2__sampler__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set Sampler :: SLM Bytes Read */ +#define kblgt2__sampler__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set Sampler :: PS FPU1 Pipe Active */ +#define kblgt2__sampler__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set Sampler :: PS Send Pipeline Active */ +#define kblgt2__sampler__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set Sampler :: VS FPU0 Pipe Active */ +#define kblgt2__sampler__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set Sampler :: GPU Busy */ +#define kblgt2__sampler__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set Sampler :: Rasterized Pixels */ +#define kblgt2__sampler__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set Sampler :: PS FPU0 Pipe Active */ +#define kblgt2__sampler__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set Sampler :: DS Threads Dispatched */ +#define kblgt2__sampler__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set Sampler :: Samples Written */ +#define kblgt2__sampler__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set Sampler :: EU Stall */ +#define kblgt2__sampler__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set Sampler :: Samples Blended */ +#define kblgt2__sampler__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set Sampler :: Early Depth Test Fails */ +#define kblgt2__sampler__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set Sampler :: Slice0 Subslice0 Sampler Output Ready */ +#define kblgt2__sampler__sampler00_output_ready__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set Sampler :: Slice0 Subslice1 Sampler Output Ready */ +#define kblgt2__sampler__sampler01_output_ready__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set Sampler :: Shader Memory Accesses */ +#define kblgt2__sampler__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set Sampler :: HS Threads Dispatched */ +#define kblgt2__sampler__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set Sampler :: SLM Bytes Written */ +#define kblgt2__sampler__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set Sampler :: L3 Shader Throughput */ +#define kblgt2__sampler__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set Sampler :: Samples Killed in FS */ +#define kblgt2__sampler__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set Sampler :: Shader Atomic Memory Accesses */ +#define kblgt2__sampler__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set TDL_1 :: GPU Core Clocks */ +#define kblgt2__tdl_1__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set TDL_1 :: EU Active */ +#define kblgt2__tdl_1__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set TDL_1 :: EU Both FPU Pipes Active */ +#define kblgt2__tdl_1__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set TDL_1 :: VS Send Pipe Active */ +#define kblgt2__tdl_1__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set TDL_1 :: VS FPU1 Pipe Active */ +#define kblgt2__tdl_1__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set TDL_1 :: GS Threads Dispatched */ +#define kblgt2__tdl_1__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set TDL_1 :: Early Hi-Depth Test Fails */ +#define kblgt2__tdl_1__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set TDL_1 :: FS Both FPU Active */ +#define kblgt2__tdl_1__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set TDL_1 :: VS Threads Dispatched */ +#define kblgt2__tdl_1__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set TDL_1 :: FS Threads Dispatched */ +#define kblgt2__tdl_1__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice2 */ +#define kblgt2__tdl_1__non_ps_thread02_ready_for_dispatch__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Metric set TDL_1 :: Shader Barrier Messages */ +#define kblgt2__tdl_1__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_1 :: Sampler Texels */ +#define kblgt2__tdl_1__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set TDL_1 :: Pixels Failing Tests */ +#define kblgt2__tdl_1__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set TDL_1 :: GPU Time Elapsed */ +#define kblgt2__tdl_1__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set TDL_1 :: AVG GPU Core Frequency */ +#define kblgt2__tdl_1__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set TDL_1 :: AVG GPU Core Frequency */ +#define kblgt2__tdl_1__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set TDL_1 :: Sampler Texels Misses */ +#define kblgt2__tdl_1__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice0 */ +#define kblgt2__tdl_1__non_ps_thread00_ready_for_dispatch__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Metric set TDL_1 :: CS Threads Dispatched */ +#define kblgt2__tdl_1__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set TDL_1 :: SLM Bytes Read */ +#define kblgt2__tdl_1__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set TDL_1 :: PS FPU1 Pipe Active */ +#define kblgt2__tdl_1__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set TDL_1 :: PS Send Pipeline Active */ +#define kblgt2__tdl_1__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set TDL_1 :: VS FPU0 Pipe Active */ +#define kblgt2__tdl_1__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set TDL_1 :: GPU Busy */ +#define kblgt2__tdl_1__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice0 */ +#define kblgt2__tdl_1__ps_thread00_ready_for_dispatch__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set TDL_1 :: Rasterized Pixels */ +#define kblgt2__tdl_1__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set TDL_1 :: PS FPU0 Pipe Active */ +#define kblgt2__tdl_1__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set TDL_1 :: DS Threads Dispatched */ +#define kblgt2__tdl_1__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set TDL_1 :: Samples Written */ +#define kblgt2__tdl_1__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set TDL_1 :: EU Stall */ +#define kblgt2__tdl_1__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set TDL_1 :: Samples Blended */ +#define kblgt2__tdl_1__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set TDL_1 :: Early Depth Test Fails */ +#define kblgt2__tdl_1__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice1 */ +#define kblgt2__tdl_1__ps_thread01_ready_for_dispatch__read \ + bdw__render_pipe_profile__cl_bottleneck__read + +/* Metric set TDL_1 :: Shader Memory Accesses */ +#define kblgt2__tdl_1__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set TDL_1 :: HS Threads Dispatched */ +#define kblgt2__tdl_1__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice2 */ +#define kblgt2__tdl_1__ps_thread02_ready_for_dispatch__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Metric set TDL_1 :: SLM Bytes Written */ +#define kblgt2__tdl_1__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set TDL_1 :: L3 Shader Throughput */ +#define kblgt2__tdl_1__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set TDL_1 :: Samples Killed in FS */ +#define kblgt2__tdl_1__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set TDL_1 :: Shader Atomic Memory Accesses */ +#define kblgt2__tdl_1__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice1 */ +#define kblgt2__tdl_1__non_ps_thread01_ready_for_dispatch__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set TDL_2 :: GPU Core Clocks */ +#define kblgt2__tdl_2__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set TDL_2 :: EU Active */ +#define kblgt2__tdl_2__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set TDL_2 :: EU Both FPU Pipes Active */ +#define kblgt2__tdl_2__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set TDL_2 :: VS Send Pipe Active */ +#define kblgt2__tdl_2__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set TDL_2 :: VS FPU1 Pipe Active */ +#define kblgt2__tdl_2__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set TDL_2 :: GS Threads Dispatched */ +#define kblgt2__tdl_2__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set TDL_2 :: Early Hi-Depth Test Fails */ +#define kblgt2__tdl_2__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set TDL_2 :: FS Both FPU Active */ +#define kblgt2__tdl_2__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set TDL_2 :: VS Threads Dispatched */ +#define kblgt2__tdl_2__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set TDL_2 :: FS Threads Dispatched */ +#define kblgt2__tdl_2__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set TDL_2 :: Shader Barrier Messages */ +#define kblgt2__tdl_2__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_2 :: Sampler Texels */ +#define kblgt2__tdl_2__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set TDL_2 :: Pixels Failing Tests */ +#define kblgt2__tdl_2__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 0 */ +#define kblgt2__tdl_2__thread_header01_ready_port0__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 1 */ +#define kblgt2__tdl_2__thread_header01_ready_port1__read \ + bdw__render_pipe_profile__ds_stall__read + +/* Metric set TDL_2 :: GPU Time Elapsed */ +#define kblgt2__tdl_2__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set TDL_2 :: AVG GPU Core Frequency */ +#define kblgt2__tdl_2__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set TDL_2 :: AVG GPU Core Frequency */ +#define kblgt2__tdl_2__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set TDL_2 :: Sampler Texels Misses */ +#define kblgt2__tdl_2__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set TDL_2 :: CS Threads Dispatched */ +#define kblgt2__tdl_2__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set TDL_2 :: SLM Bytes Read */ +#define kblgt2__tdl_2__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set TDL_2 :: PS FPU1 Pipe Active */ +#define kblgt2__tdl_2__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set TDL_2 :: PS Send Pipeline Active */ +#define kblgt2__tdl_2__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set TDL_2 :: VS FPU0 Pipe Active */ +#define kblgt2__tdl_2__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set TDL_2 :: GPU Busy */ +#define kblgt2__tdl_2__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 1 */ +#define kblgt2__tdl_2__thread_header02_ready_port1__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 0 */ +#define kblgt2__tdl_2__thread_header02_ready_port0__read \ + bdw__render_pipe_profile__so_stall__read + +/* Metric set TDL_2 :: Rasterized Pixels */ +#define kblgt2__tdl_2__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set TDL_2 :: PS FPU0 Pipe Active */ +#define kblgt2__tdl_2__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set TDL_2 :: DS Threads Dispatched */ +#define kblgt2__tdl_2__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set TDL_2 :: Samples Written */ +#define kblgt2__tdl_2__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set TDL_2 :: EU Stall */ +#define kblgt2__tdl_2__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set TDL_2 :: Samples Blended */ +#define kblgt2__tdl_2__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set TDL_2 :: Early Depth Test Fails */ +#define kblgt2__tdl_2__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_2 :: Shader Memory Accesses */ +#define kblgt2__tdl_2__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set TDL_2 :: HS Threads Dispatched */ +#define kblgt2__tdl_2__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set TDL_2 :: SLM Bytes Written */ +#define kblgt2__tdl_2__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set TDL_2 :: L3 Shader Throughput */ +#define kblgt2__tdl_2__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set TDL_2 :: Samples Killed in FS */ +#define kblgt2__tdl_2__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 0 */ +#define kblgt2__tdl_2__thread_header00_ready_port0__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set TDL_2 :: Shader Atomic Memory Accesses */ +#define kblgt2__tdl_2__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 1 */ +#define kblgt2__tdl_2__thread_header00_ready_port1__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Compute Metrics Extra Gen9 :: GPU Core Clocks */ +#define kblgt2__compute_extra__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Extra Gen9 :: EU FPU1 Pipe Active */ +#define kblgt2__compute_extra__fpu1_active__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics Extra Gen9 :: GPU Time Elapsed */ +#define kblgt2__compute_extra__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics Extra Gen9 :: AVG GPU Core Frequency */ +#define kblgt2__compute_extra__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics Extra Gen9 :: AVG GPU Core Frequency */ +#define kblgt2__compute_extra__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics Extra Gen9 :: EU FPU1 Pipe Active including Ext Math */ +#define kblgt2__compute_extra__fpu1_active_adjusted__read \ + sklgt2__compute_extra__fpu1_active_adjusted__read + +/* Media Vme Pipe Gen9 :: GPU Core Clocks */ +#define kblgt2__vme_pipe__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Media Vme Pipe Gen9 :: EU Active */ +#define kblgt2__vme_pipe__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Media Vme Pipe Gen9 :: EU Both FPU Pipes Active */ +#define kblgt2__vme_pipe__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Media Vme Pipe Gen9 :: GPU Time Elapsed */ +#define kblgt2__vme_pipe__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Media Vme Pipe Gen9 :: AVG GPU Core Frequency */ +#define kblgt2__vme_pipe__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Media Vme Pipe Gen9 :: AVG GPU Core Frequency */ +#define kblgt2__vme_pipe__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Media Vme Pipe Gen9 :: CS Threads Dispatched */ +#define kblgt2__vme_pipe__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Media Vme Pipe Gen9 :: EU Thread Occupancy */ +#define kblgt2__vme_pipe__eu_thread_occupancy__read \ + bdw__vme_pipe__eu_thread_occupancy__read + +/* Media Vme Pipe Gen9 :: EU Stall */ +#define kblgt2__vme_pipe__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Media Vme Pipe Gen9 :: VME Busy */ +#define kblgt2__vme_pipe__vme_busy__read \ + bdw__vme_pipe__vme_busy__read + +/* Media Vme Pipe Gen9 :: GPU Busy */ +#define kblgt2__vme_pipe__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Gpu Rings Busyness :: GPU Core Clocks */ +#define kblgt2__gpu_busyness__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Gpu Rings Busyness :: Vebox Ring Busy */ +#define kblgt2__gpu_busyness__vebox_busy__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Gpu Rings Busyness :: GPU Time Elapsed */ +#define kblgt2__gpu_busyness__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Gpu Rings Busyness :: AVG GPU Core Frequency */ +#define kblgt2__gpu_busyness__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Gpu Rings Busyness :: AVG GPU Core Frequency */ +#define kblgt2__gpu_busyness__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Gpu Rings Busyness :: Render Ring Busy */ +#define kblgt2__gpu_busyness__render_busy__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Gpu Rings Busyness :: Vdbox0 Ring Busy */ +#define kblgt2__gpu_busyness__vdbox0_busy__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Gpu Rings Busyness :: Blitter Ring Busy */ +#define kblgt2__gpu_busyness__blitter_busy__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Gpu Rings Busyness :: AnyRingBusy */ +#define kblgt2__gpu_busyness__any_ring_busy__read \ + bdw__render_basic__sampler0_busy__read + +/* MDAPI testing set Gen9.5 :: TestCounter7 */ +#define kblgt2__test_oa__counter7__read \ + hsw__compute_extended__gpu_clocks__read + +/* MDAPI testing set Gen9.5 :: GPU Time Elapsed */ +#define kblgt2__test_oa__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* MDAPI testing set Gen9.5 :: GPU Core Clocks */ +#define kblgt2__test_oa__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* MDAPI testing set Gen9.5 :: AVG GPU Core Frequency */ +#define kblgt2__test_oa__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* MDAPI testing set Gen9.5 :: AVG GPU Core Frequency */ +#define kblgt2__test_oa__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* MDAPI testing set Gen9.5 :: TestCounter8 */ +#define kblgt2__test_oa__counter8__read \ + hsw__memory_reads__gpu_core_clocks__read + +/* MDAPI testing set Gen9.5 :: TestCounter4 */ +#define kblgt2__test_oa__counter4__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* MDAPI testing set Gen9.5 :: TestCounter5 */ +#define kblgt2__test_oa__counter5__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* MDAPI testing set Gen9.5 :: TestCounter6 */ +#define kblgt2__test_oa__counter6__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* MDAPI testing set Gen9.5 :: TestCounter3 */ +#define kblgt2__test_oa__counter3__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* MDAPI testing set Gen9.5 :: TestCounter0 */ +#define kblgt2__test_oa__counter0__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* MDAPI testing set Gen9.5 :: TestCounter1 */ +#define kblgt2__test_oa__counter1__read \ + hsw__compute_extended__eu_untyped_writes0__read + +/* MDAPI testing set Gen9.5 :: TestCounter2 */ +#define kblgt2__test_oa__counter2__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Render Metrics Basic Gen9 :: GPU Core Clocks */ +#define kblgt3__render_basic__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Render Metrics Basic Gen9 :: EU Active */ +#define kblgt3__render_basic__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Render Metrics Basic Gen9 :: L3 Misses */ +#define kblgt3__render_basic__l3_misses__read \ + hsw__compute_extended__typed_atomics0__read + +/* Render Metrics Basic Gen9 :: GTI L3 Throughput */ +#define kblgt3__render_basic__gti_l3_throughput__read \ + hsw__render_basic__gti_l3_throughput__read + +/* Render Metrics Basic Gen9 :: EU Both FPU Pipes Active */ +#define kblgt3__render_basic__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Render Metrics Basic Gen9 :: Sampler Cache Misses */ +#define kblgt3__render_basic__sampler_l1_misses__read \ + bdw__render_basic__sampler_l1_misses__read + +/* Render Metrics Basic Gen9 :: VS Send Pipe Active */ +#define kblgt3__render_basic__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Render Metrics Basic Gen9 :: Sampler 1 Bottleneck */ +#define kblgt3__render_basic__sampler1_bottleneck__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Render Metrics Basic Gen9 :: VS FPU1 Pipe Active */ +#define kblgt3__render_basic__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Render Metrics Basic Gen9 :: GS Threads Dispatched */ +#define kblgt3__render_basic__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Render Metrics Basic Gen9 :: L3 Sampler Throughput */ +#define kblgt3__render_basic__l3_sampler_throughput__read \ + bdw__render_basic__l3_sampler_throughput__read + +/* Render Metrics Basic Gen9 :: Early Hi-Depth Test Fails */ +#define kblgt3__render_basic__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Render Metrics Basic Gen9 :: FS Both FPU Active */ +#define kblgt3__render_basic__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Render Metrics Basic Gen9 :: VS Threads Dispatched */ +#define kblgt3__render_basic__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Render Metrics Basic Gen9 :: FS Threads Dispatched */ +#define kblgt3__render_basic__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Render Metrics Basic Gen9 :: Sampler 0 Busy */ +#define kblgt3__render_basic__sampler0_busy__read \ + bdw__render_basic__sampler0_busy__read + +/* Render Metrics Basic Gen9 :: Sampler 1 Busy */ +#define kblgt3__render_basic__sampler1_busy__read \ + bdw__render_basic__sampler1_busy__read + +/* Render Metrics Basic Gen9 :: Samplers Busy */ +#define kblgt3__render_basic__samplers_busy__read \ + bdw__render_basic__samplers_busy__read + +/* Render Metrics Basic Gen9 :: GTI Fixed Pipe Throughput */ +#define kblgt3__render_basic__gti_vf_throughput__read \ + bdw__render_basic__gti_vf_throughput__read + +/* Render Metrics Basic Gen9 :: Shader Barrier Messages */ +#define kblgt3__render_basic__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Render Metrics Basic Gen9 :: Sampler 0 Bottleneck */ +#define kblgt3__render_basic__sampler0_bottleneck__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Render Metrics Basic Gen9 :: Sampler Texels */ +#define kblgt3__render_basic__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Render Metrics Basic Gen9 :: Pixels Failing Tests */ +#define kblgt3__render_basic__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Render Metrics Basic Gen9 :: GPU Time Elapsed */ +#define kblgt3__render_basic__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Render Metrics Basic Gen9 :: AVG GPU Core Frequency */ +#define kblgt3__render_basic__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Render Metrics Basic Gen9 :: AVG GPU Core Frequency */ +#define kblgt3__render_basic__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Render Metrics Basic Gen9 :: Sampler Texels Misses */ +#define kblgt3__render_basic__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Render Metrics Basic Gen9 :: CS Threads Dispatched */ +#define kblgt3__render_basic__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Render Metrics Basic Gen9 :: Shader Memory Accesses */ +#define kblgt3__render_basic__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Render Metrics Basic Gen9 :: L3 Lookup Accesses w/o IC */ +#define kblgt3__render_basic__l3_lookups__read \ + bdw__render_basic__l3_lookups__read + +/* Render Metrics Basic Gen9 :: SLM Bytes Read */ +#define kblgt3__render_basic__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Render Metrics Basic Gen9 :: GTI Read Throughput */ +#define kblgt3__render_basic__gti_read_throughput__read \ + bdw__render_basic__gti_read_throughput__read + +/* Render Metrics Basic Gen9 :: PS FPU1 Pipe Active */ +#define kblgt3__render_basic__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Render Metrics Basic Gen9 :: PS Send Pipeline Active */ +#define kblgt3__render_basic__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Render Metrics Basic Gen9 :: Rasterized Pixels */ +#define kblgt3__render_basic__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Render Metrics Basic Gen9 :: GPU Busy */ +#define kblgt3__render_basic__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Render Metrics Basic Gen9 :: GTI Depth Throughput */ +#define kblgt3__render_basic__gti_depth_throughput__read \ + bdw__render_basic__gti_depth_throughput__read + +/* Render Metrics Basic Gen9 :: VS FPU0 Pipe Active */ +#define kblgt3__render_basic__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Render Metrics Basic Gen9 :: PS FPU0 Pipe Active */ +#define kblgt3__render_basic__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Render Metrics Basic Gen9 :: DS Threads Dispatched */ +#define kblgt3__render_basic__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Render Metrics Basic Gen9 :: Samples Written */ +#define kblgt3__render_basic__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Render Metrics Basic Gen9 :: EU Stall */ +#define kblgt3__render_basic__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Render Metrics Basic Gen9 :: Samples Blended */ +#define kblgt3__render_basic__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Render Metrics Basic Gen9 :: Early Depth Test Fails */ +#define kblgt3__render_basic__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Render Metrics Basic Gen9 :: Samplers Bottleneck */ +#define kblgt3__render_basic__sampler_bottleneck__read \ + bdw__render_basic__sampler_bottleneck__read + +/* Render Metrics Basic Gen9 :: GTI HDC TLB Lookup Throughput */ +#define kblgt3__render_basic__gti_hdc_lookups_throughput__read \ + bdw__render_basic__gti_hdc_lookups_throughput__read + +/* Render Metrics Basic Gen9 :: GTI RCC Throughput */ +#define kblgt3__render_basic__gti_rcc_throughput__read \ + bdw__render_basic__gti_rcc_throughput__read + +/* Render Metrics Basic Gen9 :: HS Threads Dispatched */ +#define kblgt3__render_basic__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Render Metrics Basic Gen9 :: GTI Write Throughput */ +#define kblgt3__render_basic__gti_write_throughput__read \ + hsw__render_basic__gti_write_throughput__read + +/* Render Metrics Basic Gen9 :: SLM Bytes Written */ +#define kblgt3__render_basic__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Render Metrics Basic Gen9 :: L3 Shader Throughput */ +#define kblgt3__render_basic__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Render Metrics Basic Gen9 :: Samples Killed in FS */ +#define kblgt3__render_basic__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Render Metrics Basic Gen9 :: Shader Atomic Memory Accesses */ +#define kblgt3__render_basic__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Basic Gen9 :: GPU Core Clocks */ +#define kblgt3__compute_basic__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Basic Gen9 :: EU Active */ +#define kblgt3__compute_basic__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Compute Metrics Basic Gen9 :: Untyped Bytes Read */ +#define kblgt3__compute_basic__untyped_bytes_read__read \ + bdw__compute_basic__untyped_bytes_read__read + +/* Compute Metrics Basic Gen9 :: EU Both FPU Pipes Active */ +#define kblgt3__compute_basic__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Compute Metrics Basic Gen9 :: Typed Bytes Written */ +#define kblgt3__compute_basic__typed_bytes_written__read \ + bdw__compute_basic__typed_bytes_written__read + +/* Compute Metrics Basic Gen9 :: EU FPU0 Pipe Active */ +#define kblgt3__compute_basic__fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Compute Metrics Basic Gen9 :: EU FPU1 Pipe Active */ +#define kblgt3__compute_basic__fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Compute Metrics Basic Gen9 :: EU AVG IPC Rate */ +#define kblgt3__compute_basic__eu_avg_ipc_rate__read \ + bdw__compute_basic__eu_avg_ipc_rate__read + +/* Compute Metrics Basic Gen9 :: GS Threads Dispatched */ +#define kblgt3__compute_basic__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Compute Metrics Basic Gen9 :: Early Hi-Depth Test Fails */ +#define kblgt3__compute_basic__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Compute Metrics Basic Gen9 :: VS Threads Dispatched */ +#define kblgt3__compute_basic__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Compute Metrics Basic Gen9 :: FS Threads Dispatched */ +#define kblgt3__compute_basic__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Compute Metrics Basic Gen9 :: Shader Barrier Messages */ +#define kblgt3__compute_basic__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Compute Metrics Basic Gen9 :: Sampler Texels */ +#define kblgt3__compute_basic__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Compute Metrics Basic Gen9 :: Pixels Failing Tests */ +#define kblgt3__compute_basic__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Compute Metrics Basic Gen9 :: GPU Time Elapsed */ +#define kblgt3__compute_basic__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics Basic Gen9 :: AVG GPU Core Frequency */ +#define kblgt3__compute_basic__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics Basic Gen9 :: AVG GPU Core Frequency */ +#define kblgt3__compute_basic__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics Basic Gen9 :: Sampler Texels Misses */ +#define kblgt3__compute_basic__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Compute Metrics Basic Gen9 :: CS Threads Dispatched */ +#define kblgt3__compute_basic__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Compute Metrics Basic Gen9 :: SLM Bytes Read */ +#define kblgt3__compute_basic__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Compute Metrics Basic Gen9 :: GTI Read Throughput */ +#define kblgt3__compute_basic__gti_read_throughput__read \ + hsw__render_basic__gti_l3_throughput__read + +/* Compute Metrics Basic Gen9 :: Untyped Writes */ +#define kblgt3__compute_basic__untyped_bytes_written__read \ + bdw__compute_basic__untyped_bytes_written__read + +/* Compute Metrics Basic Gen9 :: GPU Busy */ +#define kblgt3__compute_basic__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Compute Metrics Basic Gen9 :: Rasterized Pixels */ +#define kblgt3__compute_basic__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Compute Metrics Basic Gen9 :: Typed Bytes Read */ +#define kblgt3__compute_basic__typed_bytes_read__read \ + bdw__compute_basic__typed_bytes_read__read + +/* Compute Metrics Basic Gen9 :: DS Threads Dispatched */ +#define kblgt3__compute_basic__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Compute Metrics Basic Gen9 :: EU Thread Occupancy */ +#define kblgt3__compute_basic__eu_thread_occupancy__read \ + bdw__compute_basic__eu_thread_occupancy__read + +/* Compute Metrics Basic Gen9 :: EU Stall */ +#define kblgt3__compute_basic__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics Basic Gen9 :: Samples Blended */ +#define kblgt3__compute_basic__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Compute Metrics Basic Gen9 :: Early Depth Test Fails */ +#define kblgt3__compute_basic__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Compute Metrics Basic Gen9 :: Shader Memory Accesses */ +#define kblgt3__compute_basic__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Compute Metrics Basic Gen9 :: HS Threads Dispatched */ +#define kblgt3__compute_basic__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Compute Metrics Basic Gen9 :: GTI Write Throughput */ +#define kblgt3__compute_basic__gti_write_throughput__read \ + bdw__render_basic__gti_hdc_lookups_throughput__read + +/* Compute Metrics Basic Gen9 :: SLM Bytes Written */ +#define kblgt3__compute_basic__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Compute Metrics Basic Gen9 :: L3 Shader Throughput */ +#define kblgt3__compute_basic__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Compute Metrics Basic Gen9 :: Samples Killed in FS */ +#define kblgt3__compute_basic__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Compute Metrics Basic Gen9 :: Samples Written */ +#define kblgt3__compute_basic__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Compute Metrics Basic Gen9 :: Shader Atomic Memory Accesses */ +#define kblgt3__compute_basic__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Basic Gen9 :: EU Send Pipe Active */ +#define kblgt3__compute_basic__eu_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Core Clocks */ +#define kblgt3__render_pipe_profile__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: EU Active */ +#define kblgt3__render_pipe_profile__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: VS Bottleneck */ +#define kblgt3__render_pipe_profile__vs_bottleneck__read \ + bdw__render_basic__sampler0_busy__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Hi-Depth Bottleneck */ +#define kblgt3__render_pipe_profile__hi_depth_bottleneck__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GS Bottleneck */ +#define kblgt3__render_pipe_profile__gs_bottleneck__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GS Threads Dispatched */ +#define kblgt3__render_pipe_profile__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Early Hi-Depth Test Fails */ +#define kblgt3__render_pipe_profile__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: VS Threads Dispatched */ +#define kblgt3__render_pipe_profile__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: FS Threads Dispatched */ +#define kblgt3__render_pipe_profile__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: BC Bottleneck */ +#define kblgt3__render_pipe_profile__bc_bottleneck__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: HS Stall */ +#define kblgt3__render_pipe_profile__hs_stall__read \ + bdw__render_pipe_profile__hs_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Barrier Messages */ +#define kblgt3__render_pipe_profile__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Sampler Texels */ +#define kblgt3__render_pipe_profile__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Pixels Failing Tests */ +#define kblgt3__render_pipe_profile__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Time Elapsed */ +#define kblgt3__render_pipe_profile__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: AVG GPU Core Frequency */ +#define kblgt3__render_pipe_profile__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: AVG GPU Core Frequency */ +#define kblgt3__render_pipe_profile__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Sampler Texels Misses */ +#define kblgt3__render_pipe_profile__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: CS Threads Dispatched */ +#define kblgt3__render_pipe_profile__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: VF Bottleneck */ +#define kblgt3__render_pipe_profile__vf_bottleneck__read \ + bdw__render_pipe_profile__vf_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SLM Bytes Read */ +#define kblgt3__render_pipe_profile__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Strip-Fans Bottleneck */ +#define kblgt3__render_pipe_profile__sf_bottleneck__read \ + bdw__render_pipe_profile__sf_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SF Stall */ +#define kblgt3__render_pipe_profile__sf_stall__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Busy */ +#define kblgt3__render_pipe_profile__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: HS Bottleneck */ +#define kblgt3__render_pipe_profile__hs_bottleneck__read \ + bdw__render_basic__sampler1_busy__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: CL Stall */ +#define kblgt3__render_pipe_profile__cl_stall__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SO Bottleneck */ +#define kblgt3__render_pipe_profile__so_bottleneck__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Rasterized Pixels */ +#define kblgt3__render_pipe_profile__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: DS Threads Dispatched */ +#define kblgt3__render_pipe_profile__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Written */ +#define kblgt3__render_pipe_profile__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: DS Bottleneck */ +#define kblgt3__render_pipe_profile__ds_bottleneck__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: EU Stall */ +#define kblgt3__render_pipe_profile__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Clipper Bottleneck */ +#define kblgt3__render_pipe_profile__cl_bottleneck__read \ + bdw__render_pipe_profile__cl_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: DS Stall */ +#define kblgt3__render_pipe_profile__ds_stall__read \ + bdw__render_pipe_profile__ds_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Early Depth Bottleneck */ +#define kblgt3__render_pipe_profile__early_depth_bottleneck__read \ + bdw__render_pipe_profile__early_depth_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Blended */ +#define kblgt3__render_pipe_profile__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Early Depth Test Fails */ +#define kblgt3__render_pipe_profile__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Memory Accesses */ +#define kblgt3__render_pipe_profile__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: HS Threads Dispatched */ +#define kblgt3__render_pipe_profile__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SLM Bytes Written */ +#define kblgt3__render_pipe_profile__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: L3 Shader Throughput */ +#define kblgt3__render_pipe_profile__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Killed in FS */ +#define kblgt3__render_pipe_profile__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SO Stall */ +#define kblgt3__render_pipe_profile__so_stall__read \ + bdw__render_pipe_profile__so_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Atomic Memory Accesses */ +#define kblgt3__render_pipe_profile__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Memory Reads Distribution Gen9 :: GPU Core Clocks */ +#define kblgt3__memory_reads__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Memory Reads Distribution Gen9 :: EU Active */ +#define kblgt3__memory_reads__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Memory Reads Distribution Gen9 :: GtiL3Bank0Reads */ +#define kblgt3__memory_reads__gti_l3_bank0_reads__read \ + hsw__compute_extended__typed_atomics0__read + +/* Memory Reads Distribution Gen9 :: GS Threads Dispatched */ +#define kblgt3__memory_reads__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Memory Reads Distribution Gen9 :: GtiRingAccesses */ +#define kblgt3__memory_reads__gti_ring_accesses__read \ + bdw__memory_reads__gti_ring_accesses__read + +/* Memory Reads Distribution Gen9 :: Early Hi-Depth Test Fails */ +#define kblgt3__memory_reads__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Memory Reads Distribution Gen9 :: VS Threads Dispatched */ +#define kblgt3__memory_reads__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Memory Reads Distribution Gen9 :: FS Threads Dispatched */ +#define kblgt3__memory_reads__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Memory Reads Distribution Gen9 :: GtiL3Bank3Reads */ +#define kblgt3__memory_reads__gti_l3_bank3_reads__read \ + hsw__memory_reads__gpu_core_clocks__read + +/* Memory Reads Distribution Gen9 :: Shader Barrier Messages */ +#define kblgt3__memory_reads__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Memory Reads Distribution Gen9 :: GtiRsMemoryReads */ +#define kblgt3__memory_reads__gti_rs_memory_reads__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Memory Reads Distribution Gen9 :: Sampler Texels */ +#define kblgt3__memory_reads__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Memory Reads Distribution Gen9 :: Pixels Failing Tests */ +#define kblgt3__memory_reads__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Memory Reads Distribution Gen9 :: GtiHizMemoryReads */ +#define kblgt3__memory_reads__gti_hiz_memory_reads__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* Memory Reads Distribution Gen9 :: GPU Time Elapsed */ +#define kblgt3__memory_reads__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Memory Reads Distribution Gen9 :: AVG GPU Core Frequency */ +#define kblgt3__memory_reads__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Memory Reads Distribution Gen9 :: AVG GPU Core Frequency */ +#define kblgt3__memory_reads__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Memory Reads Distribution Gen9 :: Sampler Texels Misses */ +#define kblgt3__memory_reads__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Memory Reads Distribution Gen9 :: GtiRccMemoryReads */ +#define kblgt3__memory_reads__gti_rcc_memory_reads__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* Memory Reads Distribution Gen9 :: CS Threads Dispatched */ +#define kblgt3__memory_reads__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Memory Reads Distribution Gen9 :: SLM Bytes Read */ +#define kblgt3__memory_reads__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Memory Reads Distribution Gen9 :: GtiL3Bank1Reads */ +#define kblgt3__memory_reads__gti_l3_bank1_reads__read \ + hsw__memory_reads__gti_memory_reads__read + +/* Memory Reads Distribution Gen9 :: GPU Busy */ +#define kblgt3__memory_reads__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Memory Reads Distribution Gen9 :: GtiCmdStreamerMemoryReads */ +#define kblgt3__memory_reads__gti_cmd_streamer_memory_reads__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* Memory Reads Distribution Gen9 :: GtiL3Bank2Reads */ +#define kblgt3__memory_reads__gti_l3_bank2_reads__read \ + hsw__memory_reads__llc_read_accesses__read + +/* Memory Reads Distribution Gen9 :: GtiMemoryReads */ +#define kblgt3__memory_reads__gti_memory_reads__read \ + hsw__compute_extended__typed_writes0__read + +/* Memory Reads Distribution Gen9 :: Rasterized Pixels */ +#define kblgt3__memory_reads__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Memory Reads Distribution Gen9 :: GtiRczMemoryReads */ +#define kblgt3__memory_reads__gti_rcz_memory_reads__read \ + hsw__compute_extended__gpu_clocks__read + +/* Memory Reads Distribution Gen9 :: DS Threads Dispatched */ +#define kblgt3__memory_reads__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Memory Reads Distribution Gen9 :: Samples Written */ +#define kblgt3__memory_reads__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Memory Reads Distribution Gen9 :: EU Stall */ +#define kblgt3__memory_reads__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Memory Reads Distribution Gen9 :: Samples Blended */ +#define kblgt3__memory_reads__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Memory Reads Distribution Gen9 :: Early Depth Test Fails */ +#define kblgt3__memory_reads__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Memory Reads Distribution Gen9 :: GtiMscMemoryReads */ +#define kblgt3__memory_reads__gti_msc_memory_reads__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* Memory Reads Distribution Gen9 :: GtiVfMemoryReads */ +#define kblgt3__memory_reads__gti_vf_memory_reads__read \ + hsw__compute_extended__eu_untyped_writes0__read + +/* Memory Reads Distribution Gen9 :: GtiStcMemoryReads */ +#define kblgt3__memory_reads__gti_stc_memory_reads__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* Memory Reads Distribution Gen9 :: Shader Memory Accesses */ +#define kblgt3__memory_reads__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Memory Reads Distribution Gen9 :: HS Threads Dispatched */ +#define kblgt3__memory_reads__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Memory Reads Distribution Gen9 :: Samples Killed in FS */ +#define kblgt3__memory_reads__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Memory Reads Distribution Gen9 :: SLM Bytes Written */ +#define kblgt3__memory_reads__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Memory Reads Distribution Gen9 :: GtiL3Reads */ +#define kblgt3__memory_reads__gti_l3_reads__read \ + bdw__memory_reads__gti_l3_reads__read + +/* Memory Reads Distribution Gen9 :: Shader Atomic Memory Accesses */ +#define kblgt3__memory_reads__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Memory Writes Distribution Gen9 :: GPU Core Clocks */ +#define kblgt3__memory_writes__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Memory Writes Distribution Gen9 :: EU Active */ +#define kblgt3__memory_writes__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Memory Writes Distribution Gen9 :: GtiMemoryWrites */ +#define kblgt3__memory_writes__gti_memory_writes__read \ + hsw__compute_extended__typed_writes0__read + +/* Memory Writes Distribution Gen9 :: GS Threads Dispatched */ +#define kblgt3__memory_writes__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Memory Writes Distribution Gen9 :: GtiRingAccesses */ +#define kblgt3__memory_writes__gti_ring_accesses__read \ + bdw__memory_reads__gti_ring_accesses__read + +/* Memory Writes Distribution Gen9 :: Early Hi-Depth Test Fails */ +#define kblgt3__memory_writes__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Memory Writes Distribution Gen9 :: VS Threads Dispatched */ +#define kblgt3__memory_writes__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Memory Writes Distribution Gen9 :: FS Threads Dispatched */ +#define kblgt3__memory_writes__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Memory Writes Distribution Gen9 :: GtiMscMemoryWrites */ +#define kblgt3__memory_writes__gti_msc_memory_writes__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* Memory Writes Distribution Gen9 :: Shader Barrier Messages */ +#define kblgt3__memory_writes__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Memory Writes Distribution Gen9 :: GtiCmdStreamerMemoryWrites */ +#define kblgt3__memory_writes__gti_cmd_streamer_memory_writes__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* Memory Writes Distribution Gen9 :: Sampler Texels */ +#define kblgt3__memory_writes__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Memory Writes Distribution Gen9 :: Pixels Failing Tests */ +#define kblgt3__memory_writes__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Memory Writes Distribution Gen9 :: GtiL3Bank0Writes */ +#define kblgt3__memory_writes__gti_l3_bank0_writes__read \ + hsw__compute_extended__typed_atomics0__read + +/* Memory Writes Distribution Gen9 :: GtiL3Bank1Writes */ +#define kblgt3__memory_writes__gti_l3_bank1_writes__read \ + hsw__memory_reads__gti_memory_reads__read + +/* Memory Writes Distribution Gen9 :: GtiL3Bank2Writes */ +#define kblgt3__memory_writes__gti_l3_bank2_writes__read \ + hsw__memory_reads__llc_read_accesses__read + +/* Memory Writes Distribution Gen9 :: GtiL3Bank3Writes */ +#define kblgt3__memory_writes__gti_l3_bank3_writes__read \ + hsw__memory_reads__gpu_core_clocks__read + +/* Memory Writes Distribution Gen9 :: GtiL3Writes */ +#define kblgt3__memory_writes__gti_l3_writes__read \ + bdw__memory_reads__gti_l3_reads__read + +/* Memory Writes Distribution Gen9 :: GPU Time Elapsed */ +#define kblgt3__memory_writes__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Memory Writes Distribution Gen9 :: AVG GPU Core Frequency */ +#define kblgt3__memory_writes__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Memory Writes Distribution Gen9 :: AVG GPU Core Frequency */ +#define kblgt3__memory_writes__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Memory Writes Distribution Gen9 :: Sampler Texels Misses */ +#define kblgt3__memory_writes__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Memory Writes Distribution Gen9 :: CS Threads Dispatched */ +#define kblgt3__memory_writes__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Memory Writes Distribution Gen9 :: SLM Bytes Read */ +#define kblgt3__memory_writes__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Memory Writes Distribution Gen9 :: GtiRccMemoryWrites */ +#define kblgt3__memory_writes__gti_rcc_memory_writes__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* Memory Writes Distribution Gen9 :: GtiSoMemoryWrites */ +#define kblgt3__memory_writes__gti_so_memory_writes__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Memory Writes Distribution Gen9 :: GPU Busy */ +#define kblgt3__memory_writes__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Memory Writes Distribution Gen9 :: GtiStcMemoryWrites */ +#define kblgt3__memory_writes__gti_stc_memory_writes__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* Memory Writes Distribution Gen9 :: Rasterized Pixels */ +#define kblgt3__memory_writes__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Memory Writes Distribution Gen9 :: DS Threads Dispatched */ +#define kblgt3__memory_writes__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Memory Writes Distribution Gen9 :: Samples Written */ +#define kblgt3__memory_writes__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Memory Writes Distribution Gen9 :: EU Stall */ +#define kblgt3__memory_writes__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Memory Writes Distribution Gen9 :: Samples Blended */ +#define kblgt3__memory_writes__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Memory Writes Distribution Gen9 :: Early Depth Test Fails */ +#define kblgt3__memory_writes__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Memory Writes Distribution Gen9 :: Shader Memory Accesses */ +#define kblgt3__memory_writes__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Memory Writes Distribution Gen9 :: HS Threads Dispatched */ +#define kblgt3__memory_writes__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Memory Writes Distribution Gen9 :: GtiRczMemoryWrites */ +#define kblgt3__memory_writes__gti_rcz_memory_writes__read \ + hsw__compute_extended__gpu_clocks__read + +/* Memory Writes Distribution Gen9 :: SLM Bytes Written */ +#define kblgt3__memory_writes__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Memory Writes Distribution Gen9 :: L3 Shader Throughput */ +#define kblgt3__memory_writes__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Memory Writes Distribution Gen9 :: Samples Killed in FS */ +#define kblgt3__memory_writes__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Memory Writes Distribution Gen9 :: GtiHizMemoryWrites */ +#define kblgt3__memory_writes__gti_hiz_memory_writes__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* Memory Writes Distribution Gen9 :: Shader Atomic Memory Accesses */ +#define kblgt3__memory_writes__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Extended Gen9 :: GPU Core Clocks */ +#define kblgt3__compute_extended__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Extended Gen9 :: EU Active */ +#define kblgt3__compute_extended__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Compute Metrics Extended Gen9 :: EU Both FPU Pipes Active */ +#define kblgt3__compute_extended__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Compute Metrics Extended Gen9 :: EU FPU0 Pipe Active */ +#define kblgt3__compute_extended__fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Compute Metrics Extended Gen9 :: EU FPU1 Pipe Active */ +#define kblgt3__compute_extended__fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Compute Metrics Extended Gen9 :: EU AVG IPC Rate */ +#define kblgt3__compute_extended__eu_avg_ipc_rate__read \ + bdw__compute_basic__eu_avg_ipc_rate__read + +/* Compute Metrics Extended Gen9 :: Typed Writes 0 */ +#define kblgt3__compute_extended__typed_writes0__read \ + hsw__compute_extended__typed_writes0__read + +/* Compute Metrics Extended Gen9 :: EuTypedAtomics0 */ +#define kblgt3__compute_extended__eu_typed_atomics0__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* Compute Metrics Extended Gen9 :: Typed Atomics 0 */ +#define kblgt3__compute_extended__typed_atomics0__read \ + hsw__compute_extended__typed_atomics0__read + +/* Compute Metrics Extended Gen9 :: TypedAtomicsPerCacheLine */ +#define kblgt3__compute_extended__typed_atomics_per_cache_line__read \ + hsw__compute_extended__typed_atomics_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: EuUntypedReads0 */ +#define kblgt3__compute_extended__eu_untyped_reads0__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* Compute Metrics Extended Gen9 :: Untyped Writes 0 */ +#define kblgt3__compute_extended__untyped_writes0__read \ + hsw__compute_extended__untyped_writes0__read + +/* Compute Metrics Extended Gen9 :: EuUntypedAtomics0 */ +#define kblgt3__compute_extended__eu_untyped_atomics0__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* Compute Metrics Extended Gen9 :: EuUntypedWrites0 */ +#define kblgt3__compute_extended__eu_untyped_writes0__read \ + hsw__compute_extended__eu_untyped_writes0__read + +/* Compute Metrics Extended Gen9 :: EuA64UntypedWrites0 */ +#define kblgt3__compute_extended__eu_a64_untyped_writes0__read \ + hsw__compute_extended__gpu_clocks__read + +/* Compute Metrics Extended Gen9 :: UntypedWritesPerCacheLine */ +#define kblgt3__compute_extended__untyped_writes_per_cache_line__read \ + bdw__compute_extended__untyped_writes_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: Shader Barrier Messages */ +#define kblgt3__compute_extended__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Compute Metrics Extended Gen9 :: Sampler Texels */ +#define kblgt3__compute_extended__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Compute Metrics Extended Gen9 :: GPU Time Elapsed */ +#define kblgt3__compute_extended__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics Extended Gen9 :: AVG GPU Core Frequency */ +#define kblgt3__compute_extended__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics Extended Gen9 :: AVG GPU Core Frequency */ +#define kblgt3__compute_extended__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics Extended Gen9 :: Sampler Texels Misses */ +#define kblgt3__compute_extended__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Compute Metrics Extended Gen9 :: CS Threads Dispatched */ +#define kblgt3__compute_extended__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Compute Metrics Extended Gen9 :: SLM Bytes Read */ +#define kblgt3__compute_extended__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Compute Metrics Extended Gen9 :: EuTypedWrites0 */ +#define kblgt3__compute_extended__eu_typed_writes0__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* Compute Metrics Extended Gen9 :: TypedWritesPerCacheLine */ +#define kblgt3__compute_extended__typed_writes_per_cache_line__read \ + hsw__compute_extended__typed_writes_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: Typed Reads 0 */ +#define kblgt3__compute_extended__typed_reads0__read \ + hsw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Extended Gen9 :: Untyped Reads 0 */ +#define kblgt3__compute_extended__untyped_reads0__read \ + hsw__compute_extended__untyped_reads0__read + +/* Compute Metrics Extended Gen9 :: EuA64UntypedReads0 */ +#define kblgt3__compute_extended__eu_a64_untyped_reads0__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* Compute Metrics Extended Gen9 :: EU Thread Occupancy */ +#define kblgt3__compute_extended__eu_thread_occupancy__read \ + bdw__compute_basic__eu_thread_occupancy__read + +/* Compute Metrics Extended Gen9 :: EU Stall */ +#define kblgt3__compute_extended__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics Extended Gen9 :: EuTypedReads0 */ +#define kblgt3__compute_extended__eu_typed_reads0__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Compute Metrics Extended Gen9 :: UntypedReadsPerCacheLine */ +#define kblgt3__compute_extended__untyped_reads_per_cache_line__read \ + bdw__compute_extended__untyped_reads_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: Shader Memory Accesses */ +#define kblgt3__compute_extended__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Compute Metrics Extended Gen9 :: TypedReadsPerCacheLine */ +#define kblgt3__compute_extended__typed_reads_per_cache_line__read \ + hsw__compute_extended__typed_reads_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: SLM Bytes Written */ +#define kblgt3__compute_extended__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Compute Metrics Extended Gen9 :: L3 Shader Throughput */ +#define kblgt3__compute_extended__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Compute Metrics Extended Gen9 :: Shader Atomic Memory Accesses */ +#define kblgt3__compute_extended__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Extended Gen9 :: EU Send Pipe Active */ +#define kblgt3__compute_extended__eu_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Compute Metrics L3 Cache Gen9 :: GPU Core Clocks */ +#define kblgt3__compute_l3_cache__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics L3 Cache Gen9 :: EU Active */ +#define kblgt3__compute_l3_cache__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 03 Accesses */ +#define kblgt3__compute_l3_cache__l3_bank03_accesses__read \ + bdw__compute_l3_cache__l3_bank03_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Accesses */ +#define kblgt3__compute_l3_cache__l3_accesses__read \ + sklgt2__compute_l3_cache__l3_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: EU Both FPU Pipes Active */ +#define kblgt3__compute_l3_cache__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Sampler Throughput */ +#define kblgt3__compute_l3_cache__l3_sampler_throughput__read \ + chv__render_basic__l3_sampler_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Pipe Active */ +#define kblgt3__compute_l3_cache__fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Pipe Active */ +#define kblgt3__compute_l3_cache__fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Compute Metrics L3 Cache Gen9 :: EU AVG IPC Rate */ +#define kblgt3__compute_l3_cache__eu_avg_ipc_rate__read \ + bdw__compute_basic__eu_avg_ipc_rate__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Binary Instruction */ +#define kblgt3__compute_l3_cache__eu_binary_fpu0_instruction__read \ + bdw__render_basic__ps_send_active__read + +/* Compute Metrics L3 Cache Gen9 :: GS Threads Dispatched */ +#define kblgt3__compute_l3_cache__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Compute Metrics L3 Cache Gen9 :: Shader Memory Accesses */ +#define kblgt3__compute_l3_cache__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: Early Hi-Depth Test Fails */ +#define kblgt3__compute_l3_cache__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Compute Metrics L3 Cache Gen9 :: VS Threads Dispatched */ +#define kblgt3__compute_l3_cache__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Compute Metrics L3 Cache Gen9 :: FS Threads Dispatched */ +#define kblgt3__compute_l3_cache__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Hybrid Instruction */ +#define kblgt3__compute_l3_cache__eu_hybrid_fpu0_instruction__read \ + bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Misses */ +#define kblgt3__compute_l3_cache__l3_misses__read \ + bdw__compute_l3_cache__l3_misses__read + +/* Compute Metrics L3 Cache Gen9 :: Shader Barrier Messages */ +#define kblgt3__compute_l3_cache__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 Accesses */ +#define kblgt3__compute_l3_cache__l3_bank00_accesses__read \ + bdw__compute_l3_cache__l3_bank00_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Move Instruction */ +#define kblgt3__compute_l3_cache__eu_move_fpu0_instruction__read \ + bdw__compute_l3_cache__eu_move_fpu0_instruction__read + +/* Compute Metrics L3 Cache Gen9 :: Sampler Texels */ +#define kblgt3__compute_l3_cache__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Compute Metrics L3 Cache Gen9 :: Pixels Failing Tests */ +#define kblgt3__compute_l3_cache__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Hybrid Instruction */ +#define kblgt3__compute_l3_cache__eu_hybrid_fpu1_instruction__read \ + bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read + +/* Compute Metrics L3 Cache Gen9 :: GPU Time Elapsed */ +#define kblgt3__compute_l3_cache__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics L3 Cache Gen9 :: AVG GPU Core Frequency */ +#define kblgt3__compute_l3_cache__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics L3 Cache Gen9 :: AVG GPU Core Frequency */ +#define kblgt3__compute_l3_cache__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics L3 Cache Gen9 :: Sampler Texels Misses */ +#define kblgt3__compute_l3_cache__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Compute Metrics L3 Cache Gen9 :: CS Threads Dispatched */ +#define kblgt3__compute_l3_cache__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Compute Metrics L3 Cache Gen9 :: SLM Bytes Read */ +#define kblgt3__compute_l3_cache__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Compute Metrics L3 Cache Gen9 :: GTI Read Throughput */ +#define kblgt3__compute_l3_cache__gti_read_throughput__read \ + bdw__render_basic__gti_read_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: GTI L3 Throughput */ +#define kblgt3__compute_l3_cache__gti_l3_throughput__read \ + bdw__compute_l3_cache__gti_l3_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 IC Accesses */ +#define kblgt3__compute_l3_cache__l3_bank00_ic_accesses__read \ + bdw__compute_l3_cache__l3_bank00_ic_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 IC Hits */ +#define kblgt3__compute_l3_cache__l3_bank00_ic_hits__read \ + bdw__compute_l3_cache__l3_bank00_ic_hits__read + +/* Compute Metrics L3 Cache Gen9 :: Sampler Accesses */ +#define kblgt3__compute_l3_cache__sampler_accesses__read \ + bdw__render_pipe_profile__sampler_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 01 Accesses */ +#define kblgt3__compute_l3_cache__l3_bank01_accesses__read \ + bdw__compute_l3_cache__l3_bank01_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: GPU Busy */ +#define kblgt3__compute_l3_cache__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Ternary Instruction */ +#define kblgt3__compute_l3_cache__eu_ternary_fpu0_instruction__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Compute Metrics L3 Cache Gen9 :: Shader Atomic Memory Accesses */ +#define kblgt3__compute_l3_cache__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics L3 Cache Gen9 :: Rasterized Pixels */ +#define kblgt3__compute_l3_cache__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Compute Metrics L3 Cache Gen9 :: DS Threads Dispatched */ +#define kblgt3__compute_l3_cache__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Compute Metrics L3 Cache Gen9 :: Samples Written */ +#define kblgt3__compute_l3_cache__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Move Instruction */ +#define kblgt3__compute_l3_cache__eu_move_fpu1_instruction__read \ + bdw__compute_l3_cache__eu_move_fpu1_instruction__read + +/* Compute Metrics L3 Cache Gen9 :: EU Stall */ +#define kblgt3__compute_l3_cache__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics L3 Cache Gen9 :: Samples Blended */ +#define kblgt3__compute_l3_cache__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Compute Metrics L3 Cache Gen9 :: Early Depth Test Fails */ +#define kblgt3__compute_l3_cache__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 02 Accesses */ +#define kblgt3__compute_l3_cache__l3_bank02_accesses__read \ + bdw__compute_l3_cache__l3_bank02_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: HS Threads Dispatched */ +#define kblgt3__compute_l3_cache__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Total Throughput */ +#define kblgt3__compute_l3_cache__l3_total_throughput__read \ + sklgt2__compute_l3_cache__l3_total_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: GTI Write Throughput */ +#define kblgt3__compute_l3_cache__gti_write_throughput__read \ + hsw__render_basic__gti_write_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: SLM Bytes Written */ +#define kblgt3__compute_l3_cache__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Shader Throughput */ +#define kblgt3__compute_l3_cache__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: Samples Killed in FS */ +#define kblgt3__compute_l3_cache__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Binary Instruction */ +#define kblgt3__compute_l3_cache__eu_binary_fpu1_instruction__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Ternary Instruction */ +#define kblgt3__compute_l3_cache__eu_ternary_fpu1_instruction__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Compute Metrics L3 Cache Gen9 :: EU Send Pipe Active */ +#define kblgt3__compute_l3_cache__eu_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set HDCAndSF :: GPU Core Clocks */ +#define kblgt3__hdc_and_sf__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set HDCAndSF :: EU Active */ +#define kblgt3__hdc_and_sf__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set HDCAndSF :: EU Both FPU Pipes Active */ +#define kblgt3__hdc_and_sf__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set HDCAndSF :: VS Send Pipe Active */ +#define kblgt3__hdc_and_sf__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set HDCAndSF :: VS FPU1 Pipe Active */ +#define kblgt3__hdc_and_sf__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set HDCAndSF :: GS Threads Dispatched */ +#define kblgt3__hdc_and_sf__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set HDCAndSF :: Early Hi-Depth Test Fails */ +#define kblgt3__hdc_and_sf__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set HDCAndSF :: FS Both FPU Active */ +#define kblgt3__hdc_and_sf__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set HDCAndSF :: VS Threads Dispatched */ +#define kblgt3__hdc_and_sf__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set HDCAndSF :: Polygon Data Ready */ +#define kblgt3__hdc_and_sf__poly_data_ready__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set HDCAndSF :: FS Threads Dispatched */ +#define kblgt3__hdc_and_sf__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set HDCAndSF :: Shader Barrier Messages */ +#define kblgt3__hdc_and_sf__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set HDCAndSF :: Sampler Texels */ +#define kblgt3__hdc_and_sf__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set HDCAndSF :: Pixels Failing Tests */ +#define kblgt3__hdc_and_sf__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set HDCAndSF :: GPU Time Elapsed */ +#define kblgt3__hdc_and_sf__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set HDCAndSF :: AVG GPU Core Frequency */ +#define kblgt3__hdc_and_sf__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set HDCAndSF :: AVG GPU Core Frequency */ +#define kblgt3__hdc_and_sf__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set HDCAndSF :: Sampler Texels Misses */ +#define kblgt3__hdc_and_sf__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */ +#define kblgt3__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read \ + bdw__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read + +/* Metric set HDCAndSF :: CS Threads Dispatched */ +#define kblgt3__hdc_and_sf__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss2) */ +#define kblgt3__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read \ + bdw__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read + +/* Metric set HDCAndSF :: SLM Bytes Read */ +#define kblgt3__hdc_and_sf__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set HDCAndSF :: PS FPU1 Pipe Active */ +#define kblgt3__hdc_and_sf__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set HDCAndSF :: PS Send Pipeline Active */ +#define kblgt3__hdc_and_sf__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set HDCAndSF :: VS FPU0 Pipe Active */ +#define kblgt3__hdc_and_sf__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set HDCAndSF :: GPU Busy */ +#define kblgt3__hdc_and_sf__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set HDCAndSF :: Rasterized Pixels */ +#define kblgt3__hdc_and_sf__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set HDCAndSF :: PS FPU0 Pipe Active */ +#define kblgt3__hdc_and_sf__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set HDCAndSF :: DS Threads Dispatched */ +#define kblgt3__hdc_and_sf__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set HDCAndSF :: Samples Written */ +#define kblgt3__hdc_and_sf__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set HDCAndSF :: EU Stall */ +#define kblgt3__hdc_and_sf__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set HDCAndSF :: Samples Blended */ +#define kblgt3__hdc_and_sf__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set HDCAndSF :: Early Depth Test Fails */ +#define kblgt3__hdc_and_sf__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set HDCAndSF :: Shader Memory Accesses */ +#define kblgt3__hdc_and_sf__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set HDCAndSF :: HS Threads Dispatched */ +#define kblgt3__hdc_and_sf__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set HDCAndSF :: SLM Bytes Written */ +#define kblgt3__hdc_and_sf__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set HDCAndSF :: L3 Shader Throughput */ +#define kblgt3__hdc_and_sf__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set HDCAndSF :: Samples Killed in FS */ +#define kblgt3__hdc_and_sf__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */ +#define kblgt3__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read \ + bdw__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read + +/* Metric set HDCAndSF :: Shader Atomic Memory Accesses */ +#define kblgt3__hdc_and_sf__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set L3_1 :: GPU Core Clocks */ +#define kblgt3__l3_1__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set L3_1 :: EU Active */ +#define kblgt3__l3_1__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set L3_1 :: Slice0 L3 Bank1 Active */ +#define kblgt3__l3_1__l30_bank1_active__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set L3_1 :: EU Both FPU Pipes Active */ +#define kblgt3__l3_1__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set L3_1 :: VS Send Pipe Active */ +#define kblgt3__l3_1__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set L3_1 :: VS FPU1 Pipe Active */ +#define kblgt3__l3_1__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set L3_1 :: GS Threads Dispatched */ +#define kblgt3__l3_1__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set L3_1 :: Early Hi-Depth Test Fails */ +#define kblgt3__l3_1__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set L3_1 :: FS Both FPU Active */ +#define kblgt3__l3_1__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set L3_1 :: VS Threads Dispatched */ +#define kblgt3__l3_1__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set L3_1 :: Slice0 L3 Bank1 Stalled */ +#define kblgt3__l3_1__l30_bank1_stalled__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Metric set L3_1 :: FS Threads Dispatched */ +#define kblgt3__l3_1__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set L3_1 :: Shader Barrier Messages */ +#define kblgt3__l3_1__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set L3_1 :: Sampler Texels */ +#define kblgt3__l3_1__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set L3_1 :: Pixels Failing Tests */ +#define kblgt3__l3_1__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set L3_1 :: GPU Time Elapsed */ +#define kblgt3__l3_1__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set L3_1 :: AVG GPU Core Frequency */ +#define kblgt3__l3_1__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set L3_1 :: AVG GPU Core Frequency */ +#define kblgt3__l3_1__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set L3_1 :: Sampler Texels Misses */ +#define kblgt3__l3_1__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set L3_1 :: CS Threads Dispatched */ +#define kblgt3__l3_1__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set L3_1 :: SLM Bytes Read */ +#define kblgt3__l3_1__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set L3_1 :: PS FPU1 Pipe Active */ +#define kblgt3__l3_1__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set L3_1 :: PS Send Pipeline Active */ +#define kblgt3__l3_1__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set L3_1 :: VS FPU0 Pipe Active */ +#define kblgt3__l3_1__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set L3_1 :: GPU Busy */ +#define kblgt3__l3_1__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set L3_1 :: Slice0 L3 Bank0 Active */ +#define kblgt3__l3_1__l30_bank0_active__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set L3_1 :: Rasterized Pixels */ +#define kblgt3__l3_1__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set L3_1 :: PS FPU0 Pipe Active */ +#define kblgt3__l3_1__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set L3_1 :: Slice0 L3 Bank0 Stalled */ +#define kblgt3__l3_1__l30_bank0_stalled__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set L3_1 :: DS Threads Dispatched */ +#define kblgt3__l3_1__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set L3_1 :: Samples Written */ +#define kblgt3__l3_1__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set L3_1 :: EU Stall */ +#define kblgt3__l3_1__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set L3_1 :: Samples Blended */ +#define kblgt3__l3_1__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set L3_1 :: Early Depth Test Fails */ +#define kblgt3__l3_1__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set L3_1 :: Shader Memory Accesses */ +#define kblgt3__l3_1__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set L3_1 :: HS Threads Dispatched */ +#define kblgt3__l3_1__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set L3_1 :: SLM Bytes Written */ +#define kblgt3__l3_1__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set L3_1 :: L3 Shader Throughput */ +#define kblgt3__l3_1__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set L3_1 :: Samples Killed in FS */ +#define kblgt3__l3_1__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set L3_1 :: Shader Atomic Memory Accesses */ +#define kblgt3__l3_1__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set L3_2 :: GPU Core Clocks */ +#define kblgt3__l3_2__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set L3_2 :: EU Active */ +#define kblgt3__l3_2__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set L3_2 :: EU Both FPU Pipes Active */ +#define kblgt3__l3_2__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set L3_2 :: VS Send Pipe Active */ +#define kblgt3__l3_2__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set L3_2 :: VS FPU1 Pipe Active */ +#define kblgt3__l3_2__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set L3_2 :: GS Threads Dispatched */ +#define kblgt3__l3_2__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set L3_2 :: Early Hi-Depth Test Fails */ +#define kblgt3__l3_2__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set L3_2 :: FS Both FPU Active */ +#define kblgt3__l3_2__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set L3_2 :: VS Threads Dispatched */ +#define kblgt3__l3_2__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set L3_2 :: FS Threads Dispatched */ +#define kblgt3__l3_2__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set L3_2 :: Shader Barrier Messages */ +#define kblgt3__l3_2__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set L3_2 :: Sampler Texels */ +#define kblgt3__l3_2__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set L3_2 :: Pixels Failing Tests */ +#define kblgt3__l3_2__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set L3_2 :: GPU Time Elapsed */ +#define kblgt3__l3_2__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set L3_2 :: AVG GPU Core Frequency */ +#define kblgt3__l3_2__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set L3_2 :: AVG GPU Core Frequency */ +#define kblgt3__l3_2__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set L3_2 :: Sampler Texels Misses */ +#define kblgt3__l3_2__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set L3_2 :: CS Threads Dispatched */ +#define kblgt3__l3_2__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set L3_2 :: SLM Bytes Read */ +#define kblgt3__l3_2__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set L3_2 :: PS FPU1 Pipe Active */ +#define kblgt3__l3_2__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set L3_2 :: Slice0 L3 Bank2 Stalled */ +#define kblgt3__l3_2__l30_bank2_stalled__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set L3_2 :: PS Send Pipeline Active */ +#define kblgt3__l3_2__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set L3_2 :: VS FPU0 Pipe Active */ +#define kblgt3__l3_2__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set L3_2 :: GPU Busy */ +#define kblgt3__l3_2__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set L3_2 :: Slice0 L3 Bank2 Active */ +#define kblgt3__l3_2__l30_bank2_active__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set L3_2 :: Rasterized Pixels */ +#define kblgt3__l3_2__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set L3_2 :: PS FPU0 Pipe Active */ +#define kblgt3__l3_2__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set L3_2 :: DS Threads Dispatched */ +#define kblgt3__l3_2__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set L3_2 :: Samples Written */ +#define kblgt3__l3_2__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set L3_2 :: EU Stall */ +#define kblgt3__l3_2__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set L3_2 :: Samples Blended */ +#define kblgt3__l3_2__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set L3_2 :: Early Depth Test Fails */ +#define kblgt3__l3_2__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set L3_2 :: Shader Memory Accesses */ +#define kblgt3__l3_2__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set L3_2 :: HS Threads Dispatched */ +#define kblgt3__l3_2__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set L3_2 :: SLM Bytes Written */ +#define kblgt3__l3_2__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set L3_2 :: L3 Shader Throughput */ +#define kblgt3__l3_2__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set L3_2 :: Samples Killed in FS */ +#define kblgt3__l3_2__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set L3_2 :: Shader Atomic Memory Accesses */ +#define kblgt3__l3_2__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set L3_3 :: GPU Core Clocks */ +#define kblgt3__l3_3__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set L3_3 :: EU Active */ +#define kblgt3__l3_3__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set L3_3 :: EU Both FPU Pipes Active */ +#define kblgt3__l3_3__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set L3_3 :: VS Send Pipe Active */ +#define kblgt3__l3_3__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set L3_3 :: VS FPU1 Pipe Active */ +#define kblgt3__l3_3__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set L3_3 :: GS Threads Dispatched */ +#define kblgt3__l3_3__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set L3_3 :: Early Hi-Depth Test Fails */ +#define kblgt3__l3_3__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set L3_3 :: FS Both FPU Active */ +#define kblgt3__l3_3__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set L3_3 :: VS Threads Dispatched */ +#define kblgt3__l3_3__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set L3_3 :: FS Threads Dispatched */ +#define kblgt3__l3_3__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set L3_3 :: Slice0 L3 Bank3 Stalled */ +#define kblgt3__l3_3__l30_bank3_stalled__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set L3_3 :: Shader Barrier Messages */ +#define kblgt3__l3_3__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set L3_3 :: Sampler Texels */ +#define kblgt3__l3_3__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set L3_3 :: Pixels Failing Tests */ +#define kblgt3__l3_3__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set L3_3 :: GPU Time Elapsed */ +#define kblgt3__l3_3__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set L3_3 :: AVG GPU Core Frequency */ +#define kblgt3__l3_3__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set L3_3 :: AVG GPU Core Frequency */ +#define kblgt3__l3_3__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set L3_3 :: Sampler Texels Misses */ +#define kblgt3__l3_3__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set L3_3 :: CS Threads Dispatched */ +#define kblgt3__l3_3__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set L3_3 :: SLM Bytes Read */ +#define kblgt3__l3_3__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set L3_3 :: PS FPU1 Pipe Active */ +#define kblgt3__l3_3__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set L3_3 :: Slice0 L3 Bank3 Active */ +#define kblgt3__l3_3__l30_bank3_active__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set L3_3 :: PS Send Pipeline Active */ +#define kblgt3__l3_3__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set L3_3 :: VS FPU0 Pipe Active */ +#define kblgt3__l3_3__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set L3_3 :: GPU Busy */ +#define kblgt3__l3_3__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set L3_3 :: Rasterized Pixels */ +#define kblgt3__l3_3__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set L3_3 :: PS FPU0 Pipe Active */ +#define kblgt3__l3_3__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set L3_3 :: DS Threads Dispatched */ +#define kblgt3__l3_3__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set L3_3 :: Samples Written */ +#define kblgt3__l3_3__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set L3_3 :: EU Stall */ +#define kblgt3__l3_3__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set L3_3 :: Samples Blended */ +#define kblgt3__l3_3__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set L3_3 :: Early Depth Test Fails */ +#define kblgt3__l3_3__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set L3_3 :: Shader Memory Accesses */ +#define kblgt3__l3_3__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set L3_3 :: HS Threads Dispatched */ +#define kblgt3__l3_3__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set L3_3 :: SLM Bytes Written */ +#define kblgt3__l3_3__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set L3_3 :: L3 Shader Throughput */ +#define kblgt3__l3_3__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set L3_3 :: Samples Killed in FS */ +#define kblgt3__l3_3__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set L3_3 :: Shader Atomic Memory Accesses */ +#define kblgt3__l3_3__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */ +#define kblgt3__rasterizer_and_pixel_backend__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set RasterizerAndPixelBackend :: EU Active */ +#define kblgt3__rasterizer_and_pixel_backend__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set RasterizerAndPixelBackend :: EU Both FPU Pipes Active */ +#define kblgt3__rasterizer_and_pixel_backend__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set RasterizerAndPixelBackend :: VS Send Pipe Active */ +#define kblgt3__rasterizer_and_pixel_backend__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set RasterizerAndPixelBackend :: VS FPU1 Pipe Active */ +#define kblgt3__rasterizer_and_pixel_backend__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */ +#define kblgt3__rasterizer_and_pixel_backend__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */ +#define kblgt3__rasterizer_and_pixel_backend__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set RasterizerAndPixelBackend :: FS Both FPU Active */ +#define kblgt3__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */ +#define kblgt3__rasterizer_and_pixel_backend__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */ +#define kblgt3__rasterizer_and_pixel_backend__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Pixel Values Ready */ +#define kblgt3__rasterizer_and_pixel_backend__pixel_values0_ready__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */ +#define kblgt3__rasterizer_and_pixel_backend__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set RasterizerAndPixelBackend :: Sampler Texels */ +#define kblgt3__rasterizer_and_pixel_backend__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */ +#define kblgt3__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */ +#define kblgt3__rasterizer_and_pixel_backend__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ +#define kblgt3__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ +#define kblgt3__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */ +#define kblgt3__rasterizer_and_pixel_backend__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */ +#define kblgt3__rasterizer_and_pixel_backend__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */ +#define kblgt3__rasterizer_and_pixel_backend__rasterizer0_input_available__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Post-EarlyZ Pixel Data Ready */ +#define kblgt3__rasterizer_and_pixel_backend__pixel_data0_ready__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */ +#define kblgt3__rasterizer_and_pixel_backend__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set RasterizerAndPixelBackend :: PS FPU1 Pipe Active */ +#define kblgt3__rasterizer_and_pixel_backend__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set RasterizerAndPixelBackend :: PS Send Pipeline Active */ +#define kblgt3__rasterizer_and_pixel_backend__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set RasterizerAndPixelBackend :: VS FPU0 Pipe Active */ +#define kblgt3__rasterizer_and_pixel_backend__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set RasterizerAndPixelBackend :: GPU Busy */ +#define kblgt3__rasterizer_and_pixel_backend__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */ +#define kblgt3__rasterizer_and_pixel_backend__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set RasterizerAndPixelBackend :: PS FPU0 Pipe Active */ +#define kblgt3__rasterizer_and_pixel_backend__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */ +#define kblgt3__rasterizer_and_pixel_backend__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set RasterizerAndPixelBackend :: Samples Written */ +#define kblgt3__rasterizer_and_pixel_backend__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set RasterizerAndPixelBackend :: EU Stall */ +#define kblgt3__rasterizer_and_pixel_backend__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */ +#define kblgt3__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set RasterizerAndPixelBackend :: Samples Blended */ +#define kblgt3__rasterizer_and_pixel_backend__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */ +#define kblgt3__rasterizer_and_pixel_backend__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */ +#define kblgt3__rasterizer_and_pixel_backend__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */ +#define kblgt3__rasterizer_and_pixel_backend__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */ +#define kblgt3__rasterizer_and_pixel_backend__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */ +#define kblgt3__rasterizer_and_pixel_backend__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */ +#define kblgt3__rasterizer_and_pixel_backend__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 PS Output Available */ +#define kblgt3__rasterizer_and_pixel_backend__ps_output0_available__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */ +#define kblgt3__rasterizer_and_pixel_backend__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set Sampler :: GPU Core Clocks */ +#define kblgt3__sampler__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set Sampler :: EU Active */ +#define kblgt3__sampler__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set Sampler :: Slice0 Subslice2 Input Available */ +#define kblgt3__sampler__sampler02_input_available__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set Sampler :: EU Both FPU Pipes Active */ +#define kblgt3__sampler__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set Sampler :: VS Send Pipe Active */ +#define kblgt3__sampler__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set Sampler :: Slice0 Subslice0 Input Available */ +#define kblgt3__sampler__sampler00_input_available__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Metric set Sampler :: VS FPU1 Pipe Active */ +#define kblgt3__sampler__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set Sampler :: GS Threads Dispatched */ +#define kblgt3__sampler__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set Sampler :: Early Hi-Depth Test Fails */ +#define kblgt3__sampler__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set Sampler :: FS Both FPU Active */ +#define kblgt3__sampler__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set Sampler :: VS Threads Dispatched */ +#define kblgt3__sampler__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set Sampler :: Slice0 Subslice2 Sampler Output Ready */ +#define kblgt3__sampler__sampler02_output_ready__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set Sampler :: FS Threads Dispatched */ +#define kblgt3__sampler__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set Sampler :: Shader Barrier Messages */ +#define kblgt3__sampler__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set Sampler :: Slice0 Subslice1 Input Available */ +#define kblgt3__sampler__sampler01_input_available__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set Sampler :: Sampler Texels */ +#define kblgt3__sampler__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set Sampler :: Pixels Failing Tests */ +#define kblgt3__sampler__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set Sampler :: GPU Time Elapsed */ +#define kblgt3__sampler__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set Sampler :: AVG GPU Core Frequency */ +#define kblgt3__sampler__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set Sampler :: AVG GPU Core Frequency */ +#define kblgt3__sampler__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set Sampler :: Sampler Texels Misses */ +#define kblgt3__sampler__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set Sampler :: CS Threads Dispatched */ +#define kblgt3__sampler__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set Sampler :: SLM Bytes Read */ +#define kblgt3__sampler__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set Sampler :: PS FPU1 Pipe Active */ +#define kblgt3__sampler__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set Sampler :: PS Send Pipeline Active */ +#define kblgt3__sampler__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set Sampler :: VS FPU0 Pipe Active */ +#define kblgt3__sampler__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set Sampler :: GPU Busy */ +#define kblgt3__sampler__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set Sampler :: Rasterized Pixels */ +#define kblgt3__sampler__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set Sampler :: PS FPU0 Pipe Active */ +#define kblgt3__sampler__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set Sampler :: DS Threads Dispatched */ +#define kblgt3__sampler__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set Sampler :: Samples Written */ +#define kblgt3__sampler__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set Sampler :: EU Stall */ +#define kblgt3__sampler__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set Sampler :: Samples Blended */ +#define kblgt3__sampler__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set Sampler :: Early Depth Test Fails */ +#define kblgt3__sampler__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set Sampler :: Slice0 Subslice0 Sampler Output Ready */ +#define kblgt3__sampler__sampler00_output_ready__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set Sampler :: Slice0 Subslice1 Sampler Output Ready */ +#define kblgt3__sampler__sampler01_output_ready__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set Sampler :: Shader Memory Accesses */ +#define kblgt3__sampler__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set Sampler :: HS Threads Dispatched */ +#define kblgt3__sampler__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set Sampler :: SLM Bytes Written */ +#define kblgt3__sampler__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set Sampler :: L3 Shader Throughput */ +#define kblgt3__sampler__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set Sampler :: Samples Killed in FS */ +#define kblgt3__sampler__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set Sampler :: Shader Atomic Memory Accesses */ +#define kblgt3__sampler__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set TDL_1 :: GPU Core Clocks */ +#define kblgt3__tdl_1__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set TDL_1 :: EU Active */ +#define kblgt3__tdl_1__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set TDL_1 :: EU Both FPU Pipes Active */ +#define kblgt3__tdl_1__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set TDL_1 :: VS Send Pipe Active */ +#define kblgt3__tdl_1__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set TDL_1 :: VS FPU1 Pipe Active */ +#define kblgt3__tdl_1__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set TDL_1 :: GS Threads Dispatched */ +#define kblgt3__tdl_1__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set TDL_1 :: Early Hi-Depth Test Fails */ +#define kblgt3__tdl_1__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set TDL_1 :: FS Both FPU Active */ +#define kblgt3__tdl_1__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set TDL_1 :: VS Threads Dispatched */ +#define kblgt3__tdl_1__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set TDL_1 :: FS Threads Dispatched */ +#define kblgt3__tdl_1__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice2 */ +#define kblgt3__tdl_1__non_ps_thread02_ready_for_dispatch__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Metric set TDL_1 :: Shader Barrier Messages */ +#define kblgt3__tdl_1__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_1 :: Sampler Texels */ +#define kblgt3__tdl_1__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set TDL_1 :: Pixels Failing Tests */ +#define kblgt3__tdl_1__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set TDL_1 :: GPU Time Elapsed */ +#define kblgt3__tdl_1__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set TDL_1 :: AVG GPU Core Frequency */ +#define kblgt3__tdl_1__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set TDL_1 :: AVG GPU Core Frequency */ +#define kblgt3__tdl_1__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set TDL_1 :: Sampler Texels Misses */ +#define kblgt3__tdl_1__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice0 */ +#define kblgt3__tdl_1__non_ps_thread00_ready_for_dispatch__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Metric set TDL_1 :: CS Threads Dispatched */ +#define kblgt3__tdl_1__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set TDL_1 :: SLM Bytes Read */ +#define kblgt3__tdl_1__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set TDL_1 :: PS FPU1 Pipe Active */ +#define kblgt3__tdl_1__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set TDL_1 :: PS Send Pipeline Active */ +#define kblgt3__tdl_1__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set TDL_1 :: VS FPU0 Pipe Active */ +#define kblgt3__tdl_1__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set TDL_1 :: GPU Busy */ +#define kblgt3__tdl_1__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice0 */ +#define kblgt3__tdl_1__ps_thread00_ready_for_dispatch__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set TDL_1 :: Rasterized Pixels */ +#define kblgt3__tdl_1__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set TDL_1 :: PS FPU0 Pipe Active */ +#define kblgt3__tdl_1__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set TDL_1 :: DS Threads Dispatched */ +#define kblgt3__tdl_1__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set TDL_1 :: Samples Written */ +#define kblgt3__tdl_1__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set TDL_1 :: EU Stall */ +#define kblgt3__tdl_1__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set TDL_1 :: Samples Blended */ +#define kblgt3__tdl_1__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set TDL_1 :: Early Depth Test Fails */ +#define kblgt3__tdl_1__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice1 */ +#define kblgt3__tdl_1__ps_thread01_ready_for_dispatch__read \ + bdw__render_pipe_profile__cl_bottleneck__read + +/* Metric set TDL_1 :: Shader Memory Accesses */ +#define kblgt3__tdl_1__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set TDL_1 :: HS Threads Dispatched */ +#define kblgt3__tdl_1__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice2 */ +#define kblgt3__tdl_1__ps_thread02_ready_for_dispatch__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Metric set TDL_1 :: SLM Bytes Written */ +#define kblgt3__tdl_1__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set TDL_1 :: L3 Shader Throughput */ +#define kblgt3__tdl_1__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set TDL_1 :: Samples Killed in FS */ +#define kblgt3__tdl_1__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set TDL_1 :: Shader Atomic Memory Accesses */ +#define kblgt3__tdl_1__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice1 */ +#define kblgt3__tdl_1__non_ps_thread01_ready_for_dispatch__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set TDL_2 :: GPU Core Clocks */ +#define kblgt3__tdl_2__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set TDL_2 :: EU Active */ +#define kblgt3__tdl_2__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set TDL_2 :: EU Both FPU Pipes Active */ +#define kblgt3__tdl_2__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set TDL_2 :: VS Send Pipe Active */ +#define kblgt3__tdl_2__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set TDL_2 :: VS FPU1 Pipe Active */ +#define kblgt3__tdl_2__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set TDL_2 :: GS Threads Dispatched */ +#define kblgt3__tdl_2__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set TDL_2 :: Early Hi-Depth Test Fails */ +#define kblgt3__tdl_2__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set TDL_2 :: FS Both FPU Active */ +#define kblgt3__tdl_2__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set TDL_2 :: VS Threads Dispatched */ +#define kblgt3__tdl_2__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set TDL_2 :: FS Threads Dispatched */ +#define kblgt3__tdl_2__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set TDL_2 :: Shader Barrier Messages */ +#define kblgt3__tdl_2__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_2 :: Sampler Texels */ +#define kblgt3__tdl_2__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set TDL_2 :: Pixels Failing Tests */ +#define kblgt3__tdl_2__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 0 */ +#define kblgt3__tdl_2__thread_header01_ready_port0__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 1 */ +#define kblgt3__tdl_2__thread_header01_ready_port1__read \ + bdw__render_pipe_profile__ds_stall__read + +/* Metric set TDL_2 :: GPU Time Elapsed */ +#define kblgt3__tdl_2__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set TDL_2 :: AVG GPU Core Frequency */ +#define kblgt3__tdl_2__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set TDL_2 :: AVG GPU Core Frequency */ +#define kblgt3__tdl_2__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set TDL_2 :: Sampler Texels Misses */ +#define kblgt3__tdl_2__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set TDL_2 :: CS Threads Dispatched */ +#define kblgt3__tdl_2__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set TDL_2 :: SLM Bytes Read */ +#define kblgt3__tdl_2__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set TDL_2 :: PS FPU1 Pipe Active */ +#define kblgt3__tdl_2__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set TDL_2 :: PS Send Pipeline Active */ +#define kblgt3__tdl_2__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set TDL_2 :: VS FPU0 Pipe Active */ +#define kblgt3__tdl_2__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set TDL_2 :: GPU Busy */ +#define kblgt3__tdl_2__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 1 */ +#define kblgt3__tdl_2__thread_header02_ready_port1__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 0 */ +#define kblgt3__tdl_2__thread_header02_ready_port0__read \ + bdw__render_pipe_profile__so_stall__read + +/* Metric set TDL_2 :: Rasterized Pixels */ +#define kblgt3__tdl_2__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set TDL_2 :: PS FPU0 Pipe Active */ +#define kblgt3__tdl_2__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set TDL_2 :: DS Threads Dispatched */ +#define kblgt3__tdl_2__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set TDL_2 :: Samples Written */ +#define kblgt3__tdl_2__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set TDL_2 :: EU Stall */ +#define kblgt3__tdl_2__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set TDL_2 :: Samples Blended */ +#define kblgt3__tdl_2__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set TDL_2 :: Early Depth Test Fails */ +#define kblgt3__tdl_2__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_2 :: Shader Memory Accesses */ +#define kblgt3__tdl_2__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set TDL_2 :: HS Threads Dispatched */ +#define kblgt3__tdl_2__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set TDL_2 :: SLM Bytes Written */ +#define kblgt3__tdl_2__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set TDL_2 :: L3 Shader Throughput */ +#define kblgt3__tdl_2__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set TDL_2 :: Samples Killed in FS */ +#define kblgt3__tdl_2__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 0 */ +#define kblgt3__tdl_2__thread_header00_ready_port0__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set TDL_2 :: Shader Atomic Memory Accesses */ +#define kblgt3__tdl_2__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 1 */ +#define kblgt3__tdl_2__thread_header00_ready_port1__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Compute Metrics Extra Gen9 :: GPU Core Clocks */ +#define kblgt3__compute_extra__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Extra Gen9 :: EU FPU1 Pipe Active */ +#define kblgt3__compute_extra__fpu1_active__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics Extra Gen9 :: GPU Time Elapsed */ +#define kblgt3__compute_extra__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics Extra Gen9 :: AVG GPU Core Frequency */ +#define kblgt3__compute_extra__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics Extra Gen9 :: AVG GPU Core Frequency */ +#define kblgt3__compute_extra__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics Extra Gen9 :: EU FPU1 Pipe Active including Ext Math */ +#define kblgt3__compute_extra__fpu1_active_adjusted__read \ + bdw__compute_extra__fpu1_active_adjusted__read + +/* Media Vme Pipe Gen9 :: GPU Core Clocks */ +#define kblgt3__vme_pipe__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Media Vme Pipe Gen9 :: EU Active */ +#define kblgt3__vme_pipe__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Media Vme Pipe Gen9 :: EU Both FPU Pipes Active */ +#define kblgt3__vme_pipe__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Media Vme Pipe Gen9 :: GPU Time Elapsed */ +#define kblgt3__vme_pipe__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Media Vme Pipe Gen9 :: AVG GPU Core Frequency */ +#define kblgt3__vme_pipe__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Media Vme Pipe Gen9 :: AVG GPU Core Frequency */ +#define kblgt3__vme_pipe__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Media Vme Pipe Gen9 :: CS Threads Dispatched */ +#define kblgt3__vme_pipe__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Media Vme Pipe Gen9 :: EU Thread Occupancy */ +#define kblgt3__vme_pipe__eu_thread_occupancy__read \ + bdw__vme_pipe__eu_thread_occupancy__read + +/* Media Vme Pipe Gen9 :: EU Stall */ +#define kblgt3__vme_pipe__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Media Vme Pipe Gen9 :: VME Busy */ +#define kblgt3__vme_pipe__vme_busy__read \ + bdw__vme_pipe__vme_busy__read + +/* Media Vme Pipe Gen9 :: GPU Busy */ +#define kblgt3__vme_pipe__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Gpu Rings Busyness :: GPU Core Clocks */ +#define kblgt3__gpu_busyness__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Gpu Rings Busyness :: Vebox Ring Busy */ +#define kblgt3__gpu_busyness__vebox_busy__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Gpu Rings Busyness :: GPU Time Elapsed */ +#define kblgt3__gpu_busyness__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Gpu Rings Busyness :: AVG GPU Core Frequency */ +#define kblgt3__gpu_busyness__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Gpu Rings Busyness :: AVG GPU Core Frequency */ +#define kblgt3__gpu_busyness__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Gpu Rings Busyness :: Render Ring Busy */ +#define kblgt3__gpu_busyness__render_busy__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Gpu Rings Busyness :: Vdbox0 Ring Busy */ +#define kblgt3__gpu_busyness__vdbox0_busy__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Gpu Rings Busyness :: Blitter Ring Busy */ +#define kblgt3__gpu_busyness__blitter_busy__read \ + bdw__render_pipe_profile__so_stall__read + +/* Gpu Rings Busyness :: AnyRingBusy */ +#define kblgt3__gpu_busyness__any_ring_busy__read \ + bdw__render_basic__sampler0_busy__read + +/* Gpu Rings Busyness :: Vdbox1 Ring Busy */ +#define kblgt3__gpu_busyness__vdbox1_busy__read \ + bdw__render_pipe_profile__sf_stall__read + +/* MDAPI testing set Gen9 :: TestCounter7 */ +#define kblgt3__test_oa__counter7__read \ + hsw__compute_extended__gpu_clocks__read + +/* MDAPI testing set Gen9 :: GPU Time Elapsed */ +#define kblgt3__test_oa__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* MDAPI testing set Gen9 :: GPU Core Clocks */ +#define kblgt3__test_oa__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* MDAPI testing set Gen9 :: AVG GPU Core Frequency */ +#define kblgt3__test_oa__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* MDAPI testing set Gen9 :: AVG GPU Core Frequency */ +#define kblgt3__test_oa__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* MDAPI testing set Gen9 :: TestCounter8 */ +#define kblgt3__test_oa__counter8__read \ + hsw__memory_reads__gpu_core_clocks__read + +/* MDAPI testing set Gen9 :: TestCounter4 */ +#define kblgt3__test_oa__counter4__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* MDAPI testing set Gen9 :: TestCounter5 */ +#define kblgt3__test_oa__counter5__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* MDAPI testing set Gen9 :: TestCounter6 */ +#define kblgt3__test_oa__counter6__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* MDAPI testing set Gen9 :: TestCounter3 */ +#define kblgt3__test_oa__counter3__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* MDAPI testing set Gen9 :: TestCounter0 */ +#define kblgt3__test_oa__counter0__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* MDAPI testing set Gen9 :: TestCounter1 */ +#define kblgt3__test_oa__counter1__read \ + hsw__compute_extended__eu_untyped_writes0__read + +/* MDAPI testing set Gen9 :: TestCounter2 */ +#define kblgt3__test_oa__counter2__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Render Metrics Basic Gen9 :: GPU Core Clocks */ +#define glk__render_basic__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Render Metrics Basic Gen9 :: EU Active */ +#define glk__render_basic__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Render Metrics Basic Gen9 :: L3 Misses */ +#define glk__render_basic__l3_misses__read \ + hsw__compute_extended__typed_atomics0__read + +/* Render Metrics Basic Gen9 :: GTI L3 Throughput */ +#define glk__render_basic__gti_l3_throughput__read \ + hsw__render_basic__gti_l3_throughput__read + +/* Render Metrics Basic Gen9 :: EU Both FPU Pipes Active */ +#define glk__render_basic__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Render Metrics Basic Gen9 :: Sampler Cache Misses */ +#define glk__render_basic__sampler_l1_misses__read \ + sklgt2__render_basic__sampler_l1_misses__read + +/* Render Metrics Basic Gen9 :: VS Send Pipe Active */ +#define glk__render_basic__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Render Metrics Basic Gen9 :: Sampler 1 Bottleneck */ +#define glk__render_basic__sampler1_bottleneck__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Render Metrics Basic Gen9 :: VS FPU1 Pipe Active */ +#define glk__render_basic__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Render Metrics Basic Gen9 :: GS Threads Dispatched */ +#define glk__render_basic__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Render Metrics Basic Gen9 :: L3 Sampler Throughput */ +#define glk__render_basic__l3_sampler_throughput__read \ + sklgt2__render_basic__l3_sampler_throughput__read + +/* Render Metrics Basic Gen9 :: Early Hi-Depth Test Fails */ +#define glk__render_basic__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Render Metrics Basic Gen9 :: FS Both FPU Active */ +#define glk__render_basic__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Render Metrics Basic Gen9 :: VS Threads Dispatched */ +#define glk__render_basic__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Render Metrics Basic Gen9 :: FS Threads Dispatched */ +#define glk__render_basic__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Render Metrics Basic Gen9 :: Sampler 0 Busy */ +#define glk__render_basic__sampler0_busy__read \ + bdw__render_basic__sampler0_busy__read + +/* Render Metrics Basic Gen9 :: Sampler 1 Busy */ +#define glk__render_basic__sampler1_busy__read \ + bdw__render_basic__sampler1_busy__read + +/* Render Metrics Basic Gen9 :: Samplers Busy */ +#define glk__render_basic__samplers_busy__read \ + bdw__render_basic__samplers_busy__read + +/* Render Metrics Basic Gen9 :: GTI Fixed Pipe Throughput */ +#define glk__render_basic__gti_vf_throughput__read \ + bdw__render_basic__gti_vf_throughput__read + +/* Render Metrics Basic Gen9 :: Shader Barrier Messages */ +#define glk__render_basic__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Render Metrics Basic Gen9 :: Sampler 0 Bottleneck */ +#define glk__render_basic__sampler0_bottleneck__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Render Metrics Basic Gen9 :: Sampler Texels */ +#define glk__render_basic__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Render Metrics Basic Gen9 :: Pixels Failing Tests */ +#define glk__render_basic__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Render Metrics Basic Gen9 :: GPU Time Elapsed */ +#define glk__render_basic__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Render Metrics Basic Gen9 :: AVG GPU Core Frequency */ +#define glk__render_basic__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Render Metrics Basic Gen9 :: AVG GPU Core Frequency */ +#define glk__render_basic__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Render Metrics Basic Gen9 :: Sampler Texels Misses */ +#define glk__render_basic__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Render Metrics Basic Gen9 :: CS Threads Dispatched */ +#define glk__render_basic__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Render Metrics Basic Gen9 :: Shader Memory Accesses */ +#define glk__render_basic__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Render Metrics Basic Gen9 :: L3 Lookup Accesses w/o IC */ +#define glk__render_basic__l3_lookups__read \ + sklgt2__render_basic__l3_lookups__read + +/* Render Metrics Basic Gen9 :: SLM Bytes Read */ +#define glk__render_basic__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Render Metrics Basic Gen9 :: GTI Read Throughput */ +#define glk__render_basic__gti_read_throughput__read \ + bdw__render_basic__gti_read_throughput__read + +/* Render Metrics Basic Gen9 :: PS FPU1 Pipe Active */ +#define glk__render_basic__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Render Metrics Basic Gen9 :: PS Send Pipeline Active */ +#define glk__render_basic__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Render Metrics Basic Gen9 :: Rasterized Pixels */ +#define glk__render_basic__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Render Metrics Basic Gen9 :: GPU Busy */ +#define glk__render_basic__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Render Metrics Basic Gen9 :: GTI Depth Throughput */ +#define glk__render_basic__gti_depth_throughput__read \ + bdw__render_basic__gti_depth_throughput__read + +/* Render Metrics Basic Gen9 :: VS FPU0 Pipe Active */ +#define glk__render_basic__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Render Metrics Basic Gen9 :: PS FPU0 Pipe Active */ +#define glk__render_basic__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Render Metrics Basic Gen9 :: DS Threads Dispatched */ +#define glk__render_basic__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Render Metrics Basic Gen9 :: Samples Written */ +#define glk__render_basic__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Render Metrics Basic Gen9 :: EU Stall */ +#define glk__render_basic__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Render Metrics Basic Gen9 :: Samples Blended */ +#define glk__render_basic__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Render Metrics Basic Gen9 :: Early Depth Test Fails */ +#define glk__render_basic__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Render Metrics Basic Gen9 :: Samplers Bottleneck */ +#define glk__render_basic__sampler_bottleneck__read \ + bdw__render_basic__sampler_bottleneck__read + +/* Render Metrics Basic Gen9 :: GTI HDC TLB Lookup Throughput */ +#define glk__render_basic__gti_hdc_lookups_throughput__read \ + bdw__render_basic__gti_hdc_lookups_throughput__read + +/* Render Metrics Basic Gen9 :: GTI RCC Throughput */ +#define glk__render_basic__gti_rcc_throughput__read \ + bdw__render_basic__gti_rcc_throughput__read + +/* Render Metrics Basic Gen9 :: HS Threads Dispatched */ +#define glk__render_basic__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Render Metrics Basic Gen9 :: GTI Write Throughput */ +#define glk__render_basic__gti_write_throughput__read \ + hsw__render_basic__gti_write_throughput__read + +/* Render Metrics Basic Gen9 :: SLM Bytes Written */ +#define glk__render_basic__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Render Metrics Basic Gen9 :: L3 Shader Throughput */ +#define glk__render_basic__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Render Metrics Basic Gen9 :: Samples Killed in FS */ +#define glk__render_basic__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Render Metrics Basic Gen9 :: Shader Atomic Memory Accesses */ +#define glk__render_basic__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Basic Gen9 :: GPU Core Clocks */ +#define glk__compute_basic__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Basic Gen9 :: EU Active */ +#define glk__compute_basic__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Compute Metrics Basic Gen9 :: Untyped Bytes Read */ +#define glk__compute_basic__untyped_bytes_read__read \ + hsw__compute_basic__typed_bytes_written__read + +/* Compute Metrics Basic Gen9 :: EU Both FPU Pipes Active */ +#define glk__compute_basic__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Compute Metrics Basic Gen9 :: Typed Bytes Written */ +#define glk__compute_basic__typed_bytes_written__read \ + bxt__compute_basic__typed_bytes_written__read + +/* Compute Metrics Basic Gen9 :: EU FPU0 Pipe Active */ +#define glk__compute_basic__fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Compute Metrics Basic Gen9 :: EU FPU1 Pipe Active */ +#define glk__compute_basic__fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Compute Metrics Basic Gen9 :: EU AVG IPC Rate */ +#define glk__compute_basic__eu_avg_ipc_rate__read \ + bdw__compute_basic__eu_avg_ipc_rate__read + +/* Compute Metrics Basic Gen9 :: GS Threads Dispatched */ +#define glk__compute_basic__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Compute Metrics Basic Gen9 :: Early Hi-Depth Test Fails */ +#define glk__compute_basic__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Compute Metrics Basic Gen9 :: VS Threads Dispatched */ +#define glk__compute_basic__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Compute Metrics Basic Gen9 :: FS Threads Dispatched */ +#define glk__compute_basic__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Compute Metrics Basic Gen9 :: Shader Barrier Messages */ +#define glk__compute_basic__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Compute Metrics Basic Gen9 :: Sampler Texels */ +#define glk__compute_basic__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Compute Metrics Basic Gen9 :: Pixels Failing Tests */ +#define glk__compute_basic__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Compute Metrics Basic Gen9 :: GPU Time Elapsed */ +#define glk__compute_basic__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics Basic Gen9 :: AVG GPU Core Frequency */ +#define glk__compute_basic__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics Basic Gen9 :: AVG GPU Core Frequency */ +#define glk__compute_basic__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics Basic Gen9 :: Sampler Texels Misses */ +#define glk__compute_basic__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Compute Metrics Basic Gen9 :: CS Threads Dispatched */ +#define glk__compute_basic__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Compute Metrics Basic Gen9 :: SLM Bytes Read */ +#define glk__compute_basic__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Compute Metrics Basic Gen9 :: GTI Read Throughput */ +#define glk__compute_basic__gti_read_throughput__read \ + hsw__render_basic__gti_l3_throughput__read + +/* Compute Metrics Basic Gen9 :: Untyped Writes */ +#define glk__compute_basic__untyped_bytes_written__read \ + bxt__compute_basic__untyped_bytes_written__read + +/* Compute Metrics Basic Gen9 :: GPU Busy */ +#define glk__compute_basic__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Compute Metrics Basic Gen9 :: Rasterized Pixels */ +#define glk__compute_basic__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Compute Metrics Basic Gen9 :: Typed Bytes Read */ +#define glk__compute_basic__typed_bytes_read__read \ + hsw__compute_basic__untyped_bytes_read__read + +/* Compute Metrics Basic Gen9 :: DS Threads Dispatched */ +#define glk__compute_basic__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Compute Metrics Basic Gen9 :: EU Thread Occupancy */ +#define glk__compute_basic__eu_thread_occupancy__read \ + bdw__compute_basic__eu_thread_occupancy__read + +/* Compute Metrics Basic Gen9 :: EU Stall */ +#define glk__compute_basic__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics Basic Gen9 :: Samples Blended */ +#define glk__compute_basic__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Compute Metrics Basic Gen9 :: Early Depth Test Fails */ +#define glk__compute_basic__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Compute Metrics Basic Gen9 :: Shader Memory Accesses */ +#define glk__compute_basic__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Compute Metrics Basic Gen9 :: HS Threads Dispatched */ +#define glk__compute_basic__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Compute Metrics Basic Gen9 :: GTI Write Throughput */ +#define glk__compute_basic__gti_write_throughput__read \ + bdw__render_basic__gti_hdc_lookups_throughput__read + +/* Compute Metrics Basic Gen9 :: SLM Bytes Written */ +#define glk__compute_basic__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Compute Metrics Basic Gen9 :: L3 Shader Throughput */ +#define glk__compute_basic__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Compute Metrics Basic Gen9 :: Samples Killed in FS */ +#define glk__compute_basic__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Compute Metrics Basic Gen9 :: Samples Written */ +#define glk__compute_basic__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Compute Metrics Basic Gen9 :: Shader Atomic Memory Accesses */ +#define glk__compute_basic__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Basic Gen9 :: EU Send Pipe Active */ +#define glk__compute_basic__eu_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Core Clocks */ +#define glk__render_pipe_profile__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: EU Active */ +#define glk__render_pipe_profile__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: VS Bottleneck */ +#define glk__render_pipe_profile__vs_bottleneck__read \ + bdw__render_basic__sampler0_busy__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Hi-Depth Bottleneck */ +#define glk__render_pipe_profile__hi_depth_bottleneck__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GS Bottleneck */ +#define glk__render_pipe_profile__gs_bottleneck__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GS Threads Dispatched */ +#define glk__render_pipe_profile__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Early Hi-Depth Test Fails */ +#define glk__render_pipe_profile__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: VS Threads Dispatched */ +#define glk__render_pipe_profile__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: FS Threads Dispatched */ +#define glk__render_pipe_profile__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: BC Bottleneck */ +#define glk__render_pipe_profile__bc_bottleneck__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: HS Stall */ +#define glk__render_pipe_profile__hs_stall__read \ + bdw__render_pipe_profile__hs_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Barrier Messages */ +#define glk__render_pipe_profile__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Sampler Texels */ +#define glk__render_pipe_profile__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Pixels Failing Tests */ +#define glk__render_pipe_profile__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Time Elapsed */ +#define glk__render_pipe_profile__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: AVG GPU Core Frequency */ +#define glk__render_pipe_profile__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: AVG GPU Core Frequency */ +#define glk__render_pipe_profile__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Sampler Texels Misses */ +#define glk__render_pipe_profile__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: CS Threads Dispatched */ +#define glk__render_pipe_profile__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: VF Bottleneck */ +#define glk__render_pipe_profile__vf_bottleneck__read \ + bdw__render_pipe_profile__vf_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SLM Bytes Read */ +#define glk__render_pipe_profile__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Strip-Fans Bottleneck */ +#define glk__render_pipe_profile__sf_bottleneck__read \ + bdw__render_pipe_profile__sf_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SF Stall */ +#define glk__render_pipe_profile__sf_stall__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Busy */ +#define glk__render_pipe_profile__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: HS Bottleneck */ +#define glk__render_pipe_profile__hs_bottleneck__read \ + bdw__render_basic__sampler1_busy__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: CL Stall */ +#define glk__render_pipe_profile__cl_stall__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SO Bottleneck */ +#define glk__render_pipe_profile__so_bottleneck__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Rasterized Pixels */ +#define glk__render_pipe_profile__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: DS Threads Dispatched */ +#define glk__render_pipe_profile__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Written */ +#define glk__render_pipe_profile__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: DS Bottleneck */ +#define glk__render_pipe_profile__ds_bottleneck__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: EU Stall */ +#define glk__render_pipe_profile__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Clipper Bottleneck */ +#define glk__render_pipe_profile__cl_bottleneck__read \ + bdw__render_pipe_profile__cl_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: DS Stall */ +#define glk__render_pipe_profile__ds_stall__read \ + bdw__render_pipe_profile__ds_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Early Depth Bottleneck */ +#define glk__render_pipe_profile__early_depth_bottleneck__read \ + bdw__render_pipe_profile__early_depth_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Blended */ +#define glk__render_pipe_profile__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Early Depth Test Fails */ +#define glk__render_pipe_profile__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Memory Accesses */ +#define glk__render_pipe_profile__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: HS Threads Dispatched */ +#define glk__render_pipe_profile__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SLM Bytes Written */ +#define glk__render_pipe_profile__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: L3 Shader Throughput */ +#define glk__render_pipe_profile__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Killed in FS */ +#define glk__render_pipe_profile__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SO Stall */ +#define glk__render_pipe_profile__so_stall__read \ + bdw__render_pipe_profile__so_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Atomic Memory Accesses */ +#define glk__render_pipe_profile__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Memory Reads Distribution Gen9 :: GPU Core Clocks */ +#define glk__memory_reads__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Memory Reads Distribution Gen9 :: EU Active */ +#define glk__memory_reads__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Memory Reads Distribution Gen9 :: GtiL3Bank0Reads */ +#define glk__memory_reads__gti_l3_bank0_reads__read \ + hsw__compute_extended__typed_atomics0__read + +/* Memory Reads Distribution Gen9 :: GS Threads Dispatched */ +#define glk__memory_reads__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Memory Reads Distribution Gen9 :: GtiRingAccesses */ +#define glk__memory_reads__gti_ring_accesses__read \ + bdw__memory_reads__gti_ring_accesses__read + +/* Memory Reads Distribution Gen9 :: Early Hi-Depth Test Fails */ +#define glk__memory_reads__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Memory Reads Distribution Gen9 :: VS Threads Dispatched */ +#define glk__memory_reads__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Memory Reads Distribution Gen9 :: FS Threads Dispatched */ +#define glk__memory_reads__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Memory Reads Distribution Gen9 :: GtiL3Bank3Reads */ +#define glk__memory_reads__gti_l3_bank3_reads__read \ + hsw__memory_reads__gpu_core_clocks__read + +/* Memory Reads Distribution Gen9 :: Shader Barrier Messages */ +#define glk__memory_reads__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Memory Reads Distribution Gen9 :: GtiRsMemoryReads */ +#define glk__memory_reads__gti_rs_memory_reads__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Memory Reads Distribution Gen9 :: Sampler Texels */ +#define glk__memory_reads__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Memory Reads Distribution Gen9 :: Pixels Failing Tests */ +#define glk__memory_reads__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Memory Reads Distribution Gen9 :: GtiHizMemoryReads */ +#define glk__memory_reads__gti_hiz_memory_reads__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* Memory Reads Distribution Gen9 :: GPU Time Elapsed */ +#define glk__memory_reads__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Memory Reads Distribution Gen9 :: AVG GPU Core Frequency */ +#define glk__memory_reads__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Memory Reads Distribution Gen9 :: AVG GPU Core Frequency */ +#define glk__memory_reads__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Memory Reads Distribution Gen9 :: Sampler Texels Misses */ +#define glk__memory_reads__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Memory Reads Distribution Gen9 :: GtiRccMemoryReads */ +#define glk__memory_reads__gti_rcc_memory_reads__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* Memory Reads Distribution Gen9 :: CS Threads Dispatched */ +#define glk__memory_reads__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Memory Reads Distribution Gen9 :: SLM Bytes Read */ +#define glk__memory_reads__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Memory Reads Distribution Gen9 :: GtiL3Bank1Reads */ +#define glk__memory_reads__gti_l3_bank1_reads__read \ + hsw__memory_reads__gti_memory_reads__read + +/* Memory Reads Distribution Gen9 :: GPU Busy */ +#define glk__memory_reads__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Memory Reads Distribution Gen9 :: GtiCmdStreamerMemoryReads */ +#define glk__memory_reads__gti_cmd_streamer_memory_reads__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* Memory Reads Distribution Gen9 :: GtiL3Bank2Reads */ +#define glk__memory_reads__gti_l3_bank2_reads__read \ + hsw__memory_reads__llc_read_accesses__read + +/* Memory Reads Distribution Gen9 :: GtiMemoryReads */ +#define glk__memory_reads__gti_memory_reads__read \ + hsw__compute_extended__typed_writes0__read + +/* Memory Reads Distribution Gen9 :: Rasterized Pixels */ +#define glk__memory_reads__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Memory Reads Distribution Gen9 :: GtiRczMemoryReads */ +#define glk__memory_reads__gti_rcz_memory_reads__read \ + hsw__compute_extended__gpu_clocks__read + +/* Memory Reads Distribution Gen9 :: DS Threads Dispatched */ +#define glk__memory_reads__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Memory Reads Distribution Gen9 :: Samples Written */ +#define glk__memory_reads__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Memory Reads Distribution Gen9 :: EU Stall */ +#define glk__memory_reads__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Memory Reads Distribution Gen9 :: Samples Blended */ +#define glk__memory_reads__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Memory Reads Distribution Gen9 :: Early Depth Test Fails */ +#define glk__memory_reads__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Memory Reads Distribution Gen9 :: GtiMscMemoryReads */ +#define glk__memory_reads__gti_msc_memory_reads__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* Memory Reads Distribution Gen9 :: GtiVfMemoryReads */ +#define glk__memory_reads__gti_vf_memory_reads__read \ + hsw__compute_extended__eu_untyped_writes0__read + +/* Memory Reads Distribution Gen9 :: GtiStcMemoryReads */ +#define glk__memory_reads__gti_stc_memory_reads__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* Memory Reads Distribution Gen9 :: Shader Memory Accesses */ +#define glk__memory_reads__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Memory Reads Distribution Gen9 :: HS Threads Dispatched */ +#define glk__memory_reads__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Memory Reads Distribution Gen9 :: Samples Killed in FS */ +#define glk__memory_reads__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Memory Reads Distribution Gen9 :: SLM Bytes Written */ +#define glk__memory_reads__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Memory Reads Distribution Gen9 :: GtiL3Reads */ +#define glk__memory_reads__gti_l3_reads__read \ + bdw__memory_reads__gti_l3_reads__read + +/* Memory Reads Distribution Gen9 :: Shader Atomic Memory Accesses */ +#define glk__memory_reads__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Memory Writes Distribution Gen9 :: GPU Core Clocks */ +#define glk__memory_writes__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Memory Writes Distribution Gen9 :: EU Active */ +#define glk__memory_writes__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Memory Writes Distribution Gen9 :: GtiMemoryWrites */ +#define glk__memory_writes__gti_memory_writes__read \ + hsw__compute_extended__typed_writes0__read + +/* Memory Writes Distribution Gen9 :: GS Threads Dispatched */ +#define glk__memory_writes__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Memory Writes Distribution Gen9 :: GtiRingAccesses */ +#define glk__memory_writes__gti_ring_accesses__read \ + bdw__memory_reads__gti_ring_accesses__read + +/* Memory Writes Distribution Gen9 :: Early Hi-Depth Test Fails */ +#define glk__memory_writes__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Memory Writes Distribution Gen9 :: VS Threads Dispatched */ +#define glk__memory_writes__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Memory Writes Distribution Gen9 :: FS Threads Dispatched */ +#define glk__memory_writes__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Memory Writes Distribution Gen9 :: GtiMscMemoryWrites */ +#define glk__memory_writes__gti_msc_memory_writes__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* Memory Writes Distribution Gen9 :: Shader Barrier Messages */ +#define glk__memory_writes__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Memory Writes Distribution Gen9 :: GtiCmdStreamerMemoryWrites */ +#define glk__memory_writes__gti_cmd_streamer_memory_writes__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* Memory Writes Distribution Gen9 :: Sampler Texels */ +#define glk__memory_writes__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Memory Writes Distribution Gen9 :: Pixels Failing Tests */ +#define glk__memory_writes__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Memory Writes Distribution Gen9 :: GtiL3Bank0Writes */ +#define glk__memory_writes__gti_l3_bank0_writes__read \ + hsw__compute_extended__typed_atomics0__read + +/* Memory Writes Distribution Gen9 :: GtiL3Bank1Writes */ +#define glk__memory_writes__gti_l3_bank1_writes__read \ + hsw__memory_reads__gti_memory_reads__read + +/* Memory Writes Distribution Gen9 :: GtiL3Bank2Writes */ +#define glk__memory_writes__gti_l3_bank2_writes__read \ + hsw__memory_reads__llc_read_accesses__read + +/* Memory Writes Distribution Gen9 :: GtiL3Bank3Writes */ +#define glk__memory_writes__gti_l3_bank3_writes__read \ + hsw__memory_reads__gpu_core_clocks__read + +/* Memory Writes Distribution Gen9 :: GtiL3Writes */ +#define glk__memory_writes__gti_l3_writes__read \ + bdw__memory_reads__gti_l3_reads__read + +/* Memory Writes Distribution Gen9 :: GPU Time Elapsed */ +#define glk__memory_writes__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Memory Writes Distribution Gen9 :: AVG GPU Core Frequency */ +#define glk__memory_writes__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Memory Writes Distribution Gen9 :: AVG GPU Core Frequency */ +#define glk__memory_writes__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Memory Writes Distribution Gen9 :: Sampler Texels Misses */ +#define glk__memory_writes__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Memory Writes Distribution Gen9 :: CS Threads Dispatched */ +#define glk__memory_writes__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Memory Writes Distribution Gen9 :: SLM Bytes Read */ +#define glk__memory_writes__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Memory Writes Distribution Gen9 :: GtiRccMemoryWrites */ +#define glk__memory_writes__gti_rcc_memory_writes__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* Memory Writes Distribution Gen9 :: GtiSoMemoryWrites */ +#define glk__memory_writes__gti_so_memory_writes__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Memory Writes Distribution Gen9 :: GPU Busy */ +#define glk__memory_writes__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Memory Writes Distribution Gen9 :: GtiStcMemoryWrites */ +#define glk__memory_writes__gti_stc_memory_writes__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* Memory Writes Distribution Gen9 :: Rasterized Pixels */ +#define glk__memory_writes__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Memory Writes Distribution Gen9 :: DS Threads Dispatched */ +#define glk__memory_writes__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Memory Writes Distribution Gen9 :: Samples Written */ +#define glk__memory_writes__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Memory Writes Distribution Gen9 :: EU Stall */ +#define glk__memory_writes__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Memory Writes Distribution Gen9 :: Samples Blended */ +#define glk__memory_writes__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Memory Writes Distribution Gen9 :: Early Depth Test Fails */ +#define glk__memory_writes__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Memory Writes Distribution Gen9 :: Shader Memory Accesses */ +#define glk__memory_writes__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Memory Writes Distribution Gen9 :: HS Threads Dispatched */ +#define glk__memory_writes__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Memory Writes Distribution Gen9 :: GtiRczMemoryWrites */ +#define glk__memory_writes__gti_rcz_memory_writes__read \ + hsw__compute_extended__gpu_clocks__read + +/* Memory Writes Distribution Gen9 :: SLM Bytes Written */ +#define glk__memory_writes__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Memory Writes Distribution Gen9 :: L3 Shader Throughput */ +#define glk__memory_writes__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Memory Writes Distribution Gen9 :: Samples Killed in FS */ +#define glk__memory_writes__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Memory Writes Distribution Gen9 :: GtiHizMemoryWrites */ +#define glk__memory_writes__gti_hiz_memory_writes__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* Memory Writes Distribution Gen9 :: Shader Atomic Memory Accesses */ +#define glk__memory_writes__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Extended Gen9 :: GPU Core Clocks */ +#define glk__compute_extended__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Extended Gen9 :: EU Active */ +#define glk__compute_extended__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Compute Metrics Extended Gen9 :: EU Both FPU Pipes Active */ +#define glk__compute_extended__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Compute Metrics Extended Gen9 :: EU FPU0 Pipe Active */ +#define glk__compute_extended__fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Compute Metrics Extended Gen9 :: EU FPU1 Pipe Active */ +#define glk__compute_extended__fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Compute Metrics Extended Gen9 :: EU AVG IPC Rate */ +#define glk__compute_extended__eu_avg_ipc_rate__read \ + bdw__compute_basic__eu_avg_ipc_rate__read + +/* Compute Metrics Extended Gen9 :: Typed Writes 0 */ +#define glk__compute_extended__typed_writes0__read \ + hsw__compute_extended__typed_writes0__read + +/* Compute Metrics Extended Gen9 :: EuTypedAtomics0 */ +#define glk__compute_extended__eu_typed_atomics0__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* Compute Metrics Extended Gen9 :: Typed Atomics 0 */ +#define glk__compute_extended__typed_atomics0__read \ + hsw__compute_extended__typed_atomics0__read + +/* Compute Metrics Extended Gen9 :: TypedAtomicsPerCacheLine */ +#define glk__compute_extended__typed_atomics_per_cache_line__read \ + hsw__compute_extended__typed_atomics_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: EuUntypedReads0 */ +#define glk__compute_extended__eu_untyped_reads0__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* Compute Metrics Extended Gen9 :: Untyped Writes 0 */ +#define glk__compute_extended__untyped_writes0__read \ + hsw__compute_extended__untyped_writes0__read + +/* Compute Metrics Extended Gen9 :: EuUntypedAtomics0 */ +#define glk__compute_extended__eu_untyped_atomics0__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* Compute Metrics Extended Gen9 :: EuUntypedWrites0 */ +#define glk__compute_extended__eu_untyped_writes0__read \ + hsw__compute_extended__eu_untyped_writes0__read + +/* Compute Metrics Extended Gen9 :: EuA64UntypedWrites0 */ +#define glk__compute_extended__eu_a64_untyped_writes0__read \ + hsw__compute_extended__gpu_clocks__read + +/* Compute Metrics Extended Gen9 :: UntypedWritesPerCacheLine */ +#define glk__compute_extended__untyped_writes_per_cache_line__read \ + bdw__compute_extended__untyped_writes_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: Shader Barrier Messages */ +#define glk__compute_extended__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Compute Metrics Extended Gen9 :: Sampler Texels */ +#define glk__compute_extended__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Compute Metrics Extended Gen9 :: GPU Time Elapsed */ +#define glk__compute_extended__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics Extended Gen9 :: AVG GPU Core Frequency */ +#define glk__compute_extended__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics Extended Gen9 :: AVG GPU Core Frequency */ +#define glk__compute_extended__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics Extended Gen9 :: Sampler Texels Misses */ +#define glk__compute_extended__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Compute Metrics Extended Gen9 :: CS Threads Dispatched */ +#define glk__compute_extended__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Compute Metrics Extended Gen9 :: SLM Bytes Read */ +#define glk__compute_extended__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Compute Metrics Extended Gen9 :: EuTypedWrites0 */ +#define glk__compute_extended__eu_typed_writes0__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* Compute Metrics Extended Gen9 :: TypedWritesPerCacheLine */ +#define glk__compute_extended__typed_writes_per_cache_line__read \ + hsw__compute_extended__typed_writes_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: Typed Reads 0 */ +#define glk__compute_extended__typed_reads0__read \ + hsw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Extended Gen9 :: Untyped Reads 0 */ +#define glk__compute_extended__untyped_reads0__read \ + hsw__compute_extended__untyped_reads0__read + +/* Compute Metrics Extended Gen9 :: EuA64UntypedReads0 */ +#define glk__compute_extended__eu_a64_untyped_reads0__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* Compute Metrics Extended Gen9 :: EU Thread Occupancy */ +#define glk__compute_extended__eu_thread_occupancy__read \ + bdw__compute_basic__eu_thread_occupancy__read + +/* Compute Metrics Extended Gen9 :: EU Stall */ +#define glk__compute_extended__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics Extended Gen9 :: EuTypedReads0 */ +#define glk__compute_extended__eu_typed_reads0__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Compute Metrics Extended Gen9 :: UntypedReadsPerCacheLine */ +#define glk__compute_extended__untyped_reads_per_cache_line__read \ + bdw__compute_extended__untyped_reads_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: Shader Memory Accesses */ +#define glk__compute_extended__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Compute Metrics Extended Gen9 :: TypedReadsPerCacheLine */ +#define glk__compute_extended__typed_reads_per_cache_line__read \ + hsw__compute_extended__typed_reads_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: SLM Bytes Written */ +#define glk__compute_extended__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Compute Metrics Extended Gen9 :: L3 Shader Throughput */ +#define glk__compute_extended__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Compute Metrics Extended Gen9 :: Shader Atomic Memory Accesses */ +#define glk__compute_extended__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Extended Gen9 :: EU Send Pipe Active */ +#define glk__compute_extended__eu_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Compute Metrics L3 Cache Gen9 :: GPU Core Clocks */ +#define glk__compute_l3_cache__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics L3 Cache Gen9 :: EU Active */ +#define glk__compute_l3_cache__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 03 Accesses */ +#define glk__compute_l3_cache__l3_bank03_accesses__read \ + bdw__compute_l3_cache__l3_bank03_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Accesses */ +#define glk__compute_l3_cache__l3_accesses__read \ + sklgt2__compute_l3_cache__l3_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: EU Both FPU Pipes Active */ +#define glk__compute_l3_cache__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Sampler Throughput */ +#define glk__compute_l3_cache__l3_sampler_throughput__read \ + chv__render_basic__l3_sampler_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Pipe Active */ +#define glk__compute_l3_cache__fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Pipe Active */ +#define glk__compute_l3_cache__fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Compute Metrics L3 Cache Gen9 :: EU AVG IPC Rate */ +#define glk__compute_l3_cache__eu_avg_ipc_rate__read \ + bdw__compute_basic__eu_avg_ipc_rate__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Binary Instruction */ +#define glk__compute_l3_cache__eu_binary_fpu0_instruction__read \ + bdw__render_basic__ps_send_active__read + +/* Compute Metrics L3 Cache Gen9 :: GS Threads Dispatched */ +#define glk__compute_l3_cache__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Compute Metrics L3 Cache Gen9 :: Shader Memory Accesses */ +#define glk__compute_l3_cache__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: Early Hi-Depth Test Fails */ +#define glk__compute_l3_cache__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Compute Metrics L3 Cache Gen9 :: VS Threads Dispatched */ +#define glk__compute_l3_cache__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Compute Metrics L3 Cache Gen9 :: FS Threads Dispatched */ +#define glk__compute_l3_cache__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Hybrid Instruction */ +#define glk__compute_l3_cache__eu_hybrid_fpu0_instruction__read \ + bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Misses */ +#define glk__compute_l3_cache__l3_misses__read \ + bdw__compute_l3_cache__l3_misses__read + +/* Compute Metrics L3 Cache Gen9 :: Shader Barrier Messages */ +#define glk__compute_l3_cache__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 Accesses */ +#define glk__compute_l3_cache__l3_bank00_accesses__read \ + bdw__compute_l3_cache__l3_bank00_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Move Instruction */ +#define glk__compute_l3_cache__eu_move_fpu0_instruction__read \ + bdw__compute_l3_cache__eu_move_fpu0_instruction__read + +/* Compute Metrics L3 Cache Gen9 :: Sampler Texels */ +#define glk__compute_l3_cache__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Compute Metrics L3 Cache Gen9 :: Pixels Failing Tests */ +#define glk__compute_l3_cache__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Hybrid Instruction */ +#define glk__compute_l3_cache__eu_hybrid_fpu1_instruction__read \ + bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read + +/* Compute Metrics L3 Cache Gen9 :: GPU Time Elapsed */ +#define glk__compute_l3_cache__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics L3 Cache Gen9 :: AVG GPU Core Frequency */ +#define glk__compute_l3_cache__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics L3 Cache Gen9 :: AVG GPU Core Frequency */ +#define glk__compute_l3_cache__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics L3 Cache Gen9 :: Sampler Texels Misses */ +#define glk__compute_l3_cache__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Compute Metrics L3 Cache Gen9 :: CS Threads Dispatched */ +#define glk__compute_l3_cache__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Compute Metrics L3 Cache Gen9 :: SLM Bytes Read */ +#define glk__compute_l3_cache__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Compute Metrics L3 Cache Gen9 :: GTI Read Throughput */ +#define glk__compute_l3_cache__gti_read_throughput__read \ + bdw__render_basic__gti_read_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: GTI L3 Throughput */ +#define glk__compute_l3_cache__gti_l3_throughput__read \ + bdw__compute_l3_cache__gti_l3_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 IC Accesses */ +#define glk__compute_l3_cache__l3_bank00_ic_accesses__read \ + bdw__compute_l3_cache__l3_bank00_ic_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 IC Hits */ +#define glk__compute_l3_cache__l3_bank00_ic_hits__read \ + bdw__compute_l3_cache__l3_bank00_ic_hits__read + +/* Compute Metrics L3 Cache Gen9 :: Sampler Accesses */ +#define glk__compute_l3_cache__sampler_accesses__read \ + bdw__render_pipe_profile__sampler_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 01 Accesses */ +#define glk__compute_l3_cache__l3_bank01_accesses__read \ + bdw__compute_l3_cache__l3_bank01_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: GPU Busy */ +#define glk__compute_l3_cache__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Ternary Instruction */ +#define glk__compute_l3_cache__eu_ternary_fpu0_instruction__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Compute Metrics L3 Cache Gen9 :: Shader Atomic Memory Accesses */ +#define glk__compute_l3_cache__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics L3 Cache Gen9 :: Rasterized Pixels */ +#define glk__compute_l3_cache__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Compute Metrics L3 Cache Gen9 :: DS Threads Dispatched */ +#define glk__compute_l3_cache__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Compute Metrics L3 Cache Gen9 :: Samples Written */ +#define glk__compute_l3_cache__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Move Instruction */ +#define glk__compute_l3_cache__eu_move_fpu1_instruction__read \ + bdw__compute_l3_cache__eu_move_fpu1_instruction__read + +/* Compute Metrics L3 Cache Gen9 :: EU Stall */ +#define glk__compute_l3_cache__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics L3 Cache Gen9 :: Samples Blended */ +#define glk__compute_l3_cache__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Compute Metrics L3 Cache Gen9 :: Early Depth Test Fails */ +#define glk__compute_l3_cache__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 02 Accesses */ +#define glk__compute_l3_cache__l3_bank02_accesses__read \ + bdw__compute_l3_cache__l3_bank02_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: HS Threads Dispatched */ +#define glk__compute_l3_cache__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Total Throughput */ +#define glk__compute_l3_cache__l3_total_throughput__read \ + sklgt2__compute_l3_cache__l3_total_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: GTI Write Throughput */ +#define glk__compute_l3_cache__gti_write_throughput__read \ + hsw__render_basic__gti_write_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: SLM Bytes Written */ +#define glk__compute_l3_cache__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Shader Throughput */ +#define glk__compute_l3_cache__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: Samples Killed in FS */ +#define glk__compute_l3_cache__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Binary Instruction */ +#define glk__compute_l3_cache__eu_binary_fpu1_instruction__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Ternary Instruction */ +#define glk__compute_l3_cache__eu_ternary_fpu1_instruction__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Compute Metrics L3 Cache Gen9 :: EU Send Pipe Active */ +#define glk__compute_l3_cache__eu_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set HDCAndSF :: GPU Core Clocks */ +#define glk__hdc_and_sf__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set HDCAndSF :: EU Active */ +#define glk__hdc_and_sf__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set HDCAndSF :: EU Both FPU Pipes Active */ +#define glk__hdc_and_sf__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set HDCAndSF :: VS Send Pipe Active */ +#define glk__hdc_and_sf__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set HDCAndSF :: VS FPU1 Pipe Active */ +#define glk__hdc_and_sf__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set HDCAndSF :: GS Threads Dispatched */ +#define glk__hdc_and_sf__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set HDCAndSF :: Early Hi-Depth Test Fails */ +#define glk__hdc_and_sf__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set HDCAndSF :: FS Both FPU Active */ +#define glk__hdc_and_sf__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set HDCAndSF :: VS Threads Dispatched */ +#define glk__hdc_and_sf__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set HDCAndSF :: Polygon Data Ready */ +#define glk__hdc_and_sf__poly_data_ready__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set HDCAndSF :: FS Threads Dispatched */ +#define glk__hdc_and_sf__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set HDCAndSF :: Shader Barrier Messages */ +#define glk__hdc_and_sf__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set HDCAndSF :: Sampler Texels */ +#define glk__hdc_and_sf__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set HDCAndSF :: Pixels Failing Tests */ +#define glk__hdc_and_sf__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set HDCAndSF :: GPU Time Elapsed */ +#define glk__hdc_and_sf__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set HDCAndSF :: AVG GPU Core Frequency */ +#define glk__hdc_and_sf__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set HDCAndSF :: AVG GPU Core Frequency */ +#define glk__hdc_and_sf__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set HDCAndSF :: Sampler Texels Misses */ +#define glk__hdc_and_sf__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */ +#define glk__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read \ + bdw__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read + +/* Metric set HDCAndSF :: CS Threads Dispatched */ +#define glk__hdc_and_sf__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set HDCAndSF :: SLM Bytes Read */ +#define glk__hdc_and_sf__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set HDCAndSF :: PS FPU1 Pipe Active */ +#define glk__hdc_and_sf__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set HDCAndSF :: PS Send Pipeline Active */ +#define glk__hdc_and_sf__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set HDCAndSF :: VS FPU0 Pipe Active */ +#define glk__hdc_and_sf__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set HDCAndSF :: GPU Busy */ +#define glk__hdc_and_sf__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set HDCAndSF :: Rasterized Pixels */ +#define glk__hdc_and_sf__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set HDCAndSF :: PS FPU0 Pipe Active */ +#define glk__hdc_and_sf__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set HDCAndSF :: DS Threads Dispatched */ +#define glk__hdc_and_sf__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set HDCAndSF :: Samples Written */ +#define glk__hdc_and_sf__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set HDCAndSF :: EU Stall */ +#define glk__hdc_and_sf__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set HDCAndSF :: Samples Blended */ +#define glk__hdc_and_sf__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set HDCAndSF :: Early Depth Test Fails */ +#define glk__hdc_and_sf__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set HDCAndSF :: Shader Memory Accesses */ +#define glk__hdc_and_sf__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set HDCAndSF :: HS Threads Dispatched */ +#define glk__hdc_and_sf__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set HDCAndSF :: SLM Bytes Written */ +#define glk__hdc_and_sf__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set HDCAndSF :: L3 Shader Throughput */ +#define glk__hdc_and_sf__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set HDCAndSF :: Samples Killed in FS */ +#define glk__hdc_and_sf__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */ +#define glk__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read \ + bdw__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read + +/* Metric set HDCAndSF :: Shader Atomic Memory Accesses */ +#define glk__hdc_and_sf__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set L3_1 :: GPU Core Clocks */ +#define glk__l3_1__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set L3_1 :: EU Active */ +#define glk__l3_1__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set L3_1 :: Slice0 L3 Bank1 Active */ +#define glk__l3_1__l30_bank1_active__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set L3_1 :: EU Both FPU Pipes Active */ +#define glk__l3_1__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set L3_1 :: VS Send Pipe Active */ +#define glk__l3_1__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set L3_1 :: VS FPU1 Pipe Active */ +#define glk__l3_1__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set L3_1 :: GS Threads Dispatched */ +#define glk__l3_1__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set L3_1 :: Early Hi-Depth Test Fails */ +#define glk__l3_1__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set L3_1 :: FS Both FPU Active */ +#define glk__l3_1__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set L3_1 :: VS Threads Dispatched */ +#define glk__l3_1__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set L3_1 :: Slice0 L3 Bank1 Stalled */ +#define glk__l3_1__l30_bank1_stalled__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Metric set L3_1 :: FS Threads Dispatched */ +#define glk__l3_1__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set L3_1 :: Shader Barrier Messages */ +#define glk__l3_1__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set L3_1 :: Sampler Texels */ +#define glk__l3_1__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set L3_1 :: Pixels Failing Tests */ +#define glk__l3_1__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set L3_1 :: GPU Time Elapsed */ +#define glk__l3_1__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set L3_1 :: AVG GPU Core Frequency */ +#define glk__l3_1__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set L3_1 :: AVG GPU Core Frequency */ +#define glk__l3_1__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set L3_1 :: Sampler Texels Misses */ +#define glk__l3_1__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set L3_1 :: CS Threads Dispatched */ +#define glk__l3_1__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set L3_1 :: SLM Bytes Read */ +#define glk__l3_1__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set L3_1 :: PS FPU1 Pipe Active */ +#define glk__l3_1__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set L3_1 :: PS Send Pipeline Active */ +#define glk__l3_1__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set L3_1 :: VS FPU0 Pipe Active */ +#define glk__l3_1__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set L3_1 :: GPU Busy */ +#define glk__l3_1__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set L3_1 :: Slice0 L3 Bank0 Active */ +#define glk__l3_1__l30_bank0_active__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set L3_1 :: Rasterized Pixels */ +#define glk__l3_1__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set L3_1 :: PS FPU0 Pipe Active */ +#define glk__l3_1__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set L3_1 :: Slice0 L3 Bank0 Stalled */ +#define glk__l3_1__l30_bank0_stalled__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set L3_1 :: DS Threads Dispatched */ +#define glk__l3_1__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set L3_1 :: Samples Written */ +#define glk__l3_1__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set L3_1 :: EU Stall */ +#define glk__l3_1__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set L3_1 :: Samples Blended */ +#define glk__l3_1__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set L3_1 :: Early Depth Test Fails */ +#define glk__l3_1__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set L3_1 :: Shader Memory Accesses */ +#define glk__l3_1__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set L3_1 :: HS Threads Dispatched */ +#define glk__l3_1__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set L3_1 :: SLM Bytes Written */ +#define glk__l3_1__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set L3_1 :: L3 Shader Throughput */ +#define glk__l3_1__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set L3_1 :: Samples Killed in FS */ +#define glk__l3_1__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set L3_1 :: Shader Atomic Memory Accesses */ +#define glk__l3_1__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */ +#define glk__rasterizer_and_pixel_backend__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set RasterizerAndPixelBackend :: EU Active */ +#define glk__rasterizer_and_pixel_backend__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set RasterizerAndPixelBackend :: EU Both FPU Pipes Active */ +#define glk__rasterizer_and_pixel_backend__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set RasterizerAndPixelBackend :: VS Send Pipe Active */ +#define glk__rasterizer_and_pixel_backend__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set RasterizerAndPixelBackend :: VS FPU1 Pipe Active */ +#define glk__rasterizer_and_pixel_backend__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */ +#define glk__rasterizer_and_pixel_backend__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */ +#define glk__rasterizer_and_pixel_backend__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set RasterizerAndPixelBackend :: FS Both FPU Active */ +#define glk__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */ +#define glk__rasterizer_and_pixel_backend__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */ +#define glk__rasterizer_and_pixel_backend__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Pixel Values Ready */ +#define glk__rasterizer_and_pixel_backend__pixel_values0_ready__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */ +#define glk__rasterizer_and_pixel_backend__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set RasterizerAndPixelBackend :: Sampler Texels */ +#define glk__rasterizer_and_pixel_backend__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */ +#define glk__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */ +#define glk__rasterizer_and_pixel_backend__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ +#define glk__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ +#define glk__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */ +#define glk__rasterizer_and_pixel_backend__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */ +#define glk__rasterizer_and_pixel_backend__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */ +#define glk__rasterizer_and_pixel_backend__rasterizer0_input_available__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Post-EarlyZ Pixel Data Ready */ +#define glk__rasterizer_and_pixel_backend__pixel_data0_ready__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */ +#define glk__rasterizer_and_pixel_backend__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set RasterizerAndPixelBackend :: PS FPU1 Pipe Active */ +#define glk__rasterizer_and_pixel_backend__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set RasterizerAndPixelBackend :: PS Send Pipeline Active */ +#define glk__rasterizer_and_pixel_backend__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set RasterizerAndPixelBackend :: VS FPU0 Pipe Active */ +#define glk__rasterizer_and_pixel_backend__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set RasterizerAndPixelBackend :: GPU Busy */ +#define glk__rasterizer_and_pixel_backend__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */ +#define glk__rasterizer_and_pixel_backend__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set RasterizerAndPixelBackend :: PS FPU0 Pipe Active */ +#define glk__rasterizer_and_pixel_backend__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */ +#define glk__rasterizer_and_pixel_backend__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set RasterizerAndPixelBackend :: Samples Written */ +#define glk__rasterizer_and_pixel_backend__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set RasterizerAndPixelBackend :: EU Stall */ +#define glk__rasterizer_and_pixel_backend__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */ +#define glk__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set RasterizerAndPixelBackend :: Samples Blended */ +#define glk__rasterizer_and_pixel_backend__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */ +#define glk__rasterizer_and_pixel_backend__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */ +#define glk__rasterizer_and_pixel_backend__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */ +#define glk__rasterizer_and_pixel_backend__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */ +#define glk__rasterizer_and_pixel_backend__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */ +#define glk__rasterizer_and_pixel_backend__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */ +#define glk__rasterizer_and_pixel_backend__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 PS Output Available */ +#define glk__rasterizer_and_pixel_backend__ps_output0_available__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */ +#define glk__rasterizer_and_pixel_backend__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set Sampler :: GPU Core Clocks */ +#define glk__sampler__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set Sampler :: EU Active */ +#define glk__sampler__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set Sampler :: Slice0 Subslice2 Input Available */ +#define glk__sampler__sampler02_input_available__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set Sampler :: EU Both FPU Pipes Active */ +#define glk__sampler__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set Sampler :: VS Send Pipe Active */ +#define glk__sampler__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set Sampler :: Slice0 Subslice0 Input Available */ +#define glk__sampler__sampler00_input_available__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Metric set Sampler :: VS FPU1 Pipe Active */ +#define glk__sampler__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set Sampler :: GS Threads Dispatched */ +#define glk__sampler__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set Sampler :: Early Hi-Depth Test Fails */ +#define glk__sampler__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set Sampler :: FS Both FPU Active */ +#define glk__sampler__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set Sampler :: VS Threads Dispatched */ +#define glk__sampler__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set Sampler :: Slice0 Subslice2 Sampler Output Ready */ +#define glk__sampler__sampler02_output_ready__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set Sampler :: FS Threads Dispatched */ +#define glk__sampler__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set Sampler :: Shader Barrier Messages */ +#define glk__sampler__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set Sampler :: Slice0 Subslice1 Input Available */ +#define glk__sampler__sampler01_input_available__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set Sampler :: Sampler Texels */ +#define glk__sampler__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set Sampler :: Pixels Failing Tests */ +#define glk__sampler__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set Sampler :: GPU Time Elapsed */ +#define glk__sampler__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set Sampler :: AVG GPU Core Frequency */ +#define glk__sampler__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set Sampler :: AVG GPU Core Frequency */ +#define glk__sampler__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set Sampler :: Sampler Texels Misses */ +#define glk__sampler__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set Sampler :: CS Threads Dispatched */ +#define glk__sampler__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set Sampler :: SLM Bytes Read */ +#define glk__sampler__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set Sampler :: PS FPU1 Pipe Active */ +#define glk__sampler__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set Sampler :: PS Send Pipeline Active */ +#define glk__sampler__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set Sampler :: VS FPU0 Pipe Active */ +#define glk__sampler__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set Sampler :: GPU Busy */ +#define glk__sampler__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set Sampler :: Rasterized Pixels */ +#define glk__sampler__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set Sampler :: PS FPU0 Pipe Active */ +#define glk__sampler__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set Sampler :: DS Threads Dispatched */ +#define glk__sampler__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set Sampler :: Samples Written */ +#define glk__sampler__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set Sampler :: EU Stall */ +#define glk__sampler__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set Sampler :: Samples Blended */ +#define glk__sampler__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set Sampler :: Early Depth Test Fails */ +#define glk__sampler__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set Sampler :: Slice0 Subslice0 Sampler Output Ready */ +#define glk__sampler__sampler00_output_ready__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set Sampler :: Slice0 Subslice1 Sampler Output Ready */ +#define glk__sampler__sampler01_output_ready__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set Sampler :: Shader Memory Accesses */ +#define glk__sampler__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set Sampler :: HS Threads Dispatched */ +#define glk__sampler__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set Sampler :: SLM Bytes Written */ +#define glk__sampler__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set Sampler :: L3 Shader Throughput */ +#define glk__sampler__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set Sampler :: Samples Killed in FS */ +#define glk__sampler__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set Sampler :: Shader Atomic Memory Accesses */ +#define glk__sampler__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set TDL_1 :: GPU Core Clocks */ +#define glk__tdl_1__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set TDL_1 :: EU Active */ +#define glk__tdl_1__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set TDL_1 :: EU Both FPU Pipes Active */ +#define glk__tdl_1__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set TDL_1 :: VS Send Pipe Active */ +#define glk__tdl_1__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set TDL_1 :: VS FPU1 Pipe Active */ +#define glk__tdl_1__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set TDL_1 :: GS Threads Dispatched */ +#define glk__tdl_1__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set TDL_1 :: Early Hi-Depth Test Fails */ +#define glk__tdl_1__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set TDL_1 :: FS Both FPU Active */ +#define glk__tdl_1__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set TDL_1 :: VS Threads Dispatched */ +#define glk__tdl_1__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set TDL_1 :: FS Threads Dispatched */ +#define glk__tdl_1__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice2 */ +#define glk__tdl_1__non_ps_thread02_ready_for_dispatch__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Metric set TDL_1 :: Shader Barrier Messages */ +#define glk__tdl_1__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_1 :: Sampler Texels */ +#define glk__tdl_1__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set TDL_1 :: Pixels Failing Tests */ +#define glk__tdl_1__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set TDL_1 :: GPU Time Elapsed */ +#define glk__tdl_1__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set TDL_1 :: AVG GPU Core Frequency */ +#define glk__tdl_1__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set TDL_1 :: AVG GPU Core Frequency */ +#define glk__tdl_1__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set TDL_1 :: Sampler Texels Misses */ +#define glk__tdl_1__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice0 */ +#define glk__tdl_1__non_ps_thread00_ready_for_dispatch__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Metric set TDL_1 :: CS Threads Dispatched */ +#define glk__tdl_1__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set TDL_1 :: SLM Bytes Read */ +#define glk__tdl_1__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set TDL_1 :: PS FPU1 Pipe Active */ +#define glk__tdl_1__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set TDL_1 :: PS Send Pipeline Active */ +#define glk__tdl_1__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set TDL_1 :: VS FPU0 Pipe Active */ +#define glk__tdl_1__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set TDL_1 :: GPU Busy */ +#define glk__tdl_1__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice0 */ +#define glk__tdl_1__ps_thread00_ready_for_dispatch__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set TDL_1 :: Rasterized Pixels */ +#define glk__tdl_1__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set TDL_1 :: PS FPU0 Pipe Active */ +#define glk__tdl_1__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set TDL_1 :: DS Threads Dispatched */ +#define glk__tdl_1__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set TDL_1 :: Samples Written */ +#define glk__tdl_1__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set TDL_1 :: EU Stall */ +#define glk__tdl_1__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set TDL_1 :: Samples Blended */ +#define glk__tdl_1__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set TDL_1 :: Early Depth Test Fails */ +#define glk__tdl_1__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice1 */ +#define glk__tdl_1__ps_thread01_ready_for_dispatch__read \ + bdw__render_pipe_profile__cl_bottleneck__read + +/* Metric set TDL_1 :: Shader Memory Accesses */ +#define glk__tdl_1__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set TDL_1 :: HS Threads Dispatched */ +#define glk__tdl_1__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice2 */ +#define glk__tdl_1__ps_thread02_ready_for_dispatch__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Metric set TDL_1 :: SLM Bytes Written */ +#define glk__tdl_1__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set TDL_1 :: L3 Shader Throughput */ +#define glk__tdl_1__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set TDL_1 :: Samples Killed in FS */ +#define glk__tdl_1__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set TDL_1 :: Shader Atomic Memory Accesses */ +#define glk__tdl_1__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice1 */ +#define glk__tdl_1__non_ps_thread01_ready_for_dispatch__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set TDL_2 :: GPU Core Clocks */ +#define glk__tdl_2__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set TDL_2 :: EU Active */ +#define glk__tdl_2__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set TDL_2 :: EU Both FPU Pipes Active */ +#define glk__tdl_2__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set TDL_2 :: VS Send Pipe Active */ +#define glk__tdl_2__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set TDL_2 :: VS FPU1 Pipe Active */ +#define glk__tdl_2__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set TDL_2 :: GS Threads Dispatched */ +#define glk__tdl_2__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set TDL_2 :: Early Hi-Depth Test Fails */ +#define glk__tdl_2__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set TDL_2 :: FS Both FPU Active */ +#define glk__tdl_2__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set TDL_2 :: VS Threads Dispatched */ +#define glk__tdl_2__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set TDL_2 :: FS Threads Dispatched */ +#define glk__tdl_2__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set TDL_2 :: Shader Barrier Messages */ +#define glk__tdl_2__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_2 :: Sampler Texels */ +#define glk__tdl_2__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set TDL_2 :: Pixels Failing Tests */ +#define glk__tdl_2__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 0 */ +#define glk__tdl_2__thread_header01_ready_port0__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 1 */ +#define glk__tdl_2__thread_header01_ready_port1__read \ + bdw__render_pipe_profile__ds_stall__read + +/* Metric set TDL_2 :: GPU Time Elapsed */ +#define glk__tdl_2__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set TDL_2 :: AVG GPU Core Frequency */ +#define glk__tdl_2__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set TDL_2 :: AVG GPU Core Frequency */ +#define glk__tdl_2__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set TDL_2 :: Sampler Texels Misses */ +#define glk__tdl_2__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set TDL_2 :: CS Threads Dispatched */ +#define glk__tdl_2__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set TDL_2 :: SLM Bytes Read */ +#define glk__tdl_2__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set TDL_2 :: PS FPU1 Pipe Active */ +#define glk__tdl_2__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set TDL_2 :: PS Send Pipeline Active */ +#define glk__tdl_2__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set TDL_2 :: VS FPU0 Pipe Active */ +#define glk__tdl_2__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set TDL_2 :: GPU Busy */ +#define glk__tdl_2__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 1 */ +#define glk__tdl_2__thread_header02_ready_port1__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 0 */ +#define glk__tdl_2__thread_header02_ready_port0__read \ + bdw__render_pipe_profile__so_stall__read + +/* Metric set TDL_2 :: Rasterized Pixels */ +#define glk__tdl_2__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set TDL_2 :: PS FPU0 Pipe Active */ +#define glk__tdl_2__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set TDL_2 :: DS Threads Dispatched */ +#define glk__tdl_2__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set TDL_2 :: Samples Written */ +#define glk__tdl_2__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set TDL_2 :: EU Stall */ +#define glk__tdl_2__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set TDL_2 :: Samples Blended */ +#define glk__tdl_2__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set TDL_2 :: Early Depth Test Fails */ +#define glk__tdl_2__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_2 :: Shader Memory Accesses */ +#define glk__tdl_2__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set TDL_2 :: HS Threads Dispatched */ +#define glk__tdl_2__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set TDL_2 :: SLM Bytes Written */ +#define glk__tdl_2__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set TDL_2 :: L3 Shader Throughput */ +#define glk__tdl_2__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set TDL_2 :: Samples Killed in FS */ +#define glk__tdl_2__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 0 */ +#define glk__tdl_2__thread_header00_ready_port0__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set TDL_2 :: Shader Atomic Memory Accesses */ +#define glk__tdl_2__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 1 */ +#define glk__tdl_2__thread_header00_ready_port1__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Compute Metrics Extra Gen9 :: GPU Core Clocks */ +#define glk__compute_extra__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Extra Gen9 :: EU FPU1 Pipe Active */ +#define glk__compute_extra__fpu1_active__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics Extra Gen9 :: GPU Time Elapsed */ +#define glk__compute_extra__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics Extra Gen9 :: AVG GPU Core Frequency */ +#define glk__compute_extra__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics Extra Gen9 :: AVG GPU Core Frequency */ +#define glk__compute_extra__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics Extra Gen9 :: EU FPU1 Pipe Active including Ext Math */ +#define glk__compute_extra__fpu1_active_adjusted__read \ + sklgt2__compute_extra__fpu1_active_adjusted__read + +/* MDAPI testing set Gen9 :: TestCounter7 */ +#define glk__test_oa__counter7__read \ + hsw__compute_extended__gpu_clocks__read + +/* MDAPI testing set Gen9 :: GPU Time Elapsed */ +#define glk__test_oa__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* MDAPI testing set Gen9 :: GPU Core Clocks */ +#define glk__test_oa__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* MDAPI testing set Gen9 :: AVG GPU Core Frequency */ +#define glk__test_oa__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* MDAPI testing set Gen9 :: AVG GPU Core Frequency */ +#define glk__test_oa__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* MDAPI testing set Gen9 :: TestCounter8 */ +#define glk__test_oa__counter8__read \ + hsw__memory_reads__gpu_core_clocks__read + +/* MDAPI testing set Gen9 :: TestCounter4 */ +#define glk__test_oa__counter4__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* MDAPI testing set Gen9 :: TestCounter5 */ +#define glk__test_oa__counter5__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* MDAPI testing set Gen9 :: TestCounter6 */ +#define glk__test_oa__counter6__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* MDAPI testing set Gen9 :: TestCounter3 */ +#define glk__test_oa__counter3__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* MDAPI testing set Gen9 :: TestCounter0 */ +#define glk__test_oa__counter0__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* MDAPI testing set Gen9 :: TestCounter1 */ +#define glk__test_oa__counter1__read \ + hsw__compute_extended__eu_untyped_writes0__read + +/* MDAPI testing set Gen9 :: TestCounter2 */ +#define glk__test_oa__counter2__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Render Metrics Basic Gen9 :: GPU Core Clocks */ +#define cflgt2__render_basic__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Render Metrics Basic Gen9 :: EU Active */ +#define cflgt2__render_basic__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Render Metrics Basic Gen9 :: L3 Misses */ +#define cflgt2__render_basic__l3_misses__read \ + hsw__compute_extended__typed_atomics0__read + +/* Render Metrics Basic Gen9 :: GTI L3 Throughput */ +#define cflgt2__render_basic__gti_l3_throughput__read \ + hsw__render_basic__gti_l3_throughput__read + +/* Render Metrics Basic Gen9 :: EU Both FPU Pipes Active */ +#define cflgt2__render_basic__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Render Metrics Basic Gen9 :: Sampler Cache Misses */ +#define cflgt2__render_basic__sampler_l1_misses__read \ + sklgt2__render_basic__sampler_l1_misses__read + +/* Render Metrics Basic Gen9 :: VS Send Pipe Active */ +#define cflgt2__render_basic__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Render Metrics Basic Gen9 :: Sampler 1 Bottleneck */ +#define cflgt2__render_basic__sampler1_bottleneck__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Render Metrics Basic Gen9 :: VS FPU1 Pipe Active */ +#define cflgt2__render_basic__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Render Metrics Basic Gen9 :: GS Threads Dispatched */ +#define cflgt2__render_basic__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Render Metrics Basic Gen9 :: L3 Sampler Throughput */ +#define cflgt2__render_basic__l3_sampler_throughput__read \ + sklgt2__render_basic__l3_sampler_throughput__read + +/* Render Metrics Basic Gen9 :: Early Hi-Depth Test Fails */ +#define cflgt2__render_basic__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Render Metrics Basic Gen9 :: FS Both FPU Active */ +#define cflgt2__render_basic__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Render Metrics Basic Gen9 :: VS Threads Dispatched */ +#define cflgt2__render_basic__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Render Metrics Basic Gen9 :: FS Threads Dispatched */ +#define cflgt2__render_basic__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Render Metrics Basic Gen9 :: Sampler 0 Busy */ +#define cflgt2__render_basic__sampler0_busy__read \ + bdw__render_basic__sampler0_busy__read + +/* Render Metrics Basic Gen9 :: Sampler 1 Busy */ +#define cflgt2__render_basic__sampler1_busy__read \ + bdw__render_basic__sampler1_busy__read + +/* Render Metrics Basic Gen9 :: Samplers Busy */ +#define cflgt2__render_basic__samplers_busy__read \ + bdw__render_basic__samplers_busy__read + +/* Render Metrics Basic Gen9 :: GTI Fixed Pipe Throughput */ +#define cflgt2__render_basic__gti_vf_throughput__read \ + bdw__render_basic__gti_vf_throughput__read + +/* Render Metrics Basic Gen9 :: Shader Barrier Messages */ +#define cflgt2__render_basic__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Render Metrics Basic Gen9 :: Sampler 0 Bottleneck */ +#define cflgt2__render_basic__sampler0_bottleneck__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Render Metrics Basic Gen9 :: Sampler Texels */ +#define cflgt2__render_basic__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Render Metrics Basic Gen9 :: Pixels Failing Tests */ +#define cflgt2__render_basic__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Render Metrics Basic Gen9 :: GPU Time Elapsed */ +#define cflgt2__render_basic__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Render Metrics Basic Gen9 :: AVG GPU Core Frequency */ +#define cflgt2__render_basic__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Render Metrics Basic Gen9 :: AVG GPU Core Frequency */ +#define cflgt2__render_basic__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Render Metrics Basic Gen9 :: Sampler Texels Misses */ +#define cflgt2__render_basic__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Render Metrics Basic Gen9 :: CS Threads Dispatched */ +#define cflgt2__render_basic__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Render Metrics Basic Gen9 :: Shader Memory Accesses */ +#define cflgt2__render_basic__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Render Metrics Basic Gen9 :: L3 Lookup Accesses w/o IC */ +#define cflgt2__render_basic__l3_lookups__read \ + sklgt2__render_basic__l3_lookups__read + +/* Render Metrics Basic Gen9 :: SLM Bytes Read */ +#define cflgt2__render_basic__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Render Metrics Basic Gen9 :: GTI Read Throughput */ +#define cflgt2__render_basic__gti_read_throughput__read \ + bdw__render_basic__gti_read_throughput__read + +/* Render Metrics Basic Gen9 :: PS FPU1 Pipe Active */ +#define cflgt2__render_basic__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Render Metrics Basic Gen9 :: PS Send Pipeline Active */ +#define cflgt2__render_basic__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Render Metrics Basic Gen9 :: Rasterized Pixels */ +#define cflgt2__render_basic__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Render Metrics Basic Gen9 :: GPU Busy */ +#define cflgt2__render_basic__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Render Metrics Basic Gen9 :: GTI Depth Throughput */ +#define cflgt2__render_basic__gti_depth_throughput__read \ + bdw__render_basic__gti_depth_throughput__read + +/* Render Metrics Basic Gen9 :: VS FPU0 Pipe Active */ +#define cflgt2__render_basic__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Render Metrics Basic Gen9 :: PS FPU0 Pipe Active */ +#define cflgt2__render_basic__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Render Metrics Basic Gen9 :: DS Threads Dispatched */ +#define cflgt2__render_basic__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Render Metrics Basic Gen9 :: Samples Written */ +#define cflgt2__render_basic__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Render Metrics Basic Gen9 :: EU Stall */ +#define cflgt2__render_basic__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Render Metrics Basic Gen9 :: Samples Blended */ +#define cflgt2__render_basic__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Render Metrics Basic Gen9 :: Early Depth Test Fails */ +#define cflgt2__render_basic__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Render Metrics Basic Gen9 :: Samplers Bottleneck */ +#define cflgt2__render_basic__sampler_bottleneck__read \ + bdw__render_basic__sampler_bottleneck__read + +/* Render Metrics Basic Gen9 :: GTI HDC TLB Lookup Throughput */ +#define cflgt2__render_basic__gti_hdc_lookups_throughput__read \ + bdw__render_basic__gti_hdc_lookups_throughput__read + +/* Render Metrics Basic Gen9 :: GTI RCC Throughput */ +#define cflgt2__render_basic__gti_rcc_throughput__read \ + bdw__render_basic__gti_rcc_throughput__read + +/* Render Metrics Basic Gen9 :: HS Threads Dispatched */ +#define cflgt2__render_basic__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Render Metrics Basic Gen9 :: GTI Write Throughput */ +#define cflgt2__render_basic__gti_write_throughput__read \ + hsw__render_basic__gti_write_throughput__read + +/* Render Metrics Basic Gen9 :: SLM Bytes Written */ +#define cflgt2__render_basic__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Render Metrics Basic Gen9 :: L3 Shader Throughput */ +#define cflgt2__render_basic__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Render Metrics Basic Gen9 :: Samples Killed in FS */ +#define cflgt2__render_basic__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Render Metrics Basic Gen9 :: Shader Atomic Memory Accesses */ +#define cflgt2__render_basic__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Basic Gen9 :: GPU Core Clocks */ +#define cflgt2__compute_basic__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Basic Gen9 :: EU Active */ +#define cflgt2__compute_basic__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Compute Metrics Basic Gen9 :: Untyped Bytes Read */ +#define cflgt2__compute_basic__untyped_bytes_read__read \ + bdw__compute_basic__untyped_bytes_read__read + +/* Compute Metrics Basic Gen9 :: EU Both FPU Pipes Active */ +#define cflgt2__compute_basic__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Compute Metrics Basic Gen9 :: Typed Bytes Written */ +#define cflgt2__compute_basic__typed_bytes_written__read \ + bdw__compute_basic__typed_bytes_written__read + +/* Compute Metrics Basic Gen9 :: EU FPU0 Pipe Active */ +#define cflgt2__compute_basic__fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Compute Metrics Basic Gen9 :: EU FPU1 Pipe Active */ +#define cflgt2__compute_basic__fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Compute Metrics Basic Gen9 :: EU AVG IPC Rate */ +#define cflgt2__compute_basic__eu_avg_ipc_rate__read \ + bdw__compute_basic__eu_avg_ipc_rate__read + +/* Compute Metrics Basic Gen9 :: GS Threads Dispatched */ +#define cflgt2__compute_basic__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Compute Metrics Basic Gen9 :: Early Hi-Depth Test Fails */ +#define cflgt2__compute_basic__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Compute Metrics Basic Gen9 :: VS Threads Dispatched */ +#define cflgt2__compute_basic__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Compute Metrics Basic Gen9 :: FS Threads Dispatched */ +#define cflgt2__compute_basic__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Compute Metrics Basic Gen9 :: Shader Barrier Messages */ +#define cflgt2__compute_basic__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Compute Metrics Basic Gen9 :: Sampler Texels */ +#define cflgt2__compute_basic__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Compute Metrics Basic Gen9 :: Pixels Failing Tests */ +#define cflgt2__compute_basic__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Compute Metrics Basic Gen9 :: GPU Time Elapsed */ +#define cflgt2__compute_basic__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics Basic Gen9 :: AVG GPU Core Frequency */ +#define cflgt2__compute_basic__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics Basic Gen9 :: AVG GPU Core Frequency */ +#define cflgt2__compute_basic__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics Basic Gen9 :: Sampler Texels Misses */ +#define cflgt2__compute_basic__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Compute Metrics Basic Gen9 :: CS Threads Dispatched */ +#define cflgt2__compute_basic__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Compute Metrics Basic Gen9 :: SLM Bytes Read */ +#define cflgt2__compute_basic__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Compute Metrics Basic Gen9 :: GTI Read Throughput */ +#define cflgt2__compute_basic__gti_read_throughput__read \ + hsw__render_basic__gti_l3_throughput__read + +/* Compute Metrics Basic Gen9 :: Untyped Writes */ +#define cflgt2__compute_basic__untyped_bytes_written__read \ + bdw__compute_basic__untyped_bytes_written__read + +/* Compute Metrics Basic Gen9 :: GPU Busy */ +#define cflgt2__compute_basic__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Compute Metrics Basic Gen9 :: Rasterized Pixels */ +#define cflgt2__compute_basic__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Compute Metrics Basic Gen9 :: Typed Bytes Read */ +#define cflgt2__compute_basic__typed_bytes_read__read \ + bdw__compute_basic__typed_bytes_read__read + +/* Compute Metrics Basic Gen9 :: DS Threads Dispatched */ +#define cflgt2__compute_basic__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Compute Metrics Basic Gen9 :: EU Thread Occupancy */ +#define cflgt2__compute_basic__eu_thread_occupancy__read \ + bdw__compute_basic__eu_thread_occupancy__read + +/* Compute Metrics Basic Gen9 :: EU Stall */ +#define cflgt2__compute_basic__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics Basic Gen9 :: Samples Blended */ +#define cflgt2__compute_basic__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Compute Metrics Basic Gen9 :: Early Depth Test Fails */ +#define cflgt2__compute_basic__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Compute Metrics Basic Gen9 :: Shader Memory Accesses */ +#define cflgt2__compute_basic__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Compute Metrics Basic Gen9 :: HS Threads Dispatched */ +#define cflgt2__compute_basic__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Compute Metrics Basic Gen9 :: GTI Write Throughput */ +#define cflgt2__compute_basic__gti_write_throughput__read \ + bdw__render_basic__gti_hdc_lookups_throughput__read + +/* Compute Metrics Basic Gen9 :: SLM Bytes Written */ +#define cflgt2__compute_basic__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Compute Metrics Basic Gen9 :: L3 Shader Throughput */ +#define cflgt2__compute_basic__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Compute Metrics Basic Gen9 :: Samples Killed in FS */ +#define cflgt2__compute_basic__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Compute Metrics Basic Gen9 :: Samples Written */ +#define cflgt2__compute_basic__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Compute Metrics Basic Gen9 :: Shader Atomic Memory Accesses */ +#define cflgt2__compute_basic__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Basic Gen9 :: EU Send Pipe Active */ +#define cflgt2__compute_basic__eu_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Core Clocks */ +#define cflgt2__render_pipe_profile__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: EU Active */ +#define cflgt2__render_pipe_profile__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: VS Bottleneck */ +#define cflgt2__render_pipe_profile__vs_bottleneck__read \ + bdw__render_basic__sampler0_busy__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Hi-Depth Bottleneck */ +#define cflgt2__render_pipe_profile__hi_depth_bottleneck__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GS Bottleneck */ +#define cflgt2__render_pipe_profile__gs_bottleneck__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GS Threads Dispatched */ +#define cflgt2__render_pipe_profile__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Early Hi-Depth Test Fails */ +#define cflgt2__render_pipe_profile__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: VS Threads Dispatched */ +#define cflgt2__render_pipe_profile__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: FS Threads Dispatched */ +#define cflgt2__render_pipe_profile__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: BC Bottleneck */ +#define cflgt2__render_pipe_profile__bc_bottleneck__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: HS Stall */ +#define cflgt2__render_pipe_profile__hs_stall__read \ + bdw__render_pipe_profile__hs_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Barrier Messages */ +#define cflgt2__render_pipe_profile__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Sampler Texels */ +#define cflgt2__render_pipe_profile__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Pixels Failing Tests */ +#define cflgt2__render_pipe_profile__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Time Elapsed */ +#define cflgt2__render_pipe_profile__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: AVG GPU Core Frequency */ +#define cflgt2__render_pipe_profile__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: AVG GPU Core Frequency */ +#define cflgt2__render_pipe_profile__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Sampler Texels Misses */ +#define cflgt2__render_pipe_profile__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: CS Threads Dispatched */ +#define cflgt2__render_pipe_profile__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: VF Bottleneck */ +#define cflgt2__render_pipe_profile__vf_bottleneck__read \ + bdw__render_pipe_profile__vf_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SLM Bytes Read */ +#define cflgt2__render_pipe_profile__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Strip-Fans Bottleneck */ +#define cflgt2__render_pipe_profile__sf_bottleneck__read \ + bdw__render_pipe_profile__sf_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SF Stall */ +#define cflgt2__render_pipe_profile__sf_stall__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Busy */ +#define cflgt2__render_pipe_profile__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: HS Bottleneck */ +#define cflgt2__render_pipe_profile__hs_bottleneck__read \ + bdw__render_basic__sampler1_busy__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: CL Stall */ +#define cflgt2__render_pipe_profile__cl_stall__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SO Bottleneck */ +#define cflgt2__render_pipe_profile__so_bottleneck__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Rasterized Pixels */ +#define cflgt2__render_pipe_profile__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: DS Threads Dispatched */ +#define cflgt2__render_pipe_profile__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Written */ +#define cflgt2__render_pipe_profile__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: DS Bottleneck */ +#define cflgt2__render_pipe_profile__ds_bottleneck__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: EU Stall */ +#define cflgt2__render_pipe_profile__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Clipper Bottleneck */ +#define cflgt2__render_pipe_profile__cl_bottleneck__read \ + bdw__render_pipe_profile__cl_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: DS Stall */ +#define cflgt2__render_pipe_profile__ds_stall__read \ + bdw__render_pipe_profile__ds_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Early Depth Bottleneck */ +#define cflgt2__render_pipe_profile__early_depth_bottleneck__read \ + bdw__render_pipe_profile__early_depth_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Blended */ +#define cflgt2__render_pipe_profile__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Early Depth Test Fails */ +#define cflgt2__render_pipe_profile__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Memory Accesses */ +#define cflgt2__render_pipe_profile__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: HS Threads Dispatched */ +#define cflgt2__render_pipe_profile__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SLM Bytes Written */ +#define cflgt2__render_pipe_profile__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: L3 Shader Throughput */ +#define cflgt2__render_pipe_profile__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Killed in FS */ +#define cflgt2__render_pipe_profile__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SO Stall */ +#define cflgt2__render_pipe_profile__so_stall__read \ + bdw__render_pipe_profile__so_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Atomic Memory Accesses */ +#define cflgt2__render_pipe_profile__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Memory Reads Distribution Gen9 :: GPU Core Clocks */ +#define cflgt2__memory_reads__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Memory Reads Distribution Gen9 :: EU Active */ +#define cflgt2__memory_reads__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Memory Reads Distribution Gen9 :: GtiL3Bank0Reads */ +#define cflgt2__memory_reads__gti_l3_bank0_reads__read \ + hsw__compute_extended__typed_atomics0__read + +/* Memory Reads Distribution Gen9 :: GS Threads Dispatched */ +#define cflgt2__memory_reads__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Memory Reads Distribution Gen9 :: GtiRingAccesses */ +#define cflgt2__memory_reads__gti_ring_accesses__read \ + bdw__memory_reads__gti_ring_accesses__read + +/* Memory Reads Distribution Gen9 :: Early Hi-Depth Test Fails */ +#define cflgt2__memory_reads__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Memory Reads Distribution Gen9 :: VS Threads Dispatched */ +#define cflgt2__memory_reads__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Memory Reads Distribution Gen9 :: FS Threads Dispatched */ +#define cflgt2__memory_reads__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Memory Reads Distribution Gen9 :: GtiL3Bank3Reads */ +#define cflgt2__memory_reads__gti_l3_bank3_reads__read \ + hsw__memory_reads__gpu_core_clocks__read + +/* Memory Reads Distribution Gen9 :: Shader Barrier Messages */ +#define cflgt2__memory_reads__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Memory Reads Distribution Gen9 :: GtiRsMemoryReads */ +#define cflgt2__memory_reads__gti_rs_memory_reads__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Memory Reads Distribution Gen9 :: Sampler Texels */ +#define cflgt2__memory_reads__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Memory Reads Distribution Gen9 :: Pixels Failing Tests */ +#define cflgt2__memory_reads__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Memory Reads Distribution Gen9 :: GtiHizMemoryReads */ +#define cflgt2__memory_reads__gti_hiz_memory_reads__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* Memory Reads Distribution Gen9 :: GPU Time Elapsed */ +#define cflgt2__memory_reads__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Memory Reads Distribution Gen9 :: AVG GPU Core Frequency */ +#define cflgt2__memory_reads__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Memory Reads Distribution Gen9 :: AVG GPU Core Frequency */ +#define cflgt2__memory_reads__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Memory Reads Distribution Gen9 :: Sampler Texels Misses */ +#define cflgt2__memory_reads__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Memory Reads Distribution Gen9 :: GtiRccMemoryReads */ +#define cflgt2__memory_reads__gti_rcc_memory_reads__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* Memory Reads Distribution Gen9 :: CS Threads Dispatched */ +#define cflgt2__memory_reads__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Memory Reads Distribution Gen9 :: SLM Bytes Read */ +#define cflgt2__memory_reads__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Memory Reads Distribution Gen9 :: GtiL3Bank1Reads */ +#define cflgt2__memory_reads__gti_l3_bank1_reads__read \ + hsw__memory_reads__gti_memory_reads__read + +/* Memory Reads Distribution Gen9 :: GPU Busy */ +#define cflgt2__memory_reads__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Memory Reads Distribution Gen9 :: GtiCmdStreamerMemoryReads */ +#define cflgt2__memory_reads__gti_cmd_streamer_memory_reads__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* Memory Reads Distribution Gen9 :: GtiL3Bank2Reads */ +#define cflgt2__memory_reads__gti_l3_bank2_reads__read \ + hsw__memory_reads__llc_read_accesses__read + +/* Memory Reads Distribution Gen9 :: GtiMemoryReads */ +#define cflgt2__memory_reads__gti_memory_reads__read \ + hsw__compute_extended__typed_writes0__read + +/* Memory Reads Distribution Gen9 :: Rasterized Pixels */ +#define cflgt2__memory_reads__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Memory Reads Distribution Gen9 :: GtiRczMemoryReads */ +#define cflgt2__memory_reads__gti_rcz_memory_reads__read \ + hsw__compute_extended__gpu_clocks__read + +/* Memory Reads Distribution Gen9 :: DS Threads Dispatched */ +#define cflgt2__memory_reads__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Memory Reads Distribution Gen9 :: Samples Written */ +#define cflgt2__memory_reads__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Memory Reads Distribution Gen9 :: EU Stall */ +#define cflgt2__memory_reads__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Memory Reads Distribution Gen9 :: Samples Blended */ +#define cflgt2__memory_reads__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Memory Reads Distribution Gen9 :: Early Depth Test Fails */ +#define cflgt2__memory_reads__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Memory Reads Distribution Gen9 :: GtiMscMemoryReads */ +#define cflgt2__memory_reads__gti_msc_memory_reads__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* Memory Reads Distribution Gen9 :: GtiVfMemoryReads */ +#define cflgt2__memory_reads__gti_vf_memory_reads__read \ + hsw__compute_extended__eu_untyped_writes0__read + +/* Memory Reads Distribution Gen9 :: GtiStcMemoryReads */ +#define cflgt2__memory_reads__gti_stc_memory_reads__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* Memory Reads Distribution Gen9 :: Shader Memory Accesses */ +#define cflgt2__memory_reads__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Memory Reads Distribution Gen9 :: HS Threads Dispatched */ +#define cflgt2__memory_reads__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Memory Reads Distribution Gen9 :: Samples Killed in FS */ +#define cflgt2__memory_reads__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Memory Reads Distribution Gen9 :: SLM Bytes Written */ +#define cflgt2__memory_reads__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Memory Reads Distribution Gen9 :: GtiL3Reads */ +#define cflgt2__memory_reads__gti_l3_reads__read \ + bdw__memory_reads__gti_l3_reads__read + +/* Memory Reads Distribution Gen9 :: Shader Atomic Memory Accesses */ +#define cflgt2__memory_reads__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Memory Writes Distribution Gen9 :: GPU Core Clocks */ +#define cflgt2__memory_writes__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Memory Writes Distribution Gen9 :: EU Active */ +#define cflgt2__memory_writes__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Memory Writes Distribution Gen9 :: GtiMemoryWrites */ +#define cflgt2__memory_writes__gti_memory_writes__read \ + hsw__compute_extended__typed_writes0__read + +/* Memory Writes Distribution Gen9 :: GS Threads Dispatched */ +#define cflgt2__memory_writes__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Memory Writes Distribution Gen9 :: GtiRingAccesses */ +#define cflgt2__memory_writes__gti_ring_accesses__read \ + bdw__memory_reads__gti_ring_accesses__read + +/* Memory Writes Distribution Gen9 :: Early Hi-Depth Test Fails */ +#define cflgt2__memory_writes__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Memory Writes Distribution Gen9 :: VS Threads Dispatched */ +#define cflgt2__memory_writes__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Memory Writes Distribution Gen9 :: FS Threads Dispatched */ +#define cflgt2__memory_writes__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Memory Writes Distribution Gen9 :: GtiMscMemoryWrites */ +#define cflgt2__memory_writes__gti_msc_memory_writes__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* Memory Writes Distribution Gen9 :: Shader Barrier Messages */ +#define cflgt2__memory_writes__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Memory Writes Distribution Gen9 :: GtiCmdStreamerMemoryWrites */ +#define cflgt2__memory_writes__gti_cmd_streamer_memory_writes__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* Memory Writes Distribution Gen9 :: Sampler Texels */ +#define cflgt2__memory_writes__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Memory Writes Distribution Gen9 :: Pixels Failing Tests */ +#define cflgt2__memory_writes__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Memory Writes Distribution Gen9 :: GtiL3Bank0Writes */ +#define cflgt2__memory_writes__gti_l3_bank0_writes__read \ + hsw__compute_extended__typed_atomics0__read + +/* Memory Writes Distribution Gen9 :: GtiL3Bank1Writes */ +#define cflgt2__memory_writes__gti_l3_bank1_writes__read \ + hsw__memory_reads__gti_memory_reads__read + +/* Memory Writes Distribution Gen9 :: GtiL3Bank2Writes */ +#define cflgt2__memory_writes__gti_l3_bank2_writes__read \ + hsw__memory_reads__llc_read_accesses__read + +/* Memory Writes Distribution Gen9 :: GtiL3Bank3Writes */ +#define cflgt2__memory_writes__gti_l3_bank3_writes__read \ + hsw__memory_reads__gpu_core_clocks__read + +/* Memory Writes Distribution Gen9 :: GtiL3Writes */ +#define cflgt2__memory_writes__gti_l3_writes__read \ + bdw__memory_reads__gti_l3_reads__read + +/* Memory Writes Distribution Gen9 :: GPU Time Elapsed */ +#define cflgt2__memory_writes__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Memory Writes Distribution Gen9 :: AVG GPU Core Frequency */ +#define cflgt2__memory_writes__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Memory Writes Distribution Gen9 :: AVG GPU Core Frequency */ +#define cflgt2__memory_writes__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Memory Writes Distribution Gen9 :: Sampler Texels Misses */ +#define cflgt2__memory_writes__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Memory Writes Distribution Gen9 :: CS Threads Dispatched */ +#define cflgt2__memory_writes__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Memory Writes Distribution Gen9 :: SLM Bytes Read */ +#define cflgt2__memory_writes__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Memory Writes Distribution Gen9 :: GtiRccMemoryWrites */ +#define cflgt2__memory_writes__gti_rcc_memory_writes__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* Memory Writes Distribution Gen9 :: GtiSoMemoryWrites */ +#define cflgt2__memory_writes__gti_so_memory_writes__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Memory Writes Distribution Gen9 :: GPU Busy */ +#define cflgt2__memory_writes__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Memory Writes Distribution Gen9 :: GtiStcMemoryWrites */ +#define cflgt2__memory_writes__gti_stc_memory_writes__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* Memory Writes Distribution Gen9 :: Rasterized Pixels */ +#define cflgt2__memory_writes__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Memory Writes Distribution Gen9 :: DS Threads Dispatched */ +#define cflgt2__memory_writes__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Memory Writes Distribution Gen9 :: Samples Written */ +#define cflgt2__memory_writes__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Memory Writes Distribution Gen9 :: EU Stall */ +#define cflgt2__memory_writes__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Memory Writes Distribution Gen9 :: Samples Blended */ +#define cflgt2__memory_writes__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Memory Writes Distribution Gen9 :: Early Depth Test Fails */ +#define cflgt2__memory_writes__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Memory Writes Distribution Gen9 :: Shader Memory Accesses */ +#define cflgt2__memory_writes__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Memory Writes Distribution Gen9 :: HS Threads Dispatched */ +#define cflgt2__memory_writes__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Memory Writes Distribution Gen9 :: GtiRczMemoryWrites */ +#define cflgt2__memory_writes__gti_rcz_memory_writes__read \ + hsw__compute_extended__gpu_clocks__read + +/* Memory Writes Distribution Gen9 :: SLM Bytes Written */ +#define cflgt2__memory_writes__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Memory Writes Distribution Gen9 :: L3 Shader Throughput */ +#define cflgt2__memory_writes__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Memory Writes Distribution Gen9 :: Samples Killed in FS */ +#define cflgt2__memory_writes__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Memory Writes Distribution Gen9 :: GtiHizMemoryWrites */ +#define cflgt2__memory_writes__gti_hiz_memory_writes__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* Memory Writes Distribution Gen9 :: Shader Atomic Memory Accesses */ +#define cflgt2__memory_writes__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Extended Gen9 :: GPU Core Clocks */ +#define cflgt2__compute_extended__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Extended Gen9 :: EU Active */ +#define cflgt2__compute_extended__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Compute Metrics Extended Gen9 :: EU Both FPU Pipes Active */ +#define cflgt2__compute_extended__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Compute Metrics Extended Gen9 :: EU FPU0 Pipe Active */ +#define cflgt2__compute_extended__fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Compute Metrics Extended Gen9 :: EU FPU1 Pipe Active */ +#define cflgt2__compute_extended__fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Compute Metrics Extended Gen9 :: EU AVG IPC Rate */ +#define cflgt2__compute_extended__eu_avg_ipc_rate__read \ + bdw__compute_basic__eu_avg_ipc_rate__read + +/* Compute Metrics Extended Gen9 :: Typed Writes 0 */ +#define cflgt2__compute_extended__typed_writes0__read \ + hsw__compute_extended__typed_writes0__read + +/* Compute Metrics Extended Gen9 :: EuTypedAtomics0 */ +#define cflgt2__compute_extended__eu_typed_atomics0__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* Compute Metrics Extended Gen9 :: Typed Atomics 0 */ +#define cflgt2__compute_extended__typed_atomics0__read \ + hsw__compute_extended__typed_atomics0__read + +/* Compute Metrics Extended Gen9 :: TypedAtomicsPerCacheLine */ +#define cflgt2__compute_extended__typed_atomics_per_cache_line__read \ + hsw__compute_extended__typed_atomics_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: EuUntypedReads0 */ +#define cflgt2__compute_extended__eu_untyped_reads0__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* Compute Metrics Extended Gen9 :: Untyped Writes 0 */ +#define cflgt2__compute_extended__untyped_writes0__read \ + hsw__compute_extended__untyped_writes0__read + +/* Compute Metrics Extended Gen9 :: EuUntypedAtomics0 */ +#define cflgt2__compute_extended__eu_untyped_atomics0__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* Compute Metrics Extended Gen9 :: EuUntypedWrites0 */ +#define cflgt2__compute_extended__eu_untyped_writes0__read \ + hsw__compute_extended__eu_untyped_writes0__read + +/* Compute Metrics Extended Gen9 :: EuA64UntypedWrites0 */ +#define cflgt2__compute_extended__eu_a64_untyped_writes0__read \ + hsw__compute_extended__gpu_clocks__read + +/* Compute Metrics Extended Gen9 :: UntypedWritesPerCacheLine */ +#define cflgt2__compute_extended__untyped_writes_per_cache_line__read \ + bdw__compute_extended__untyped_writes_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: Shader Barrier Messages */ +#define cflgt2__compute_extended__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Compute Metrics Extended Gen9 :: Sampler Texels */ +#define cflgt2__compute_extended__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Compute Metrics Extended Gen9 :: GPU Time Elapsed */ +#define cflgt2__compute_extended__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics Extended Gen9 :: AVG GPU Core Frequency */ +#define cflgt2__compute_extended__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics Extended Gen9 :: AVG GPU Core Frequency */ +#define cflgt2__compute_extended__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics Extended Gen9 :: Sampler Texels Misses */ +#define cflgt2__compute_extended__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Compute Metrics Extended Gen9 :: CS Threads Dispatched */ +#define cflgt2__compute_extended__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Compute Metrics Extended Gen9 :: SLM Bytes Read */ +#define cflgt2__compute_extended__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Compute Metrics Extended Gen9 :: EuTypedWrites0 */ +#define cflgt2__compute_extended__eu_typed_writes0__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* Compute Metrics Extended Gen9 :: TypedWritesPerCacheLine */ +#define cflgt2__compute_extended__typed_writes_per_cache_line__read \ + hsw__compute_extended__typed_writes_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: Typed Reads 0 */ +#define cflgt2__compute_extended__typed_reads0__read \ + hsw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Extended Gen9 :: Untyped Reads 0 */ +#define cflgt2__compute_extended__untyped_reads0__read \ + hsw__compute_extended__untyped_reads0__read + +/* Compute Metrics Extended Gen9 :: EuA64UntypedReads0 */ +#define cflgt2__compute_extended__eu_a64_untyped_reads0__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* Compute Metrics Extended Gen9 :: EU Thread Occupancy */ +#define cflgt2__compute_extended__eu_thread_occupancy__read \ + bdw__compute_basic__eu_thread_occupancy__read + +/* Compute Metrics Extended Gen9 :: EU Stall */ +#define cflgt2__compute_extended__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics Extended Gen9 :: EuTypedReads0 */ +#define cflgt2__compute_extended__eu_typed_reads0__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Compute Metrics Extended Gen9 :: UntypedReadsPerCacheLine */ +#define cflgt2__compute_extended__untyped_reads_per_cache_line__read \ + bdw__compute_extended__untyped_reads_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: Shader Memory Accesses */ +#define cflgt2__compute_extended__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Compute Metrics Extended Gen9 :: TypedReadsPerCacheLine */ +#define cflgt2__compute_extended__typed_reads_per_cache_line__read \ + hsw__compute_extended__typed_reads_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: SLM Bytes Written */ +#define cflgt2__compute_extended__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Compute Metrics Extended Gen9 :: L3 Shader Throughput */ +#define cflgt2__compute_extended__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Compute Metrics Extended Gen9 :: Shader Atomic Memory Accesses */ +#define cflgt2__compute_extended__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Extended Gen9 :: EU Send Pipe Active */ +#define cflgt2__compute_extended__eu_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Compute Metrics L3 Cache Gen9 :: GPU Core Clocks */ +#define cflgt2__compute_l3_cache__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics L3 Cache Gen9 :: EU Active */ +#define cflgt2__compute_l3_cache__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 03 Accesses */ +#define cflgt2__compute_l3_cache__l3_bank03_accesses__read \ + bdw__compute_l3_cache__l3_bank03_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Accesses */ +#define cflgt2__compute_l3_cache__l3_accesses__read \ + sklgt2__compute_l3_cache__l3_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: EU Both FPU Pipes Active */ +#define cflgt2__compute_l3_cache__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Sampler Throughput */ +#define cflgt2__compute_l3_cache__l3_sampler_throughput__read \ + chv__render_basic__l3_sampler_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Pipe Active */ +#define cflgt2__compute_l3_cache__fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Pipe Active */ +#define cflgt2__compute_l3_cache__fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Compute Metrics L3 Cache Gen9 :: EU AVG IPC Rate */ +#define cflgt2__compute_l3_cache__eu_avg_ipc_rate__read \ + bdw__compute_basic__eu_avg_ipc_rate__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Binary Instruction */ +#define cflgt2__compute_l3_cache__eu_binary_fpu0_instruction__read \ + bdw__render_basic__ps_send_active__read + +/* Compute Metrics L3 Cache Gen9 :: GS Threads Dispatched */ +#define cflgt2__compute_l3_cache__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Compute Metrics L3 Cache Gen9 :: Shader Memory Accesses */ +#define cflgt2__compute_l3_cache__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: Early Hi-Depth Test Fails */ +#define cflgt2__compute_l3_cache__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Compute Metrics L3 Cache Gen9 :: VS Threads Dispatched */ +#define cflgt2__compute_l3_cache__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Compute Metrics L3 Cache Gen9 :: FS Threads Dispatched */ +#define cflgt2__compute_l3_cache__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Hybrid Instruction */ +#define cflgt2__compute_l3_cache__eu_hybrid_fpu0_instruction__read \ + bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Misses */ +#define cflgt2__compute_l3_cache__l3_misses__read \ + bdw__compute_l3_cache__l3_misses__read + +/* Compute Metrics L3 Cache Gen9 :: Shader Barrier Messages */ +#define cflgt2__compute_l3_cache__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 Accesses */ +#define cflgt2__compute_l3_cache__l3_bank00_accesses__read \ + bdw__compute_l3_cache__l3_bank00_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Move Instruction */ +#define cflgt2__compute_l3_cache__eu_move_fpu0_instruction__read \ + bdw__compute_l3_cache__eu_move_fpu0_instruction__read + +/* Compute Metrics L3 Cache Gen9 :: Sampler Texels */ +#define cflgt2__compute_l3_cache__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Compute Metrics L3 Cache Gen9 :: Pixels Failing Tests */ +#define cflgt2__compute_l3_cache__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Hybrid Instruction */ +#define cflgt2__compute_l3_cache__eu_hybrid_fpu1_instruction__read \ + bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read + +/* Compute Metrics L3 Cache Gen9 :: GPU Time Elapsed */ +#define cflgt2__compute_l3_cache__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics L3 Cache Gen9 :: AVG GPU Core Frequency */ +#define cflgt2__compute_l3_cache__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics L3 Cache Gen9 :: AVG GPU Core Frequency */ +#define cflgt2__compute_l3_cache__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics L3 Cache Gen9 :: Sampler Texels Misses */ +#define cflgt2__compute_l3_cache__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Compute Metrics L3 Cache Gen9 :: CS Threads Dispatched */ +#define cflgt2__compute_l3_cache__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Compute Metrics L3 Cache Gen9 :: SLM Bytes Read */ +#define cflgt2__compute_l3_cache__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Compute Metrics L3 Cache Gen9 :: GTI Read Throughput */ +#define cflgt2__compute_l3_cache__gti_read_throughput__read \ + bdw__render_basic__gti_read_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: GTI L3 Throughput */ +#define cflgt2__compute_l3_cache__gti_l3_throughput__read \ + bdw__compute_l3_cache__gti_l3_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 IC Accesses */ +#define cflgt2__compute_l3_cache__l3_bank00_ic_accesses__read \ + bdw__compute_l3_cache__l3_bank00_ic_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 IC Hits */ +#define cflgt2__compute_l3_cache__l3_bank00_ic_hits__read \ + bdw__compute_l3_cache__l3_bank00_ic_hits__read + +/* Compute Metrics L3 Cache Gen9 :: Sampler Accesses */ +#define cflgt2__compute_l3_cache__sampler_accesses__read \ + bdw__render_pipe_profile__sampler_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 01 Accesses */ +#define cflgt2__compute_l3_cache__l3_bank01_accesses__read \ + bdw__compute_l3_cache__l3_bank01_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: GPU Busy */ +#define cflgt2__compute_l3_cache__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Ternary Instruction */ +#define cflgt2__compute_l3_cache__eu_ternary_fpu0_instruction__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Compute Metrics L3 Cache Gen9 :: Shader Atomic Memory Accesses */ +#define cflgt2__compute_l3_cache__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics L3 Cache Gen9 :: Rasterized Pixels */ +#define cflgt2__compute_l3_cache__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Compute Metrics L3 Cache Gen9 :: DS Threads Dispatched */ +#define cflgt2__compute_l3_cache__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Compute Metrics L3 Cache Gen9 :: Samples Written */ +#define cflgt2__compute_l3_cache__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Move Instruction */ +#define cflgt2__compute_l3_cache__eu_move_fpu1_instruction__read \ + bdw__compute_l3_cache__eu_move_fpu1_instruction__read + +/* Compute Metrics L3 Cache Gen9 :: EU Stall */ +#define cflgt2__compute_l3_cache__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics L3 Cache Gen9 :: Samples Blended */ +#define cflgt2__compute_l3_cache__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Compute Metrics L3 Cache Gen9 :: Early Depth Test Fails */ +#define cflgt2__compute_l3_cache__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 02 Accesses */ +#define cflgt2__compute_l3_cache__l3_bank02_accesses__read \ + bdw__compute_l3_cache__l3_bank02_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: HS Threads Dispatched */ +#define cflgt2__compute_l3_cache__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Total Throughput */ +#define cflgt2__compute_l3_cache__l3_total_throughput__read \ + sklgt2__compute_l3_cache__l3_total_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: GTI Write Throughput */ +#define cflgt2__compute_l3_cache__gti_write_throughput__read \ + hsw__render_basic__gti_write_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: SLM Bytes Written */ +#define cflgt2__compute_l3_cache__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Shader Throughput */ +#define cflgt2__compute_l3_cache__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: Samples Killed in FS */ +#define cflgt2__compute_l3_cache__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Binary Instruction */ +#define cflgt2__compute_l3_cache__eu_binary_fpu1_instruction__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Ternary Instruction */ +#define cflgt2__compute_l3_cache__eu_ternary_fpu1_instruction__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Compute Metrics L3 Cache Gen9 :: EU Send Pipe Active */ +#define cflgt2__compute_l3_cache__eu_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set HDCAndSF :: GPU Core Clocks */ +#define cflgt2__hdc_and_sf__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set HDCAndSF :: EU Active */ +#define cflgt2__hdc_and_sf__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set HDCAndSF :: EU Both FPU Pipes Active */ +#define cflgt2__hdc_and_sf__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set HDCAndSF :: VS Send Pipe Active */ +#define cflgt2__hdc_and_sf__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set HDCAndSF :: VS FPU1 Pipe Active */ +#define cflgt2__hdc_and_sf__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set HDCAndSF :: GS Threads Dispatched */ +#define cflgt2__hdc_and_sf__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set HDCAndSF :: Early Hi-Depth Test Fails */ +#define cflgt2__hdc_and_sf__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set HDCAndSF :: FS Both FPU Active */ +#define cflgt2__hdc_and_sf__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set HDCAndSF :: VS Threads Dispatched */ +#define cflgt2__hdc_and_sf__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set HDCAndSF :: Polygon Data Ready */ +#define cflgt2__hdc_and_sf__poly_data_ready__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set HDCAndSF :: FS Threads Dispatched */ +#define cflgt2__hdc_and_sf__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set HDCAndSF :: Shader Barrier Messages */ +#define cflgt2__hdc_and_sf__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set HDCAndSF :: Sampler Texels */ +#define cflgt2__hdc_and_sf__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set HDCAndSF :: Pixels Failing Tests */ +#define cflgt2__hdc_and_sf__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set HDCAndSF :: GPU Time Elapsed */ +#define cflgt2__hdc_and_sf__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set HDCAndSF :: AVG GPU Core Frequency */ +#define cflgt2__hdc_and_sf__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set HDCAndSF :: AVG GPU Core Frequency */ +#define cflgt2__hdc_and_sf__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set HDCAndSF :: Sampler Texels Misses */ +#define cflgt2__hdc_and_sf__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */ +#define cflgt2__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read \ + bdw__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read + +/* Metric set HDCAndSF :: CS Threads Dispatched */ +#define cflgt2__hdc_and_sf__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss2) */ +#define cflgt2__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read \ + bdw__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read + +/* Metric set HDCAndSF :: SLM Bytes Read */ +#define cflgt2__hdc_and_sf__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set HDCAndSF :: PS FPU1 Pipe Active */ +#define cflgt2__hdc_and_sf__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set HDCAndSF :: PS Send Pipeline Active */ +#define cflgt2__hdc_and_sf__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set HDCAndSF :: VS FPU0 Pipe Active */ +#define cflgt2__hdc_and_sf__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set HDCAndSF :: GPU Busy */ +#define cflgt2__hdc_and_sf__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set HDCAndSF :: Rasterized Pixels */ +#define cflgt2__hdc_and_sf__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set HDCAndSF :: PS FPU0 Pipe Active */ +#define cflgt2__hdc_and_sf__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set HDCAndSF :: DS Threads Dispatched */ +#define cflgt2__hdc_and_sf__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set HDCAndSF :: Samples Written */ +#define cflgt2__hdc_and_sf__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set HDCAndSF :: EU Stall */ +#define cflgt2__hdc_and_sf__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set HDCAndSF :: Samples Blended */ +#define cflgt2__hdc_and_sf__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set HDCAndSF :: Early Depth Test Fails */ +#define cflgt2__hdc_and_sf__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set HDCAndSF :: Shader Memory Accesses */ +#define cflgt2__hdc_and_sf__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set HDCAndSF :: HS Threads Dispatched */ +#define cflgt2__hdc_and_sf__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set HDCAndSF :: SLM Bytes Written */ +#define cflgt2__hdc_and_sf__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set HDCAndSF :: L3 Shader Throughput */ +#define cflgt2__hdc_and_sf__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set HDCAndSF :: Samples Killed in FS */ +#define cflgt2__hdc_and_sf__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */ +#define cflgt2__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read \ + bdw__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read + +/* Metric set HDCAndSF :: Shader Atomic Memory Accesses */ +#define cflgt2__hdc_and_sf__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set L3_1 :: GPU Core Clocks */ +#define cflgt2__l3_1__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set L3_1 :: EU Active */ +#define cflgt2__l3_1__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set L3_1 :: Slice0 L3 Bank1 Active */ +#define cflgt2__l3_1__l30_bank1_active__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set L3_1 :: EU Both FPU Pipes Active */ +#define cflgt2__l3_1__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set L3_1 :: VS Send Pipe Active */ +#define cflgt2__l3_1__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set L3_1 :: VS FPU1 Pipe Active */ +#define cflgt2__l3_1__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set L3_1 :: GS Threads Dispatched */ +#define cflgt2__l3_1__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set L3_1 :: Early Hi-Depth Test Fails */ +#define cflgt2__l3_1__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set L3_1 :: FS Both FPU Active */ +#define cflgt2__l3_1__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set L3_1 :: VS Threads Dispatched */ +#define cflgt2__l3_1__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set L3_1 :: Slice0 L3 Bank1 Stalled */ +#define cflgt2__l3_1__l30_bank1_stalled__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Metric set L3_1 :: FS Threads Dispatched */ +#define cflgt2__l3_1__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set L3_1 :: Shader Barrier Messages */ +#define cflgt2__l3_1__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set L3_1 :: Sampler Texels */ +#define cflgt2__l3_1__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set L3_1 :: Pixels Failing Tests */ +#define cflgt2__l3_1__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set L3_1 :: GPU Time Elapsed */ +#define cflgt2__l3_1__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set L3_1 :: AVG GPU Core Frequency */ +#define cflgt2__l3_1__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set L3_1 :: AVG GPU Core Frequency */ +#define cflgt2__l3_1__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set L3_1 :: Sampler Texels Misses */ +#define cflgt2__l3_1__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set L3_1 :: CS Threads Dispatched */ +#define cflgt2__l3_1__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set L3_1 :: SLM Bytes Read */ +#define cflgt2__l3_1__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set L3_1 :: PS FPU1 Pipe Active */ +#define cflgt2__l3_1__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set L3_1 :: PS Send Pipeline Active */ +#define cflgt2__l3_1__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set L3_1 :: VS FPU0 Pipe Active */ +#define cflgt2__l3_1__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set L3_1 :: GPU Busy */ +#define cflgt2__l3_1__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set L3_1 :: Slice0 L3 Bank0 Active */ +#define cflgt2__l3_1__l30_bank0_active__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set L3_1 :: Rasterized Pixels */ +#define cflgt2__l3_1__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set L3_1 :: PS FPU0 Pipe Active */ +#define cflgt2__l3_1__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set L3_1 :: Slice0 L3 Bank0 Stalled */ +#define cflgt2__l3_1__l30_bank0_stalled__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set L3_1 :: DS Threads Dispatched */ +#define cflgt2__l3_1__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set L3_1 :: Samples Written */ +#define cflgt2__l3_1__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set L3_1 :: EU Stall */ +#define cflgt2__l3_1__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set L3_1 :: Samples Blended */ +#define cflgt2__l3_1__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set L3_1 :: Early Depth Test Fails */ +#define cflgt2__l3_1__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set L3_1 :: Shader Memory Accesses */ +#define cflgt2__l3_1__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set L3_1 :: HS Threads Dispatched */ +#define cflgt2__l3_1__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set L3_1 :: SLM Bytes Written */ +#define cflgt2__l3_1__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set L3_1 :: L3 Shader Throughput */ +#define cflgt2__l3_1__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set L3_1 :: Samples Killed in FS */ +#define cflgt2__l3_1__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set L3_1 :: Shader Atomic Memory Accesses */ +#define cflgt2__l3_1__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set L3_2 :: GPU Core Clocks */ +#define cflgt2__l3_2__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set L3_2 :: EU Active */ +#define cflgt2__l3_2__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set L3_2 :: EU Both FPU Pipes Active */ +#define cflgt2__l3_2__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set L3_2 :: VS Send Pipe Active */ +#define cflgt2__l3_2__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set L3_2 :: VS FPU1 Pipe Active */ +#define cflgt2__l3_2__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set L3_2 :: GS Threads Dispatched */ +#define cflgt2__l3_2__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set L3_2 :: Early Hi-Depth Test Fails */ +#define cflgt2__l3_2__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set L3_2 :: FS Both FPU Active */ +#define cflgt2__l3_2__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set L3_2 :: VS Threads Dispatched */ +#define cflgt2__l3_2__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set L3_2 :: FS Threads Dispatched */ +#define cflgt2__l3_2__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set L3_2 :: Shader Barrier Messages */ +#define cflgt2__l3_2__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set L3_2 :: Sampler Texels */ +#define cflgt2__l3_2__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set L3_2 :: Pixels Failing Tests */ +#define cflgt2__l3_2__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set L3_2 :: GPU Time Elapsed */ +#define cflgt2__l3_2__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set L3_2 :: AVG GPU Core Frequency */ +#define cflgt2__l3_2__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set L3_2 :: AVG GPU Core Frequency */ +#define cflgt2__l3_2__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set L3_2 :: Sampler Texels Misses */ +#define cflgt2__l3_2__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set L3_2 :: CS Threads Dispatched */ +#define cflgt2__l3_2__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set L3_2 :: SLM Bytes Read */ +#define cflgt2__l3_2__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set L3_2 :: PS FPU1 Pipe Active */ +#define cflgt2__l3_2__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set L3_2 :: Slice0 L3 Bank2 Stalled */ +#define cflgt2__l3_2__l30_bank2_stalled__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set L3_2 :: PS Send Pipeline Active */ +#define cflgt2__l3_2__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set L3_2 :: VS FPU0 Pipe Active */ +#define cflgt2__l3_2__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set L3_2 :: GPU Busy */ +#define cflgt2__l3_2__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set L3_2 :: Slice0 L3 Bank2 Active */ +#define cflgt2__l3_2__l30_bank2_active__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set L3_2 :: Rasterized Pixels */ +#define cflgt2__l3_2__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set L3_2 :: PS FPU0 Pipe Active */ +#define cflgt2__l3_2__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set L3_2 :: DS Threads Dispatched */ +#define cflgt2__l3_2__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set L3_2 :: Samples Written */ +#define cflgt2__l3_2__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set L3_2 :: EU Stall */ +#define cflgt2__l3_2__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set L3_2 :: Samples Blended */ +#define cflgt2__l3_2__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set L3_2 :: Early Depth Test Fails */ +#define cflgt2__l3_2__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set L3_2 :: Shader Memory Accesses */ +#define cflgt2__l3_2__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set L3_2 :: HS Threads Dispatched */ +#define cflgt2__l3_2__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set L3_2 :: SLM Bytes Written */ +#define cflgt2__l3_2__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set L3_2 :: L3 Shader Throughput */ +#define cflgt2__l3_2__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set L3_2 :: Samples Killed in FS */ +#define cflgt2__l3_2__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set L3_2 :: Shader Atomic Memory Accesses */ +#define cflgt2__l3_2__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set L3_3 :: GPU Core Clocks */ +#define cflgt2__l3_3__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set L3_3 :: EU Active */ +#define cflgt2__l3_3__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set L3_3 :: EU Both FPU Pipes Active */ +#define cflgt2__l3_3__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set L3_3 :: VS Send Pipe Active */ +#define cflgt2__l3_3__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set L3_3 :: VS FPU1 Pipe Active */ +#define cflgt2__l3_3__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set L3_3 :: GS Threads Dispatched */ +#define cflgt2__l3_3__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set L3_3 :: Early Hi-Depth Test Fails */ +#define cflgt2__l3_3__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set L3_3 :: FS Both FPU Active */ +#define cflgt2__l3_3__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set L3_3 :: VS Threads Dispatched */ +#define cflgt2__l3_3__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set L3_3 :: FS Threads Dispatched */ +#define cflgt2__l3_3__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set L3_3 :: Slice0 L3 Bank3 Stalled */ +#define cflgt2__l3_3__l30_bank3_stalled__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set L3_3 :: Shader Barrier Messages */ +#define cflgt2__l3_3__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set L3_3 :: Sampler Texels */ +#define cflgt2__l3_3__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set L3_3 :: Pixels Failing Tests */ +#define cflgt2__l3_3__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set L3_3 :: GPU Time Elapsed */ +#define cflgt2__l3_3__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set L3_3 :: AVG GPU Core Frequency */ +#define cflgt2__l3_3__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set L3_3 :: AVG GPU Core Frequency */ +#define cflgt2__l3_3__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set L3_3 :: Sampler Texels Misses */ +#define cflgt2__l3_3__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set L3_3 :: CS Threads Dispatched */ +#define cflgt2__l3_3__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set L3_3 :: SLM Bytes Read */ +#define cflgt2__l3_3__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set L3_3 :: PS FPU1 Pipe Active */ +#define cflgt2__l3_3__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set L3_3 :: Slice0 L3 Bank3 Active */ +#define cflgt2__l3_3__l30_bank3_active__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set L3_3 :: PS Send Pipeline Active */ +#define cflgt2__l3_3__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set L3_3 :: VS FPU0 Pipe Active */ +#define cflgt2__l3_3__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set L3_3 :: GPU Busy */ +#define cflgt2__l3_3__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set L3_3 :: Rasterized Pixels */ +#define cflgt2__l3_3__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set L3_3 :: PS FPU0 Pipe Active */ +#define cflgt2__l3_3__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set L3_3 :: DS Threads Dispatched */ +#define cflgt2__l3_3__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set L3_3 :: Samples Written */ +#define cflgt2__l3_3__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set L3_3 :: EU Stall */ +#define cflgt2__l3_3__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set L3_3 :: Samples Blended */ +#define cflgt2__l3_3__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set L3_3 :: Early Depth Test Fails */ +#define cflgt2__l3_3__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set L3_3 :: Shader Memory Accesses */ +#define cflgt2__l3_3__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set L3_3 :: HS Threads Dispatched */ +#define cflgt2__l3_3__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set L3_3 :: SLM Bytes Written */ +#define cflgt2__l3_3__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set L3_3 :: L3 Shader Throughput */ +#define cflgt2__l3_3__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set L3_3 :: Samples Killed in FS */ +#define cflgt2__l3_3__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set L3_3 :: Shader Atomic Memory Accesses */ +#define cflgt2__l3_3__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */ +#define cflgt2__rasterizer_and_pixel_backend__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set RasterizerAndPixelBackend :: EU Active */ +#define cflgt2__rasterizer_and_pixel_backend__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set RasterizerAndPixelBackend :: EU Both FPU Pipes Active */ +#define cflgt2__rasterizer_and_pixel_backend__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set RasterizerAndPixelBackend :: VS Send Pipe Active */ +#define cflgt2__rasterizer_and_pixel_backend__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set RasterizerAndPixelBackend :: VS FPU1 Pipe Active */ +#define cflgt2__rasterizer_and_pixel_backend__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */ +#define cflgt2__rasterizer_and_pixel_backend__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */ +#define cflgt2__rasterizer_and_pixel_backend__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set RasterizerAndPixelBackend :: FS Both FPU Active */ +#define cflgt2__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */ +#define cflgt2__rasterizer_and_pixel_backend__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */ +#define cflgt2__rasterizer_and_pixel_backend__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Pixel Values Ready */ +#define cflgt2__rasterizer_and_pixel_backend__pixel_values0_ready__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */ +#define cflgt2__rasterizer_and_pixel_backend__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set RasterizerAndPixelBackend :: Sampler Texels */ +#define cflgt2__rasterizer_and_pixel_backend__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */ +#define cflgt2__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */ +#define cflgt2__rasterizer_and_pixel_backend__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ +#define cflgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ +#define cflgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */ +#define cflgt2__rasterizer_and_pixel_backend__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */ +#define cflgt2__rasterizer_and_pixel_backend__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */ +#define cflgt2__rasterizer_and_pixel_backend__rasterizer0_input_available__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Post-EarlyZ Pixel Data Ready */ +#define cflgt2__rasterizer_and_pixel_backend__pixel_data0_ready__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */ +#define cflgt2__rasterizer_and_pixel_backend__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set RasterizerAndPixelBackend :: PS FPU1 Pipe Active */ +#define cflgt2__rasterizer_and_pixel_backend__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set RasterizerAndPixelBackend :: PS Send Pipeline Active */ +#define cflgt2__rasterizer_and_pixel_backend__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set RasterizerAndPixelBackend :: VS FPU0 Pipe Active */ +#define cflgt2__rasterizer_and_pixel_backend__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set RasterizerAndPixelBackend :: GPU Busy */ +#define cflgt2__rasterizer_and_pixel_backend__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */ +#define cflgt2__rasterizer_and_pixel_backend__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set RasterizerAndPixelBackend :: PS FPU0 Pipe Active */ +#define cflgt2__rasterizer_and_pixel_backend__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */ +#define cflgt2__rasterizer_and_pixel_backend__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set RasterizerAndPixelBackend :: Samples Written */ +#define cflgt2__rasterizer_and_pixel_backend__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set RasterizerAndPixelBackend :: EU Stall */ +#define cflgt2__rasterizer_and_pixel_backend__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */ +#define cflgt2__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set RasterizerAndPixelBackend :: Samples Blended */ +#define cflgt2__rasterizer_and_pixel_backend__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */ +#define cflgt2__rasterizer_and_pixel_backend__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */ +#define cflgt2__rasterizer_and_pixel_backend__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */ +#define cflgt2__rasterizer_and_pixel_backend__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */ +#define cflgt2__rasterizer_and_pixel_backend__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */ +#define cflgt2__rasterizer_and_pixel_backend__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */ +#define cflgt2__rasterizer_and_pixel_backend__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 PS Output Available */ +#define cflgt2__rasterizer_and_pixel_backend__ps_output0_available__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */ +#define cflgt2__rasterizer_and_pixel_backend__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set Sampler :: GPU Core Clocks */ +#define cflgt2__sampler__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set Sampler :: EU Active */ +#define cflgt2__sampler__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set Sampler :: Slice0 Subslice2 Input Available */ +#define cflgt2__sampler__sampler02_input_available__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set Sampler :: EU Both FPU Pipes Active */ +#define cflgt2__sampler__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set Sampler :: VS Send Pipe Active */ +#define cflgt2__sampler__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set Sampler :: Slice0 Subslice0 Input Available */ +#define cflgt2__sampler__sampler00_input_available__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Metric set Sampler :: VS FPU1 Pipe Active */ +#define cflgt2__sampler__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set Sampler :: GS Threads Dispatched */ +#define cflgt2__sampler__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set Sampler :: Early Hi-Depth Test Fails */ +#define cflgt2__sampler__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set Sampler :: FS Both FPU Active */ +#define cflgt2__sampler__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set Sampler :: VS Threads Dispatched */ +#define cflgt2__sampler__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set Sampler :: Slice0 Subslice2 Sampler Output Ready */ +#define cflgt2__sampler__sampler02_output_ready__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set Sampler :: FS Threads Dispatched */ +#define cflgt2__sampler__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set Sampler :: Shader Barrier Messages */ +#define cflgt2__sampler__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set Sampler :: Slice0 Subslice1 Input Available */ +#define cflgt2__sampler__sampler01_input_available__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set Sampler :: Sampler Texels */ +#define cflgt2__sampler__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set Sampler :: Pixels Failing Tests */ +#define cflgt2__sampler__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set Sampler :: GPU Time Elapsed */ +#define cflgt2__sampler__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set Sampler :: AVG GPU Core Frequency */ +#define cflgt2__sampler__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set Sampler :: AVG GPU Core Frequency */ +#define cflgt2__sampler__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set Sampler :: Sampler Texels Misses */ +#define cflgt2__sampler__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set Sampler :: CS Threads Dispatched */ +#define cflgt2__sampler__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set Sampler :: SLM Bytes Read */ +#define cflgt2__sampler__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set Sampler :: PS FPU1 Pipe Active */ +#define cflgt2__sampler__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set Sampler :: PS Send Pipeline Active */ +#define cflgt2__sampler__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set Sampler :: VS FPU0 Pipe Active */ +#define cflgt2__sampler__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set Sampler :: GPU Busy */ +#define cflgt2__sampler__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set Sampler :: Rasterized Pixels */ +#define cflgt2__sampler__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set Sampler :: PS FPU0 Pipe Active */ +#define cflgt2__sampler__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set Sampler :: DS Threads Dispatched */ +#define cflgt2__sampler__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set Sampler :: Samples Written */ +#define cflgt2__sampler__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set Sampler :: EU Stall */ +#define cflgt2__sampler__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set Sampler :: Samples Blended */ +#define cflgt2__sampler__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set Sampler :: Early Depth Test Fails */ +#define cflgt2__sampler__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set Sampler :: Slice0 Subslice0 Sampler Output Ready */ +#define cflgt2__sampler__sampler00_output_ready__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set Sampler :: Slice0 Subslice1 Sampler Output Ready */ +#define cflgt2__sampler__sampler01_output_ready__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set Sampler :: Shader Memory Accesses */ +#define cflgt2__sampler__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set Sampler :: HS Threads Dispatched */ +#define cflgt2__sampler__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set Sampler :: SLM Bytes Written */ +#define cflgt2__sampler__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set Sampler :: L3 Shader Throughput */ +#define cflgt2__sampler__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set Sampler :: Samples Killed in FS */ +#define cflgt2__sampler__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set Sampler :: Shader Atomic Memory Accesses */ +#define cflgt2__sampler__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set TDL_1 :: GPU Core Clocks */ +#define cflgt2__tdl_1__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set TDL_1 :: EU Active */ +#define cflgt2__tdl_1__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set TDL_1 :: EU Both FPU Pipes Active */ +#define cflgt2__tdl_1__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set TDL_1 :: VS Send Pipe Active */ +#define cflgt2__tdl_1__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set TDL_1 :: VS FPU1 Pipe Active */ +#define cflgt2__tdl_1__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set TDL_1 :: GS Threads Dispatched */ +#define cflgt2__tdl_1__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set TDL_1 :: Early Hi-Depth Test Fails */ +#define cflgt2__tdl_1__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set TDL_1 :: FS Both FPU Active */ +#define cflgt2__tdl_1__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set TDL_1 :: VS Threads Dispatched */ +#define cflgt2__tdl_1__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set TDL_1 :: FS Threads Dispatched */ +#define cflgt2__tdl_1__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice2 */ +#define cflgt2__tdl_1__non_ps_thread02_ready_for_dispatch__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Metric set TDL_1 :: Shader Barrier Messages */ +#define cflgt2__tdl_1__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_1 :: Sampler Texels */ +#define cflgt2__tdl_1__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set TDL_1 :: Pixels Failing Tests */ +#define cflgt2__tdl_1__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set TDL_1 :: GPU Time Elapsed */ +#define cflgt2__tdl_1__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set TDL_1 :: AVG GPU Core Frequency */ +#define cflgt2__tdl_1__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set TDL_1 :: AVG GPU Core Frequency */ +#define cflgt2__tdl_1__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set TDL_1 :: Sampler Texels Misses */ +#define cflgt2__tdl_1__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice0 */ +#define cflgt2__tdl_1__non_ps_thread00_ready_for_dispatch__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Metric set TDL_1 :: CS Threads Dispatched */ +#define cflgt2__tdl_1__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set TDL_1 :: SLM Bytes Read */ +#define cflgt2__tdl_1__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set TDL_1 :: PS FPU1 Pipe Active */ +#define cflgt2__tdl_1__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set TDL_1 :: PS Send Pipeline Active */ +#define cflgt2__tdl_1__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set TDL_1 :: VS FPU0 Pipe Active */ +#define cflgt2__tdl_1__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set TDL_1 :: GPU Busy */ +#define cflgt2__tdl_1__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice0 */ +#define cflgt2__tdl_1__ps_thread00_ready_for_dispatch__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set TDL_1 :: Rasterized Pixels */ +#define cflgt2__tdl_1__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set TDL_1 :: PS FPU0 Pipe Active */ +#define cflgt2__tdl_1__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set TDL_1 :: DS Threads Dispatched */ +#define cflgt2__tdl_1__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set TDL_1 :: Samples Written */ +#define cflgt2__tdl_1__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set TDL_1 :: EU Stall */ +#define cflgt2__tdl_1__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set TDL_1 :: Samples Blended */ +#define cflgt2__tdl_1__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set TDL_1 :: Early Depth Test Fails */ +#define cflgt2__tdl_1__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice1 */ +#define cflgt2__tdl_1__ps_thread01_ready_for_dispatch__read \ + bdw__render_pipe_profile__cl_bottleneck__read + +/* Metric set TDL_1 :: Shader Memory Accesses */ +#define cflgt2__tdl_1__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set TDL_1 :: HS Threads Dispatched */ +#define cflgt2__tdl_1__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice2 */ +#define cflgt2__tdl_1__ps_thread02_ready_for_dispatch__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Metric set TDL_1 :: SLM Bytes Written */ +#define cflgt2__tdl_1__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set TDL_1 :: L3 Shader Throughput */ +#define cflgt2__tdl_1__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set TDL_1 :: Samples Killed in FS */ +#define cflgt2__tdl_1__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set TDL_1 :: Shader Atomic Memory Accesses */ +#define cflgt2__tdl_1__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice1 */ +#define cflgt2__tdl_1__non_ps_thread01_ready_for_dispatch__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set TDL_2 :: GPU Core Clocks */ +#define cflgt2__tdl_2__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set TDL_2 :: EU Active */ +#define cflgt2__tdl_2__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set TDL_2 :: EU Both FPU Pipes Active */ +#define cflgt2__tdl_2__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set TDL_2 :: VS Send Pipe Active */ +#define cflgt2__tdl_2__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set TDL_2 :: VS FPU1 Pipe Active */ +#define cflgt2__tdl_2__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set TDL_2 :: GS Threads Dispatched */ +#define cflgt2__tdl_2__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set TDL_2 :: Early Hi-Depth Test Fails */ +#define cflgt2__tdl_2__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set TDL_2 :: FS Both FPU Active */ +#define cflgt2__tdl_2__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set TDL_2 :: VS Threads Dispatched */ +#define cflgt2__tdl_2__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set TDL_2 :: FS Threads Dispatched */ +#define cflgt2__tdl_2__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set TDL_2 :: Shader Barrier Messages */ +#define cflgt2__tdl_2__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_2 :: Sampler Texels */ +#define cflgt2__tdl_2__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set TDL_2 :: Pixels Failing Tests */ +#define cflgt2__tdl_2__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 0 */ +#define cflgt2__tdl_2__thread_header01_ready_port0__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 1 */ +#define cflgt2__tdl_2__thread_header01_ready_port1__read \ + bdw__render_pipe_profile__ds_stall__read + +/* Metric set TDL_2 :: GPU Time Elapsed */ +#define cflgt2__tdl_2__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set TDL_2 :: AVG GPU Core Frequency */ +#define cflgt2__tdl_2__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set TDL_2 :: AVG GPU Core Frequency */ +#define cflgt2__tdl_2__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set TDL_2 :: Sampler Texels Misses */ +#define cflgt2__tdl_2__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set TDL_2 :: CS Threads Dispatched */ +#define cflgt2__tdl_2__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set TDL_2 :: SLM Bytes Read */ +#define cflgt2__tdl_2__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set TDL_2 :: PS FPU1 Pipe Active */ +#define cflgt2__tdl_2__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set TDL_2 :: PS Send Pipeline Active */ +#define cflgt2__tdl_2__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set TDL_2 :: VS FPU0 Pipe Active */ +#define cflgt2__tdl_2__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set TDL_2 :: GPU Busy */ +#define cflgt2__tdl_2__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 1 */ +#define cflgt2__tdl_2__thread_header02_ready_port1__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 0 */ +#define cflgt2__tdl_2__thread_header02_ready_port0__read \ + bdw__render_pipe_profile__so_stall__read + +/* Metric set TDL_2 :: Rasterized Pixels */ +#define cflgt2__tdl_2__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set TDL_2 :: PS FPU0 Pipe Active */ +#define cflgt2__tdl_2__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set TDL_2 :: DS Threads Dispatched */ +#define cflgt2__tdl_2__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set TDL_2 :: Samples Written */ +#define cflgt2__tdl_2__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set TDL_2 :: EU Stall */ +#define cflgt2__tdl_2__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set TDL_2 :: Samples Blended */ +#define cflgt2__tdl_2__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set TDL_2 :: Early Depth Test Fails */ +#define cflgt2__tdl_2__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_2 :: Shader Memory Accesses */ +#define cflgt2__tdl_2__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set TDL_2 :: HS Threads Dispatched */ +#define cflgt2__tdl_2__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set TDL_2 :: SLM Bytes Written */ +#define cflgt2__tdl_2__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set TDL_2 :: L3 Shader Throughput */ +#define cflgt2__tdl_2__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set TDL_2 :: Samples Killed in FS */ +#define cflgt2__tdl_2__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 0 */ +#define cflgt2__tdl_2__thread_header00_ready_port0__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set TDL_2 :: Shader Atomic Memory Accesses */ +#define cflgt2__tdl_2__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 1 */ +#define cflgt2__tdl_2__thread_header00_ready_port1__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Compute Metrics Extra Gen9 :: GPU Core Clocks */ +#define cflgt2__compute_extra__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Extra Gen9 :: EU FPU1 Pipe Active */ +#define cflgt2__compute_extra__fpu1_active__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics Extra Gen9 :: GPU Time Elapsed */ +#define cflgt2__compute_extra__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics Extra Gen9 :: AVG GPU Core Frequency */ +#define cflgt2__compute_extra__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics Extra Gen9 :: AVG GPU Core Frequency */ +#define cflgt2__compute_extra__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics Extra Gen9 :: EU FPU1 Pipe Active including Ext Math */ +#define cflgt2__compute_extra__fpu1_active_adjusted__read \ + sklgt2__compute_extra__fpu1_active_adjusted__read + +/* Media Vme Pipe Gen9 :: GPU Core Clocks */ +#define cflgt2__vme_pipe__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Media Vme Pipe Gen9 :: EU Active */ +#define cflgt2__vme_pipe__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Media Vme Pipe Gen9 :: EU Both FPU Pipes Active */ +#define cflgt2__vme_pipe__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Media Vme Pipe Gen9 :: GPU Time Elapsed */ +#define cflgt2__vme_pipe__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Media Vme Pipe Gen9 :: AVG GPU Core Frequency */ +#define cflgt2__vme_pipe__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Media Vme Pipe Gen9 :: AVG GPU Core Frequency */ +#define cflgt2__vme_pipe__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Media Vme Pipe Gen9 :: CS Threads Dispatched */ +#define cflgt2__vme_pipe__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Media Vme Pipe Gen9 :: EU Thread Occupancy */ +#define cflgt2__vme_pipe__eu_thread_occupancy__read \ + bdw__vme_pipe__eu_thread_occupancy__read + +/* Media Vme Pipe Gen9 :: EU Stall */ +#define cflgt2__vme_pipe__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Media Vme Pipe Gen9 :: VME Busy */ +#define cflgt2__vme_pipe__vme_busy__read \ + bdw__vme_pipe__vme_busy__read + +/* Media Vme Pipe Gen9 :: GPU Busy */ +#define cflgt2__vme_pipe__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* MDAPI testing set Gen9.5 :: TestCounter7 */ +#define cflgt2__test_oa__counter7__read \ + hsw__compute_extended__gpu_clocks__read + +/* MDAPI testing set Gen9.5 :: GPU Time Elapsed */ +#define cflgt2__test_oa__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* MDAPI testing set Gen9.5 :: GPU Core Clocks */ +#define cflgt2__test_oa__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* MDAPI testing set Gen9.5 :: AVG GPU Core Frequency */ +#define cflgt2__test_oa__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* MDAPI testing set Gen9.5 :: AVG GPU Core Frequency */ +#define cflgt2__test_oa__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* MDAPI testing set Gen9.5 :: TestCounter8 */ +#define cflgt2__test_oa__counter8__read \ + hsw__memory_reads__gpu_core_clocks__read + +/* MDAPI testing set Gen9.5 :: TestCounter4 */ +#define cflgt2__test_oa__counter4__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* MDAPI testing set Gen9.5 :: TestCounter5 */ +#define cflgt2__test_oa__counter5__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* MDAPI testing set Gen9.5 :: TestCounter6 */ +#define cflgt2__test_oa__counter6__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* MDAPI testing set Gen9.5 :: TestCounter3 */ +#define cflgt2__test_oa__counter3__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* MDAPI testing set Gen9.5 :: TestCounter0 */ +#define cflgt2__test_oa__counter0__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* MDAPI testing set Gen9.5 :: TestCounter1 */ +#define cflgt2__test_oa__counter1__read \ + hsw__compute_extended__eu_untyped_writes0__read + +/* MDAPI testing set Gen9.5 :: TestCounter2 */ +#define cflgt2__test_oa__counter2__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Render Metrics Basic Gen9 :: GPU Core Clocks */ +#define cflgt3__render_basic__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Render Metrics Basic Gen9 :: EU Active */ +#define cflgt3__render_basic__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Render Metrics Basic Gen9 :: L3 Misses */ +#define cflgt3__render_basic__l3_misses__read \ + hsw__compute_extended__typed_atomics0__read + +/* Render Metrics Basic Gen9 :: GTI L3 Throughput */ +#define cflgt3__render_basic__gti_l3_throughput__read \ + hsw__render_basic__gti_l3_throughput__read + +/* Render Metrics Basic Gen9 :: EU Both FPU Pipes Active */ +#define cflgt3__render_basic__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Render Metrics Basic Gen9 :: Sampler Cache Misses */ +#define cflgt3__render_basic__sampler_l1_misses__read \ + bdw__render_basic__sampler_l1_misses__read + +/* Render Metrics Basic Gen9 :: VS Send Pipe Active */ +#define cflgt3__render_basic__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Render Metrics Basic Gen9 :: Sampler 1 Bottleneck */ +#define cflgt3__render_basic__sampler1_bottleneck__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Render Metrics Basic Gen9 :: VS FPU1 Pipe Active */ +#define cflgt3__render_basic__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Render Metrics Basic Gen9 :: GS Threads Dispatched */ +#define cflgt3__render_basic__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Render Metrics Basic Gen9 :: L3 Sampler Throughput */ +#define cflgt3__render_basic__l3_sampler_throughput__read \ + bdw__render_basic__l3_sampler_throughput__read + +/* Render Metrics Basic Gen9 :: Early Hi-Depth Test Fails */ +#define cflgt3__render_basic__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Render Metrics Basic Gen9 :: FS Both FPU Active */ +#define cflgt3__render_basic__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Render Metrics Basic Gen9 :: VS Threads Dispatched */ +#define cflgt3__render_basic__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Render Metrics Basic Gen9 :: FS Threads Dispatched */ +#define cflgt3__render_basic__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Render Metrics Basic Gen9 :: Sampler 0 Busy */ +#define cflgt3__render_basic__sampler0_busy__read \ + bdw__render_basic__sampler0_busy__read + +/* Render Metrics Basic Gen9 :: Sampler 1 Busy */ +#define cflgt3__render_basic__sampler1_busy__read \ + bdw__render_basic__sampler1_busy__read + +/* Render Metrics Basic Gen9 :: Samplers Busy */ +#define cflgt3__render_basic__samplers_busy__read \ + bdw__render_basic__samplers_busy__read + +/* Render Metrics Basic Gen9 :: GTI Fixed Pipe Throughput */ +#define cflgt3__render_basic__gti_vf_throughput__read \ + bdw__render_basic__gti_vf_throughput__read + +/* Render Metrics Basic Gen9 :: Shader Barrier Messages */ +#define cflgt3__render_basic__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Render Metrics Basic Gen9 :: Sampler 0 Bottleneck */ +#define cflgt3__render_basic__sampler0_bottleneck__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Render Metrics Basic Gen9 :: Sampler Texels */ +#define cflgt3__render_basic__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Render Metrics Basic Gen9 :: Pixels Failing Tests */ +#define cflgt3__render_basic__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Render Metrics Basic Gen9 :: GPU Time Elapsed */ +#define cflgt3__render_basic__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Render Metrics Basic Gen9 :: AVG GPU Core Frequency */ +#define cflgt3__render_basic__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Render Metrics Basic Gen9 :: AVG GPU Core Frequency */ +#define cflgt3__render_basic__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Render Metrics Basic Gen9 :: Sampler Texels Misses */ +#define cflgt3__render_basic__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Render Metrics Basic Gen9 :: CS Threads Dispatched */ +#define cflgt3__render_basic__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Render Metrics Basic Gen9 :: Shader Memory Accesses */ +#define cflgt3__render_basic__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Render Metrics Basic Gen9 :: L3 Lookup Accesses w/o IC */ +#define cflgt3__render_basic__l3_lookups__read \ + bdw__render_basic__l3_lookups__read + +/* Render Metrics Basic Gen9 :: SLM Bytes Read */ +#define cflgt3__render_basic__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Render Metrics Basic Gen9 :: GTI Read Throughput */ +#define cflgt3__render_basic__gti_read_throughput__read \ + bdw__render_basic__gti_read_throughput__read + +/* Render Metrics Basic Gen9 :: PS FPU1 Pipe Active */ +#define cflgt3__render_basic__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Render Metrics Basic Gen9 :: PS Send Pipeline Active */ +#define cflgt3__render_basic__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Render Metrics Basic Gen9 :: Rasterized Pixels */ +#define cflgt3__render_basic__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Render Metrics Basic Gen9 :: GPU Busy */ +#define cflgt3__render_basic__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Render Metrics Basic Gen9 :: GTI Depth Throughput */ +#define cflgt3__render_basic__gti_depth_throughput__read \ + bdw__render_basic__gti_depth_throughput__read + +/* Render Metrics Basic Gen9 :: VS FPU0 Pipe Active */ +#define cflgt3__render_basic__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Render Metrics Basic Gen9 :: PS FPU0 Pipe Active */ +#define cflgt3__render_basic__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Render Metrics Basic Gen9 :: DS Threads Dispatched */ +#define cflgt3__render_basic__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Render Metrics Basic Gen9 :: Samples Written */ +#define cflgt3__render_basic__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Render Metrics Basic Gen9 :: EU Stall */ +#define cflgt3__render_basic__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Render Metrics Basic Gen9 :: Samples Blended */ +#define cflgt3__render_basic__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Render Metrics Basic Gen9 :: Early Depth Test Fails */ +#define cflgt3__render_basic__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Render Metrics Basic Gen9 :: Samplers Bottleneck */ +#define cflgt3__render_basic__sampler_bottleneck__read \ + bdw__render_basic__sampler_bottleneck__read + +/* Render Metrics Basic Gen9 :: GTI HDC TLB Lookup Throughput */ +#define cflgt3__render_basic__gti_hdc_lookups_throughput__read \ + bdw__render_basic__gti_hdc_lookups_throughput__read + +/* Render Metrics Basic Gen9 :: GTI RCC Throughput */ +#define cflgt3__render_basic__gti_rcc_throughput__read \ + bdw__render_basic__gti_rcc_throughput__read + +/* Render Metrics Basic Gen9 :: HS Threads Dispatched */ +#define cflgt3__render_basic__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Render Metrics Basic Gen9 :: GTI Write Throughput */ +#define cflgt3__render_basic__gti_write_throughput__read \ + hsw__render_basic__gti_write_throughput__read + +/* Render Metrics Basic Gen9 :: SLM Bytes Written */ +#define cflgt3__render_basic__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Render Metrics Basic Gen9 :: L3 Shader Throughput */ +#define cflgt3__render_basic__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Render Metrics Basic Gen9 :: Samples Killed in FS */ +#define cflgt3__render_basic__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Render Metrics Basic Gen9 :: Shader Atomic Memory Accesses */ +#define cflgt3__render_basic__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Basic Gen9 :: GPU Core Clocks */ +#define cflgt3__compute_basic__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Basic Gen9 :: EU Active */ +#define cflgt3__compute_basic__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Compute Metrics Basic Gen9 :: Untyped Bytes Read */ +#define cflgt3__compute_basic__untyped_bytes_read__read \ + bdw__compute_basic__untyped_bytes_read__read + +/* Compute Metrics Basic Gen9 :: EU Both FPU Pipes Active */ +#define cflgt3__compute_basic__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Compute Metrics Basic Gen9 :: Typed Bytes Written */ +#define cflgt3__compute_basic__typed_bytes_written__read \ + bdw__compute_basic__typed_bytes_written__read + +/* Compute Metrics Basic Gen9 :: EU FPU0 Pipe Active */ +#define cflgt3__compute_basic__fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Compute Metrics Basic Gen9 :: EU FPU1 Pipe Active */ +#define cflgt3__compute_basic__fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Compute Metrics Basic Gen9 :: EU AVG IPC Rate */ +#define cflgt3__compute_basic__eu_avg_ipc_rate__read \ + bdw__compute_basic__eu_avg_ipc_rate__read + +/* Compute Metrics Basic Gen9 :: GS Threads Dispatched */ +#define cflgt3__compute_basic__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Compute Metrics Basic Gen9 :: Early Hi-Depth Test Fails */ +#define cflgt3__compute_basic__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Compute Metrics Basic Gen9 :: VS Threads Dispatched */ +#define cflgt3__compute_basic__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Compute Metrics Basic Gen9 :: FS Threads Dispatched */ +#define cflgt3__compute_basic__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Compute Metrics Basic Gen9 :: Shader Barrier Messages */ +#define cflgt3__compute_basic__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Compute Metrics Basic Gen9 :: Sampler Texels */ +#define cflgt3__compute_basic__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Compute Metrics Basic Gen9 :: Pixels Failing Tests */ +#define cflgt3__compute_basic__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Compute Metrics Basic Gen9 :: GPU Time Elapsed */ +#define cflgt3__compute_basic__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics Basic Gen9 :: AVG GPU Core Frequency */ +#define cflgt3__compute_basic__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics Basic Gen9 :: AVG GPU Core Frequency */ +#define cflgt3__compute_basic__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics Basic Gen9 :: Sampler Texels Misses */ +#define cflgt3__compute_basic__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Compute Metrics Basic Gen9 :: CS Threads Dispatched */ +#define cflgt3__compute_basic__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Compute Metrics Basic Gen9 :: SLM Bytes Read */ +#define cflgt3__compute_basic__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Compute Metrics Basic Gen9 :: GTI Read Throughput */ +#define cflgt3__compute_basic__gti_read_throughput__read \ + hsw__render_basic__gti_l3_throughput__read + +/* Compute Metrics Basic Gen9 :: Untyped Writes */ +#define cflgt3__compute_basic__untyped_bytes_written__read \ + bdw__compute_basic__untyped_bytes_written__read + +/* Compute Metrics Basic Gen9 :: GPU Busy */ +#define cflgt3__compute_basic__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Compute Metrics Basic Gen9 :: Rasterized Pixels */ +#define cflgt3__compute_basic__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Compute Metrics Basic Gen9 :: Typed Bytes Read */ +#define cflgt3__compute_basic__typed_bytes_read__read \ + bdw__compute_basic__typed_bytes_read__read + +/* Compute Metrics Basic Gen9 :: DS Threads Dispatched */ +#define cflgt3__compute_basic__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Compute Metrics Basic Gen9 :: EU Thread Occupancy */ +#define cflgt3__compute_basic__eu_thread_occupancy__read \ + bdw__compute_basic__eu_thread_occupancy__read + +/* Compute Metrics Basic Gen9 :: EU Stall */ +#define cflgt3__compute_basic__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics Basic Gen9 :: Samples Blended */ +#define cflgt3__compute_basic__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Compute Metrics Basic Gen9 :: Early Depth Test Fails */ +#define cflgt3__compute_basic__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Compute Metrics Basic Gen9 :: Shader Memory Accesses */ +#define cflgt3__compute_basic__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Compute Metrics Basic Gen9 :: HS Threads Dispatched */ +#define cflgt3__compute_basic__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Compute Metrics Basic Gen9 :: GTI Write Throughput */ +#define cflgt3__compute_basic__gti_write_throughput__read \ + bdw__render_basic__gti_hdc_lookups_throughput__read + +/* Compute Metrics Basic Gen9 :: SLM Bytes Written */ +#define cflgt3__compute_basic__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Compute Metrics Basic Gen9 :: L3 Shader Throughput */ +#define cflgt3__compute_basic__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Compute Metrics Basic Gen9 :: Samples Killed in FS */ +#define cflgt3__compute_basic__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Compute Metrics Basic Gen9 :: Samples Written */ +#define cflgt3__compute_basic__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Compute Metrics Basic Gen9 :: Shader Atomic Memory Accesses */ +#define cflgt3__compute_basic__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Basic Gen9 :: EU Send Pipe Active */ +#define cflgt3__compute_basic__eu_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Core Clocks */ +#define cflgt3__render_pipe_profile__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: EU Active */ +#define cflgt3__render_pipe_profile__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: VS Bottleneck */ +#define cflgt3__render_pipe_profile__vs_bottleneck__read \ + bdw__render_basic__sampler0_busy__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Hi-Depth Bottleneck */ +#define cflgt3__render_pipe_profile__hi_depth_bottleneck__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GS Bottleneck */ +#define cflgt3__render_pipe_profile__gs_bottleneck__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GS Threads Dispatched */ +#define cflgt3__render_pipe_profile__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Early Hi-Depth Test Fails */ +#define cflgt3__render_pipe_profile__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: VS Threads Dispatched */ +#define cflgt3__render_pipe_profile__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: FS Threads Dispatched */ +#define cflgt3__render_pipe_profile__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: BC Bottleneck */ +#define cflgt3__render_pipe_profile__bc_bottleneck__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: HS Stall */ +#define cflgt3__render_pipe_profile__hs_stall__read \ + bdw__render_pipe_profile__hs_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Barrier Messages */ +#define cflgt3__render_pipe_profile__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Sampler Texels */ +#define cflgt3__render_pipe_profile__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Pixels Failing Tests */ +#define cflgt3__render_pipe_profile__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Time Elapsed */ +#define cflgt3__render_pipe_profile__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: AVG GPU Core Frequency */ +#define cflgt3__render_pipe_profile__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: AVG GPU Core Frequency */ +#define cflgt3__render_pipe_profile__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Sampler Texels Misses */ +#define cflgt3__render_pipe_profile__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: CS Threads Dispatched */ +#define cflgt3__render_pipe_profile__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: VF Bottleneck */ +#define cflgt3__render_pipe_profile__vf_bottleneck__read \ + bdw__render_pipe_profile__vf_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SLM Bytes Read */ +#define cflgt3__render_pipe_profile__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Strip-Fans Bottleneck */ +#define cflgt3__render_pipe_profile__sf_bottleneck__read \ + bdw__render_pipe_profile__sf_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SF Stall */ +#define cflgt3__render_pipe_profile__sf_stall__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: GPU Busy */ +#define cflgt3__render_pipe_profile__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: HS Bottleneck */ +#define cflgt3__render_pipe_profile__hs_bottleneck__read \ + bdw__render_basic__sampler1_busy__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: CL Stall */ +#define cflgt3__render_pipe_profile__cl_stall__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SO Bottleneck */ +#define cflgt3__render_pipe_profile__so_bottleneck__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Rasterized Pixels */ +#define cflgt3__render_pipe_profile__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: DS Threads Dispatched */ +#define cflgt3__render_pipe_profile__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Written */ +#define cflgt3__render_pipe_profile__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: DS Bottleneck */ +#define cflgt3__render_pipe_profile__ds_bottleneck__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: EU Stall */ +#define cflgt3__render_pipe_profile__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Clipper Bottleneck */ +#define cflgt3__render_pipe_profile__cl_bottleneck__read \ + bdw__render_pipe_profile__cl_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: DS Stall */ +#define cflgt3__render_pipe_profile__ds_stall__read \ + bdw__render_pipe_profile__ds_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Early Depth Bottleneck */ +#define cflgt3__render_pipe_profile__early_depth_bottleneck__read \ + bdw__render_pipe_profile__early_depth_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Blended */ +#define cflgt3__render_pipe_profile__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Early Depth Test Fails */ +#define cflgt3__render_pipe_profile__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Memory Accesses */ +#define cflgt3__render_pipe_profile__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: HS Threads Dispatched */ +#define cflgt3__render_pipe_profile__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SLM Bytes Written */ +#define cflgt3__render_pipe_profile__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: L3 Shader Throughput */ +#define cflgt3__render_pipe_profile__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Samples Killed in FS */ +#define cflgt3__render_pipe_profile__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: SO Stall */ +#define cflgt3__render_pipe_profile__so_stall__read \ + bdw__render_pipe_profile__so_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen9 :: Shader Atomic Memory Accesses */ +#define cflgt3__render_pipe_profile__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Memory Reads Distribution Gen9 :: GPU Core Clocks */ +#define cflgt3__memory_reads__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Memory Reads Distribution Gen9 :: EU Active */ +#define cflgt3__memory_reads__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Memory Reads Distribution Gen9 :: GtiL3Bank0Reads */ +#define cflgt3__memory_reads__gti_l3_bank0_reads__read \ + hsw__compute_extended__typed_atomics0__read + +/* Memory Reads Distribution Gen9 :: GS Threads Dispatched */ +#define cflgt3__memory_reads__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Memory Reads Distribution Gen9 :: GtiRingAccesses */ +#define cflgt3__memory_reads__gti_ring_accesses__read \ + bdw__memory_reads__gti_ring_accesses__read + +/* Memory Reads Distribution Gen9 :: Early Hi-Depth Test Fails */ +#define cflgt3__memory_reads__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Memory Reads Distribution Gen9 :: VS Threads Dispatched */ +#define cflgt3__memory_reads__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Memory Reads Distribution Gen9 :: FS Threads Dispatched */ +#define cflgt3__memory_reads__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Memory Reads Distribution Gen9 :: GtiL3Bank3Reads */ +#define cflgt3__memory_reads__gti_l3_bank3_reads__read \ + hsw__memory_reads__gpu_core_clocks__read + +/* Memory Reads Distribution Gen9 :: Shader Barrier Messages */ +#define cflgt3__memory_reads__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Memory Reads Distribution Gen9 :: GtiRsMemoryReads */ +#define cflgt3__memory_reads__gti_rs_memory_reads__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Memory Reads Distribution Gen9 :: Sampler Texels */ +#define cflgt3__memory_reads__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Memory Reads Distribution Gen9 :: Pixels Failing Tests */ +#define cflgt3__memory_reads__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Memory Reads Distribution Gen9 :: GtiHizMemoryReads */ +#define cflgt3__memory_reads__gti_hiz_memory_reads__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* Memory Reads Distribution Gen9 :: GPU Time Elapsed */ +#define cflgt3__memory_reads__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Memory Reads Distribution Gen9 :: AVG GPU Core Frequency */ +#define cflgt3__memory_reads__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Memory Reads Distribution Gen9 :: AVG GPU Core Frequency */ +#define cflgt3__memory_reads__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Memory Reads Distribution Gen9 :: Sampler Texels Misses */ +#define cflgt3__memory_reads__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Memory Reads Distribution Gen9 :: GtiRccMemoryReads */ +#define cflgt3__memory_reads__gti_rcc_memory_reads__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* Memory Reads Distribution Gen9 :: CS Threads Dispatched */ +#define cflgt3__memory_reads__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Memory Reads Distribution Gen9 :: SLM Bytes Read */ +#define cflgt3__memory_reads__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Memory Reads Distribution Gen9 :: GtiL3Bank1Reads */ +#define cflgt3__memory_reads__gti_l3_bank1_reads__read \ + hsw__memory_reads__gti_memory_reads__read + +/* Memory Reads Distribution Gen9 :: GPU Busy */ +#define cflgt3__memory_reads__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Memory Reads Distribution Gen9 :: GtiCmdStreamerMemoryReads */ +#define cflgt3__memory_reads__gti_cmd_streamer_memory_reads__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* Memory Reads Distribution Gen9 :: GtiL3Bank2Reads */ +#define cflgt3__memory_reads__gti_l3_bank2_reads__read \ + hsw__memory_reads__llc_read_accesses__read + +/* Memory Reads Distribution Gen9 :: GtiMemoryReads */ +#define cflgt3__memory_reads__gti_memory_reads__read \ + hsw__compute_extended__typed_writes0__read + +/* Memory Reads Distribution Gen9 :: Rasterized Pixels */ +#define cflgt3__memory_reads__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Memory Reads Distribution Gen9 :: GtiRczMemoryReads */ +#define cflgt3__memory_reads__gti_rcz_memory_reads__read \ + hsw__compute_extended__gpu_clocks__read + +/* Memory Reads Distribution Gen9 :: DS Threads Dispatched */ +#define cflgt3__memory_reads__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Memory Reads Distribution Gen9 :: Samples Written */ +#define cflgt3__memory_reads__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Memory Reads Distribution Gen9 :: EU Stall */ +#define cflgt3__memory_reads__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Memory Reads Distribution Gen9 :: Samples Blended */ +#define cflgt3__memory_reads__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Memory Reads Distribution Gen9 :: Early Depth Test Fails */ +#define cflgt3__memory_reads__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Memory Reads Distribution Gen9 :: GtiMscMemoryReads */ +#define cflgt3__memory_reads__gti_msc_memory_reads__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* Memory Reads Distribution Gen9 :: GtiVfMemoryReads */ +#define cflgt3__memory_reads__gti_vf_memory_reads__read \ + hsw__compute_extended__eu_untyped_writes0__read + +/* Memory Reads Distribution Gen9 :: GtiStcMemoryReads */ +#define cflgt3__memory_reads__gti_stc_memory_reads__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* Memory Reads Distribution Gen9 :: Shader Memory Accesses */ +#define cflgt3__memory_reads__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Memory Reads Distribution Gen9 :: HS Threads Dispatched */ +#define cflgt3__memory_reads__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Memory Reads Distribution Gen9 :: Samples Killed in FS */ +#define cflgt3__memory_reads__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Memory Reads Distribution Gen9 :: SLM Bytes Written */ +#define cflgt3__memory_reads__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Memory Reads Distribution Gen9 :: GtiL3Reads */ +#define cflgt3__memory_reads__gti_l3_reads__read \ + bdw__memory_reads__gti_l3_reads__read + +/* Memory Reads Distribution Gen9 :: Shader Atomic Memory Accesses */ +#define cflgt3__memory_reads__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Memory Writes Distribution Gen9 :: GPU Core Clocks */ +#define cflgt3__memory_writes__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Memory Writes Distribution Gen9 :: EU Active */ +#define cflgt3__memory_writes__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Memory Writes Distribution Gen9 :: GtiMemoryWrites */ +#define cflgt3__memory_writes__gti_memory_writes__read \ + hsw__compute_extended__typed_writes0__read + +/* Memory Writes Distribution Gen9 :: GS Threads Dispatched */ +#define cflgt3__memory_writes__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Memory Writes Distribution Gen9 :: GtiRingAccesses */ +#define cflgt3__memory_writes__gti_ring_accesses__read \ + bdw__memory_reads__gti_ring_accesses__read + +/* Memory Writes Distribution Gen9 :: Early Hi-Depth Test Fails */ +#define cflgt3__memory_writes__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Memory Writes Distribution Gen9 :: VS Threads Dispatched */ +#define cflgt3__memory_writes__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Memory Writes Distribution Gen9 :: FS Threads Dispatched */ +#define cflgt3__memory_writes__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Memory Writes Distribution Gen9 :: GtiMscMemoryWrites */ +#define cflgt3__memory_writes__gti_msc_memory_writes__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* Memory Writes Distribution Gen9 :: Shader Barrier Messages */ +#define cflgt3__memory_writes__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Memory Writes Distribution Gen9 :: GtiCmdStreamerMemoryWrites */ +#define cflgt3__memory_writes__gti_cmd_streamer_memory_writes__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* Memory Writes Distribution Gen9 :: Sampler Texels */ +#define cflgt3__memory_writes__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Memory Writes Distribution Gen9 :: Pixels Failing Tests */ +#define cflgt3__memory_writes__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Memory Writes Distribution Gen9 :: GtiL3Bank0Writes */ +#define cflgt3__memory_writes__gti_l3_bank0_writes__read \ + hsw__compute_extended__typed_atomics0__read + +/* Memory Writes Distribution Gen9 :: GtiL3Bank1Writes */ +#define cflgt3__memory_writes__gti_l3_bank1_writes__read \ + hsw__memory_reads__gti_memory_reads__read + +/* Memory Writes Distribution Gen9 :: GtiL3Bank2Writes */ +#define cflgt3__memory_writes__gti_l3_bank2_writes__read \ + hsw__memory_reads__llc_read_accesses__read + +/* Memory Writes Distribution Gen9 :: GtiL3Bank3Writes */ +#define cflgt3__memory_writes__gti_l3_bank3_writes__read \ + hsw__memory_reads__gpu_core_clocks__read + +/* Memory Writes Distribution Gen9 :: GtiL3Writes */ +#define cflgt3__memory_writes__gti_l3_writes__read \ + bdw__memory_reads__gti_l3_reads__read + +/* Memory Writes Distribution Gen9 :: GPU Time Elapsed */ +#define cflgt3__memory_writes__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Memory Writes Distribution Gen9 :: AVG GPU Core Frequency */ +#define cflgt3__memory_writes__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Memory Writes Distribution Gen9 :: AVG GPU Core Frequency */ +#define cflgt3__memory_writes__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Memory Writes Distribution Gen9 :: Sampler Texels Misses */ +#define cflgt3__memory_writes__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Memory Writes Distribution Gen9 :: CS Threads Dispatched */ +#define cflgt3__memory_writes__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Memory Writes Distribution Gen9 :: SLM Bytes Read */ +#define cflgt3__memory_writes__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Memory Writes Distribution Gen9 :: GtiRccMemoryWrites */ +#define cflgt3__memory_writes__gti_rcc_memory_writes__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* Memory Writes Distribution Gen9 :: GtiSoMemoryWrites */ +#define cflgt3__memory_writes__gti_so_memory_writes__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Memory Writes Distribution Gen9 :: GPU Busy */ +#define cflgt3__memory_writes__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Memory Writes Distribution Gen9 :: GtiStcMemoryWrites */ +#define cflgt3__memory_writes__gti_stc_memory_writes__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* Memory Writes Distribution Gen9 :: Rasterized Pixels */ +#define cflgt3__memory_writes__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Memory Writes Distribution Gen9 :: DS Threads Dispatched */ +#define cflgt3__memory_writes__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Memory Writes Distribution Gen9 :: Samples Written */ +#define cflgt3__memory_writes__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Memory Writes Distribution Gen9 :: EU Stall */ +#define cflgt3__memory_writes__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Memory Writes Distribution Gen9 :: Samples Blended */ +#define cflgt3__memory_writes__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Memory Writes Distribution Gen9 :: Early Depth Test Fails */ +#define cflgt3__memory_writes__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Memory Writes Distribution Gen9 :: Shader Memory Accesses */ +#define cflgt3__memory_writes__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Memory Writes Distribution Gen9 :: HS Threads Dispatched */ +#define cflgt3__memory_writes__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Memory Writes Distribution Gen9 :: GtiRczMemoryWrites */ +#define cflgt3__memory_writes__gti_rcz_memory_writes__read \ + hsw__compute_extended__gpu_clocks__read + +/* Memory Writes Distribution Gen9 :: SLM Bytes Written */ +#define cflgt3__memory_writes__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Memory Writes Distribution Gen9 :: L3 Shader Throughput */ +#define cflgt3__memory_writes__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Memory Writes Distribution Gen9 :: Samples Killed in FS */ +#define cflgt3__memory_writes__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Memory Writes Distribution Gen9 :: GtiHizMemoryWrites */ +#define cflgt3__memory_writes__gti_hiz_memory_writes__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* Memory Writes Distribution Gen9 :: Shader Atomic Memory Accesses */ +#define cflgt3__memory_writes__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Extended Gen9 :: GPU Core Clocks */ +#define cflgt3__compute_extended__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Extended Gen9 :: EU Active */ +#define cflgt3__compute_extended__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Compute Metrics Extended Gen9 :: EU Both FPU Pipes Active */ +#define cflgt3__compute_extended__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Compute Metrics Extended Gen9 :: EU FPU0 Pipe Active */ +#define cflgt3__compute_extended__fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Compute Metrics Extended Gen9 :: EU FPU1 Pipe Active */ +#define cflgt3__compute_extended__fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Compute Metrics Extended Gen9 :: EU AVG IPC Rate */ +#define cflgt3__compute_extended__eu_avg_ipc_rate__read \ + bdw__compute_basic__eu_avg_ipc_rate__read + +/* Compute Metrics Extended Gen9 :: Typed Writes 0 */ +#define cflgt3__compute_extended__typed_writes0__read \ + hsw__compute_extended__typed_writes0__read + +/* Compute Metrics Extended Gen9 :: EuTypedAtomics0 */ +#define cflgt3__compute_extended__eu_typed_atomics0__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* Compute Metrics Extended Gen9 :: Typed Atomics 0 */ +#define cflgt3__compute_extended__typed_atomics0__read \ + hsw__compute_extended__typed_atomics0__read + +/* Compute Metrics Extended Gen9 :: TypedAtomicsPerCacheLine */ +#define cflgt3__compute_extended__typed_atomics_per_cache_line__read \ + hsw__compute_extended__typed_atomics_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: EuUntypedReads0 */ +#define cflgt3__compute_extended__eu_untyped_reads0__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* Compute Metrics Extended Gen9 :: Untyped Writes 0 */ +#define cflgt3__compute_extended__untyped_writes0__read \ + hsw__compute_extended__untyped_writes0__read + +/* Compute Metrics Extended Gen9 :: EuUntypedAtomics0 */ +#define cflgt3__compute_extended__eu_untyped_atomics0__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* Compute Metrics Extended Gen9 :: EuUntypedWrites0 */ +#define cflgt3__compute_extended__eu_untyped_writes0__read \ + hsw__compute_extended__eu_untyped_writes0__read + +/* Compute Metrics Extended Gen9 :: EuA64UntypedWrites0 */ +#define cflgt3__compute_extended__eu_a64_untyped_writes0__read \ + hsw__compute_extended__gpu_clocks__read + +/* Compute Metrics Extended Gen9 :: UntypedWritesPerCacheLine */ +#define cflgt3__compute_extended__untyped_writes_per_cache_line__read \ + bdw__compute_extended__untyped_writes_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: Shader Barrier Messages */ +#define cflgt3__compute_extended__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Compute Metrics Extended Gen9 :: Sampler Texels */ +#define cflgt3__compute_extended__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Compute Metrics Extended Gen9 :: GPU Time Elapsed */ +#define cflgt3__compute_extended__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics Extended Gen9 :: AVG GPU Core Frequency */ +#define cflgt3__compute_extended__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics Extended Gen9 :: AVG GPU Core Frequency */ +#define cflgt3__compute_extended__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics Extended Gen9 :: Sampler Texels Misses */ +#define cflgt3__compute_extended__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Compute Metrics Extended Gen9 :: CS Threads Dispatched */ +#define cflgt3__compute_extended__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Compute Metrics Extended Gen9 :: SLM Bytes Read */ +#define cflgt3__compute_extended__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Compute Metrics Extended Gen9 :: EuTypedWrites0 */ +#define cflgt3__compute_extended__eu_typed_writes0__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* Compute Metrics Extended Gen9 :: TypedWritesPerCacheLine */ +#define cflgt3__compute_extended__typed_writes_per_cache_line__read \ + hsw__compute_extended__typed_writes_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: Typed Reads 0 */ +#define cflgt3__compute_extended__typed_reads0__read \ + hsw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Extended Gen9 :: Untyped Reads 0 */ +#define cflgt3__compute_extended__untyped_reads0__read \ + hsw__compute_extended__untyped_reads0__read + +/* Compute Metrics Extended Gen9 :: EuA64UntypedReads0 */ +#define cflgt3__compute_extended__eu_a64_untyped_reads0__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* Compute Metrics Extended Gen9 :: EU Thread Occupancy */ +#define cflgt3__compute_extended__eu_thread_occupancy__read \ + bdw__compute_basic__eu_thread_occupancy__read + +/* Compute Metrics Extended Gen9 :: EU Stall */ +#define cflgt3__compute_extended__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics Extended Gen9 :: EuTypedReads0 */ +#define cflgt3__compute_extended__eu_typed_reads0__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Compute Metrics Extended Gen9 :: UntypedReadsPerCacheLine */ +#define cflgt3__compute_extended__untyped_reads_per_cache_line__read \ + bdw__compute_extended__untyped_reads_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: Shader Memory Accesses */ +#define cflgt3__compute_extended__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Compute Metrics Extended Gen9 :: TypedReadsPerCacheLine */ +#define cflgt3__compute_extended__typed_reads_per_cache_line__read \ + hsw__compute_extended__typed_reads_per_cache_line__read + +/* Compute Metrics Extended Gen9 :: SLM Bytes Written */ +#define cflgt3__compute_extended__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Compute Metrics Extended Gen9 :: L3 Shader Throughput */ +#define cflgt3__compute_extended__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Compute Metrics Extended Gen9 :: Shader Atomic Memory Accesses */ +#define cflgt3__compute_extended__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Extended Gen9 :: EU Send Pipe Active */ +#define cflgt3__compute_extended__eu_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Compute Metrics L3 Cache Gen9 :: GPU Core Clocks */ +#define cflgt3__compute_l3_cache__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics L3 Cache Gen9 :: EU Active */ +#define cflgt3__compute_l3_cache__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 03 Accesses */ +#define cflgt3__compute_l3_cache__l3_bank03_accesses__read \ + bdw__compute_l3_cache__l3_bank03_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Accesses */ +#define cflgt3__compute_l3_cache__l3_accesses__read \ + sklgt2__compute_l3_cache__l3_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: EU Both FPU Pipes Active */ +#define cflgt3__compute_l3_cache__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Sampler Throughput */ +#define cflgt3__compute_l3_cache__l3_sampler_throughput__read \ + chv__render_basic__l3_sampler_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Pipe Active */ +#define cflgt3__compute_l3_cache__fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Pipe Active */ +#define cflgt3__compute_l3_cache__fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Compute Metrics L3 Cache Gen9 :: EU AVG IPC Rate */ +#define cflgt3__compute_l3_cache__eu_avg_ipc_rate__read \ + bdw__compute_basic__eu_avg_ipc_rate__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Binary Instruction */ +#define cflgt3__compute_l3_cache__eu_binary_fpu0_instruction__read \ + bdw__render_basic__ps_send_active__read + +/* Compute Metrics L3 Cache Gen9 :: GS Threads Dispatched */ +#define cflgt3__compute_l3_cache__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Compute Metrics L3 Cache Gen9 :: Shader Memory Accesses */ +#define cflgt3__compute_l3_cache__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: Early Hi-Depth Test Fails */ +#define cflgt3__compute_l3_cache__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Compute Metrics L3 Cache Gen9 :: VS Threads Dispatched */ +#define cflgt3__compute_l3_cache__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Compute Metrics L3 Cache Gen9 :: FS Threads Dispatched */ +#define cflgt3__compute_l3_cache__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Hybrid Instruction */ +#define cflgt3__compute_l3_cache__eu_hybrid_fpu0_instruction__read \ + bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Misses */ +#define cflgt3__compute_l3_cache__l3_misses__read \ + bdw__compute_l3_cache__l3_misses__read + +/* Compute Metrics L3 Cache Gen9 :: Shader Barrier Messages */ +#define cflgt3__compute_l3_cache__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 Accesses */ +#define cflgt3__compute_l3_cache__l3_bank00_accesses__read \ + bdw__compute_l3_cache__l3_bank00_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Move Instruction */ +#define cflgt3__compute_l3_cache__eu_move_fpu0_instruction__read \ + bdw__compute_l3_cache__eu_move_fpu0_instruction__read + +/* Compute Metrics L3 Cache Gen9 :: Sampler Texels */ +#define cflgt3__compute_l3_cache__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Compute Metrics L3 Cache Gen9 :: Pixels Failing Tests */ +#define cflgt3__compute_l3_cache__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Hybrid Instruction */ +#define cflgt3__compute_l3_cache__eu_hybrid_fpu1_instruction__read \ + bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read + +/* Compute Metrics L3 Cache Gen9 :: GPU Time Elapsed */ +#define cflgt3__compute_l3_cache__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics L3 Cache Gen9 :: AVG GPU Core Frequency */ +#define cflgt3__compute_l3_cache__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics L3 Cache Gen9 :: AVG GPU Core Frequency */ +#define cflgt3__compute_l3_cache__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics L3 Cache Gen9 :: Sampler Texels Misses */ +#define cflgt3__compute_l3_cache__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Compute Metrics L3 Cache Gen9 :: CS Threads Dispatched */ +#define cflgt3__compute_l3_cache__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Compute Metrics L3 Cache Gen9 :: SLM Bytes Read */ +#define cflgt3__compute_l3_cache__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Compute Metrics L3 Cache Gen9 :: GTI Read Throughput */ +#define cflgt3__compute_l3_cache__gti_read_throughput__read \ + bdw__render_basic__gti_read_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: GTI L3 Throughput */ +#define cflgt3__compute_l3_cache__gti_l3_throughput__read \ + bdw__compute_l3_cache__gti_l3_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 IC Accesses */ +#define cflgt3__compute_l3_cache__l3_bank00_ic_accesses__read \ + bdw__compute_l3_cache__l3_bank00_ic_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 00 IC Hits */ +#define cflgt3__compute_l3_cache__l3_bank00_ic_hits__read \ + bdw__compute_l3_cache__l3_bank00_ic_hits__read + +/* Compute Metrics L3 Cache Gen9 :: Sampler Accesses */ +#define cflgt3__compute_l3_cache__sampler_accesses__read \ + bdw__render_pipe_profile__sampler_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 01 Accesses */ +#define cflgt3__compute_l3_cache__l3_bank01_accesses__read \ + bdw__compute_l3_cache__l3_bank01_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: GPU Busy */ +#define cflgt3__compute_l3_cache__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU0 Ternary Instruction */ +#define cflgt3__compute_l3_cache__eu_ternary_fpu0_instruction__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Compute Metrics L3 Cache Gen9 :: Shader Atomic Memory Accesses */ +#define cflgt3__compute_l3_cache__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics L3 Cache Gen9 :: Rasterized Pixels */ +#define cflgt3__compute_l3_cache__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Compute Metrics L3 Cache Gen9 :: DS Threads Dispatched */ +#define cflgt3__compute_l3_cache__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Compute Metrics L3 Cache Gen9 :: Samples Written */ +#define cflgt3__compute_l3_cache__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Move Instruction */ +#define cflgt3__compute_l3_cache__eu_move_fpu1_instruction__read \ + bdw__compute_l3_cache__eu_move_fpu1_instruction__read + +/* Compute Metrics L3 Cache Gen9 :: EU Stall */ +#define cflgt3__compute_l3_cache__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics L3 Cache Gen9 :: Samples Blended */ +#define cflgt3__compute_l3_cache__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Compute Metrics L3 Cache Gen9 :: Early Depth Test Fails */ +#define cflgt3__compute_l3_cache__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Bank 02 Accesses */ +#define cflgt3__compute_l3_cache__l3_bank02_accesses__read \ + bdw__compute_l3_cache__l3_bank02_accesses__read + +/* Compute Metrics L3 Cache Gen9 :: HS Threads Dispatched */ +#define cflgt3__compute_l3_cache__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Total Throughput */ +#define cflgt3__compute_l3_cache__l3_total_throughput__read \ + sklgt2__compute_l3_cache__l3_total_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: GTI Write Throughput */ +#define cflgt3__compute_l3_cache__gti_write_throughput__read \ + hsw__render_basic__gti_write_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: SLM Bytes Written */ +#define cflgt3__compute_l3_cache__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Compute Metrics L3 Cache Gen9 :: L3 Shader Throughput */ +#define cflgt3__compute_l3_cache__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Compute Metrics L3 Cache Gen9 :: Samples Killed in FS */ +#define cflgt3__compute_l3_cache__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Binary Instruction */ +#define cflgt3__compute_l3_cache__eu_binary_fpu1_instruction__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Compute Metrics L3 Cache Gen9 :: EU FPU1 Ternary Instruction */ +#define cflgt3__compute_l3_cache__eu_ternary_fpu1_instruction__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Compute Metrics L3 Cache Gen9 :: EU Send Pipe Active */ +#define cflgt3__compute_l3_cache__eu_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set HDCAndSF :: GPU Core Clocks */ +#define cflgt3__hdc_and_sf__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set HDCAndSF :: EU Active */ +#define cflgt3__hdc_and_sf__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set HDCAndSF :: EU Both FPU Pipes Active */ +#define cflgt3__hdc_and_sf__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set HDCAndSF :: VS Send Pipe Active */ +#define cflgt3__hdc_and_sf__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set HDCAndSF :: VS FPU1 Pipe Active */ +#define cflgt3__hdc_and_sf__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set HDCAndSF :: GS Threads Dispatched */ +#define cflgt3__hdc_and_sf__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set HDCAndSF :: Early Hi-Depth Test Fails */ +#define cflgt3__hdc_and_sf__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set HDCAndSF :: FS Both FPU Active */ +#define cflgt3__hdc_and_sf__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set HDCAndSF :: VS Threads Dispatched */ +#define cflgt3__hdc_and_sf__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set HDCAndSF :: Polygon Data Ready */ +#define cflgt3__hdc_and_sf__poly_data_ready__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set HDCAndSF :: FS Threads Dispatched */ +#define cflgt3__hdc_and_sf__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set HDCAndSF :: Shader Barrier Messages */ +#define cflgt3__hdc_and_sf__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set HDCAndSF :: Sampler Texels */ +#define cflgt3__hdc_and_sf__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set HDCAndSF :: Pixels Failing Tests */ +#define cflgt3__hdc_and_sf__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set HDCAndSF :: GPU Time Elapsed */ +#define cflgt3__hdc_and_sf__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set HDCAndSF :: AVG GPU Core Frequency */ +#define cflgt3__hdc_and_sf__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set HDCAndSF :: AVG GPU Core Frequency */ +#define cflgt3__hdc_and_sf__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set HDCAndSF :: Sampler Texels Misses */ +#define cflgt3__hdc_and_sf__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss1) */ +#define cflgt3__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read \ + bdw__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read + +/* Metric set HDCAndSF :: CS Threads Dispatched */ +#define cflgt3__hdc_and_sf__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss2) */ +#define cflgt3__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read \ + bdw__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read + +/* Metric set HDCAndSF :: SLM Bytes Read */ +#define cflgt3__hdc_and_sf__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set HDCAndSF :: PS FPU1 Pipe Active */ +#define cflgt3__hdc_and_sf__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set HDCAndSF :: PS Send Pipeline Active */ +#define cflgt3__hdc_and_sf__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set HDCAndSF :: VS FPU0 Pipe Active */ +#define cflgt3__hdc_and_sf__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set HDCAndSF :: GPU Busy */ +#define cflgt3__hdc_and_sf__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set HDCAndSF :: Rasterized Pixels */ +#define cflgt3__hdc_and_sf__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set HDCAndSF :: PS FPU0 Pipe Active */ +#define cflgt3__hdc_and_sf__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set HDCAndSF :: DS Threads Dispatched */ +#define cflgt3__hdc_and_sf__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set HDCAndSF :: Samples Written */ +#define cflgt3__hdc_and_sf__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set HDCAndSF :: EU Stall */ +#define cflgt3__hdc_and_sf__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set HDCAndSF :: Samples Blended */ +#define cflgt3__hdc_and_sf__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set HDCAndSF :: Early Depth Test Fails */ +#define cflgt3__hdc_and_sf__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set HDCAndSF :: Shader Memory Accesses */ +#define cflgt3__hdc_and_sf__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set HDCAndSF :: HS Threads Dispatched */ +#define cflgt3__hdc_and_sf__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set HDCAndSF :: SLM Bytes Written */ +#define cflgt3__hdc_and_sf__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set HDCAndSF :: L3 Shader Throughput */ +#define cflgt3__hdc_and_sf__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set HDCAndSF :: Samples Killed in FS */ +#define cflgt3__hdc_and_sf__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set HDCAndSF :: HDC stalled by L3 (s0.ss0) */ +#define cflgt3__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read \ + bdw__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read + +/* Metric set HDCAndSF :: Shader Atomic Memory Accesses */ +#define cflgt3__hdc_and_sf__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set L3_1 :: GPU Core Clocks */ +#define cflgt3__l3_1__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set L3_1 :: EU Active */ +#define cflgt3__l3_1__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set L3_1 :: Slice0 L3 Bank1 Active */ +#define cflgt3__l3_1__l30_bank1_active__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set L3_1 :: EU Both FPU Pipes Active */ +#define cflgt3__l3_1__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set L3_1 :: VS Send Pipe Active */ +#define cflgt3__l3_1__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set L3_1 :: VS FPU1 Pipe Active */ +#define cflgt3__l3_1__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set L3_1 :: GS Threads Dispatched */ +#define cflgt3__l3_1__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set L3_1 :: Early Hi-Depth Test Fails */ +#define cflgt3__l3_1__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set L3_1 :: FS Both FPU Active */ +#define cflgt3__l3_1__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set L3_1 :: VS Threads Dispatched */ +#define cflgt3__l3_1__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set L3_1 :: Slice0 L3 Bank1 Stalled */ +#define cflgt3__l3_1__l30_bank1_stalled__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Metric set L3_1 :: FS Threads Dispatched */ +#define cflgt3__l3_1__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set L3_1 :: Shader Barrier Messages */ +#define cflgt3__l3_1__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set L3_1 :: Sampler Texels */ +#define cflgt3__l3_1__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set L3_1 :: Pixels Failing Tests */ +#define cflgt3__l3_1__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set L3_1 :: GPU Time Elapsed */ +#define cflgt3__l3_1__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set L3_1 :: AVG GPU Core Frequency */ +#define cflgt3__l3_1__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set L3_1 :: AVG GPU Core Frequency */ +#define cflgt3__l3_1__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set L3_1 :: Sampler Texels Misses */ +#define cflgt3__l3_1__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set L3_1 :: CS Threads Dispatched */ +#define cflgt3__l3_1__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set L3_1 :: SLM Bytes Read */ +#define cflgt3__l3_1__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set L3_1 :: PS FPU1 Pipe Active */ +#define cflgt3__l3_1__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set L3_1 :: PS Send Pipeline Active */ +#define cflgt3__l3_1__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set L3_1 :: VS FPU0 Pipe Active */ +#define cflgt3__l3_1__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set L3_1 :: GPU Busy */ +#define cflgt3__l3_1__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set L3_1 :: Slice0 L3 Bank0 Active */ +#define cflgt3__l3_1__l30_bank0_active__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set L3_1 :: Rasterized Pixels */ +#define cflgt3__l3_1__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set L3_1 :: PS FPU0 Pipe Active */ +#define cflgt3__l3_1__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set L3_1 :: Slice0 L3 Bank0 Stalled */ +#define cflgt3__l3_1__l30_bank0_stalled__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set L3_1 :: DS Threads Dispatched */ +#define cflgt3__l3_1__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set L3_1 :: Samples Written */ +#define cflgt3__l3_1__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set L3_1 :: EU Stall */ +#define cflgt3__l3_1__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set L3_1 :: Samples Blended */ +#define cflgt3__l3_1__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set L3_1 :: Early Depth Test Fails */ +#define cflgt3__l3_1__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set L3_1 :: Shader Memory Accesses */ +#define cflgt3__l3_1__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set L3_1 :: HS Threads Dispatched */ +#define cflgt3__l3_1__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set L3_1 :: SLM Bytes Written */ +#define cflgt3__l3_1__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set L3_1 :: L3 Shader Throughput */ +#define cflgt3__l3_1__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set L3_1 :: Samples Killed in FS */ +#define cflgt3__l3_1__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set L3_1 :: Shader Atomic Memory Accesses */ +#define cflgt3__l3_1__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set L3_2 :: GPU Core Clocks */ +#define cflgt3__l3_2__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set L3_2 :: EU Active */ +#define cflgt3__l3_2__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set L3_2 :: EU Both FPU Pipes Active */ +#define cflgt3__l3_2__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set L3_2 :: VS Send Pipe Active */ +#define cflgt3__l3_2__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set L3_2 :: VS FPU1 Pipe Active */ +#define cflgt3__l3_2__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set L3_2 :: GS Threads Dispatched */ +#define cflgt3__l3_2__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set L3_2 :: Early Hi-Depth Test Fails */ +#define cflgt3__l3_2__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set L3_2 :: FS Both FPU Active */ +#define cflgt3__l3_2__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set L3_2 :: VS Threads Dispatched */ +#define cflgt3__l3_2__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set L3_2 :: FS Threads Dispatched */ +#define cflgt3__l3_2__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set L3_2 :: Shader Barrier Messages */ +#define cflgt3__l3_2__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set L3_2 :: Sampler Texels */ +#define cflgt3__l3_2__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set L3_2 :: Pixels Failing Tests */ +#define cflgt3__l3_2__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set L3_2 :: GPU Time Elapsed */ +#define cflgt3__l3_2__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set L3_2 :: AVG GPU Core Frequency */ +#define cflgt3__l3_2__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set L3_2 :: AVG GPU Core Frequency */ +#define cflgt3__l3_2__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set L3_2 :: Sampler Texels Misses */ +#define cflgt3__l3_2__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set L3_2 :: CS Threads Dispatched */ +#define cflgt3__l3_2__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set L3_2 :: SLM Bytes Read */ +#define cflgt3__l3_2__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set L3_2 :: PS FPU1 Pipe Active */ +#define cflgt3__l3_2__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set L3_2 :: Slice0 L3 Bank2 Stalled */ +#define cflgt3__l3_2__l30_bank2_stalled__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set L3_2 :: PS Send Pipeline Active */ +#define cflgt3__l3_2__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set L3_2 :: VS FPU0 Pipe Active */ +#define cflgt3__l3_2__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set L3_2 :: GPU Busy */ +#define cflgt3__l3_2__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set L3_2 :: Slice0 L3 Bank2 Active */ +#define cflgt3__l3_2__l30_bank2_active__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set L3_2 :: Rasterized Pixels */ +#define cflgt3__l3_2__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set L3_2 :: PS FPU0 Pipe Active */ +#define cflgt3__l3_2__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set L3_2 :: DS Threads Dispatched */ +#define cflgt3__l3_2__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set L3_2 :: Samples Written */ +#define cflgt3__l3_2__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set L3_2 :: EU Stall */ +#define cflgt3__l3_2__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set L3_2 :: Samples Blended */ +#define cflgt3__l3_2__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set L3_2 :: Early Depth Test Fails */ +#define cflgt3__l3_2__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set L3_2 :: Shader Memory Accesses */ +#define cflgt3__l3_2__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set L3_2 :: HS Threads Dispatched */ +#define cflgt3__l3_2__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set L3_2 :: SLM Bytes Written */ +#define cflgt3__l3_2__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set L3_2 :: L3 Shader Throughput */ +#define cflgt3__l3_2__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set L3_2 :: Samples Killed in FS */ +#define cflgt3__l3_2__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set L3_2 :: Shader Atomic Memory Accesses */ +#define cflgt3__l3_2__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set L3_3 :: GPU Core Clocks */ +#define cflgt3__l3_3__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set L3_3 :: EU Active */ +#define cflgt3__l3_3__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set L3_3 :: EU Both FPU Pipes Active */ +#define cflgt3__l3_3__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set L3_3 :: VS Send Pipe Active */ +#define cflgt3__l3_3__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set L3_3 :: VS FPU1 Pipe Active */ +#define cflgt3__l3_3__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set L3_3 :: GS Threads Dispatched */ +#define cflgt3__l3_3__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set L3_3 :: Early Hi-Depth Test Fails */ +#define cflgt3__l3_3__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set L3_3 :: FS Both FPU Active */ +#define cflgt3__l3_3__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set L3_3 :: VS Threads Dispatched */ +#define cflgt3__l3_3__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set L3_3 :: FS Threads Dispatched */ +#define cflgt3__l3_3__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set L3_3 :: Slice0 L3 Bank3 Stalled */ +#define cflgt3__l3_3__l30_bank3_stalled__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set L3_3 :: Shader Barrier Messages */ +#define cflgt3__l3_3__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set L3_3 :: Sampler Texels */ +#define cflgt3__l3_3__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set L3_3 :: Pixels Failing Tests */ +#define cflgt3__l3_3__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set L3_3 :: GPU Time Elapsed */ +#define cflgt3__l3_3__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set L3_3 :: AVG GPU Core Frequency */ +#define cflgt3__l3_3__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set L3_3 :: AVG GPU Core Frequency */ +#define cflgt3__l3_3__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set L3_3 :: Sampler Texels Misses */ +#define cflgt3__l3_3__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set L3_3 :: CS Threads Dispatched */ +#define cflgt3__l3_3__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set L3_3 :: SLM Bytes Read */ +#define cflgt3__l3_3__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set L3_3 :: PS FPU1 Pipe Active */ +#define cflgt3__l3_3__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set L3_3 :: Slice0 L3 Bank3 Active */ +#define cflgt3__l3_3__l30_bank3_active__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set L3_3 :: PS Send Pipeline Active */ +#define cflgt3__l3_3__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set L3_3 :: VS FPU0 Pipe Active */ +#define cflgt3__l3_3__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set L3_3 :: GPU Busy */ +#define cflgt3__l3_3__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set L3_3 :: Rasterized Pixels */ +#define cflgt3__l3_3__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set L3_3 :: PS FPU0 Pipe Active */ +#define cflgt3__l3_3__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set L3_3 :: DS Threads Dispatched */ +#define cflgt3__l3_3__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set L3_3 :: Samples Written */ +#define cflgt3__l3_3__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set L3_3 :: EU Stall */ +#define cflgt3__l3_3__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set L3_3 :: Samples Blended */ +#define cflgt3__l3_3__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set L3_3 :: Early Depth Test Fails */ +#define cflgt3__l3_3__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set L3_3 :: Shader Memory Accesses */ +#define cflgt3__l3_3__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set L3_3 :: HS Threads Dispatched */ +#define cflgt3__l3_3__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set L3_3 :: SLM Bytes Written */ +#define cflgt3__l3_3__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set L3_3 :: L3 Shader Throughput */ +#define cflgt3__l3_3__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set L3_3 :: Samples Killed in FS */ +#define cflgt3__l3_3__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set L3_3 :: Shader Atomic Memory Accesses */ +#define cflgt3__l3_3__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */ +#define cflgt3__rasterizer_and_pixel_backend__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set RasterizerAndPixelBackend :: EU Active */ +#define cflgt3__rasterizer_and_pixel_backend__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set RasterizerAndPixelBackend :: EU Both FPU Pipes Active */ +#define cflgt3__rasterizer_and_pixel_backend__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set RasterizerAndPixelBackend :: VS Send Pipe Active */ +#define cflgt3__rasterizer_and_pixel_backend__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set RasterizerAndPixelBackend :: VS FPU1 Pipe Active */ +#define cflgt3__rasterizer_and_pixel_backend__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */ +#define cflgt3__rasterizer_and_pixel_backend__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */ +#define cflgt3__rasterizer_and_pixel_backend__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set RasterizerAndPixelBackend :: FS Both FPU Active */ +#define cflgt3__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */ +#define cflgt3__rasterizer_and_pixel_backend__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */ +#define cflgt3__rasterizer_and_pixel_backend__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Pixel Values Ready */ +#define cflgt3__rasterizer_and_pixel_backend__pixel_values0_ready__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */ +#define cflgt3__rasterizer_and_pixel_backend__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set RasterizerAndPixelBackend :: Sampler Texels */ +#define cflgt3__rasterizer_and_pixel_backend__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */ +#define cflgt3__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */ +#define cflgt3__rasterizer_and_pixel_backend__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ +#define cflgt3__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ +#define cflgt3__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */ +#define cflgt3__rasterizer_and_pixel_backend__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */ +#define cflgt3__rasterizer_and_pixel_backend__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */ +#define cflgt3__rasterizer_and_pixel_backend__rasterizer0_input_available__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Post-EarlyZ Pixel Data Ready */ +#define cflgt3__rasterizer_and_pixel_backend__pixel_data0_ready__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */ +#define cflgt3__rasterizer_and_pixel_backend__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set RasterizerAndPixelBackend :: PS FPU1 Pipe Active */ +#define cflgt3__rasterizer_and_pixel_backend__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set RasterizerAndPixelBackend :: PS Send Pipeline Active */ +#define cflgt3__rasterizer_and_pixel_backend__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set RasterizerAndPixelBackend :: VS FPU0 Pipe Active */ +#define cflgt3__rasterizer_and_pixel_backend__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set RasterizerAndPixelBackend :: GPU Busy */ +#define cflgt3__rasterizer_and_pixel_backend__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */ +#define cflgt3__rasterizer_and_pixel_backend__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set RasterizerAndPixelBackend :: PS FPU0 Pipe Active */ +#define cflgt3__rasterizer_and_pixel_backend__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */ +#define cflgt3__rasterizer_and_pixel_backend__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set RasterizerAndPixelBackend :: Samples Written */ +#define cflgt3__rasterizer_and_pixel_backend__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set RasterizerAndPixelBackend :: EU Stall */ +#define cflgt3__rasterizer_and_pixel_backend__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */ +#define cflgt3__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set RasterizerAndPixelBackend :: Samples Blended */ +#define cflgt3__rasterizer_and_pixel_backend__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */ +#define cflgt3__rasterizer_and_pixel_backend__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */ +#define cflgt3__rasterizer_and_pixel_backend__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */ +#define cflgt3__rasterizer_and_pixel_backend__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */ +#define cflgt3__rasterizer_and_pixel_backend__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */ +#define cflgt3__rasterizer_and_pixel_backend__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */ +#define cflgt3__rasterizer_and_pixel_backend__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 PS Output Available */ +#define cflgt3__rasterizer_and_pixel_backend__ps_output0_available__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */ +#define cflgt3__rasterizer_and_pixel_backend__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set Sampler :: GPU Core Clocks */ +#define cflgt3__sampler__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set Sampler :: EU Active */ +#define cflgt3__sampler__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set Sampler :: Slice0 Subslice2 Input Available */ +#define cflgt3__sampler__sampler02_input_available__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set Sampler :: EU Both FPU Pipes Active */ +#define cflgt3__sampler__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set Sampler :: VS Send Pipe Active */ +#define cflgt3__sampler__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set Sampler :: Slice0 Subslice0 Input Available */ +#define cflgt3__sampler__sampler00_input_available__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Metric set Sampler :: VS FPU1 Pipe Active */ +#define cflgt3__sampler__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set Sampler :: GS Threads Dispatched */ +#define cflgt3__sampler__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set Sampler :: Early Hi-Depth Test Fails */ +#define cflgt3__sampler__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set Sampler :: FS Both FPU Active */ +#define cflgt3__sampler__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set Sampler :: VS Threads Dispatched */ +#define cflgt3__sampler__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set Sampler :: Slice0 Subslice2 Sampler Output Ready */ +#define cflgt3__sampler__sampler02_output_ready__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set Sampler :: FS Threads Dispatched */ +#define cflgt3__sampler__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set Sampler :: Shader Barrier Messages */ +#define cflgt3__sampler__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set Sampler :: Slice0 Subslice1 Input Available */ +#define cflgt3__sampler__sampler01_input_available__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set Sampler :: Sampler Texels */ +#define cflgt3__sampler__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set Sampler :: Pixels Failing Tests */ +#define cflgt3__sampler__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set Sampler :: GPU Time Elapsed */ +#define cflgt3__sampler__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set Sampler :: AVG GPU Core Frequency */ +#define cflgt3__sampler__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set Sampler :: AVG GPU Core Frequency */ +#define cflgt3__sampler__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set Sampler :: Sampler Texels Misses */ +#define cflgt3__sampler__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set Sampler :: CS Threads Dispatched */ +#define cflgt3__sampler__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set Sampler :: SLM Bytes Read */ +#define cflgt3__sampler__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set Sampler :: PS FPU1 Pipe Active */ +#define cflgt3__sampler__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set Sampler :: PS Send Pipeline Active */ +#define cflgt3__sampler__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set Sampler :: VS FPU0 Pipe Active */ +#define cflgt3__sampler__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set Sampler :: GPU Busy */ +#define cflgt3__sampler__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set Sampler :: Rasterized Pixels */ +#define cflgt3__sampler__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set Sampler :: PS FPU0 Pipe Active */ +#define cflgt3__sampler__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set Sampler :: DS Threads Dispatched */ +#define cflgt3__sampler__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set Sampler :: Samples Written */ +#define cflgt3__sampler__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set Sampler :: EU Stall */ +#define cflgt3__sampler__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set Sampler :: Samples Blended */ +#define cflgt3__sampler__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set Sampler :: Early Depth Test Fails */ +#define cflgt3__sampler__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set Sampler :: Slice0 Subslice0 Sampler Output Ready */ +#define cflgt3__sampler__sampler00_output_ready__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set Sampler :: Slice0 Subslice1 Sampler Output Ready */ +#define cflgt3__sampler__sampler01_output_ready__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set Sampler :: Shader Memory Accesses */ +#define cflgt3__sampler__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set Sampler :: HS Threads Dispatched */ +#define cflgt3__sampler__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set Sampler :: SLM Bytes Written */ +#define cflgt3__sampler__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set Sampler :: L3 Shader Throughput */ +#define cflgt3__sampler__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set Sampler :: Samples Killed in FS */ +#define cflgt3__sampler__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set Sampler :: Shader Atomic Memory Accesses */ +#define cflgt3__sampler__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set TDL_1 :: GPU Core Clocks */ +#define cflgt3__tdl_1__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set TDL_1 :: EU Active */ +#define cflgt3__tdl_1__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set TDL_1 :: EU Both FPU Pipes Active */ +#define cflgt3__tdl_1__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set TDL_1 :: VS Send Pipe Active */ +#define cflgt3__tdl_1__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set TDL_1 :: VS FPU1 Pipe Active */ +#define cflgt3__tdl_1__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set TDL_1 :: GS Threads Dispatched */ +#define cflgt3__tdl_1__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set TDL_1 :: Early Hi-Depth Test Fails */ +#define cflgt3__tdl_1__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set TDL_1 :: FS Both FPU Active */ +#define cflgt3__tdl_1__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set TDL_1 :: VS Threads Dispatched */ +#define cflgt3__tdl_1__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set TDL_1 :: FS Threads Dispatched */ +#define cflgt3__tdl_1__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice2 */ +#define cflgt3__tdl_1__non_ps_thread02_ready_for_dispatch__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Metric set TDL_1 :: Shader Barrier Messages */ +#define cflgt3__tdl_1__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_1 :: Sampler Texels */ +#define cflgt3__tdl_1__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set TDL_1 :: Pixels Failing Tests */ +#define cflgt3__tdl_1__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set TDL_1 :: GPU Time Elapsed */ +#define cflgt3__tdl_1__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set TDL_1 :: AVG GPU Core Frequency */ +#define cflgt3__tdl_1__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set TDL_1 :: AVG GPU Core Frequency */ +#define cflgt3__tdl_1__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set TDL_1 :: Sampler Texels Misses */ +#define cflgt3__tdl_1__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice0 */ +#define cflgt3__tdl_1__non_ps_thread00_ready_for_dispatch__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Metric set TDL_1 :: CS Threads Dispatched */ +#define cflgt3__tdl_1__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set TDL_1 :: SLM Bytes Read */ +#define cflgt3__tdl_1__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set TDL_1 :: PS FPU1 Pipe Active */ +#define cflgt3__tdl_1__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set TDL_1 :: PS Send Pipeline Active */ +#define cflgt3__tdl_1__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set TDL_1 :: VS FPU0 Pipe Active */ +#define cflgt3__tdl_1__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set TDL_1 :: GPU Busy */ +#define cflgt3__tdl_1__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice0 */ +#define cflgt3__tdl_1__ps_thread00_ready_for_dispatch__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set TDL_1 :: Rasterized Pixels */ +#define cflgt3__tdl_1__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set TDL_1 :: PS FPU0 Pipe Active */ +#define cflgt3__tdl_1__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set TDL_1 :: DS Threads Dispatched */ +#define cflgt3__tdl_1__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set TDL_1 :: Samples Written */ +#define cflgt3__tdl_1__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set TDL_1 :: EU Stall */ +#define cflgt3__tdl_1__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set TDL_1 :: Samples Blended */ +#define cflgt3__tdl_1__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set TDL_1 :: Early Depth Test Fails */ +#define cflgt3__tdl_1__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice1 */ +#define cflgt3__tdl_1__ps_thread01_ready_for_dispatch__read \ + bdw__render_pipe_profile__cl_bottleneck__read + +/* Metric set TDL_1 :: Shader Memory Accesses */ +#define cflgt3__tdl_1__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set TDL_1 :: HS Threads Dispatched */ +#define cflgt3__tdl_1__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice2 */ +#define cflgt3__tdl_1__ps_thread02_ready_for_dispatch__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Metric set TDL_1 :: SLM Bytes Written */ +#define cflgt3__tdl_1__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set TDL_1 :: L3 Shader Throughput */ +#define cflgt3__tdl_1__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set TDL_1 :: Samples Killed in FS */ +#define cflgt3__tdl_1__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set TDL_1 :: Shader Atomic Memory Accesses */ +#define cflgt3__tdl_1__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice1 */ +#define cflgt3__tdl_1__non_ps_thread01_ready_for_dispatch__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set TDL_2 :: GPU Core Clocks */ +#define cflgt3__tdl_2__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set TDL_2 :: EU Active */ +#define cflgt3__tdl_2__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set TDL_2 :: EU Both FPU Pipes Active */ +#define cflgt3__tdl_2__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set TDL_2 :: VS Send Pipe Active */ +#define cflgt3__tdl_2__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set TDL_2 :: VS FPU1 Pipe Active */ +#define cflgt3__tdl_2__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set TDL_2 :: GS Threads Dispatched */ +#define cflgt3__tdl_2__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set TDL_2 :: Early Hi-Depth Test Fails */ +#define cflgt3__tdl_2__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set TDL_2 :: FS Both FPU Active */ +#define cflgt3__tdl_2__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set TDL_2 :: VS Threads Dispatched */ +#define cflgt3__tdl_2__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set TDL_2 :: FS Threads Dispatched */ +#define cflgt3__tdl_2__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set TDL_2 :: Shader Barrier Messages */ +#define cflgt3__tdl_2__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_2 :: Sampler Texels */ +#define cflgt3__tdl_2__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set TDL_2 :: Pixels Failing Tests */ +#define cflgt3__tdl_2__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 0 */ +#define cflgt3__tdl_2__thread_header01_ready_port0__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 1 */ +#define cflgt3__tdl_2__thread_header01_ready_port1__read \ + bdw__render_pipe_profile__ds_stall__read + +/* Metric set TDL_2 :: GPU Time Elapsed */ +#define cflgt3__tdl_2__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set TDL_2 :: AVG GPU Core Frequency */ +#define cflgt3__tdl_2__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set TDL_2 :: AVG GPU Core Frequency */ +#define cflgt3__tdl_2__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set TDL_2 :: Sampler Texels Misses */ +#define cflgt3__tdl_2__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set TDL_2 :: CS Threads Dispatched */ +#define cflgt3__tdl_2__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set TDL_2 :: SLM Bytes Read */ +#define cflgt3__tdl_2__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set TDL_2 :: PS FPU1 Pipe Active */ +#define cflgt3__tdl_2__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set TDL_2 :: PS Send Pipeline Active */ +#define cflgt3__tdl_2__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set TDL_2 :: VS FPU0 Pipe Active */ +#define cflgt3__tdl_2__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set TDL_2 :: GPU Busy */ +#define cflgt3__tdl_2__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 1 */ +#define cflgt3__tdl_2__thread_header02_ready_port1__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 0 */ +#define cflgt3__tdl_2__thread_header02_ready_port0__read \ + bdw__render_pipe_profile__so_stall__read + +/* Metric set TDL_2 :: Rasterized Pixels */ +#define cflgt3__tdl_2__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set TDL_2 :: PS FPU0 Pipe Active */ +#define cflgt3__tdl_2__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set TDL_2 :: DS Threads Dispatched */ +#define cflgt3__tdl_2__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set TDL_2 :: Samples Written */ +#define cflgt3__tdl_2__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set TDL_2 :: EU Stall */ +#define cflgt3__tdl_2__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set TDL_2 :: Samples Blended */ +#define cflgt3__tdl_2__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set TDL_2 :: Early Depth Test Fails */ +#define cflgt3__tdl_2__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_2 :: Shader Memory Accesses */ +#define cflgt3__tdl_2__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set TDL_2 :: HS Threads Dispatched */ +#define cflgt3__tdl_2__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set TDL_2 :: SLM Bytes Written */ +#define cflgt3__tdl_2__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set TDL_2 :: L3 Shader Throughput */ +#define cflgt3__tdl_2__l3_shader_throughput__read \ + bdw__hdc_and_sf__l3_shader_throughput__read + +/* Metric set TDL_2 :: Samples Killed in FS */ +#define cflgt3__tdl_2__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 0 */ +#define cflgt3__tdl_2__thread_header00_ready_port0__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set TDL_2 :: Shader Atomic Memory Accesses */ +#define cflgt3__tdl_2__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 1 */ +#define cflgt3__tdl_2__thread_header00_ready_port1__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Compute Metrics Extra Gen9 :: GPU Core Clocks */ +#define cflgt3__compute_extra__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Extra Gen9 :: EU FPU1 Pipe Active */ +#define cflgt3__compute_extra__fpu1_active__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics Extra Gen9 :: GPU Time Elapsed */ +#define cflgt3__compute_extra__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics Extra Gen9 :: AVG GPU Core Frequency */ +#define cflgt3__compute_extra__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics Extra Gen9 :: AVG GPU Core Frequency */ +#define cflgt3__compute_extra__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics Extra Gen9 :: EU FPU1 Pipe Active including Ext Math */ +#define cflgt3__compute_extra__fpu1_active_adjusted__read \ + bdw__compute_extra__fpu1_active_adjusted__read + +/* Media Vme Pipe Gen9 :: GPU Core Clocks */ +#define cflgt3__vme_pipe__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Media Vme Pipe Gen9 :: EU Active */ +#define cflgt3__vme_pipe__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Media Vme Pipe Gen9 :: EU Both FPU Pipes Active */ +#define cflgt3__vme_pipe__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Media Vme Pipe Gen9 :: GPU Time Elapsed */ +#define cflgt3__vme_pipe__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Media Vme Pipe Gen9 :: AVG GPU Core Frequency */ +#define cflgt3__vme_pipe__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Media Vme Pipe Gen9 :: AVG GPU Core Frequency */ +#define cflgt3__vme_pipe__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Media Vme Pipe Gen9 :: CS Threads Dispatched */ +#define cflgt3__vme_pipe__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Media Vme Pipe Gen9 :: EU Thread Occupancy */ +#define cflgt3__vme_pipe__eu_thread_occupancy__read \ + bdw__vme_pipe__eu_thread_occupancy__read + +/* Media Vme Pipe Gen9 :: EU Stall */ +#define cflgt3__vme_pipe__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Media Vme Pipe Gen9 :: VME Busy */ +#define cflgt3__vme_pipe__vme_busy__read \ + bdw__vme_pipe__vme_busy__read + +/* Media Vme Pipe Gen9 :: GPU Busy */ +#define cflgt3__vme_pipe__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Gpu Rings Busyness :: GPU Core Clocks */ +#define cflgt3__gpu_busyness__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Gpu Rings Busyness :: Vebox Ring Busy */ +#define cflgt3__gpu_busyness__vebox_busy__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Gpu Rings Busyness :: GPU Time Elapsed */ +#define cflgt3__gpu_busyness__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Gpu Rings Busyness :: AVG GPU Core Frequency */ +#define cflgt3__gpu_busyness__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Gpu Rings Busyness :: AVG GPU Core Frequency */ +#define cflgt3__gpu_busyness__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Gpu Rings Busyness :: Render Ring Busy */ +#define cflgt3__gpu_busyness__render_busy__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Gpu Rings Busyness :: Vdbox0 Ring Busy */ +#define cflgt3__gpu_busyness__vdbox0_busy__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Gpu Rings Busyness :: Blitter Ring Busy */ +#define cflgt3__gpu_busyness__blitter_busy__read \ + bdw__render_pipe_profile__so_stall__read + +/* Gpu Rings Busyness :: AnyRingBusy */ +#define cflgt3__gpu_busyness__any_ring_busy__read \ + bdw__render_basic__sampler0_busy__read + +/* Gpu Rings Busyness :: Vdbox1 Ring Busy */ +#define cflgt3__gpu_busyness__vdbox1_busy__read \ + bdw__render_pipe_profile__sf_stall__read + +/* MDAPI testing set Gen9 :: TestCounter7 */ +#define cflgt3__test_oa__counter7__read \ + hsw__compute_extended__gpu_clocks__read + +/* MDAPI testing set Gen9 :: GPU Time Elapsed */ +#define cflgt3__test_oa__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* MDAPI testing set Gen9 :: GPU Core Clocks */ +#define cflgt3__test_oa__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* MDAPI testing set Gen9 :: AVG GPU Core Frequency */ +#define cflgt3__test_oa__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* MDAPI testing set Gen9 :: AVG GPU Core Frequency */ +#define cflgt3__test_oa__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* MDAPI testing set Gen9 :: TestCounter8 */ +#define cflgt3__test_oa__counter8__read \ + hsw__memory_reads__gpu_core_clocks__read + +/* MDAPI testing set Gen9 :: TestCounter4 */ +#define cflgt3__test_oa__counter4__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* MDAPI testing set Gen9 :: TestCounter5 */ +#define cflgt3__test_oa__counter5__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* MDAPI testing set Gen9 :: TestCounter6 */ +#define cflgt3__test_oa__counter6__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* MDAPI testing set Gen9 :: TestCounter3 */ +#define cflgt3__test_oa__counter3__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* MDAPI testing set Gen9 :: TestCounter0 */ +#define cflgt3__test_oa__counter0__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* MDAPI testing set Gen9 :: TestCounter1 */ +#define cflgt3__test_oa__counter1__read \ + hsw__compute_extended__eu_untyped_writes0__read + +/* MDAPI testing set Gen9 :: TestCounter2 */ +#define cflgt3__test_oa__counter2__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Render Metrics Basic Gen10 :: GPU Core Clocks */ +#define cnl__render_basic__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Render Metrics Basic Gen10 :: EU Active */ +#define cnl__render_basic__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Render Metrics Basic Gen10 :: L3 Misses */ +static uint64_t +cnl__render_basic__l3_misses__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 2 READ C 3 READ UADD */ + uint64_t tmp0 = accumulator[query->c_offset + 2]; + uint64_t tmp1 = accumulator[query->c_offset + 3]; + uint64_t tmp2 = tmp0 + tmp1; + + return tmp2; +} + +/* Render Metrics Basic Gen10 :: GTI L3 Throughput */ +#define cnl__render_basic__gti_l3_throughput__read \ + bdw__render_basic__gti_rcc_throughput__read + +/* Render Metrics Basic Gen10 :: EU Both FPU Pipes Active */ +#define cnl__render_basic__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Render Metrics Basic Gen10 :: Sampler Cache Misses */ +static uint64_t +cnl__render_basic__sampler_l1_misses__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $SliceMask 1 AND B 4 READ UMUL $SliceMask 1 >> 1 AND B 5 READ UMUL UADD 8 UMUL */ + uint64_t tmp0 = brw->perfquery.sys_vars.slice_mask & 1; + uint64_t tmp1 = accumulator[query->b_offset + 4]; + uint64_t tmp2 = tmp0 * tmp1; + uint64_t tmp3 = brw->perfquery.sys_vars.slice_mask >> 1; + uint64_t tmp4 = tmp3 & 1; + uint64_t tmp5 = accumulator[query->b_offset + 5]; + uint64_t tmp6 = tmp4 * tmp5; + uint64_t tmp7 = tmp2 + tmp6; + uint64_t tmp8 = tmp7 * 8; + + return tmp8; +} + +/* Render Metrics Basic Gen10 :: VS Send Pipe Active */ +#define cnl__render_basic__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Render Metrics Basic Gen10 :: VS FPU1 Pipe Active */ +#define cnl__render_basic__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Render Metrics Basic Gen10 :: GS Threads Dispatched */ +#define cnl__render_basic__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Render Metrics Basic Gen10 :: L3 Sampler Throughput */ +static uint64_t +cnl__render_basic__l3_sampler_throughput__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: 64 $SamplerL1Misses UMUL */ + uint64_t tmp0 = 64 * cnl__render_basic__sampler_l1_misses__read(brw, query, accumulator); + + return tmp0; +} + +/* Render Metrics Basic Gen10 :: Early Hi-Depth Test Fails */ +#define cnl__render_basic__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Render Metrics Basic Gen10 :: FS Both FPU Active */ +#define cnl__render_basic__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Render Metrics Basic Gen10 :: VS Threads Dispatched */ +#define cnl__render_basic__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Render Metrics Basic Gen10 :: FS Threads Dispatched */ +#define cnl__render_basic__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Render Metrics Basic Gen10 :: Sampler00 Busy */ +#define cnl__render_basic__sampler00_busy__read \ + bdw__render_basic__sampler0_busy__read + +/* Render Metrics Basic Gen10 :: Sampler10 Busy */ +#define cnl__render_basic__sampler10_busy__read \ + bdw__render_basic__sampler1_busy__read + +/* Render Metrics Basic Gen10 :: Samplers Busy */ +static float +cnl__render_basic__samplers_busy__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $SubsliceMask 1 AND $Sampler00Busy FMUL $SubsliceMask 3 >> 1 AND $Sampler10Busy FMUL FADD $SubsliceMask 1 AND $SubsliceMask 3 >> 1 AND FADD FDIV */ + uint64_t tmp0 = brw->perfquery.sys_vars.subslice_mask & 1; + double tmp1 = tmp0 * cnl__render_basic__sampler00_busy__read(brw, query, accumulator); + uint64_t tmp2 = brw->perfquery.sys_vars.subslice_mask >> 3; + uint64_t tmp3 = tmp2 & 1; + double tmp4 = tmp3 * cnl__render_basic__sampler10_busy__read(brw, query, accumulator); + double tmp5 = tmp1 + tmp4; + uint64_t tmp6 = brw->perfquery.sys_vars.subslice_mask & 1; + uint64_t tmp7 = brw->perfquery.sys_vars.subslice_mask >> 3; + uint64_t tmp8 = tmp7 & 1; + double tmp9 = tmp6 + tmp8; + double tmp10 = tmp5; + double tmp11 = tmp9; + double tmp12 = tmp11 ? tmp10 / tmp11 : 0; + + return tmp12; +} + +/* Render Metrics Basic Gen10 :: GTI Fixed Pipe Throughput */ +#define cnl__render_basic__gti_vf_throughput__read \ + bdw__compute_l3_cache__gti_l3_throughput__read + +/* Render Metrics Basic Gen10 :: Shader Barrier Messages */ +#define cnl__render_basic__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Render Metrics Basic Gen10 :: Sampler Texels */ +#define cnl__render_basic__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Render Metrics Basic Gen10 :: Pixels Failing Tests */ +#define cnl__render_basic__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Render Metrics Basic Gen10 :: GPU Time Elapsed */ +#define cnl__render_basic__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Render Metrics Basic Gen10 :: AVG GPU Core Frequency */ +#define cnl__render_basic__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Render Metrics Basic Gen10 :: AVG GPU Core Frequency */ +#define cnl__render_basic__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Render Metrics Basic Gen10 :: Sampler Texels Misses */ +#define cnl__render_basic__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Render Metrics Basic Gen10 :: CS Threads Dispatched */ +#define cnl__render_basic__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Render Metrics Basic Gen10 :: Shader Memory Accesses */ +#define cnl__render_basic__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Render Metrics Basic Gen10 :: L3 Lookup Accesses w/o IC */ +static uint64_t +cnl__render_basic__l3_lookups__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $SamplerL1Misses $ShaderMemoryAccesses UADD */ + uint64_t tmp0 = cnl__render_basic__sampler_l1_misses__read(brw, query, accumulator) + cnl__render_basic__shader_memory_accesses__read(brw, query, accumulator); + + return tmp0; +} + +/* Render Metrics Basic Gen10 :: Sampler00 Bottleneck */ +#define cnl__render_basic__sampler00_bottleneck__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Render Metrics Basic Gen10 :: SLM Bytes Read */ +#define cnl__render_basic__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Render Metrics Basic Gen10 :: GTI Read Throughput */ +static uint64_t +cnl__render_basic__gti_read_throughput__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: 64 C 6 READ UMUL */ + uint64_t tmp0 = accumulator[query->c_offset + 6]; + uint64_t tmp1 = 64 * tmp0; + + return tmp1; +} + +/* Render Metrics Basic Gen10 :: PS FPU1 Pipe Active */ +#define cnl__render_basic__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Render Metrics Basic Gen10 :: PS Send Pipeline Active */ +#define cnl__render_basic__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Render Metrics Basic Gen10 :: Rasterized Pixels */ +#define cnl__render_basic__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Render Metrics Basic Gen10 :: GPU Busy */ +#define cnl__render_basic__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Render Metrics Basic Gen10 :: GTI Depth Throughput */ +static uint64_t +cnl__render_basic__gti_depth_throughput__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: 128 B 6 READ UMUL */ + uint64_t tmp0 = accumulator[query->b_offset + 6]; + uint64_t tmp1 = 128 * tmp0; + + return tmp1; +} + +/* Render Metrics Basic Gen10 :: VS FPU0 Pipe Active */ +#define cnl__render_basic__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Render Metrics Basic Gen10 :: PS FPU0 Pipe Active */ +#define cnl__render_basic__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Render Metrics Basic Gen10 :: DS Threads Dispatched */ +#define cnl__render_basic__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Render Metrics Basic Gen10 :: Samples Written */ +#define cnl__render_basic__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Render Metrics Basic Gen10 :: EU Stall */ +#define cnl__render_basic__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Render Metrics Basic Gen10 :: Samples Blended */ +#define cnl__render_basic__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Render Metrics Basic Gen10 :: Early Depth Test Fails */ +#define cnl__render_basic__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Render Metrics Basic Gen10 :: Sampler10 Bottleneck */ +#define cnl__render_basic__sampler10_bottleneck__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Render Metrics Basic Gen10 :: Samplers Bottleneck */ +static float +cnl__render_basic__sampler_bottleneck__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $SubsliceMask 1 AND $Sampler00Bottleneck FMUL $SubsliceMask 3 >> 1 AND $Sampler10Bottleneck FMUL FADD $SubsliceMask 1 AND $SubsliceMask 3 >> 1 AND FADD FDIV */ + uint64_t tmp0 = brw->perfquery.sys_vars.subslice_mask & 1; + double tmp1 = tmp0 * cnl__render_basic__sampler00_bottleneck__read(brw, query, accumulator); + uint64_t tmp2 = brw->perfquery.sys_vars.subslice_mask >> 3; + uint64_t tmp3 = tmp2 & 1; + double tmp4 = tmp3 * cnl__render_basic__sampler10_bottleneck__read(brw, query, accumulator); + double tmp5 = tmp1 + tmp4; + uint64_t tmp6 = brw->perfquery.sys_vars.subslice_mask & 1; + uint64_t tmp7 = brw->perfquery.sys_vars.subslice_mask >> 3; + uint64_t tmp8 = tmp7 & 1; + double tmp9 = tmp6 + tmp8; + double tmp10 = tmp5; + double tmp11 = tmp9; + double tmp12 = tmp11 ? tmp10 / tmp11 : 0; + + return tmp12; +} + +/* Render Metrics Basic Gen10 :: GTI RCC Throughput */ +static uint64_t +cnl__render_basic__gti_rcc_throughput__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 0 READ C 1 READ UADD 128 UMUL */ + uint64_t tmp0 = accumulator[query->c_offset + 0]; + uint64_t tmp1 = accumulator[query->c_offset + 1]; + uint64_t tmp2 = tmp0 + tmp1; + uint64_t tmp3 = tmp2 * 128; + + return tmp3; +} + +/* Render Metrics Basic Gen10 :: HS Threads Dispatched */ +#define cnl__render_basic__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Render Metrics Basic Gen10 :: GTI Write Throughput */ +static uint64_t +cnl__render_basic__gti_write_throughput__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: 64 C 7 READ UMUL */ + uint64_t tmp0 = accumulator[query->c_offset + 7]; + uint64_t tmp1 = 64 * tmp0; + + return tmp1; +} + +/* Render Metrics Basic Gen10 :: L3 Shader Throughput */ +static uint64_t +cnl__render_basic__l3_shader_throughput__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 30 READ A 31 READ UADD A 32 READ UADD 64 UMUL */ + uint64_t tmp0 = accumulator[query->a_offset + 30]; + uint64_t tmp1 = accumulator[query->a_offset + 31]; + uint64_t tmp2 = tmp0 + tmp1; + uint64_t tmp3 = accumulator[query->a_offset + 32]; + uint64_t tmp4 = tmp2 + tmp3; + uint64_t tmp5 = tmp4 * 64; + + return tmp5; +} + +/* Render Metrics Basic Gen10 :: Samples Killed in FS */ +#define cnl__render_basic__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Render Metrics Basic Gen10 :: SLM Bytes Written */ +#define cnl__render_basic__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Render Metrics Basic Gen10 :: Shader Atomic Memory Accesses */ +#define cnl__render_basic__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Basic Gen10 :: GPU Core Clocks */ +#define cnl__compute_basic__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Basic Gen10 :: EU Active */ +#define cnl__compute_basic__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Compute Metrics Basic Gen10 :: Untyped Bytes Read */ +static uint64_t +cnl__compute_basic__untyped_bytes_read__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $EuSubslicesTotalCount $SubsliceMask 1 AND C 2 READ FMUL $SubsliceMask 3 >> 1 AND C 3 READ FMUL FADD FMUL $SubsliceMask 1 AND $SubsliceMask 3 >> 1 AND FADD FDIV 64 UMUL */ + uint64_t tmp0 = brw->perfquery.sys_vars.subslice_mask & 1; + uint64_t tmp1 = accumulator[query->c_offset + 2]; + double tmp2 = tmp0 * tmp1; + uint64_t tmp3 = brw->perfquery.sys_vars.subslice_mask >> 3; + uint64_t tmp4 = tmp3 & 1; + uint64_t tmp5 = accumulator[query->c_offset + 3]; + double tmp6 = tmp4 * tmp5; + double tmp7 = tmp2 + tmp6; + double tmp8 = brw->perfquery.sys_vars.n_eu_sub_slices * tmp7; + uint64_t tmp9 = brw->perfquery.sys_vars.subslice_mask & 1; + uint64_t tmp10 = brw->perfquery.sys_vars.subslice_mask >> 3; + uint64_t tmp11 = tmp10 & 1; + double tmp12 = tmp9 + tmp11; + double tmp13 = tmp8; + double tmp14 = tmp12; + double tmp15 = tmp14 ? tmp13 / tmp14 : 0; + uint64_t tmp16 = tmp15 * 64; + + return tmp16; +} + +/* Compute Metrics Basic Gen10 :: EU Both FPU Pipes Active */ +#define cnl__compute_basic__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Compute Metrics Basic Gen10 :: Typed Bytes Written */ +static uint64_t +cnl__compute_basic__typed_bytes_written__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $SubsliceMask 1 AND B 5 READ UMUL $SubsliceMask 1 >> 1 AND B 6 READ UMUL UADD $SubsliceMask 2 >> 1 AND B 7 READ UMUL UADD $SubsliceMask 3 >> 1 AND C 0 READ UMUL UADD $SubsliceMask 4 >> 1 AND C 1 READ UMUL UADD 64 UMUL */ + uint64_t tmp0 = brw->perfquery.sys_vars.subslice_mask & 1; + uint64_t tmp1 = accumulator[query->b_offset + 5]; + uint64_t tmp2 = tmp0 * tmp1; + uint64_t tmp3 = brw->perfquery.sys_vars.subslice_mask >> 1; + uint64_t tmp4 = tmp3 & 1; + uint64_t tmp5 = accumulator[query->b_offset + 6]; + uint64_t tmp6 = tmp4 * tmp5; + uint64_t tmp7 = tmp2 + tmp6; + uint64_t tmp8 = brw->perfquery.sys_vars.subslice_mask >> 2; + uint64_t tmp9 = tmp8 & 1; + uint64_t tmp10 = accumulator[query->b_offset + 7]; + uint64_t tmp11 = tmp9 * tmp10; + uint64_t tmp12 = tmp7 + tmp11; + uint64_t tmp13 = brw->perfquery.sys_vars.subslice_mask >> 3; + uint64_t tmp14 = tmp13 & 1; + uint64_t tmp15 = accumulator[query->c_offset + 0]; + uint64_t tmp16 = tmp14 * tmp15; + uint64_t tmp17 = tmp12 + tmp16; + uint64_t tmp18 = brw->perfquery.sys_vars.subslice_mask >> 4; + uint64_t tmp19 = tmp18 & 1; + uint64_t tmp20 = accumulator[query->c_offset + 1]; + uint64_t tmp21 = tmp19 * tmp20; + uint64_t tmp22 = tmp17 + tmp21; + uint64_t tmp23 = tmp22 * 64; + + return tmp23; +} + +/* Compute Metrics Basic Gen10 :: EU AVG IPC Rate */ +static float +cnl__compute_basic__eu_avg_ipc_rate__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: A 9 READ A 10 READ A 11 READ FADD A 9 READ FSUB FDIV 1 FADD */ + uint64_t tmp0 = accumulator[query->a_offset + 9]; + uint64_t tmp1 = accumulator[query->a_offset + 10]; + uint64_t tmp2 = accumulator[query->a_offset + 11]; + double tmp3 = tmp1 + tmp2; + uint64_t tmp4 = accumulator[query->a_offset + 9]; + double tmp5 = tmp3 - tmp4; + double tmp6 = tmp0; + double tmp7 = tmp5; + double tmp8 = tmp7 ? tmp6 / tmp7 : 0; + double tmp9 = tmp8 + 1; + + return tmp9; +} + +/* Compute Metrics Basic Gen10 :: GS Threads Dispatched */ +#define cnl__compute_basic__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Compute Metrics Basic Gen10 :: Early Hi-Depth Test Fails */ +#define cnl__compute_basic__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Compute Metrics Basic Gen10 :: VS Threads Dispatched */ +#define cnl__compute_basic__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Compute Metrics Basic Gen10 :: FS Threads Dispatched */ +#define cnl__compute_basic__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Compute Metrics Basic Gen10 :: EU FPU1 Pipe Active */ +#define cnl__compute_basic__fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Compute Metrics Basic Gen10 :: EU FPU0 Pipe Active */ +#define cnl__compute_basic__fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Compute Metrics Basic Gen10 :: Shader Barrier Messages */ +#define cnl__compute_basic__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Compute Metrics Basic Gen10 :: Sampler Texels */ +#define cnl__compute_basic__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Compute Metrics Basic Gen10 :: Pixels Failing Tests */ +#define cnl__compute_basic__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Compute Metrics Basic Gen10 :: GPU Time Elapsed */ +#define cnl__compute_basic__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics Basic Gen10 :: AVG GPU Core Frequency */ +#define cnl__compute_basic__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics Basic Gen10 :: AVG GPU Core Frequency */ +#define cnl__compute_basic__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics Basic Gen10 :: Sampler Texels Misses */ +#define cnl__compute_basic__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Compute Metrics Basic Gen10 :: CS Threads Dispatched */ +#define cnl__compute_basic__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Compute Metrics Basic Gen10 :: SLM Bytes Read */ +#define cnl__compute_basic__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Compute Metrics Basic Gen10 :: GTI Read Throughput */ +#define cnl__compute_basic__gti_read_throughput__read \ + cnl__render_basic__gti_read_throughput__read + +/* Compute Metrics Basic Gen10 :: Untyped Writes */ +static uint64_t +cnl__compute_basic__untyped_bytes_written__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $EuSubslicesTotalCount $SubsliceMask 1 AND C 4 READ FMUL $SubsliceMask 3 >> 1 AND C 5 READ FMUL FADD FMUL $SubsliceMask 1 AND $SubsliceMask 3 >> 1 AND FADD FDIV 64 UMUL */ + uint64_t tmp0 = brw->perfquery.sys_vars.subslice_mask & 1; + uint64_t tmp1 = accumulator[query->c_offset + 4]; + double tmp2 = tmp0 * tmp1; + uint64_t tmp3 = brw->perfquery.sys_vars.subslice_mask >> 3; + uint64_t tmp4 = tmp3 & 1; + uint64_t tmp5 = accumulator[query->c_offset + 5]; + double tmp6 = tmp4 * tmp5; + double tmp7 = tmp2 + tmp6; + double tmp8 = brw->perfquery.sys_vars.n_eu_sub_slices * tmp7; + uint64_t tmp9 = brw->perfquery.sys_vars.subslice_mask & 1; + uint64_t tmp10 = brw->perfquery.sys_vars.subslice_mask >> 3; + uint64_t tmp11 = tmp10 & 1; + double tmp12 = tmp9 + tmp11; + double tmp13 = tmp8; + double tmp14 = tmp12; + double tmp15 = tmp14 ? tmp13 / tmp14 : 0; + uint64_t tmp16 = tmp15 * 64; + + return tmp16; +} + +/* Compute Metrics Basic Gen10 :: GPU Busy */ +#define cnl__compute_basic__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Compute Metrics Basic Gen10 :: Rasterized Pixels */ +#define cnl__compute_basic__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Compute Metrics Basic Gen10 :: Typed Bytes Read */ +static uint64_t +cnl__compute_basic__typed_bytes_read__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $SubsliceMask 1 AND B 0 READ UMUL $SubsliceMask 1 >> 1 AND B 1 READ UMUL UADD $SubsliceMask 2 >> 1 AND B 2 READ UMUL UADD $SubsliceMask 3 >> 1 AND B 3 READ UMUL UADD $SubsliceMask 4 >> 1 AND B 4 READ UMUL UADD 64 UMUL */ + uint64_t tmp0 = brw->perfquery.sys_vars.subslice_mask & 1; + uint64_t tmp1 = accumulator[query->b_offset + 0]; + uint64_t tmp2 = tmp0 * tmp1; + uint64_t tmp3 = brw->perfquery.sys_vars.subslice_mask >> 1; + uint64_t tmp4 = tmp3 & 1; + uint64_t tmp5 = accumulator[query->b_offset + 1]; + uint64_t tmp6 = tmp4 * tmp5; + uint64_t tmp7 = tmp2 + tmp6; + uint64_t tmp8 = brw->perfquery.sys_vars.subslice_mask >> 2; + uint64_t tmp9 = tmp8 & 1; + uint64_t tmp10 = accumulator[query->b_offset + 2]; + uint64_t tmp11 = tmp9 * tmp10; + uint64_t tmp12 = tmp7 + tmp11; + uint64_t tmp13 = brw->perfquery.sys_vars.subslice_mask >> 3; + uint64_t tmp14 = tmp13 & 1; + uint64_t tmp15 = accumulator[query->b_offset + 3]; + uint64_t tmp16 = tmp14 * tmp15; + uint64_t tmp17 = tmp12 + tmp16; + uint64_t tmp18 = brw->perfquery.sys_vars.subslice_mask >> 4; + uint64_t tmp19 = tmp18 & 1; + uint64_t tmp20 = accumulator[query->b_offset + 4]; + uint64_t tmp21 = tmp19 * tmp20; + uint64_t tmp22 = tmp17 + tmp21; + uint64_t tmp23 = tmp22 * 64; + + return tmp23; +} + +/* Compute Metrics Basic Gen10 :: DS Threads Dispatched */ +#define cnl__compute_basic__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Compute Metrics Basic Gen10 :: EU Thread Occupancy */ +static float +cnl__compute_basic__eu_thread_occupancy__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: 8 A 13 READ FMUL $EuThreadsCount FDIV $EuCoresTotalCount UDIV 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->a_offset + 13]; + double tmp1 = 8 * tmp0; + double tmp2 = tmp1; + double tmp3 = brw->perfquery.sys_vars.eu_threads_count; + double tmp4 = tmp3 ? tmp2 / tmp3 : 0; + uint64_t tmp5 = tmp4; + uint64_t tmp6 = brw->perfquery.sys_vars.n_eus; + uint64_t tmp7 = tmp6 ? tmp5 / tmp6 : 0; + uint64_t tmp8 = tmp7 * 100; + double tmp9 = tmp8; + double tmp10 = cnl__compute_basic__gpu_core_clocks__read(brw, query, accumulator); + double tmp11 = tmp10 ? tmp9 / tmp10 : 0; + + return tmp11; +} + +/* Compute Metrics Basic Gen10 :: EU Stall */ +#define cnl__compute_basic__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics Basic Gen10 :: Samples Blended */ +#define cnl__compute_basic__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Compute Metrics Basic Gen10 :: Early Depth Test Fails */ +#define cnl__compute_basic__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Compute Metrics Basic Gen10 :: Shader Memory Accesses */ +#define cnl__compute_basic__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Compute Metrics Basic Gen10 :: HS Threads Dispatched */ +#define cnl__compute_basic__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Compute Metrics Basic Gen10 :: GTI Write Throughput */ +#define cnl__compute_basic__gti_write_throughput__read \ + cnl__render_basic__gti_write_throughput__read + +/* Compute Metrics Basic Gen10 :: L3 Shader Throughput */ +#define cnl__compute_basic__l3_shader_throughput__read \ + cnl__render_basic__l3_shader_throughput__read + +/* Compute Metrics Basic Gen10 :: Samples Killed in FS */ +#define cnl__compute_basic__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Compute Metrics Basic Gen10 :: SLM Bytes Written */ +#define cnl__compute_basic__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Compute Metrics Basic Gen10 :: Samples Written */ +#define cnl__compute_basic__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Compute Metrics Basic Gen10 :: Shader Atomic Memory Accesses */ +#define cnl__compute_basic__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Basic Gen10 :: EU Send Pipe Active */ +#define cnl__compute_basic__eu_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: GPU Core Clocks */ +#define cnl__render_pipe_profile__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: EU Active */ +#define cnl__render_pipe_profile__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: VS Bottleneck */ +#define cnl__render_pipe_profile__vs_bottleneck__read \ + bdw__render_pipe_profile__so_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: Hi-Depth Bottleneck */ +#define cnl__render_pipe_profile__hi_depth_bottleneck__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: GS Bottleneck */ +#define cnl__render_pipe_profile__gs_bottleneck__read \ + bdw__render_pipe_profile__vf_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: GS Threads Dispatched */ +#define cnl__render_pipe_profile__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: Early Hi-Depth Test Fails */ +#define cnl__render_pipe_profile__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: VS Threads Dispatched */ +#define cnl__render_pipe_profile__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: FS Threads Dispatched */ +#define cnl__render_pipe_profile__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: BC Bottleneck */ +#define cnl__render_pipe_profile__bc_bottleneck__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: HS Stall */ +#define cnl__render_pipe_profile__hs_stall__read \ + bdw__render_basic__sampler1_busy__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: Shader Barrier Messages */ +#define cnl__render_pipe_profile__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: Sampler Texels */ +#define cnl__render_pipe_profile__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: Pixels Failing Tests */ +#define cnl__render_pipe_profile__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: GPU Time Elapsed */ +#define cnl__render_pipe_profile__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: AVG GPU Core Frequency */ +#define cnl__render_pipe_profile__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: AVG GPU Core Frequency */ +#define cnl__render_pipe_profile__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Render Metrics for 3D Pipeline Profile Gen10 :: Sampler Texels Misses */ +#define cnl__render_pipe_profile__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: CS Threads Dispatched */ +#define cnl__render_pipe_profile__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: VF Bottleneck */ +#define cnl__render_pipe_profile__vf_bottleneck__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: SLM Bytes Read */ +#define cnl__render_pipe_profile__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: Strip-Fans Bottleneck */ +#define cnl__render_pipe_profile__sf_bottleneck__read \ + bdw__render_pipe_profile__sf_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: SF Stall */ +#define cnl__render_pipe_profile__sf_stall__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: GPU Busy */ +#define cnl__render_pipe_profile__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: HS Bottleneck */ +#define cnl__render_pipe_profile__hs_bottleneck__read \ + bdw__render_pipe_profile__ds_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: CL Stall */ +#define cnl__render_pipe_profile__cl_stall__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: SO Bottleneck */ +#define cnl__render_pipe_profile__so_bottleneck__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: Rasterized Pixels */ +#define cnl__render_pipe_profile__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: DS Threads Dispatched */ +#define cnl__render_pipe_profile__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: Samples Written */ +#define cnl__render_pipe_profile__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: DS Bottleneck */ +#define cnl__render_pipe_profile__ds_bottleneck__read \ + bdw__render_pipe_profile__hs_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: EU Stall */ +#define cnl__render_pipe_profile__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: Clipper Bottleneck */ +#define cnl__render_pipe_profile__cl_bottleneck__read \ + bdw__render_pipe_profile__early_depth_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: DS Stall */ +#define cnl__render_pipe_profile__ds_stall__read \ + bdw__render_basic__sampler0_busy__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: Early Depth Bottleneck */ +#define cnl__render_pipe_profile__early_depth_bottleneck__read \ + bdw__render_pipe_profile__cl_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: Samples Blended */ +#define cnl__render_pipe_profile__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: Early Depth Test Fails */ +#define cnl__render_pipe_profile__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: Shader Memory Accesses */ +#define cnl__render_pipe_profile__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: HS Threads Dispatched */ +#define cnl__render_pipe_profile__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: L3 Shader Throughput */ +#define cnl__render_pipe_profile__l3_shader_throughput__read \ + cnl__render_basic__l3_shader_throughput__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: Samples Killed in FS */ +#define cnl__render_pipe_profile__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: SLM Bytes Written */ +#define cnl__render_pipe_profile__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: SO Stall */ +#define cnl__render_pipe_profile__so_stall__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Render Metrics for 3D Pipeline Profile Gen10 :: Shader Atomic Memory Accesses */ +#define cnl__render_pipe_profile__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Memory Reads Distribution Gen10 :: GPU Core Clocks */ +#define cnl__memory_reads__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Memory Reads Distribution Gen10 :: EU Active */ +#define cnl__memory_reads__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Memory Reads Distribution Gen10 :: GtiL3Bank0Reads */ +#define cnl__memory_reads__gti_l3_bank0_reads__read \ + hsw__compute_extended__untyped_writes0__read + +/* Memory Reads Distribution Gen10 :: GS Threads Dispatched */ +#define cnl__memory_reads__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Memory Reads Distribution Gen10 :: GtiRingAccesses */ +#define cnl__memory_reads__gti_ring_accesses__read \ + hsw__memory_reads__gpu_core_clocks__read + +/* Memory Reads Distribution Gen10 :: Early Hi-Depth Test Fails */ +#define cnl__memory_reads__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Memory Reads Distribution Gen10 :: VS Threads Dispatched */ +#define cnl__memory_reads__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Memory Reads Distribution Gen10 :: FS Threads Dispatched */ +#define cnl__memory_reads__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Memory Reads Distribution Gen10 :: Shader Barrier Messages */ +#define cnl__memory_reads__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Memory Reads Distribution Gen10 :: GtiRsMemoryReads */ +#define cnl__memory_reads__gti_rs_memory_reads__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Memory Reads Distribution Gen10 :: Sampler Texels */ +#define cnl__memory_reads__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Memory Reads Distribution Gen10 :: Pixels Failing Tests */ +#define cnl__memory_reads__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Memory Reads Distribution Gen10 :: GtiHizMemoryReads */ +#define cnl__memory_reads__gti_hiz_memory_reads__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* Memory Reads Distribution Gen10 :: GPU Time Elapsed */ +#define cnl__memory_reads__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Memory Reads Distribution Gen10 :: AVG GPU Core Frequency */ +#define cnl__memory_reads__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Memory Reads Distribution Gen10 :: AVG GPU Core Frequency */ +#define cnl__memory_reads__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Memory Reads Distribution Gen10 :: Sampler Texels Misses */ +#define cnl__memory_reads__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Memory Reads Distribution Gen10 :: GtiRccMemoryReads */ +#define cnl__memory_reads__gti_rcc_memory_reads__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* Memory Reads Distribution Gen10 :: CS Threads Dispatched */ +#define cnl__memory_reads__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Memory Reads Distribution Gen10 :: SLM Bytes Read */ +#define cnl__memory_reads__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Memory Reads Distribution Gen10 :: GtiL3Bank1Reads */ +#define cnl__memory_reads__gti_l3_bank1_reads__read \ + hsw__render_basic__gpu_core_clocks__read + +/* Memory Reads Distribution Gen10 :: GPU Busy */ +#define cnl__memory_reads__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Memory Reads Distribution Gen10 :: GtiCmdStreamerMemoryReads */ +#define cnl__memory_reads__gti_cmd_streamer_memory_reads__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* Memory Reads Distribution Gen10 :: GtiL3Bank2Reads */ +#define cnl__memory_reads__gti_l3_bank2_reads__read \ + hsw__compute_extended__untyped_reads0__read + +/* Memory Reads Distribution Gen10 :: GtiMemoryReads */ +#define cnl__memory_reads__gti_memory_reads__read \ + hsw__compute_extended__typed_writes0__read + +/* Memory Reads Distribution Gen10 :: Rasterized Pixels */ +#define cnl__memory_reads__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Memory Reads Distribution Gen10 :: GtiRczMemoryReads */ +#define cnl__memory_reads__gti_rcz_memory_reads__read \ + hsw__compute_extended__gpu_clocks__read + +/* Memory Reads Distribution Gen10 :: DS Threads Dispatched */ +#define cnl__memory_reads__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Memory Reads Distribution Gen10 :: Samples Written */ +#define cnl__memory_reads__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Memory Reads Distribution Gen10 :: EU Stall */ +#define cnl__memory_reads__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Memory Reads Distribution Gen10 :: Samples Blended */ +#define cnl__memory_reads__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Memory Reads Distribution Gen10 :: Early Depth Test Fails */ +#define cnl__memory_reads__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Memory Reads Distribution Gen10 :: GtiMscMemoryReads */ +#define cnl__memory_reads__gti_msc_memory_reads__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* Memory Reads Distribution Gen10 :: GtiVfMemoryReads */ +#define cnl__memory_reads__gti_vf_memory_reads__read \ + hsw__compute_extended__eu_untyped_writes0__read + +/* Memory Reads Distribution Gen10 :: GtiStcMemoryReads */ +#define cnl__memory_reads__gti_stc_memory_reads__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* Memory Reads Distribution Gen10 :: Shader Memory Accesses */ +#define cnl__memory_reads__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Memory Reads Distribution Gen10 :: HS Threads Dispatched */ +#define cnl__memory_reads__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Memory Reads Distribution Gen10 :: Samples Killed in FS */ +#define cnl__memory_reads__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Memory Reads Distribution Gen10 :: SLM Bytes Written */ +#define cnl__memory_reads__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Memory Reads Distribution Gen10 :: GtiL3Reads */ +static uint64_t +cnl__memory_reads__gti_l3_reads__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $GtiL3Bank0Reads $GtiL3Bank1Reads UADD $GtiL3Bank2Reads UADD */ + uint64_t tmp0 = cnl__memory_reads__gti_l3_bank0_reads__read(brw, query, accumulator) + cnl__memory_reads__gti_l3_bank1_reads__read(brw, query, accumulator); + uint64_t tmp1 = tmp0 + cnl__memory_reads__gti_l3_bank2_reads__read(brw, query, accumulator); + + return tmp1; +} + +/* Memory Reads Distribution Gen10 :: Shader Atomic Memory Accesses */ +#define cnl__memory_reads__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Memory Writes Distribution Gen10 :: GPU Core Clocks */ +#define cnl__memory_writes__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Memory Writes Distribution Gen10 :: EU Active */ +#define cnl__memory_writes__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Memory Writes Distribution Gen10 :: GtiMemoryWrites */ +#define cnl__memory_writes__gti_memory_writes__read \ + hsw__compute_extended__typed_writes0__read + +/* Memory Writes Distribution Gen10 :: GS Threads Dispatched */ +#define cnl__memory_writes__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Memory Writes Distribution Gen10 :: GtiRingAccesses */ +#define cnl__memory_writes__gti_ring_accesses__read \ + hsw__memory_reads__gpu_core_clocks__read + +/* Memory Writes Distribution Gen10 :: Early Hi-Depth Test Fails */ +#define cnl__memory_writes__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Memory Writes Distribution Gen10 :: VS Threads Dispatched */ +#define cnl__memory_writes__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Memory Writes Distribution Gen10 :: FS Threads Dispatched */ +#define cnl__memory_writes__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Memory Writes Distribution Gen10 :: GtiMscMemoryWrites */ +#define cnl__memory_writes__gti_msc_memory_writes__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* Memory Writes Distribution Gen10 :: Shader Barrier Messages */ +#define cnl__memory_writes__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Memory Writes Distribution Gen10 :: GtiCmdStreamerMemoryWrites */ +#define cnl__memory_writes__gti_cmd_streamer_memory_writes__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* Memory Writes Distribution Gen10 :: Sampler Texels */ +#define cnl__memory_writes__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Memory Writes Distribution Gen10 :: Pixels Failing Tests */ +#define cnl__memory_writes__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Memory Writes Distribution Gen10 :: GtiL3Bank0Writes */ +#define cnl__memory_writes__gti_l3_bank0_writes__read \ + hsw__compute_extended__untyped_writes0__read + +/* Memory Writes Distribution Gen10 :: GtiL3Bank1Writes */ +#define cnl__memory_writes__gti_l3_bank1_writes__read \ + hsw__render_basic__gpu_core_clocks__read + +/* Memory Writes Distribution Gen10 :: GtiL3Bank2Writes */ +#define cnl__memory_writes__gti_l3_bank2_writes__read \ + hsw__compute_extended__untyped_reads0__read + +/* Memory Writes Distribution Gen10 :: GtiL3Writes */ +#define cnl__memory_writes__gti_l3_writes__read \ + cnl__memory_reads__gti_l3_reads__read + +/* Memory Writes Distribution Gen10 :: GPU Time Elapsed */ +#define cnl__memory_writes__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Memory Writes Distribution Gen10 :: AVG GPU Core Frequency */ +#define cnl__memory_writes__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Memory Writes Distribution Gen10 :: AVG GPU Core Frequency */ +#define cnl__memory_writes__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Memory Writes Distribution Gen10 :: Sampler Texels Misses */ +#define cnl__memory_writes__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Memory Writes Distribution Gen10 :: CS Threads Dispatched */ +#define cnl__memory_writes__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Memory Writes Distribution Gen10 :: SLM Bytes Read */ +#define cnl__memory_writes__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Memory Writes Distribution Gen10 :: GtiRccMemoryWrites */ +#define cnl__memory_writes__gti_rcc_memory_writes__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Memory Writes Distribution Gen10 :: GtiSoMemoryWrites */ +#define cnl__memory_writes__gti_so_memory_writes__read \ + hsw__compute_extended__eu_untyped_writes0__read + +/* Memory Writes Distribution Gen10 :: GPU Busy */ +#define cnl__memory_writes__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Memory Writes Distribution Gen10 :: GtiStcMemoryWrites */ +#define cnl__memory_writes__gti_stc_memory_writes__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* Memory Writes Distribution Gen10 :: Rasterized Pixels */ +#define cnl__memory_writes__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Memory Writes Distribution Gen10 :: DS Threads Dispatched */ +#define cnl__memory_writes__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Memory Writes Distribution Gen10 :: Samples Written */ +#define cnl__memory_writes__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Memory Writes Distribution Gen10 :: EU Stall */ +#define cnl__memory_writes__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Memory Writes Distribution Gen10 :: Samples Blended */ +#define cnl__memory_writes__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Memory Writes Distribution Gen10 :: Early Depth Test Fails */ +#define cnl__memory_writes__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Memory Writes Distribution Gen10 :: Shader Memory Accesses */ +#define cnl__memory_writes__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Memory Writes Distribution Gen10 :: HS Threads Dispatched */ +#define cnl__memory_writes__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Memory Writes Distribution Gen10 :: GtiRczMemoryWrites */ +#define cnl__memory_writes__gti_rcz_memory_writes__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* Memory Writes Distribution Gen10 :: L3 Shader Throughput */ +#define cnl__memory_writes__l3_shader_throughput__read \ + cnl__render_basic__l3_shader_throughput__read + +/* Memory Writes Distribution Gen10 :: Samples Killed in FS */ +#define cnl__memory_writes__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Memory Writes Distribution Gen10 :: SLM Bytes Written */ +#define cnl__memory_writes__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Memory Writes Distribution Gen10 :: GtiHizMemoryWrites */ +#define cnl__memory_writes__gti_hiz_memory_writes__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* Memory Writes Distribution Gen10 :: Shader Atomic Memory Accesses */ +#define cnl__memory_writes__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Extended Gen10 :: GPU Core Clocks */ +#define cnl__compute_extended__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Extended Gen10 :: EU Active */ +#define cnl__compute_extended__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Compute Metrics Extended Gen10 :: EU Both FPU Pipes Active */ +#define cnl__compute_extended__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Compute Metrics Extended Gen10 :: EU AVG IPC Rate */ +#define cnl__compute_extended__eu_avg_ipc_rate__read \ + cnl__compute_basic__eu_avg_ipc_rate__read + +/* Compute Metrics Extended Gen10 :: Typed Writes 0 */ +#define cnl__compute_extended__typed_writes0__read \ + hsw__compute_extended__typed_atomics0__read + +/* Compute Metrics Extended Gen10 :: EuTypedAtomics0 */ +#define cnl__compute_extended__eu_typed_atomics0__read \ + hsw__compute_extended__gpu_clocks__read + +/* Compute Metrics Extended Gen10 :: Typed Atomics 0 */ +#define cnl__compute_extended__typed_atomics0__read \ + hsw__memory_reads__gti_memory_reads__read + +/* Compute Metrics Extended Gen10 :: TypedAtomicsPerCacheLine */ +static float +cnl__compute_extended__typed_atomics_per_cache_line__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $EuTypedAtomics0 $TypedAtomics0 FDIV */ + double tmp0 = cnl__compute_extended__eu_typed_atomics0__read(brw, query, accumulator); + double tmp1 = cnl__compute_extended__typed_atomics0__read(brw, query, accumulator); + double tmp2 = tmp1 ? tmp0 / tmp1 : 0; + + return tmp2; +} + +/* Compute Metrics Extended Gen10 :: EuUntypedReads0 */ +#define cnl__compute_extended__eu_untyped_reads0__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* Compute Metrics Extended Gen10 :: Untyped Writes 0 */ +#define cnl__compute_extended__untyped_writes0__read \ + hsw__render_basic__gpu_core_clocks__read + +/* Compute Metrics Extended Gen10 :: EU FPU1 Pipe Active */ +#define cnl__compute_extended__fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Compute Metrics Extended Gen10 :: EU FPU0 Pipe Active */ +#define cnl__compute_extended__fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Compute Metrics Extended Gen10 :: EuUntypedAtomics0 */ +#define cnl__compute_extended__eu_untyped_atomics0__read \ + hsw__compute_extended__eu_typed_reads0__read + +/* Compute Metrics Extended Gen10 :: EuUntypedWrites0 */ +#define cnl__compute_extended__eu_untyped_writes0__read \ + hsw__compute_extended__eu_untyped_writes0__read + +/* Compute Metrics Extended Gen10 :: EuA64UntypedWrites0 */ +#define cnl__compute_extended__eu_a64_untyped_writes0__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* Compute Metrics Extended Gen10 :: UntypedWritesPerCacheLine */ +static float +cnl__compute_extended__untyped_writes_per_cache_line__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $EuUntypedWrites0 $EuA64UntypedWrites0 FADD $UntypedWrites0 FDIV */ + double tmp0 = cnl__compute_extended__eu_untyped_writes0__read(brw, query, accumulator) + cnl__compute_extended__eu_a64_untyped_writes0__read(brw, query, accumulator); + double tmp1 = tmp0; + double tmp2 = cnl__compute_extended__untyped_writes0__read(brw, query, accumulator); + double tmp3 = tmp2 ? tmp1 / tmp2 : 0; + + return tmp3; +} + +/* Compute Metrics Extended Gen10 :: Shader Barrier Messages */ +#define cnl__compute_extended__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Compute Metrics Extended Gen10 :: Sampler Texels */ +#define cnl__compute_extended__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Compute Metrics Extended Gen10 :: GPU Time Elapsed */ +#define cnl__compute_extended__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics Extended Gen10 :: AVG GPU Core Frequency */ +#define cnl__compute_extended__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics Extended Gen10 :: AVG GPU Core Frequency */ +#define cnl__compute_extended__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics Extended Gen10 :: Sampler Texels Misses */ +#define cnl__compute_extended__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Compute Metrics Extended Gen10 :: CS Threads Dispatched */ +#define cnl__compute_extended__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Compute Metrics Extended Gen10 :: SLM Bytes Read */ +#define cnl__compute_extended__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Compute Metrics Extended Gen10 :: EuTypedWrites0 */ +#define cnl__compute_extended__eu_typed_writes0__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* Compute Metrics Extended Gen10 :: TypedWritesPerCacheLine */ +static float +cnl__compute_extended__typed_writes_per_cache_line__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $EuTypedWrites0 $TypedWrites0 FDIV */ + double tmp0 = cnl__compute_extended__eu_typed_writes0__read(brw, query, accumulator); + double tmp1 = cnl__compute_extended__typed_writes0__read(brw, query, accumulator); + double tmp2 = tmp1 ? tmp0 / tmp1 : 0; + + return tmp2; +} + +/* Compute Metrics Extended Gen10 :: Typed Reads 0 */ +#define cnl__compute_extended__typed_reads0__read \ + hsw__compute_extended__untyped_reads0__read + +/* Compute Metrics Extended Gen10 :: Untyped Reads 0 */ +#define cnl__compute_extended__untyped_reads0__read \ + hsw__compute_extended__untyped_writes0__read + +/* Compute Metrics Extended Gen10 :: EuA64UntypedReads0 */ +#define cnl__compute_extended__eu_a64_untyped_reads0__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* Compute Metrics Extended Gen10 :: EU Thread Occupancy */ +#define cnl__compute_extended__eu_thread_occupancy__read \ + cnl__compute_basic__eu_thread_occupancy__read + +/* Compute Metrics Extended Gen10 :: EU Stall */ +#define cnl__compute_extended__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics Extended Gen10 :: EuTypedReads0 */ +#define cnl__compute_extended__eu_typed_reads0__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* Compute Metrics Extended Gen10 :: UntypedReadsPerCacheLine */ +static float +cnl__compute_extended__untyped_reads_per_cache_line__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $EuUntypedReads0 $EuA64UntypedReads0 FADD $UntypedReads0 FDIV */ + double tmp0 = cnl__compute_extended__eu_untyped_reads0__read(brw, query, accumulator) + cnl__compute_extended__eu_a64_untyped_reads0__read(brw, query, accumulator); + double tmp1 = tmp0; + double tmp2 = cnl__compute_extended__untyped_reads0__read(brw, query, accumulator); + double tmp3 = tmp2 ? tmp1 / tmp2 : 0; + + return tmp3; +} + +/* Compute Metrics Extended Gen10 :: Shader Memory Accesses */ +#define cnl__compute_extended__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Compute Metrics Extended Gen10 :: TypedReadsPerCacheLine */ +static float +cnl__compute_extended__typed_reads_per_cache_line__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $EuTypedReads0 $TypedReads0 FDIV */ + double tmp0 = cnl__compute_extended__eu_typed_reads0__read(brw, query, accumulator); + double tmp1 = cnl__compute_extended__typed_reads0__read(brw, query, accumulator); + double tmp2 = tmp1 ? tmp0 / tmp1 : 0; + + return tmp2; +} + +/* Compute Metrics Extended Gen10 :: L3 Shader Throughput */ +#define cnl__compute_extended__l3_shader_throughput__read \ + cnl__render_basic__l3_shader_throughput__read + +/* Compute Metrics Extended Gen10 :: SLM Bytes Written */ +#define cnl__compute_extended__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Compute Metrics Extended Gen10 :: Shader Atomic Memory Accesses */ +#define cnl__compute_extended__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics Extended Gen10 :: EU Send Pipe Active */ +#define cnl__compute_extended__eu_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Compute Metrics L3 Cache Gen10 :: GPU Core Clocks */ +#define cnl__compute_l3_cache__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Compute Metrics L3 Cache Gen10 :: EU Active */ +#define cnl__compute_l3_cache__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Compute Metrics L3 Cache Gen10 :: L3 Misses */ +#define cnl__compute_l3_cache__l3_misses__read \ + cnl__render_basic__l3_misses__read + +/* Compute Metrics L3 Cache Gen10 :: GTI L3 Throughput */ +#define cnl__compute_l3_cache__gti_l3_throughput__read \ + bdw__render_basic__gti_rcc_throughput__read + +/* Compute Metrics L3 Cache Gen10 :: Slice0 L3 Bank0 Accesses */ +static uint64_t +cnl__compute_l3_cache__l3_bank00_accesses__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 0 READ 2 UMUL */ + uint64_t tmp0 = accumulator[query->b_offset + 0]; + uint64_t tmp1 = tmp0 * 2; + + return tmp1; +} + +/* Compute Metrics L3 Cache Gen10 :: Slice0 L3 Bank1 Accesses */ +static uint64_t +cnl__compute_l3_cache__l3_bank01_accesses__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 1 READ 2 UMUL */ + uint64_t tmp0 = accumulator[query->b_offset + 1]; + uint64_t tmp1 = tmp0 * 2; + + return tmp1; +} + +/* Compute Metrics L3 Cache Gen10 :: Slice0 L3 Bank2 Accesses */ +#define cnl__compute_l3_cache__l3_bank02_accesses__read \ + bdw__compute_l3_cache__l3_bank02_accesses__read + +/* Compute Metrics L3 Cache Gen10 :: Slice1 L3 Bank0 Accesses */ +#define cnl__compute_l3_cache__l3_bank10_accesses__read \ + bdw__compute_l3_cache__l3_bank03_accesses__read + +/* Compute Metrics L3 Cache Gen10 :: Slice1 L3 Bank1 Accesses */ +static uint64_t +cnl__compute_l3_cache__l3_bank11_accesses__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 4 READ 2 UMUL */ + uint64_t tmp0 = accumulator[query->b_offset + 4]; + uint64_t tmp1 = tmp0 * 2; + + return tmp1; +} + +/* Compute Metrics L3 Cache Gen10 :: Slice1 L3 Bank2 Accesses */ +static uint64_t +cnl__compute_l3_cache__l3_bank12_accesses__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 5 READ 2 UMUL */ + uint64_t tmp0 = accumulator[query->b_offset + 5]; + uint64_t tmp1 = tmp0 * 2; + + return tmp1; +} + +/* Compute Metrics L3 Cache Gen10 :: L3 Accesses */ +static uint64_t +cnl__compute_l3_cache__l3_accesses__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $L3Bank00Accesses $L3Bank01Accesses UADD $L3Bank02Accesses UADD $L3Bank10Accesses UADD $L3Bank11Accesses UADD $L3Bank12Accesses UADD */ + uint64_t tmp0 = cnl__compute_l3_cache__l3_bank00_accesses__read(brw, query, accumulator) + cnl__compute_l3_cache__l3_bank01_accesses__read(brw, query, accumulator); + uint64_t tmp1 = tmp0 + cnl__compute_l3_cache__l3_bank02_accesses__read(brw, query, accumulator); + uint64_t tmp2 = tmp1 + cnl__compute_l3_cache__l3_bank10_accesses__read(brw, query, accumulator); + uint64_t tmp3 = tmp2 + cnl__compute_l3_cache__l3_bank11_accesses__read(brw, query, accumulator); + uint64_t tmp4 = tmp3 + cnl__compute_l3_cache__l3_bank12_accesses__read(brw, query, accumulator); + + return tmp4; +} + +/* Compute Metrics L3 Cache Gen10 :: EU Both FPU Pipes Active */ +#define cnl__compute_l3_cache__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Compute Metrics L3 Cache Gen10 :: L3 Sampler Throughput */ +static uint64_t +cnl__compute_l3_cache__l3_sampler_throughput__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: 64 $SliceMask 1 AND C 4 READ UMUL $SliceMask 1 >> 1 AND C 5 READ UMUL UADD 8 UMUL UMUL */ + uint64_t tmp0 = brw->perfquery.sys_vars.slice_mask & 1; + uint64_t tmp1 = accumulator[query->c_offset + 4]; + uint64_t tmp2 = tmp0 * tmp1; + uint64_t tmp3 = brw->perfquery.sys_vars.slice_mask >> 1; + uint64_t tmp4 = tmp3 & 1; + uint64_t tmp5 = accumulator[query->c_offset + 5]; + uint64_t tmp6 = tmp4 * tmp5; + uint64_t tmp7 = tmp2 + tmp6; + uint64_t tmp8 = tmp7 * 8; + uint64_t tmp9 = 64 * tmp8; + + return tmp9; +} + +/* Compute Metrics L3 Cache Gen10 :: EU AVG IPC Rate */ +#define cnl__compute_l3_cache__eu_avg_ipc_rate__read \ + cnl__compute_basic__eu_avg_ipc_rate__read + +/* Compute Metrics L3 Cache Gen10 :: EU FPU0 Binary Instruction */ +#define cnl__compute_l3_cache__eu_binary_fpu0_instruction__read \ + bdw__render_basic__ps_send_active__read + +/* Compute Metrics L3 Cache Gen10 :: GS Threads Dispatched */ +#define cnl__compute_l3_cache__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Compute Metrics L3 Cache Gen10 :: Early Hi-Depth Test Fails */ +#define cnl__compute_l3_cache__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Compute Metrics L3 Cache Gen10 :: VS Threads Dispatched */ +#define cnl__compute_l3_cache__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Compute Metrics L3 Cache Gen10 :: FS Threads Dispatched */ +#define cnl__compute_l3_cache__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Compute Metrics L3 Cache Gen10 :: EU FPU0 Hybrid Instruction */ +#define cnl__compute_l3_cache__eu_hybrid_fpu0_instruction__read \ + bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read + +/* Compute Metrics L3 Cache Gen10 :: EU FPU1 Pipe Active */ +#define cnl__compute_l3_cache__fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Compute Metrics L3 Cache Gen10 :: EU FPU0 Pipe Active */ +#define cnl__compute_l3_cache__fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Compute Metrics L3 Cache Gen10 :: Shader Barrier Messages */ +#define cnl__compute_l3_cache__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Compute Metrics L3 Cache Gen10 :: EU FPU0 Move Instruction */ +#define cnl__compute_l3_cache__eu_move_fpu0_instruction__read \ + bdw__compute_l3_cache__eu_move_fpu0_instruction__read + +/* Compute Metrics L3 Cache Gen10 :: Sampler Accesses */ +#define cnl__compute_l3_cache__sampler_accesses__read \ + bdw__render_pipe_profile__sampler_accesses__read + +/* Compute Metrics L3 Cache Gen10 :: Sampler Texels */ +#define cnl__compute_l3_cache__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Compute Metrics L3 Cache Gen10 :: Pixels Failing Tests */ +#define cnl__compute_l3_cache__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Compute Metrics L3 Cache Gen10 :: EU FPU1 Hybrid Instruction */ +#define cnl__compute_l3_cache__eu_hybrid_fpu1_instruction__read \ + bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read + +/* Compute Metrics L3 Cache Gen10 :: GPU Time Elapsed */ +#define cnl__compute_l3_cache__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Compute Metrics L3 Cache Gen10 :: AVG GPU Core Frequency */ +#define cnl__compute_l3_cache__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Compute Metrics L3 Cache Gen10 :: AVG GPU Core Frequency */ +#define cnl__compute_l3_cache__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Compute Metrics L3 Cache Gen10 :: Sampler Texels Misses */ +#define cnl__compute_l3_cache__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Compute Metrics L3 Cache Gen10 :: CS Threads Dispatched */ +#define cnl__compute_l3_cache__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Compute Metrics L3 Cache Gen10 :: L3 Lookup Accesses w/o IC */ +static uint64_t +cnl__compute_l3_cache__l3_lookups__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $SliceMask 1 AND C 4 READ UMUL $SliceMask 1 >> 1 AND C 5 READ UMUL UADD 8 UMUL A 32 READ UADD */ + uint64_t tmp0 = brw->perfquery.sys_vars.slice_mask & 1; + uint64_t tmp1 = accumulator[query->c_offset + 4]; + uint64_t tmp2 = tmp0 * tmp1; + uint64_t tmp3 = brw->perfquery.sys_vars.slice_mask >> 1; + uint64_t tmp4 = tmp3 & 1; + uint64_t tmp5 = accumulator[query->c_offset + 5]; + uint64_t tmp6 = tmp4 * tmp5; + uint64_t tmp7 = tmp2 + tmp6; + uint64_t tmp8 = tmp7 * 8; + uint64_t tmp9 = accumulator[query->a_offset + 32]; + uint64_t tmp10 = tmp8 + tmp9; + + return tmp10; +} + +/* Compute Metrics L3 Cache Gen10 :: SLM Bytes Read */ +#define cnl__compute_l3_cache__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Compute Metrics L3 Cache Gen10 :: GTI Read Throughput */ +#define cnl__compute_l3_cache__gti_read_throughput__read \ + cnl__render_basic__gti_read_throughput__read + +/* Compute Metrics L3 Cache Gen10 :: GPU Busy */ +#define cnl__compute_l3_cache__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Compute Metrics L3 Cache Gen10 :: EU FPU0 Ternary Instruction */ +#define cnl__compute_l3_cache__eu_ternary_fpu0_instruction__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Compute Metrics L3 Cache Gen10 :: Shader Atomic Memory Accesses */ +#define cnl__compute_l3_cache__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Compute Metrics L3 Cache Gen10 :: Rasterized Pixels */ +#define cnl__compute_l3_cache__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Compute Metrics L3 Cache Gen10 :: DS Threads Dispatched */ +#define cnl__compute_l3_cache__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Compute Metrics L3 Cache Gen10 :: Samples Written */ +#define cnl__compute_l3_cache__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Compute Metrics L3 Cache Gen10 :: EU FPU1 Move Instruction */ +#define cnl__compute_l3_cache__eu_move_fpu1_instruction__read \ + bdw__compute_l3_cache__eu_move_fpu1_instruction__read + +/* Compute Metrics L3 Cache Gen10 :: EU Stall */ +#define cnl__compute_l3_cache__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Compute Metrics L3 Cache Gen10 :: Samples Blended */ +#define cnl__compute_l3_cache__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Compute Metrics L3 Cache Gen10 :: Early Depth Test Fails */ +#define cnl__compute_l3_cache__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Compute Metrics L3 Cache Gen10 :: Shader Memory Accesses */ +#define cnl__compute_l3_cache__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Compute Metrics L3 Cache Gen10 :: HS Threads Dispatched */ +#define cnl__compute_l3_cache__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Compute Metrics L3 Cache Gen10 :: L3 Total Throughput */ +static uint64_t +cnl__compute_l3_cache__l3_total_throughput__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: $L3Accesses 64 UMUL */ + uint64_t tmp0 = cnl__compute_l3_cache__l3_accesses__read(brw, query, accumulator) * 64; + + return tmp0; +} + +/* Compute Metrics L3 Cache Gen10 :: GTI Write Throughput */ +#define cnl__compute_l3_cache__gti_write_throughput__read \ + cnl__render_basic__gti_write_throughput__read + +/* Compute Metrics L3 Cache Gen10 :: L3 Shader Throughput */ +#define cnl__compute_l3_cache__l3_shader_throughput__read \ + cnl__render_basic__l3_shader_throughput__read + +/* Compute Metrics L3 Cache Gen10 :: Samples Killed in FS */ +#define cnl__compute_l3_cache__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Compute Metrics L3 Cache Gen10 :: SLM Bytes Written */ +#define cnl__compute_l3_cache__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Compute Metrics L3 Cache Gen10 :: EU FPU1 Binary Instruction */ +#define cnl__compute_l3_cache__eu_binary_fpu1_instruction__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Compute Metrics L3 Cache Gen10 :: EU FPU1 Ternary Instruction */ +#define cnl__compute_l3_cache__eu_ternary_fpu1_instruction__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Compute Metrics L3 Cache Gen10 :: EU Send Pipe Active */ +#define cnl__compute_l3_cache__eu_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set HDCAndSF :: GPU Core Clocks */ +#define cnl__hdc_and_sf__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set HDCAndSF :: EU Active */ +#define cnl__hdc_and_sf__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set HDCAndSF :: EU Both FPU Pipes Active */ +#define cnl__hdc_and_sf__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set HDCAndSF :: SQ is full */ +#define cnl__hdc_and_sf__gt_request_queue_full__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set HDCAndSF :: VS Send Pipe Active */ +#define cnl__hdc_and_sf__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set HDCAndSF :: VS FPU1 Pipe Active */ +#define cnl__hdc_and_sf__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set HDCAndSF :: GS Threads Dispatched */ +#define cnl__hdc_and_sf__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set HDCAndSF :: Early Hi-Depth Test Fails */ +#define cnl__hdc_and_sf__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set HDCAndSF :: FS Both FPU Active */ +#define cnl__hdc_and_sf__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set HDCAndSF :: VS Threads Dispatched */ +#define cnl__hdc_and_sf__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set HDCAndSF :: Polygon Data Ready */ +#define cnl__hdc_and_sf__poly_data_ready__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set HDCAndSF :: FS Threads Dispatched */ +#define cnl__hdc_and_sf__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set HDCAndSF :: Shader Barrier Messages */ +#define cnl__hdc_and_sf__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set HDCAndSF :: Sampler Texels */ +#define cnl__hdc_and_sf__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set HDCAndSF :: Pixels Failing Tests */ +#define cnl__hdc_and_sf__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set HDCAndSF :: GPU Time Elapsed */ +#define cnl__hdc_and_sf__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set HDCAndSF :: AVG GPU Core Frequency */ +#define cnl__hdc_and_sf__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set HDCAndSF :: AVG GPU Core Frequency */ +#define cnl__hdc_and_sf__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set HDCAndSF :: Sampler Texels Misses */ +#define cnl__hdc_and_sf__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set HDCAndSF :: Slice0 Subslice1 Non-sampler Shader Access Stalled On L3 */ +static float +cnl__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 4 READ B 5 READ FSUB 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->b_offset + 4]; + uint64_t tmp1 = accumulator[query->b_offset + 5]; + double tmp2 = tmp0 - tmp1; + uint64_t tmp3 = tmp2 * 100; + double tmp4 = tmp3; + double tmp5 = cnl__hdc_and_sf__gpu_core_clocks__read(brw, query, accumulator); + double tmp6 = tmp5 ? tmp4 / tmp5 : 0; + + return tmp6; +} + +/* Metric set HDCAndSF :: CS Threads Dispatched */ +#define cnl__hdc_and_sf__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set HDCAndSF :: Slice0 Subslice2 Non-sampler Shader Access Stalled On L3 */ +static float +cnl__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 6 READ B 7 READ FSUB 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->b_offset + 6]; + uint64_t tmp1 = accumulator[query->b_offset + 7]; + double tmp2 = tmp0 - tmp1; + uint64_t tmp3 = tmp2 * 100; + double tmp4 = tmp3; + double tmp5 = cnl__hdc_and_sf__gpu_core_clocks__read(brw, query, accumulator); + double tmp6 = tmp5 ? tmp4 / tmp5 : 0; + + return tmp6; +} + +/* Metric set HDCAndSF :: SLM Bytes Read */ +#define cnl__hdc_and_sf__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set HDCAndSF :: PS FPU1 Pipe Active */ +#define cnl__hdc_and_sf__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set HDCAndSF :: PS Send Pipeline Active */ +#define cnl__hdc_and_sf__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set HDCAndSF :: VS FPU0 Pipe Active */ +#define cnl__hdc_and_sf__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set HDCAndSF :: GPU Busy */ +#define cnl__hdc_and_sf__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set HDCAndSF :: Slice1 Subslice0 Non-sampler Shader Access Stalled On L3 */ +static float +cnl__hdc_and_sf__non_sampler_shader10_access_stalled_on_l3__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 0 READ C 1 READ FSUB 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->c_offset + 0]; + uint64_t tmp1 = accumulator[query->c_offset + 1]; + double tmp2 = tmp0 - tmp1; + uint64_t tmp3 = tmp2 * 100; + double tmp4 = tmp3; + double tmp5 = cnl__hdc_and_sf__gpu_core_clocks__read(brw, query, accumulator); + double tmp6 = tmp5 ? tmp4 / tmp5 : 0; + + return tmp6; +} + +/* Metric set HDCAndSF :: Rasterized Pixels */ +#define cnl__hdc_and_sf__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set HDCAndSF :: PS FPU0 Pipe Active */ +#define cnl__hdc_and_sf__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set HDCAndSF :: DS Threads Dispatched */ +#define cnl__hdc_and_sf__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set HDCAndSF :: Samples Written */ +#define cnl__hdc_and_sf__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set HDCAndSF :: EU Stall */ +#define cnl__hdc_and_sf__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set HDCAndSF :: Samples Blended */ +#define cnl__hdc_and_sf__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set HDCAndSF :: Early Depth Test Fails */ +#define cnl__hdc_and_sf__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set HDCAndSF :: Shader Memory Accesses */ +#define cnl__hdc_and_sf__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set HDCAndSF :: HS Threads Dispatched */ +#define cnl__hdc_and_sf__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set HDCAndSF :: Slice1 Subslice1 Non-sampler Shader Access Stalled On L3 */ +static float +cnl__hdc_and_sf__non_sampler_shader11_access_stalled_on_l3__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: C 2 READ C 3 READ FSUB 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->c_offset + 2]; + uint64_t tmp1 = accumulator[query->c_offset + 3]; + double tmp2 = tmp0 - tmp1; + uint64_t tmp3 = tmp2 * 100; + double tmp4 = tmp3; + double tmp5 = cnl__hdc_and_sf__gpu_core_clocks__read(brw, query, accumulator); + double tmp6 = tmp5 ? tmp4 / tmp5 : 0; + + return tmp6; +} + +/* Metric set HDCAndSF :: L3 Shader Throughput */ +#define cnl__hdc_and_sf__l3_shader_throughput__read \ + cnl__render_basic__l3_shader_throughput__read + +/* Metric set HDCAndSF :: Samples Killed in FS */ +#define cnl__hdc_and_sf__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set HDCAndSF :: Slice0 Subslice0 Non-sampler Shader Access Stalled On L3 */ +static float +cnl__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: B 2 READ B 3 READ FSUB 100 UMUL $GpuCoreClocks FDIV */ + uint64_t tmp0 = accumulator[query->b_offset + 2]; + uint64_t tmp1 = accumulator[query->b_offset + 3]; + double tmp2 = tmp0 - tmp1; + uint64_t tmp3 = tmp2 * 100; + double tmp4 = tmp3; + double tmp5 = cnl__hdc_and_sf__gpu_core_clocks__read(brw, query, accumulator); + double tmp6 = tmp5 ? tmp4 / tmp5 : 0; + + return tmp6; +} + +/* Metric set HDCAndSF :: SLM Bytes Written */ +#define cnl__hdc_and_sf__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set HDCAndSF :: Shader Atomic Memory Accesses */ +#define cnl__hdc_and_sf__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set L3_1 :: GPU Core Clocks */ +#define cnl__l3_1__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set L3_1 :: EU Active */ +#define cnl__l3_1__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set L3_1 :: Slice0 L3 Bank1 Active */ +#define cnl__l3_1__l30_bank1_active__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Metric set L3_1 :: EU Both FPU Pipes Active */ +#define cnl__l3_1__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set L3_1 :: SQ is full */ +#define cnl__l3_1__gt_request_queue_full__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set L3_1 :: VS Send Pipe Active */ +#define cnl__l3_1__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set L3_1 :: VS FPU1 Pipe Active */ +#define cnl__l3_1__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set L3_1 :: GS Threads Dispatched */ +#define cnl__l3_1__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set L3_1 :: Early Hi-Depth Test Fails */ +#define cnl__l3_1__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set L3_1 :: FS Both FPU Active */ +#define cnl__l3_1__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set L3_1 :: VS Threads Dispatched */ +#define cnl__l3_1__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set L3_1 :: Slice0 L3 Bank1 Stalled */ +#define cnl__l3_1__l30_bank1_stalled__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set L3_1 :: FS Threads Dispatched */ +#define cnl__l3_1__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set L3_1 :: Shader Barrier Messages */ +#define cnl__l3_1__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set L3_1 :: Sampler Texels */ +#define cnl__l3_1__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set L3_1 :: Pixels Failing Tests */ +#define cnl__l3_1__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set L3_1 :: GPU Time Elapsed */ +#define cnl__l3_1__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set L3_1 :: AVG GPU Core Frequency */ +#define cnl__l3_1__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set L3_1 :: AVG GPU Core Frequency */ +#define cnl__l3_1__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set L3_1 :: Sampler Texels Misses */ +#define cnl__l3_1__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set L3_1 :: CS Threads Dispatched */ +#define cnl__l3_1__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set L3_1 :: SLM Bytes Read */ +#define cnl__l3_1__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set L3_1 :: PS FPU1 Pipe Active */ +#define cnl__l3_1__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set L3_1 :: PS Send Pipeline Active */ +#define cnl__l3_1__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set L3_1 :: VS FPU0 Pipe Active */ +#define cnl__l3_1__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set L3_1 :: GPU Busy */ +#define cnl__l3_1__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set L3_1 :: Slice0 L3 Bank2 Active */ +#define cnl__l3_1__l30_bank2_active__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set L3_1 :: Slice0 L3 Bank0 Active */ +#define cnl__l3_1__l30_bank0_active__read \ + bdw__render_pipe_profile__so_stall__read + +/* Metric set L3_1 :: Rasterized Pixels */ +#define cnl__l3_1__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set L3_1 :: Slice1 L3 Bank2 Stalled */ +#define cnl__l3_1__l31_bank2_stalled__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Metric set L3_1 :: PS FPU0 Pipe Active */ +#define cnl__l3_1__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set L3_1 :: Slice0 L3 Bank0 Stalled */ +#define cnl__l3_1__l30_bank0_stalled__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set L3_1 :: DS Threads Dispatched */ +#define cnl__l3_1__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set L3_1 :: Samples Written */ +#define cnl__l3_1__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set L3_1 :: EU Stall */ +#define cnl__l3_1__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set L3_1 :: Samples Blended */ +#define cnl__l3_1__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set L3_1 :: Early Depth Test Fails */ +#define cnl__l3_1__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set L3_1 :: Shader Memory Accesses */ +#define cnl__l3_1__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set L3_1 :: HS Threads Dispatched */ +#define cnl__l3_1__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set L3_1 :: L3 Shader Throughput */ +#define cnl__l3_1__l3_shader_throughput__read \ + cnl__render_basic__l3_shader_throughput__read + +/* Metric set L3_1 :: Samples Killed in FS */ +#define cnl__l3_1__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set L3_1 :: SLM Bytes Written */ +#define cnl__l3_1__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set L3_1 :: Shader Atomic Memory Accesses */ +#define cnl__l3_1__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set L3_2 :: GPU Core Clocks */ +#define cnl__l3_2__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set L3_2 :: EU Active */ +#define cnl__l3_2__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set L3_2 :: Slice1 L3 Bank1 Stalled */ +#define cnl__l3_2__l31_bank1_stalled__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set L3_2 :: EU Both FPU Pipes Active */ +#define cnl__l3_2__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set L3_2 :: SQ is full */ +#define cnl__l3_2__gt_request_queue_full__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set L3_2 :: VS Send Pipe Active */ +#define cnl__l3_2__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set L3_2 :: VS FPU1 Pipe Active */ +#define cnl__l3_2__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set L3_2 :: GS Threads Dispatched */ +#define cnl__l3_2__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set L3_2 :: Early Hi-Depth Test Fails */ +#define cnl__l3_2__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set L3_2 :: FS Both FPU Active */ +#define cnl__l3_2__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set L3_2 :: VS Threads Dispatched */ +#define cnl__l3_2__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set L3_2 :: FS Threads Dispatched */ +#define cnl__l3_2__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set L3_2 :: Shader Barrier Messages */ +#define cnl__l3_2__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set L3_2 :: Slice1 L3 Bank0 Stalled */ +#define cnl__l3_2__l31_bank0_stalled__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set L3_2 :: Sampler Texels */ +#define cnl__l3_2__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set L3_2 :: Pixels Failing Tests */ +#define cnl__l3_2__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set L3_2 :: GPU Time Elapsed */ +#define cnl__l3_2__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set L3_2 :: AVG GPU Core Frequency */ +#define cnl__l3_2__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set L3_2 :: AVG GPU Core Frequency */ +#define cnl__l3_2__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set L3_2 :: Sampler Texels Misses */ +#define cnl__l3_2__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set L3_2 :: CS Threads Dispatched */ +#define cnl__l3_2__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set L3_2 :: SLM Bytes Read */ +#define cnl__l3_2__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set L3_2 :: PS FPU1 Pipe Active */ +#define cnl__l3_2__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set L3_2 :: Slice0 L3 Bank2 Stalled */ +#define cnl__l3_2__l30_bank2_stalled__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Metric set L3_2 :: PS Send Pipeline Active */ +#define cnl__l3_2__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set L3_2 :: VS FPU0 Pipe Active */ +#define cnl__l3_2__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set L3_2 :: GPU Busy */ +#define cnl__l3_2__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set L3_2 :: Slice1 L3 Bank2 Active */ +#define cnl__l3_2__l31_bank2_active__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set L3_2 :: Rasterized Pixels */ +#define cnl__l3_2__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set L3_2 :: Slice1 L3 Bank1 Active */ +#define cnl__l3_2__l31_bank1_active__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Metric set L3_2 :: PS FPU0 Pipe Active */ +#define cnl__l3_2__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set L3_2 :: DS Threads Dispatched */ +#define cnl__l3_2__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set L3_2 :: Samples Written */ +#define cnl__l3_2__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set L3_2 :: EU Stall */ +#define cnl__l3_2__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set L3_2 :: Slice1 L3 Bank0 Active */ +#define cnl__l3_2__l31_bank0_active__read \ + bdw__render_pipe_profile__so_stall__read + +/* Metric set L3_2 :: Samples Blended */ +#define cnl__l3_2__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set L3_2 :: Early Depth Test Fails */ +#define cnl__l3_2__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set L3_2 :: Shader Memory Accesses */ +#define cnl__l3_2__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set L3_2 :: HS Threads Dispatched */ +#define cnl__l3_2__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set L3_2 :: L3 Shader Throughput */ +#define cnl__l3_2__l3_shader_throughput__read \ + cnl__render_basic__l3_shader_throughput__read + +/* Metric set L3_2 :: Samples Killed in FS */ +#define cnl__l3_2__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set L3_2 :: SLM Bytes Written */ +#define cnl__l3_2__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set L3_2 :: Shader Atomic Memory Accesses */ +#define cnl__l3_2__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set RasterizerAndPixelBackend :: GPU Core Clocks */ +#define cnl__rasterizer_and_pixel_backend__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set RasterizerAndPixelBackend :: EU Active */ +#define cnl__rasterizer_and_pixel_backend__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set RasterizerAndPixelBackend :: EU Both FPU Pipes Active */ +#define cnl__rasterizer_and_pixel_backend__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set RasterizerAndPixelBackend :: Slice1 Rasterizer Input Available */ +#define cnl__rasterizer_and_pixel_backend__rasterizer1_input_available__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set RasterizerAndPixelBackend :: VS Send Pipe Active */ +#define cnl__rasterizer_and_pixel_backend__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set RasterizerAndPixelBackend :: VS FPU1 Pipe Active */ +#define cnl__rasterizer_and_pixel_backend__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set RasterizerAndPixelBackend :: GS Threads Dispatched */ +#define cnl__rasterizer_and_pixel_backend__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set RasterizerAndPixelBackend :: Early Hi-Depth Test Fails */ +#define cnl__rasterizer_and_pixel_backend__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set RasterizerAndPixelBackend :: FS Both FPU Active */ +#define cnl__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set RasterizerAndPixelBackend :: VS Threads Dispatched */ +#define cnl__rasterizer_and_pixel_backend__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set RasterizerAndPixelBackend :: FS Threads Dispatched */ +#define cnl__rasterizer_and_pixel_backend__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Pixel Values Ready */ +#define cnl__rasterizer_and_pixel_backend__pixel_values0_ready__read \ + bdw__render_pipe_profile__vf_bottleneck__read + +/* Metric set RasterizerAndPixelBackend :: Shader Barrier Messages */ +#define cnl__rasterizer_and_pixel_backend__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set RasterizerAndPixelBackend :: Sampler Texels */ +#define cnl__rasterizer_and_pixel_backend__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set RasterizerAndPixelBackend :: Pixels Failing Tests */ +#define cnl__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set RasterizerAndPixelBackend :: GPU Time Elapsed */ +#define cnl__rasterizer_and_pixel_backend__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ +#define cnl__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set RasterizerAndPixelBackend :: AVG GPU Core Frequency */ +#define cnl__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set RasterizerAndPixelBackend :: Sampler Texels Misses */ +#define cnl__rasterizer_and_pixel_backend__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set RasterizerAndPixelBackend :: CS Threads Dispatched */ +#define cnl__rasterizer_and_pixel_backend__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Input Available */ +#define cnl__rasterizer_and_pixel_backend__rasterizer0_input_available__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Post-EarlyZ Pixel Data Ready */ +#define cnl__rasterizer_and_pixel_backend__pixel_data0_ready__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Metric set RasterizerAndPixelBackend :: SLM Bytes Read */ +#define cnl__rasterizer_and_pixel_backend__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set RasterizerAndPixelBackend :: PS FPU1 Pipe Active */ +#define cnl__rasterizer_and_pixel_backend__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set RasterizerAndPixelBackend :: PS Send Pipeline Active */ +#define cnl__rasterizer_and_pixel_backend__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set RasterizerAndPixelBackend :: VS FPU0 Pipe Active */ +#define cnl__rasterizer_and_pixel_backend__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set RasterizerAndPixelBackend :: GPU Busy */ +#define cnl__rasterizer_and_pixel_backend__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set RasterizerAndPixelBackend :: Slice1 Pixel Values Ready */ +#define cnl__rasterizer_and_pixel_backend__pixel_values1_ready__read \ + bdw__render_pipe_profile__hs_stall__read + +/* Metric set RasterizerAndPixelBackend :: Slice1 PS Output Available */ +#define cnl__rasterizer_and_pixel_backend__ps_output1_available__read \ + bdw__render_pipe_profile__early_depth_bottleneck__read + +/* Metric set RasterizerAndPixelBackend :: Rasterized Pixels */ +#define cnl__rasterizer_and_pixel_backend__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set RasterizerAndPixelBackend :: PS FPU0 Pipe Active */ +#define cnl__rasterizer_and_pixel_backend__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set RasterizerAndPixelBackend :: DS Threads Dispatched */ +#define cnl__rasterizer_and_pixel_backend__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set RasterizerAndPixelBackend :: Samples Written */ +#define cnl__rasterizer_and_pixel_backend__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set RasterizerAndPixelBackend :: EU Stall */ +#define cnl__rasterizer_and_pixel_backend__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 Rasterizer Output Ready */ +#define cnl__rasterizer_and_pixel_backend__rasterizer0_output_ready__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Metric set RasterizerAndPixelBackend :: Samples Blended */ +#define cnl__rasterizer_and_pixel_backend__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set RasterizerAndPixelBackend :: Early Depth Test Fails */ +#define cnl__rasterizer_and_pixel_backend__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set RasterizerAndPixelBackend :: Slice1 Rasterizer Output Ready */ +#define cnl__rasterizer_and_pixel_backend__rasterizer1_output_ready__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Metric set RasterizerAndPixelBackend :: Slice1 Post-EarlyZ Pixel Data Ready */ +#define cnl__rasterizer_and_pixel_backend__pixel_data1_ready__read \ + bdw__render_pipe_profile__cl_bottleneck__read + +/* Metric set RasterizerAndPixelBackend :: Shader Memory Accesses */ +#define cnl__rasterizer_and_pixel_backend__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set RasterizerAndPixelBackend :: SQ is full */ +#define cnl__rasterizer_and_pixel_backend__gt_request_queue_full__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set RasterizerAndPixelBackend :: HS Threads Dispatched */ +#define cnl__rasterizer_and_pixel_backend__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set RasterizerAndPixelBackend :: L3 Shader Throughput */ +#define cnl__rasterizer_and_pixel_backend__l3_shader_throughput__read \ + cnl__render_basic__l3_shader_throughput__read + +/* Metric set RasterizerAndPixelBackend :: Samples Killed in FS */ +#define cnl__rasterizer_and_pixel_backend__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set RasterizerAndPixelBackend :: SLM Bytes Written */ +#define cnl__rasterizer_and_pixel_backend__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set RasterizerAndPixelBackend :: Slice0 PS Output Available */ +#define cnl__rasterizer_and_pixel_backend__ps_output0_available__read \ + bdw__render_pipe_profile__sf_bottleneck__read + +/* Metric set RasterizerAndPixelBackend :: Shader Atomic Memory Accesses */ +#define cnl__rasterizer_and_pixel_backend__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set Sampler :: GPU Core Clocks */ +#define cnl__sampler__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set Sampler :: EU Active */ +#define cnl__sampler__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set Sampler :: Slice0 Subslice2 Input Available */ +#define cnl__sampler__sampler02_input_available__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Metric set Sampler :: EU Both FPU Pipes Active */ +#define cnl__sampler__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set Sampler :: SQ is full */ +#define cnl__sampler__gt_request_queue_full__read \ + bdw__render_pipe_profile__ds_stall__read + +/* Metric set Sampler :: VS Send Pipe Active */ +#define cnl__sampler__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set Sampler :: Slice0 Subslice0 Input Available */ +#define cnl__sampler__sampler00_input_available__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set Sampler :: VS FPU1 Pipe Active */ +#define cnl__sampler__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set Sampler :: GS Threads Dispatched */ +#define cnl__sampler__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set Sampler :: Slice1 Subslice0 Input Available */ +#define cnl__sampler__sampler10_input_available__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Metric set Sampler :: Early Hi-Depth Test Fails */ +#define cnl__sampler__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set Sampler :: FS Both FPU Active */ +#define cnl__sampler__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set Sampler :: VS Threads Dispatched */ +#define cnl__sampler__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set Sampler :: Slice0 Subslice2 Sampler Output Ready */ +#define cnl__sampler__sampler02_output_ready__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set Sampler :: FS Threads Dispatched */ +#define cnl__sampler__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set Sampler :: Shader Barrier Messages */ +#define cnl__sampler__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set Sampler :: Slice0 Subslice1 Input Available */ +#define cnl__sampler__sampler01_input_available__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set Sampler :: Sampler Texels */ +#define cnl__sampler__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set Sampler :: Pixels Failing Tests */ +#define cnl__sampler__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set Sampler :: GPU Time Elapsed */ +#define cnl__sampler__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set Sampler :: AVG GPU Core Frequency */ +#define cnl__sampler__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set Sampler :: AVG GPU Core Frequency */ +#define cnl__sampler__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set Sampler :: Sampler Texels Misses */ +#define cnl__sampler__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set Sampler :: CS Threads Dispatched */ +#define cnl__sampler__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set Sampler :: SLM Bytes Read */ +#define cnl__sampler__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set Sampler :: PS FPU1 Pipe Active */ +#define cnl__sampler__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set Sampler :: PS Send Pipeline Active */ +#define cnl__sampler__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set Sampler :: VS FPU0 Pipe Active */ +#define cnl__sampler__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set Sampler :: GPU Busy */ +#define cnl__sampler__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set Sampler :: Slice1 Subslice1 Input Available */ +#define cnl__sampler__sampler11_input_available__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Metric set Sampler :: Rasterized Pixels */ +#define cnl__sampler__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set Sampler :: PS FPU0 Pipe Active */ +#define cnl__sampler__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set Sampler :: DS Threads Dispatched */ +#define cnl__sampler__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set Sampler :: Samples Written */ +#define cnl__sampler__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set Sampler :: EU Stall */ +#define cnl__sampler__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set Sampler :: Samples Blended */ +#define cnl__sampler__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set Sampler :: Early Depth Test Fails */ +#define cnl__sampler__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set Sampler :: Slice0 Subslice0 Sampler Output Ready */ +#define cnl__sampler__sampler00_output_ready__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set Sampler :: Slice1 Subslice0 Sampler Output Ready */ +#define cnl__sampler__sampler10_output_ready__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Metric set Sampler :: Slice0 Subslice1 Sampler Output Ready */ +#define cnl__sampler__sampler01_output_ready__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set Sampler :: Shader Memory Accesses */ +#define cnl__sampler__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set Sampler :: Slice1 Subslice1 Sampler Output Ready */ +#define cnl__sampler__sampler11_output_ready__read \ + bdw__render_pipe_profile__so_stall__read + +/* Metric set Sampler :: HS Threads Dispatched */ +#define cnl__sampler__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set Sampler :: L3 Shader Throughput */ +#define cnl__sampler__l3_shader_throughput__read \ + cnl__render_basic__l3_shader_throughput__read + +/* Metric set Sampler :: Samples Killed in FS */ +#define cnl__sampler__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set Sampler :: SLM Bytes Written */ +#define cnl__sampler__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set Sampler :: Shader Atomic Memory Accesses */ +#define cnl__sampler__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set TDL_1 :: GPU Core Clocks */ +#define cnl__tdl_1__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set TDL_1 :: EU Active */ +#define cnl__tdl_1__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set TDL_1 :: EU Both FPU Pipes Active */ +#define cnl__tdl_1__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set TDL_1 :: SQ is full */ +#define cnl__tdl_1__gt_request_queue_full__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set TDL_1 :: VS Send Pipe Active */ +#define cnl__tdl_1__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set TDL_1 :: VS FPU1 Pipe Active */ +#define cnl__tdl_1__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set TDL_1 :: GS Threads Dispatched */ +#define cnl__tdl_1__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set TDL_1 :: Early Hi-Depth Test Fails */ +#define cnl__tdl_1__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set TDL_1 :: FS Both FPU Active */ +#define cnl__tdl_1__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set TDL_1 :: VS Threads Dispatched */ +#define cnl__tdl_1__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice1 Subslice1 */ +#define cnl__tdl_1__ps_thread11_ready_for_dispatch__read \ + bdw__render_pipe_profile__so_bottleneck__read + +/* Metric set TDL_1 :: FS Threads Dispatched */ +#define cnl__tdl_1__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice2 */ +static float +cnl__tdl_1__non_ps_thread02_ready_for_dispatch__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: 1 C 4 READ $GpuCoreClocks FDIV FSUB */ + uint64_t tmp0 = accumulator[query->c_offset + 4]; + double tmp1 = tmp0; + double tmp2 = cnl__tdl_1__gpu_core_clocks__read(brw, query, accumulator); + double tmp3 = tmp2 ? tmp1 / tmp2 : 0; + double tmp4 = 1 - tmp3; + + return tmp4; +} + +/* Metric set TDL_1 :: Shader Barrier Messages */ +#define cnl__tdl_1__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_1 :: Sampler Texels */ +#define cnl__tdl_1__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set TDL_1 :: Pixels Failing Tests */ +#define cnl__tdl_1__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice1 Subslice0 */ +static float +cnl__tdl_1__non_ps_thread10_ready_for_dispatch__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: 1 C 5 READ $GpuCoreClocks FDIV FSUB */ + uint64_t tmp0 = accumulator[query->c_offset + 5]; + double tmp1 = tmp0; + double tmp2 = cnl__tdl_1__gpu_core_clocks__read(brw, query, accumulator); + double tmp3 = tmp2 ? tmp1 / tmp2 : 0; + double tmp4 = 1 - tmp3; + + return tmp4; +} + +/* Metric set TDL_1 :: GPU Time Elapsed */ +#define cnl__tdl_1__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set TDL_1 :: AVG GPU Core Frequency */ +#define cnl__tdl_1__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set TDL_1 :: AVG GPU Core Frequency */ +#define cnl__tdl_1__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set TDL_1 :: Sampler Texels Misses */ +#define cnl__tdl_1__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice0 */ +static float +cnl__tdl_1__non_ps_thread00_ready_for_dispatch__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: 1 C 2 READ $GpuCoreClocks FDIV FSUB */ + uint64_t tmp0 = accumulator[query->c_offset + 2]; + double tmp1 = tmp0; + double tmp2 = cnl__tdl_1__gpu_core_clocks__read(brw, query, accumulator); + double tmp3 = tmp2 ? tmp1 / tmp2 : 0; + double tmp4 = 1 - tmp3; + + return tmp4; +} + +/* Metric set TDL_1 :: CS Threads Dispatched */ +#define cnl__tdl_1__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set TDL_1 :: SLM Bytes Read */ +#define cnl__tdl_1__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set TDL_1 :: PS FPU1 Pipe Active */ +#define cnl__tdl_1__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set TDL_1 :: PS Send Pipeline Active */ +#define cnl__tdl_1__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set TDL_1 :: VS FPU0 Pipe Active */ +#define cnl__tdl_1__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set TDL_1 :: GPU Busy */ +#define cnl__tdl_1__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice0 */ +#define cnl__tdl_1__ps_thread00_ready_for_dispatch__read \ + bdw__render_basic__sampler0_busy__read + +/* Metric set TDL_1 :: Rasterized Pixels */ +#define cnl__tdl_1__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set TDL_1 :: PS FPU0 Pipe Active */ +#define cnl__tdl_1__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set TDL_1 :: DS Threads Dispatched */ +#define cnl__tdl_1__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set TDL_1 :: Samples Written */ +#define cnl__tdl_1__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set TDL_1 :: EU Stall */ +#define cnl__tdl_1__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set TDL_1 :: Samples Blended */ +#define cnl__tdl_1__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set TDL_1 :: Early Depth Test Fails */ +#define cnl__tdl_1__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice1 */ +#define cnl__tdl_1__ps_thread01_ready_for_dispatch__read \ + bdw__render_basic__sampler1_busy__read + +/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice1 Subslice0 */ +#define cnl__tdl_1__ps_thread10_ready_for_dispatch__read \ + bdw__render_basic__sampler1_bottleneck__read + +/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice1 Subslice1 */ +static float +cnl__tdl_1__non_ps_thread11_ready_for_dispatch__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: 1 C 6 READ $GpuCoreClocks FDIV FSUB */ + uint64_t tmp0 = accumulator[query->c_offset + 6]; + double tmp1 = tmp0; + double tmp2 = cnl__tdl_1__gpu_core_clocks__read(brw, query, accumulator); + double tmp3 = tmp2 ? tmp1 / tmp2 : 0; + double tmp4 = 1 - tmp3; + + return tmp4; +} + +/* Metric set TDL_1 :: Shader Memory Accesses */ +#define cnl__tdl_1__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set TDL_1 :: HS Threads Dispatched */ +#define cnl__tdl_1__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set TDL_1 :: PS Thread Ready For Dispatch on Slice0 Subslice2 */ +#define cnl__tdl_1__ps_thread02_ready_for_dispatch__read \ + bdw__render_basic__sampler0_bottleneck__read + +/* Metric set TDL_1 :: L3 Shader Throughput */ +#define cnl__tdl_1__l3_shader_throughput__read \ + cnl__render_basic__l3_shader_throughput__read + +/* Metric set TDL_1 :: Samples Killed in FS */ +#define cnl__tdl_1__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set TDL_1 :: SLM Bytes Written */ +#define cnl__tdl_1__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set TDL_1 :: Shader Atomic Memory Accesses */ +#define cnl__tdl_1__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set TDL_1 :: NonPS Thread Ready For Dispatch on Slice0 Subslice1 */ +static float +cnl__tdl_1__non_ps_thread01_ready_for_dispatch__read(MAYBE_UNUSED struct brw_context *brw, + const struct brw_perf_query_info *query, + uint64_t *accumulator) +{ + /* RPN equation: 1 C 3 READ $GpuCoreClocks FDIV FSUB */ + uint64_t tmp0 = accumulator[query->c_offset + 3]; + double tmp1 = tmp0; + double tmp2 = cnl__tdl_1__gpu_core_clocks__read(brw, query, accumulator); + double tmp3 = tmp2 ? tmp1 / tmp2 : 0; + double tmp4 = 1 - tmp3; + + return tmp4; +} + +/* Metric set TDL_2 :: GPU Core Clocks */ +#define cnl__tdl_2__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set TDL_2 :: EU Active */ +#define cnl__tdl_2__eu_active__read \ + bdw__render_basic__eu_active__read + +/* Metric set TDL_2 :: EU Both FPU Pipes Active */ +#define cnl__tdl_2__eu_fpu_both_active__read \ + bdw__render_basic__eu_fpu_both_active__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice1 Port 1 */ +#define cnl__tdl_2__thread_header11_ready_port1__read \ + bdw__render_pipe_profile__bc_bottleneck__read + +/* Metric set TDL_2 :: VS Send Pipe Active */ +#define cnl__tdl_2__vs_send_active__read \ + bdw__render_basic__vs_send_active__read + +/* Metric set TDL_2 :: VS FPU1 Pipe Active */ +#define cnl__tdl_2__vs_fpu1_active__read \ + bdw__render_basic__vs_fpu1_active__read + +/* Metric set TDL_2 :: GS Threads Dispatched */ +#define cnl__tdl_2__gs_threads__read \ + hsw__render_basic__vs_threads__read + +/* Metric set TDL_2 :: Early Hi-Depth Test Fails */ +#define cnl__tdl_2__hi_depth_test_fails__read \ + bdw__render_basic__hi_depth_test_fails__read + +/* Metric set TDL_2 :: FS Both FPU Active */ +#define cnl__tdl_2__ps_eu_both_fpu_active__read \ + bdw__render_basic__ps_eu_both_fpu_active__read + +/* Metric set TDL_2 :: VS Threads Dispatched */ +#define cnl__tdl_2__vs_threads__read \ + bdw__render_basic__vs_threads__read + +/* Metric set TDL_2 :: FS Threads Dispatched */ +#define cnl__tdl_2__ps_threads__read \ + bdw__render_basic__ps_threads__read + +/* Metric set TDL_2 :: Shader Barrier Messages */ +#define cnl__tdl_2__shader_barriers__read \ + hsw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_2 :: Sampler Texels */ +#define cnl__tdl_2__sampler_texels__read \ + bdw__render_basic__sampler_texels__read + +/* Metric set TDL_2 :: Pixels Failing Tests */ +#define cnl__tdl_2__pixels_failing_post_ps_tests__read \ + bdw__render_basic__pixels_failing_post_ps_tests__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 0 */ +#define cnl__tdl_2__thread_header01_ready_port0__read \ + bdw__render_pipe_profile__vf_bottleneck__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice1 Port 1 */ +#define cnl__tdl_2__thread_header01_ready_port1__read \ + bdw__render_pipe_profile__hs_stall__read + +/* Metric set TDL_2 :: GPU Time Elapsed */ +#define cnl__tdl_2__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set TDL_2 :: AVG GPU Core Frequency */ +#define cnl__tdl_2__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set TDL_2 :: AVG GPU Core Frequency */ +#define cnl__tdl_2__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set TDL_2 :: Sampler Texels Misses */ +#define cnl__tdl_2__sampler_texel_misses__read \ + bdw__render_basic__sampler_texel_misses__read + +/* Metric set TDL_2 :: CS Threads Dispatched */ +#define cnl__tdl_2__cs_threads__read \ + bdw__render_basic__cs_threads__read + +/* Metric set TDL_2 :: SQ is full */ +#define cnl__tdl_2__gt_request_queue_full__read \ + bdw__render_pipe_profile__cl_bottleneck__read + +/* Metric set TDL_2 :: SLM Bytes Read */ +#define cnl__tdl_2__slm_bytes_read__read \ + bdw__render_basic__slm_bytes_read__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice1 Port 0 */ +#define cnl__tdl_2__thread_header11_ready_port0__read \ + bdw__render_pipe_profile__hi_depth_bottleneck__read + +/* Metric set TDL_2 :: PS FPU1 Pipe Active */ +#define cnl__tdl_2__ps_fpu1_active__read \ + bdw__render_basic__ps_fpu1_active__read + +/* Metric set TDL_2 :: PS Send Pipeline Active */ +#define cnl__tdl_2__ps_send_active__read \ + bdw__render_basic__ps_send_active__read + +/* Metric set TDL_2 :: VS FPU0 Pipe Active */ +#define cnl__tdl_2__vs_fpu0_active__read \ + bdw__render_basic__vs_fpu0_active__read + +/* Metric set TDL_2 :: GPU Busy */ +#define cnl__tdl_2__gpu_busy__read \ + bdw__render_basic__gpu_busy__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 1 */ +#define cnl__tdl_2__thread_header02_ready_port1__read \ + bdw__render_pipe_profile__so_stall__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice2 Port 0 */ +#define cnl__tdl_2__thread_header02_ready_port0__read \ + bdw__render_pipe_profile__ds_stall__read + +/* Metric set TDL_2 :: Rasterized Pixels */ +#define cnl__tdl_2__rasterized_pixels__read \ + bdw__render_basic__rasterized_pixels__read + +/* Metric set TDL_2 :: PS FPU0 Pipe Active */ +#define cnl__tdl_2__ps_fpu0_active__read \ + bdw__render_basic__ps_fpu0_active__read + +/* Metric set TDL_2 :: DS Threads Dispatched */ +#define cnl__tdl_2__ds_threads__read \ + bdw__render_basic__ds_threads__read + +/* Metric set TDL_2 :: Samples Written */ +#define cnl__tdl_2__samples_written__read \ + bdw__render_basic__samples_written__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice0 Port 1 */ +#define cnl__tdl_2__thread_header10_ready_port1__read \ + bdw__render_pipe_profile__sf_stall__read + +/* Metric set TDL_2 :: EU Stall */ +#define cnl__tdl_2__eu_stall__read \ + bdw__render_basic__eu_stall__read + +/* Metric set TDL_2 :: Samples Blended */ +#define cnl__tdl_2__samples_blended__read \ + bdw__render_basic__samples_blended__read + +/* Metric set TDL_2 :: Early Depth Test Fails */ +#define cnl__tdl_2__early_depth_test_fails__read \ + bdw__render_basic__early_depth_test_fails__read + +/* Metric set TDL_2 :: Shader Memory Accesses */ +#define cnl__tdl_2__shader_memory_accesses__read \ + bdw__render_basic__shader_memory_accesses__read + +/* Metric set TDL_2 :: HS Threads Dispatched */ +#define cnl__tdl_2__hs_threads__read \ + bdw__render_basic__hs_threads__read + +/* Metric set TDL_2 :: L3 Shader Throughput */ +#define cnl__tdl_2__l3_shader_throughput__read \ + cnl__render_basic__l3_shader_throughput__read + +/* Metric set TDL_2 :: Samples Killed in FS */ +#define cnl__tdl_2__samples_killed_in_ps__read \ + bdw__render_basic__samples_killed_in_ps__read + +/* Metric set TDL_2 :: SLM Bytes Written */ +#define cnl__tdl_2__slm_bytes_written__read \ + bdw__render_basic__slm_bytes_written__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice1 Subslice0 Port 0 */ +#define cnl__tdl_2__thread_header10_ready_port0__read \ + bdw__render_pipe_profile__cl_stall__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 0 */ +#define cnl__tdl_2__thread_header00_ready_port0__read \ + bdw__render_pipe_profile__sf_bottleneck__read + +/* Metric set TDL_2 :: Shader Atomic Memory Accesses */ +#define cnl__tdl_2__shader_atomics__read \ + bdw__render_basic__shader_atomics__read + +/* Metric set TDL_2 :: Thread Header Ready on Slice0 Subslice0 Port 1 */ +#define cnl__tdl_2__thread_header00_ready_port1__read \ + bdw__render_pipe_profile__early_depth_bottleneck__read + +/* Metric set TestOa :: TestCounter7 */ +#define cnl__test_oa__counter7__read \ + hsw__compute_extended__gpu_clocks__read + +/* Metric set TestOa :: GPU Time Elapsed */ +#define cnl__test_oa__gpu_time__read \ + hsw__render_basic__gpu_time__read + +/* Metric set TestOa :: GPU Core Clocks */ +#define cnl__test_oa__gpu_core_clocks__read \ + bdw__render_basic__gpu_core_clocks__read + +/* Metric set TestOa :: AVG GPU Core Frequency */ +#define cnl__test_oa__avg_gpu_core_frequency__read \ + bdw__render_basic__avg_gpu_core_frequency__read + +/* Metric set TestOa :: AVG GPU Core Frequency */ +#define cnl__test_oa__avg_gpu_core_frequency__max \ + hsw__render_basic__avg_gpu_core_frequency__max + +/* Metric set TestOa :: TestCounter8 */ +#define cnl__test_oa__counter8__read \ + hsw__memory_reads__gpu_core_clocks__read + +/* Metric set TestOa :: TestCounter4 */ +#define cnl__test_oa__counter4__read \ + hsw__compute_extended__eu_untyped_atomics0__read + +/* Metric set TestOa :: TestCounter5 */ +#define cnl__test_oa__counter5__read \ + hsw__compute_extended__eu_typed_atomics0__read + +/* Metric set TestOa :: TestCounter6 */ +#define cnl__test_oa__counter6__read \ + hsw__compute_extended__eu_urb_atomics0__read + +/* Metric set TestOa :: TestCounter3 */ +#define cnl__test_oa__counter3__read \ + hsw__compute_extended__eu_typed_writes0__read + +/* Metric set TestOa :: TestCounter0 */ +#define cnl__test_oa__counter0__read \ + hsw__compute_extended__eu_untyped_reads0__read + +/* Metric set TestOa :: TestCounter1 */ +#define cnl__test_oa__counter1__read \ + hsw__compute_extended__eu_untyped_writes0__read + +/* Metric set TestOa :: TestCounter2 */ +#define cnl__test_oa__counter2__read \ + hsw__compute_extended__eu_typed_reads0__read + +static struct brw_perf_query_register_prog hsw_render_basic_mux_regs[60]; +static struct brw_perf_query_register_prog hsw_render_basic_b_counter_regs[4]; + +static struct brw_perf_query_counter hsw_render_basic_query_counters[67]; +static struct brw_perf_query_info hsw_render_basic_query = { + .kind = OA_COUNTERS, + .name = "Render Metrics Basic Gen7.5", + .guid = "403d8832-1a27-4aa6-a64e-f5389ce7b212", + .counters = hsw_render_basic_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A45_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .a_offset = 1, + .b_offset = 46, + .c_offset = 54, + .mux_regs = hsw_render_basic_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = hsw_render_basic_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ +}; + +static void +hsw_register_render_basic_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &hsw_render_basic_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000253A4, .val = 0x01600000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025440, .val = 0x00100000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025128, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0002691C, .val = 0x00000800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026AA0, .val = 0x01500000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026B9C, .val = 0x00006000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0002791C, .val = 0x00000800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00027AA0, .val = 0x01500000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00027B9C, .val = 0x00006000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0002641C, .val = 0x00000400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025380, .val = 0x00000010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0002538C, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025384, .val = 0x0800AAAA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025400, .val = 0x00000004 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0002540C, .val = 0x06029000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025410, .val = 0x00000002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025404, .val = 0x5C30FFFF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025100, .val = 0x00000016 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025110, .val = 0x00000400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025104, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026804, .val = 0x00001211 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026884, .val = 0x00000100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026900, .val = 0x00000002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026908, .val = 0x00700000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026904, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026984, .val = 0x00001022 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026A04, .val = 0x00000011 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026A80, .val = 0x00000006 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026A88, .val = 0x00000C02 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026A84, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026B04, .val = 0x00001000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026B80, .val = 0x00000002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026B8C, .val = 0x00000007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026B84, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00027804, .val = 0x00004844 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00027884, .val = 0x00000400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00027900, .val = 0x00000002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00027908, .val = 0x0E000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00027904, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00027984, .val = 0x00004088 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00027A04, .val = 0x00000044 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00027A80, .val = 0x00000006 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00027A88, .val = 0x00018040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00027A84, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00027B04, .val = 0x00004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00027B80, .val = 0x00000002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00027B8C, .val = 0x000000E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00027B84, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026104, .val = 0x00002222 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026184, .val = 0x0C006666 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026284, .val = 0x04000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026304, .val = 0x04000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026400, .val = 0x00000002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026410, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026404, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025420, .val = 0x04108020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025424, .val = 0x1284A420 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0002541C, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025428, .val = 0x00042049 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__render_basic__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__render_basic__ds_eu_stall__read; + counter->name = "TES EU Stall"; + counter->desc = "The percentage of time in which evaluation shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__alpha_test_fails__read; + counter->name = "Alpha Test Fails"; + counter->desc = "The total number of pixels dropped on post-FS alpha test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__render_basic__sampler1_bottleneck__read; + counter->name = "Sampler 1 Bottleneck"; + counter->desc = "The percentage of time in which sampler 1 was bottlenecks."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__ds_threads__read; + counter->name = "TES Threads Dispatched"; + counter->desc = "The total number of evaluation shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__ds_eu_active_per_thread__read; + counter->name = "TES AVG Active per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which evaluation shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__render_basic__gs_eu_stall__read; + counter->name = "GS EU Stall"; + counter->desc = "The percentage of time in which geometry shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__render_basic__cs_eu_active__read; + counter->name = "CS EU Active"; + counter->desc = "The percentage of time in which compute shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 60; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__render_basic__vs_eu_active__read; + counter->name = "VS EU Active"; + counter->desc = "The percentage of time in which vertex shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__render_basic__hs_eu_active__read; + counter->name = "TCS EU Active"; + counter->desc = "The percentage of time in which control shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 68; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__render_basic__ds_eu_active__read; + counter->name = "TES EU Active"; + counter->desc = "The percentage of time in which evaluation shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 72; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__render_basic__gs_eu_active__read; + counter->name = "GS EU Active"; + counter->desc = "The percentage of time in which geometry shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 76; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__render_basic__ps_eu_active__read; + counter->name = "FS EU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 80; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__render_basic__cs_eu_stall__read; + counter->name = "CS EU Stall"; + counter->desc = "The percentage of time in which compute shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 84; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__render_basic__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 88; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__render_basic__vs_eu_stall__read; + counter->name = "VS EU Stall"; + counter->desc = "The percentage of time in which vertex shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 92; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__render_basic__hs_eu_stall__read; + counter->name = "TCS EU Stall"; + counter->desc = "The percentage of time in which control shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 96; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__render_basic__ps_eu_stall__read; + counter->name = "FS EU Stall"; + counter->desc = "The percentage of time in which fragment shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 100; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__cs_duration__read; + counter->name = "CS Duration"; + counter->desc = "Total Compute Shader GPU duration."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__render_basic__sampler0_busy__read; + counter->name = "Sampler 0 Busy"; + counter->desc = "The percentage of time in which sampler 0 was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__render_basic__sampler1_busy__read; + counter->name = "Sampler 1 Busy"; + counter->desc = "The percentage of time in which sampler 1 was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 140; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__render_basic__samplers_busy__read; + counter->name = "Samplers Busy"; + counter->desc = "The percentage of time in which samplers were busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__ds_duration__read; + counter->name = "TES Duration"; + counter->desc = "Total Evaluation Shader GPU duration."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__gti_vf_throughput__read; + counter->name = "GTI Fixed Pipe Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between 3D Pipeline (Command Dispatch, Input Assembly and Stream Output) and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__gti_read_throughput__read; + counter->name = "GTI Read Throughput"; + counter->desc = "The total number of GPU memory bytes read from GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__cs_eu_active_per_thread__read; + counter->name = "CS AVG Active per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which compute shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 100.0; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__render_basic__sampler0_bottleneck__read; + counter->name = "Sampler 0 Bottleneck"; + counter->desc = "The percentage of time in which sampler 0 was bottlenecks."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__gs_eu_stall_per_thread__read; + counter->name = "GS AVG Stall per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which geometry shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__sampler0_texels__read; + counter->name = "Sampler 0 Texels LOD0"; + counter->desc = "The total number of texels lookups in LOD0 in sampler 0 unit."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__sampler1_texels__read; + counter->name = "Sampler 1 Texels LOD0"; + counter->desc = "The total number of texels lookups in LOD0 in sampler 1 unit."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__sampler_texels__read; + counter->name = "Sampler Texels LOD0"; + counter->desc = "The total number of texels lookups in LOD0 in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__gs_duration__read; + counter->name = "GS Duration"; + counter->desc = "Total Geometry Shader GPU duration."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = hsw__render_basic__avg_gpu_core_frequency__max(brw); + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__render_basic__eu_idle__read; + counter->name = "EU Idle"; + counter->desc = "The percentage of time in which the Execution Units were idle."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 248; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__gti_depth_throughput__read; + counter->name = "GTI Depth Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between depth caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__gti_write_throughput__read; + counter->name = "GTI Write Throughput"; + counter->desc = "The total number of GPU memory bytes written to GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__ps_eu_stall_per_thread__read; + counter->name = "FS AVG Stall per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which fragment shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__gti_l3_throughput__read; + counter->name = "GTI L3 Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__vs_eu_stall_per_thread__read; + counter->name = "VS AVG Stall per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which vertex shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__render_basic__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has being processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 304; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__ps_eu_active_per_thread__read; + counter->name = "FS AVG Active per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which fragment shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 100.0; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__hs_duration__read; + counter->name = "TCS Duration"; + counter->desc = "Total Control Shader GPU duration."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 328; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__ds_eu_stall_per_thread__read; + counter->name = "TES AVG Stall per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which evaluation shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 336; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__gs_eu_active_per_thread__read; + counter->name = "GS AVG Active per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which geometry shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 100.0; + counter->offset = 344; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__hs_threads__read; + counter->name = "TCS Threads Dispatched"; + counter->desc = "The total number of control shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 352; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__hs_eu_stall_per_thread__read; + counter->name = "TCS AVG Stall per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which control shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 360; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 368; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__post_ps_depth_test_fails__read; + counter->name = "Late Depth Test Fails"; + counter->desc = "The total number of pixels dropped on post-FS depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 376; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__render_basic__sampler_bottleneck__read; + counter->name = "Sampler Bottleneck"; + counter->desc = "The percentage of time in which samplers were bottlenecks."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 384; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__hs_eu_active_per_thread__read; + counter->name = "TCS AVG Active per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which control shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 100.0; + counter->offset = 392; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__ps_duration__read; + counter->name = "FS Duration"; + counter->desc = "Total Fragment Shader GPU duration."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 400; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 408; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__cs_eu_stall_per_thread__read; + counter->name = "CS AVG Stall per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which compute shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 416; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__post_ps_stencil_test_fails__read; + counter->name = "Late Stencil Test Fails"; + counter->desc = "The total number of pixels dropped on post-FS stencil test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 424; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__gti_rcc_throughput__read; + counter->name = "GTI RCC Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between render color caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 432; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__l3_sampler_throughput__read; + counter->name = "L3 Sampler Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 440; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__vs_eu_active_per_thread__read; + counter->name = "VS AVG Active per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which vertex shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 100.0; + counter->offset = 448; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__vs_duration__read; + counter->name = "VS Duration"; + counter->desc = "Total Vertex Shader GPU duration."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 456; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__render_basic__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 464; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog hsw_compute_basic_mux_regs[33]; +static struct brw_perf_query_register_prog hsw_compute_basic_b_counter_regs[17]; + +static struct brw_perf_query_counter hsw_compute_basic_query_counters[50]; +static struct brw_perf_query_info hsw_compute_basic_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics Basic Gen7.5", + .guid = "39ad14bc-2380-45c4-91eb-fbcb3aa7ae7b", + .counters = hsw_compute_basic_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A45_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .a_offset = 1, + .b_offset = 46, + .c_offset = 54, + .mux_regs = hsw_compute_basic_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = hsw_compute_basic_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ +}; + +static void +hsw_register_compute_basic_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &hsw_compute_basic_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000253A4, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0002681C, .val = 0x01F00800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026820, .val = 0x00001000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0002781C, .val = 0x01F00800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026520, .val = 0x00000007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000265A0, .val = 0x00000007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025380, .val = 0x00000010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0002538C, .val = 0x00300000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025384, .val = 0xAA8AAAAA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025404, .val = 0xFFFFFFFF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026800, .val = 0x00004202 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026808, .val = 0x00605817 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0002680C, .val = 0x10001005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026804, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00027800, .val = 0x00000102 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00027808, .val = 0x0C0701E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0002780C, .val = 0x000200A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00027804, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026484, .val = 0x44000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026704, .val = 0x44000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026500, .val = 0x00000006 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026510, .val = 0x00000001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026504, .val = 0x88000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026580, .val = 0x00000006 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026590, .val = 0x00000020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026584, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026104, .val = 0x55822222 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026184, .val = 0xAA866666 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025420, .val = 0x08320C83 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025424, .val = 0x06820C83 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0002541C, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025428, .val = 0x00000C03 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002718, .val = 0xAAAAAAAA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000271C, .val = 0xAAAAAAAA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002728, .val = 0xAAAAAAAA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000272C, .val = 0xAAAAAAAA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002748, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002758, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000236C, .val = 0x00000000 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_basic__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__compute_basic__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__compute_basic__ds_eu_stall__read; + counter->name = "TES EU Stall"; + counter->desc = "The percentage of time in which evaluation shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_basic__typed_bytes_written__read; + counter->name = "Typed Bytes Written"; + counter->desc = "The total number of untyped memory bytes written via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_basic__alpha_test_fails__read; + counter->name = "Alpha Test Fails"; + counter->desc = "The total number of pixels dropped on post-FS alpha test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_basic__hs_threads__read; + counter->name = "TCS Threads Dispatched"; + counter->desc = "The total number of control shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_basic__hs_eu_active_per_thread__read; + counter->name = "TCS AVG Active per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which control shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_basic__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__compute_basic__gs_eu_stall__read; + counter->name = "GS EU Stall"; + counter->desc = "The percentage of time in which geometry shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_basic__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_basic__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_basic__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_basic__cs_eu_active_per_thread__read; + counter->name = "CS AVG Active per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which compute shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 100.0; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_basic__untyped_bytes_read__read; + counter->name = "Untyped Bytes Read"; + counter->desc = "The total number of typed memory bytes read via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_basic__gs_eu_stall_per_thread__read; + counter->name = "GS AVG Stall per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which geometry shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_basic__typed_atomics__read; + counter->name = "Typed Atomics"; + counter->desc = "The total number of typed atomics."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_basic__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_basic__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = hsw__compute_basic__avg_gpu_core_frequency__max(brw); + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_basic__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_basic__ps_eu_stall_per_thread__read; + counter->name = "FS AVG Stall per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which fragment shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__compute_basic__ds_eu_active__read; + counter->name = "TES EU Active"; + counter->desc = "The percentage of time in which evaluation shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_basic__vs_eu_stall_per_thread__read; + counter->name = "VS AVG Stall per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which vertex shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__compute_basic__hs_eu_stall__read; + counter->name = "TCS EU Stall"; + counter->desc = "The percentage of time in which control shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__compute_basic__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has being processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 172; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_basic__ps_eu_active_per_thread__read; + counter->name = "FS AVG Active per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which fragment shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_basic__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_basic__ds_threads__read; + counter->name = "TES Threads Dispatched"; + counter->desc = "The total number of evaluation shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_basic__ds_eu_active_per_thread__read; + counter->name = "TES AVG Active per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which evaluation shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__compute_basic__gs_eu_active__read; + counter->name = "GS EU Active"; + counter->desc = "The percentage of time in which geometry shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 208; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__compute_basic__ps_eu_active__read; + counter->name = "FS EU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 212; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_basic__ds_eu_stall_per_thread__read; + counter->name = "TES AVG Stall per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which evaluation shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_basic__gs_eu_active_per_thread__read; + counter->name = "GS AVG Active per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which geometry shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 100.0; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_basic__untyped_bytes_written__read; + counter->name = "Untyped Writes"; + counter->desc = "The total number of untyped memory bytes written via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_basic__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of byten written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_basic__hs_eu_stall_per_thread__read; + counter->name = "TCS AVG Stall per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which control shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__compute_basic__hs_eu_active__read; + counter->name = "TCS EU Active"; + counter->desc = "The percentage of time in which control shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 256; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_basic__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_basic__post_ps_depth_test_fails__read; + counter->name = "Late Depth Test Fails"; + counter->desc = "The total number of pixels dropped on post-FS depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__compute_basic__ps_eu_stall__read; + counter->name = "FS EU Stall"; + counter->desc = "The percentage of time in which fragment shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 280; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__compute_basic__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 284; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_basic__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__compute_basic__vs_eu_active__read; + counter->name = "VS EU Active"; + counter->desc = "The percentage of time in which vertex shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 296; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__compute_basic__cs_eu_active__read; + counter->name = "CS EU Active"; + counter->desc = "The percentage of time in which compute shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 300; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_basic__cs_eu_stall_per_thread__read; + counter->name = "CS AVG Stall per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which compute shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_basic__post_ps_stencil_test_fails__read; + counter->name = "Late Stencil Test Fails"; + counter->desc = "The total number of pixels dropped on post-FS stencil test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_basic__vs_eu_active_per_thread__read; + counter->name = "VS AVG Active per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which vertex shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 100.0; + counter->offset = 320; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__compute_basic__cs_eu_stall__read; + counter->name = "CS EU Stall"; + counter->desc = "The percentage of time in which compute shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 328; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_basic__typed_bytes_read__read; + counter->name = "Typed Bytes Read"; + counter->desc = "The total number of typed memory bytes read via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 336; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_basic__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 344; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__compute_basic__vs_eu_stall__read; + counter->name = "VS EU Stall"; + counter->desc = "The percentage of time in which vertex shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 352; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog hsw_compute_extended_mux_regs[16]; +static struct brw_perf_query_register_prog hsw_compute_extended_b_counter_regs[20]; + +static struct brw_perf_query_counter hsw_compute_extended_query_counters[20]; +static struct brw_perf_query_info hsw_compute_extended_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics Extended Gen7.5", + .guid = "3865be28-6982-49fe-9494-e4d1b4795413", + .counters = hsw_compute_extended_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A45_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .a_offset = 1, + .b_offset = 46, + .c_offset = 54, + .mux_regs = hsw_compute_extended_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = hsw_compute_extended_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ +}; + +static void +hsw_register_compute_extended_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &hsw_compute_extended_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0002681C, .val = 0x3EB00800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026820, .val = 0x00900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025384, .val = 0x02AAAAAA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025404, .val = 0x03FFFFFF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026800, .val = 0x00142284 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026808, .val = 0x0E629062 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0002680C, .val = 0x3F6F55CB }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026810, .val = 0x00000014 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026804, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026104, .val = 0x02AAAAAA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026184, .val = 0x02AAAAAA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025420, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025424, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0002541C, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025428, .val = 0x00000000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FE2A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FE6A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007FE92 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007FEA2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FE32 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FE9A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007FF23 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007FFF3 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FFFE }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_extended__eu_untyped_writes0__read; + counter->name = "EuUntypedWrites0"; + counter->desc = "The subslice 0 EU Untyped Writes subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_extended__untyped_writes0__read; + counter->name = "Untyped Writes 0"; + counter->desc = "The subslice 0 untyped writes (including SLM writes)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 8; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__compute_extended__untyped_writes_per_cache_line__read; + counter->name = "UntypedWritesPerCacheLine"; + counter->desc = "The ratio of EU untyped write requests to L3 cache line writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_extended__typed_reads0__read; + counter->name = "Typed Reads 0"; + counter->desc = "The subslice 0 typed reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_extended__typed_writes0__read; + counter->name = "Typed Writes 0"; + counter->desc = "The subslice 0 typed writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_extended__eu_typed_atomics0__read; + counter->name = "EuTypedAtomics0"; + counter->desc = "The subslice 0 EU Typed Atomics subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_extended__typed_atomics0__read; + counter->name = "Typed Atomics 0"; + counter->desc = "The subslice 0 typed atomics."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__compute_extended__typed_atomics_per_cache_line__read; + counter->name = "TypedAtomicsPerCacheLine"; + counter->desc = "The ratio of EU typed atomics requests to L3 cache line writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_extended__eu_untyped_reads0__read; + counter->name = "EuUntypedReads0"; + counter->desc = "The subslice 0 EU Untyped Reads subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_extended__eu_untyped_atomics0__read; + counter->name = "EuUntypedAtomics0"; + counter->desc = "The subslice 0 EU Untyped Atomics subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_extended__gpu_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_extended__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_extended__eu_typed_writes0__read; + counter->name = "EuTypedWrites0"; + counter->desc = "The subslice 0 EU Typed Writes subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__compute_extended__typed_writes_per_cache_line__read; + counter->name = "TypedWritesPerCacheLine"; + counter->desc = "The ratio of EU typed write requests to L3 cache line writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_extended__eu_typed_reads0__read; + counter->name = "EuTypedReads0"; + counter->desc = "The subslice 0 EU Typed Reads subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_extended__eu_urb_atomics0__read; + counter->name = "EuUrbAtomics0"; + counter->desc = "The subslice 0 EU URB Atomics subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_extended__untyped_reads0__read; + counter->name = "Untyped Reads 0"; + counter->desc = "The subslice 0 untyped reads (including SLM reads)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__compute_extended__untyped_reads_per_cache_line__read; + counter->name = "UntypedReadsPerCacheLine"; + counter->desc = "The ratio of EU untyped read requests to L3 cache line reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__compute_extended__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__compute_extended__typed_reads_per_cache_line__read; + counter->name = "TypedReadsPerCacheLine"; + counter->desc = "The ratio of EU typed read requests to L3 cache line reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog hsw_memory_reads_mux_regs[19]; +static struct brw_perf_query_register_prog hsw_memory_reads_b_counter_regs[28]; + +static struct brw_perf_query_counter hsw_memory_reads_query_counters[54]; +static struct brw_perf_query_info hsw_memory_reads_query = { + .kind = OA_COUNTERS, + .name = "Memory Reads Distribution Gen7.5", + .guid = "bb5ed49b-2497-4095-94f6-26ba294db88a", + .counters = hsw_memory_reads_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A45_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .a_offset = 1, + .b_offset = 46, + .c_offset = 54, + .mux_regs = hsw_memory_reads_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = hsw_memory_reads_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ +}; + +static void +hsw_register_memory_reads_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &hsw_memory_reads_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000253A4, .val = 0x34300000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025440, .val = 0x2D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025444, .val = 0x00000008 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025128, .val = 0x0E600000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025380, .val = 0x00000450 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025390, .val = 0x00052C43 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025384, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025400, .val = 0x00006144 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025408, .val = 0x0A418820 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0002540C, .val = 0x000820E6 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025404, .val = 0xFF500000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025100, .val = 0x000005D6 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0002510C, .val = 0x0EF00000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025104, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025420, .val = 0x02108421 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025424, .val = 0x00008421 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0002541C, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025428, .val = 0x00000000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x76543298 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002748, .val = 0x98989898 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x000000E4 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x98A98A98 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002758, .val = 0x88888888 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002754, .val = 0x000C5500 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FC00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FC00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F872 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FC00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FC00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FC00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FC00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FC00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FC00 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__memory_reads__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__memory_reads__ds_eu_stall__read; + counter->name = "TES EU Stall"; + counter->desc = "The percentage of time in which evaluation shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__alpha_test_fails__read; + counter->name = "Alpha Test Fails"; + counter->desc = "The total number of pixels dropped on post-FS alpha test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__ds_threads__read; + counter->name = "TES Threads Dispatched"; + counter->desc = "The total number of evaluation shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__ds_eu_active_per_thread__read; + counter->name = "TES AVG Active per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which evaluation shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__memory_reads__gs_eu_stall__read; + counter->name = "GS EU Stall"; + counter->desc = "The percentage of time in which geometry shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__llc_read_accesses__read; + counter->name = "LLC GPU Read Accesses"; + counter->desc = "The total number of LLC cache lookups for reads done from the GPU."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__gti_memory_reads__read; + counter->name = "GtiMemoryReads"; + counter->desc = "The total number of GTI memory reads (64B each)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__cs_eu_active_per_thread__read; + counter->name = "CS AVG Active per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which compute shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 100.0; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__gti_rcz_memory_reads__read; + counter->name = "GtiRczMemoryReads"; + counter->desc = "The total number of GTI memory reads from Render Depth Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__gs_eu_stall_per_thread__read; + counter->name = "GS AVG Stall per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which geometry shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = hsw__memory_reads__avg_gpu_core_frequency__max(brw); + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__gti_rcc_memory_reads__read; + counter->name = "GtiRccMemoryReads"; + counter->desc = "The total number of GTI memory reads from Render Color Cache (Render Color Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__ps_eu_stall_per_thread__read; + counter->name = "FS AVG Stall per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which fragment shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__memory_reads__ds_eu_active__read; + counter->name = "TES EU Active"; + counter->desc = "The percentage of time in which evaluation shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__vs_eu_stall_per_thread__read; + counter->name = "VS AVG Stall per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which vertex shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__memory_reads__hs_eu_stall__read; + counter->name = "TCS EU Stall"; + counter->desc = "The percentage of time in which control shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__memory_reads__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has being processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 172; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__ps_eu_active_per_thread__read; + counter->name = "FS AVG Active per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which fragment shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__gti_cmd_streamer_memory_reads__read; + counter->name = "GtiCmdStreamerMemoryReads"; + counter->desc = "The total number of GTI memory reads from Command Streamer."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__memory_reads__gs_eu_active__read; + counter->name = "GS EU Active"; + counter->desc = "The percentage of time in which geometry shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__memory_reads__ps_eu_active__read; + counter->name = "FS EU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 204; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__ds_eu_stall_per_thread__read; + counter->name = "TES AVG Stall per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which evaluation shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__gs_eu_active_per_thread__read; + counter->name = "GS AVG Active per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which geometry shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 100.0; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__gti_hi_depth_memory_reads__read; + counter->name = "GtiHiDepthMemoryReads"; + counter->desc = "The total number of GTI memory reads from Hierarchical Depth Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__hs_threads__read; + counter->name = "TCS Threads Dispatched"; + counter->desc = "The total number of control shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__hs_eu_stall_per_thread__read; + counter->name = "TCS AVG Stall per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which control shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__memory_reads__hs_eu_active__read; + counter->name = "TCS EU Active"; + counter->desc = "The percentage of time in which control shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 248; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__post_ps_depth_test_fails__read; + counter->name = "Late Depth Test Fails"; + counter->desc = "The total number of pixels dropped on post-FS depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__hs_eu_active_per_thread__read; + counter->name = "TCS AVG Active per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which control shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 100.0; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__memory_reads__ps_eu_stall__read; + counter->name = "FS EU Stall"; + counter->desc = "The percentage of time in which fragment shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 280; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__memory_reads__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 284; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__gti_msc_memory_reads__read; + counter->name = "GtiMscMemoryReads"; + counter->desc = "The total number of GTI memory reads from Multisampling Color Cache (Multisampling Color Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__memory_reads__vs_eu_active__read; + counter->name = "VS EU Active"; + counter->desc = "The percentage of time in which vertex shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 304; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__memory_reads__cs_eu_active__read; + counter->name = "CS EU Active"; + counter->desc = "The percentage of time in which compute shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 308; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__cs_eu_stall_per_thread__read; + counter->name = "CS AVG Stall per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which compute shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__gti_vf_memory_reads__read; + counter->name = "GtiVfMemoryReads"; + counter->desc = "The total number of GTI memory reads from Vertex Fetch."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__post_ps_stencil_test_fails__read; + counter->name = "Late Stencil Test Fails"; + counter->desc = "The total number of pixels dropped on post-FS stencil test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 328; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__gti_stc_memory_reads__read; + counter->name = "GtiStcMemoryReads"; + counter->desc = "The total number of GTI memory reads from Stencil Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 336; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__vs_eu_active_per_thread__read; + counter->name = "VS AVG Active per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which vertex shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 100.0; + counter->offset = 344; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__gti_rs_memory_reads__read; + counter->name = "GtiRsMemoryReads"; + counter->desc = "The total number of GTI memory reads from Resource Streamer."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 352; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__memory_reads__cs_eu_stall__read; + counter->name = "CS EU Stall"; + counter->desc = "The percentage of time in which compute shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 360; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 368; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_reads__gti_l3_reads__read; + counter->name = "GtiL3Reads"; + counter->desc = "The total number of GTI memory reads from L3 (L3 misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 376; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__memory_reads__vs_eu_stall__read; + counter->name = "VS EU Stall"; + counter->desc = "The percentage of time in which vertex shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 384; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog hsw_memory_writes_mux_regs[19]; +static struct brw_perf_query_register_prog hsw_memory_writes_b_counter_regs[28]; + +static struct brw_perf_query_counter hsw_memory_writes_query_counters[53]; +static struct brw_perf_query_info hsw_memory_writes_query = { + .kind = OA_COUNTERS, + .name = "Memory Writes Distribution Gen7.5", + .guid = "3358d639-9b5f-45ab-976d-9b08cbfc6240", + .counters = hsw_memory_writes_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A45_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .a_offset = 1, + .b_offset = 46, + .c_offset = 54, + .mux_regs = hsw_memory_writes_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = hsw_memory_writes_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ +}; + +static void +hsw_register_memory_writes_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &hsw_memory_writes_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000253A4, .val = 0x34300000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025440, .val = 0x01500000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025444, .val = 0x00000120 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025128, .val = 0x0C200000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025380, .val = 0x00000450 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025390, .val = 0x00052C43 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025384, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025400, .val = 0x00007184 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025408, .val = 0x0A418820 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0002540C, .val = 0x000820E6 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025404, .val = 0xFF500000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025100, .val = 0x000005D6 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0002510C, .val = 0x1E700000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025104, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025420, .val = 0x02108421 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025424, .val = 0x00008421 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0002541C, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025428, .val = 0x00000000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x76543298 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002748, .val = 0x98989898 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x000000E4 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000275C, .val = 0xBABABABA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002758, .val = 0x88888888 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002754, .val = 0x000C5500 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FC00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FC00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F822 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FC00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FC00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FC00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FC00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FC00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FC00 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_writes__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__memory_writes__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__memory_writes__ds_eu_stall__read; + counter->name = "TES EU Stall"; + counter->desc = "The percentage of time in which evaluation shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_writes__alpha_test_fails__read; + counter->name = "Alpha Test Fails"; + counter->desc = "The total number of pixels dropped on post-FS alpha test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_writes__ds_threads__read; + counter->name = "TES Threads Dispatched"; + counter->desc = "The total number of evaluation shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_writes__ds_eu_active_per_thread__read; + counter->name = "TES AVG Active per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which evaluation shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_writes__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__memory_writes__gs_eu_stall__read; + counter->name = "GS EU Stall"; + counter->desc = "The percentage of time in which geometry shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_writes__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_writes__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_writes__gti_msc_memory_writes__read; + counter->name = "GtiMscMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Multisampling Color Cache (Multisampling Color Cache invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_writes__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_writes__cs_eu_active_per_thread__read; + counter->name = "CS AVG Active per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which compute shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 100.0; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_writes__gti_cmd_streamer_memory_writes__read; + counter->name = "GtiCmdStreamerMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Command Streamer."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_writes__gs_eu_stall_per_thread__read; + counter->name = "GS AVG Stall per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which geometry shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_writes__gti_l3_writes__read; + counter->name = "GtiL3Writes"; + counter->desc = "The total number of GTI memory writes from L3 (L3 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_writes__gti_hiz_memory_writes__read; + counter->name = "GtiHizMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Hierarchical Depth Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_writes__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_writes__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = hsw__memory_writes__avg_gpu_core_frequency__max(brw); + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_writes__ps_eu_stall_per_thread__read; + counter->name = "FS AVG Stall per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which fragment shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_writes__gti_rcc_memory_writes__read; + counter->name = "GtiRccMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Render Color Cache (Render Color Cache invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__memory_writes__ds_eu_active__read; + counter->name = "TES EU Active"; + counter->desc = "The percentage of time in which evaluation shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_writes__vs_eu_stall_per_thread__read; + counter->name = "VS AVG Stall per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which vertex shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__memory_writes__hs_eu_stall__read; + counter->name = "TCS EU Stall"; + counter->desc = "The percentage of time in which control shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__memory_writes__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has being processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 180; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_writes__ps_eu_active_per_thread__read; + counter->name = "FS AVG Active per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which fragment shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 100.0; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_writes__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_writes__llc_wr_accesses__read; + counter->name = "LLC GPU Write Accesses"; + counter->desc = "The total number of LLC cache lookups for write done from the GPU (32B writes)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__memory_writes__gs_eu_active__read; + counter->name = "GS EU Active"; + counter->desc = "The percentage of time in which geometry shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 208; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__memory_writes__ps_eu_active__read; + counter->name = "FS EU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 212; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_writes__gti_stc_memory_writes__read; + counter->name = "GtiStcMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Stencil Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_writes__ds_eu_stall_per_thread__read; + counter->name = "TES AVG Stall per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which evaluation shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_writes__gs_eu_active_per_thread__read; + counter->name = "GS AVG Active per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which geometry shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 100.0; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_writes__hs_threads__read; + counter->name = "TCS Threads Dispatched"; + counter->desc = "The total number of control shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_writes__hs_eu_stall_per_thread__read; + counter->name = "TCS AVG Stall per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which control shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__memory_writes__hs_eu_active__read; + counter->name = "TCS EU Active"; + counter->desc = "The percentage of time in which control shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 256; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_writes__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_writes__post_ps_depth_test_fails__read; + counter->name = "Late Depth Test Fails"; + counter->desc = "The total number of pixels dropped on post-FS depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_writes__hs_eu_active_per_thread__read; + counter->name = "TCS AVG Active per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which control shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 100.0; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__memory_writes__ps_eu_stall__read; + counter->name = "FS EU Stall"; + counter->desc = "The percentage of time in which fragment shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 288; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__memory_writes__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 292; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_writes__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__memory_writes__vs_eu_active__read; + counter->name = "VS EU Active"; + counter->desc = "The percentage of time in which vertex shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 304; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__memory_writes__cs_eu_active__read; + counter->name = "CS EU Active"; + counter->desc = "The percentage of time in which compute shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 308; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_writes__cs_eu_stall_per_thread__read; + counter->name = "CS AVG Stall per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which compute shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_writes__post_ps_stencil_test_fails__read; + counter->name = "Late Stencil Test Fails"; + counter->desc = "The total number of pixels dropped on post-FS stencil test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_writes__gti_so_memory_writes__read; + counter->name = "GtiSoMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Stream Output."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 328; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_writes__vs_eu_active_per_thread__read; + counter->name = "VS AVG Active per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which vertex shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 100.0; + counter->offset = 336; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_writes__gti_rcz_memory_writes__read; + counter->name = "GtiRczMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Render Depth Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 344; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__memory_writes__cs_eu_stall__read; + counter->name = "CS EU Stall"; + counter->desc = "The percentage of time in which compute shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 352; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_writes__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 360; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__memory_writes__gti_memory_writes__read; + counter->name = "GtiMemoryWrites"; + counter->desc = "The total number of GTI memory writes (64B each)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 368; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__memory_writes__vs_eu_stall__read; + counter->name = "VS EU Stall"; + counter->desc = "The percentage of time in which vertex shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 376; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog hsw_sampler_balance_mux_regs[41]; +static struct brw_perf_query_register_prog hsw_sampler_balance_b_counter_regs[6]; + +static struct brw_perf_query_counter hsw_sampler_balance_query_counters[55]; +static struct brw_perf_query_info hsw_sampler_balance_query = { + .kind = OA_COUNTERS, + .name = "Metric set SamplerBalance", + .guid = "bc274488-b4b6-40c7-90da-b77d7ad16189", + .counters = hsw_sampler_balance_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A45_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .a_offset = 1, + .b_offset = 46, + .c_offset = 54, + .mux_regs = hsw_sampler_balance_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = hsw_sampler_balance_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ +}; + +static void +hsw_register_sampler_balance_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &hsw_sampler_balance_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0002EB9C, .val = 0x01906400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0002FB9C, .val = 0x01906400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000253A4, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026B9C, .val = 0x01906400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00027B9C, .val = 0x01906400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00027104, .val = 0x00A00000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00027184, .val = 0x00A50000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0002E804, .val = 0x00500000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0002E984, .val = 0x00500000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0002EB04, .val = 0x00500000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0002EB80, .val = 0x00000084 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0002EB8C, .val = 0x14200000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0002EB84, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0002F804, .val = 0x00050000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0002F984, .val = 0x00050000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0002FB04, .val = 0x00050000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0002FB80, .val = 0x00000084 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0002FB8C, .val = 0x00050800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0002FB84, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025380, .val = 0x00000010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0002538C, .val = 0x000000C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025384, .val = 0xAA550000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025404, .val = 0xFFFFC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026804, .val = 0x50000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026984, .val = 0x50000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026B04, .val = 0x50000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026B80, .val = 0x00000084 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026B90, .val = 0x00050800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026B84, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00027804, .val = 0x05000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00027984, .val = 0x05000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00027B04, .val = 0x05000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00027B80, .val = 0x00000084 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00027B90, .val = 0x00000142 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00027B84, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026104, .val = 0xA0000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00026184, .val = 0xA5000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025424, .val = 0x00008620 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0002541C, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00025428, .val = 0x0004A54A }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__sampler_balance__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__sampler_balance__ds_eu_stall__read; + counter->name = "TES EU Stall"; + counter->desc = "The percentage of time in which evaluation shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x8) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__sampler3_l2_cache_misses__read; + counter->name = "Sampler L2 cache misses (ss3)"; + counter->desc = "Number of sampler L2 cache misses (ss3)"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__alpha_test_fails__read; + counter->name = "Alpha Test Fails"; + counter->desc = "The total number of pixels dropped on post-FS alpha test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__ds_threads__read; + counter->name = "TES Threads Dispatched"; + counter->desc = "The total number of evaluation shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__ds_eu_active_per_thread__read; + counter->name = "TES AVG Active per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which evaluation shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__sampler_balance__gs_eu_stall__read; + counter->name = "GS EU Stall"; + counter->desc = "The percentage of time in which geometry shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__sampler_balance__cs_eu_active__read; + counter->name = "CS EU Active"; + counter->desc = "The percentage of time in which compute shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 60; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__sampler_balance__vs_eu_active__read; + counter->name = "VS EU Active"; + counter->desc = "The percentage of time in which vertex shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__sampler_balance__hs_eu_active__read; + counter->name = "TCS EU Active"; + counter->desc = "The percentage of time in which control shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 68; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__sampler_balance__ds_eu_active__read; + counter->name = "TES EU Active"; + counter->desc = "The percentage of time in which evaluation shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 72; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__sampler_balance__gs_eu_active__read; + counter->name = "GS EU Active"; + counter->desc = "The percentage of time in which geometry shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 76; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__sampler_balance__ps_eu_active__read; + counter->name = "FS EU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 80; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__sampler_balance__cs_eu_stall__read; + counter->name = "CS EU Stall"; + counter->desc = "The percentage of time in which compute shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 84; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__sampler_balance__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 88; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__sampler_balance__vs_eu_stall__read; + counter->name = "VS EU Stall"; + counter->desc = "The percentage of time in which vertex shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 92; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__sampler_balance__hs_eu_stall__read; + counter->name = "TCS EU Stall"; + counter->desc = "The percentage of time in which control shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 96; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__sampler_balance__ps_eu_stall__read; + counter->name = "FS EU Stall"; + counter->desc = "The percentage of time in which fragment shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 100; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__cs_duration__read; + counter->name = "CS Duration"; + counter->desc = "Total Compute Shader GPU duration."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__ds_duration__read; + counter->name = "TES Duration"; + counter->desc = "Total Evaluation Shader GPU duration."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__gs_duration__read; + counter->name = "GS Duration"; + counter->desc = "Total Geometry Shader GPU duration."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__cs_eu_active_per_thread__read; + counter->name = "CS AVG Active per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which compute shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__sampler_l2_cache_misses__read; + counter->name = "Sampler L2 cache misses"; + counter->desc = "Number of sampler L2 cache misses"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__gs_eu_stall_per_thread__read; + counter->name = "GS AVG Stall per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which geometry shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__sampler2_l2_cache_misses__read; + counter->name = "Sampler L2 cache misses (ss2)"; + counter->desc = "Number of sampler L2 cache misses (ss2)"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = hsw__sampler_balance__avg_gpu_core_frequency__max(brw); + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__sampler_balance__eu_idle__read; + counter->name = "EU Idle"; + counter->desc = "The percentage of time in which the Execution Units were idle."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__ps_eu_stall_per_thread__read; + counter->name = "FS AVG Stall per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which fragment shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__vs_eu_stall_per_thread__read; + counter->name = "VS AVG Stall per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which vertex shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = hsw__sampler_balance__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has being processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 224; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__ps_eu_active_per_thread__read; + counter->name = "FS AVG Active per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which fragment shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 100.0; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__hs_duration__read; + counter->name = "TCS Duration"; + counter->desc = "Total Control Shader GPU duration."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__ds_eu_stall_per_thread__read; + counter->name = "TES AVG Stall per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which evaluation shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__gs_eu_active_per_thread__read; + counter->name = "GS AVG Active per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which geometry shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 100.0; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__hs_threads__read; + counter->name = "TCS Threads Dispatched"; + counter->desc = "The total number of control shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__hs_eu_stall_per_thread__read; + counter->name = "TCS AVG Stall per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which control shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__post_ps_depth_test_fails__read; + counter->name = "Late Depth Test Fails"; + counter->desc = "The total number of pixels dropped on post-FS depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__hs_eu_active_per_thread__read; + counter->name = "TCS AVG Active per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which control shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 100.0; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__ps_duration__read; + counter->name = "FS Duration"; + counter->desc = "Total Fragment Shader GPU duration."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__sampler1_l2_cache_misses__read; + counter->name = "Sampler L2 cache misses (ss1)"; + counter->desc = "Number of sampler L2 cache misses (ss1)"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 328; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__cs_eu_stall_per_thread__read; + counter->name = "CS AVG Stall per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which compute shaders were stalled on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 336; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__post_ps_stencil_test_fails__read; + counter->name = "Late Stencil Test Fails"; + counter->desc = "The total number of pixels dropped on post-FS stencil test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 344; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__sampler0_l2_cache_misses__read; + counter->name = "Sampler L2 cache misses (ss0)"; + counter->desc = "Number of sampler L2 cache misses (ss0)"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 352; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__vs_eu_active_per_thread__read; + counter->name = "VS AVG Active per Thread"; + counter->desc = "The average number of cycles per hardware thread run in which vertex shaders were processed actively on the EUs."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 100.0; + counter->offset = 360; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__vs_duration__read; + counter->name = "VS Duration"; + counter->desc = "Total Vertex Shader GPU duration."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 368; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = hsw__sampler_balance__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 376; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +void +brw_oa_register_queries_hsw(struct brw_context *brw) +{ + hsw_register_render_basic_counter_query(brw); + hsw_register_compute_basic_counter_query(brw); + hsw_register_compute_extended_counter_query(brw); + hsw_register_memory_reads_counter_query(brw); + hsw_register_memory_writes_counter_query(brw); + hsw_register_sampler_balance_counter_query(brw); +} + +static struct brw_perf_query_register_prog bdw_render_basic_mux_regs[219]; +static struct brw_perf_query_register_prog bdw_render_basic_b_counter_regs[5]; +static struct brw_perf_query_register_prog bdw_render_basic_flex_regs[7]; + +static struct brw_perf_query_counter bdw_render_basic_query_counters[52]; +static struct brw_perf_query_info bdw_render_basic_query = { + .kind = OA_COUNTERS, + .name = "Render Metrics Basic Gen8", + .guid = "b541bd57-0e0f-4154-b4c0-5858010a2bf7", + .counters = bdw_render_basic_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bdw_render_basic_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bdw_render_basic_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = bdw_render_basic_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +bdw_register_render_basic_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bdw_render_basic_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143F000F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14110014 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14310014 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14BF000F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118A0317 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13837BE0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3B800060 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x183D0800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A3F0023 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x103F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00584000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08584000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5A4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x185B2400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1F0800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1FAA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18380001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00392000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06398000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0839A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A391000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00104000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08104000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00110030 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08110031 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10110000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00134000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16130020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06308000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08308000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06311800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08311880 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10310000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E334000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16330080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ABF1180 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10BF0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ADA8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A9D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB94000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A0380 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A000E }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8A00A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B2820 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B2550 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAA0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D831021 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F83572F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01835680 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0383002C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11830000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05830000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0184C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05844000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C137 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C147 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1180C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15804000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D801110 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800331 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800802 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45801465 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53801111 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x478014A5 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800CA5 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + } + + if (brw->perfquery.sys_vars.slice_mask & 0x02) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143F000F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14BF000F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14910014 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14B10014 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118A0317 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13837BE0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3B800060 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A3F0023 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x103F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5A4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A391000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00DC4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06DC8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08DCC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00BD8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18BD0800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ABF1180 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10BF0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08D84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ADA8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00DB4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EDB8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18DB2400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A9D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9F0800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9F2A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16B84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18B80001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B92000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B98000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB94000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00910030 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08910031 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10910000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00934000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16930020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B08000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B08000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B11800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B11880 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B10000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB34000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16B30080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D88B800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A0380 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A000E }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8A0080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B2840 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B26A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178C2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C1100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAA0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D831021 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F83572F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01835680 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0383002C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11830000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05830000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0184C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05844000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C137 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C147 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1180C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15804000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D801550 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800331 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800802 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x458004A1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53805555 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800421 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F801421 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800845 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + } + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_basic__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__render_basic__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_basic__l3_misses__read; + counter->name = "L3 Misses"; + counter->desc = "The total number of L3 misses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_basic__gti_l3_throughput__read; + counter->name = "GTI L3 Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__render_basic__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_basic__sampler_l1_misses__read; + counter->name = "Sampler Cache Misses"; + counter->desc = "The total number of sampler cache misses in all LODs in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__render_basic__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x12) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__render_basic__sampler1_bottleneck__read; + counter->name = "Sampler 1 Bottleneck"; + counter->desc = "The percentage of time in which Sampler 1 has been slowing down the pipe when processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 52; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__render_basic__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_basic__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_basic__l3_sampler_throughput__read; + counter->name = "L3 Sampler Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_basic__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__render_basic__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 88; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_basic__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_basic__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x09) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__render_basic__sampler0_busy__read; + counter->name = "Sampler 0 Busy"; + counter->desc = "The percentage of time in which Sampler 0 has been processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 112; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x12) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__render_basic__sampler1_busy__read; + counter->name = "Sampler 1 Busy"; + counter->desc = "The percentage of time in which Sampler 1 has been processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 116; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__render_basic__samplers_busy__read; + counter->name = "Samplers Busy"; + counter->desc = "The percentage of time in which samplers have been processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 120; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_basic__gti_vf_throughput__read; + counter->name = "GTI Fixed Pipe Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between 3D Pipeline (Command Dispatch, Input Assembly and Stream Output) and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_basic__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x09) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__render_basic__sampler0_bottleneck__read; + counter->name = "Sampler 0 Bottleneck"; + counter->desc = "The percentage of time in which Sampler 0 has been slowing down the pipe when processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_basic__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_basic__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_basic__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_basic__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bdw__render_basic__avg_gpu_core_frequency__max(brw); + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_basic__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_basic__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_basic__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_basic__l3_lookups__read; + counter->name = "L3 Lookup Accesses w/o IC"; + counter->desc = "The total number of L3 cache lookup accesses w/o IC."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_basic__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_basic__gti_read_throughput__read; + counter->name = "GTI Read Throughput"; + counter->desc = "The total number of GPU memory bytes read from GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__render_basic__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 232; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__render_basic__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 236; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_basic__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__render_basic__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 248; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_basic__gti_depth_throughput__read; + counter->name = "GTI Depth Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between depth caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__render_basic__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 264; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__render_basic__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 268; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_basic__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_basic__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__render_basic__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 288; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_basic__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_basic__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__render_basic__sampler_bottleneck__read; + counter->name = "Samplers Bottleneck"; + counter->desc = "The percentage of time in which samplers have been slowing down the pipe when processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 312; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_basic__gti_hdc_lookups_throughput__read; + counter->name = "GTI HDC TLB Lookup Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between GTI and HDC, when HDC is doing TLB lookups."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_basic__gti_rcc_throughput__read; + counter->name = "GTI RCC Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between render color caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 328; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_basic__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 336; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_basic__gti_write_throughput__read; + counter->name = "GTI Write Throughput"; + counter->desc = "The total number of GPU memory bytes written to GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 344; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_basic__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 352; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_basic__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 360; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_basic__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 368; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_basic__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 376; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog bdw_compute_basic_mux_regs[182]; +static struct brw_perf_query_register_prog bdw_compute_basic_b_counter_regs[5]; +static struct brw_perf_query_register_prog bdw_compute_basic_flex_regs[7]; + +static struct brw_perf_query_counter bdw_compute_basic_query_counters[39]; +static struct brw_perf_query_info bdw_compute_basic_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics Basic Gen8", + .guid = "35fbc9b2-a891-40a6-a38d-022bb7057552", + .counters = bdw_compute_basic_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bdw_compute_basic_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bdw_compute_basic_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = bdw_compute_basic_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +bdw_register_compute_basic_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bdw_compute_basic_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x105C00E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x105800E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x103800E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3580001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3B800060 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065C2100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5C0041 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5C6600 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005C6580 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00580042 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08582080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C58004C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E582580 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x185B1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5B0104 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1FAA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101F02AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08380042 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A382080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E38404C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0238404B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16380000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18381145 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04380000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0039A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06398000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0839A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A39A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C39A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E39A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02392000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8AAAA0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B02A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B5550 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F850A80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAA0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0184C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03844000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17808137 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C147 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C0E5 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C0E3 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1180C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13804000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00000D24, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D801000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800111 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800062 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800062 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800062 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F801062 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41801084 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + } + + if (brw->perfquery.sys_vars.slice_mask & 0x02) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10DC00E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10D800E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B800E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3580001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3B800060 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06DC2100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ADC0041 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDC6600 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00DC6580 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08DC8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EDC8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D80042 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08D82080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CD8004C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ED82580 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00DB4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18DB1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ADB0104 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9FA800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9FAA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F02AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B80042 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB82080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB8404C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B8404B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16B80000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18B81145 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B80000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B98000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B92000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D88F800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F88000F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B0540 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258BAAA0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178C2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C5500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8C0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F850A80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAA0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0184C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03844000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17808137 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C147 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C0E5 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C0E3 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1180C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13804000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00000D24, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D805000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800555 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800062 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800062 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800062 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800062 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + } + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_basic__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_basic__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_basic__untyped_bytes_read__read; + counter->name = "Untyped Bytes Read"; + counter->desc = "The total number of typed memory bytes read via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_basic__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_basic__typed_bytes_written__read; + counter->name = "Typed Bytes Written"; + counter->desc = "The total number of typed memory bytes written via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_basic__fpu0_active__read; + counter->name = "EU FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_basic__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 44; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_basic__eu_avg_ipc_rate__read; + counter->name = "EU AVG IPC Rate"; + counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 2.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_basic__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_basic__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_basic__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_basic__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_basic__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_basic__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_basic__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_basic__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_basic__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bdw__compute_basic__avg_gpu_core_frequency__max(brw); + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_basic__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_basic__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_basic__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_basic__gti_read_throughput__read; + counter->name = "GTI Read Throughput"; + counter->desc = "The total number of GPU memory bytes read from GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_basic__untyped_bytes_written__read; + counter->name = "Untyped Writes"; + counter->desc = "The total number of untyped memory bytes written via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_basic__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_basic__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_basic__typed_bytes_read__read; + counter->name = "Typed Bytes Read"; + counter->desc = "The total number of typed memory bytes read via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_basic__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_basic__eu_thread_occupancy__read; + counter->name = "EU Thread Occupancy"; + counter->desc = "The percentage of time in which hardware threads occupied EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_basic__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 204; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_basic__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_basic__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_basic__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_basic__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_basic__gti_write_throughput__read; + counter->name = "GTI Write Throughput"; + counter->desc = "The total number of GPU memory bytes written to GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_basic__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_basic__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_basic__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_basic__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_basic__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_basic__eu_send_active__read; + counter->name = "EU Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 288; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog bdw_render_pipe_profile_mux_regs[111]; +static struct brw_perf_query_register_prog bdw_render_pipe_profile_b_counter_regs[21]; +static struct brw_perf_query_register_prog bdw_render_pipe_profile_flex_regs[7]; + +static struct brw_perf_query_counter bdw_render_pipe_profile_query_counters[44]; +static struct brw_perf_query_info bdw_render_pipe_profile_query = { + .kind = OA_COUNTERS, + .name = "Render Metrics for 3D Pipeline Profile", + .guid = "233d0544-fff7-4281-8291-e02f222aff72", + .counters = bdw_render_pipe_profile_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bdw_render_pipe_profile_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bdw_render_pipe_profile_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = bdw_render_pipe_profile_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +bdw_register_render_pipe_profile_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bdw_render_pipe_profile_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1E0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1F000F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10176800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1191001F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B880320 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01890C40 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118A1C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118D7C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118E0020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118F4C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06584000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081E0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1E0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021F5400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101F0010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F0080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06392000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C13C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06164000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06170012 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00170000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01910005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07880002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01880C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F880000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D880000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05880000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09890032 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078A0800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A0A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198A4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8A2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B54C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258BAA55 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B0019 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C0100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8D0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018D1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8DF000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8D3000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038DE000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058D3000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8E0004 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058E000C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098E0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078E0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038E0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8F0020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198F0C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078F8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B900980 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03900D80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAAA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0184C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0784C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1180C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1780C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00000D24, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D801111 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F801011 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800443 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51801111 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800422 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53801111 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800C60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800422 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800021 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFEA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFC }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007AFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F5FD }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00079FFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000F3FB }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007BF7A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F7E7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FEFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000F7CF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00077FFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000EFDF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0006FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000CFBF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0003FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x00005F7F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_pipe_profile__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__render_pipe_profile__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__render_pipe_profile__vs_bottleneck__read; + counter->name = "VS Bottleneck"; + counter->desc = "The percentage of time in which vertex shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__render_pipe_profile__hi_depth_bottleneck__read; + counter->name = "Hi-Depth Bottleneck"; + counter->desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__render_pipe_profile__gs_bottleneck__read; + counter->name = "GS Bottleneck"; + counter->desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_pipe_profile__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_pipe_profile__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_pipe_profile__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_pipe_profile__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__render_pipe_profile__bc_bottleneck__read; + counter->name = "BC Bottleneck"; + counter->desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__render_pipe_profile__hs_stall__read; + counter->name = "HS Stall"; + counter->desc = "The percentage of time in which hull stall pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 60; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_pipe_profile__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_pipe_profile__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_pipe_profile__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_pipe_profile__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_pipe_profile__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bdw__render_pipe_profile__avg_gpu_core_frequency__max(brw); + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_pipe_profile__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_pipe_profile__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__render_pipe_profile__vf_bottleneck__read; + counter->name = "VF Bottleneck"; + counter->desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_pipe_profile__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__render_pipe_profile__sf_bottleneck__read; + counter->name = "Strip-Fans Bottleneck"; + counter->desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_pipe_profile__sampler_accesses__read; + counter->name = "Sampler Accesses"; + counter->desc = "The total number of messages send to samplers."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__render_pipe_profile__sf_stall__read; + counter->name = "SF Stall"; + counter->desc = "The percentage of time in which strip-fans pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__render_pipe_profile__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__render_pipe_profile__hs_bottleneck__read; + counter->name = "HS Bottleneck"; + counter->desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__render_pipe_profile__cl_stall__read; + counter->name = "CL Stall"; + counter->desc = "The percentage of time in which clipper pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 164; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__render_pipe_profile__so_bottleneck__read; + counter->name = "SO Bottleneck"; + counter->desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_pipe_profile__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_pipe_profile__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_pipe_profile__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__render_pipe_profile__ds_bottleneck__read; + counter->name = "DS Bottleneck"; + counter->desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__render_pipe_profile__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 204; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__render_pipe_profile__cl_bottleneck__read; + counter->name = "Clipper Bottleneck"; + counter->desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__render_pipe_profile__ds_stall__read; + counter->name = "DS Stall"; + counter->desc = "The percentage of time in which domain shader pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 212; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__render_pipe_profile__early_depth_bottleneck__read; + counter->name = "Early Depth Bottleneck"; + counter->desc = "The percentage of time in which early depth test pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_pipe_profile__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_pipe_profile__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_pipe_profile__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_pipe_profile__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_pipe_profile__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_pipe_profile__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_pipe_profile__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__render_pipe_profile__so_stall__read; + counter->name = "SO Stall"; + counter->desc = "The percentage of time in which stream-output pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__render_pipe_profile__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog bdw_memory_reads_mux_regs[50]; +static struct brw_perf_query_register_prog bdw_memory_reads_b_counter_regs[28]; +static struct brw_perf_query_register_prog bdw_memory_reads_flex_regs[7]; + +static struct brw_perf_query_counter bdw_memory_reads_query_counters[42]; +static struct brw_perf_query_info bdw_memory_reads_query = { + .kind = OA_COUNTERS, + .name = "Memory Reads Distribution Gen8", + .guid = "2b255d48-2117-4fef-a8f7-f151e1d25a2c", + .counters = bdw_memory_reads_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bdw_memory_reads_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bdw_memory_reads_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = bdw_memory_reads_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +bdw_register_memory_reads_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bdw_memory_reads_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198B0343 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13845800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15840018 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3580001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038B6300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058B6B62 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078B006A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118B0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85A080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAAA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385000A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01840018 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07844C80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09840D9A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B840E9C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D840F9E }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F840010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11840000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F8000E5 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x138080E3 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C0E1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11804000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1780C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F804000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00000D24, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47801042 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800084 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F872 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__memory_reads__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__gti_l3_bank0_reads__read; + counter->name = "GtiL3Bank0Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 0 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__gti_ring_accesses__read; + counter->name = "GtiRingAccesses"; + counter->desc = "The total number of all accesses from GTI to the ring."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__gti_l3_bank3_reads__read; + counter->name = "GtiL3Bank3Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 3 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__gti_rs_memory_reads__read; + counter->name = "GtiRsMemoryReads"; + counter->desc = "The total number of GTI memory reads from Resource Streamer."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__gti_hiz_memory_reads__read; + counter->name = "GtiHizMemoryReads"; + counter->desc = "The total number of GTI memory reads from Hierarchical Depth Cache (Hi-Depth Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bdw__memory_reads__avg_gpu_core_frequency__max(brw); + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__gti_rcc_memory_reads__read; + counter->name = "GtiRccMemoryReads"; + counter->desc = "The total number of GTI memory reads from Render Color Cache (Render Color Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__gti_l3_bank1_reads__read; + counter->name = "GtiL3Bank1Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 1 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__memory_reads__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__gti_cmd_streamer_memory_reads__read; + counter->name = "GtiCmdStreamerMemoryReads"; + counter->desc = "The total number of GTI memory reads from Command Streamer."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__gti_l3_bank2_reads__read; + counter->name = "GtiL3Bank2Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 2 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__gti_memory_reads__read; + counter->name = "GtiMemoryReads"; + counter->desc = "The total number of GTI memory reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__gti_rcz_memory_reads__read; + counter->name = "GtiRczMemoryReads"; + counter->desc = "The total number of GTI memory reads from Render Depth Cache (Render Depth Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__memory_reads__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 232; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__gti_msc_memory_reads__read; + counter->name = "GtiMscMemoryReads"; + counter->desc = "The total number of GTI memory reads from Multisampling Color Cache (Multisampling Color Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__gti_vf_memory_reads__read; + counter->name = "GtiVfMemoryReads"; + counter->desc = "The total number of GTI memory reads from Vertex Fetch."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__gti_stc_memory_reads__read; + counter->name = "GtiStcMemoryReads"; + counter->desc = "The total number of GTI memory reads from Stencil Cache (Stencil Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__gti_l3_reads__read; + counter->name = "GtiL3Reads"; + counter->desc = "The total number of GTI memory reads from L3 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_reads__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 328; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog bdw_memory_writes_mux_regs[49]; +static struct brw_perf_query_register_prog bdw_memory_writes_b_counter_regs[28]; +static struct brw_perf_query_register_prog bdw_memory_writes_flex_regs[7]; + +static struct brw_perf_query_counter bdw_memory_writes_query_counters[41]; +static struct brw_perf_query_info bdw_memory_writes_query = { + .kind = OA_COUNTERS, + .name = "Memory Writes Distribution Gen8", + .guid = "f7fd3220-b466-4a4d-9f98-b0caf3f2394c", + .counters = bdw_memory_writes_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bdw_memory_writes_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bdw_memory_writes_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = bdw_memory_writes_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +bdw_register_memory_writes_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bdw_memory_writes_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198B0343 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13845400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3580001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800805 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038B6300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058B6B62 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078B006A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118B0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85A080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAAA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23850002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01840010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07844880 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09840992 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B840A94 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D840B96 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11840000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D800147 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F8000E5 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x138080E3 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C0E1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11804000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1780C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00000D24, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47801082 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800084 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F822 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_writes__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__memory_writes__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_writes__gti_memory_writes__read; + counter->name = "GtiMemoryWrites"; + counter->desc = "The total number of GTI memory writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_writes__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_writes__gti_ring_accesses__read; + counter->name = "GtiRingAccesses"; + counter->desc = "The total number of all GTI accesses to the ring."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_writes__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_writes__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_writes__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_writes__gti_msc_memory_writes__read; + counter->name = "GtiMscMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Multisampling Color Cache (Multisampling Color Cache invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_writes__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_writes__gti_cmd_streamer_memory_writes__read; + counter->name = "GtiCmdStreamerMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Command Streamer."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_writes__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_writes__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_writes__gti_l3_bank0_writes__read; + counter->name = "GtiL3Bank0Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 0 (L3 Bank 0 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_writes__gti_l3_bank1_writes__read; + counter->name = "GtiL3Bank1Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 1 (L3 Bank 1 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_writes__gti_l3_bank2_writes__read; + counter->name = "GtiL3Bank2Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 2 (L3 Bank 2 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_writes__gti_l3_bank3_writes__read; + counter->name = "GtiL3Bank3Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 3 (L3 Bank 3 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_writes__gti_l3_writes__read; + counter->name = "GtiL3Writes"; + counter->desc = "The total number of GTI memory writes from L3 (L3 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_writes__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_writes__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bdw__memory_writes__avg_gpu_core_frequency__max(brw); + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_writes__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_writes__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_writes__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_writes__gti_rcc_memory_writes__read; + counter->name = "GtiRccMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Render Color Cache (Render Color Cache invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_writes__gti_so_memory_writes__read; + counter->name = "GtiSoMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Stream Output."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__memory_writes__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_writes__gti_stc_memory_writes__read; + counter->name = "GtiStcMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Stencil Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_writes__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_writes__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_writes__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__memory_writes__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 240; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_writes__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_writes__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_writes__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_writes__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_writes__gti_rcz_memory_writes__read; + counter->name = "GtiRczMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Render Depth Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_writes__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_writes__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_writes__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_writes__gti_hiz_memory_writes__read; + counter->name = "GtiHizMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Hierarchical Depth Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__memory_writes__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog bdw_compute_extended_mux_regs[648]; +static struct brw_perf_query_register_prog bdw_compute_extended_b_counter_regs[21]; +static struct brw_perf_query_register_prog bdw_compute_extended_flex_regs[7]; + +static struct brw_perf_query_counter bdw_compute_extended_query_counters[38]; +static struct brw_perf_query_info bdw_compute_extended_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics Extended Gen8", + .guid = "e99ccaca-821c-4df9-97a7-96bdb7204e43", + .counters = bdw_compute_extended_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bdw_compute_extended_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bdw_compute_extended_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = bdw_compute_extended_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +bdw_register_compute_extended_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bdw_compute_extended_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + if (brw->perfquery.sys_vars.subslice_mask & 0x01) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143D0160 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x163D2800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x183D0120 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x105800E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003D0011 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x063D0900 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x083D0A13 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A3D0B15 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3D2317 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x043D21B7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x103D0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E3D0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A3D0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5825C1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00586100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0258204C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06588000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0858C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A58C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C58C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0458C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x185B5400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5B0155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1FAA2A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101F02AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18381555 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0039A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06398000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0839A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A39A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C39A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E39A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0239A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0439A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8AAAA0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B2AA0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B5551 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAA2 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0184C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1180C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00000D24, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800420 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800421 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x02) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x105C00E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145B0160 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x165B2800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x185B0120 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5C25C1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005C6100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025C204C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B0011 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B0900 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085B0A13 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5B0B15 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5B2317 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045B21B7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x105B0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5B0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5B0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1FAA2A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101F02AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18381555 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0039A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06398000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0839A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A39A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C39A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E39A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0239A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0439A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8AAAA0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B2AA0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B5551 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAA2 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0184C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1180C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00000D24, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800420 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800421 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x04) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x103800E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143A0160 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x163A2800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x183A0120 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1FAA2A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101F02AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E38A5C1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0038A100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0238204C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16388000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x183802AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04380000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06380000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08388000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A388000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0039A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06398000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0839A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A39A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C39A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E39A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0239A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0439A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003A0011 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x063A0900 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x083A0A13 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A3A0B15 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3A2317 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x043A21B7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x103A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E3A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A3A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8AAAA0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B2AA0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B5551 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAA2 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0184C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1180C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00000D24, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800420 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800421 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x08) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14BD0160 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16BD2800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18BD0120 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10D800E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00DCC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06DC8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08DCC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ADCC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDCC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EDCC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02DCC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04DCC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00BD0011 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06BD0900 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08BD0A13 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ABD0B15 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CBD2317 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04BD21B7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10BD0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EBD0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ABD0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ED825C1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D86100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02D8204C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06D88000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08D8C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AD8C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CD8C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04D8C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00DB4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EDB4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18DB5400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ADB0155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02DB4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04DB4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06DB4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08DB4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ADB4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9FA800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9FAA2A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F02AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16B84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18B81555 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B98000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D88F800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F88000F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B5540 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258BAAA2 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178C2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C5500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8C0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAA2 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0184C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1180C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00000D24, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800420 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800421 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x10) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10DC00E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14DB0160 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16DB2800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18DB0120 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EDC25C1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00DC6100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02DC204C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06DC8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08DCC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ADCC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDCC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04DCC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00DB0011 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06DB0900 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08DB0A13 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ADB0B15 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDB2317 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04DB21B7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10DB0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EDB0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ADB0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9FA800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9FAA2A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F02AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16B84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18B81555 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B98000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D88F800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F88000F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B5540 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258BAAA2 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178C2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C5500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8C0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAA2 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0184C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1180C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00000D24, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800420 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800421 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x20) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B800E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14BA0160 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16BA2800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18BA0120 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9FA800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9FAA2A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F02AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB8A5C1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B8A100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B8204C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16B88000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18B802AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B80000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B80000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B88000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB88000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B98000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00BA0011 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06BA0900 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08BA0A13 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ABA0B15 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CBA2317 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04BA21B7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10BA0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EBA0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ABA0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D88F800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F88000F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B5540 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258BAAA2 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178C2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C5500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8C0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAA2 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0184C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1180C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00000D24, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800420 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800421 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + } + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FC2A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FC6A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007FC92 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007FCA2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FC32 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FC9A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007FE6A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007FE7A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000BF00 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_extended__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_extended__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_extended__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_extended__fpu0_active__read; + counter->name = "EU FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_extended__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_extended__eu_avg_ipc_rate__read; + counter->name = "EU AVG IPC Rate"; + counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 2.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_extended__typed_writes0__read; + counter->name = "Typed Writes 0"; + counter->desc = "The subslice 0 typed writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_extended__eu_typed_atomics0__read; + counter->name = "EuTypedAtomics0"; + counter->desc = "The subslice 0 EU Typed Atomics subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_extended__typed_atomics0__read; + counter->name = "Typed Atomics 0"; + counter->desc = "The subslice 0 typed atomics."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_extended__typed_atomics_per_cache_line__read; + counter->name = "TypedAtomicsPerCacheLine"; + counter->desc = "Ratio of EU typed atomics requests to L3 cache line writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_extended__eu_untyped_reads0__read; + counter->name = "EuUntypedReads0"; + counter->desc = "The subslice 0 EU Untyped Reads subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_extended__untyped_writes0__read; + counter->name = "Untyped Writes 0"; + counter->desc = "The subslice 0 untyped writes (including SLM writes)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_extended__eu_untyped_atomics0__read; + counter->name = "EuUntypedAtomics0"; + counter->desc = "The subslice 0 EU Untyped Atomics subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_extended__eu_untyped_writes0__read; + counter->name = "EuUntypedWrites0"; + counter->desc = "The subslice 0 EU Untyped Writes subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_extended__eu_a64_untyped_writes0__read; + counter->name = "EuA64UntypedWrites0"; + counter->desc = "The subslice 0 EU A64 Untyped Writes subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_extended__untyped_writes_per_cache_line__read; + counter->name = "UntypedWritesPerCacheLine"; + counter->desc = "Ratio of EU untyped write requests to L3 cache line writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_extended__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_extended__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_extended__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_extended__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bdw__compute_extended__avg_gpu_core_frequency__max(brw); + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_extended__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_extended__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_extended__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_extended__eu_typed_writes0__read; + counter->name = "EuTypedWrites0"; + counter->desc = "The subslice 0 EU Typed Writes subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_extended__typed_writes_per_cache_line__read; + counter->name = "TypedWritesPerCacheLine"; + counter->desc = "Ratio of EU typed write requests to L3 cache line writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_extended__typed_reads0__read; + counter->name = "Typed Reads 0"; + counter->desc = "The subslice 0 typed reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_extended__untyped_reads0__read; + counter->name = "Untyped Reads 0"; + counter->desc = "The subslice 0 untyped reads (including SLM reads)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_extended__eu_a64_untyped_reads0__read; + counter->name = "EuA64UntypedReads0"; + counter->desc = "The subslice 0 EU A64 Untyped Reads subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_extended__eu_thread_occupancy__read; + counter->name = "EU Thread Occupancy"; + counter->desc = "The percentage of time in which hardware threads occupied EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 208; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_extended__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 212; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_extended__eu_typed_reads0__read; + counter->name = "EuTypedReads0"; + counter->desc = "The subslice 0 EU Typed Reads subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_extended__untyped_reads_per_cache_line__read; + counter->name = "UntypedReadsPerCacheLine"; + counter->desc = "Ratio of EU untyped read requests to L3 cache line reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_extended__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_extended__typed_reads_per_cache_line__read; + counter->name = "TypedReadsPerCacheLine"; + counter->desc = "Ratio of EU typed read requests to L3 cache line reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_extended__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_extended__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_extended__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_extended__eu_send_active__read; + counter->name = "EU Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 272; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog bdw_compute_l3_cache_mux_regs[107]; +static struct brw_perf_query_register_prog bdw_compute_l3_cache_b_counter_regs[13]; +static struct brw_perf_query_register_prog bdw_compute_l3_cache_flex_regs[7]; + +static struct brw_perf_query_counter bdw_compute_l3_cache_query_counters[58]; +static struct brw_perf_query_info bdw_compute_l3_cache_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics L3 Cache Gen8", + .guid = "27a364dc-8225-4ecb-b607-d6f1925598d9", + .counters = bdw_compute_l3_cache_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bdw_compute_l3_cache_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bdw_compute_l3_cache_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = bdw_compute_l3_cache_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +bdw_register_compute_l3_cache_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bdw_compute_l3_cache_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143F00B3 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14BF00B3 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x138303C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3B800060 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800805 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003F0029 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x063F1400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x083F1225 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E3F1327 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x103F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005A4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085AC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5AC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1F0800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F2A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101F0280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00391000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06394000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08395000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E395000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ABF1429 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CBF1225 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00BF1380 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02BF0026 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10BF0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ADAC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDAC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00DA8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02DA4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A9DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x009D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x029D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9F8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9FA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB95000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB95000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B94000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B91000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D88C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F880003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8A8020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B0520 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258BA950 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B0016 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C5400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8C0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAA0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03835180 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834022 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11830000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07830000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09830000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0184C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05844000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C137 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C147 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1180C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15804000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00000D24, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D801000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800111 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800840 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x418014A2 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FEFE }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FEFD }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FBEF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FBDF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00101100 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00201200 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00301300 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00401400 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_l3_cache__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__l3_bank03_accesses__read; + counter->name = "L3 Bank 03 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 03."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__l3_accesses__read; + counter->name = "L3 Accesses"; + counter->desc = "The total number of L3 accesses from all entities."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_l3_cache__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__l3_total_throughput__read; + counter->name = "L3 Total Throughput"; + counter->desc = "The total number of GPU memory bytes transferred via L3."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_l3_cache__fpu0_active__read; + counter->name = "EU FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_l3_cache__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 52; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_l3_cache__eu_avg_ipc_rate__read; + counter->name = "EU AVG IPC Rate"; + counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 2.0; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_l3_cache__eu_binary_fpu0_instruction__read; + counter->name = "EU FPU0 Binary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 60; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_l3_cache__eu_hybrid_fpu0_instruction__read; + counter->name = "EU FPU0 Hybrid Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 96; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__l3_misses__read; + counter->name = "L3 Misses"; + counter->desc = "The total number of L3 misses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__l3_bank00_accesses__read; + counter->name = "L3 Bank 00 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 00."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_l3_cache__eu_move_fpu0_instruction__read; + counter->name = "EU FPU0 Move Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 128; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x02) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__l3_bank10_accesses__read; + counter->name = "L3 Bank 10 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 10."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_l3_cache__eu_hybrid_fpu1_instruction__read; + counter->name = "EU FPU1 Hybrid Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bdw__compute_l3_cache__avg_gpu_core_frequency__max(brw); + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x02) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__l3_bank10_ic_accesses__read; + counter->name = "L3 Bank 10 IC Accesses"; + counter->desc = "The total number of accesses to L3 Bank 10 from IC cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + } + + if (brw->perfquery.sys_vars.slice_mask & 0x02) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__l3_bank10_ic_hits__read; + counter->name = "L3 Bank 10 IC Hits"; + counter->desc = "The total number of hits in L3 Bank 10 from IC cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__gti_read_throughput__read; + counter->name = "GTI Read Throughput"; + counter->desc = "The total number of GPU memory bytes read from GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__gti_l3_throughput__read; + counter->name = "GTI L3 Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__l3_bank00_ic_accesses__read; + counter->name = "L3 Bank 00 IC Accesses"; + counter->desc = "The total number of accesses to L3 Bank 00 from IC cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + } + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__l3_bank00_ic_hits__read; + counter->name = "L3 Bank 00 IC Hits"; + counter->desc = "The total number of hits in L3 Bank 00 from IC cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + } + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__l3_bank01_accesses__read; + counter->name = "L3 Bank 01 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 01."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_l3_cache__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 264; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_l3_cache__eu_ternary_fpu0_instruction__read; + counter->name = "EU FPU0 Ternary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 268; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_l3_cache__eu_move_fpu1_instruction__read; + counter->name = "EU FPU1 Move Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 304; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_l3_cache__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 308; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x02) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__l3_bank11_accesses__read; + counter->name = "L3 Bank 11 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 11."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 328; + counter->size = sizeof(uint64_t); + } + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__l3_bank02_accesses__read; + counter->name = "L3 Bank 02 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 02."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 336; + counter->size = sizeof(uint64_t); + } + + if (brw->perfquery.sys_vars.slice_mask & 0x02) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__l3_bank13_accesses__read; + counter->name = "L3 Bank 13 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 13."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 344; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 352; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 360; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__gti_write_throughput__read; + counter->name = "GTI Write Throughput"; + counter->desc = "The total number of GPU memory bytes written to GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 368; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 376; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 384; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 392; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x02) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_l3_cache__l3_bank12_accesses__read; + counter->name = "L3 Bank 12 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 12."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 400; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_l3_cache__eu_binary_fpu1_instruction__read; + counter->name = "EU FPU1 Binary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 408; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_l3_cache__eu_ternary_fpu1_instruction__read; + counter->name = "EU FPU1 Ternary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 412; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_l3_cache__eu_send_active__read; + counter->name = "EU Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 416; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog bdw_data_port_reads_coalescing_mux_regs[114]; +static struct brw_perf_query_register_prog bdw_data_port_reads_coalescing_b_counter_regs[24]; +static struct brw_perf_query_register_prog bdw_data_port_reads_coalescing_flex_regs[7]; + +static struct brw_perf_query_counter bdw_data_port_reads_coalescing_query_counters[35]; +static struct brw_perf_query_info bdw_data_port_reads_coalescing_query = { + .kind = OA_COUNTERS, + .name = "Data Port Reads Coalescing Gen8", + .guid = "857fc630-2f09-4804-85f1-084adfadd5ab", + .counters = bdw_data_port_reads_coalescing_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bdw_data_port_reads_coalescing_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bdw_data_port_reads_coalescing_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = bdw_data_port_reads_coalescing_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +bdw_register_data_port_reads_coalescing_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bdw_data_port_reads_coalescing_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + if (brw->perfquery.sys_vars.subslice_mask & 0x01) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x103D0005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x163D240B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1058022F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x185B5520 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198B0003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003D0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x063D00B0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x083D0182 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A3D10A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3D11A2 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E3D0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x183D0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A3D0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E582242 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00586700 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0258004F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0658C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0858C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A58C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C58C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045B6300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x105B0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5B0155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5B0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1FAAA0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101F02AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18381555 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0039A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0639A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0839A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A39A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C39A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E39A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02392000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04398000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8AAAA0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038B6300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058B0062 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118B0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B02A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B5555 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAAA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0184C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0784C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1180C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1780C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00000D24, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D801000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800420 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800421 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800041 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + } + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000274C, .val = 0xBA98BA98 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002748, .val = 0xBA98BA98 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00003377 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFF2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FF0 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FFE2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00007FF0 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007FFC2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00007FF0 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007FF82 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x00007FF0 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000BFEF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000BFDF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000BFBF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000BF7F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__data_port_reads_coalescing__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__data_port_reads_coalescing__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__data_port_reads_coalescing__fpu0_active__read; + counter->name = "EU FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__data_port_reads_coalescing__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__data_port_reads_coalescing__eu_avg_ipc_rate__read; + counter->name = "EU AVG IPC Rate"; + counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 2.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bdw__data_port_reads_coalescing__avg_gpu_core_frequency__max(brw); + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__eu_hdc0_reads64_b__read; + counter->name = "EU to Data Port 0 Reads 64"; + counter->desc = "The subslice 0 EU data reads from Data Port with 64B per message."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__hdc0_l3_data_reads__read; + counter->name = "Data Port 0 to L3 Data Reads"; + counter->desc = "The subslice 0 Data Port data and constant reads from L3 cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__hdc0_l3_data_writes__read; + counter->name = "Data Port 0 to L3 Data Writes"; + counter->desc = "The subslice 0 Data Port data writes to L3 cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__eu_hdc0_reads128_b__read; + counter->name = "EU to Data Port 0 Reads 128"; + counter->desc = "The subslice 0 EU data reads from Data Port with 128B per message."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__data_port_reads_coalescing__eu_thread_occupancy__read; + counter->name = "EU Thread Occupancy"; + counter->desc = "The percentage of time in which hardware threads occupied EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__hdc0_l3_writes__read; + counter->name = "All Data Port 0 Writes to L3"; + counter->desc = "The subslice 0 Data Port writes to L3 cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__data_port_reads_coalescing__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__eu_hdc0_reads32_b__read; + counter->name = "EU to Data Port 0 Reads 32"; + counter->desc = "The subslice 0 EU data reads from Data Port with 32B per message."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__eu_hdc0_reads256_b__read; + counter->name = "EU to Data Port 0 Reads 256"; + counter->desc = "The subslice 0 EU data reads from Data Port with 256B per message."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__data_port_reads_coalescing__eu_bytes_read_per_cache_line__read; + counter->name = "EuBytesReadPerCacheLine"; + counter->desc = "Average EU bytes read per L3 cache line."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__data_port_reads_coalescing__eu_data_reads_per_cache_line__read; + counter->name = "EuDataReadsPerCacheLine"; + counter->desc = "Coalescing ratio of EU read requests to L3 cache lines."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 196; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__hdc0_l3_reads__read; + counter->name = "All Data Port 0 Reads from L3"; + counter->desc = "The subslice 0 Data Port reads from L3 cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_reads_coalescing__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__data_port_reads_coalescing__eu_send_active__read; + counter->name = "EU Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 248; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog bdw_data_port_writes_coalescing_mux_regs[110]; +static struct brw_perf_query_register_prog bdw_data_port_writes_coalescing_b_counter_regs[24]; +static struct brw_perf_query_register_prog bdw_data_port_writes_coalescing_flex_regs[7]; + +static struct brw_perf_query_counter bdw_data_port_writes_coalescing_query_counters[38]; +static struct brw_perf_query_info bdw_data_port_writes_coalescing_query = { + .kind = OA_COUNTERS, + .name = "Data Port Writes Coalescing Gen8", + .guid = "343ebc99-4a55-414c-8c17-d8e259cf5e20", + .counters = bdw_data_port_writes_coalescing_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bdw_data_port_writes_coalescing_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bdw_data_port_writes_coalescing_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = bdw_data_port_writes_coalescing_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +bdw_register_data_port_writes_coalescing_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bdw_data_port_writes_coalescing_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + if (brw->perfquery.sys_vars.subslice_mask & 0x01) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x103D0005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143D0120 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x163D2400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1058022F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x105B0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198B0003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003D0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x063D0094 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x083D0182 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A3D1814 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E3D0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x183D0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A3D0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3D0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E582242 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00586700 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0258004F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0658C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0858C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A58C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045B6A80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x185B5400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5B0141 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5B0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1FAAA0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101F0282 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18381415 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0039A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0639A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0839A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A39A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E39A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02392000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04398000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8A82A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038B6300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058B0062 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118B0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B02A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B1555 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B0014 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21852AAA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23850028 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830141 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0184C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0784C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1180C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1780C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00000D24, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D801000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800420 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800421 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800041 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + } + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000274C, .val = 0xBA98BA98 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002748, .val = 0xBA98BA98 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00003377 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FF72 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000BFD0 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FF62 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000BFD0 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007FF42 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000BFD0 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007FF02 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000BFD0 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0005FFF2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000BFD0 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0005FFE2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000BFD0 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0005FFC2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000BFD0 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0005FF82 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000BFD0 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__data_port_writes_coalescing__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__eu_hdc0_writes192_b__read; + counter->name = "EU to Data Port 0 Writes 128"; + counter->desc = "The subslice 0 EU data simd16 writes to Data Port with 192B per message."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__data_port_writes_coalescing__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__data_port_writes_coalescing__fpu0_active__read; + counter->name = "EU FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 28; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__data_port_writes_coalescing__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__data_port_writes_coalescing__eu_avg_ipc_rate__read; + counter->name = "EU AVG IPC Rate"; + counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 2.0; + counter->offset = 36; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__eu_hdc0_writes32_b__read; + counter->name = "EU to Data Port 0 Writes 32B"; + counter->desc = "The subslice 0 EU data writes to Data Port with 32B per message."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bdw__data_port_writes_coalescing__avg_gpu_core_frequency__max(brw); + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__eu_hdc0_writes256_b_simd16__read; + counter->name = "EU to Data Port 0 Writes 256B"; + counter->desc = "The subslice 0 EU data simd16 writes to Data Port with 256B per message."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__hdc0_l3_data_reads__read; + counter->name = "Data Port 0 to L3 Data Reads"; + counter->desc = "The subslice 0 Data Port data and constant reads from L3 cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__hdc0_l3_data_writes__read; + counter->name = "Data Port 0 to L3 Data Writes"; + counter->desc = "The subslice 0 Data Port data writes to L3 cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__eu_hdc0_writes128_b_simd16__read; + counter->name = "EU to Data Port 0 Writes 64B"; + counter->desc = "The subslice 0 EU data simd16 writes to Data Port with 128B per message."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__eu_hdc0_writes96_b__read; + counter->name = "EU to Data Port 0 Writes 64B"; + counter->desc = "The subslice 0 EU data writes to Data Port with 64B per message."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__data_port_writes_coalescing__eu_thread_occupancy__read; + counter->name = "EU Thread Occupancy"; + counter->desc = "The percentage of time in which hardware threads occupied EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__hdc0_l3_writes__read; + counter->name = "All Data Port 0 Writes to L3"; + counter->desc = "The subslice 0 Data Port writes to L3 cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__data_port_writes_coalescing__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__eu_hdc0_writes64_b__read; + counter->name = "EU to Data Port 0 Writes 64B"; + counter->desc = "The subslice 0 EU data writes to Data Port with 64B per message."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__eu_hdc0_writes128_b__read; + counter->name = "EU to Data Port 0 Writes 128"; + counter->desc = "The subslice 0 EU data writes to Data Port with 128B per message."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__data_port_writes_coalescing__eu_bytes_written_per_cache_line__read; + counter->name = "EuBytesWrittenPerCacheLine"; + counter->desc = "Average EU bytes written per L3 cache line."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__data_port_writes_coalescing__eu_data_writes_per_cache_line__read; + counter->name = "EuDataWritesPerCacheLine"; + counter->desc = "Coalescing ratio of EU write requests to L3 cache lines."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 220; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__hdc0_l3_reads__read; + counter->name = "All Data Port 0 Reads from L3"; + counter->desc = "The subslice 0 Data Port reads from L3 cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__data_port_writes_coalescing__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__data_port_writes_coalescing__eu_send_active__read; + counter->name = "EU Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 272; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog bdw_hdc_and_sf_mux_regs[98]; +static struct brw_perf_query_register_prog bdw_hdc_and_sf_b_counter_regs[8]; +static struct brw_perf_query_register_prog bdw_hdc_and_sf_flex_regs[7]; + +static struct brw_perf_query_counter bdw_hdc_and_sf_query_counters[42]; +static struct brw_perf_query_info bdw_hdc_and_sf_query = { + .kind = OA_COUNTERS, + .name = "Metric set HDCAndSF", + .guid = "7bdafd88-a4fa-4ed5-bc09-1a977aa5be3e", + .counters = bdw_hdc_and_sf_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bdw_hdc_and_sf_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bdw_hdc_and_sf_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = bdw_hdc_and_sf_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +bdw_register_hdc_and_sf_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bdw_hdc_and_sf_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x105C0232 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10580232 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10380232 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10DC0232 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10D80232 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B80232 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118E4400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025C6080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045C004B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00582080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0258004B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F00AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04386080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0638404B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A380000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C380000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00398000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0239A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0439A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06392000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDC25C1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ADCC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AD825C1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18DB4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ADB0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9F8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F02AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB825C1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18B80154 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D88C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F88000F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258BAA05 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B2A80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C5400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8C0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098E05C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058E0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198F0020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AA0A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07844000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17804000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800C62 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F801042 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x418014A4 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF7 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__hdc_and_sf__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__hdc_and_sf__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__hdc_and_sf__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__hdc_and_sf__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__hdc_and_sf__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__hdc_and_sf__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__hdc_and_sf__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__hdc_and_sf__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__hdc_and_sf__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__hdc_and_sf__poly_data_ready__read; + counter->name = "Polygon Data Ready"; + counter->desc = "The percentage of time in which geometry pipeline output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__hdc_and_sf__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x20) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__hdc_and_sf__non_sampler_shader12_access_stalled_on_l3__read; + counter->name = "HDC stalled by L3 (s0.ss2)"; + counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss2)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 72; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__hdc_and_sf__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__hdc_and_sf__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__hdc_and_sf__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__hdc_and_sf__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__hdc_and_sf__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bdw__hdc_and_sf__avg_gpu_core_frequency__max(brw); + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__hdc_and_sf__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read; + counter->name = "HDC stalled by L3 (s0.ss1)"; + counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss1)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 128; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__hdc_and_sf__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read; + counter->name = "HDC stalled by L3 (s0.ss2)"; + counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss2)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__hdc_and_sf__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__hdc_and_sf__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__hdc_and_sf__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 164; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__hdc_and_sf__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__hdc_and_sf__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 172; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x8) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__hdc_and_sf__non_sampler_shader10_access_stalled_on_l3__read; + counter->name = "HDC stalled by L3 (s0.ss0)"; + counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss0)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__hdc_and_sf__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__hdc_and_sf__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__hdc_and_sf__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__hdc_and_sf__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__hdc_and_sf__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 216; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__hdc_and_sf__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__hdc_and_sf__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__hdc_and_sf__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__hdc_and_sf__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x10) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__hdc_and_sf__non_sampler_shader11_access_stalled_on_l3__read; + counter->name = "HDC stalled by L3 (s0.ss1)"; + counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss1)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 256; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__hdc_and_sf__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__hdc_and_sf__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__hdc_and_sf__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read; + counter->name = "HDC stalled by L3 (s0.ss0)"; + counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss0)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 288; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__hdc_and_sf__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog bdw_l3_1_mux_regs[91]; +static struct brw_perf_query_register_prog bdw_l3_1_b_counter_regs[22]; +static struct brw_perf_query_register_prog bdw_l3_1_flex_regs[7]; + +static struct brw_perf_query_counter bdw_l3_1_query_counters[39]; +static struct brw_perf_query_info bdw_l3_1_query = { + .kind = OA_COUNTERS, + .name = "Metric set L3_1", + .guid = "9385ebb2-f34f-4aa5-aec5-7e9cbbea0f0b", + .counters = bdw_l3_1_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bdw_l3_1_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bdw_l3_1_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = bdw_l3_1_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +bdw_register_l3_1_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bdw_l3_1_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10BF03DA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14BF0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12980340 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12990340 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CBF1187 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EBF1205 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00BF0500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02BF042B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04BF002C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDAC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EDAC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00DA8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02DAC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04DA4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04983400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10980000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06990034 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10990000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x009D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x029DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x049D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F02A8 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9FA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9F00BA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB88000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB95000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB95000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B94000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B95000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B91000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B92000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CBA4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F88000F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D880400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B800A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B5500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8C0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185800A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830154 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07844000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17804000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800060 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00014002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000C3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00010002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000C7FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00004002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000D3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100700 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FF1F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00001402 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FC3F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00001002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FC7F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00000402 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FD3F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_1__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_1__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_1__l31_bank1_stalled__read; + counter->name = "Slice1 L3 Bank1 Stalled"; + counter->desc = "The percentage of time in which slice1 L3 bank1 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_1__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_1__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_1__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_1__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_1__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_1__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_1__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_1__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_1__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_1__l31_bank0_stalled__read; + counter->name = "Slice1 L3 Bank0 Stalled"; + counter->desc = "The percentage of time in which slice1 L3 bank0 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 80; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_1__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_1__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_1__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_1__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bdw__l3_1__avg_gpu_core_frequency__max(brw); + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_1__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_1__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_1__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_1__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_1__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_1__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_1__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_1__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_1__l31_bank1_active__read; + counter->name = "Slice1 L3 Bank1 Active"; + counter->desc = "The percentage of time in which slice1 L3 bank1 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_1__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 172; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_1__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_1__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_1__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_1__l31_bank0_active__read; + counter->name = "Slice1 L3 Bank0 Active"; + counter->desc = "The percentage of time in which slice1 L3 bank0 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 196; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_1__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_1__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_1__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_1__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_1__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_1__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_1__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_1__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog bdw_l3_2_mux_regs[78]; +static struct brw_perf_query_register_prog bdw_l3_2_b_counter_regs[22]; +static struct brw_perf_query_register_prog bdw_l3_2_flex_regs[7]; + +static struct brw_perf_query_counter bdw_l3_2_query_counters[39]; +static struct brw_perf_query_info bdw_l3_2_query = { + .kind = OA_COUNTERS, + .name = "Metric set L3_2", + .guid = "446ae59b-ff2e-41c9-b49e-0184a54bf00a", + .counters = bdw_l3_2_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bdw_l3_2_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bdw_l3_2_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = bdw_l3_2_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +bdw_register_l3_2_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bdw_l3_2_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x103F03DA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143F0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12180340 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12190340 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3F1187 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E3F1205 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003F0500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x023F042B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x043F002C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5AC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5AC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025AC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045A4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04183400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10180000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06190034 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10190000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101F02A8 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F00BA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C388000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C395000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E395000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00394000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02395000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04391000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06392000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3A4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8AA800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B4005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B2A80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185800A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830154 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07844000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17804000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800060 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00014002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000C3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00010002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000C7FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00004002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000D3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100700 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FF1F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00001402 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FC3F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00001002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FC7F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00000402 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FD3F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_2__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_2__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_2__l30_bank1_active__read; + counter->name = "Slice0 L3 Bank1 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank1 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_2__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_2__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_2__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_2__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_2__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_2__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_2__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_2__l30_bank1_stalled__read; + counter->name = "Slice0 L3 Bank1 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank1 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_2__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_2__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_2__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_2__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_2__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_2__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bdw__l3_2__avg_gpu_core_frequency__max(brw); + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_2__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_2__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_2__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_2__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_2__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_2__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_2__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_2__l30_bank0_active__read; + counter->name = "Slice0 L3 Bank0 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank0 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_2__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_2__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_2__l30_bank0_stalled__read; + counter->name = "Slice0 L3 Bank0 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank0 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 180; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_2__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_2__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_2__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_2__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_2__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_2__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_2__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_2__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_2__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_2__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_2__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog bdw_l3_3_mux_regs[94]; +static struct brw_perf_query_register_prog bdw_l3_3_b_counter_regs[22]; +static struct brw_perf_query_register_prog bdw_l3_3_flex_regs[7]; + +static struct brw_perf_query_counter bdw_l3_3_query_counters[39]; +static struct brw_perf_query_info bdw_l3_3_query = { + .kind = OA_COUNTERS, + .name = "Metric set L3_3", + .guid = "84a7956f-1ea4-4d0d-837f-e39a0376e38c", + .counters = bdw_l3_3_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bdw_l3_3_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bdw_l3_3_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = bdw_l3_3_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +bdw_register_l3_3_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bdw_l3_3_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121B0340 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x103F0274 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x129B0340 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10BF0274 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12BF0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041B3400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101B0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A3D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003F0080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x023F0793 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x043F0014 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04588000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025AC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045A4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00394000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02395000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04399000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x069B0034 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109B0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06DC4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CBD4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CBF0981 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EBF0A0F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06D84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDAC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EDAC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDB4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F02A8 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9F0080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB95000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB95000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B92000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F88000F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D880400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B8009 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B2A80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8C0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185800A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830154 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07844000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17804000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800C63 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F8014A5 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800045 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00014002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000C3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00010002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000C7FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00004002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000D3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100700 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FF1F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00001402 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FC3F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00001002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FC7F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00000402 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FD3F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_3__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_3__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_3__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_3__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_3__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_3__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_3__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_3__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_3__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_3__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_3__l30_bank3_stalled__read; + counter->name = "Slice0 L3 Bank3 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank3 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_3__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_3__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_3__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_3__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_3__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bdw__l3_3__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_3__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_3__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_3__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_3__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_3__l30_bank3_active__read; + counter->name = "Slice0 L3 Bank3 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank3 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 140; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_3__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_3__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_3__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_3__l31_bank3_active__read; + counter->name = "Slice1 L3 Bank3 Active"; + counter->desc = "The percentage of time in which slice1 L3 bank3 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.slice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_3__l31_bank3_stalled__read; + counter->name = "Slice1 L3 Bank3 Stalled"; + counter->desc = "The percentage of time in which slice1 L3 bank3 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_3__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_3__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_3__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_3__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_3__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_3__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_3__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_3__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_3__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_3__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_3__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_3__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_3__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog bdw_l3_4_mux_regs[93]; +static struct brw_perf_query_register_prog bdw_l3_4_b_counter_regs[22]; +static struct brw_perf_query_register_prog bdw_l3_4_flex_regs[7]; + +static struct brw_perf_query_counter bdw_l3_4_query_counters[39]; +static struct brw_perf_query_info bdw_l3_4_query = { + .kind = OA_COUNTERS, + .name = "Metric set L3_4", + .guid = "92b493d9-df18-4bed-be06-5cac6f2a6f5f", + .counters = bdw_l3_4_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bdw_l3_4_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bdw_l3_4_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = bdw_l3_4_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +bdw_register_l3_4_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bdw_l3_4_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121A0340 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x103F0017 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123F0020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x129A0340 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10BF0017 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12BF0020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041A3400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x043B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A3E0010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003F0200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x023F0113 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x043F0014 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02592000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025AC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045A4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00394000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02395000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04391000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x069A0034 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06BB4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ABE0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CBF0984 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EBF0A02 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02D94000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDAC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EDAC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9C0400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9E0400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F02A8 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9F0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB95000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB95000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F88000F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D880400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B8009 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B2A80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8C0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185800A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830154 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07844000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17804000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F801084 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800044 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00014002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000C3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00010002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000C7FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00004002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000D3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100700 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FF1F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00001402 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FC3F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00001002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FC7F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00000402 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FD3F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_4__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_4__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_4__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_4__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_4__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_4__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_4__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_4__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_4__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_4__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_4__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_4__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_4__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_4__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_4__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bdw__l3_4__avg_gpu_core_frequency__max(brw); + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_4__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_4__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_4__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_4__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 128; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_4__l30_bank2_stalled__read; + counter->name = "Slice0 L3 Bank2 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank2 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 132; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_4__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_4__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 140; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_4__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_4__l31_bank2_active__read; + counter->name = "Slice1 L3 Bank2 Active"; + counter->desc = "The percentage of time in which slice1 L3 bank2 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_4__l30_bank2_active__read; + counter->name = "Slice0 L3 Bank2 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank2 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_4__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_4__l31_bank2_stalled__read; + counter->name = "Slice1 L3 Bank2 Stalled"; + counter->desc = "The percentage of time in which slice1 L3 bank2 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_4__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 172; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_4__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_4__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__l3_4__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_4__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_4__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_4__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_4__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_4__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_4__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_4__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__l3_4__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog bdw_rasterizer_and_pixel_backend_mux_regs[114]; +static struct brw_perf_query_register_prog bdw_rasterizer_and_pixel_backend_b_counter_regs[18]; +static struct brw_perf_query_register_prog bdw_rasterizer_and_pixel_backend_flex_regs[7]; + +static struct brw_perf_query_counter bdw_rasterizer_and_pixel_backend_query_counters[45]; +static struct brw_perf_query_info bdw_rasterizer_and_pixel_backend_query = { + .kind = OA_COUNTERS, + .name = "Metric set RasterizerAndPixelBackend", + .guid = "14345c35-cc46-40d0-bb04-6ed1fbb43679", + .counters = bdw_rasterizer_and_pixel_backend_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bdw_rasterizer_and_pixel_backend_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bdw_rasterizer_and_pixel_backend_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = bdw_rasterizer_and_pixel_backend_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +bdw_register_rasterizer_and_pixel_backend_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bdw_rasterizer_and_pixel_backend_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143B000E }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x043C55C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1E0280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1E0408 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10390000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12397A1F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14BB000E }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04BC5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A9E0296 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9E0008 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B90000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12B97A1F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x063B0042 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x103B0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x083C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A3E0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x043F8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02594000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1C0400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081E02C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1E0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F0260 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101F0014 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003905E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06390BC0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02390018 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04394000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04BB0042 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10BB0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02BC05C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08BC0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ABE0004 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02BF8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02D91000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02DA8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x089C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x029D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x089E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9E0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9FA806 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F0142 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B90617 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB90BE0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B94000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D88F000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F88000C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8A2800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B52A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B6A95 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B0029 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178C2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C1500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8C0014 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAAA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0184C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0784C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1180C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1780C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800444 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F804000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43801080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800084 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800044 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47801080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800840 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00006000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000F3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00001800 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FCFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000600 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FF3F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000180 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFCF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000060 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFF3 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000018 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFFC }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__rasterizer1_input_available__read; + counter->name = "Slice1 Rasterizer Input Available"; + counter->desc = "The percentage of time in which slice1 rasterizer input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__pixel_values0_ready__read; + counter->name = "Slice0 Pixel Values Ready"; + counter->desc = "The percentage of time in which slice0 pixel values are ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 72; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bdw__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max(brw); + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__rasterizer0_input_available__read; + counter->name = "Slice0 Rasterizer Input Available"; + counter->desc = "The percentage of time in which slice0 rasterizer input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__pixel_data0_ready__read; + counter->name = "Slice0 Post-EarlyZ Pixel Data Ready"; + counter->desc = "The percentage of time in which slice0 post-EarlyZ pixel data is ready (after early Z tests have been applied)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 140; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 164; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__pixel_values1_ready__read; + counter->name = "Slice1 Pixel Values Ready"; + counter->desc = "The percentage of time in which slice1 pixel values are ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.slice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__ps_output1_available__read; + counter->name = "Slice1 PS Output Available"; + counter->desc = "The percentage of time in which slice1 PS output is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 172; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 184; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 208; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__rasterizer0_output_ready__read; + counter->name = "Slice0 Rasterizer Output Ready"; + counter->desc = "The percentage of time in which slice0 rasterizer output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 212; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__rasterizer1_output_ready__read; + counter->name = "Slice1 Rasterizer Output Ready"; + counter->desc = "The percentage of time in which slice1 rasterizer output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 232; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.slice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__pixel_data1_ready__read; + counter->name = "Slice1 Post-EarlyZ Pixel Data Ready"; + counter->desc = "The percentage of time in which slice1 post-EarlyZ pixel data is ready (after early Z tests have been applied)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 236; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__rasterizer_and_pixel_backend__ps_output0_available__read; + counter->name = "Slice0 PS Output Available"; + counter->desc = "The percentage of time in which slice0 PS output is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 280; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__rasterizer_and_pixel_backend__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog bdw_sampler_1_mux_regs[126]; +static struct brw_perf_query_register_prog bdw_sampler_1_b_counter_regs[12]; +static struct brw_perf_query_register_prog bdw_sampler_1_flex_regs[7]; + +static struct brw_perf_query_counter bdw_sampler_1_query_counters[41]; +static struct brw_perf_query_info bdw_sampler_1_query = { + .kind = OA_COUNTERS, + .name = "Metric set Sampler_1", + .guid = "f0c6ba37-d3d3-4211-91b5-226730312a54", + .counters = bdw_sampler_1_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bdw_sampler_1_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bdw_sampler_1_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = bdw_sampler_1_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +bdw_register_sampler_1_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bdw_sampler_1_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18921400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x149500AB }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18B21400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14B500AB }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18D21400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14D500AB }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDC8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EDC4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02DCC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04DCC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ABD00A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ABD8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CD88000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ED84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04D88000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ADB0050 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04DB8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06DB8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08DB8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ADB4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F02A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9FA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9F00AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18B82500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B88000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB88000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB98000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B98000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B92000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ABA0200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02BA8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CBA8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04918000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04927300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10920000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1893000A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A934000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A946000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C959000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E950098 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10950000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B04000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B14000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B20073 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B20000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B38000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B38000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B34000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B4C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B59890 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B50000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06D04000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06D14000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06D20073 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10D20000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18D30020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02D38000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CD34000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AD48000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04D42000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ED59000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D59800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10D50000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F88000E }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D880400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B5500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B000A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8C0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185000A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830150 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07844000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17804000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47801021 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800C64 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800C02 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x70800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0000C000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000E7FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00003000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F9FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000C00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE7F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_1__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__sampler_1__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__sampler_1__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__sampler_1__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__sampler_1__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_1__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x8) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__sampler_1__sampler10_input_available__read; + counter->name = "Slice1 Subslice0 Input Available"; + counter->desc = "The percentage of time in which slice1 subslice0 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_1__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__sampler_1__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_1__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_1__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_1__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_1__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_1__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x20) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__sampler_1__sampler12_output_ready__read; + counter->name = "Slice1 Subslice2 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice1 subslice2 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 96; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_1__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_1__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bdw__sampler_1__avg_gpu_core_frequency__max(brw); + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_1__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_1__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_1__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__sampler_1__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__sampler_1__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__sampler_1__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__sampler_1__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x10) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__sampler_1__sampler11_input_available__read; + counter->name = "Slice1 Subslice1 Input Available"; + counter->desc = "The percentage of time in which slice1 subslice1 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_1__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__sampler_1__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_1__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_1__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__sampler_1__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_1__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_1__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x20) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__sampler_1__sampler12_input_available__read; + counter->name = "Slice1 Subslice2 Input Available"; + counter->desc = "The percentage of time in which slice1 subslice2 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 224; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x8) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__sampler_1__sampler10_output_ready__read; + counter->name = "Slice1 Subslice0 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice1 subslice0 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 228; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_1__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x10) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__sampler_1__sampler11_output_ready__read; + counter->name = "Slice1 Subslice1 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice1 subslice1 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 240; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_1__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_1__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_1__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_1__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_1__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog bdw_sampler_2_mux_regs[114]; +static struct brw_perf_query_register_prog bdw_sampler_2_b_counter_regs[12]; +static struct brw_perf_query_register_prog bdw_sampler_2_flex_regs[7]; + +static struct brw_perf_query_counter bdw_sampler_2_query_counters[41]; +static struct brw_perf_query_info bdw_sampler_2_query = { + .kind = OA_COUNTERS, + .name = "Metric set Sampler_2", + .guid = "30bf3702-48cf-4bca-b412-7cf50bb2f564", + .counters = bdw_sampler_2_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bdw_sampler_2_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bdw_sampler_2_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = bdw_sampler_2_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +bdw_register_sampler_2_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bdw_sampler_2_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18121400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141500AB }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18321400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143500AB }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18521400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145500AB }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A3D00A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A3D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C588000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E584000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04588000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5B0050 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101F02A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F00AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18382500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02388000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C388000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C398000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E39A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00398000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0239A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0439A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06392000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A3A0200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x023A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04108000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04118000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04127300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10120000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1813000A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A134000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A146000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C159000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E150098 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10150000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04304000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04314000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04320073 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10320000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04338000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06338000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08334000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0434C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02359890 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10350000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06504000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06514000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06520073 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10520000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18530020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02538000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C534000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A548000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04542000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E559000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00559800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10550000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8AA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B2A80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B0005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185000A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830150 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07844000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17804000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47801021 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800C64 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800C02 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x70800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0000C000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000E7FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00003000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F9FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000C00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE7F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_2__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__sampler_2__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__sampler_2__sampler02_input_available__read; + counter->name = "Slice0 Subslice2 Input Available"; + counter->desc = "The percentage of time in which slice0 subslice2 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__sampler_2__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__sampler_2__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__sampler_2__sampler00_input_available__read; + counter->name = "Slice0 Subslice0 Input Available"; + counter->desc = "The percentage of time in which slice0 subslice0 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__sampler_2__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 28; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_2__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_2__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__sampler_2__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_2__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__sampler_2__sampler02_output_ready__read; + counter->name = "Slice0 Subslice2 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice0 subslice2 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_2__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_2__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__sampler_2__sampler01_input_available__read; + counter->name = "Slice0 Subslice1 Input Available"; + counter->desc = "The percentage of time in which slice0 subslice1 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 88; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_2__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_2__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_2__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_2__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bdw__sampler_2__avg_gpu_core_frequency__max(brw); + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_2__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_2__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_2__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__sampler_2__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__sampler_2__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__sampler_2__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__sampler_2__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 164; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_2__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__sampler_2__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_2__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_2__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__sampler_2__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_2__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_2__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__sampler_2__sampler00_output_ready__read; + counter->name = "Slice0 Subslice0 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice0 subslice0 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 224; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__sampler_2__sampler01_output_ready__read; + counter->name = "Slice0 Subslice1 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice0 subslice1 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 228; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_2__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_2__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_2__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_2__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_2__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__sampler_2__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog bdw_tdl_1_mux_regs[151]; +static struct brw_perf_query_register_prog bdw_tdl_1_b_counter_regs[18]; +static struct brw_perf_query_register_prog bdw_tdl_1_flex_regs[7]; + +static struct brw_perf_query_counter bdw_tdl_1_query_counters[47]; +static struct brw_perf_query_info bdw_tdl_1_query = { + .kind = OA_COUNTERS, + .name = "Metric set TDL_1", + .guid = "238bec85-df05-44f3-b905-d166712f2451", + .counters = bdw_tdl_1_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bdw_tdl_1_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bdw_tdl_1_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = bdw_tdl_1_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +bdw_register_tdl_1_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bdw_tdl_1_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16154D60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16352E60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16554D60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16950000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16B50000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16D50000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x083D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A3D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0458C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F00AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04388000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06388000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00398000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0239A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0439A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06392000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x043A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x063A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08138000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A138000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06143000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0415CFC7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10150000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02338000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C338000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04342000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06344000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0035C700 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x063500CF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10350000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04538000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06538000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0454C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0255CFC7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10550000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06DC8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08DC4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDCC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EDCC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ABD00A8 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CD8C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ED84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EDB8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18DB0800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ADB0254 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9FAA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F02AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16B84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18B8156A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B98000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18BAA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ABA0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16934000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1893000A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A947000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C95C5C1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9500C3 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10950000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB38000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16B30040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18B30020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B48000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B41000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB48000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B5C500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B500C3 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB5C100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B50000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16D31500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08D4E000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08D5C100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AD5C3C5 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10D50000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D88F800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F88000F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258BAAA5 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B2A80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178C2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C5500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8C0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAAA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0784C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1780C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800C42 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F8014A4 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41801042 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FDFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE7F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FFBF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFCF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFF7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFF9 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_1__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_1__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_1__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_1__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_1__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_1__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_1__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_1__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_1__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x10) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_1__ps_thread11_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice1 Subslice1"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice1 subslice1 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 56; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_1__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x20) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_1__non_ps_thread12_ready_for_dispatch__read; + counter->name = "NonPS Thread Ready For Dispatch on Slice1 Subslice2"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice1 subslice2 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 72; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_1__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_1__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_1__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x8) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_1__non_ps_thread10_ready_for_dispatch__read; + counter->name = "NonPS Thread Ready For Dispatch on Slice1 Subslice0"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice1 subslice0 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 104; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_1__thread_header01_ready_port0__read; + counter->name = "Thread Header Ready on Slice0 Subslice1 Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 108; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_1__thread_header01_ready_port1__read; + counter->name = "Thread Header Ready on Slice0 Subslice1 Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 112; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_1__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_1__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bdw__tdl_1__avg_gpu_core_frequency__max(brw); + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_1__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_1__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_1__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_1__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_1__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 164; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_1__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_1__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 172; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_1__thread_header02_ready_port1__read; + counter->name = "Thread Header Ready on Slice0 Subslice2 Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_1__thread_header02_ready_port0__read; + counter->name = "Thread Header Ready on Slice0 Subslice2 Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 180; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_1__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_1__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_1__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_1__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_1__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 216; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_1__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_1__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x20) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_1__ps_thread12_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice1 Subslice2"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice1 subslice2 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 240; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x8) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_1__ps_thread10_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice1 Subslice0"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice1 subslice0 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 244; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x10) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_1__non_ps_thread11_ready_for_dispatch__read; + counter->name = "NonPS Thread Ready For Dispatch on Slice1 Subslice1"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice1 subslice1 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 248; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_1__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_1__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_1__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_1__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_1__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_1__thread_header00_ready_port0__read; + counter->name = "Thread Header Ready on Slice0 Subslice0 Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 296; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_1__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_1__thread_header00_ready_port1__read; + counter->name = "Thread Header Ready on Slice0 Subslice0 Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 312; + counter->size = sizeof(float); + } + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog bdw_tdl_2_mux_regs[155]; +static struct brw_perf_query_register_prog bdw_tdl_2_b_counter_regs[18]; +static struct brw_perf_query_register_prog bdw_tdl_2_flex_regs[7]; + +static struct brw_perf_query_counter bdw_tdl_2_query_counters[47]; +static struct brw_perf_query_info bdw_tdl_2_query = { + .kind = OA_COUNTERS, + .name = "Metric set TDL_2", + .guid = "24bf02cd-8693-4583-981c-c4165b33da01", + .counters = bdw_tdl_2_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bdw_tdl_2_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bdw_tdl_2_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = bdw_tdl_2_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +bdw_register_tdl_2_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bdw_tdl_2_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16150000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16350000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16550000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16952E60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16B54D60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16D52E60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E3D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x183DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06588000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08588000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A584000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x185B5800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5B000A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1FAA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101F02AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18382A55 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06398000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0839A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A39A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C39A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E39A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A3A02A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E138000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16130500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06148000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08146000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0615C100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0815C500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1500C3 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10150000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16335040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08349000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A341000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x083500C1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A35C500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3500C3 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10350000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1853002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A54E000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C55C500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E55C1C3 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10550000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00DC8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02DCC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04DC4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04BD8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06BD8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02D8C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02DB8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04DB4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06DB4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08DB8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9FA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9F00AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB88000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB88000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B98000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B92000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ABA8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CBA8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0494C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0295CFC7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10950000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B38000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B38000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B42000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B41000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B5C700 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B500CF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B50000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AD38000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CD38000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06D46000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04D5C700 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06D500CF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10D50000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D880400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8AAAA0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B555A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B5500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAAA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0784C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1780C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800882 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45801082 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x478014A5 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800C62 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FDFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE7F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FF9F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFE7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFFB }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFFD }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_2__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_2__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_2__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x10) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_2__thread_header11_ready_port1__read; + counter->name = "Thread Header Ready on Slice1 Subslice1 Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice1 subslice1 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_2__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_2__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_2__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_2__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_2__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_2__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_2__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_2__non_ps_thread02_ready_for_dispatch__read; + counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice2"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 72; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_2__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_2__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_2__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_2__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_2__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bdw__tdl_2__avg_gpu_core_frequency__max(brw); + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_2__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_2__non_ps_thread00_ready_for_dispatch__read; + counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice0"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 128; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_2__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_2__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x10) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_2__thread_header11_ready_port0__read; + counter->name = "Thread Header Ready on Slice1 Subslice1 Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice1 subslice1 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_2__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_2__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_2__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 164; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_2__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x20) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_2__thread_header12_ready_port0__read; + counter->name = "Thread Header Ready on Slice1 Subslice2 Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice1 subslice2 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 172; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_2__ps_thread00_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice0"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_2__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_2__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_2__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_2__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x8) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_2__thread_header10_ready_port1__read; + counter->name = "Thread Header Ready on Slice1 Subslice0 Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice1 subslice0 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 216; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_2__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 220; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_2__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_2__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_2__ps_thread01_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice1"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 240; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x20) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_2__thread_header12_ready_port1__read; + counter->name = "Thread Header Ready on Slice1 Subslice2 Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice1 subslice2 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 244; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_2__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_2__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_2__ps_thread02_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice2"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 264; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_2__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_2__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_2__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x8) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_2__thread_header10_ready_port0__read; + counter->name = "Thread Header Ready on Slice1 Subslice0 Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice1 subslice0 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 296; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__tdl_2__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__tdl_2__non_ps_thread01_ready_for_dispatch__read; + counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice1"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 312; + counter->size = sizeof(float); + } + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog bdw_compute_extra_mux_regs[93]; +static struct brw_perf_query_register_prog bdw_compute_extra_b_counter_regs[6]; +static struct brw_perf_query_register_prog bdw_compute_extra_flex_regs[7]; + +static struct brw_perf_query_counter bdw_compute_extra_query_counters[5]; +static struct brw_perf_query_info bdw_compute_extra_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics Extra Gen8", + .guid = "8fb61ba2-2fbb-454c-a136-2dec5a8a595e", + .counters = bdw_compute_extra_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bdw_compute_extra_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bdw_compute_extra_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = bdw_compute_extra_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +bdw_register_compute_extra_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bdw_compute_extra_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161503E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x163503E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x165503E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x169503E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16B503E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16D503E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x083D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04584000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F00A8 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C388000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0439A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06392000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08138000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06141000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041500C3 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10150000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A338000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06342000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0435C300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10350000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C538000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06544000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065500C3 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10550000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00DC8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02DC4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02BD8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D88000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02DB4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04DB8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9FA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9F0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B88000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B98000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06BA8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04942000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0095C300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10950000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B38000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B44000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B500C3 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B50000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06D38000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04D48000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02D5C300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10D50000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B3500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B0005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185000A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07844000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17804000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800C40 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41801482 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00001000 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00003002 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00011010 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00050012 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00052051 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00000008 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_extra__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_extra__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_extra__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__compute_extra__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bdw__compute_extra__avg_gpu_core_frequency__max(brw); + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__compute_extra__fpu1_active_adjusted__read; + counter->name = "EU FPU1 Pipe Active including Ext Math"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing including Extended Math processing"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog bdw_vme_pipe_mux_regs[87]; +static struct brw_perf_query_register_prog bdw_vme_pipe_b_counter_regs[17]; +static struct brw_perf_query_register_prog bdw_vme_pipe_flex_regs[2]; + +static struct brw_perf_query_counter bdw_vme_pipe_query_counters[10]; +static struct brw_perf_query_info bdw_vme_pipe_query = { + .kind = OA_COUNTERS, + .name = "Media Vme Pipe Gen8", + .guid = "e1743ca0-7fc8-410b-a066-de7bbb9280b7", + .counters = bdw_vme_pipe_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bdw_vme_pipe_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bdw_vme_pipe_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = bdw_vme_pipe_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +bdw_register_vme_pipe_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bdw_vme_pipe_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14100812 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14125800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161200C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14300812 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14325800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x163200C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E3D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x183D2800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00584000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06588000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0858C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x185B9400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5B002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1F0800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1FAA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101F002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18380155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00392000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06398000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0839A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A39A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C39A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00100047 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06101A80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10100000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0810C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0811C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08126151 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10120000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00134000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E134000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161300A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A301AC7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10300000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C30C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C31C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C326151 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10320000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16332A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18330001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8A2AA0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B0020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B5550 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F850080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAA0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23850002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01844000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11804000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800884 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100030 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF9 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FFFC }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FFF3 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100180 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFCF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FF3F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00008003 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__vme_pipe__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__vme_pipe__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__vme_pipe__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__vme_pipe__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__vme_pipe__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bdw__vme_pipe__avg_gpu_core_frequency__max(brw); + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__vme_pipe__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__vme_pipe__eu_thread_occupancy__read; + counter->name = "EU Thread Occupancy"; + counter->desc = "The percentage of time in which hardware threads occupied EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__vme_pipe__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 44; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__vme_pipe__vme_busy__read; + counter->name = "VME Busy"; + counter->desc = "The percentage of time in which VME (IME or CRE) was actively processing data."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__vme_pipe__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 52; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog bdw_gpu_busyness_mux_regs[39]; +static struct brw_perf_query_register_prog bdw_gpu_busyness_b_counter_regs[7]; + +static struct brw_perf_query_counter bdw_gpu_busyness_query_counters[9]; +static struct brw_perf_query_info bdw_gpu_busyness_query = { + .kind = OA_COUNTERS, + .name = "Gpu Rings Busyness", + .guid = "0a9eb7be-feee-4275-a139-6d9cedf0fdb0", + .counters = bdw_gpu_busyness_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bdw_gpu_busyness_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bdw_gpu_busyness_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ +}; + +static void +bdw_register_gpu_busyness_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bdw_gpu_busyness_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1AF00100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118B0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11850008 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17830100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A700100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D940040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02F00085 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10F00000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x24F00000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078B0003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B0400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03850500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F858800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185000A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11830000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09830000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B838000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03844000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07844000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17804000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04708500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10700000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x24700000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D801000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800004 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x418014A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007C000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x000007FF }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__gpu_busyness__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__gpu_busyness__vebox_busy__read; + counter->name = "Vebox Ring Busy"; + counter->desc = "The percentage of time when vebox command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__gpu_busyness__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__gpu_busyness__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bdw__gpu_busyness__avg_gpu_core_frequency__max(brw); + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__gpu_busyness__render_busy__read; + counter->name = "Render Ring Busy"; + counter->desc = "The percentage of time when render command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__gpu_busyness__vdbox0_busy__read; + counter->name = "Vdbox0 Ring Busy"; + counter->desc = "The percentage of time when Vdbox0 command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 36; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__gpu_busyness__blitter_busy__read; + counter->name = "Blitter Ring Busy"; + counter->desc = "The percentage of time when blitter command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__gpu_busyness__any_ring_busy__read; + counter->name = "AnyRingBusy"; + counter->desc = "The percentage of time when any command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 44; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bdw__gpu_busyness__vdbox1_busy__read; + counter->name = "Vdbox1 Ring Busy"; + counter->desc = "The percentage of time when Vdbox1 command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog bdw_test_oa_mux_regs[14]; +static struct brw_perf_query_register_prog bdw_test_oa_b_counter_regs[22]; + +static struct brw_perf_query_counter bdw_test_oa_query_counters[12]; +static struct brw_perf_query_info bdw_test_oa_query = { + .kind = OA_COUNTERS, + .name = "MDAPI testing set Gen8", + .guid = "d6de6f55-e526-4f79-a6a6-d7315c09044e", + .counters = bdw_test_oa_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bdw_test_oa_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bdw_test_oa_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ +}; + +static void +bdw_register_test_oa_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bdw_test_oa_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198B0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078B0066 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118B0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21850008 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07844000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17804000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000004 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000003 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000007 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFF7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00100082 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFEF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x001000C2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FFE7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00100001 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FFE7 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__test_oa__counter7__read; + counter->name = "TestCounter7"; + counter->desc = "HW test counter 7. Factor: 0.666"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__test_oa__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 8; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__test_oa__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__test_oa__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bdw__test_oa__avg_gpu_core_frequency__max(brw); + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__test_oa__counter8__read; + counter->name = "TestCounter8"; + counter->desc = "HW test counter 8. Should be equal to 1."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__test_oa__counter4__read; + counter->name = "TestCounter4"; + counter->desc = "HW test counter 4. Factor: 0.333"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__test_oa__counter5__read; + counter->name = "TestCounter5"; + counter->desc = "HW test counter 5. Factor: 0.333"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__test_oa__counter6__read; + counter->name = "TestCounter6"; + counter->desc = "HW test counter 6. Factor: 0.166"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__test_oa__counter3__read; + counter->name = "TestCounter3"; + counter->desc = "HW test counter 3. Factor: 0.5"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__test_oa__counter0__read; + counter->name = "TestCounter0"; + counter->desc = "HW test counter 0. Factor: 0.0"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__test_oa__counter1__read; + counter->name = "TestCounter1"; + counter->desc = "HW test counter 1. Factor: 1.0"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bdw__test_oa__counter2__read; + counter->name = "TestCounter2"; + counter->desc = "HW test counter 2. Factor: 1.0"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +void +brw_oa_register_queries_bdw(struct brw_context *brw) +{ + bdw_register_render_basic_counter_query(brw); + bdw_register_compute_basic_counter_query(brw); + bdw_register_render_pipe_profile_counter_query(brw); + bdw_register_memory_reads_counter_query(brw); + bdw_register_memory_writes_counter_query(brw); + bdw_register_compute_extended_counter_query(brw); + bdw_register_compute_l3_cache_counter_query(brw); + bdw_register_data_port_reads_coalescing_counter_query(brw); + bdw_register_data_port_writes_coalescing_counter_query(brw); + bdw_register_hdc_and_sf_counter_query(brw); + bdw_register_l3_1_counter_query(brw); + bdw_register_l3_2_counter_query(brw); + bdw_register_l3_3_counter_query(brw); + bdw_register_l3_4_counter_query(brw); + bdw_register_rasterizer_and_pixel_backend_counter_query(brw); + bdw_register_sampler_1_counter_query(brw); + bdw_register_sampler_2_counter_query(brw); + bdw_register_tdl_1_counter_query(brw); + bdw_register_tdl_2_counter_query(brw); + bdw_register_compute_extra_counter_query(brw); + bdw_register_vme_pipe_counter_query(brw); + bdw_register_gpu_busyness_counter_query(brw); + bdw_register_test_oa_counter_query(brw); +} + +static struct brw_perf_query_register_prog chv_render_basic_mux_regs[73]; +static struct brw_perf_query_register_prog chv_render_basic_b_counter_regs[5]; +static struct brw_perf_query_register_prog chv_render_basic_flex_regs[7]; + +static struct brw_perf_query_counter chv_render_basic_query_counters[50]; +static struct brw_perf_query_info chv_render_basic_query = { + .kind = OA_COUNTERS, + .name = "Render Metrics Basic Gen8LP", + .guid = "9d8a3af5-c02c-4a4a-b947-f1672469e0fb", + .counters = chv_render_basic_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = chv_render_basic_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = chv_render_basic_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = chv_render_basic_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +chv_register_render_basic_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &chv_render_basic_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59800001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x285A0006 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2C110014 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2E110000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2C310014 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2E310000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B8303DF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3580024F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00580888 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E5A0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x205A0014 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02180500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00190555 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021D0500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021F0A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00380444 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02390500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003A0666 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00100111 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06110030 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A110031 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E110046 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04110000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00110000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00130111 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00300444 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08310030 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C310031 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10310046 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04310000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00310000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00330444 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A0A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018B0FFF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038B0A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01855000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03850055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13830021 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15830020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1783002F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1983002E }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B83002D }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D83002C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05830000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01840555 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03840500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23800074 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2580007D }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01805000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03800055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01865000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03860055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01875000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03870055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x418000AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4380000A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4780000A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_basic__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__render_basic__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_basic__l3_misses__read; + counter->name = "L3 Misses"; + counter->desc = "The total number of L3 misses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_basic__gti_l3_throughput__read; + counter->name = "GTI L3 Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__render_basic__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__render_basic__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 36; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__render_basic__sampler1_bottleneck__read; + counter->name = "Sampler 1 Bottleneck"; + counter->desc = "The percentage of time in which Sampler 1 has been slowing down the pipe when processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__render_basic__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 44; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_basic__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_basic__l3_sampler_throughput__read; + counter->name = "L3 Sampler Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_basic__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__render_basic__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 72; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_basic__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_basic__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__render_basic__sampler0_busy__read; + counter->name = "Sampler 0 Busy"; + counter->desc = "The percentage of time in which Sampler 0 has been processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 96; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__render_basic__sampler1_busy__read; + counter->name = "Sampler 1 Busy"; + counter->desc = "The percentage of time in which Sampler 1 has been processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 100; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__render_basic__samplers_busy__read; + counter->name = "Samplers Busy"; + counter->desc = "The percentage of time in which samplers have been processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 104; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_basic__gti_vf_throughput__read; + counter->name = "GTI Fixed Pipe Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between 3D Pipeline (Command Dispatch, Input Assembly and Stream Output) and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_basic__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__render_basic__sampler0_bottleneck__read; + counter->name = "Sampler 0 Bottleneck"; + counter->desc = "The percentage of time in which Sampler 0 has been slowing down the pipe when processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 128; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_basic__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_basic__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_basic__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_basic__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = chv__render_basic__avg_gpu_core_frequency__max(brw); + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_basic__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_basic__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_basic__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_basic__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_basic__gti_read_throughput__read; + counter->name = "GTI Read Throughput"; + counter->desc = "The total number of GPU memory bytes read from GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__render_basic__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 208; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__render_basic__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 212; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_basic__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__render_basic__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 224; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_basic__gti_depth_throughput__read; + counter->name = "GTI Depth Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between depth caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__render_basic__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 240; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__render_basic__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 244; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_basic__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_basic__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__render_basic__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 264; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_basic__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_basic__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__render_basic__sampler_bottleneck__read; + counter->name = "Samplers Bottleneck"; + counter->desc = "The percentage of time in which samplers have been slowing down the pipe when processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 288; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_basic__gti_hdc_lookups_throughput__read; + counter->name = "GTI HDC TLB Lookup Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between GTI and HDC, when HDC is doing TLB lookups."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_basic__gti_rcc_throughput__read; + counter->name = "GTI RCC Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between render color caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_basic__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_basic__gti_write_throughput__read; + counter->name = "GTI Write Throughput"; + counter->desc = "The total number of GPU memory bytes written to GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_basic__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 328; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_basic__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 336; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_basic__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 344; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_basic__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 352; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog chv_compute_basic_mux_regs[43]; +static struct brw_perf_query_register_prog chv_compute_basic_b_counter_regs[4]; +static struct brw_perf_query_register_prog chv_compute_basic_flex_regs[7]; + +static struct brw_perf_query_counter chv_compute_basic_query_counters[42]; +static struct brw_perf_query_info chv_compute_basic_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics Basic Gen8LP", + .guid = "f522a89c-ecd1-4522-8331-3383c54af5f5", + .counters = chv_compute_basic_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = chv_compute_basic_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = chv_compute_basic_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = chv_compute_basic_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +chv_register_compute_basic_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &chv_compute_basic_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59800001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2E5800E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2E3800E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3580024F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800140 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08580042 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C580040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1058004C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1458004B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04580000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00580000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00195555 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06380042 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A380040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E38004C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1238004B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04380000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00384444 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003A5555 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018BFFFF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01845555 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17800074 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980007D }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80007C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8000B6 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F8000B7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x418000AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x438000AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4980012A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B80012A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D80012A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F80012A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x518001CE }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x538001CE }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x5580000E }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__compute_basic__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__compute_basic__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__compute_basic__untyped_bytes_read__read; + counter->name = "Untyped Bytes Read"; + counter->desc = "The total number of typed memory bytes read via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__compute_basic__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__compute_basic__typed_bytes_written__read; + counter->name = "Typed Bytes Written"; + counter->desc = "The total number of untyped memory bytes written via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__compute_basic__fpu0_active__read; + counter->name = "EU FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__compute_basic__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 44; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__compute_basic__eu_avg_ipc_rate__read; + counter->name = "EU AVG IPC Rate"; + counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 2.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__compute_basic__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__compute_basic__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__compute_basic__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__compute_basic__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__compute_basic__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__compute_basic__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__compute_basic__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__compute_basic__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__compute_basic__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = chv__compute_basic__avg_gpu_core_frequency__max(brw); + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__compute_basic__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__compute_basic__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__compute_basic__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__compute_basic__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__compute_basic__gti_read_throughput__read; + counter->name = "GTI Read Throughput"; + counter->desc = "The total number of GPU memory bytes read from GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__compute_basic__gti_ring_throughput__read; + counter->name = "GTI Ring Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between GTI and Uncore ring."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__compute_basic__untyped_bytes_written__read; + counter->name = "Untyped Writes"; + counter->desc = "The total number of untyped memory bytes written via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__compute_basic__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 184; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__compute_basic__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__compute_basic__typed_bytes_read__read; + counter->name = "Typed Bytes Read"; + counter->desc = "The total number of typed memory bytes read via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__compute_basic__gti_ro_stall__read; + counter->name = "GTI Read-Only Stall"; + counter->desc = "The percentage of time in which GTI Read-Only port has been stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 208; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__compute_basic__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__compute_basic__eu_thread_occupancy__read; + counter->name = "EU Thread Occupancy"; + counter->desc = "The percentage of time in which hardware threads occupied EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 224; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__compute_basic__gti_rw_stall__read; + counter->name = "GTI Read-Write Stall"; + counter->desc = "The percentage of time in which GTI Read-Write port has been stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 228; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__compute_basic__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 232; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__compute_basic__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__compute_basic__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__compute_basic__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__compute_basic__gti_write_throughput__read; + counter->name = "GTI Write Throughput"; + counter->desc = "The total number of GPU memory bytes written to GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__compute_basic__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__compute_basic__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__compute_basic__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__compute_basic__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__compute_basic__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__compute_basic__eu_send_active__read; + counter->name = "EU Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 312; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog chv_render_pipe_profile_mux_regs[82]; +static struct brw_perf_query_register_prog chv_render_pipe_profile_b_counter_regs[20]; +static struct brw_perf_query_register_prog chv_render_pipe_profile_flex_regs[7]; + +static struct brw_perf_query_counter chv_render_pipe_profile_query_counters[44]; +static struct brw_perf_query_info chv_render_pipe_profile_query = { + .kind = OA_COUNTERS, + .name = "Render Metrics for 3D Pipeline Profile", + .guid = "a9ccc03d-a943-4e6b-9cd6-13e063075927", + .counters = chv_render_pipe_profile_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = chv_render_pipe_profile_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = chv_render_pipe_profile_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = chv_render_pipe_profile_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +chv_register_render_pipe_profile_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &chv_render_pipe_profile_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59800001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x261E0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x281F000F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2817001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2791001F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27880019 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D890000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278A0007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x298D001F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278E0020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B8F0012 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00184000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02181000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02194000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141E0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041E0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001E0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x221F0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x023A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0213C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02164000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x24170012 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04170000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07910005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05910000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01911500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03910501 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D880002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D880003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05880000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B890032 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B890031 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05890000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01890040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03890040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198A0004 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018A8050 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A2050 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018B95A9 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038BE5A9 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018C1500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038C0501 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178D0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058D0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x138E0004 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x218E000C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058E0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018E0500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038E0101 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8F0027 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038F0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900013 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900017 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01900100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03900001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01845555 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03845555 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x418000AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x438000AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x458000AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x478000AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4980018C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B80014B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800128 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F80012A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800187 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x5380014B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55800149 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x5780010A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFEA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFC }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007AFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F5FD }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00079FFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000F3FB }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007BF7A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F7E7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FEFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000F7CF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00077FFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000EFDF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0006FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000CFBF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0003FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x00005F7F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_pipe_profile__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__render_pipe_profile__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__render_pipe_profile__vs_bottleneck__read; + counter->name = "VS Bottleneck"; + counter->desc = "The percentage of time in which vertex shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__render_pipe_profile__hi_depth_bottleneck__read; + counter->name = "Hi-Depth Bottleneck"; + counter->desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__render_pipe_profile__gs_bottleneck__read; + counter->name = "GS Bottleneck"; + counter->desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_pipe_profile__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_pipe_profile__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_pipe_profile__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_pipe_profile__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__render_pipe_profile__bc_bottleneck__read; + counter->name = "BC Bottleneck"; + counter->desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__render_pipe_profile__hs_stall__read; + counter->name = "HS Stall"; + counter->desc = "The percentage of time in which hull stall pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 60; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_pipe_profile__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_pipe_profile__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_pipe_profile__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_pipe_profile__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_pipe_profile__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = chv__render_pipe_profile__avg_gpu_core_frequency__max(brw); + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_pipe_profile__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_pipe_profile__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__render_pipe_profile__vf_bottleneck__read; + counter->name = "VF Bottleneck"; + counter->desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_pipe_profile__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__render_pipe_profile__sf_bottleneck__read; + counter->name = "Strip-Fans Bottleneck"; + counter->desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_pipe_profile__sampler_accesses__read; + counter->name = "Sampler Accesses"; + counter->desc = "The total number of messages send to samplers."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__render_pipe_profile__sf_stall__read; + counter->name = "SF Stall"; + counter->desc = "The percentage of time in which strip-fans pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__render_pipe_profile__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__render_pipe_profile__hs_bottleneck__read; + counter->name = "HS Bottleneck"; + counter->desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__render_pipe_profile__cl_stall__read; + counter->name = "CL Stall"; + counter->desc = "The percentage of time in which clipper pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 164; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__render_pipe_profile__so_bottleneck__read; + counter->name = "SO Bottleneck"; + counter->desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_pipe_profile__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_pipe_profile__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_pipe_profile__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__render_pipe_profile__ds_bottleneck__read; + counter->name = "DS Bottleneck"; + counter->desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__render_pipe_profile__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 204; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__render_pipe_profile__cl_bottleneck__read; + counter->name = "Clipper Bottleneck"; + counter->desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__render_pipe_profile__ds_stall__read; + counter->name = "DS Stall"; + counter->desc = "The percentage of time in which domain shader pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 212; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__render_pipe_profile__early_depth_bottleneck__read; + counter->name = "Early Depth Bottleneck"; + counter->desc = "The percentage of time in which early depth test pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_pipe_profile__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_pipe_profile__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_pipe_profile__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_pipe_profile__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_pipe_profile__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_pipe_profile__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_pipe_profile__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__render_pipe_profile__so_stall__read; + counter->name = "SO Stall"; + counter->desc = "The percentage of time in which stream-output pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__render_pipe_profile__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog chv_hdc_and_sf_mux_regs[98]; +static struct brw_perf_query_register_prog chv_hdc_and_sf_b_counter_regs[8]; +static struct brw_perf_query_register_prog chv_hdc_and_sf_flex_regs[7]; + +static struct brw_perf_query_counter chv_hdc_and_sf_query_counters[42]; +static struct brw_perf_query_info chv_hdc_and_sf_query = { + .kind = OA_COUNTERS, + .name = "Metric set HDCAndSF", + .guid = "2cf0c064-68df-4fac-9b3f-57f51ca8a069", + .counters = chv_hdc_and_sf_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = chv_hdc_and_sf_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = chv_hdc_and_sf_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = chv_hdc_and_sf_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +chv_register_hdc_and_sf_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &chv_hdc_and_sf_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x105C0232 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10580232 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10380232 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10DC0232 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10D80232 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B80232 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118E4400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025C6080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045C004B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00582080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0258004B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F00AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04386080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0638404B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A380000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C380000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00398000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0239A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0439A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06392000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDC25C1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ADCC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AD825C1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18DB4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ADB0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9F8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F02AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB825C1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18B80154 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D88C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F88000F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258BAA05 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B2A80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C5400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8C0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098E05C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058E0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198F0020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AA0A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07844000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17804000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800C62 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F801042 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x418014A4 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF7 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__hdc_and_sf__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__hdc_and_sf__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__hdc_and_sf__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__hdc_and_sf__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__hdc_and_sf__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__hdc_and_sf__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__hdc_and_sf__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__hdc_and_sf__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__hdc_and_sf__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__hdc_and_sf__poly_data_ready__read; + counter->name = "Polygon Data Ready"; + counter->desc = "The percentage of time in which geometry pipeline output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__hdc_and_sf__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x20) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__hdc_and_sf__non_sampler_shader12_access_stalled_on_l3__read; + counter->name = "HDC stalled by L3 (s0.ss2)"; + counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss2)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 72; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__hdc_and_sf__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__hdc_and_sf__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__hdc_and_sf__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__hdc_and_sf__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__hdc_and_sf__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = chv__hdc_and_sf__avg_gpu_core_frequency__max(brw); + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__hdc_and_sf__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read; + counter->name = "HDC stalled by L3 (s0.ss1)"; + counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss1)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 128; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__hdc_and_sf__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read; + counter->name = "HDC stalled by L3 (s0.ss2)"; + counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss2)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__hdc_and_sf__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__hdc_and_sf__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__hdc_and_sf__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 164; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__hdc_and_sf__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__hdc_and_sf__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 172; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x8) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__hdc_and_sf__non_sampler_shader10_access_stalled_on_l3__read; + counter->name = "HDC stalled by L3 (s0.ss0)"; + counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss0)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__hdc_and_sf__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__hdc_and_sf__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__hdc_and_sf__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__hdc_and_sf__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__hdc_and_sf__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 216; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__hdc_and_sf__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__hdc_and_sf__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__hdc_and_sf__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__hdc_and_sf__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x10) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__hdc_and_sf__non_sampler_shader11_access_stalled_on_l3__read; + counter->name = "HDC stalled by L3 (s0.ss1)"; + counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss1)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 256; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__hdc_and_sf__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__hdc_and_sf__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__hdc_and_sf__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read; + counter->name = "HDC stalled by L3 (s0.ss0)"; + counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss0)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 288; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__hdc_and_sf__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog chv_l3_1_mux_regs[91]; +static struct brw_perf_query_register_prog chv_l3_1_b_counter_regs[22]; +static struct brw_perf_query_register_prog chv_l3_1_flex_regs[7]; + +static struct brw_perf_query_counter chv_l3_1_query_counters[39]; +static struct brw_perf_query_info chv_l3_1_query = { + .kind = OA_COUNTERS, + .name = "Metric set L3_1", + .guid = "78a87ff9-543a-49ce-95ea-26d86071ea93", + .counters = chv_l3_1_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = chv_l3_1_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = chv_l3_1_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = chv_l3_1_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +chv_register_l3_1_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &chv_l3_1_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10BF03DA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14BF0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12980340 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12990340 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CBF1187 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EBF1205 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00BF0500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02BF042B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04BF002C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDAC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EDAC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00DA8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02DAC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04DA4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04983400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10980000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06990034 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10990000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x009D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x029DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x049D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F02A8 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9FA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9F00BA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB88000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB95000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB95000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B94000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B95000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B91000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B92000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CBA4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F88000F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D880400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B800A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B5500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8C0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185800A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830154 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07844000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17804000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800060 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00014002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000C3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00010002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000C7FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00004002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000D3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100700 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FF1F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00001402 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FC3F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00001002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FC7F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00000402 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FD3F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_1__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_1__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_1__l31_bank1_stalled__read; + counter->name = "Slice1 L3 Bank1 Stalled"; + counter->desc = "The percentage of time in which slice1 L3 bank1 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_1__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_1__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_1__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_1__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_1__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_1__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_1__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_1__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_1__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_1__l31_bank0_stalled__read; + counter->name = "Slice1 L3 Bank0 Stalled"; + counter->desc = "The percentage of time in which slice1 L3 bank0 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 80; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_1__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_1__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_1__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_1__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = chv__l3_1__avg_gpu_core_frequency__max(brw); + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_1__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_1__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_1__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_1__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_1__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_1__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_1__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_1__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_1__l31_bank1_active__read; + counter->name = "Slice1 L3 Bank1 Active"; + counter->desc = "The percentage of time in which slice1 L3 bank1 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_1__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 172; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_1__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_1__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_1__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_1__l31_bank0_active__read; + counter->name = "Slice1 L3 Bank0 Active"; + counter->desc = "The percentage of time in which slice1 L3 bank0 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 196; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_1__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_1__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_1__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_1__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_1__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_1__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_1__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_1__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog chv_l3_2_mux_regs[78]; +static struct brw_perf_query_register_prog chv_l3_2_b_counter_regs[22]; +static struct brw_perf_query_register_prog chv_l3_2_flex_regs[7]; + +static struct brw_perf_query_counter chv_l3_2_query_counters[39]; +static struct brw_perf_query_info chv_l3_2_query = { + .kind = OA_COUNTERS, + .name = "Metric set L3_2", + .guid = "9f2cece5-7bfe-4320-ad66-8c7cc526bec5", + .counters = chv_l3_2_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = chv_l3_2_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = chv_l3_2_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = chv_l3_2_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +chv_register_l3_2_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &chv_l3_2_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x103F03DA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143F0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12180340 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12190340 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3F1187 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E3F1205 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003F0500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x023F042B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x043F002C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5AC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5AC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025AC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045A4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04183400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10180000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06190034 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10190000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101F02A8 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F00BA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C388000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C395000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E395000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00394000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02395000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04391000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06392000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3A4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8AA800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B4005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B2A80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185800A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830154 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07844000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17804000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800060 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00014002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000C3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00010002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000C7FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00004002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000D3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100700 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FF1F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00001402 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FC3F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00001002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FC7F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00000402 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FD3F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_2__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_2__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_2__l30_bank1_active__read; + counter->name = "Slice0 L3 Bank1 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank1 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_2__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_2__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_2__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_2__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_2__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_2__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_2__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_2__l30_bank1_stalled__read; + counter->name = "Slice0 L3 Bank1 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank1 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_2__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_2__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_2__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_2__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_2__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_2__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = chv__l3_2__avg_gpu_core_frequency__max(brw); + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_2__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_2__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_2__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_2__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_2__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_2__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_2__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_2__l30_bank0_active__read; + counter->name = "Slice0 L3 Bank0 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank0 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_2__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_2__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_2__l30_bank0_stalled__read; + counter->name = "Slice0 L3 Bank0 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank0 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 180; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_2__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_2__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_2__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_2__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_2__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_2__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_2__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_2__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_2__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_2__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_2__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog chv_l3_3_mux_regs[94]; +static struct brw_perf_query_register_prog chv_l3_3_b_counter_regs[22]; +static struct brw_perf_query_register_prog chv_l3_3_flex_regs[7]; + +static struct brw_perf_query_counter chv_l3_3_query_counters[39]; +static struct brw_perf_query_info chv_l3_3_query = { + .kind = OA_COUNTERS, + .name = "Metric set L3_3", + .guid = "d890ef38-d309-47e4-b8b5-aa779bb19ab0", + .counters = chv_l3_3_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = chv_l3_3_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = chv_l3_3_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = chv_l3_3_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +chv_register_l3_3_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &chv_l3_3_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121B0340 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x103F0274 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x129B0340 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10BF0274 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12BF0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041B3400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101B0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A3D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003F0080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x023F0793 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x043F0014 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04588000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025AC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045A4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00394000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02395000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04399000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x069B0034 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109B0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06DC4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CBD4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CBF0981 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EBF0A0F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06D84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDAC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EDAC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDB4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F02A8 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9F0080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB95000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB95000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B92000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F88000F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D880400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B8009 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B2A80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8C0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185800A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830154 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07844000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17804000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800C63 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F8014A5 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800045 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00014002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000C3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00010002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000C7FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00004002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000D3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100700 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FF1F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00001402 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FC3F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00001002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FC7F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00000402 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FD3F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_3__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_3__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_3__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_3__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_3__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_3__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_3__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_3__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_3__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_3__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_3__l30_bank3_stalled__read; + counter->name = "Slice0 L3 Bank3 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank3 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_3__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_3__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_3__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_3__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_3__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = chv__l3_3__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_3__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_3__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_3__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_3__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_3__l30_bank3_active__read; + counter->name = "Slice0 L3 Bank3 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank3 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 140; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_3__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_3__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_3__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_3__l31_bank3_active__read; + counter->name = "Slice1 L3 Bank3 Active"; + counter->desc = "The percentage of time in which slice1 L3 bank3 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.slice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_3__l31_bank3_stalled__read; + counter->name = "Slice1 L3 Bank3 Stalled"; + counter->desc = "The percentage of time in which slice1 L3 bank3 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_3__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_3__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_3__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_3__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_3__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_3__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_3__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_3__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_3__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_3__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_3__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_3__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_3__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog chv_l3_4_mux_regs[93]; +static struct brw_perf_query_register_prog chv_l3_4_b_counter_regs[22]; +static struct brw_perf_query_register_prog chv_l3_4_flex_regs[7]; + +static struct brw_perf_query_counter chv_l3_4_query_counters[39]; +static struct brw_perf_query_info chv_l3_4_query = { + .kind = OA_COUNTERS, + .name = "Metric set L3_4", + .guid = "5fdff4a6-9dc8-45e1-bfda-ef54869fbdd4", + .counters = chv_l3_4_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = chv_l3_4_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = chv_l3_4_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = chv_l3_4_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +chv_register_l3_4_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &chv_l3_4_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121A0340 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x103F0017 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123F0020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x129A0340 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10BF0017 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12BF0020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041A3400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x043B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A3E0010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003F0200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x023F0113 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x043F0014 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02592000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025AC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045A4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00394000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02395000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04391000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x069A0034 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06BB4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ABE0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CBF0984 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EBF0A02 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02D94000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDAC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EDAC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9C0400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9E0400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F02A8 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9F0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB95000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB95000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F88000F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D880400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B8009 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B2A80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8C0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185800A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830154 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07844000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17804000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F801084 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800044 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00014002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000C3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00010002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000C7FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00004002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000D3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100700 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FF1F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00001402 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FC3F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00001002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FC7F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00000402 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FD3F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_4__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_4__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_4__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_4__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_4__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_4__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_4__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_4__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_4__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_4__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_4__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_4__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_4__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_4__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_4__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = chv__l3_4__avg_gpu_core_frequency__max(brw); + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_4__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_4__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_4__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_4__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 128; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_4__l30_bank2_stalled__read; + counter->name = "Slice0 L3 Bank2 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank2 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 132; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_4__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_4__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 140; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_4__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_4__l31_bank2_active__read; + counter->name = "Slice1 L3 Bank2 Active"; + counter->desc = "The percentage of time in which slice1 L3 bank2 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_4__l30_bank2_active__read; + counter->name = "Slice0 L3 Bank2 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank2 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_4__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_4__l31_bank2_stalled__read; + counter->name = "Slice1 L3 Bank2 Stalled"; + counter->desc = "The percentage of time in which slice1 L3 bank2 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_4__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 172; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_4__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_4__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__l3_4__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_4__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_4__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_4__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_4__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_4__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_4__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_4__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__l3_4__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog chv_rasterizer_and_pixel_backend_mux_regs[114]; +static struct brw_perf_query_register_prog chv_rasterizer_and_pixel_backend_b_counter_regs[18]; +static struct brw_perf_query_register_prog chv_rasterizer_and_pixel_backend_flex_regs[7]; + +static struct brw_perf_query_counter chv_rasterizer_and_pixel_backend_query_counters[45]; +static struct brw_perf_query_info chv_rasterizer_and_pixel_backend_query = { + .kind = OA_COUNTERS, + .name = "Metric set RasterizerAndPixelBackend", + .guid = "2c0e45e1-7e2c-4a14-ae00-0b7ec868b8aa", + .counters = chv_rasterizer_and_pixel_backend_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = chv_rasterizer_and_pixel_backend_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = chv_rasterizer_and_pixel_backend_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = chv_rasterizer_and_pixel_backend_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +chv_register_rasterizer_and_pixel_backend_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &chv_rasterizer_and_pixel_backend_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143B000E }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x043C55C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1E0280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1E0408 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10390000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12397A1F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14BB000E }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04BC5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A9E0296 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9E0008 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B90000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12B97A1F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x063B0042 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x103B0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x083C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A3E0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x043F8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02594000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1C0400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081E02C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1E0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F0260 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101F0014 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003905E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06390BC0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02390018 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04394000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04BB0042 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10BB0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02BC05C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08BC0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ABE0004 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02BF8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02D91000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02DA8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x089C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x029D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x089E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9E0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9FA806 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F0142 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B90617 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB90BE0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B94000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D88F000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F88000C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8A2800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B52A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B6A95 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B0029 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178C2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C1500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8C0014 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAAA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0184C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0784C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1180C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1780C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800444 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F804000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43801080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800084 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800044 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47801080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800840 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00006000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000F3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00001800 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FCFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000600 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FF3F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000180 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFCF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000060 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFF3 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000018 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFFC }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__rasterizer1_input_available__read; + counter->name = "Slice1 Rasterizer Input Available"; + counter->desc = "The percentage of time in which slice1 rasterizer input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__pixel_values0_ready__read; + counter->name = "Slice0 Pixel Values Ready"; + counter->desc = "The percentage of time in which slice0 pixel values are ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 72; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = chv__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max(brw); + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__rasterizer0_input_available__read; + counter->name = "Slice0 Rasterizer Input Available"; + counter->desc = "The percentage of time in which slice0 rasterizer input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__pixel_data0_ready__read; + counter->name = "Slice0 Post-EarlyZ Pixel Data Ready"; + counter->desc = "The percentage of time in which slice0 post-EarlyZ pixel data is ready (after early Z tests have been applied))"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 140; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 164; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__pixel_values1_ready__read; + counter->name = "Slice1 Pixel Values Ready"; + counter->desc = "The percentage of time in which slice1 pixel values are ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.slice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__ps_output1_available__read; + counter->name = "Slice1 PS Output Available"; + counter->desc = "The percentage of time in which slice1 PS output is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 172; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 184; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 208; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__rasterizer0_output_ready__read; + counter->name = "Slice0 Rasterizer Output Ready"; + counter->desc = "The percentage of time in which slice0 rasterizer output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 212; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__rasterizer1_output_ready__read; + counter->name = "Slice1 Rasterizer Output Ready"; + counter->desc = "The percentage of time in which slice1 rasterizer output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 232; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.slice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__pixel_data1_ready__read; + counter->name = "Slice1 Post-EarlyZ Pixel Data Ready"; + counter->desc = "The percentage of time in which slice1 post-EarlyZ pixel data is ready (after early Z tests have been applied)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 236; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__rasterizer_and_pixel_backend__ps_output0_available__read; + counter->name = "Slice0 PS Output Available"; + counter->desc = "The percentage of time in which slice0 PS output is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 280; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__rasterizer_and_pixel_backend__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog chv_sampler_1_mux_regs[126]; +static struct brw_perf_query_register_prog chv_sampler_1_b_counter_regs[12]; +static struct brw_perf_query_register_prog chv_sampler_1_flex_regs[7]; + +static struct brw_perf_query_counter chv_sampler_1_query_counters[41]; +static struct brw_perf_query_info chv_sampler_1_query = { + .kind = OA_COUNTERS, + .name = "Metric set Sampler_1", + .guid = "71148d78-baf5-474f-878a-e23158d0265d", + .counters = chv_sampler_1_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = chv_sampler_1_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = chv_sampler_1_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = chv_sampler_1_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +chv_register_sampler_1_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &chv_sampler_1_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18921400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x149500AB }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18B21400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14B500AB }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18D21400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14D500AB }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDC8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EDC4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02DCC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04DCC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ABD00A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ABD8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CD88000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ED84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04D88000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ADB0050 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04DB8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06DB8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08DB8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ADB4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F02A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9FA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9F00AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18B82500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B88000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB88000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB98000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B98000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B92000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ABA0200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02BA8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CBA8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04918000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04927300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10920000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1893000A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A934000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A946000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C959000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E950098 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10950000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B04000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B14000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B20073 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B20000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B38000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B38000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B34000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B4C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B59890 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B50000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06D04000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06D14000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06D20073 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10D20000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18D30020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02D38000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CD34000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AD48000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04D42000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ED59000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D59800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10D50000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F88000E }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D880400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B5500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B000A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8C0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185000A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830150 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07844000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17804000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47801021 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800C64 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800C02 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x70800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0000C000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000E7FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00003000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F9FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000C00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE7F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_1__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__sampler_1__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__sampler_1__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__sampler_1__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__sampler_1__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_1__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x8) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__sampler_1__sampler10_input_available__read; + counter->name = "Slice1 Subslice0 Input Available"; + counter->desc = "The percentage of time in which slice1 subslice0 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_1__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__sampler_1__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_1__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_1__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_1__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_1__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_1__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x20) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__sampler_1__sampler12_output_ready__read; + counter->name = "Slice1 Subslice2 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice1 subslice2 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 96; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_1__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_1__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = chv__sampler_1__avg_gpu_core_frequency__max(brw); + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_1__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_1__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_1__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__sampler_1__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__sampler_1__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__sampler_1__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__sampler_1__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x10) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__sampler_1__sampler11_input_available__read; + counter->name = "Slice1 Subslice1 Input Available"; + counter->desc = "The percentage of time in which slice1 subslice1 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_1__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__sampler_1__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_1__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_1__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__sampler_1__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_1__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_1__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x20) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__sampler_1__sampler12_input_available__read; + counter->name = "Slice1 Subslice2 Input Available"; + counter->desc = "The percentage of time in which slice1 subslice2 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 224; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x8) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__sampler_1__sampler10_output_ready__read; + counter->name = "Slice1 Subslice0 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice1 subslice0 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 228; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_1__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x10) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__sampler_1__sampler11_output_ready__read; + counter->name = "Slice1 Subslice1 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice1 subslice1 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 240; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_1__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_1__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_1__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_1__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_1__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog chv_sampler_2_mux_regs[114]; +static struct brw_perf_query_register_prog chv_sampler_2_b_counter_regs[12]; +static struct brw_perf_query_register_prog chv_sampler_2_flex_regs[7]; + +static struct brw_perf_query_counter chv_sampler_2_query_counters[41]; +static struct brw_perf_query_info chv_sampler_2_query = { + .kind = OA_COUNTERS, + .name = "Metric set Sampler_2", + .guid = "b996a2b7-c59c-492d-877a-8cd54fd6df84", + .counters = chv_sampler_2_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = chv_sampler_2_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = chv_sampler_2_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = chv_sampler_2_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +chv_register_sampler_2_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &chv_sampler_2_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18121400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141500AB }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18321400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143500AB }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18521400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145500AB }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A3D00A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A3D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C588000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E584000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04588000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5B0050 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101F02A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F00AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18382500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02388000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C388000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C398000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E39A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00398000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0239A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0439A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06392000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A3A0200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x023A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04108000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04118000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04127300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10120000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1813000A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A134000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A146000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C159000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E150098 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10150000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04304000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04314000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04320073 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10320000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04338000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06338000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08334000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0434C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02359890 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10350000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06504000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06514000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06520073 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10520000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18530020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02538000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C534000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A548000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04542000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E559000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00559800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10550000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8AA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B2A80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B0005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185000A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830150 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07844000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17804000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47801021 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800C64 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800C02 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x70800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0000C000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000E7FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00003000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F9FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000C00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE7F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_2__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__sampler_2__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__sampler_2__sampler02_input_available__read; + counter->name = "Slice0 Subslice2 Input Available"; + counter->desc = "The percentage of time in which slice0 subslice2 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__sampler_2__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__sampler_2__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__sampler_2__sampler00_input_available__read; + counter->name = "Slice0 Subslice0 Input Available"; + counter->desc = "The percentage of time in which slice0 subslice0 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__sampler_2__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 28; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_2__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_2__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__sampler_2__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_2__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__sampler_2__sampler02_output_ready__read; + counter->name = "Slice0 Subslice2 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice0 subslice2 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_2__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_2__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__sampler_2__sampler01_input_available__read; + counter->name = "Slice0 Subslice1 Input Available"; + counter->desc = "The percentage of time in which slice0 subslice1 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 88; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_2__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_2__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_2__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_2__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = chv__sampler_2__avg_gpu_core_frequency__max(brw); + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_2__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_2__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_2__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__sampler_2__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__sampler_2__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__sampler_2__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__sampler_2__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 164; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_2__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__sampler_2__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_2__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_2__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__sampler_2__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_2__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_2__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__sampler_2__sampler00_output_ready__read; + counter->name = "Slice0 Subslice0 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice0 subslice0 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 224; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__sampler_2__sampler01_output_ready__read; + counter->name = "Slice0 Subslice1 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice0 subslice1 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 228; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_2__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_2__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_2__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_2__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_2__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__sampler_2__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog chv_tdl_1_mux_regs[151]; +static struct brw_perf_query_register_prog chv_tdl_1_b_counter_regs[18]; +static struct brw_perf_query_register_prog chv_tdl_1_flex_regs[7]; + +static struct brw_perf_query_counter chv_tdl_1_query_counters[47]; +static struct brw_perf_query_info chv_tdl_1_query = { + .kind = OA_COUNTERS, + .name = "Metric set TDL_1", + .guid = "eb2fecba-b431-42e7-8261-fe9429a6e67a", + .counters = chv_tdl_1_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = chv_tdl_1_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = chv_tdl_1_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = chv_tdl_1_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +chv_register_tdl_1_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &chv_tdl_1_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16154D60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16352E60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16554D60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16950000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16B50000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16D50000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x083D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A3D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0458C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1FA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1F00AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04388000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06388000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00398000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0239A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0439A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06392000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x043A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x063A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08138000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A138000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06143000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0415CFC7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10150000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02338000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C338000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04342000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06344000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0035C700 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x063500CF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10350000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04538000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06538000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0454C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0255CFC7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10550000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06DC8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08DC4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CDCC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EDCC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ABD00A8 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CD8C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ED84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EDB8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18DB0800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ADB0254 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9FAA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109F02AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16B84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18B8156A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B98000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18BAA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ABA0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16934000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1893000A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A947000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C95C5C1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9500C3 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10950000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB38000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16B30040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18B30020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B48000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B41000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB48000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B5C500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B500C3 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB5C100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B50000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16D31500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08D4E000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08D5C100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AD5C3C5 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10D50000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D88F800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F88000F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258BAAA5 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B2A80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178C2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198C5500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8C0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAAA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0784C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1780C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800C42 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45800063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F8014A4 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41801042 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FDFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE7F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FFBF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFCF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFF7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFF9 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_1__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_1__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_1__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_1__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_1__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_1__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_1__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_1__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_1__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x10) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_1__ps_thread11_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice1 Subslice1 Thread Dispatcher"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice1 subslice1 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 56; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_1__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x20) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_1__non_ps_thread12_ready_for_dispatch__read; + counter->name = "Non-PS Thread Ready For Dispatch on Slice1 Subslice2 Thread Dispatcher"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice1 subslice2 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 72; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_1__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_1__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_1__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x8) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_1__non_ps_thread10_ready_for_dispatch__read; + counter->name = "Non-PS Thread Ready For Dispatch on Slice1 Subslice0 Thread Dispatcher"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice1 subslice0 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 104; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_1__thread_header01_ready_port0__read; + counter->name = "Thread Header Ready on Slice0 Subslice1 Thread Dispatcher Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 108; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_1__thread_header01_ready_port1__read; + counter->name = "Thread Header Ready on Slice0 Subslice1 Thread Dispatcher Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 112; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_1__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_1__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = chv__tdl_1__avg_gpu_core_frequency__max(brw); + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_1__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_1__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_1__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_1__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_1__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 164; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_1__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_1__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 172; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_1__thread_header02_ready_port1__read; + counter->name = "Thread Header Ready on Slice0 Subslice2 Thread Dispatcher Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_1__thread_header02_ready_port0__read; + counter->name = "Thread Header Ready on Slice0 Subslice2 Thread Dispatcher Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 180; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_1__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_1__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_1__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_1__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_1__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 216; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_1__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_1__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x20) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_1__ps_thread12_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice1 Subslice2 Thread Dispatcher"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice1 subslice2 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 240; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x8) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_1__ps_thread10_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice1 Subslice0 Thread Dispatcher"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice1 subslice0 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 244; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x10) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_1__non_ps_thread11_ready_for_dispatch__read; + counter->name = "Non-PS Thread Ready For Dispatch on Slice1 Subslice1 Thread Dispatcher"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice1 subslice1 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 248; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_1__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_1__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_1__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_1__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_1__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_1__thread_header00_ready_port0__read; + counter->name = "Thread Header Ready on Slice0 Subslice0 Thread Dispatcher Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 296; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_1__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_1__thread_header00_ready_port1__read; + counter->name = "Thread Header Ready on Slice0 Subslice0 Thread Dispatcher Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 312; + counter->size = sizeof(float); + } + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog chv_tdl_2_mux_regs[155]; +static struct brw_perf_query_register_prog chv_tdl_2_b_counter_regs[18]; +static struct brw_perf_query_register_prog chv_tdl_2_flex_regs[7]; + +static struct brw_perf_query_counter chv_tdl_2_query_counters[47]; +static struct brw_perf_query_info chv_tdl_2_query = { + .kind = OA_COUNTERS, + .name = "Metric set TDL_2", + .guid = "60749470-a648-4a4b-9f10-dbfe1e36e44d", + .counters = chv_tdl_2_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = chv_tdl_2_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = chv_tdl_2_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = chv_tdl_2_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +chv_register_tdl_2_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &chv_tdl_2_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16150000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16350000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16550000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16952E60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16B54D60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16D52E60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E3D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x183DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06588000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08588000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A584000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x185B5800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5B000A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1FAA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101F02AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16384000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18382A55 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06398000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0839A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A39A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C39A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E39A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A3A02A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E138000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16130500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06148000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08146000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0615C100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0815C500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1500C3 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10150000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16335040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08349000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A341000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x083500C1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A35C500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3500C3 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10350000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1853002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A54E000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C55C500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E55C1C3 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10550000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00DC8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02DCC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04DC4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04BD8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06BD8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02D8C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02DB8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04DB4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06DB4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08DB8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9FA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9F00AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB88000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB88000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B98000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B9A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B92000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ABA8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CBA8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0494C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0295CFC7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10950000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B38000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B38000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B42000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B41000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B5C700 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B500CF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B50000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AD38000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CD38000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06D46000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04D5C700 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06D500CF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10D50000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B888000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D880400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x198A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8AAAA0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B555A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x278B0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x238B5500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x098C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B8C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D8C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x018D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x078D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2185AAAA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2385002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F85AA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19835400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B830155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D834000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0784C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0984C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F84C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0384C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0584C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1780C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1980C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F80C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1580C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4F800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43800882 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45801082 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x478014A5 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F800002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41800C62 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FDFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE7F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FF9F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFE7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFFB }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFFD }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_2__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_2__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_2__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x10) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_2__thread_header11_ready_port1__read; + counter->name = "Thread Header Ready on Slice1 Subslice1 Thread Dispatcher Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice1 subslice1 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_2__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_2__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_2__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_2__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_2__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_2__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_2__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_2__non_ps_thread02_ready_for_dispatch__read; + counter->name = "Non-PS Thread Ready For Dispatch on Slice0 Subslice2 Thread Dispatcher"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 72; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_2__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_2__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_2__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_2__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_2__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = chv__tdl_2__avg_gpu_core_frequency__max(brw); + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_2__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_2__non_ps_thread00_ready_for_dispatch__read; + counter->name = "Non-PS Thread Ready For Dispatch on Slice0 Subslice0 Thread Dispatcher"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 128; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_2__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_2__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x10) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_2__thread_header11_ready_port0__read; + counter->name = "Thread Header Ready on Slice1 Subslice1 Thread Dispatcher Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice1 subslice1 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_2__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_2__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_2__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 164; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_2__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x20) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_2__thread_header12_ready_port0__read; + counter->name = "Thread Header Ready on Slice1 Subslice2 Thread Dispatcher Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice1 subslice2 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 172; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_2__ps_thread00_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice0 Thread Dispatcher"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_2__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_2__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_2__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_2__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x8) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_2__thread_header10_ready_port1__read; + counter->name = "Thread Header Ready on Slice1 Subslice0 Thread Dispatcher Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice1 subslice0 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 216; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_2__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 220; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_2__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_2__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_2__ps_thread01_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice1 Thread Dispatcher"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 240; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x20) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_2__thread_header12_ready_port1__read; + counter->name = "Thread Header Ready on Slice1 Subslice2 Thread Dispatcher Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice1 subslice2 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 244; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_2__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_2__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_2__ps_thread02_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice2 Thread Dispatcher"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 264; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_2__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_2__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_2__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x8) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_2__thread_header10_ready_port0__read; + counter->name = "Thread Header Ready on Slice1 Subslice0 Thread Dispatcher Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice1 subslice0 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 296; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__tdl_2__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = chv__tdl_2__non_ps_thread01_ready_for_dispatch__read; + counter->name = "Non-PS Thread Ready For Dispatch on Slice0 Subslice1 Thread Dispatcher"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 312; + counter->size = sizeof(float); + } + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog chv_test_oa_mux_regs[13]; +static struct brw_perf_query_register_prog chv_test_oa_b_counter_regs[22]; + +static struct brw_perf_query_counter chv_test_oa_query_counters[12]; +static struct brw_perf_query_info chv_test_oa_query = { + .kind = OA_COUNTERS, + .name = "MDAPI testing set Gen8LP", + .guid = "4a534b07-cba3-414d-8d60-874830e883aa", + .counters = chv_test_oa_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = chv_test_oa_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = chv_test_oa_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ +}; + +static void +chv_register_test_oa_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &chv_test_oa_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59800001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x338B0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x258B0066 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058B0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x038B0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03844000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47800080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x001823A4, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000004 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000003 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000007 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFF7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00100082 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFEF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x001000C2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FFE7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00100001 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FFE7 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__test_oa__counter7__read; + counter->name = "TestCounter7"; + counter->desc = "HW test counter 7. Factor: 0.666"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__test_oa__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 8; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__test_oa__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__test_oa__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = chv__test_oa__avg_gpu_core_frequency__max(brw); + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__test_oa__counter8__read; + counter->name = "TestCounter8"; + counter->desc = "HW test counter 8. Should be equal to 1."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__test_oa__counter4__read; + counter->name = "TestCounter4"; + counter->desc = "HW test counter 4. Factor: 0.333"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__test_oa__counter5__read; + counter->name = "TestCounter5"; + counter->desc = "HW test counter 5. Factor: 0.333"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__test_oa__counter6__read; + counter->name = "TestCounter6"; + counter->desc = "HW test counter 6. Factor: 0.166"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__test_oa__counter3__read; + counter->name = "TestCounter3"; + counter->desc = "HW test counter 3. Factor: 0.5"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__test_oa__counter0__read; + counter->name = "TestCounter0"; + counter->desc = "HW test counter 0. Factor: 0.0"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__test_oa__counter1__read; + counter->name = "TestCounter1"; + counter->desc = "HW test counter 1. Factor: 1.0"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = chv__test_oa__counter2__read; + counter->name = "TestCounter2"; + counter->desc = "HW test counter 2. Factor: 1.0"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +void +brw_oa_register_queries_chv(struct brw_context *brw) +{ + chv_register_render_basic_counter_query(brw); + chv_register_compute_basic_counter_query(brw); + chv_register_render_pipe_profile_counter_query(brw); + chv_register_hdc_and_sf_counter_query(brw); + chv_register_l3_1_counter_query(brw); + chv_register_l3_2_counter_query(brw); + chv_register_l3_3_counter_query(brw); + chv_register_l3_4_counter_query(brw); + chv_register_rasterizer_and_pixel_backend_counter_query(brw); + chv_register_sampler_1_counter_query(brw); + chv_register_sampler_2_counter_query(brw); + chv_register_tdl_1_counter_query(brw); + chv_register_tdl_2_counter_query(brw); + chv_register_test_oa_counter_query(brw); +} + +static struct brw_perf_query_register_prog sklgt2_render_basic_mux_regs[70]; +static struct brw_perf_query_register_prog sklgt2_render_basic_b_counter_regs[5]; +static struct brw_perf_query_register_prog sklgt2_render_basic_flex_regs[7]; + +static struct brw_perf_query_counter sklgt2_render_basic_query_counters[52]; +static struct brw_perf_query_info sklgt2_render_basic_query = { + .kind = OA_COUNTERS, + .name = "Render Metrics Basic Gen9", + .guid = "f519e481-24d2-4d42-87c9-3fdd12c00202", + .counters = sklgt2_render_basic_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt2_render_basic_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt2_render_basic_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt2_render_basic_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt2_register_render_basic_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt2_render_basic_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + if (brw->perfquery.sys_vars.revision >= 0x02) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C01E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12170280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12370280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11930317 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x159303DF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E0080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A6C0053 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C8400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F6600 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162C2200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00133000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08133000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00170020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08170021 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10170000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0633C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0833C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06370800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08370840 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10370000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D933031 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F933E3F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01933D00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0393073C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0593000E }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900157 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900158 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190001F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51904400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C21 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900061 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57904440 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900004 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53904444 }; + } + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_basic__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__render_basic__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_basic__l3_misses__read; + counter->name = "L3 Misses"; + counter->desc = "The total number of L3 misses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_basic__gti_l3_throughput__read; + counter->name = "GTI L3 Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__render_basic__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_basic__sampler_l1_misses__read; + counter->name = "Sampler Cache Misses"; + counter->desc = "The total number of sampler cache misses in all LODs in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__render_basic__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x12) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__render_basic__sampler1_bottleneck__read; + counter->name = "Sampler 1 Bottleneck"; + counter->desc = "The percentage of time in which Sampler 1 has been slowing down the pipe when processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 52; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__render_basic__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_basic__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_basic__l3_sampler_throughput__read; + counter->name = "L3 Sampler Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_basic__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__render_basic__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 88; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_basic__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_basic__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x09) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__render_basic__sampler0_busy__read; + counter->name = "Sampler 0 Busy"; + counter->desc = "The percentage of time in which Sampler 0 has been processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 112; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x12) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__render_basic__sampler1_busy__read; + counter->name = "Sampler 1 Busy"; + counter->desc = "The percentage of time in which Sampler 1 has been processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 116; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__render_basic__samplers_busy__read; + counter->name = "Samplers Busy"; + counter->desc = "The percentage of time in which samplers have been processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 120; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_basic__gti_vf_throughput__read; + counter->name = "GTI Fixed Pipe Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between 3D Pipeline (Command Dispatch, Input Assembly and Stream Output) and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_basic__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x09) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__render_basic__sampler0_bottleneck__read; + counter->name = "Sampler 0 Bottleneck"; + counter->desc = "The percentage of time in which Sampler 0 has been slowing down the pipe when processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_basic__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_basic__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_basic__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_basic__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt2__render_basic__avg_gpu_core_frequency__max(brw); + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_basic__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_basic__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_basic__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_basic__l3_lookups__read; + counter->name = "L3 Lookup Accesses w/o IC"; + counter->desc = "The total number of L3 cache lookup accesses w/o IC."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_basic__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_basic__gti_read_throughput__read; + counter->name = "GTI Read Throughput"; + counter->desc = "The total number of GPU memory bytes read from GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__render_basic__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 232; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__render_basic__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 236; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_basic__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__render_basic__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 248; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_basic__gti_depth_throughput__read; + counter->name = "GTI Depth Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between depth caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__render_basic__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 264; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__render_basic__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 268; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_basic__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_basic__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__render_basic__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 288; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_basic__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_basic__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__render_basic__sampler_bottleneck__read; + counter->name = "Samplers Bottleneck"; + counter->desc = "The percentage of time in which samplers have been slowing down the pipe when processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 312; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_basic__gti_hdc_lookups_throughput__read; + counter->name = "GTI HDC TLB Lookup Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between GTI and HDC, when HDC is doing TLB lookups."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_basic__gti_rcc_throughput__read; + counter->name = "GTI RCC Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between render color caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 328; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_basic__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 336; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_basic__gti_write_throughput__read; + counter->name = "GTI Write Throughput"; + counter->desc = "The total number of GPU memory bytes written to GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 344; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_basic__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 352; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_basic__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 360; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_basic__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 368; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_basic__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 376; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt2_compute_basic_mux_regs[157]; +static struct brw_perf_query_register_prog sklgt2_compute_basic_b_counter_regs[5]; +static struct brw_perf_query_register_prog sklgt2_compute_basic_flex_regs[7]; + +static struct brw_perf_query_counter sklgt2_compute_basic_query_counters[39]; +static struct brw_perf_query_info sklgt2_compute_basic_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics Basic Gen9", + .guid = "fe47b29d-ae51-423e-bff4-27d965a95b60", + .counters = sklgt2_compute_basic_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt2_compute_basic_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt2_compute_basic_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt2_compute_basic_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt2_register_compute_basic_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt2_compute_basic_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + if ((brw->perfquery.sys_vars.slice_mask & 0x01) && + (brw->perfquery.sys_vars.revision < 0x02)) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F00E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124F1C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C00E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F901403 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x184E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E8200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004F0DB2 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F0900 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084F1880 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4F0011 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4F0E3C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4F1D80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A6C0100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C000C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C000B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0012 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x105C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5CA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C5C002D }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0082 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CBE00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00EF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19900157 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B900167 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900105 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900103 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00000D28, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900FFF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900840 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900840 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900840 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900840 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53901111 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + } + + if ((brw->perfquery.sys_vars.slice_mask & 0x01) && + (brw->perfquery.sys_vars.revision >= 0x02)) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F00E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124F1C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C00E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F901403 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E0820 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F0900 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084F0032 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4F1810 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4F0E00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4F003C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004F0D80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024F003B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C6C000C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C0B00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0024 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C6000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C5C001B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0208 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CFB00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00BE }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19900157 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B900167 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900105 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900103 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900FFF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900802 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900802 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53901111 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + } + + if ((brw->perfquery.sys_vars.slice_mask & 0x02) && + (brw->perfquery.sys_vars.revision < 0x02)) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000000 }; + } + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_basic__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_basic__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_basic__untyped_bytes_read__read; + counter->name = "Untyped Bytes Read"; + counter->desc = "The total number of typed memory bytes read via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_basic__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_basic__typed_bytes_written__read; + counter->name = "Typed Bytes Written"; + counter->desc = "The total number of untyped memory bytes written via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_basic__fpu0_active__read; + counter->name = "EU FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_basic__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 44; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_basic__eu_avg_ipc_rate__read; + counter->name = "EU AVG IPC Rate"; + counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 2.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_basic__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_basic__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_basic__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_basic__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_basic__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_basic__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_basic__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_basic__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_basic__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt2__compute_basic__avg_gpu_core_frequency__max(brw); + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_basic__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_basic__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_basic__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_basic__gti_read_throughput__read; + counter->name = "GTI Read Throughput"; + counter->desc = "The total number of GPU memory bytes read from GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_basic__untyped_bytes_written__read; + counter->name = "Untyped Writes"; + counter->desc = "The total number of untyped memory bytes written via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_basic__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_basic__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_basic__typed_bytes_read__read; + counter->name = "Typed Bytes Read"; + counter->desc = "The total number of typed memory bytes read via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_basic__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_basic__eu_thread_occupancy__read; + counter->name = "EU Thread Occupancy"; + counter->desc = "The percentage of time in which hardware threads occupied EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_basic__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 204; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_basic__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_basic__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_basic__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_basic__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_basic__gti_write_throughput__read; + counter->name = "GTI Write Throughput"; + counter->desc = "The total number of GPU memory bytes written to GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_basic__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_basic__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_basic__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_basic__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_basic__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_basic__eu_send_active__read; + counter->name = "EU Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 288; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt2_render_pipe_profile_mux_regs[231]; +static struct brw_perf_query_register_prog sklgt2_render_pipe_profile_b_counter_regs[21]; +static struct brw_perf_query_register_prog sklgt2_render_pipe_profile_flex_regs[7]; + +static struct brw_perf_query_counter sklgt2_render_pipe_profile_query_counters[43]; +static struct brw_perf_query_info sklgt2_render_pipe_profile_query = { + .kind = OA_COUNTERS, + .name = "Render Metrics for 3D Pipeline Profile Gen9", + .guid = "e0ad5ae0-84ba-4f29-a723-1906c12cb774", + .counters = sklgt2_render_pipe_profile_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt2_render_pipe_profile_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt2_render_pipe_profile_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt2_render_pipe_profile_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt2_register_render_pipe_profile_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt2_render_pipe_profile_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + if (brw->perfquery.sys_vars.revision < 0x02) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0E001F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10116800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178A03E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11824C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11830020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13840020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11850019 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11860007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01870C40 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17880000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020E5400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000E0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080F0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06104000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06110012 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06131000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01898000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D890100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03898000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A0075 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8A4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x138A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D81A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15818000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17818000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B820030 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07828000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D824000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F828000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05824000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D830003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0583000C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09830000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03838000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07838000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B840980 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03844D80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11840000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09850080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03850003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01850000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07860000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F860400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09870032 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01888052 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11880000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09884000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15968000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17968000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F96C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F950011 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950014 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0592C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B928000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D924000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F924000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11928000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1392C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09924000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01985000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07988000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09981000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B982000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D982000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F989000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05982000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B978000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F974000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11974000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13978000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09974000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00000D28, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190C080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x419010A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45901000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900084 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57904400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x499000A5 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900081 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x439014A4 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + } + + if (brw->perfquery.sys_vars.revision >= 0x02) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0E001F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10116800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178A03E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11824C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11830020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13840020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11850019 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11860007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01870C40 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17880000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020E5400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000E0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080F0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06104000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06110012 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06131000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01898000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D890100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03898000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A0075 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8A4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x138A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D81A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15818000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17818000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B820030 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07828000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D824000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F828000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05824000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D830003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0583000C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09830000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03838000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07838000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B840980 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03844D80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11840000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09850080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03850003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01850000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07860000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F860400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09870032 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01888052 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11880000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09884000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B931001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D930001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19934000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B958000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950094 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19958000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05E5A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01E5C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0592C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B928000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D924000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F924000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11928000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1392C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09924000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01985000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07988000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09981000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B982000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D982000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F989000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05982000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190C080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x419010A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45901000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900084 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57904400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x499000A5 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900081 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x439014A4 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + } + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFEA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFC }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007AFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F5FD }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00079FFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000F3FB }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007BF7A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F7E7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FEFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000F7CF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00077FFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000EFDF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0006FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000CFBF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0003FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x00005F7F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__render_pipe_profile__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__render_pipe_profile__vs_bottleneck__read; + counter->name = "VS Bottleneck"; + counter->desc = "The percentage of time in which vertex shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__render_pipe_profile__hi_depth_bottleneck__read; + counter->name = "Hi-Depth Bottleneck"; + counter->desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__render_pipe_profile__gs_bottleneck__read; + counter->name = "GS Bottleneck"; + counter->desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__render_pipe_profile__bc_bottleneck__read; + counter->name = "BC Bottleneck"; + counter->desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__render_pipe_profile__hs_stall__read; + counter->name = "HS Stall"; + counter->desc = "The percentage of time in which hull stall pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 60; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt2__render_pipe_profile__avg_gpu_core_frequency__max(brw); + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__render_pipe_profile__vf_bottleneck__read; + counter->name = "VF Bottleneck"; + counter->desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__render_pipe_profile__sf_bottleneck__read; + counter->name = "Strip-Fans Bottleneck"; + counter->desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__render_pipe_profile__sf_stall__read; + counter->name = "SF Stall"; + counter->desc = "The percentage of time in which strip-fans pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 140; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__render_pipe_profile__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__render_pipe_profile__hs_bottleneck__read; + counter->name = "HS Bottleneck"; + counter->desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__render_pipe_profile__cl_stall__read; + counter->name = "CL Stall"; + counter->desc = "The percentage of time in which clipper pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__render_pipe_profile__so_bottleneck__read; + counter->name = "SO Bottleneck"; + counter->desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__render_pipe_profile__ds_bottleneck__read; + counter->name = "DS Bottleneck"; + counter->desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__render_pipe_profile__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 188; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__render_pipe_profile__cl_bottleneck__read; + counter->name = "Clipper Bottleneck"; + counter->desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__render_pipe_profile__ds_stall__read; + counter->name = "DS Stall"; + counter->desc = "The percentage of time in which domain shader pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 196; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__render_pipe_profile__early_depth_bottleneck__read; + counter->name = "Early Depth Bottleneck"; + counter->desc = "The percentage of time in which early depth test pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__render_pipe_profile__so_stall__read; + counter->name = "SO Stall"; + counter->desc = "The percentage of time in which stream-output pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__render_pipe_profile__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt2_memory_reads_mux_regs[168]; +static struct brw_perf_query_register_prog sklgt2_memory_reads_b_counter_regs[32]; +static struct brw_perf_query_register_prog sklgt2_memory_reads_flex_regs[7]; + +static struct brw_perf_query_counter sklgt2_memory_reads_query_counters[41]; +static struct brw_perf_query_info sklgt2_memory_reads_query = { + .kind = OA_COUNTERS, + .name = "Memory Reads Distribution Gen9", + .guid = "9bc436dd-6130-4add-affc-283eb6eaa864", + .counters = sklgt2_memory_reads_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt2_memory_reads_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt2_memory_reads_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt2_memory_reads_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt2_register_memory_reads_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt2_memory_reads_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + if ((brw->perfquery.sys_vars.slice_mask & 0x01) && + (brw->perfquery.sys_vars.revision < 0x02)) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1381001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13946000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03811300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05811B12 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0781001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F968000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1196C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13964000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B93FE00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01940010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07941100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09941312 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B941514 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D941716 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11940000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19940000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B940000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D940000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B954000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D95A550 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F9502AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F900157 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900105 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900103 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900101 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00000D28, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + } + + if ((brw->perfquery.sys_vars.revision < 0x05) && + (brw->perfquery.sys_vars.revision >= 0x02)) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1381001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13946000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15940016 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03811300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05811B12 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0781001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19930800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B93AA55 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D9300AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01940010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07941100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09941312 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B941514 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D941716 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F940018 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B940000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11940000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01E58000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E57000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900105 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900103 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900101 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C20 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900421 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900421 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900061 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + } + + if (brw->perfquery.sys_vars.revision >= 0x05) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1381001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900064 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03811300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05811B12 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0781001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E58000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05E5C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900150 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21900151 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23900152 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25900153 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27900154 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B900156 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D900157 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F90015F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900105 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900103 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900101 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C63 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900C63 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + } + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000272C, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002728, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000271C, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002718, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F872 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_reads__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__memory_reads__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_reads__gti_l3_bank0_reads__read; + counter->name = "GtiL3Bank0Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 0 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_reads__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_reads__gti_ring_accesses__read; + counter->name = "GtiRingAccesses"; + counter->desc = "The total number of all accesses from GTI to the ring."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_reads__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_reads__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_reads__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_reads__gti_l3_bank3_reads__read; + counter->name = "GtiL3Bank3Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 3 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_reads__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_reads__gti_rs_memory_reads__read; + counter->name = "GtiRsMemoryReads"; + counter->desc = "The total number of GTI memory reads from Resource Streamer."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_reads__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_reads__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_reads__gti_hiz_memory_reads__read; + counter->name = "GtiHizMemoryReads"; + counter->desc = "The total number of GTI memory reads from Hierarchical Depth Cache (Hi-Depth Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_reads__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_reads__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt2__memory_reads__avg_gpu_core_frequency__max(brw); + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_reads__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_reads__gti_rcc_memory_reads__read; + counter->name = "GtiRccMemoryReads"; + counter->desc = "The total number of GTI memory reads from Render Color Cache (Render Color Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_reads__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_reads__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_reads__gti_l3_bank1_reads__read; + counter->name = "GtiL3Bank1Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 1 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__memory_reads__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_reads__gti_cmd_streamer_memory_reads__read; + counter->name = "GtiCmdStreamerMemoryReads"; + counter->desc = "The total number of GTI memory reads from Command Streamer."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_reads__gti_l3_bank2_reads__read; + counter->name = "GtiL3Bank2Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 2 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_reads__gti_memory_reads__read; + counter->name = "GtiMemoryReads"; + counter->desc = "The total number of GTI memory reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_reads__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_reads__gti_rcz_memory_reads__read; + counter->name = "GtiRczMemoryReads"; + counter->desc = "The total number of GTI memory reads from Render Depth Cache (Render Depth Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_reads__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_reads__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__memory_reads__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 232; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_reads__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_reads__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_reads__gti_msc_memory_reads__read; + counter->name = "GtiMscMemoryReads"; + counter->desc = "The total number of GTI memory reads from Multisampling Color Cache (Multisampling Color Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_reads__gti_vf_memory_reads__read; + counter->name = "GtiVfMemoryReads"; + counter->desc = "The total number of GTI memory reads from Vertex Fetch."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_reads__gti_stc_memory_reads__read; + counter->name = "GtiStcMemoryReads"; + counter->desc = "The total number of GTI memory reads from Stencil Cache (Stencil Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_reads__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_reads__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_reads__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_reads__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_reads__gti_l3_reads__read; + counter->name = "GtiL3Reads"; + counter->desc = "The total number of GTI memory reads from L3 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_reads__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt2_memory_writes_mux_regs[167]; +static struct brw_perf_query_register_prog sklgt2_memory_writes_b_counter_regs[32]; +static struct brw_perf_query_register_prog sklgt2_memory_writes_flex_regs[7]; + +static struct brw_perf_query_counter sklgt2_memory_writes_query_counters[41]; +static struct brw_perf_query_info sklgt2_memory_writes_query = { + .kind = OA_COUNTERS, + .name = "Memory Writes Distribution Gen9", + .guid = "2ea0da8f-3527-4669-9d9d-13099a7435bf", + .counters = sklgt2_memory_writes_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt2_memory_writes_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt2_memory_writes_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt2_memory_writes_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt2_register_memory_writes_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt2_memory_writes_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + if ((brw->perfquery.sys_vars.slice_mask & 0x01) && + (brw->perfquery.sys_vars.revision < 0x02)) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1381001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13945400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F901400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03811300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05811B12 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0781001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F968000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1196C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13964000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B93FE00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01940010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07941100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09941312 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B941514 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D941716 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11940000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19940000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B940000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D940000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B954000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D95A550 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F9502AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F900167 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900105 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900103 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900101 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00000D28, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + } + + if ((brw->perfquery.sys_vars.revision < 0x05) && + (brw->perfquery.sys_vars.revision >= 0x02)) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1381001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13945400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F901400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03811300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05811B12 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0781001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19930800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B93AA55 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D93002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01940010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07941100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09941312 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B941514 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D941716 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B940000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11940000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01E58000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E57000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F900167 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900105 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900103 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900101 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C20 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900421 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900421 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + } + + if (brw->perfquery.sys_vars.revision >= 0x05) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1381001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F901000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03811300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05811B12 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0781001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E58000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05E5C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900160 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21900161 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23900162 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25900163 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27900164 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900165 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B900166 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D900167 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F900150 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900105 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900103 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900101 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C63 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900C63 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + } + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000272C, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002728, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000271C, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002718, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F822 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_writes__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__memory_writes__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_writes__gti_memory_writes__read; + counter->name = "GtiMemoryWrites"; + counter->desc = "The total number of GTI memory writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_writes__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_writes__gti_ring_accesses__read; + counter->name = "GtiRingAccesses"; + counter->desc = "The total number of all GTI accesses to the ring."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_writes__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_writes__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_writes__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_writes__gti_msc_memory_writes__read; + counter->name = "GtiMscMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Multisampling Color Cache (Multisampling Color Cache invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_writes__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_writes__gti_cmd_streamer_memory_writes__read; + counter->name = "GtiCmdStreamerMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Command Streamer."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_writes__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_writes__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_writes__gti_l3_bank0_writes__read; + counter->name = "GtiL3Bank0Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 0 (L3 Bank 0 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_writes__gti_l3_bank1_writes__read; + counter->name = "GtiL3Bank1Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 1 (L3 Bank 1 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_writes__gti_l3_bank2_writes__read; + counter->name = "GtiL3Bank2Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 2 (L3 Bank 2 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_writes__gti_l3_bank3_writes__read; + counter->name = "GtiL3Bank3Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 3 (L3 Bank 3 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_writes__gti_l3_writes__read; + counter->name = "GtiL3Writes"; + counter->desc = "The total number of GTI memory writes from L3 (L3 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_writes__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_writes__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt2__memory_writes__avg_gpu_core_frequency__max(brw); + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_writes__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_writes__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_writes__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_writes__gti_rcc_memory_writes__read; + counter->name = "GtiRccMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Render Color Cache (Render Color Cache invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_writes__gti_so_memory_writes__read; + counter->name = "GtiSoMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Stream Output."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__memory_writes__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_writes__gti_stc_memory_writes__read; + counter->name = "GtiStcMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Stencil Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_writes__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_writes__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_writes__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__memory_writes__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 240; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_writes__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_writes__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_writes__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_writes__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_writes__gti_rcz_memory_writes__read; + counter->name = "GtiRczMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Render Depth Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_writes__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_writes__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_writes__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_writes__gti_hiz_memory_writes__read; + counter->name = "GtiHizMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Hierarchical Depth Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__memory_writes__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt2_compute_extended_mux_regs[74]; +static struct brw_perf_query_register_prog sklgt2_compute_extended_b_counter_regs[21]; +static struct brw_perf_query_register_prog sklgt2_compute_extended_flex_regs[7]; + +static struct brw_perf_query_counter sklgt2_compute_extended_query_counters[38]; +static struct brw_perf_query_info sklgt2_compute_extended_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics Extended Gen9", + .guid = "d97d16af-028b-4cd1-a672-6210cb5513dd", + .counters = sklgt2_compute_extended_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt2_compute_extended_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt2_compute_extended_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt2_compute_extended_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt2_register_compute_extended_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt2_compute_extended_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + if (brw->perfquery.sys_vars.subslice_mask & 0x01) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C00E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8160 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C0120 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x184E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4EAAA0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C0B01 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C000C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001C0041 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061C4200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081C4443 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1C4645 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1C7647 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041C7357 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0030 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4CAA2A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C02AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5515 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CAA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00000D28, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11907FFF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900802 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + } + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FC2A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FC6A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007FC92 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007FCA2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FC32 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FC9A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007FE6A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007FE7A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000BF00 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_extended__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_extended__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_extended__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_extended__fpu0_active__read; + counter->name = "EU FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_extended__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_extended__eu_avg_ipc_rate__read; + counter->name = "EU AVG IPC Rate"; + counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 2.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_extended__typed_writes0__read; + counter->name = "Typed Writes 0"; + counter->desc = "The subslice 0 typed writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_extended__eu_typed_atomics0__read; + counter->name = "EuTypedAtomics0"; + counter->desc = "The subslice 0 EU Typed Atomics subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_extended__typed_atomics0__read; + counter->name = "Typed Atomics 0"; + counter->desc = "The subslice 0 typed atomics."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_extended__typed_atomics_per_cache_line__read; + counter->name = "TypedAtomicsPerCacheLine"; + counter->desc = "The ratio of EU typed atomics requests to L3 cache line writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_extended__eu_untyped_reads0__read; + counter->name = "EuUntypedReads0"; + counter->desc = "The subslice 0 EU Untyped Reads subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_extended__untyped_writes0__read; + counter->name = "Untyped Writes 0"; + counter->desc = "The subslice 0 untyped writes (including SLM writes)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_extended__eu_untyped_atomics0__read; + counter->name = "EuUntypedAtomics0"; + counter->desc = "The subslice 0 EU Untyped Atomics subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_extended__eu_untyped_writes0__read; + counter->name = "EuUntypedWrites0"; + counter->desc = "The subslice 0 EU Untyped Writes subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_extended__eu_a64_untyped_writes0__read; + counter->name = "EuA64UntypedWrites0"; + counter->desc = "The subslice 0 EU A64 Untyped Writes subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_extended__untyped_writes_per_cache_line__read; + counter->name = "UntypedWritesPerCacheLine"; + counter->desc = "The ratio of EU untyped write requests to L3 cache line writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_extended__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_extended__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_extended__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_extended__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt2__compute_extended__avg_gpu_core_frequency__max(brw); + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_extended__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_extended__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_extended__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_extended__eu_typed_writes0__read; + counter->name = "EuTypedWrites0"; + counter->desc = "The subslice 0 EU Typed Writes subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_extended__typed_writes_per_cache_line__read; + counter->name = "TypedWritesPerCacheLine"; + counter->desc = "The ratio of EU typed write requests to L3 cache line writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_extended__typed_reads0__read; + counter->name = "Typed Reads 0"; + counter->desc = "The subslice 0 typed reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_extended__untyped_reads0__read; + counter->name = "Untyped Reads 0"; + counter->desc = "The subslice 0 untyped reads (including SLM reads)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_extended__eu_a64_untyped_reads0__read; + counter->name = "EuA64UntypedReads0"; + counter->desc = "The subslice 0 EU A64 Untyped Reads subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_extended__eu_thread_occupancy__read; + counter->name = "EU Thread Occupancy"; + counter->desc = "The percentage of time in which hardware threads occupied EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 208; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_extended__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 212; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_extended__eu_typed_reads0__read; + counter->name = "EuTypedReads0"; + counter->desc = "The subslice 0 EU Typed Reads subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_extended__untyped_reads_per_cache_line__read; + counter->name = "UntypedReadsPerCacheLine"; + counter->desc = "The ratio of EU untyped read requests to L3 cache line reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_extended__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_extended__typed_reads_per_cache_line__read; + counter->name = "TypedReadsPerCacheLine"; + counter->desc = "The ratio of EU typed read requests to L3 cache line reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_extended__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_extended__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_extended__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_extended__eu_send_active__read; + counter->name = "EU Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 272; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt2_compute_l3_cache_mux_regs[61]; +static struct brw_perf_query_register_prog sklgt2_compute_l3_cache_b_counter_regs[13]; +static struct brw_perf_query_register_prog sklgt2_compute_l3_cache_flex_regs[7]; + +static struct brw_perf_query_counter sklgt2_compute_l3_cache_query_counters[54]; +static struct brw_perf_query_info sklgt2_compute_l3_cache_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics L3 Cache Gen9", + .guid = "9fb22842-e708-43f7-9752-e0e41670c39e", + .counters = sklgt2_compute_l3_cache_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt2_compute_l3_cache_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt2_compute_l3_cache_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt2_compute_l3_cache_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt2_register_compute_l3_cache_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt2_compute_l3_cache_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C0760 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1593001E }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F901403 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x184E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E8020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0051 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C5C5D }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C5E5F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1CE000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0030 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C2A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F1500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0140 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162C0A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03933300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05930032 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900157 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900167 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190030F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900042 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53901111 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900420 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FEFE }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FEFD }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FBEF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FBDF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00101100 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00201200 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00301300 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00401400 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_l3_cache__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__l3_bank03_accesses__read; + counter->name = "L3 Bank 03 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 03."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__l3_accesses__read; + counter->name = "L3 Accesses"; + counter->desc = "The total number of L3 accesses from all entities."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_l3_cache__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__l3_sampler_throughput__read; + counter->name = "L3 Sampler Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_l3_cache__fpu0_active__read; + counter->name = "EU FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_l3_cache__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 52; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_l3_cache__eu_avg_ipc_rate__read; + counter->name = "EU AVG IPC Rate"; + counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 2.0; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_l3_cache__eu_binary_fpu0_instruction__read; + counter->name = "EU FPU0 Binary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 60; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_l3_cache__eu_hybrid_fpu0_instruction__read; + counter->name = "EU FPU0 Hybrid Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 104; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__l3_misses__read; + counter->name = "L3 Misses"; + counter->desc = "The total number of L3 misses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__l3_bank00_accesses__read; + counter->name = "L3 Bank 00 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 00."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_l3_cache__eu_move_fpu0_instruction__read; + counter->name = "EU FPU0 Move Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_l3_cache__eu_hybrid_fpu1_instruction__read; + counter->name = "EU FPU1 Hybrid Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt2__compute_l3_cache__avg_gpu_core_frequency__max(brw); + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__gti_read_throughput__read; + counter->name = "GTI Read Throughput"; + counter->desc = "The total number of GPU memory bytes read from GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__gti_l3_throughput__read; + counter->name = "GTI L3 Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__l3_bank00_ic_accesses__read; + counter->name = "L3 Bank 00 IC Accesses"; + counter->desc = "The total number of accesses to L3 Bank 00 from IC cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + } + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__l3_bank00_ic_hits__read; + counter->name = "L3 Bank 00 IC Hits"; + counter->desc = "The total number of hits in L3 Bank 00 from IC cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__sampler_accesses__read; + counter->name = "Sampler Accesses"; + counter->desc = "The total number of messages send to samplers."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__l3_bank01_accesses__read; + counter->name = "L3 Bank 01 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 01."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_l3_cache__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 256; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_l3_cache__eu_ternary_fpu0_instruction__read; + counter->name = "EU FPU0 Ternary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 260; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_l3_cache__eu_move_fpu1_instruction__read; + counter->name = "EU FPU1 Move Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 296; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_l3_cache__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 300; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__l3_bank02_accesses__read; + counter->name = "L3 Bank 02 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 02."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 328; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__l3_total_throughput__read; + counter->name = "L3 Total Throughput"; + counter->desc = "The total number of GPU memory bytes transferred via L3."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 336; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__gti_write_throughput__read; + counter->name = "GTI Write Throughput"; + counter->desc = "The total number of GPU memory bytes written to GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 344; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 352; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 360; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_l3_cache__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 368; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_l3_cache__eu_binary_fpu1_instruction__read; + counter->name = "EU FPU1 Binary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 376; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_l3_cache__eu_ternary_fpu1_instruction__read; + counter->name = "EU FPU1 Ternary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 380; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_l3_cache__eu_send_active__read; + counter->name = "EU Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 384; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt2_hdc_and_sf_mux_regs[55]; +static struct brw_perf_query_register_prog sklgt2_hdc_and_sf_b_counter_regs[8]; +static struct brw_perf_query_register_prog sklgt2_hdc_and_sf_flex_regs[7]; + +static struct brw_perf_query_counter sklgt2_hdc_and_sf_query_counters[39]; +static struct brw_perf_query_info sklgt2_hdc_and_sf_query = { + .kind = OA_COUNTERS, + .name = "Metric set HDCAndSF", + .guid = "5378e2a1-4248-4188-a4ae-da25a794c603", + .counters = sklgt2_hdc_and_sf_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt2_hdc_and_sf_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt2_hdc_and_sf_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt2_hdc_and_sf_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt2_register_hdc_and_sf_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt2_hdc_and_sf_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F0232 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124F4640 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0232 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11834400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004F1880 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024F08BB }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044F001B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C0100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C000B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C1800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x165C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x185C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C00A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F828000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8305C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09830000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07830000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13928000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F988000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B9000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FDFF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__hdc_and_sf__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__hdc_and_sf__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__hdc_and_sf__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__hdc_and_sf__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__hdc_and_sf__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__hdc_and_sf__poly_data_ready__read; + counter->name = "Polygon Data Ready"; + counter->desc = "The percentage of time in which geometry pipeline output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt2__hdc_and_sf__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read; + counter->name = "HDC stalled by L3 (s0.ss1)"; + counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss1)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 120; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read; + counter->name = "HDC stalled by L3 (s0.ss2)"; + counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss2)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__hdc_and_sf__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__hdc_and_sf__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__hdc_and_sf__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__hdc_and_sf__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 164; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__hdc_and_sf__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__hdc_and_sf__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read; + counter->name = "HDC stalled by L3 (s0.ss0)"; + counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss0)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 264; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__hdc_and_sf__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt2_l3_1_mux_regs[72]; +static struct brw_perf_query_register_prog sklgt2_l3_1_b_counter_regs[22]; +static struct brw_perf_query_register_prog sklgt2_l3_1_flex_regs[7]; + +static struct brw_perf_query_counter sklgt2_l3_1_query_counters[39]; +static struct brw_perf_query_info sklgt2_l3_1_query = { + .kind = OA_COUNTERS, + .name = "Metric set L3_1", + .guid = "f42cdd6a-b000-42cb-870f-5eb423a7f514", + .counters = sklgt2_l3_1_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt2_l3_1_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt2_l3_1_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt2_l3_1_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt2_register_l3_1_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt2_l3_1_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C7B40 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C0020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A603444 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A613400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4EA800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C6C5327 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C5425 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C2A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C285B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C005C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C003C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10600000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04600000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C610044 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10610000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06610000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C02A8 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0154 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FFC0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900420 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900021 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900421 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00014002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000C3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00010002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000C7FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00004002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000D3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100700 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FF1F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00001402 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FC3F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00001002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FC7F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00000402 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FD3F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_1__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_1__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_1__l30_bank1_active__read; + counter->name = "Slice0 L3 Bank1 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank1 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_1__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_1__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_1__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_1__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_1__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_1__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_1__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_1__l30_bank1_stalled__read; + counter->name = "Slice0 L3 Bank1 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank1 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_1__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_1__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_1__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_1__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_1__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_1__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt2__l3_1__avg_gpu_core_frequency__max(brw); + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_1__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_1__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_1__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_1__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_1__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_1__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_1__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_1__l30_bank0_active__read; + counter->name = "Slice0 L3 Bank0 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank0 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_1__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_1__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_1__l30_bank0_stalled__read; + counter->name = "Slice0 L3 Bank0 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank0 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 180; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_1__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_1__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_1__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_1__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_1__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_1__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_1__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_1__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_1__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_1__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_1__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt2_l3_2_mux_regs[45]; +static struct brw_perf_query_register_prog sklgt2_l3_2_b_counter_regs[14]; +static struct brw_perf_query_register_prog sklgt2_l3_2_flex_regs[7]; + +static struct brw_perf_query_counter sklgt2_l3_2_query_counters[37]; +static struct brw_perf_query_info sklgt2_l3_2_query = { + .kind = OA_COUNTERS, + .name = "Metric set L3_2", + .guid = "b9bf2423-d88c-4a7b-a051-627611d00dcc", + .counters = sklgt2_l3_2_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt2_l3_2_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt2_l3_2_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt2_l3_2_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt2_register_l3_2_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt2_l3_2_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C02E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146C0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A623400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C3324 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C3422 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06614000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C620044 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10620000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06620000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190F800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00028002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x000087FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00020002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00008FFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00008002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000A7FF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_2__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_2__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_2__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_2__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_2__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_2__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_2__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_2__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_2__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_2__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_2__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_2__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_2__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_2__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_2__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt2__l3_2__avg_gpu_core_frequency__max(brw); + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_2__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_2__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_2__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_2__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 128; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_2__l30_bank2_stalled__read; + counter->name = "Slice0 L3 Bank2 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank2 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 132; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_2__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_2__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 140; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_2__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_2__l30_bank2_active__read; + counter->name = "Slice0 L3 Bank2 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank2 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_2__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_2__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_2__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_2__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_2__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 184; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_2__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_2__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_2__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_2__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_2__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_2__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_2__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_2__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt2_l3_3_mux_regs[44]; +static struct brw_perf_query_register_prog sklgt2_l3_3_b_counter_regs[14]; +static struct brw_perf_query_register_prog sklgt2_l3_3_flex_regs[7]; + +static struct brw_perf_query_counter sklgt2_l3_3_query_counters[37]; +static struct brw_perf_query_info sklgt2_l3_3_query = { + .kind = OA_COUNTERS, + .name = "Metric set L3_3", + .guid = "2414a93d-d84f-406e-99c0-472161194b40", + .counters = sklgt2_l3_3_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt2_l3_3_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt2_l3_3_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt2_l3_3_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt2_register_l3_3_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt2_l3_3_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C4E80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A633400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C3321 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C342F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C1800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06604000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C630044 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10630000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06630000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C00AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190F800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00028002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x000087FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00020002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00008FFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00008002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000A7FF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_3__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_3__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_3__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_3__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_3__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_3__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_3__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_3__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_3__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_3__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_3__l30_bank3_stalled__read; + counter->name = "Slice0 L3 Bank3 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank3 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_3__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_3__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_3__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_3__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_3__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt2__l3_3__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_3__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_3__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_3__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_3__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_3__l30_bank3_active__read; + counter->name = "Slice0 L3 Bank3 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank3 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 140; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_3__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_3__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_3__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_3__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_3__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_3__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_3__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__l3_3__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_3__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_3__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_3__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_3__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_3__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_3__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_3__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__l3_3__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt2_rasterizer_and_pixel_backend_mux_regs[32]; +static struct brw_perf_query_register_prog sklgt2_rasterizer_and_pixel_backend_b_counter_regs[10]; +static struct brw_perf_query_register_prog sklgt2_rasterizer_and_pixel_backend_flex_regs[7]; + +static struct brw_perf_query_counter sklgt2_rasterizer_and_pixel_backend_query_counters[40]; +static struct brw_perf_query_info sklgt2_rasterizer_and_pixel_backend_query = { + .kind = OA_COUNTERS, + .name = "Metric set RasterizerAndPixelBackend", + .guid = "53a45d2d-170b-4cf5-b7bb-585120c8e2f5", + .counters = sklgt2_rasterizer_and_pixel_backend_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt2_rasterizer_and_pixel_backend_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt2_rasterizer_and_pixel_backend_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt2_rasterizer_and_pixel_backend_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt2_register_rasterizer_and_pixel_backend_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt2_rasterizer_and_pixel_backend_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102F3800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x144D0500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x120D03C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x140D03CF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0004 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F0480 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0090 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064D0027 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004D0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D0D40 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020D803F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040D8023 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100D0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020F0010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0050 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41901400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43901485 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000EFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00006000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F3FF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__rasterizer_and_pixel_backend__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__rasterizer_and_pixel_backend__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__rasterizer_and_pixel_backend__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__rasterizer_and_pixel_backend__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__rasterizer_and_pixel_backend__pixel_values0_ready__read; + counter->name = "Slice0 Pixel Values Ready"; + counter->desc = "The percentage of time in which slice0 pixel values are ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__rasterizer_and_pixel_backend__rasterizer0_input_available__read; + counter->name = "Slice0 Rasterizer Input Available"; + counter->desc = "The percentage of time in which slice0 rasterizer input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 128; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__rasterizer_and_pixel_backend__pixel_data0_ready__read; + counter->name = "Slice0 Post-EarlyZ Pixel Data Ready"; + counter->desc = "The percentage of time in which slice0 post-EarlyZ pixel data is ready (after early Z tests have been applied)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 132; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__rasterizer_and_pixel_backend__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__rasterizer_and_pixel_backend__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__rasterizer_and_pixel_backend__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__rasterizer_and_pixel_backend__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__rasterizer_and_pixel_backend__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__rasterizer_and_pixel_backend__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__rasterizer_and_pixel_backend__rasterizer0_output_ready__read; + counter->name = "Slice0 Rasterizer Output Ready"; + counter->desc = "The percentage of time in which slice0 rasterizer output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 196; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__rasterizer_and_pixel_backend__ps_output0_available__read; + counter->name = "Slice0 PS Output Available"; + counter->desc = "The percentage of time in which slice0 PS output is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 256; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__rasterizer_and_pixel_backend__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt2_sampler_mux_regs[70]; +static struct brw_perf_query_register_prog sklgt2_sampler_b_counter_regs[12]; +static struct brw_perf_query_register_prog sklgt2_sampler_flex_regs[7]; + +static struct brw_perf_query_counter sklgt2_sampler_query_counters[41]; +static struct brw_perf_query_info sklgt2_sampler_query = { + .kind = OA_COUNTERS, + .name = "Metric set Sampler", + .guid = "b4cff514-a91e-4798-a0b3-426ca13fc9c1", + .counters = sklgt2_sampler_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt2_sampler_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt2_sampler_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt2_sampler_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt2_register_sampler_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt2_sampler_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14152C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16150005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121600A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14352C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16350005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123600A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14552C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16550005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125600A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062F6000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0050 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0350 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FB000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F00DA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C0028 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C138000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E132000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0413C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C140018 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C157000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E150078 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10150000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04162180 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02160000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04174000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0233A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04333000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14348000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16348000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02357870 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10350000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04360043 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02360000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04371000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E538000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00538000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06533000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C540020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12548000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E557000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00557800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10550000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06560043 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02560000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06571000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FF80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900060 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900060 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x70800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0000C000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000E7FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00003000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F9FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000C00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE7F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__sampler__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__sampler__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__sampler__sampler02_input_available__read; + counter->name = "Slice0 Subslice2 Input Available"; + counter->desc = "The percentage of time in which slice0 subslice2 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__sampler__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__sampler__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__sampler__sampler00_input_available__read; + counter->name = "Slice0 Subslice0 Input Available"; + counter->desc = "The percentage of time in which slice0 subslice0 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__sampler__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 28; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__sampler__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__sampler__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__sampler__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__sampler__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__sampler__sampler02_output_ready__read; + counter->name = "Slice0 Subslice2 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice0 subslice2 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__sampler__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__sampler__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__sampler__sampler01_input_available__read; + counter->name = "Slice0 Subslice1 Input Available"; + counter->desc = "The percentage of time in which slice0 subslice1 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 88; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__sampler__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__sampler__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__sampler__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__sampler__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt2__sampler__avg_gpu_core_frequency__max(brw); + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__sampler__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__sampler__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__sampler__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__sampler__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__sampler__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__sampler__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__sampler__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 164; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__sampler__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__sampler__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__sampler__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__sampler__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__sampler__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__sampler__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__sampler__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__sampler__sampler00_output_ready__read; + counter->name = "Slice0 Subslice0 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice0 subslice0 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 224; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__sampler__sampler01_output_ready__read; + counter->name = "Slice0 Subslice1 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice0 subslice1 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 228; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__sampler__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__sampler__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__sampler__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__sampler__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__sampler__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__sampler__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt2_tdl_1_mux_regs[69]; +static struct brw_perf_query_register_prog sklgt2_tdl_1_b_counter_regs[18]; +static struct brw_perf_query_register_prog sklgt2_tdl_1_flex_regs[7]; + +static struct brw_perf_query_counter sklgt2_tdl_1_query_counters[41]; +static struct brw_perf_query_info sklgt2_tdl_1_query = { + .kind = OA_COUNTERS, + .name = "Metric set TDL_1", + .guid = "7821d13b-9b8b-4405-9618-78cd56b62cce", + .counters = sklgt2_tdl_1_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt2_tdl_1_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt2_tdl_1_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt2_tdl_1_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt2_register_tdl_1_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt2_tdl_1_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12120000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12320000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12520000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F3000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F03A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FF000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0095 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02108000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0410C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02118000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0411C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02121880 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041219B5 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02134000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04135000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C308000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E304000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06304000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C318000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E314000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06314000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C321A80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E320033 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06320031 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00320000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C334000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E331000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06331000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E508000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00508000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02504000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E518000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00518000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02514000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E521880 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00521A80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02520033 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E534000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00534000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02531000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FF80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900062 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00009FFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000EFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FDFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE7F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_1__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__tdl_1__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__tdl_1__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__tdl_1__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__tdl_1__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_1__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_1__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__tdl_1__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_1__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_1__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__tdl_1__non_ps_thread02_ready_for_dispatch__read; + counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice2"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_1__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_1__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_1__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_1__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_1__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt2__tdl_1__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_1__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__tdl_1__non_ps_thread00_ready_for_dispatch__read; + counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice0"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 120; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_1__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_1__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__tdl_1__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__tdl_1__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__tdl_1__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__tdl_1__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__tdl_1__ps_thread00_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice0"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_1__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__tdl_1__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_1__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_1__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__tdl_1__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_1__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_1__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__tdl_1__ps_thread01_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice1"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 224; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_1__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_1__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__tdl_1__ps_thread02_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice2"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 248; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_1__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_1__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_1__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_1__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__tdl_1__non_ps_thread01_ready_for_dispatch__read; + counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice1"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 288; + counter->size = sizeof(float); + } + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt2_tdl_2_mux_regs[43]; +static struct brw_perf_query_register_prog sklgt2_tdl_2_b_counter_regs[6]; +static struct brw_perf_query_register_prog sklgt2_tdl_2_flex_regs[7]; + +static struct brw_perf_query_counter sklgt2_tdl_2_query_counters[41]; +static struct brw_perf_query_info sklgt2_tdl_2_query = { + .kind = OA_COUNTERS, + .name = "Metric set TDL_2", + .guid = "893f1a4d-919d-4388-8cb7-746d73ea7259", + .counters = sklgt2_tdl_2_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt2_tdl_2_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt2_tdl_2_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt2_tdl_2_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt2_register_tdl_2_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt2_tdl_2_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x000000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12124D60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12322E60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12524D60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F3000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0014 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FE000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0097 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0410C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0411C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04121FB7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04135000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00308000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06304000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00318000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06314000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00321B80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0632003F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00334000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06331000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0250C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0251C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02521FB7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00520000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02535000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_2__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__tdl_2__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__tdl_2__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__tdl_2__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__tdl_2__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_2__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_2__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__tdl_2__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_2__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_2__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_2__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_2__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_2__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__tdl_2__thread_header01_ready_port0__read; + counter->name = "Thread Header Ready on Slice0 Subslice1 Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 88; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__tdl_2__thread_header01_ready_port1__read; + counter->name = "Thread Header Ready on Slice0 Subslice1 Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 92; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_2__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_2__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt2__tdl_2__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_2__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_2__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_2__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__tdl_2__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__tdl_2__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 140; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__tdl_2__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__tdl_2__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__tdl_2__thread_header02_ready_port1__read; + counter->name = "Thread Header Ready on Slice0 Subslice2 Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__tdl_2__thread_header02_ready_port0__read; + counter->name = "Thread Header Ready on Slice0 Subslice2 Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_2__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__tdl_2__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_2__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_2__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__tdl_2__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_2__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_2__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_2__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_2__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_2__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_2__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_2__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__tdl_2__thread_header00_ready_port0__read; + counter->name = "Thread Header Ready on Slice0 Subslice0 Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 256; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__tdl_2__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__tdl_2__thread_header00_ready_port1__read; + counter->name = "Thread Header Ready on Slice0 Subslice0 Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 272; + counter->size = sizeof(float); + } + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt2_compute_extra_mux_regs[32]; +static struct brw_perf_query_register_prog sklgt2_compute_extra_b_counter_regs[6]; +static struct brw_perf_query_register_prog sklgt2_compute_extra_flex_regs[7]; + +static struct brw_perf_query_counter sklgt2_compute_extra_query_counters[5]; +static struct brw_perf_query_info sklgt2_compute_extra_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics Extra Gen9", + .guid = "41a24047-7484-4ead-ae37-de907e5ff2b2", + .counters = sklgt2_compute_extra_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt2_compute_extra_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt2_compute_extra_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt2_compute_extra_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt2_register_compute_extra_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt2_compute_extra_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121203E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123203E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125203E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F006C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06104000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06114000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06120033 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06131000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04308000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04318000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04321980 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00320000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04334000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04504000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04514000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04520033 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00520000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04531000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190E000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00001000 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00003002 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00011010 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00050012 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00052051 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00000008 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_extra__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_extra__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_extra__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__compute_extra__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt2__compute_extra__avg_gpu_core_frequency__max(brw); + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__compute_extra__fpu1_active_adjusted__read; + counter->name = "EU FPU1 Pipe Active including Ext Math"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing including Extended Math processing"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt2_vme_pipe_mux_regs[62]; +static struct brw_perf_query_register_prog sklgt2_vme_pipe_b_counter_regs[17]; +static struct brw_perf_query_register_prog sklgt2_vme_pipe_flex_regs[2]; + +static struct brw_perf_query_counter sklgt2_vme_pipe_query_counters[10]; +static struct brw_perf_query_info sklgt2_vme_pipe_query = { + .kind = OA_COUNTERS, + .name = "Media Vme Pipe Gen9", + .guid = "95910492-943f-44bd-9461-390240f243fd", + .counters = sklgt2_vme_pipe_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt2_vme_pipe_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt2_vme_pipe_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt2_vme_pipe_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt2_register_vme_pipe_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt2_vme_pipe_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141A5800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161A00C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12180240 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14180002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143A5800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x163A00C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12380240 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14380002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F3000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C1500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F9500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162C0A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04193000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081A28C1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00133000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0613C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0813F000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00172000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06178000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0817A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00180037 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06180940 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08180000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02180000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04183000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06393000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3A28C1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A33F000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C33F000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A37A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C37A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A380977 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08380000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04380000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06383000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x119000FF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47901000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900844 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100030 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF9 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FFFC }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FFF3 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100180 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFCF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FF3F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00008003 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__vme_pipe__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__vme_pipe__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__vme_pipe__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__vme_pipe__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__vme_pipe__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt2__vme_pipe__avg_gpu_core_frequency__max(brw); + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__vme_pipe__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__vme_pipe__eu_thread_occupancy__read; + counter->name = "EU Thread Occupancy"; + counter->desc = "The percentage of time in which hardware threads occupied EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__vme_pipe__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 44; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__vme_pipe__vme_busy__read; + counter->name = "VME Busy"; + counter->desc = "The percentage of time in which VME (IME or CRE) was actively processing data."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__vme_pipe__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 52; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt2_gpu_busyness_mux_regs[34]; +static struct brw_perf_query_register_prog sklgt2_gpu_busyness_b_counter_regs[7]; + +static struct brw_perf_query_counter sklgt2_gpu_busyness_query_counters[8]; +static struct brw_perf_query_info sklgt2_gpu_busyness_query = { + .kind = OA_COUNTERS, + .name = "Gpu Rings Busyness", + .guid = "c44a5cf7-886d-477b-bebd-2d738923e4c3", + .counters = sklgt2_gpu_busyness_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt2_gpu_busyness_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt2_gpu_busyness_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt2_register_gpu_busyness_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt2_gpu_busyness_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13805800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05962C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19950016 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21C05800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07800035 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07960025 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21960000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B964000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930062 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17948000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B940008 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05950075 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09924000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05982000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09978000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0BC000A5 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11C00000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05C00000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0BC54000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900C60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00078000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00000FFF }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__gpu_busyness__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__gpu_busyness__vebox_busy__read; + counter->name = "Vebox Ring Busy"; + counter->desc = "The percentage of time when vebox command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__gpu_busyness__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__gpu_busyness__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt2__gpu_busyness__avg_gpu_core_frequency__max(brw); + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__gpu_busyness__render_busy__read; + counter->name = "Render Ring Busy"; + counter->desc = "The percentage of time when render command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__gpu_busyness__vdbox0_busy__read; + counter->name = "Vdbox0 Ring Busy"; + counter->desc = "The percentage of time when Vdbox0 command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 36; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__gpu_busyness__blitter_busy__read; + counter->name = "Blitter Ring Busy"; + counter->desc = "The percentage of time when blitter command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt2__gpu_busyness__any_ring_busy__read; + counter->name = "AnyRingBusy"; + counter->desc = "The percentage of time when any command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 44; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt2_test_oa_mux_regs[13]; +static struct brw_perf_query_register_prog sklgt2_test_oa_b_counter_regs[21]; + +static struct brw_perf_query_counter sklgt2_test_oa_query_counters[12]; +static struct brw_perf_query_info sklgt2_test_oa_query = { + .kind = OA_COUNTERS, + .name = "MDAPI testing set Gen9", + .guid = "1651949f-0ac0-4cb1-a06f-dafd74a407d1", + .counters = sklgt2_test_oa_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt2_test_oa_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt2_test_oa_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt2_register_test_oa_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt2_test_oa_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07810016 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000004 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000003 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000007 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFF7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00100082 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFEF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x001000C2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FFE7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00100001 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FFE7 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__test_oa__counter7__read; + counter->name = "TestCounter7"; + counter->desc = "HW test counter 7. Factor: 0.666"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__test_oa__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 8; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__test_oa__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__test_oa__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt2__test_oa__avg_gpu_core_frequency__max(brw); + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__test_oa__counter8__read; + counter->name = "TestCounter8"; + counter->desc = "HW test counter 8. Should be equal to 1."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__test_oa__counter4__read; + counter->name = "TestCounter4"; + counter->desc = "HW test counter 4. Factor: 0.333"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__test_oa__counter5__read; + counter->name = "TestCounter5"; + counter->desc = "HW test counter 5. Factor: 0.333"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__test_oa__counter6__read; + counter->name = "TestCounter6"; + counter->desc = "HW test counter 6. Factor: 0.166"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__test_oa__counter3__read; + counter->name = "TestCounter3"; + counter->desc = "HW test counter 3. Factor: 0.5"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__test_oa__counter0__read; + counter->name = "TestCounter0"; + counter->desc = "HW test counter 0. Factor: 0.0"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__test_oa__counter1__read; + counter->name = "TestCounter1"; + counter->desc = "HW test counter 1. Factor: 1.0"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt2__test_oa__counter2__read; + counter->name = "TestCounter2"; + counter->desc = "HW test counter 2. Factor: 1.0"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +void +brw_oa_register_queries_sklgt2(struct brw_context *brw) +{ + sklgt2_register_render_basic_counter_query(brw); + sklgt2_register_compute_basic_counter_query(brw); + sklgt2_register_render_pipe_profile_counter_query(brw); + sklgt2_register_memory_reads_counter_query(brw); + sklgt2_register_memory_writes_counter_query(brw); + sklgt2_register_compute_extended_counter_query(brw); + sklgt2_register_compute_l3_cache_counter_query(brw); + sklgt2_register_hdc_and_sf_counter_query(brw); + sklgt2_register_l3_1_counter_query(brw); + sklgt2_register_l3_2_counter_query(brw); + sklgt2_register_l3_3_counter_query(brw); + sklgt2_register_rasterizer_and_pixel_backend_counter_query(brw); + sklgt2_register_sampler_counter_query(brw); + sklgt2_register_tdl_1_counter_query(brw); + sklgt2_register_tdl_2_counter_query(brw); + sklgt2_register_compute_extra_counter_query(brw); + sklgt2_register_vme_pipe_counter_query(brw); + sklgt2_register_gpu_busyness_counter_query(brw); + sklgt2_register_test_oa_counter_query(brw); +} + +static struct brw_perf_query_register_prog sklgt3_render_basic_mux_regs[83]; +static struct brw_perf_query_register_prog sklgt3_render_basic_b_counter_regs[5]; +static struct brw_perf_query_register_prog sklgt3_render_basic_flex_regs[7]; + +static struct brw_perf_query_counter sklgt3_render_basic_query_counters[52]; +static struct brw_perf_query_info sklgt3_render_basic_query = { + .kind = OA_COUNTERS, + .name = "Render Metrics Basic Gen9", + .guid = "4616d450-2393-4836-8146-53c5ed84d359", + .counters = sklgt3_render_basic_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt3_render_basic_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt3_render_basic_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt3_render_basic_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt3_register_render_basic_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt3_render_basic_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C01E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12170280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12370280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16EC01E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11930317 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x159303DF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E0380 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A6C0053 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C8400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F6600 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CA200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00133000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08133000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00170020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08170021 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10170000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0633C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0833C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06370800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08370840 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10370000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ACE0200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AEC5300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10EC0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CEC0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A9B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C9C0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CCC0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A8D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x108F0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16AC8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D933031 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F933E3F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01933D00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0393073C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0593000E }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900157 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900158 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190003F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51907710 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x419020A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55901515 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900529 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47901025 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57907770 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49902100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900108 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43902108 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53907777 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_basic__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__render_basic__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_basic__l3_misses__read; + counter->name = "L3 Misses"; + counter->desc = "The total number of L3 misses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_basic__gti_l3_throughput__read; + counter->name = "GTI L3 Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__render_basic__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_basic__sampler_l1_misses__read; + counter->name = "Sampler Cache Misses"; + counter->desc = "The total number of sampler cache misses in all LODs in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__render_basic__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x12) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__render_basic__sampler1_bottleneck__read; + counter->name = "Sampler 1 Bottleneck"; + counter->desc = "The percentage of time in which Sampler 1 has been slowing down the pipe when processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 52; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__render_basic__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_basic__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_basic__l3_sampler_throughput__read; + counter->name = "L3 Sampler Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_basic__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__render_basic__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 88; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_basic__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_basic__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x09) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__render_basic__sampler0_busy__read; + counter->name = "Sampler 0 Busy"; + counter->desc = "The percentage of time in which Sampler 0 has been processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 112; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x12) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__render_basic__sampler1_busy__read; + counter->name = "Sampler 1 Busy"; + counter->desc = "The percentage of time in which Sampler 1 has been processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 116; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__render_basic__samplers_busy__read; + counter->name = "Samplers Busy"; + counter->desc = "The percentage of time in which samplers have been processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 120; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_basic__gti_vf_throughput__read; + counter->name = "GTI Fixed Pipe Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between 3D Pipeline (Command Dispatch, Input Assembly and Stream Output) and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_basic__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x09) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__render_basic__sampler0_bottleneck__read; + counter->name = "Sampler 0 Bottleneck"; + counter->desc = "The percentage of time in which Sampler 0 has been slowing down the pipe when processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_basic__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_basic__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_basic__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_basic__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt3__render_basic__avg_gpu_core_frequency__max(brw); + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_basic__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_basic__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_basic__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_basic__l3_lookups__read; + counter->name = "L3 Lookup Accesses w/o IC"; + counter->desc = "The total number of L3 cache lookup accesses w/o IC."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_basic__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_basic__gti_read_throughput__read; + counter->name = "GTI Read Throughput"; + counter->desc = "The total number of GPU memory bytes read from GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__render_basic__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 232; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__render_basic__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 236; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_basic__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__render_basic__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 248; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_basic__gti_depth_throughput__read; + counter->name = "GTI Depth Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between depth caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__render_basic__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 264; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__render_basic__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 268; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_basic__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_basic__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__render_basic__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 288; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_basic__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_basic__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__render_basic__sampler_bottleneck__read; + counter->name = "Samplers Bottleneck"; + counter->desc = "The percentage of time in which samplers have been slowing down the pipe when processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 312; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_basic__gti_hdc_lookups_throughput__read; + counter->name = "GTI HDC TLB Lookup Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between GTI and HDC, when HDC is doing TLB lookups."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_basic__gti_rcc_throughput__read; + counter->name = "GTI RCC Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between render color caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 328; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_basic__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 336; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_basic__gti_write_throughput__read; + counter->name = "GTI Write Throughput"; + counter->desc = "The total number of GPU memory bytes written to GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 344; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_basic__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 352; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_basic__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 360; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_basic__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 368; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_basic__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 376; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt3_compute_basic_mux_regs[78]; +static struct brw_perf_query_register_prog sklgt3_compute_basic_b_counter_regs[5]; +static struct brw_perf_query_register_prog sklgt3_compute_basic_flex_regs[7]; + +static struct brw_perf_query_counter sklgt3_compute_basic_query_counters[39]; +static struct brw_perf_query_info sklgt3_compute_basic_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics Basic Gen9", + .guid = "4320492b-fd03-42ac-922f-dbe1ef3b7b58", + .counters = sklgt3_compute_basic_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt3_compute_basic_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt3_compute_basic_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt3_compute_basic_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt3_register_compute_basic_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt3_compute_basic_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F00E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124F1C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C00E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E0820 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F0900 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084F0032 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4F1891 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4F0E00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4F003C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004F0D80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024F003B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C0100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C6C000C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C0B00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0024 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C6000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C5C001B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0208 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CFB00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00BE }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19900157 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B900158 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900105 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900103 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900FFF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900863 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900802 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900802 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900C62 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53903333 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_basic__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_basic__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_basic__untyped_bytes_read__read; + counter->name = "Untyped Bytes Read"; + counter->desc = "The total number of typed memory bytes read via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_basic__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_basic__typed_bytes_written__read; + counter->name = "Typed Bytes Written"; + counter->desc = "The total number of untyped memory bytes written via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_basic__fpu0_active__read; + counter->name = "EU FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_basic__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 44; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_basic__eu_avg_ipc_rate__read; + counter->name = "EU AVG IPC Rate"; + counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 2.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_basic__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_basic__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_basic__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_basic__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_basic__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_basic__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_basic__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_basic__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_basic__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt3__compute_basic__avg_gpu_core_frequency__max(brw); + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_basic__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_basic__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_basic__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_basic__gti_read_throughput__read; + counter->name = "GTI Read Throughput"; + counter->desc = "The total number of GPU memory bytes read from GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_basic__untyped_bytes_written__read; + counter->name = "Untyped Writes"; + counter->desc = "The total number of untyped memory bytes written via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_basic__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_basic__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_basic__typed_bytes_read__read; + counter->name = "Typed Bytes Read"; + counter->desc = "The total number of typed memory bytes read via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_basic__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_basic__eu_thread_occupancy__read; + counter->name = "EU Thread Occupancy"; + counter->desc = "The percentage of time in which hardware threads occupied EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_basic__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 204; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_basic__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_basic__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_basic__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_basic__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_basic__gti_write_throughput__read; + counter->name = "GTI Write Throughput"; + counter->desc = "The total number of GPU memory bytes written to GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_basic__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_basic__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_basic__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_basic__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_basic__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_basic__eu_send_active__read; + counter->name = "EU Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 288; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt3_render_pipe_profile_mux_regs[114]; +static struct brw_perf_query_register_prog sklgt3_render_pipe_profile_b_counter_regs[21]; +static struct brw_perf_query_register_prog sklgt3_render_pipe_profile_flex_regs[7]; + +static struct brw_perf_query_counter sklgt3_render_pipe_profile_query_counters[43]; +static struct brw_perf_query_info sklgt3_render_pipe_profile_query = { + .kind = OA_COUNTERS, + .name = "Render Metrics for 3D Pipeline Profile Gen9", + .guid = "bd2d9cae-b9ec-4f5b-9d2f-934bed398a2d", + .counters = sklgt3_render_pipe_profile_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt3_render_pipe_profile_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt3_render_pipe_profile_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt3_render_pipe_profile_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt3_register_render_pipe_profile_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt3_render_pipe_profile_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0E001F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10116800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178A03E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11824C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11830020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13840020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11850019 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11860007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01870C40 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17880000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020E5400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000E0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080F0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06104000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06110012 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06131000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01898000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D890100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03898000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A0075 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8A4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x138A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D81A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15818000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17818000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B820030 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07828000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D824000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F828000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05824000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D830003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0583000C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09830000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03838000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07838000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B840980 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03844D80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11840000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09850080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03850003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01850000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07860000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F860400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09870032 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01888052 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11880000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09884000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B931001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D930001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19934000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B958000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950094 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19958000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09E58000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0BE58000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E5C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0592C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B928000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D924000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F924000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11928000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1392C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09924000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01985000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07988000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09981000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B982000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D982000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F989000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05982000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190C080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51901150 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41901400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55905111 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45901400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x479004A5 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57903455 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B9000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900455 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFEA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFC }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007AFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F5FD }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00079FFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000F3FB }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007BF7A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F7E7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FEFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000F7CF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00077FFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000EFDF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0006FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000CFBF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0003FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x00005F7F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__render_pipe_profile__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__render_pipe_profile__vs_bottleneck__read; + counter->name = "VS Bottleneck"; + counter->desc = "The percentage of time in which vertex shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__render_pipe_profile__hi_depth_bottleneck__read; + counter->name = "Hi-Depth Bottleneck"; + counter->desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__render_pipe_profile__gs_bottleneck__read; + counter->name = "GS Bottleneck"; + counter->desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__render_pipe_profile__bc_bottleneck__read; + counter->name = "BC Bottleneck"; + counter->desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__render_pipe_profile__hs_stall__read; + counter->name = "HS Stall"; + counter->desc = "The percentage of time in which hull stall pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 60; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt3__render_pipe_profile__avg_gpu_core_frequency__max(brw); + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__render_pipe_profile__vf_bottleneck__read; + counter->name = "VF Bottleneck"; + counter->desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__render_pipe_profile__sf_bottleneck__read; + counter->name = "Strip-Fans Bottleneck"; + counter->desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__render_pipe_profile__sf_stall__read; + counter->name = "SF Stall"; + counter->desc = "The percentage of time in which strip-fans pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 140; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__render_pipe_profile__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__render_pipe_profile__hs_bottleneck__read; + counter->name = "HS Bottleneck"; + counter->desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__render_pipe_profile__cl_stall__read; + counter->name = "CL Stall"; + counter->desc = "The percentage of time in which clipper pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__render_pipe_profile__so_bottleneck__read; + counter->name = "SO Bottleneck"; + counter->desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__render_pipe_profile__ds_bottleneck__read; + counter->name = "DS Bottleneck"; + counter->desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__render_pipe_profile__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 188; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__render_pipe_profile__cl_bottleneck__read; + counter->name = "Clipper Bottleneck"; + counter->desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__render_pipe_profile__ds_stall__read; + counter->name = "DS Stall"; + counter->desc = "The percentage of time in which domain shader pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 196; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__render_pipe_profile__early_depth_bottleneck__read; + counter->name = "Early Depth Bottleneck"; + counter->desc = "The percentage of time in which early depth test pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__render_pipe_profile__so_stall__read; + counter->name = "SO Stall"; + counter->desc = "The percentage of time in which stream-output pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__render_pipe_profile__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt3_memory_reads_mux_regs[47]; +static struct brw_perf_query_register_prog sklgt3_memory_reads_b_counter_regs[32]; +static struct brw_perf_query_register_prog sklgt3_memory_reads_flex_regs[7]; + +static struct brw_perf_query_counter sklgt3_memory_reads_query_counters[41]; +static struct brw_perf_query_info sklgt3_memory_reads_query = { + .kind = OA_COUNTERS, + .name = "Memory Reads Distribution Gen9", + .guid = "4ca0f3fe-7fd3-4924-98cb-1807d9879767", + .counters = sklgt3_memory_reads_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt3_memory_reads_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt3_memory_reads_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt3_memory_reads_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt3_register_memory_reads_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt3_memory_reads_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1381001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900064 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03811300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05811B12 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0781001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E58000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05E5C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900150 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21900151 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23900152 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25900153 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27900154 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B900156 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D900157 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F90015F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900105 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900103 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900101 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C63 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900C63 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000272C, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002728, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000271C, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002718, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F872 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_reads__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__memory_reads__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_reads__gti_l3_bank0_reads__read; + counter->name = "GtiL3Bank0Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 0 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_reads__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_reads__gti_ring_accesses__read; + counter->name = "GtiRingAccesses"; + counter->desc = "The total number of all accesses from GTI to the ring."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_reads__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_reads__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_reads__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_reads__gti_l3_bank3_reads__read; + counter->name = "GtiL3Bank3Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 3 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_reads__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_reads__gti_rs_memory_reads__read; + counter->name = "GtiRsMemoryReads"; + counter->desc = "The total number of GTI memory reads from Resource Streamer."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_reads__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_reads__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_reads__gti_hiz_memory_reads__read; + counter->name = "GtiHizMemoryReads"; + counter->desc = "The total number of GTI memory reads from Hierarchical Depth Cache (Hi-Depth Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_reads__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_reads__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt3__memory_reads__avg_gpu_core_frequency__max(brw); + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_reads__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_reads__gti_rcc_memory_reads__read; + counter->name = "GtiRccMemoryReads"; + counter->desc = "The total number of GTI memory reads from Render Color Cache (Render Color Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_reads__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_reads__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_reads__gti_l3_bank1_reads__read; + counter->name = "GtiL3Bank1Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 1 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__memory_reads__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_reads__gti_cmd_streamer_memory_reads__read; + counter->name = "GtiCmdStreamerMemoryReads"; + counter->desc = "The total number of GTI memory reads from Command Streamer."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_reads__gti_l3_bank2_reads__read; + counter->name = "GtiL3Bank2Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 2 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_reads__gti_memory_reads__read; + counter->name = "GtiMemoryReads"; + counter->desc = "The total number of GTI memory reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_reads__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_reads__gti_rcz_memory_reads__read; + counter->name = "GtiRczMemoryReads"; + counter->desc = "The total number of GTI memory reads from Render Depth Cache (Render Depth Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_reads__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_reads__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__memory_reads__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 232; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_reads__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_reads__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_reads__gti_msc_memory_reads__read; + counter->name = "GtiMscMemoryReads"; + counter->desc = "The total number of GTI memory reads from Multisampling Color Cache (Multisampling Color Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_reads__gti_vf_memory_reads__read; + counter->name = "GtiVfMemoryReads"; + counter->desc = "The total number of GTI memory reads from Vertex Fetch."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_reads__gti_stc_memory_reads__read; + counter->name = "GtiStcMemoryReads"; + counter->desc = "The total number of GTI memory reads from Stencil Cache (Stencil Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_reads__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_reads__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_reads__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_reads__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_reads__gti_l3_reads__read; + counter->name = "GtiL3Reads"; + counter->desc = "The total number of GTI memory reads from L3 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_reads__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt3_memory_writes_mux_regs[47]; +static struct brw_perf_query_register_prog sklgt3_memory_writes_b_counter_regs[32]; +static struct brw_perf_query_register_prog sklgt3_memory_writes_flex_regs[7]; + +static struct brw_perf_query_counter sklgt3_memory_writes_query_counters[41]; +static struct brw_perf_query_info sklgt3_memory_writes_query = { + .kind = OA_COUNTERS, + .name = "Memory Writes Distribution Gen9", + .guid = "a0c0172c-ee13-403d-99ff-2bdf6936cf14", + .counters = sklgt3_memory_writes_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt3_memory_writes_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt3_memory_writes_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt3_memory_writes_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt3_register_memory_writes_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt3_memory_writes_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1381001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F901000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03811300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05811B12 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0781001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E58000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05E5C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900160 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21900161 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23900162 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25900163 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27900164 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900165 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B900166 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D900167 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F900150 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900105 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900103 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900101 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C63 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900C63 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000272C, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002728, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000271C, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002718, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F822 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_writes__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__memory_writes__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_writes__gti_memory_writes__read; + counter->name = "GtiMemoryWrites"; + counter->desc = "The total number of GTI memory writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_writes__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_writes__gti_ring_accesses__read; + counter->name = "GtiRingAccesses"; + counter->desc = "The total number of all GTI accesses to the ring."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_writes__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_writes__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_writes__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_writes__gti_msc_memory_writes__read; + counter->name = "GtiMscMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Multisampling Color Cache (Multisampling Color Cache invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_writes__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_writes__gti_cmd_streamer_memory_writes__read; + counter->name = "GtiCmdStreamerMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Command Streamer."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_writes__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_writes__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_writes__gti_l3_bank0_writes__read; + counter->name = "GtiL3Bank0Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 0 (L3 Bank 0 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_writes__gti_l3_bank1_writes__read; + counter->name = "GtiL3Bank1Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 1 (L3 Bank 1 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_writes__gti_l3_bank2_writes__read; + counter->name = "GtiL3Bank2Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 2 (L3 Bank 2 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_writes__gti_l3_bank3_writes__read; + counter->name = "GtiL3Bank3Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 3 (L3 Bank 3 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_writes__gti_l3_writes__read; + counter->name = "GtiL3Writes"; + counter->desc = "The total number of GTI memory writes from L3 (L3 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_writes__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_writes__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt3__memory_writes__avg_gpu_core_frequency__max(brw); + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_writes__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_writes__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_writes__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_writes__gti_rcc_memory_writes__read; + counter->name = "GtiRccMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Render Color Cache (Render Color Cache invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_writes__gti_so_memory_writes__read; + counter->name = "GtiSoMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Stream Output."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__memory_writes__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_writes__gti_stc_memory_writes__read; + counter->name = "GtiStcMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Stencil Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_writes__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_writes__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_writes__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__memory_writes__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 240; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_writes__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_writes__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_writes__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_writes__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_writes__gti_rcz_memory_writes__read; + counter->name = "GtiRczMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Render Depth Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_writes__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_writes__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_writes__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_writes__gti_hiz_memory_writes__read; + counter->name = "GtiHizMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Hierarchical Depth Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__memory_writes__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt3_compute_extended_mux_regs[72]; +static struct brw_perf_query_register_prog sklgt3_compute_extended_b_counter_regs[21]; +static struct brw_perf_query_register_prog sklgt3_compute_extended_flex_regs[7]; + +static struct brw_perf_query_counter sklgt3_compute_extended_query_counters[38]; +static struct brw_perf_query_info sklgt3_compute_extended_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics Extended Gen9", + .guid = "52435e0b-f188-42ea-8680-21a56ee20dee", + .counters = sklgt3_compute_extended_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt3_compute_extended_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt3_compute_extended_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt3_compute_extended_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt3_register_compute_extended_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt3_compute_extended_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C00E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8160 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C0120 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x184E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4EAAA0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C0B01 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C000C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001C0041 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061C4200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081C4443 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1C4645 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1C7647 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041C7357 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0030 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4CAA2A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C02AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5515 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CAA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11907FFF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900802 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FC2A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FC6A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007FC92 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007FCA2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FC32 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FC9A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007FE6A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007FE7A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000BF00 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_extended__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_extended__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_extended__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_extended__fpu0_active__read; + counter->name = "EU FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_extended__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_extended__eu_avg_ipc_rate__read; + counter->name = "EU AVG IPC Rate"; + counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 2.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_extended__typed_writes0__read; + counter->name = "Typed Writes 0"; + counter->desc = "The subslice 0 typed writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_extended__eu_typed_atomics0__read; + counter->name = "EuTypedAtomics0"; + counter->desc = "The subslice 0 EU Typed Atomics subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_extended__typed_atomics0__read; + counter->name = "Typed Atomics 0"; + counter->desc = "The subslice 0 typed atomics."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_extended__typed_atomics_per_cache_line__read; + counter->name = "TypedAtomicsPerCacheLine"; + counter->desc = "The ratio of EU typed atomics requests to L3 cache line writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_extended__eu_untyped_reads0__read; + counter->name = "EuUntypedReads0"; + counter->desc = "The subslice 0 EU Untyped Reads subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_extended__untyped_writes0__read; + counter->name = "Untyped Writes 0"; + counter->desc = "The subslice 0 untyped writes (including SLM writes)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_extended__eu_untyped_atomics0__read; + counter->name = "EuUntypedAtomics0"; + counter->desc = "The subslice 0 EU Untyped Atomics subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_extended__eu_untyped_writes0__read; + counter->name = "EuUntypedWrites0"; + counter->desc = "The subslice 0 EU Untyped Writes subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_extended__eu_a64_untyped_writes0__read; + counter->name = "EuA64UntypedWrites0"; + counter->desc = "The subslice 0 EU A64 Untyped Writes subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_extended__untyped_writes_per_cache_line__read; + counter->name = "UntypedWritesPerCacheLine"; + counter->desc = "The ratio of EU untyped write requests to L3 cache line writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_extended__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_extended__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_extended__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_extended__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt3__compute_extended__avg_gpu_core_frequency__max(brw); + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_extended__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_extended__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_extended__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_extended__eu_typed_writes0__read; + counter->name = "EuTypedWrites0"; + counter->desc = "The subslice 0 EU Typed Writes subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_extended__typed_writes_per_cache_line__read; + counter->name = "TypedWritesPerCacheLine"; + counter->desc = "The ratio of EU typed write requests to L3 cache line writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_extended__typed_reads0__read; + counter->name = "Typed Reads 0"; + counter->desc = "The subslice 0 typed reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_extended__untyped_reads0__read; + counter->name = "Untyped Reads 0"; + counter->desc = "The subslice 0 untyped reads (including SLM reads)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_extended__eu_a64_untyped_reads0__read; + counter->name = "EuA64UntypedReads0"; + counter->desc = "The subslice 0 EU A64 Untyped Reads subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_extended__eu_thread_occupancy__read; + counter->name = "EU Thread Occupancy"; + counter->desc = "The percentage of time in which hardware threads occupied EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 208; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_extended__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 212; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_extended__eu_typed_reads0__read; + counter->name = "EuTypedReads0"; + counter->desc = "The subslice 0 EU Typed Reads subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_extended__untyped_reads_per_cache_line__read; + counter->name = "UntypedReadsPerCacheLine"; + counter->desc = "The ratio of EU untyped read requests to L3 cache line reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_extended__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_extended__typed_reads_per_cache_line__read; + counter->name = "TypedReadsPerCacheLine"; + counter->desc = "The ratio of EU typed read requests to L3 cache line reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_extended__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_extended__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_extended__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_extended__eu_send_active__read; + counter->name = "EU Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 272; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt3_compute_l3_cache_mux_regs[60]; +static struct brw_perf_query_register_prog sklgt3_compute_l3_cache_b_counter_regs[13]; +static struct brw_perf_query_register_prog sklgt3_compute_l3_cache_flex_regs[7]; + +static struct brw_perf_query_counter sklgt3_compute_l3_cache_query_counters[54]; +static struct brw_perf_query_info sklgt3_compute_l3_cache_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics L3 Cache Gen9", + .guid = "27076eeb-49f3-4fed-8423-c66506005c63", + .counters = sklgt3_compute_l3_cache_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt3_compute_l3_cache_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt3_compute_l3_cache_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt3_compute_l3_cache_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt3_register_compute_l3_cache_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt3_compute_l3_cache_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C0760 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1593001E }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x184E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E8020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0051 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C5C5D }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C5E5F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1CE000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0030 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C2A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F1500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0140 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162C0A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03933300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05930032 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900157 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900158 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190030F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53903333 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900840 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FEFE }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FEFD }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FBEF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FBDF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00101100 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00201200 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00301300 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00401400 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_l3_cache__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__l3_bank03_accesses__read; + counter->name = "L3 Bank 03 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 03."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__l3_accesses__read; + counter->name = "L3 Accesses"; + counter->desc = "The total number of L3 accesses from all entities."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_l3_cache__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__l3_sampler_throughput__read; + counter->name = "L3 Sampler Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_l3_cache__fpu0_active__read; + counter->name = "EU FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_l3_cache__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 52; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_l3_cache__eu_avg_ipc_rate__read; + counter->name = "EU AVG IPC Rate"; + counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 2.0; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_l3_cache__eu_binary_fpu0_instruction__read; + counter->name = "EU FPU0 Binary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 60; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_l3_cache__eu_hybrid_fpu0_instruction__read; + counter->name = "EU FPU0 Hybrid Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 104; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__l3_misses__read; + counter->name = "L3 Misses"; + counter->desc = "The total number of L3 misses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__l3_bank00_accesses__read; + counter->name = "L3 Bank 00 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 00."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_l3_cache__eu_move_fpu0_instruction__read; + counter->name = "EU FPU0 Move Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_l3_cache__eu_hybrid_fpu1_instruction__read; + counter->name = "EU FPU1 Hybrid Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt3__compute_l3_cache__avg_gpu_core_frequency__max(brw); + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__gti_read_throughput__read; + counter->name = "GTI Read Throughput"; + counter->desc = "The total number of GPU memory bytes read from GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__gti_l3_throughput__read; + counter->name = "GTI L3 Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__l3_bank00_ic_accesses__read; + counter->name = "L3 Bank 00 IC Accesses"; + counter->desc = "The total number of accesses to L3 Bank 00 from IC cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + } + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__l3_bank00_ic_hits__read; + counter->name = "L3 Bank 00 IC Hits"; + counter->desc = "The total number of hits in L3 Bank 00 from IC cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__sampler_accesses__read; + counter->name = "Sampler Accesses"; + counter->desc = "The total number of messages send to samplers."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__l3_bank01_accesses__read; + counter->name = "L3 Bank 01 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 01."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_l3_cache__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 256; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_l3_cache__eu_ternary_fpu0_instruction__read; + counter->name = "EU FPU0 Ternary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 260; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_l3_cache__eu_move_fpu1_instruction__read; + counter->name = "EU FPU1 Move Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 296; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_l3_cache__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 300; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__l3_bank02_accesses__read; + counter->name = "L3 Bank 02 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 02."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 328; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__l3_total_throughput__read; + counter->name = "L3 Total Throughput"; + counter->desc = "The total number of GPU memory bytes transferred via L3."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 336; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__gti_write_throughput__read; + counter->name = "GTI Write Throughput"; + counter->desc = "The total number of GPU memory bytes written to GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 344; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 352; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 360; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_l3_cache__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 368; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_l3_cache__eu_binary_fpu1_instruction__read; + counter->name = "EU FPU1 Binary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 376; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_l3_cache__eu_ternary_fpu1_instruction__read; + counter->name = "EU FPU1 Ternary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 380; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_l3_cache__eu_send_active__read; + counter->name = "EU Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 384; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt3_hdc_and_sf_mux_regs[54]; +static struct brw_perf_query_register_prog sklgt3_hdc_and_sf_b_counter_regs[8]; +static struct brw_perf_query_register_prog sklgt3_hdc_and_sf_flex_regs[7]; + +static struct brw_perf_query_counter sklgt3_hdc_and_sf_query_counters[39]; +static struct brw_perf_query_info sklgt3_hdc_and_sf_query = { + .kind = OA_COUNTERS, + .name = "Metric set HDCAndSF", + .guid = "8071b409-c39a-4674-94d7-32962ecfb512", + .counters = sklgt3_hdc_and_sf_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt3_hdc_and_sf_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt3_hdc_and_sf_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt3_hdc_and_sf_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt3_register_hdc_and_sf_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt3_hdc_and_sf_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F0232 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124F4640 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0232 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11834400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004F1880 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024F08BB }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044F001B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C0100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C000B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C1800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x165C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x185C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C00A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F828000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8305C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09830000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07830000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13928000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F988000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FDFF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__hdc_and_sf__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__hdc_and_sf__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__hdc_and_sf__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__hdc_and_sf__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__hdc_and_sf__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__hdc_and_sf__poly_data_ready__read; + counter->name = "Polygon Data Ready"; + counter->desc = "The percentage of time in which geometry pipeline output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt3__hdc_and_sf__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read; + counter->name = "HDC stalled by L3 (s0.ss1)"; + counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss1)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 120; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read; + counter->name = "HDC stalled by L3 (s0.ss2)"; + counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss2)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__hdc_and_sf__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__hdc_and_sf__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__hdc_and_sf__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__hdc_and_sf__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 164; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__hdc_and_sf__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__hdc_and_sf__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read; + counter->name = "HDC stalled by L3 (s0.ss0)"; + counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss0)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 264; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__hdc_and_sf__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt3_l3_1_mux_regs[71]; +static struct brw_perf_query_register_prog sklgt3_l3_1_b_counter_regs[22]; +static struct brw_perf_query_register_prog sklgt3_l3_1_flex_regs[7]; + +static struct brw_perf_query_counter sklgt3_l3_1_query_counters[39]; +static struct brw_perf_query_info sklgt3_l3_1_query = { + .kind = OA_COUNTERS, + .name = "Metric set L3_1", + .guid = "5e0b391e-9ea8-4901-b2ff-b64ff616c7ed", + .counters = sklgt3_l3_1_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt3_l3_1_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt3_l3_1_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt3_l3_1_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt3_register_l3_1_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt3_l3_1_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C7B40 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C0020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A603444 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A613400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4EA800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C6C5327 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C5425 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C2A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C285B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C005C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C003C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10600000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04600000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C610044 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10610000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06610000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C02A8 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0154 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FFC0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900420 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900021 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900421 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00014002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000C3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00010002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000C7FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00004002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000D3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100700 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FF1F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00001402 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FC3F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00001002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FC7F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00000402 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FD3F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_1__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_1__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_1__l30_bank1_active__read; + counter->name = "Slice0 L3 Bank1 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank1 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_1__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_1__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_1__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_1__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_1__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_1__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_1__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_1__l30_bank1_stalled__read; + counter->name = "Slice0 L3 Bank1 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank1 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_1__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_1__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_1__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_1__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_1__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_1__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt3__l3_1__avg_gpu_core_frequency__max(brw); + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_1__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_1__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_1__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_1__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_1__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_1__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_1__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_1__l30_bank0_active__read; + counter->name = "Slice0 L3 Bank0 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank0 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_1__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_1__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_1__l30_bank0_stalled__read; + counter->name = "Slice0 L3 Bank0 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank0 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 180; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_1__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_1__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_1__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_1__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_1__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_1__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_1__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_1__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_1__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_1__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_1__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt3_l3_2_mux_regs[44]; +static struct brw_perf_query_register_prog sklgt3_l3_2_b_counter_regs[14]; +static struct brw_perf_query_register_prog sklgt3_l3_2_flex_regs[7]; + +static struct brw_perf_query_counter sklgt3_l3_2_query_counters[37]; +static struct brw_perf_query_info sklgt3_l3_2_query = { + .kind = OA_COUNTERS, + .name = "Metric set L3_2", + .guid = "25dc828e-1d2d-426e-9546-a1d4233cdf16", + .counters = sklgt3_l3_2_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt3_l3_2_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt3_l3_2_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt3_l3_2_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt3_register_l3_2_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt3_l3_2_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C02E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146C0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A623400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C3324 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C3422 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06614000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C620044 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10620000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06620000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190F800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00028002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x000087FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00020002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00008FFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00008002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000A7FF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_2__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_2__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_2__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_2__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_2__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_2__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_2__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_2__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_2__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_2__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_2__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_2__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_2__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_2__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_2__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt3__l3_2__avg_gpu_core_frequency__max(brw); + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_2__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_2__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_2__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_2__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 128; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_2__l30_bank2_stalled__read; + counter->name = "Slice0 L3 Bank2 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank2 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 132; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_2__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_2__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 140; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_2__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_2__l30_bank2_active__read; + counter->name = "Slice0 L3 Bank2 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank2 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_2__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_2__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_2__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_2__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_2__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 184; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_2__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_2__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_2__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_2__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_2__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_2__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_2__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_2__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt3_l3_3_mux_regs[43]; +static struct brw_perf_query_register_prog sklgt3_l3_3_b_counter_regs[14]; +static struct brw_perf_query_register_prog sklgt3_l3_3_flex_regs[7]; + +static struct brw_perf_query_counter sklgt3_l3_3_query_counters[37]; +static struct brw_perf_query_info sklgt3_l3_3_query = { + .kind = OA_COUNTERS, + .name = "Metric set L3_3", + .guid = "3dba9405-2d7e-4d70-8199-e734e82fd6bf", + .counters = sklgt3_l3_3_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt3_l3_3_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt3_l3_3_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt3_l3_3_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt3_register_l3_3_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt3_l3_3_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C4E80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A633400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C3321 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C342F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C1800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06604000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C630044 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10630000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06630000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C00AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190F800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00028002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x000087FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00020002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00008FFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00008002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000A7FF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_3__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_3__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_3__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_3__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_3__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_3__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_3__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_3__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_3__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_3__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_3__l30_bank3_stalled__read; + counter->name = "Slice0 L3 Bank3 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank3 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_3__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_3__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_3__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_3__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_3__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt3__l3_3__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_3__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_3__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_3__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_3__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_3__l30_bank3_active__read; + counter->name = "Slice0 L3 Bank3 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank3 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 140; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_3__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_3__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_3__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_3__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_3__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_3__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_3__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__l3_3__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_3__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_3__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_3__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_3__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_3__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_3__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_3__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__l3_3__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt3_rasterizer_and_pixel_backend_mux_regs[31]; +static struct brw_perf_query_register_prog sklgt3_rasterizer_and_pixel_backend_b_counter_regs[10]; +static struct brw_perf_query_register_prog sklgt3_rasterizer_and_pixel_backend_flex_regs[7]; + +static struct brw_perf_query_counter sklgt3_rasterizer_and_pixel_backend_query_counters[40]; +static struct brw_perf_query_info sklgt3_rasterizer_and_pixel_backend_query = { + .kind = OA_COUNTERS, + .name = "Metric set RasterizerAndPixelBackend", + .guid = "76935d7b-09c9-46bf-87f1-c18b4a86ebe5", + .counters = sklgt3_rasterizer_and_pixel_backend_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt3_rasterizer_and_pixel_backend_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt3_rasterizer_and_pixel_backend_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt3_rasterizer_and_pixel_backend_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt3_register_rasterizer_and_pixel_backend_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt3_rasterizer_and_pixel_backend_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102F3800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x144D0500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x120D03C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x140D03CF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0004 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F0480 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0090 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064D0027 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004D0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D0D40 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020D803F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040D8023 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100D0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020F0010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0050 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41901400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43901485 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000EFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00006000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F3FF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__rasterizer_and_pixel_backend__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__rasterizer_and_pixel_backend__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__rasterizer_and_pixel_backend__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__rasterizer_and_pixel_backend__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__rasterizer_and_pixel_backend__pixel_values0_ready__read; + counter->name = "Slice0 Pixel Values Ready"; + counter->desc = "The percentage of time in which slice0 pixel values are ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt3__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__rasterizer_and_pixel_backend__rasterizer0_input_available__read; + counter->name = "Slice0 Rasterizer Input Available"; + counter->desc = "The percentage of time in which slice0 rasterizer input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 128; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__rasterizer_and_pixel_backend__pixel_data0_ready__read; + counter->name = "Slice0 Post-EarlyZ Pixel Data Ready"; + counter->desc = "The percentage of time in which slice0 post-EarlyZ pixel data is ready (after early Z tests have been applied)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 132; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__rasterizer_and_pixel_backend__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__rasterizer_and_pixel_backend__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__rasterizer_and_pixel_backend__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__rasterizer_and_pixel_backend__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__rasterizer_and_pixel_backend__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__rasterizer_and_pixel_backend__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__rasterizer_and_pixel_backend__rasterizer0_output_ready__read; + counter->name = "Slice0 Rasterizer Output Ready"; + counter->desc = "The percentage of time in which slice0 rasterizer output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 196; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__rasterizer_and_pixel_backend__ps_output0_available__read; + counter->name = "Slice0 PS Output Available"; + counter->desc = "The percentage of time in which slice0 PS output is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 256; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__rasterizer_and_pixel_backend__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt3_sampler_mux_regs[69]; +static struct brw_perf_query_register_prog sklgt3_sampler_b_counter_regs[12]; +static struct brw_perf_query_register_prog sklgt3_sampler_flex_regs[7]; + +static struct brw_perf_query_counter sklgt3_sampler_query_counters[41]; +static struct brw_perf_query_info sklgt3_sampler_query = { + .kind = OA_COUNTERS, + .name = "Metric set Sampler", + .guid = "1b34c0d6-4f4c-4d7b-833f-4aaf236d87a6", + .counters = sklgt3_sampler_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt3_sampler_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt3_sampler_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt3_sampler_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt3_register_sampler_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt3_sampler_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14152C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16150005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121600A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14352C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16350005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123600A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14552C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16550005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125600A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062F6000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0050 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0350 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FB000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F00DA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C0028 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C138000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E132000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0413C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C140018 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C157000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E150078 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10150000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04162180 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02160000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04174000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0233A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04333000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14348000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16348000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02357870 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10350000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04360043 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02360000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04371000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E538000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00538000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06533000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C540020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12548000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E557000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00557800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10550000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06560043 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02560000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06571000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FF80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900060 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900060 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x70800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0000C000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000E7FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00003000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F9FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000C00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE7F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__sampler__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__sampler__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__sampler__sampler02_input_available__read; + counter->name = "Slice0 Subslice2 Input Available"; + counter->desc = "The percentage of time in which slice0 subslice2 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__sampler__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__sampler__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__sampler__sampler00_input_available__read; + counter->name = "Slice0 Subslice0 Input Available"; + counter->desc = "The percentage of time in which slice0 subslice0 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__sampler__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 28; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__sampler__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__sampler__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__sampler__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__sampler__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__sampler__sampler02_output_ready__read; + counter->name = "Slice0 Subslice2 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice0 subslice2 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__sampler__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__sampler__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__sampler__sampler01_input_available__read; + counter->name = "Slice0 Subslice1 Input Available"; + counter->desc = "The percentage of time in which slice0 subslice1 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 88; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__sampler__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__sampler__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__sampler__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__sampler__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt3__sampler__avg_gpu_core_frequency__max(brw); + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__sampler__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__sampler__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__sampler__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__sampler__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__sampler__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__sampler__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__sampler__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 164; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__sampler__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__sampler__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__sampler__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__sampler__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__sampler__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__sampler__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__sampler__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__sampler__sampler00_output_ready__read; + counter->name = "Slice0 Subslice0 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice0 subslice0 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 224; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__sampler__sampler01_output_ready__read; + counter->name = "Slice0 Subslice1 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice0 subslice1 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 228; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__sampler__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__sampler__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__sampler__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__sampler__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__sampler__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__sampler__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt3_tdl_1_mux_regs[68]; +static struct brw_perf_query_register_prog sklgt3_tdl_1_b_counter_regs[18]; +static struct brw_perf_query_register_prog sklgt3_tdl_1_flex_regs[7]; + +static struct brw_perf_query_counter sklgt3_tdl_1_query_counters[41]; +static struct brw_perf_query_info sklgt3_tdl_1_query = { + .kind = OA_COUNTERS, + .name = "Metric set TDL_1", + .guid = "b375c985-9953-455b-bda2-b03f7594e9db", + .counters = sklgt3_tdl_1_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt3_tdl_1_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt3_tdl_1_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt3_tdl_1_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt3_register_tdl_1_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt3_tdl_1_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12120000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12320000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12520000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F3000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F03A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FF000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0095 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02108000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0410C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02118000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0411C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02121880 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041219B5 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02134000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04135000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C308000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E304000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06304000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C318000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E314000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06314000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C321A80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E320033 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06320031 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00320000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C334000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E331000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06331000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E508000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00508000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02504000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E518000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00518000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02514000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E521880 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00521A80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02520033 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E534000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00534000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02531000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FF80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900062 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00009FFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000EFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FDFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE7F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_1__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__tdl_1__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__tdl_1__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__tdl_1__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__tdl_1__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_1__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_1__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__tdl_1__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_1__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_1__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__tdl_1__non_ps_thread02_ready_for_dispatch__read; + counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice2"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_1__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_1__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_1__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_1__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_1__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt3__tdl_1__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_1__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__tdl_1__non_ps_thread00_ready_for_dispatch__read; + counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice0"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 120; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_1__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_1__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__tdl_1__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__tdl_1__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__tdl_1__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__tdl_1__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__tdl_1__ps_thread00_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice0"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_1__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__tdl_1__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_1__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_1__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__tdl_1__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_1__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_1__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__tdl_1__ps_thread01_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice1"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 224; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_1__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_1__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__tdl_1__ps_thread02_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice2"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 248; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_1__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_1__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_1__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_1__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__tdl_1__non_ps_thread01_ready_for_dispatch__read; + counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice1"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 288; + counter->size = sizeof(float); + } + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt3_tdl_2_mux_regs[42]; +static struct brw_perf_query_register_prog sklgt3_tdl_2_b_counter_regs[6]; +static struct brw_perf_query_register_prog sklgt3_tdl_2_flex_regs[7]; + +static struct brw_perf_query_counter sklgt3_tdl_2_query_counters[41]; +static struct brw_perf_query_info sklgt3_tdl_2_query = { + .kind = OA_COUNTERS, + .name = "Metric set TDL_2", + .guid = "3e2be2bb-884a-49bb-82c5-2358e6bd5f2d", + .counters = sklgt3_tdl_2_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt3_tdl_2_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt3_tdl_2_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt3_tdl_2_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt3_register_tdl_2_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt3_tdl_2_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12124D60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12322E60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12524D60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F3000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0014 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FE000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0097 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0410C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0411C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04121FB7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04135000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00308000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06304000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00318000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06314000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00321B80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0632003F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00334000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06331000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0250C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0251C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02521FB7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00520000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02535000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_2__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__tdl_2__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__tdl_2__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__tdl_2__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__tdl_2__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_2__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_2__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__tdl_2__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_2__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_2__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_2__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_2__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_2__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__tdl_2__thread_header01_ready_port0__read; + counter->name = "Thread Header Ready on Slice0 Subslice1 Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 88; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__tdl_2__thread_header01_ready_port1__read; + counter->name = "Thread Header Ready on Slice0 Subslice1 Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 92; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_2__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_2__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt3__tdl_2__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_2__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_2__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_2__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__tdl_2__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__tdl_2__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 140; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__tdl_2__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__tdl_2__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__tdl_2__thread_header02_ready_port1__read; + counter->name = "Thread Header Ready on Slice0 Subslice2 Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__tdl_2__thread_header02_ready_port0__read; + counter->name = "Thread Header Ready on Slice0 Subslice2 Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_2__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__tdl_2__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_2__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_2__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__tdl_2__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_2__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_2__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_2__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_2__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_2__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_2__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_2__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__tdl_2__thread_header00_ready_port0__read; + counter->name = "Thread Header Ready on Slice0 Subslice0 Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 256; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__tdl_2__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__tdl_2__thread_header00_ready_port1__read; + counter->name = "Thread Header Ready on Slice0 Subslice0 Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 272; + counter->size = sizeof(float); + } + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt3_compute_extra_mux_regs[69]; + +static struct brw_perf_query_counter sklgt3_compute_extra_query_counters[5]; +static struct brw_perf_query_info sklgt3_compute_extra_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics Extra Gen9", + .guid = "2d80a648-7b5a-4e92-bbe7-3b5c76f2e221", + .counters = sklgt3_compute_extra_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt3_compute_extra_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt3_register_compute_extra_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt3_compute_extra_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121203E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123203E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125203E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x129203E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12B203E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12D203E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024EC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044EC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064EC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0042 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F006D }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06104000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06114000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06120033 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06131000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04308000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04318000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04321980 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00320000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04334000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04504000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04514000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04520033 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00520000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04531000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00AF8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ACC0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x008D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x028DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C8FB000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E8F0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06AC8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02AD4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02918000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02921980 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00920000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02934000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B04000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B14000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B20033 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B20000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B31000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D08000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D18000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D21980 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D34000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900402 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53901550 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_extra__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_extra__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_extra__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__compute_extra__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt3__compute_extra__avg_gpu_core_frequency__max(brw); + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__compute_extra__fpu1_active_adjusted__read; + counter->name = "EU FPU1 Pipe Active including Ext Math"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing including Extended Math processing"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt3_vme_pipe_mux_regs[73]; +static struct brw_perf_query_register_prog sklgt3_vme_pipe_b_counter_regs[17]; +static struct brw_perf_query_register_prog sklgt3_vme_pipe_flex_regs[2]; + +static struct brw_perf_query_counter sklgt3_vme_pipe_query_counters[10]; +static struct brw_perf_query_info sklgt3_vme_pipe_query = { + .kind = OA_COUNTERS, + .name = "Media Vme Pipe Gen9", + .guid = "cfae9232-6ffc-42cc-a703-9790016925f0", + .counters = sklgt3_vme_pipe_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt3_vme_pipe_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt3_vme_pipe_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt3_vme_pipe_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt3_register_vme_pipe_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt3_vme_pipe_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141A5800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161A00C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12180240 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14180002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x149A5800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x169A00C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12980240 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14980002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E3FC0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F3000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C9500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CAA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C000A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04193000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081A28C1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00133000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0613C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0813F000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00172000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06178000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0817A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00180037 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06180940 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08180000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02180000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04183000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04AFC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06AF3000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ACC4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CCC0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E8F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x108F0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16ACA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18AC000A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06993000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9A28C1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x009A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A93F000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C93F000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A97A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C97A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A980977 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08980000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04980000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06983000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x119000FF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900050 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900115 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900884 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100030 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF9 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FFFC }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FFF3 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100180 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFCF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FF3F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00008003 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__vme_pipe__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__vme_pipe__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__vme_pipe__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__vme_pipe__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__vme_pipe__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt3__vme_pipe__avg_gpu_core_frequency__max(brw); + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__vme_pipe__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__vme_pipe__eu_thread_occupancy__read; + counter->name = "EU Thread Occupancy"; + counter->desc = "The percentage of time in which hardware threads occupied EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__vme_pipe__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 44; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__vme_pipe__vme_busy__read; + counter->name = "VME Busy"; + counter->desc = "The percentage of time in which VME (IME or CRE) was actively processing data."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__vme_pipe__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 52; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt3_gpu_busyness_mux_regs[43]; +static struct brw_perf_query_register_prog sklgt3_gpu_busyness_b_counter_regs[7]; + +static struct brw_perf_query_counter sklgt3_gpu_busyness_query_counters[9]; +static struct brw_perf_query_info sklgt3_gpu_busyness_query = { + .kind = OA_COUNTERS, + .name = "Gpu Rings Busyness", + .guid = "0c5058ff-fdf4-4e0d-81fb-c0310fb76525", + .counters = sklgt3_gpu_busyness_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt3_gpu_busyness_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt3_gpu_busyness_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt3_register_gpu_busyness_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt3_gpu_busyness_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21D05800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13805800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05962C25 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19950016 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21C05800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09D000A5 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11D00000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05D00000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09D54000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07800035 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21960000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0996C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B964000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930068 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15948000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B94000C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03957500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17950000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07928000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03988000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09978000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0BC000A5 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11C00000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05C00000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0BC54000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900463 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007C000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x000007FF }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__gpu_busyness__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__gpu_busyness__vebox_busy__read; + counter->name = "Vebox Ring Busy"; + counter->desc = "The percentage of time when vebox command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__gpu_busyness__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__gpu_busyness__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt3__gpu_busyness__avg_gpu_core_frequency__max(brw); + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__gpu_busyness__render_busy__read; + counter->name = "Render Ring Busy"; + counter->desc = "The percentage of time when render command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__gpu_busyness__vdbox0_busy__read; + counter->name = "Vdbox0 Ring Busy"; + counter->desc = "The percentage of time when Vdbox0 command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 36; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__gpu_busyness__blitter_busy__read; + counter->name = "Blitter Ring Busy"; + counter->desc = "The percentage of time when blitter command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__gpu_busyness__any_ring_busy__read; + counter->name = "AnyRingBusy"; + counter->desc = "The percentage of time when any command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 44; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt3__gpu_busyness__vdbox1_busy__read; + counter->name = "Vdbox1 Ring Busy"; + counter->desc = "The percentage of time when Vdbox1 command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt3_test_oa_mux_regs[13]; +static struct brw_perf_query_register_prog sklgt3_test_oa_b_counter_regs[22]; + +static struct brw_perf_query_counter sklgt3_test_oa_query_counters[12]; +static struct brw_perf_query_info sklgt3_test_oa_query = { + .kind = OA_COUNTERS, + .name = "MDAPI testing set Gen9", + .guid = "2b985803-d3c9-4629-8a4f-634bfecba0e8", + .counters = sklgt3_test_oa_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt3_test_oa_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt3_test_oa_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt3_register_test_oa_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt3_test_oa_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07810013 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000004 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000003 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000007 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFF7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00100082 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFEF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x001000C2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FFE7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00100001 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FFE7 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__test_oa__counter7__read; + counter->name = "TestCounter7"; + counter->desc = "HW test counter 7. Factor: 0.666"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__test_oa__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 8; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__test_oa__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__test_oa__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt3__test_oa__avg_gpu_core_frequency__max(brw); + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__test_oa__counter8__read; + counter->name = "TestCounter8"; + counter->desc = "HW test counter 8. Should be equal to 1."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__test_oa__counter4__read; + counter->name = "TestCounter4"; + counter->desc = "HW test counter 4. Factor: 0.333"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__test_oa__counter5__read; + counter->name = "TestCounter5"; + counter->desc = "HW test counter 5. Factor: 0.333"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__test_oa__counter6__read; + counter->name = "TestCounter6"; + counter->desc = "HW test counter 6. Factor: 0.166"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__test_oa__counter3__read; + counter->name = "TestCounter3"; + counter->desc = "HW test counter 3. Factor: 0.5"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__test_oa__counter0__read; + counter->name = "TestCounter0"; + counter->desc = "HW test counter 0. Factor: 0.0"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__test_oa__counter1__read; + counter->name = "TestCounter1"; + counter->desc = "HW test counter 1. Factor: 1.0"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt3__test_oa__counter2__read; + counter->name = "TestCounter2"; + counter->desc = "HW test counter 2. Factor: 1.0"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +void +brw_oa_register_queries_sklgt3(struct brw_context *brw) +{ + sklgt3_register_render_basic_counter_query(brw); + sklgt3_register_compute_basic_counter_query(brw); + sklgt3_register_render_pipe_profile_counter_query(brw); + sklgt3_register_memory_reads_counter_query(brw); + sklgt3_register_memory_writes_counter_query(brw); + sklgt3_register_compute_extended_counter_query(brw); + sklgt3_register_compute_l3_cache_counter_query(brw); + sklgt3_register_hdc_and_sf_counter_query(brw); + sklgt3_register_l3_1_counter_query(brw); + sklgt3_register_l3_2_counter_query(brw); + sklgt3_register_l3_3_counter_query(brw); + sklgt3_register_rasterizer_and_pixel_backend_counter_query(brw); + sklgt3_register_sampler_counter_query(brw); + sklgt3_register_tdl_1_counter_query(brw); + sklgt3_register_tdl_2_counter_query(brw); + sklgt3_register_compute_extra_counter_query(brw); + sklgt3_register_vme_pipe_counter_query(brw); + sklgt3_register_gpu_busyness_counter_query(brw); + sklgt3_register_test_oa_counter_query(brw); +} + +static struct brw_perf_query_register_prog sklgt4_render_basic_mux_regs[94]; +static struct brw_perf_query_register_prog sklgt4_render_basic_b_counter_regs[5]; +static struct brw_perf_query_register_prog sklgt4_render_basic_flex_regs[7]; + +static struct brw_perf_query_counter sklgt4_render_basic_query_counters[51]; +static struct brw_perf_query_info sklgt4_render_basic_query = { + .kind = OA_COUNTERS, + .name = "Render Metrics Basic Gen9", + .guid = "bad77c24-cc64-480d-99bf-e7b740713800", + .counters = sklgt4_render_basic_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt4_render_basic_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt4_render_basic_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt4_render_basic_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt4_register_render_basic_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt4_render_basic_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C01E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12170280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12370280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16EC01E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x176C01E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11930317 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x159303DF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E03B0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A6C0053 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4CA400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5600 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CAA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00133000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08133000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00170020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08170021 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10170000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0633C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06370800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10370000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ACE0230 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AEC5300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10EC0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CEC0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A9B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C9C0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ACC2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CCC0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x088D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A8D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E8F1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x108F0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16AC8800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B4E0020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x096C5300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x116C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x091B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B1C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B4C2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x090D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F0F1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x172C0800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D933031 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F933E3F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01933D00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0393073C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0593000E }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900157 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900158 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190003F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x5190FF30 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900060 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55903033 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45901421 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900803 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x5790FFF1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x5990000F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x5390FFFF }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_basic__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__render_basic__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_basic__l3_misses__read; + counter->name = "L3 Misses"; + counter->desc = "The total number of L3 misses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_basic__gti_l3_throughput__read; + counter->name = "GTI L3 Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__render_basic__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_basic__sampler_l1_misses__read; + counter->name = "Sampler Cache Misses"; + counter->desc = "The total number of sampler cache misses in all LODs in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__render_basic__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__render_basic__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 52; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_basic__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_basic__l3_sampler_throughput__read; + counter->name = "L3 Sampler Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_basic__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__render_basic__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 80; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_basic__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_basic__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x09) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__render_basic__sampler0_busy__read; + counter->name = "Sampler 0 Busy"; + counter->desc = "The percentage of time in which Sampler 0 has been processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 104; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x12) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__render_basic__sampler1_busy__read; + counter->name = "Sampler 1 Busy"; + counter->desc = "The percentage of time in which Sampler 1 has been processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 108; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__render_basic__samplers_busy__read; + counter->name = "Samplers Busy"; + counter->desc = "The percentage of time in which samplers have been processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 112; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_basic__gti_vf_throughput__read; + counter->name = "GTI Fixed Pipe Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between 3D Pipeline (Command Dispatch, Input Assembly and Stream Output) and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_basic__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x09) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__render_basic__sampler0_bottleneck__read; + counter->name = "Sampler 0 Bottleneck"; + counter->desc = "The percentage of time in which Sampler 0 has been slowing down the pipe when processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_basic__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_basic__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_basic__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_basic__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt4__render_basic__avg_gpu_core_frequency__max(brw); + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_basic__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_basic__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_basic__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_basic__l3_lookups__read; + counter->name = "L3 Lookup Accesses w/o IC"; + counter->desc = "The total number of L3 cache lookup accesses w/o IC."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_basic__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_basic__gti_read_throughput__read; + counter->name = "GTI Read Throughput"; + counter->desc = "The total number of GPU memory bytes read from GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__render_basic__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 224; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__render_basic__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 228; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_basic__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__render_basic__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 240; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_basic__gti_depth_throughput__read; + counter->name = "GTI Depth Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between depth caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__render_basic__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 256; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__render_basic__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 260; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_basic__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_basic__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__render_basic__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 280; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_basic__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_basic__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__render_basic__sampler_bottleneck__read; + counter->name = "Samplers Bottleneck"; + counter->desc = "The percentage of time in which samplers have been slowing down the pipe when processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 304; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_basic__gti_hdc_lookups_throughput__read; + counter->name = "GTI HDC TLB Lookup Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between GTI and HDC, when HDC is doing TLB lookups."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_basic__gti_rcc_throughput__read; + counter->name = "GTI RCC Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between render color caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_basic__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 328; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_basic__gti_write_throughput__read; + counter->name = "GTI Write Throughput"; + counter->desc = "The total number of GPU memory bytes written to GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 336; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_basic__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 344; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_basic__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 352; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_basic__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 360; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_basic__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 368; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt4_compute_basic_mux_regs[78]; +static struct brw_perf_query_register_prog sklgt4_compute_basic_b_counter_regs[5]; +static struct brw_perf_query_register_prog sklgt4_compute_basic_flex_regs[7]; + +static struct brw_perf_query_counter sklgt4_compute_basic_query_counters[39]; +static struct brw_perf_query_info sklgt4_compute_basic_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics Basic Gen9", + .guid = "7277228f-e7f3-4743-945a-6a2049d11377", + .counters = sklgt4_compute_basic_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt4_compute_basic_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt4_compute_basic_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt4_compute_basic_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt4_register_compute_basic_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt4_compute_basic_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F00E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124F1C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C00E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E0820 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F0900 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084F0032 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4F1891 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4F0E00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4F003C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004F0D80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024F003B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C0100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C6C000C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C0B00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0024 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C6000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C5C001B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0208 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CFB00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00BE }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19900157 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B900158 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900105 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900103 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900FFF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900821 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900802 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900802 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900422 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53905555 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_basic__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_basic__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_basic__untyped_bytes_read__read; + counter->name = "Untyped Bytes Read"; + counter->desc = "The total number of typed memory bytes read via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_basic__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_basic__typed_bytes_written__read; + counter->name = "Typed Bytes Written"; + counter->desc = "The total number of untyped memory bytes written via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_basic__fpu0_active__read; + counter->name = "EU FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_basic__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 44; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_basic__eu_avg_ipc_rate__read; + counter->name = "EU AVG IPC Rate"; + counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 2.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_basic__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_basic__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_basic__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_basic__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_basic__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_basic__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_basic__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_basic__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_basic__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt4__compute_basic__avg_gpu_core_frequency__max(brw); + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_basic__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_basic__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_basic__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_basic__gti_read_throughput__read; + counter->name = "GTI Read Throughput"; + counter->desc = "The total number of GPU memory bytes read from GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_basic__untyped_bytes_written__read; + counter->name = "Untyped Writes"; + counter->desc = "The total number of untyped memory bytes written via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_basic__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_basic__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_basic__typed_bytes_read__read; + counter->name = "Typed Bytes Read"; + counter->desc = "The total number of typed memory bytes read via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_basic__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_basic__eu_thread_occupancy__read; + counter->name = "EU Thread Occupancy"; + counter->desc = "The percentage of time in which hardware threads occupied EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_basic__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 204; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_basic__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_basic__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_basic__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_basic__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_basic__gti_write_throughput__read; + counter->name = "GTI Write Throughput"; + counter->desc = "The total number of GPU memory bytes written to GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_basic__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_basic__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_basic__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_basic__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_basic__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_basic__eu_send_active__read; + counter->name = "EU Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 288; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt4_render_pipe_profile_mux_regs[114]; +static struct brw_perf_query_register_prog sklgt4_render_pipe_profile_b_counter_regs[21]; +static struct brw_perf_query_register_prog sklgt4_render_pipe_profile_flex_regs[7]; + +static struct brw_perf_query_counter sklgt4_render_pipe_profile_query_counters[43]; +static struct brw_perf_query_info sklgt4_render_pipe_profile_query = { + .kind = OA_COUNTERS, + .name = "Render Metrics for 3D Pipeline Profile Gen9", + .guid = "463c668c-3f60-49b6-8f85-d995b635b3b2", + .counters = sklgt4_render_pipe_profile_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt4_render_pipe_profile_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt4_render_pipe_profile_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt4_render_pipe_profile_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt4_register_render_pipe_profile_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt4_render_pipe_profile_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0E001F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10116800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178A03E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11824C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11830020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13840020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11850019 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11860007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01870C40 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17880000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020E5400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000E0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080F0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06104000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06110012 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06131000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01898000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D890100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03898000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A0075 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8A4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x138A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D81A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15818000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17818000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B820030 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07828000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D824000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F828000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05824000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D830003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0583000C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09830000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03838000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07838000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B840980 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03844D80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11840000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09850080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03850003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01850000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07860000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F860400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09870032 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01888052 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11880000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09884000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B931001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D930001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19934000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B958000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950094 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19958000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09E58000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0BE58000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E5C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0592C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B928000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D924000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F924000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11928000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1392C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09924000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01985000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07988000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09981000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B982000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D982000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F989000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05982000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190C080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51901110 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900440 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55901111 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C21 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57901411 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900042 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900024 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900841 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900411 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFEA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFC }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007AFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F5FD }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00079FFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000F3FB }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007BF7A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F7E7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FEFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000F7CF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00077FFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000EFDF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0006FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000CFBF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0003FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x00005F7F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__render_pipe_profile__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__render_pipe_profile__vs_bottleneck__read; + counter->name = "VS Bottleneck"; + counter->desc = "The percentage of time in which vertex shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__render_pipe_profile__hi_depth_bottleneck__read; + counter->name = "Hi-Depth Bottleneck"; + counter->desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__render_pipe_profile__gs_bottleneck__read; + counter->name = "GS Bottleneck"; + counter->desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__render_pipe_profile__bc_bottleneck__read; + counter->name = "BC Bottleneck"; + counter->desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__render_pipe_profile__hs_stall__read; + counter->name = "HS Stall"; + counter->desc = "The percentage of time in which hull stall pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 60; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt4__render_pipe_profile__avg_gpu_core_frequency__max(brw); + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__render_pipe_profile__vf_bottleneck__read; + counter->name = "VF Bottleneck"; + counter->desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__render_pipe_profile__sf_bottleneck__read; + counter->name = "Strip-Fans Bottleneck"; + counter->desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__render_pipe_profile__sf_stall__read; + counter->name = "SF Stall"; + counter->desc = "The percentage of time in which strip-fans pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 140; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__render_pipe_profile__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__render_pipe_profile__hs_bottleneck__read; + counter->name = "HS Bottleneck"; + counter->desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__render_pipe_profile__cl_stall__read; + counter->name = "CL Stall"; + counter->desc = "The percentage of time in which clipper pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__render_pipe_profile__so_bottleneck__read; + counter->name = "SO Bottleneck"; + counter->desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__render_pipe_profile__ds_bottleneck__read; + counter->name = "DS Bottleneck"; + counter->desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__render_pipe_profile__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 188; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__render_pipe_profile__cl_bottleneck__read; + counter->name = "Clipper Bottleneck"; + counter->desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__render_pipe_profile__ds_stall__read; + counter->name = "DS Stall"; + counter->desc = "The percentage of time in which domain shader pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 196; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__render_pipe_profile__early_depth_bottleneck__read; + counter->name = "Early Depth Bottleneck"; + counter->desc = "The percentage of time in which early depth test pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__render_pipe_profile__so_stall__read; + counter->name = "SO Stall"; + counter->desc = "The percentage of time in which stream-output pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__render_pipe_profile__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt4_memory_reads_mux_regs[47]; +static struct brw_perf_query_register_prog sklgt4_memory_reads_b_counter_regs[32]; +static struct brw_perf_query_register_prog sklgt4_memory_reads_flex_regs[7]; + +static struct brw_perf_query_counter sklgt4_memory_reads_query_counters[41]; +static struct brw_perf_query_info sklgt4_memory_reads_query = { + .kind = OA_COUNTERS, + .name = "Memory Reads Distribution Gen9", + .guid = "3ae6e74c-72c3-4040-9bd0-7961430b8cc8", + .counters = sklgt4_memory_reads_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt4_memory_reads_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt4_memory_reads_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt4_memory_reads_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt4_register_memory_reads_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt4_memory_reads_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1381001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900064 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03811300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05811B12 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0781001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E58000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05E5C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900150 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21900151 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23900152 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25900153 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27900154 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B900156 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D900157 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F90015F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900105 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900103 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900101 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C63 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900C63 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000272C, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002728, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000271C, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002718, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F872 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_reads__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__memory_reads__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_reads__gti_l3_bank0_reads__read; + counter->name = "GtiL3Bank0Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 0 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_reads__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_reads__gti_ring_accesses__read; + counter->name = "GtiRingAccesses"; + counter->desc = "The total number of all accesses from GTI to the ring."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_reads__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_reads__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_reads__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_reads__gti_l3_bank3_reads__read; + counter->name = "GtiL3Bank3Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 3 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_reads__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_reads__gti_rs_memory_reads__read; + counter->name = "GtiRsMemoryReads"; + counter->desc = "The total number of GTI memory reads from Resource Streamer."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_reads__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_reads__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_reads__gti_hiz_memory_reads__read; + counter->name = "GtiHizMemoryReads"; + counter->desc = "The total number of GTI memory reads from Hierarchical Depth Cache (Hi-Depth Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_reads__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_reads__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt4__memory_reads__avg_gpu_core_frequency__max(brw); + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_reads__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_reads__gti_rcc_memory_reads__read; + counter->name = "GtiRccMemoryReads"; + counter->desc = "The total number of GTI memory reads from Render Color Cache (Render Color Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_reads__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_reads__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_reads__gti_l3_bank1_reads__read; + counter->name = "GtiL3Bank1Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 1 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__memory_reads__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_reads__gti_cmd_streamer_memory_reads__read; + counter->name = "GtiCmdStreamerMemoryReads"; + counter->desc = "The total number of GTI memory reads from Command Streamer."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_reads__gti_l3_bank2_reads__read; + counter->name = "GtiL3Bank2Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 2 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_reads__gti_memory_reads__read; + counter->name = "GtiMemoryReads"; + counter->desc = "The total number of GTI memory reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_reads__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_reads__gti_rcz_memory_reads__read; + counter->name = "GtiRczMemoryReads"; + counter->desc = "The total number of GTI memory reads from Render Depth Cache (Render Depth Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_reads__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_reads__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__memory_reads__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 232; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_reads__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_reads__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_reads__gti_msc_memory_reads__read; + counter->name = "GtiMscMemoryReads"; + counter->desc = "The total number of GTI memory reads from Multisampling Color Cache (Multisampling Color Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_reads__gti_vf_memory_reads__read; + counter->name = "GtiVfMemoryReads"; + counter->desc = "The total number of GTI memory reads from Vertex Fetch."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_reads__gti_stc_memory_reads__read; + counter->name = "GtiStcMemoryReads"; + counter->desc = "The total number of GTI memory reads from Stencil Cache (Stencil Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_reads__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_reads__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_reads__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_reads__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_reads__gti_l3_reads__read; + counter->name = "GtiL3Reads"; + counter->desc = "The total number of GTI memory reads from L3 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_reads__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt4_memory_writes_mux_regs[47]; +static struct brw_perf_query_register_prog sklgt4_memory_writes_b_counter_regs[32]; +static struct brw_perf_query_register_prog sklgt4_memory_writes_flex_regs[7]; + +static struct brw_perf_query_counter sklgt4_memory_writes_query_counters[41]; +static struct brw_perf_query_info sklgt4_memory_writes_query = { + .kind = OA_COUNTERS, + .name = "Memory Writes Distribution Gen9", + .guid = "055f256d-4052-467c-8dec-6064a4806433", + .counters = sklgt4_memory_writes_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt4_memory_writes_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt4_memory_writes_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt4_memory_writes_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt4_register_memory_writes_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt4_memory_writes_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1381001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F901000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03811300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05811B12 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0781001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E58000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05E5C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900160 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21900161 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23900162 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25900163 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27900164 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900165 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B900166 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D900167 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F900150 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900105 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900103 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900101 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C63 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900C63 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000272C, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002728, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000271C, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002718, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F822 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_writes__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__memory_writes__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_writes__gti_memory_writes__read; + counter->name = "GtiMemoryWrites"; + counter->desc = "The total number of GTI memory writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_writes__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_writes__gti_ring_accesses__read; + counter->name = "GtiRingAccesses"; + counter->desc = "The total number of all GTI accesses to the ring."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_writes__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_writes__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_writes__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_writes__gti_msc_memory_writes__read; + counter->name = "GtiMscMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Multisampling Color Cache (Multisampling Color Cache invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_writes__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_writes__gti_cmd_streamer_memory_writes__read; + counter->name = "GtiCmdStreamerMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Command Streamer."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_writes__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_writes__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_writes__gti_l3_bank0_writes__read; + counter->name = "GtiL3Bank0Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 0 (L3 Bank 0 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_writes__gti_l3_bank1_writes__read; + counter->name = "GtiL3Bank1Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 1 (L3 Bank 1 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_writes__gti_l3_bank2_writes__read; + counter->name = "GtiL3Bank2Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 2 (L3 Bank 2 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_writes__gti_l3_bank3_writes__read; + counter->name = "GtiL3Bank3Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 3 (L3 Bank 3 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_writes__gti_l3_writes__read; + counter->name = "GtiL3Writes"; + counter->desc = "The total number of GTI memory writes from L3 (L3 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_writes__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_writes__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt4__memory_writes__avg_gpu_core_frequency__max(brw); + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_writes__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_writes__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_writes__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_writes__gti_rcc_memory_writes__read; + counter->name = "GtiRccMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Render Color Cache (Render Color Cache invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_writes__gti_so_memory_writes__read; + counter->name = "GtiSoMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Stream Output."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__memory_writes__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_writes__gti_stc_memory_writes__read; + counter->name = "GtiStcMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Stencil Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_writes__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_writes__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_writes__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__memory_writes__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 240; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_writes__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_writes__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_writes__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_writes__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_writes__gti_rcz_memory_writes__read; + counter->name = "GtiRczMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Render Depth Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_writes__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_writes__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_writes__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_writes__gti_hiz_memory_writes__read; + counter->name = "GtiHizMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Hierarchical Depth Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__memory_writes__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt4_compute_extended_mux_regs[72]; +static struct brw_perf_query_register_prog sklgt4_compute_extended_b_counter_regs[21]; +static struct brw_perf_query_register_prog sklgt4_compute_extended_flex_regs[7]; + +static struct brw_perf_query_counter sklgt4_compute_extended_query_counters[38]; +static struct brw_perf_query_info sklgt4_compute_extended_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics Extended Gen9", + .guid = "753972d4-87cd-4460-824d-754463ac5054", + .counters = sklgt4_compute_extended_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt4_compute_extended_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt4_compute_extended_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt4_compute_extended_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt4_register_compute_extended_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt4_compute_extended_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C00E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8160 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C0120 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x184E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4EAAA0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C0B01 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C000C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001C0041 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061C4200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081C4443 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1C4645 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1C7647 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041C7357 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0030 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4CAA2A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C02AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5515 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CAA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11907FFF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900802 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FC2A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FC6A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007FC92 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007FCA2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FC32 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FC9A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007FE6A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007FE7A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000BF00 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_extended__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_extended__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_extended__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_extended__fpu0_active__read; + counter->name = "EU FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_extended__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_extended__eu_avg_ipc_rate__read; + counter->name = "EU AVG IPC Rate"; + counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 2.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_extended__typed_writes0__read; + counter->name = "Typed Writes 0"; + counter->desc = "The subslice 0 typed writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_extended__eu_typed_atomics0__read; + counter->name = "EuTypedAtomics0"; + counter->desc = "The subslice 0 EU Typed Atomics subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_extended__typed_atomics0__read; + counter->name = "Typed Atomics 0"; + counter->desc = "The subslice 0 typed atomics."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_extended__typed_atomics_per_cache_line__read; + counter->name = "TypedAtomicsPerCacheLine"; + counter->desc = "The ratio of EU typed atomics requests to L3 cache line writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_extended__eu_untyped_reads0__read; + counter->name = "EuUntypedReads0"; + counter->desc = "The subslice 0 EU Untyped Reads subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_extended__untyped_writes0__read; + counter->name = "Untyped Writes 0"; + counter->desc = "The subslice 0 untyped writes (including SLM writes)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_extended__eu_untyped_atomics0__read; + counter->name = "EuUntypedAtomics0"; + counter->desc = "The subslice 0 EU Untyped Atomics subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_extended__eu_untyped_writes0__read; + counter->name = "EuUntypedWrites0"; + counter->desc = "The subslice 0 EU Untyped Writes subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_extended__eu_a64_untyped_writes0__read; + counter->name = "EuA64UntypedWrites0"; + counter->desc = "The subslice 0 EU A64 Untyped Writes subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_extended__untyped_writes_per_cache_line__read; + counter->name = "UntypedWritesPerCacheLine"; + counter->desc = "The ratio of EU untyped write requests to L3 cache line writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_extended__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_extended__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_extended__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_extended__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt4__compute_extended__avg_gpu_core_frequency__max(brw); + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_extended__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_extended__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_extended__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_extended__eu_typed_writes0__read; + counter->name = "EuTypedWrites0"; + counter->desc = "The subslice 0 EU Typed Writes subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_extended__typed_writes_per_cache_line__read; + counter->name = "TypedWritesPerCacheLine"; + counter->desc = "The ratio of EU typed write requests to L3 cache line writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_extended__typed_reads0__read; + counter->name = "Typed Reads 0"; + counter->desc = "The subslice 0 typed reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_extended__untyped_reads0__read; + counter->name = "Untyped Reads 0"; + counter->desc = "The subslice 0 untyped reads (including SLM reads)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_extended__eu_a64_untyped_reads0__read; + counter->name = "EuA64UntypedReads0"; + counter->desc = "The subslice 0 EU A64 Untyped Reads subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_extended__eu_thread_occupancy__read; + counter->name = "EU Thread Occupancy"; + counter->desc = "The percentage of time in which hardware threads occupied EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 208; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_extended__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 212; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_extended__eu_typed_reads0__read; + counter->name = "EuTypedReads0"; + counter->desc = "The subslice 0 EU Typed Reads subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_extended__untyped_reads_per_cache_line__read; + counter->name = "UntypedReadsPerCacheLine"; + counter->desc = "The ratio of EU untyped read requests to L3 cache line reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_extended__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_extended__typed_reads_per_cache_line__read; + counter->name = "TypedReadsPerCacheLine"; + counter->desc = "The ratio of EU typed read requests to L3 cache line reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_extended__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_extended__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_extended__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_extended__eu_send_active__read; + counter->name = "EU Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 272; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt4_compute_l3_cache_mux_regs[60]; +static struct brw_perf_query_register_prog sklgt4_compute_l3_cache_b_counter_regs[13]; +static struct brw_perf_query_register_prog sklgt4_compute_l3_cache_flex_regs[7]; + +static struct brw_perf_query_counter sklgt4_compute_l3_cache_query_counters[54]; +static struct brw_perf_query_info sklgt4_compute_l3_cache_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics L3 Cache Gen9", + .guid = "4e4392e9-8f73-457b-ab44-b49f7a0c733b", + .counters = sklgt4_compute_l3_cache_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt4_compute_l3_cache_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt4_compute_l3_cache_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt4_compute_l3_cache_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt4_register_compute_l3_cache_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt4_compute_l3_cache_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C0760 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1593001E }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x184E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E8020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0051 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C5C5D }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C5E5F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1CE000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0030 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C2A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F1500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0140 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162C0A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03933300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05930032 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900157 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900158 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190030F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900021 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53905555 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FEFE }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FEFD }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FBEF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FBDF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00101100 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00201200 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00301300 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00401400 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_l3_cache__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__l3_bank03_accesses__read; + counter->name = "L3 Bank 03 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 03."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__l3_accesses__read; + counter->name = "L3 Accesses"; + counter->desc = "The total number of L3 accesses from all entities."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_l3_cache__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__l3_sampler_throughput__read; + counter->name = "L3 Sampler Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_l3_cache__fpu0_active__read; + counter->name = "EU FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_l3_cache__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 52; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_l3_cache__eu_avg_ipc_rate__read; + counter->name = "EU AVG IPC Rate"; + counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 2.0; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_l3_cache__eu_binary_fpu0_instruction__read; + counter->name = "EU FPU0 Binary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 60; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_l3_cache__eu_hybrid_fpu0_instruction__read; + counter->name = "EU FPU0 Hybrid Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 104; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__l3_misses__read; + counter->name = "L3 Misses"; + counter->desc = "The total number of L3 misses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__l3_bank00_accesses__read; + counter->name = "L3 Bank 00 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 00."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_l3_cache__eu_move_fpu0_instruction__read; + counter->name = "EU FPU0 Move Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_l3_cache__eu_hybrid_fpu1_instruction__read; + counter->name = "EU FPU1 Hybrid Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt4__compute_l3_cache__avg_gpu_core_frequency__max(brw); + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__gti_read_throughput__read; + counter->name = "GTI Read Throughput"; + counter->desc = "The total number of GPU memory bytes read from GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__gti_l3_throughput__read; + counter->name = "GTI L3 Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__l3_bank00_ic_accesses__read; + counter->name = "L3 Bank 00 IC Accesses"; + counter->desc = "The total number of accesses to L3 Bank 00 from IC cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + } + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__l3_bank00_ic_hits__read; + counter->name = "L3 Bank 00 IC Hits"; + counter->desc = "The total number of hits in L3 Bank 00 from IC cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__sampler_accesses__read; + counter->name = "Sampler Accesses"; + counter->desc = "The total number of messages send to samplers."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__l3_bank01_accesses__read; + counter->name = "L3 Bank 01 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 01."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_l3_cache__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 256; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_l3_cache__eu_ternary_fpu0_instruction__read; + counter->name = "EU FPU0 Ternary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 260; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_l3_cache__eu_move_fpu1_instruction__read; + counter->name = "EU FPU1 Move Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 296; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_l3_cache__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 300; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__l3_bank02_accesses__read; + counter->name = "L3 Bank 02 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 02."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 328; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__l3_total_throughput__read; + counter->name = "L3 Total Throughput"; + counter->desc = "The total number of GPU memory bytes transferred via L3."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 336; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__gti_write_throughput__read; + counter->name = "GTI Write Throughput"; + counter->desc = "The total number of GPU memory bytes written to GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 344; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 352; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 360; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_l3_cache__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 368; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_l3_cache__eu_binary_fpu1_instruction__read; + counter->name = "EU FPU1 Binary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 376; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_l3_cache__eu_ternary_fpu1_instruction__read; + counter->name = "EU FPU1 Ternary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 380; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_l3_cache__eu_send_active__read; + counter->name = "EU Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 384; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt4_hdc_and_sf_mux_regs[54]; +static struct brw_perf_query_register_prog sklgt4_hdc_and_sf_b_counter_regs[8]; +static struct brw_perf_query_register_prog sklgt4_hdc_and_sf_flex_regs[7]; + +static struct brw_perf_query_counter sklgt4_hdc_and_sf_query_counters[39]; +static struct brw_perf_query_info sklgt4_hdc_and_sf_query = { + .kind = OA_COUNTERS, + .name = "Metric set HDCAndSF", + .guid = "730d95dd-7da8-4e1c-ab8d-c0eb1e4c1805", + .counters = sklgt4_hdc_and_sf_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt4_hdc_and_sf_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt4_hdc_and_sf_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt4_hdc_and_sf_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt4_register_hdc_and_sf_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt4_hdc_and_sf_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F0232 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124F4640 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0232 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11834400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004F1880 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024F08BB }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044F001B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C0100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C000B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C1800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x165C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x185C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C00A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F828000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8305C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09830000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07830000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13928000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F988000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FDFF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__hdc_and_sf__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__hdc_and_sf__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__hdc_and_sf__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__hdc_and_sf__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__hdc_and_sf__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__hdc_and_sf__poly_data_ready__read; + counter->name = "Polygon Data Ready"; + counter->desc = "The percentage of time in which geometry pipeline output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt4__hdc_and_sf__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read; + counter->name = "HDC stalled by L3 (s0.ss1)"; + counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss1)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 120; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read; + counter->name = "HDC stalled by L3 (s0.ss2)"; + counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss2)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__hdc_and_sf__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__hdc_and_sf__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__hdc_and_sf__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__hdc_and_sf__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 164; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__hdc_and_sf__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__hdc_and_sf__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read; + counter->name = "HDC stalled by L3 (s0.ss0)"; + counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss0)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 264; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__hdc_and_sf__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt4_l3_1_mux_regs[71]; +static struct brw_perf_query_register_prog sklgt4_l3_1_b_counter_regs[22]; +static struct brw_perf_query_register_prog sklgt4_l3_1_flex_regs[7]; + +static struct brw_perf_query_counter sklgt4_l3_1_query_counters[39]; +static struct brw_perf_query_info sklgt4_l3_1_query = { + .kind = OA_COUNTERS, + .name = "Metric set L3_1", + .guid = "d9e86d70-462b-462a-851e-fd63e8c13d63", + .counters = sklgt4_l3_1_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt4_l3_1_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt4_l3_1_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt4_l3_1_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt4_register_l3_1_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt4_l3_1_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C7B40 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C0020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A603444 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A613400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4EA800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C6C5327 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C5425 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C2A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C285B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C005C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C003C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10600000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04600000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C610044 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10610000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06610000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C02A8 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0154 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FFC0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900420 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900021 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900421 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00014002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000C3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00010002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000C7FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00004002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000D3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100700 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FF1F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00001402 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FC3F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00001002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FC7F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00000402 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FD3F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_1__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_1__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_1__l30_bank1_active__read; + counter->name = "Slice0 L3 Bank1 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank1 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_1__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_1__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_1__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_1__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_1__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_1__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_1__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_1__l30_bank1_stalled__read; + counter->name = "Slice0 L3 Bank1 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank1 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_1__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_1__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_1__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_1__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_1__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_1__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt4__l3_1__avg_gpu_core_frequency__max(brw); + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_1__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_1__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_1__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_1__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_1__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_1__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_1__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_1__l30_bank0_active__read; + counter->name = "Slice0 L3 Bank0 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank0 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_1__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_1__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_1__l30_bank0_stalled__read; + counter->name = "Slice0 L3 Bank0 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank0 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 180; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_1__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_1__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_1__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_1__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_1__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_1__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_1__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_1__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_1__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_1__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_1__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt4_l3_2_mux_regs[44]; +static struct brw_perf_query_register_prog sklgt4_l3_2_b_counter_regs[14]; +static struct brw_perf_query_register_prog sklgt4_l3_2_flex_regs[7]; + +static struct brw_perf_query_counter sklgt4_l3_2_query_counters[37]; +static struct brw_perf_query_info sklgt4_l3_2_query = { + .kind = OA_COUNTERS, + .name = "Metric set L3_2", + .guid = "52200424-6ee9-48b3-b7fa-0afcf1975e4d", + .counters = sklgt4_l3_2_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt4_l3_2_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt4_l3_2_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt4_l3_2_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt4_register_l3_2_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt4_l3_2_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C02E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146C0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A623400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C3324 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C3422 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06614000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C620044 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10620000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06620000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190F800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00028002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x000087FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00020002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00008FFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00008002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000A7FF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_2__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_2__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_2__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_2__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_2__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_2__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_2__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_2__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_2__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_2__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_2__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_2__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_2__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_2__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_2__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt4__l3_2__avg_gpu_core_frequency__max(brw); + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_2__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_2__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_2__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_2__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 128; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_2__l30_bank2_stalled__read; + counter->name = "Slice0 L3 Bank2 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank2 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 132; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_2__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_2__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 140; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_2__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_2__l30_bank2_active__read; + counter->name = "Slice0 L3 Bank2 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank2 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_2__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_2__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_2__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_2__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_2__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 184; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_2__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_2__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_2__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_2__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_2__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_2__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_2__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_2__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt4_l3_3_mux_regs[43]; +static struct brw_perf_query_register_prog sklgt4_l3_3_b_counter_regs[14]; +static struct brw_perf_query_register_prog sklgt4_l3_3_flex_regs[7]; + +static struct brw_perf_query_counter sklgt4_l3_3_query_counters[37]; +static struct brw_perf_query_info sklgt4_l3_3_query = { + .kind = OA_COUNTERS, + .name = "Metric set L3_3", + .guid = "1988315f-0a26-44df-acb0-df7ec86b1456", + .counters = sklgt4_l3_3_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt4_l3_3_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt4_l3_3_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt4_l3_3_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt4_register_l3_3_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt4_l3_3_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C4E80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A633400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C3321 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C342F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C1800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06604000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C630044 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10630000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06630000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C00AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190F800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00028002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x000087FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00020002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00008FFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00008002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000A7FF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_3__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_3__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_3__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_3__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_3__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_3__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_3__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_3__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_3__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_3__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_3__l30_bank3_stalled__read; + counter->name = "Slice0 L3 Bank3 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank3 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_3__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_3__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_3__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_3__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_3__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt4__l3_3__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_3__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_3__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_3__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_3__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_3__l30_bank3_active__read; + counter->name = "Slice0 L3 Bank3 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank3 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 140; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_3__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_3__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_3__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_3__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_3__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_3__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_3__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__l3_3__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_3__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_3__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_3__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_3__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_3__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_3__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_3__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__l3_3__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt4_rasterizer_and_pixel_backend_mux_regs[31]; +static struct brw_perf_query_register_prog sklgt4_rasterizer_and_pixel_backend_b_counter_regs[10]; +static struct brw_perf_query_register_prog sklgt4_rasterizer_and_pixel_backend_flex_regs[7]; + +static struct brw_perf_query_counter sklgt4_rasterizer_and_pixel_backend_query_counters[40]; +static struct brw_perf_query_info sklgt4_rasterizer_and_pixel_backend_query = { + .kind = OA_COUNTERS, + .name = "Metric set RasterizerAndPixelBackend", + .guid = "f1f17ca7-286e-4ae5-9d15-9fccad6c665d", + .counters = sklgt4_rasterizer_and_pixel_backend_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt4_rasterizer_and_pixel_backend_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt4_rasterizer_and_pixel_backend_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt4_rasterizer_and_pixel_backend_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt4_register_rasterizer_and_pixel_backend_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt4_rasterizer_and_pixel_backend_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102F3800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x144D0500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x120D03C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x140D03CF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0004 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F0480 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0090 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064D0027 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004D0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D0D40 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020D803F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040D8023 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100D0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020F0010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0050 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41901400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43901485 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000EFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00006000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F3FF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__rasterizer_and_pixel_backend__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__rasterizer_and_pixel_backend__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__rasterizer_and_pixel_backend__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__rasterizer_and_pixel_backend__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__rasterizer_and_pixel_backend__pixel_values0_ready__read; + counter->name = "Slice0 Pixel Values Ready"; + counter->desc = "The percentage of time in which slice0 pixel values are ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt4__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__rasterizer_and_pixel_backend__rasterizer0_input_available__read; + counter->name = "Slice0 Rasterizer Input Available"; + counter->desc = "The percentage of time in which slice0 rasterizer input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 128; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__rasterizer_and_pixel_backend__pixel_data0_ready__read; + counter->name = "Slice0 Post-EarlyZ Pixel Data Ready"; + counter->desc = "The percentage of time in which slice0 post-EarlyZ pixel data is ready (after early Z tests have been applied)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 132; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__rasterizer_and_pixel_backend__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__rasterizer_and_pixel_backend__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__rasterizer_and_pixel_backend__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__rasterizer_and_pixel_backend__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__rasterizer_and_pixel_backend__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__rasterizer_and_pixel_backend__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__rasterizer_and_pixel_backend__rasterizer0_output_ready__read; + counter->name = "Slice0 Rasterizer Output Ready"; + counter->desc = "The percentage of time in which slice0 rasterizer output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 196; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__rasterizer_and_pixel_backend__ps_output0_available__read; + counter->name = "Slice0 PS Output Available"; + counter->desc = "The percentage of time in which slice0 PS output is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 256; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__rasterizer_and_pixel_backend__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt4_sampler_mux_regs[69]; +static struct brw_perf_query_register_prog sklgt4_sampler_b_counter_regs[12]; +static struct brw_perf_query_register_prog sklgt4_sampler_flex_regs[7]; + +static struct brw_perf_query_counter sklgt4_sampler_query_counters[41]; +static struct brw_perf_query_info sklgt4_sampler_query = { + .kind = OA_COUNTERS, + .name = "Metric set Sampler", + .guid = "00a9e0fb-3d2e-4405-852c-dce6334ffb3b", + .counters = sklgt4_sampler_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt4_sampler_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt4_sampler_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt4_sampler_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt4_register_sampler_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt4_sampler_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14152C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16150005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121600A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14352C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16350005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123600A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14552C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16550005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125600A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062F6000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0050 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0350 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FB000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F00DA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C0028 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C138000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E132000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0413C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C140018 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C157000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E150078 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10150000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04162180 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02160000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04174000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0233A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04333000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14348000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16348000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02357870 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10350000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04360043 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02360000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04371000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E538000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00538000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06533000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C540020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12548000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E557000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00557800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10550000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06560043 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02560000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06571000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FF80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900060 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900060 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x70800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0000C000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000E7FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00003000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F9FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000C00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE7F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__sampler__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__sampler__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__sampler__sampler02_input_available__read; + counter->name = "Slice0 Subslice2 Input Available"; + counter->desc = "The percentage of time in which slice0 subslice2 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__sampler__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__sampler__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__sampler__sampler00_input_available__read; + counter->name = "Slice0 Subslice0 Input Available"; + counter->desc = "The percentage of time in which slice0 subslice0 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__sampler__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 28; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__sampler__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__sampler__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__sampler__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__sampler__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__sampler__sampler02_output_ready__read; + counter->name = "Slice0 Subslice2 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice0 subslice2 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__sampler__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__sampler__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__sampler__sampler01_input_available__read; + counter->name = "Slice0 Subslice1 Input Available"; + counter->desc = "The percentage of time in which slice0 subslice1 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 88; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__sampler__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__sampler__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__sampler__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__sampler__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt4__sampler__avg_gpu_core_frequency__max(brw); + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__sampler__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__sampler__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__sampler__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__sampler__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__sampler__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__sampler__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__sampler__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 164; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__sampler__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__sampler__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__sampler__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__sampler__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__sampler__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__sampler__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__sampler__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__sampler__sampler00_output_ready__read; + counter->name = "Slice0 Subslice0 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice0 subslice0 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 224; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__sampler__sampler01_output_ready__read; + counter->name = "Slice0 Subslice1 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice0 subslice1 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 228; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__sampler__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__sampler__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__sampler__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__sampler__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__sampler__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__sampler__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt4_tdl_1_mux_regs[68]; +static struct brw_perf_query_register_prog sklgt4_tdl_1_b_counter_regs[18]; +static struct brw_perf_query_register_prog sklgt4_tdl_1_flex_regs[7]; + +static struct brw_perf_query_counter sklgt4_tdl_1_query_counters[41]; +static struct brw_perf_query_info sklgt4_tdl_1_query = { + .kind = OA_COUNTERS, + .name = "Metric set TDL_1", + .guid = "13dcc50a-7ec0-409b-99d6-a3f932cedcb3", + .counters = sklgt4_tdl_1_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt4_tdl_1_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt4_tdl_1_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt4_tdl_1_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt4_register_tdl_1_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt4_tdl_1_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12120000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12320000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12520000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F3000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F03A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FF000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0095 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02108000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0410C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02118000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0411C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02121880 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041219B5 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02134000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04135000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C308000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E304000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06304000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C318000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E314000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06314000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C321A80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E320033 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06320031 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00320000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C334000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E331000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06331000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E508000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00508000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02504000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E518000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00518000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02514000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E521880 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00521A80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02520033 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E534000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00534000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02531000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FF80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900062 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00009FFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000EFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FDFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE7F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_1__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__tdl_1__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__tdl_1__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__tdl_1__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__tdl_1__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_1__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_1__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__tdl_1__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_1__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_1__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__tdl_1__non_ps_thread02_ready_for_dispatch__read; + counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice2"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_1__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_1__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_1__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_1__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_1__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt4__tdl_1__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_1__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__tdl_1__non_ps_thread00_ready_for_dispatch__read; + counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice0"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 120; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_1__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_1__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__tdl_1__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__tdl_1__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__tdl_1__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__tdl_1__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__tdl_1__ps_thread00_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice0"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_1__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__tdl_1__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_1__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_1__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__tdl_1__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_1__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_1__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__tdl_1__ps_thread01_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice1"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 224; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_1__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_1__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__tdl_1__ps_thread02_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice2"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 248; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_1__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_1__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_1__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_1__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__tdl_1__non_ps_thread01_ready_for_dispatch__read; + counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice1"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 288; + counter->size = sizeof(float); + } + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt4_tdl_2_mux_regs[42]; +static struct brw_perf_query_register_prog sklgt4_tdl_2_b_counter_regs[6]; +static struct brw_perf_query_register_prog sklgt4_tdl_2_flex_regs[7]; + +static struct brw_perf_query_counter sklgt4_tdl_2_query_counters[41]; +static struct brw_perf_query_info sklgt4_tdl_2_query = { + .kind = OA_COUNTERS, + .name = "Metric set TDL_2", + .guid = "97875e21-6624-4aee-9191-682feb3eae21", + .counters = sklgt4_tdl_2_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt4_tdl_2_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt4_tdl_2_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt4_tdl_2_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt4_register_tdl_2_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt4_tdl_2_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12124D60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12322E60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12524D60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F3000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0014 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FE000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0097 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0410C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0411C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04121FB7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04135000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00308000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06304000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00318000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06314000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00321B80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0632003F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00334000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06331000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0250C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0251C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02521FB7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00520000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02535000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_2__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__tdl_2__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__tdl_2__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__tdl_2__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__tdl_2__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_2__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_2__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__tdl_2__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_2__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_2__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_2__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_2__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_2__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__tdl_2__thread_header01_ready_port0__read; + counter->name = "Thread Header Ready on Slice0 Subslice1 Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 88; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__tdl_2__thread_header01_ready_port1__read; + counter->name = "Thread Header Ready on Slice0 Subslice1 Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 92; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_2__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_2__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt4__tdl_2__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_2__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_2__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_2__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__tdl_2__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__tdl_2__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 140; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__tdl_2__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__tdl_2__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__tdl_2__thread_header02_ready_port1__read; + counter->name = "Thread Header Ready on Slice0 Subslice2 Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__tdl_2__thread_header02_ready_port0__read; + counter->name = "Thread Header Ready on Slice0 Subslice2 Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_2__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__tdl_2__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_2__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_2__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__tdl_2__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_2__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_2__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_2__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_2__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_2__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_2__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_2__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__tdl_2__thread_header00_ready_port0__read; + counter->name = "Thread Header Ready on Slice0 Subslice0 Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 256; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__tdl_2__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__tdl_2__thread_header00_ready_port1__read; + counter->name = "Thread Header Ready on Slice0 Subslice0 Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 272; + counter->size = sizeof(float); + } + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt4_compute_extra_mux_regs[112]; + +static struct brw_perf_query_counter sklgt4_compute_extra_query_counters[4]; +static struct brw_perf_query_info sklgt4_compute_extra_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics Extra Gen9", + .guid = "a5aa857d-e8f0-4dfa-8981-ce340fa748fd", + .counters = sklgt4_compute_extra_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt4_compute_extra_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt4_register_compute_extra_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt4_compute_extra_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121203E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123203E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125203E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x129203E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12B203E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12D203E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x131203E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x133203E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x135203E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4EF000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024EC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044EC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064EC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C02A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0042 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0150 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F006D }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00A8 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06104000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06114000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06120033 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06131000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04308000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04318000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04321980 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00320000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04334000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04504000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04514000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04520033 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00520000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04531000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ACEF000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CCE0003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00AF8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CCC02A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ACC0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C8D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x008D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x028DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x108F0150 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C8FB000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E8F0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18AC00A8 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06AC8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02AD4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02918000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02921980 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00920000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02934000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B04000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B14000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B20033 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B20000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B31000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D08000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D18000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D21980 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D34000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x072F8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D4C0100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D0D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x110F01B0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x192C0080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F2D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F108000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F118000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F121980 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01120000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F134000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F304000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F314000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F320033 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01320000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F331000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D508000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D518000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D521980 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01520000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D534000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FF80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51901100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41901000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43901423 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53903331 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900044 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_extra__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__compute_extra__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_extra__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__compute_extra__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt4__compute_extra__avg_gpu_core_frequency__max(brw); + counter->offset = 24; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt4_vme_pipe_mux_regs[73]; +static struct brw_perf_query_register_prog sklgt4_vme_pipe_b_counter_regs[17]; +static struct brw_perf_query_register_prog sklgt4_vme_pipe_flex_regs[2]; + +static struct brw_perf_query_counter sklgt4_vme_pipe_query_counters[10]; +static struct brw_perf_query_info sklgt4_vme_pipe_query = { + .kind = OA_COUNTERS, + .name = "Media Vme Pipe Gen9", + .guid = "0e8d8b86-4ee7-4cdd-aaaa-58adc92cb29e", + .counters = sklgt4_vme_pipe_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt4_vme_pipe_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt4_vme_pipe_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = sklgt4_vme_pipe_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt4_register_vme_pipe_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt4_vme_pipe_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141A5800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161A00C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12180240 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14180002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x149A5800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x169A00C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12980240 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14980002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E3FC0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F3000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C9500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CAA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C000A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04193000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081A28C1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00133000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0613C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0813F000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00172000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06178000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0817A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00180037 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06180940 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08180000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02180000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04183000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04AFC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06AF3000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ACC4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CCC0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E8F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x108F0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16ACA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18AC000A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06993000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9A28C1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x009A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A93F000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C93F000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A97A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C97A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A980977 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08980000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04980000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06983000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x119000FF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900060 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900111 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900821 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100030 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF9 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FFFC }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FFF3 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100180 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFCF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FF3F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00008003 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__vme_pipe__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__vme_pipe__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__vme_pipe__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__vme_pipe__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__vme_pipe__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt4__vme_pipe__avg_gpu_core_frequency__max(brw); + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__vme_pipe__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__vme_pipe__eu_thread_occupancy__read; + counter->name = "EU Thread Occupancy"; + counter->desc = "The percentage of time in which hardware threads occupied EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__vme_pipe__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 44; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__vme_pipe__vme_busy__read; + counter->name = "VME Busy"; + counter->desc = "The percentage of time in which VME (IME or CRE) was actively processing data."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__vme_pipe__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 52; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt4_gpu_busyness_mux_regs[43]; +static struct brw_perf_query_register_prog sklgt4_gpu_busyness_b_counter_regs[7]; + +static struct brw_perf_query_counter sklgt4_gpu_busyness_query_counters[9]; +static struct brw_perf_query_info sklgt4_gpu_busyness_query = { + .kind = OA_COUNTERS, + .name = "Gpu Rings Busyness", + .guid = "4e5b1599-5b01-4b3d-89fa-6b26a25fe02b", + .counters = sklgt4_gpu_busyness_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt4_gpu_busyness_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt4_gpu_busyness_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt4_register_gpu_busyness_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt4_gpu_busyness_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21D05800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13805800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05962C25 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19950016 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21C05800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09D000A5 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11D00000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05D00000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09D54000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07800035 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21960000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0996C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B964000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930068 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15948000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B94000C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03957500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17950000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07928000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03988000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09978000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0BC000A5 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11C00000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05C00000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0BC54000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900463 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007C000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x000007FF }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__gpu_busyness__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__gpu_busyness__vebox_busy__read; + counter->name = "Vebox Ring Busy"; + counter->desc = "The percentage of time when vebox command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__gpu_busyness__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__gpu_busyness__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt4__gpu_busyness__avg_gpu_core_frequency__max(brw); + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__gpu_busyness__render_busy__read; + counter->name = "Render Ring Busy"; + counter->desc = "The percentage of time when render command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__gpu_busyness__vdbox0_busy__read; + counter->name = "Vdbox0 Ring Busy"; + counter->desc = "The percentage of time when Vdbox0 command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 36; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__gpu_busyness__blitter_busy__read; + counter->name = "Blitter Ring Busy"; + counter->desc = "The percentage of time when blitter command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__gpu_busyness__any_ring_busy__read; + counter->name = "AnyRingBusy"; + counter->desc = "The percentage of time when any command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 44; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = sklgt4__gpu_busyness__vdbox1_busy__read; + counter->name = "Vdbox1 Ring Busy"; + counter->desc = "The percentage of time when Vdbox1 command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog sklgt4_test_oa_mux_regs[13]; +static struct brw_perf_query_register_prog sklgt4_test_oa_b_counter_regs[22]; + +static struct brw_perf_query_counter sklgt4_test_oa_query_counters[12]; +static struct brw_perf_query_info sklgt4_test_oa_query = { + .kind = OA_COUNTERS, + .name = "MDAPI testing set Gen9", + .guid = "882fa433-1f4a-4a67-a962-c741888fe5f5", + .counters = sklgt4_test_oa_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = sklgt4_test_oa_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = sklgt4_test_oa_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ +}; + +static void +sklgt4_register_test_oa_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &sklgt4_test_oa_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07810013 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000004 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000003 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000007 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFF7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00100082 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFEF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x001000C2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FFE7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00100001 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FFE7 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__test_oa__counter7__read; + counter->name = "TestCounter7"; + counter->desc = "HW test counter 7. Factor: 0.666"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__test_oa__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 8; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__test_oa__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__test_oa__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = sklgt4__test_oa__avg_gpu_core_frequency__max(brw); + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__test_oa__counter8__read; + counter->name = "TestCounter8"; + counter->desc = "HW test counter 8. Should be equal to 1."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__test_oa__counter4__read; + counter->name = "TestCounter4"; + counter->desc = "HW test counter 4. Factor: 0.333"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__test_oa__counter5__read; + counter->name = "TestCounter5"; + counter->desc = "HW test counter 5. Factor: 0.333"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__test_oa__counter6__read; + counter->name = "TestCounter6"; + counter->desc = "HW test counter 6. Factor: 0.166"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__test_oa__counter3__read; + counter->name = "TestCounter3"; + counter->desc = "HW test counter 3. Factor: 0.5"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__test_oa__counter0__read; + counter->name = "TestCounter0"; + counter->desc = "HW test counter 0. Factor: 0.0"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__test_oa__counter1__read; + counter->name = "TestCounter1"; + counter->desc = "HW test counter 1. Factor: 1.0"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = sklgt4__test_oa__counter2__read; + counter->name = "TestCounter2"; + counter->desc = "HW test counter 2. Factor: 1.0"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +void +brw_oa_register_queries_sklgt4(struct brw_context *brw) +{ + sklgt4_register_render_basic_counter_query(brw); + sklgt4_register_compute_basic_counter_query(brw); + sklgt4_register_render_pipe_profile_counter_query(brw); + sklgt4_register_memory_reads_counter_query(brw); + sklgt4_register_memory_writes_counter_query(brw); + sklgt4_register_compute_extended_counter_query(brw); + sklgt4_register_compute_l3_cache_counter_query(brw); + sklgt4_register_hdc_and_sf_counter_query(brw); + sklgt4_register_l3_1_counter_query(brw); + sklgt4_register_l3_2_counter_query(brw); + sklgt4_register_l3_3_counter_query(brw); + sklgt4_register_rasterizer_and_pixel_backend_counter_query(brw); + sklgt4_register_sampler_counter_query(brw); + sklgt4_register_tdl_1_counter_query(brw); + sklgt4_register_tdl_2_counter_query(brw); + sklgt4_register_compute_extra_counter_query(brw); + sklgt4_register_vme_pipe_counter_query(brw); + sklgt4_register_gpu_busyness_counter_query(brw); + sklgt4_register_test_oa_counter_query(brw); +} + +static struct brw_perf_query_register_prog bxt_render_basic_mux_regs[80]; +static struct brw_perf_query_register_prog bxt_render_basic_b_counter_regs[5]; +static struct brw_perf_query_register_prog bxt_render_basic_flex_regs[7]; + +static struct brw_perf_query_counter bxt_render_basic_query_counters[52]; +static struct brw_perf_query_info bxt_render_basic_query = { + .kind = OA_COUNTERS, + .name = "Render Metrics Basic Gen9", + .guid = "22b9519a-e9ba-4c41-8b54-f4f8ca14fa0a", + .counters = bxt_render_basic_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bxt_render_basic_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bxt_render_basic_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = bxt_render_basic_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +bxt_register_render_basic_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bxt_render_basic_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + if (brw->perfquery.sys_vars.revision >= 0x03) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C00F0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12120280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12320280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11930317 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x159303DF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x419000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2D1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E0800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E5900 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4F0010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A6C0053 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0FCC00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C0F0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C2C0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00101000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04101000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00114000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08114000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08120021 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00141000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08141000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02308000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04302000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06318000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08318000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06320800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08320840 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00320000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06344000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08344000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D931831 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F939F3F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01939E80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x039303BC }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0593000E }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1993002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900177 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900187 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53901110 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900423 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900111 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C02 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59901111 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900421 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900821 }; + } + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_basic__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__render_basic__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_basic__l3_misses__read; + counter->name = "L3 Misses"; + counter->desc = "The total number of L3 misses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_basic__gti_l3_throughput__read; + counter->name = "GTI L3 Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__render_basic__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_basic__sampler_l1_misses__read; + counter->name = "Sampler Cache Misses"; + counter->desc = "The total number of sampler cache misses in all LODs in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__render_basic__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x12) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__render_basic__sampler1_bottleneck__read; + counter->name = "Sampler 1 Bottleneck"; + counter->desc = "The percentage of time in which Sampler 1 has been slowing down the pipe when processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 52; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__render_basic__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_basic__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_basic__l3_sampler_throughput__read; + counter->name = "L3 Sampler Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_basic__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__render_basic__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 88; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_basic__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_basic__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x09) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__render_basic__sampler0_busy__read; + counter->name = "Sampler 0 Busy"; + counter->desc = "The percentage of time in which Sampler 0 has been processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 112; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x12) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__render_basic__sampler1_busy__read; + counter->name = "Sampler 1 Busy"; + counter->desc = "The percentage of time in which Sampler 1 has been processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 116; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__render_basic__samplers_busy__read; + counter->name = "Samplers Busy"; + counter->desc = "The percentage of time in which samplers have been processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 120; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_basic__gti_vf_throughput__read; + counter->name = "GTI Fixed Pipe Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between 3D Pipeline (Command Dispatch, Input Assembly and Stream Output) and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_basic__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x09) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__render_basic__sampler0_bottleneck__read; + counter->name = "Sampler 0 Bottleneck"; + counter->desc = "The percentage of time in which Sampler 0 has been slowing down the pipe when processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_basic__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_basic__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_basic__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_basic__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bxt__render_basic__avg_gpu_core_frequency__max(brw); + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_basic__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_basic__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_basic__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_basic__l3_lookups__read; + counter->name = "L3 Lookup Accesses w/o IC"; + counter->desc = "The total number of L3 cache lookup accesses w/o IC."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_basic__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_basic__gti_read_throughput__read; + counter->name = "GTI Read Throughput"; + counter->desc = "The total number of GPU memory bytes read from GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__render_basic__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 232; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__render_basic__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 236; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_basic__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__render_basic__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 248; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_basic__gti_depth_throughput__read; + counter->name = "GTI Depth Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between depth caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__render_basic__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 264; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__render_basic__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 268; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_basic__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_basic__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__render_basic__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 288; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_basic__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_basic__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__render_basic__sampler_bottleneck__read; + counter->name = "Samplers Bottleneck"; + counter->desc = "The percentage of time in which samplers have been slowing down the pipe when processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 312; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_basic__gti_hdc_lookups_throughput__read; + counter->name = "GTI HDC TLB Lookup Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between GTI and HDC, when HDC is doing TLB lookups."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_basic__gti_rcc_throughput__read; + counter->name = "GTI RCC Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between render color caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 328; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_basic__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 336; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_basic__gti_write_throughput__read; + counter->name = "GTI Write Throughput"; + counter->desc = "The total number of GPU memory bytes written to GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 344; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_basic__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 352; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_basic__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 360; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_basic__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 368; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_basic__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 376; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog bxt_compute_basic_mux_regs[72]; +static struct brw_perf_query_register_prog bxt_compute_basic_b_counter_regs[5]; +static struct brw_perf_query_register_prog bxt_compute_basic_flex_regs[7]; + +static struct brw_perf_query_counter bxt_compute_basic_query_counters[39]; +static struct brw_perf_query_info bxt_compute_basic_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics Basic Gen9", + .guid = "012d72cf-82a9-4d25-8ddf-74076fd30797", + .counters = bxt_compute_basic_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bxt_compute_basic_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bxt_compute_basic_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = bxt_compute_basic_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +bxt_register_compute_basic_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bxt_compute_basic_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F00E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124F1C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x39900340 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2D1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E1400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E5100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102E0114 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x164C2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004F6B42 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F6200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084F4100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4F0061 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4F6C4C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4F4B00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x180F5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0F8800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C0F08A2 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C2C1451 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E2C0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2C0010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19938A28 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19900177 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B900178 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900125 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900123 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53901000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900111 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_basic__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_basic__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_basic__untyped_bytes_read__read; + counter->name = "Untyped Bytes Read"; + counter->desc = "The total number of typed memory bytes read via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_basic__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_basic__typed_bytes_written__read; + counter->name = "Typed Bytes Written"; + counter->desc = "The total number of untyped memory bytes written via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_basic__fpu0_active__read; + counter->name = "EU FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_basic__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 44; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_basic__eu_avg_ipc_rate__read; + counter->name = "EU AVG IPC Rate"; + counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 2.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_basic__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_basic__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_basic__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_basic__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_basic__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_basic__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_basic__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_basic__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_basic__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bxt__compute_basic__avg_gpu_core_frequency__max(brw); + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_basic__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_basic__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_basic__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_basic__gti_read_throughput__read; + counter->name = "GTI Read Throughput"; + counter->desc = "The total number of GPU memory bytes read from GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_basic__untyped_bytes_written__read; + counter->name = "Untyped Writes"; + counter->desc = "The total number of untyped memory bytes written via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_basic__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_basic__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_basic__typed_bytes_read__read; + counter->name = "Typed Bytes Read"; + counter->desc = "The total number of typed memory bytes read via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_basic__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_basic__eu_thread_occupancy__read; + counter->name = "EU Thread Occupancy"; + counter->desc = "The percentage of time in which hardware threads occupied EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_basic__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 204; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_basic__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_basic__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_basic__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_basic__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_basic__gti_write_throughput__read; + counter->name = "GTI Write Throughput"; + counter->desc = "The total number of GPU memory bytes written to GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_basic__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_basic__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_basic__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_basic__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_basic__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_basic__eu_send_active__read; + counter->name = "EU Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 288; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog bxt_render_pipe_profile_mux_regs[94]; +static struct brw_perf_query_register_prog bxt_render_pipe_profile_b_counter_regs[21]; +static struct brw_perf_query_register_prog bxt_render_pipe_profile_flex_regs[7]; + +static struct brw_perf_query_counter bxt_render_pipe_profile_query_counters[43]; +static struct brw_perf_query_info bxt_render_pipe_profile_query = { + .kind = OA_COUNTERS, + .name = "Render Metrics for 3D Pipeline Profile Gen9", + .guid = "ce416533-e49e-4211-80af-ec513590a914", + .counters = bxt_render_pipe_profile_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bxt_render_pipe_profile_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bxt_render_pipe_profile_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = bxt_render_pipe_profile_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +bxt_register_render_pipe_profile_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bxt_render_pipe_profile_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E001F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10186800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810019 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15810013 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13820020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11830020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17840000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11860007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21860000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178703E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022E5400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002E0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E0080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082F0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06143000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06174000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06180012 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00180000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D804000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F804000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05804000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09810200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B810030 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03810003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21819140 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23819050 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25810018 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B820980 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03820D80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11820000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0182C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07828000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09824000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F828000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D830004 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0583000C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F831000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848072 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11840000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09844000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07860000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09860092 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F860400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01869100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F870065 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01870000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19930800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B952000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D955055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F951455 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0992A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F928000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1192A800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1392028A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B92A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D922000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900C01 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900863 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900061 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C22 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFEA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFC }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007AFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F5FD }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00079FFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000F3FB }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007BF7A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F7E7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FEFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000F7CF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00077FFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000EFDF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0006FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000CFBF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0003FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x00005F7F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_pipe_profile__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__render_pipe_profile__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__render_pipe_profile__vs_bottleneck__read; + counter->name = "VS Bottleneck"; + counter->desc = "The percentage of time in which vertex shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__render_pipe_profile__hi_depth_bottleneck__read; + counter->name = "Hi-Depth Bottleneck"; + counter->desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__render_pipe_profile__gs_bottleneck__read; + counter->name = "GS Bottleneck"; + counter->desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_pipe_profile__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_pipe_profile__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_pipe_profile__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_pipe_profile__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__render_pipe_profile__bc_bottleneck__read; + counter->name = "BC Bottleneck"; + counter->desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__render_pipe_profile__hs_stall__read; + counter->name = "HS Stall"; + counter->desc = "The percentage of time in which hull stall pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 60; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_pipe_profile__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_pipe_profile__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_pipe_profile__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_pipe_profile__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_pipe_profile__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bxt__render_pipe_profile__avg_gpu_core_frequency__max(brw); + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_pipe_profile__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_pipe_profile__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__render_pipe_profile__vf_bottleneck__read; + counter->name = "VF Bottleneck"; + counter->desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_pipe_profile__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__render_pipe_profile__sf_bottleneck__read; + counter->name = "Strip-Fans Bottleneck"; + counter->desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__render_pipe_profile__sf_stall__read; + counter->name = "SF Stall"; + counter->desc = "The percentage of time in which strip-fans pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 140; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__render_pipe_profile__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__render_pipe_profile__hs_bottleneck__read; + counter->name = "HS Bottleneck"; + counter->desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__render_pipe_profile__cl_stall__read; + counter->name = "CL Stall"; + counter->desc = "The percentage of time in which clipper pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__render_pipe_profile__so_bottleneck__read; + counter->name = "SO Bottleneck"; + counter->desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_pipe_profile__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_pipe_profile__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_pipe_profile__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__render_pipe_profile__ds_bottleneck__read; + counter->name = "DS Bottleneck"; + counter->desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__render_pipe_profile__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 188; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__render_pipe_profile__cl_bottleneck__read; + counter->name = "Clipper Bottleneck"; + counter->desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__render_pipe_profile__ds_stall__read; + counter->name = "DS Stall"; + counter->desc = "The percentage of time in which domain shader pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 196; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__render_pipe_profile__early_depth_bottleneck__read; + counter->name = "Early Depth Bottleneck"; + counter->desc = "The percentage of time in which early depth test pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_pipe_profile__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_pipe_profile__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_pipe_profile__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_pipe_profile__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_pipe_profile__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_pipe_profile__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_pipe_profile__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__render_pipe_profile__so_stall__read; + counter->name = "SO Stall"; + counter->desc = "The percentage of time in which stream-output pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__render_pipe_profile__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog bxt_memory_reads_mux_regs[44]; +static struct brw_perf_query_register_prog bxt_memory_reads_b_counter_regs[32]; +static struct brw_perf_query_register_prog bxt_memory_reads_flex_regs[7]; + +static struct brw_perf_query_counter bxt_memory_reads_query_counters[41]; +static struct brw_perf_query_info bxt_memory_reads_query = { + .kind = OA_COUNTERS, + .name = "Memory Reads Distribution Gen9", + .guid = "398e2452-18d7-42d0-b241-e4d0a9148ada", + .counters = bxt_memory_reads_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bxt_memory_reads_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bxt_memory_reads_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = bxt_memory_reads_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +bxt_register_memory_reads_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bxt_memory_reads_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19800343 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x39900340 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F901000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03803180 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058035E2 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0780006A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2181A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2381000A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950550 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B928000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D92A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F922000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900170 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21900171 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23900172 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25900173 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27900174 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900175 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B900176 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D900177 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F90017F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900125 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900123 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900121 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43901084 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47901080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49901084 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B901084 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900004 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000272C, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002728, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000271C, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002718, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F872 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_reads__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__memory_reads__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_reads__gti_l3_bank0_reads__read; + counter->name = "GtiL3Bank0Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 0 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_reads__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_reads__gti_ring_accesses__read; + counter->name = "GtiRingAccesses"; + counter->desc = "The total number of all accesses from GTI to the ring."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_reads__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_reads__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_reads__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_reads__gti_l3_bank3_reads__read; + counter->name = "GtiL3Bank3Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 3 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_reads__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_reads__gti_rs_memory_reads__read; + counter->name = "GtiRsMemoryReads"; + counter->desc = "The total number of GTI memory reads from Resource Streamer."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_reads__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_reads__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_reads__gti_hiz_memory_reads__read; + counter->name = "GtiHizMemoryReads"; + counter->desc = "The total number of GTI memory reads from Hierarchical Depth Cache (Hi-Depth Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_reads__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_reads__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bxt__memory_reads__avg_gpu_core_frequency__max(brw); + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_reads__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_reads__gti_rcc_memory_reads__read; + counter->name = "GtiRccMemoryReads"; + counter->desc = "The total number of GTI memory reads from Render Color Cache (Render Color Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_reads__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_reads__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_reads__gti_l3_bank1_reads__read; + counter->name = "GtiL3Bank1Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 1 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__memory_reads__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_reads__gti_cmd_streamer_memory_reads__read; + counter->name = "GtiCmdStreamerMemoryReads"; + counter->desc = "The total number of GTI memory reads from Command Streamer."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_reads__gti_l3_bank2_reads__read; + counter->name = "GtiL3Bank2Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 2 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_reads__gti_memory_reads__read; + counter->name = "GtiMemoryReads"; + counter->desc = "The total number of GTI memory reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_reads__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_reads__gti_rcz_memory_reads__read; + counter->name = "GtiRczMemoryReads"; + counter->desc = "The total number of GTI memory reads from Render Depth Cache (Render Depth Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_reads__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_reads__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__memory_reads__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 232; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_reads__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_reads__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_reads__gti_msc_memory_reads__read; + counter->name = "GtiMscMemoryReads"; + counter->desc = "The total number of GTI memory reads from Multisampling Color Cache (Multisampling Color Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_reads__gti_vf_memory_reads__read; + counter->name = "GtiVfMemoryReads"; + counter->desc = "The total number of GTI memory reads from Vertex Fetch."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_reads__gti_stc_memory_reads__read; + counter->name = "GtiStcMemoryReads"; + counter->desc = "The total number of GTI memory reads from Stencil Cache (Stencil Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_reads__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_reads__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_reads__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_reads__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_reads__gti_l3_reads__read; + counter->name = "GtiL3Reads"; + counter->desc = "The total number of GTI memory reads from L3 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_reads__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog bxt_memory_writes_mux_regs[44]; +static struct brw_perf_query_register_prog bxt_memory_writes_b_counter_regs[32]; +static struct brw_perf_query_register_prog bxt_memory_writes_flex_regs[7]; + +static struct brw_perf_query_counter bxt_memory_writes_query_counters[41]; +static struct brw_perf_query_info bxt_memory_writes_query = { + .kind = OA_COUNTERS, + .name = "Memory Writes Distribution Gen9", + .guid = "d324a0d6-7269-4847-a5c2-6f71ddc7fed5", + .counters = bxt_memory_writes_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bxt_memory_writes_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bxt_memory_writes_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = bxt_memory_writes_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +bxt_register_memory_writes_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bxt_memory_writes_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19800343 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x39900340 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03803180 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058035E2 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0780006A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2181A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2381000A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950550 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B928000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D92A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F922000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900180 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21900181 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23900182 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25900183 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27900184 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900185 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B900186 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D900187 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F900170 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900125 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900123 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900121 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43901084 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47901080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49901084 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B901084 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900004 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000272C, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002728, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000271C, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002718, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F822 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_writes__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__memory_writes__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_writes__gti_memory_writes__read; + counter->name = "GtiMemoryWrites"; + counter->desc = "The total number of GTI memory writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_writes__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_writes__gti_ring_accesses__read; + counter->name = "GtiRingAccesses"; + counter->desc = "The total number of all GTI accesses to the ring."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_writes__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_writes__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_writes__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_writes__gti_msc_memory_writes__read; + counter->name = "GtiMscMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Multisampling Color Cache (Multisampling Color Cache invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_writes__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_writes__gti_cmd_streamer_memory_writes__read; + counter->name = "GtiCmdStreamerMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Command Streamer."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_writes__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_writes__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_writes__gti_l3_bank0_writes__read; + counter->name = "GtiL3Bank0Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 0 (L3 Bank 0 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_writes__gti_l3_bank1_writes__read; + counter->name = "GtiL3Bank1Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 1 (L3 Bank 1 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_writes__gti_l3_bank2_writes__read; + counter->name = "GtiL3Bank2Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 2 (L3 Bank 2 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_writes__gti_l3_bank3_writes__read; + counter->name = "GtiL3Bank3Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 3 (L3 Bank 3 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_writes__gti_l3_writes__read; + counter->name = "GtiL3Writes"; + counter->desc = "The total number of GTI memory writes from L3 (L3 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_writes__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_writes__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bxt__memory_writes__avg_gpu_core_frequency__max(brw); + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_writes__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_writes__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_writes__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_writes__gti_rcc_memory_writes__read; + counter->name = "GtiRccMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Render Color Cache (Render Color Cache invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_writes__gti_so_memory_writes__read; + counter->name = "GtiSoMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Stream Output."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__memory_writes__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_writes__gti_stc_memory_writes__read; + counter->name = "GtiStcMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Stencil Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_writes__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_writes__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_writes__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__memory_writes__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 240; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_writes__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_writes__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_writes__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_writes__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_writes__gti_rcz_memory_writes__read; + counter->name = "GtiRczMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Render Depth Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_writes__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_writes__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_writes__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_writes__gti_hiz_memory_writes__read; + counter->name = "GtiHizMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Hierarchical Depth Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__memory_writes__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog bxt_compute_extended_mux_regs[93]; +static struct brw_perf_query_register_prog bxt_compute_extended_b_counter_regs[21]; +static struct brw_perf_query_register_prog bxt_compute_extended_flex_regs[7]; + +static struct brw_perf_query_counter bxt_compute_extended_query_counters[38]; +static struct brw_perf_query_info bxt_compute_extended_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics Extended Gen9", + .guid = "caf3596a-7bb1-4dec-b3b3-2a080d283b49", + .counters = bxt_compute_extended_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bxt_compute_extended_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bxt_compute_extended_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = bxt_compute_extended_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +bxt_register_compute_extended_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bxt_compute_extended_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F00E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C0160 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C0120 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E5400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E5515 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102E0155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x144C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x164C2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4F4B41 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004F4200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024F404C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001C0031 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061C1900 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081C1A33 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1C1B35 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1C3337 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041C31C7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x180F5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0FA8AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C0F0AAA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C2C6AAA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E2C0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2C2950 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1993AAAA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900420 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900001 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FC2A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FC6A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007FC92 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007FCA2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FC32 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FC9A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007FE6A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007FE7A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000BF00 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_extended__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_extended__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_extended__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_extended__fpu0_active__read; + counter->name = "EU FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_extended__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_extended__eu_avg_ipc_rate__read; + counter->name = "EU AVG IPC Rate"; + counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 2.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_extended__typed_writes0__read; + counter->name = "Typed Writes 0"; + counter->desc = "The subslice 0 typed writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_extended__eu_typed_atomics0__read; + counter->name = "EuTypedAtomics0"; + counter->desc = "The subslice 0 EU Typed Atomics subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_extended__typed_atomics0__read; + counter->name = "Typed Atomics 0"; + counter->desc = "The subslice 0 typed atomics."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_extended__typed_atomics_per_cache_line__read; + counter->name = "TypedAtomicsPerCacheLine"; + counter->desc = "The ratio of EU typed atomics requests to L3 cache line writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_extended__eu_untyped_reads0__read; + counter->name = "EuUntypedReads0"; + counter->desc = "The subslice 0 EU Untyped Reads subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_extended__untyped_writes0__read; + counter->name = "Untyped Writes 0"; + counter->desc = "The subslice 0 untyped writes (including SLM writes)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_extended__eu_untyped_atomics0__read; + counter->name = "EuUntypedAtomics0"; + counter->desc = "The subslice 0 EU Untyped Atomics subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_extended__eu_untyped_writes0__read; + counter->name = "EuUntypedWrites0"; + counter->desc = "The subslice 0 EU Untyped Writes subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_extended__eu_a64_untyped_writes0__read; + counter->name = "EuA64UntypedWrites0"; + counter->desc = "The subslice 0 EU A64 Untyped Writes subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_extended__untyped_writes_per_cache_line__read; + counter->name = "UntypedWritesPerCacheLine"; + counter->desc = "The ratio of EU untyped write requests to L3 cache line writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_extended__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_extended__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_extended__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_extended__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bxt__compute_extended__avg_gpu_core_frequency__max(brw); + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_extended__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_extended__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_extended__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_extended__eu_typed_writes0__read; + counter->name = "EuTypedWrites0"; + counter->desc = "The subslice 0 EU Typed Writes subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_extended__typed_writes_per_cache_line__read; + counter->name = "TypedWritesPerCacheLine"; + counter->desc = "The ratio of EU typed write requests to L3 cache line writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_extended__typed_reads0__read; + counter->name = "Typed Reads 0"; + counter->desc = "The subslice 0 typed reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_extended__untyped_reads0__read; + counter->name = "Untyped Reads 0"; + counter->desc = "The subslice 0 untyped reads (including SLM reads)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_extended__eu_a64_untyped_reads0__read; + counter->name = "EuA64UntypedReads0"; + counter->desc = "The subslice 0 EU A64 Untyped Reads subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_extended__eu_thread_occupancy__read; + counter->name = "EU Thread Occupancy"; + counter->desc = "The percentage of time in which hardware threads occupied EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 208; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_extended__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 212; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_extended__eu_typed_reads0__read; + counter->name = "EuTypedReads0"; + counter->desc = "The subslice 0 EU Typed Reads subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_extended__untyped_reads_per_cache_line__read; + counter->name = "UntypedReadsPerCacheLine"; + counter->desc = "The ratio of EU untyped read requests to L3 cache line reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_extended__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_extended__typed_reads_per_cache_line__read; + counter->name = "TypedReadsPerCacheLine"; + counter->desc = "The ratio of EU typed read requests to L3 cache line reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_extended__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_extended__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_extended__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_extended__eu_send_active__read; + counter->name = "EU Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 272; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog bxt_compute_l3_cache_mux_regs[68]; +static struct brw_perf_query_register_prog bxt_compute_l3_cache_b_counter_regs[13]; +static struct brw_perf_query_register_prog bxt_compute_l3_cache_flex_regs[7]; + +static struct brw_perf_query_counter bxt_compute_l3_cache_query_counters[54]; +static struct brw_perf_query_info bxt_compute_l3_cache_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics L3 Cache Gen9", + .guid = "49b956e2-d5b9-47e0-9d8a-cee5e8cec527", + .counters = bxt_compute_l3_cache_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bxt_compute_l3_cache_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bxt_compute_l3_cache_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = bxt_compute_l3_cache_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +bxt_register_compute_l3_cache_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bxt_compute_l3_cache_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C03B0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1593001E }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E0400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E1500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102E0140 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x144C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x164C2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4F4001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4F5005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0051 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C5C5D }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C5E5F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x180F1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0FA800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C0F0A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C2C4015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E2C0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03931980 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05930032 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1993A00A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900177 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900178 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53901000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900111 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900400 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FEFE }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FEFD }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FBEF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FBDF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00101100 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00201200 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00301300 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00401400 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_l3_cache__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_l3_cache__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_l3_cache__l3_bank03_accesses__read; + counter->name = "L3 Bank 03 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 03."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_l3_cache__l3_accesses__read; + counter->name = "L3 Accesses"; + counter->desc = "The total number of L3 accesses from all entities."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_l3_cache__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_l3_cache__l3_sampler_throughput__read; + counter->name = "L3 Sampler Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_l3_cache__fpu0_active__read; + counter->name = "EU FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_l3_cache__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 52; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_l3_cache__eu_avg_ipc_rate__read; + counter->name = "EU AVG IPC Rate"; + counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 2.0; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_l3_cache__eu_binary_fpu0_instruction__read; + counter->name = "EU FPU0 Binary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 60; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_l3_cache__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_l3_cache__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_l3_cache__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_l3_cache__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_l3_cache__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_l3_cache__eu_hybrid_fpu0_instruction__read; + counter->name = "EU FPU0 Hybrid Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 104; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_l3_cache__l3_misses__read; + counter->name = "L3 Misses"; + counter->desc = "The total number of L3 misses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_l3_cache__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_l3_cache__l3_bank00_accesses__read; + counter->name = "L3 Bank 00 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 00."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_l3_cache__eu_move_fpu0_instruction__read; + counter->name = "EU FPU0 Move Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_l3_cache__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_l3_cache__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_l3_cache__eu_hybrid_fpu1_instruction__read; + counter->name = "EU FPU1 Hybrid Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_l3_cache__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_l3_cache__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bxt__compute_l3_cache__avg_gpu_core_frequency__max(brw); + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_l3_cache__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_l3_cache__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_l3_cache__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_l3_cache__gti_read_throughput__read; + counter->name = "GTI Read Throughput"; + counter->desc = "The total number of GPU memory bytes read from GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_l3_cache__gti_l3_throughput__read; + counter->name = "GTI L3 Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_l3_cache__l3_bank00_ic_accesses__read; + counter->name = "L3 Bank 00 IC Accesses"; + counter->desc = "The total number of accesses to L3 Bank 00 from IC cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + } + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_l3_cache__l3_bank00_ic_hits__read; + counter->name = "L3 Bank 00 IC Hits"; + counter->desc = "The total number of hits in L3 Bank 00 from IC cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_l3_cache__sampler_accesses__read; + counter->name = "Sampler Accesses"; + counter->desc = "The total number of messages send to samplers."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_l3_cache__l3_bank01_accesses__read; + counter->name = "L3 Bank 01 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 01."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_l3_cache__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 256; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_l3_cache__eu_ternary_fpu0_instruction__read; + counter->name = "EU FPU0 Ternary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 260; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_l3_cache__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_l3_cache__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_l3_cache__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_l3_cache__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_l3_cache__eu_move_fpu1_instruction__read; + counter->name = "EU FPU1 Move Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 296; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_l3_cache__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 300; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_l3_cache__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_l3_cache__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_l3_cache__l3_bank02_accesses__read; + counter->name = "L3 Bank 02 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 02."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_l3_cache__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 328; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_l3_cache__l3_total_throughput__read; + counter->name = "L3 Total Throughput"; + counter->desc = "The total number of GPU memory bytes transferred via L3."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 336; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_l3_cache__gti_write_throughput__read; + counter->name = "GTI Write Throughput"; + counter->desc = "The total number of GPU memory bytes written to GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 344; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_l3_cache__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 352; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_l3_cache__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 360; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_l3_cache__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 368; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_l3_cache__eu_binary_fpu1_instruction__read; + counter->name = "EU FPU1 Binary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 376; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_l3_cache__eu_ternary_fpu1_instruction__read; + counter->name = "EU FPU1 Ternary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 380; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_l3_cache__eu_send_active__read; + counter->name = "EU Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 384; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog bxt_hdc_and_sf_mux_regs[42]; +static struct brw_perf_query_register_prog bxt_hdc_and_sf_b_counter_regs[8]; +static struct brw_perf_query_register_prog bxt_hdc_and_sf_flex_regs[7]; + +static struct brw_perf_query_counter bxt_hdc_and_sf_query_counters[38]; +static struct brw_perf_query_info bxt_hdc_and_sf_query = { + .kind = OA_COUNTERS, + .name = "Metric set HDCAndSF", + .guid = "f64ef50a-bdba-4b35-8f09-203c13d8ee5a", + .counters = bxt_hdc_and_sf_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bxt_hdc_and_sf_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bxt_hdc_and_sf_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = bxt_hdc_and_sf_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +bxt_register_hdc_and_sf_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bxt_hdc_and_sf_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F0232 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124F4640 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11834400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E0055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024F6100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044F416B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F004B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0F02A8 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2C5500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25810020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8305C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F951000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13920200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FDFF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__hdc_and_sf__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__hdc_and_sf__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__hdc_and_sf__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__hdc_and_sf__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__hdc_and_sf__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__hdc_and_sf__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__hdc_and_sf__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__hdc_and_sf__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__hdc_and_sf__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__hdc_and_sf__poly_data_ready__read; + counter->name = "Polygon Data Ready"; + counter->desc = "The percentage of time in which geometry pipeline output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__hdc_and_sf__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__hdc_and_sf__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__hdc_and_sf__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__hdc_and_sf__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__hdc_and_sf__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__hdc_and_sf__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bxt__hdc_and_sf__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__hdc_and_sf__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read; + counter->name = "HDC stalled by L3 (s0.ss1)"; + counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss1)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 120; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__hdc_and_sf__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__hdc_and_sf__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__hdc_and_sf__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__hdc_and_sf__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__hdc_and_sf__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__hdc_and_sf__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__hdc_and_sf__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__hdc_and_sf__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__hdc_and_sf__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__hdc_and_sf__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__hdc_and_sf__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__hdc_and_sf__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__hdc_and_sf__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__hdc_and_sf__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__hdc_and_sf__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__hdc_and_sf__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__hdc_and_sf__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__hdc_and_sf__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read; + counter->name = "HDC stalled by L3 (s0.ss0)"; + counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss0)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 256; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__hdc_and_sf__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog bxt_l3_1_mux_regs[154]; +static struct brw_perf_query_register_prog bxt_l3_1_b_counter_regs[22]; +static struct brw_perf_query_register_prog bxt_l3_1_flex_regs[7]; + +static struct brw_perf_query_counter bxt_l3_1_query_counters[39]; +static struct brw_perf_query_info bxt_l3_1_query = { + .kind = OA_COUNTERS, + .name = "Metric set L3_1", + .guid = "00ad5a41-7eab-4f7a-9103-49d411c67219", + .counters = bxt_l3_1_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bxt_l3_1_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bxt_l3_1_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = bxt_l3_1_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +bxt_register_l3_1_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bxt_l3_1_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + if (brw->perfquery.sys_vars.revision >= 0x03) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12643400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12653400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C6800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C001E }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C0010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102E0154 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E0055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x144C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x164C2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4F5500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4F1554 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A640024 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10640000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04640000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C650024 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10650000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06650000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C6C5327 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C5425 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C2A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C285B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C005C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0900 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C0F0AA0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x180F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0F02AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C2C5400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E2C0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2C5550 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1993AA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900421 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900420 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900021 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; + } + + if (brw->perfquery.sys_vars.revision < 0x03) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14640340 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14650340 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C6800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C001E }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C0010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102E0154 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E0055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x144C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x164C2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4F5500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4F1554 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04642400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x22640000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A640000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06650024 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x22650000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C650000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C6C5327 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C5425 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C2A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C285B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C005C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0900 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C0F0AA0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x180F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0F02AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C2C5400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E2C0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2C5550 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1993AA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900421 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900420 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900021 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; + } + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00014002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000C3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00010002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000C7FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00004002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000D3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100700 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FF1F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00001402 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FC3F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00001002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FC7F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00000402 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FD3F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__l3_1__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__l3_1__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__l3_1__l30_bank1_active__read; + counter->name = "Slice0 L3 Bank1 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank1 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__l3_1__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__l3_1__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__l3_1__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__l3_1__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__l3_1__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__l3_1__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__l3_1__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__l3_1__l30_bank1_stalled__read; + counter->name = "Slice0 L3 Bank1 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank1 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__l3_1__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__l3_1__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__l3_1__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__l3_1__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__l3_1__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__l3_1__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bxt__l3_1__avg_gpu_core_frequency__max(brw); + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__l3_1__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__l3_1__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__l3_1__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__l3_1__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__l3_1__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__l3_1__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__l3_1__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__l3_1__l30_bank0_active__read; + counter->name = "Slice0 L3 Bank0 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank0 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__l3_1__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__l3_1__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__l3_1__l30_bank0_stalled__read; + counter->name = "Slice0 L3 Bank0 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank0 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 180; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__l3_1__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__l3_1__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__l3_1__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__l3_1__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__l3_1__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__l3_1__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__l3_1__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__l3_1__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__l3_1__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__l3_1__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__l3_1__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog bxt_rasterizer_and_pixel_backend_mux_regs[41]; +static struct brw_perf_query_register_prog bxt_rasterizer_and_pixel_backend_b_counter_regs[10]; +static struct brw_perf_query_register_prog bxt_rasterizer_and_pixel_backend_flex_regs[7]; + +static struct brw_perf_query_counter bxt_rasterizer_and_pixel_backend_query_counters[40]; +static struct brw_perf_query_info bxt_rasterizer_and_pixel_backend_query = { + .kind = OA_COUNTERS, + .name = "Metric set RasterizerAndPixelBackend", + .guid = "46dc44ca-491c-4cc1-a951-e7b3e62bf02b", + .counters = bxt_rasterizer_and_pixel_backend_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bxt_rasterizer_and_pixel_backend_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bxt_rasterizer_and_pixel_backend_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = bxt_rasterizer_and_pixel_backend_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +bxt_register_rasterizer_and_pixel_backend_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bxt_rasterizer_and_pixel_backend_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102D7800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x122D79E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2F0004 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100E3800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x180F0005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D0940 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022D802F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D4013 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E0050 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F0010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040E0480 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000E0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060F0027 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0F0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x439014A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x459000A4 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000EFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00006000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F3FF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__rasterizer_and_pixel_backend__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__rasterizer_and_pixel_backend__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__rasterizer_and_pixel_backend__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__rasterizer_and_pixel_backend__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__rasterizer_and_pixel_backend__pixel_values0_ready__read; + counter->name = "Slice0 Pixel Values Ready"; + counter->desc = "The percentage of time in which slice0 pixel values are ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bxt__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__rasterizer_and_pixel_backend__rasterizer0_input_available__read; + counter->name = "Slice0 Rasterizer Input Available"; + counter->desc = "The percentage of time in which slice0 rasterizer input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 128; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__rasterizer_and_pixel_backend__pixel_data0_ready__read; + counter->name = "Slice0 Post-EarlyZ Pixel Data Ready"; + counter->desc = "The percentage of time in which slice0 post-EarlyZ pixel data is ready (after early Z tests have been applied)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 132; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__rasterizer_and_pixel_backend__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__rasterizer_and_pixel_backend__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__rasterizer_and_pixel_backend__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__rasterizer_and_pixel_backend__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__rasterizer_and_pixel_backend__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__rasterizer_and_pixel_backend__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__rasterizer_and_pixel_backend__rasterizer0_output_ready__read; + counter->name = "Slice0 Rasterizer Output Ready"; + counter->desc = "The percentage of time in which slice0 rasterizer output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 196; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__rasterizer_and_pixel_backend__ps_output0_available__read; + counter->name = "Slice0 PS Output Available"; + counter->desc = "The percentage of time in which slice0 PS output is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 256; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__rasterizer_and_pixel_backend__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog bxt_sampler_mux_regs[93]; +static struct brw_perf_query_register_prog bxt_sampler_b_counter_regs[12]; +static struct brw_perf_query_register_prog bxt_sampler_flex_regs[7]; + +static struct brw_perf_query_counter bxt_sampler_query_counters[41]; +static struct brw_perf_query_info bxt_sampler_query = { + .kind = OA_COUNTERS, + .name = "Metric set Sampler", + .guid = "8364e2a8-af63-40af-b0d5-42969a255654", + .counters = bxt_sampler_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bxt_sampler_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bxt_sampler_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = bxt_sampler_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +bxt_register_sampler_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bxt_sampler_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121300A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141600AB }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123300A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143600AB }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125300A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145600AB }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102E01A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E0065 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x164C2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C0F0800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x180F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0F023F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E2C0003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2CC030 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04132180 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02130000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C148000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E142000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04148000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E150140 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C150040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C163000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E160068 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10160000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18160000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A164000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04330043 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02330000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0234A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04342000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C350015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02363460 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10360000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04360000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06360000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08364000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06530043 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02530000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E548000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00548000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06542000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E550400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A552000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C550100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E563000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00563400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10560000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18560000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02560000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C564000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1993A800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B9014A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900820 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45901022 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x70800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0000C000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000E7FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00003000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F9FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000C00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE7F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__sampler__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__sampler__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__sampler__sampler02_input_available__read; + counter->name = "Slice0 Subslice2 Input Available"; + counter->desc = "The percentage of time in which slice0 subslice2 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__sampler__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__sampler__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__sampler__sampler00_input_available__read; + counter->name = "Slice0 Subslice0 Input Available"; + counter->desc = "The percentage of time in which slice0 subslice0 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__sampler__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 28; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__sampler__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__sampler__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__sampler__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__sampler__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__sampler__sampler02_output_ready__read; + counter->name = "Slice0 Subslice2 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice0 subslice2 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__sampler__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__sampler__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__sampler__sampler01_input_available__read; + counter->name = "Slice0 Subslice1 Input Available"; + counter->desc = "The percentage of time in which slice0 subslice1 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 88; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__sampler__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__sampler__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__sampler__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__sampler__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bxt__sampler__avg_gpu_core_frequency__max(brw); + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__sampler__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__sampler__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__sampler__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__sampler__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__sampler__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__sampler__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__sampler__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 164; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__sampler__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__sampler__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__sampler__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__sampler__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__sampler__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__sampler__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__sampler__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__sampler__sampler00_output_ready__read; + counter->name = "Slice0 Subslice0 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice0 subslice0 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 224; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__sampler__sampler01_output_ready__read; + counter->name = "Slice0 Subslice1 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice0 subslice1 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 228; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__sampler__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__sampler__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__sampler__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__sampler__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__sampler__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__sampler__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog bxt_tdl_1_mux_regs[86]; +static struct brw_perf_query_register_prog bxt_tdl_1_b_counter_regs[18]; +static struct brw_perf_query_register_prog bxt_tdl_1_flex_regs[7]; + +static struct brw_perf_query_counter bxt_tdl_1_query_counters[41]; +static struct brw_perf_query_info bxt_tdl_1_query = { + .kind = OA_COUNTERS, + .name = "Metric set TDL_1", + .guid = "175c8092-cb25-4d1e-8dc7-b4fdd39e2d92", + .counters = bxt_tdl_1_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bxt_tdl_1_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bxt_tdl_1_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = bxt_tdl_1_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +bxt_register_tdl_1_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bxt_tdl_1_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102E0150 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E006A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x144C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x164C2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024E2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C0F0BC0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x180F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0F0302 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E2C0003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2C00F0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021A3080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041A31E5 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02148000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0414A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C150054 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06168000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08168000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A168000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3A3280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E3A0063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x063A0061 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x023A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C348000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E342000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06342000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E350140 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C350100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18360028 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C368000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5A3080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005A3280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025A0063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E548000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00548000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02542000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E550400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A552000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C550001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18560080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02568000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04568000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1993A800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900420 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45901084 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900001 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00009FFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000EFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FDFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE7F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_1__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__tdl_1__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__tdl_1__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__tdl_1__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__tdl_1__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_1__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_1__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__tdl_1__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_1__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_1__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__tdl_1__non_ps_thread02_ready_for_dispatch__read; + counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice2"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_1__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_1__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_1__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_1__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_1__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bxt__tdl_1__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_1__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__tdl_1__non_ps_thread00_ready_for_dispatch__read; + counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice0"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 120; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_1__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_1__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__tdl_1__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__tdl_1__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__tdl_1__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__tdl_1__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__tdl_1__ps_thread00_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice0"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_1__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__tdl_1__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_1__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_1__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__tdl_1__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_1__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_1__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__tdl_1__ps_thread01_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice1"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 224; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_1__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_1__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__tdl_1__ps_thread02_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice2"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 248; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_1__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_1__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_1__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_1__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__tdl_1__non_ps_thread01_ready_for_dispatch__read; + counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice1"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 288; + counter->size = sizeof(float); + } + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog bxt_tdl_2_mux_regs[58]; +static struct brw_perf_query_register_prog bxt_tdl_2_b_counter_regs[6]; +static struct brw_perf_query_register_prog bxt_tdl_2_flex_regs[7]; + +static struct brw_perf_query_counter bxt_tdl_2_query_counters[41]; +static struct brw_perf_query_info bxt_tdl_2_query = { + .kind = OA_COUNTERS, + .name = "Metric set TDL_2", + .guid = "d260f03f-b34d-4b49-a44e-436819117332", + .counters = bxt_tdl_2_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bxt_tdl_2_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bxt_tdl_2_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = bxt_tdl_2_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +bxt_register_tdl_2_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bxt_tdl_2_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141A026B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143A0173 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145A026B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E0069 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x180F6000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0F030A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2C03C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041A37E7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0414A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C150050 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08168000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A168000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003A3380 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x063A006F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x023A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00348000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06342000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A352000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C350100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02368000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C368000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025A37E7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0254A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C550005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04568000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06568000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45901080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_2__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__tdl_2__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__tdl_2__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__tdl_2__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__tdl_2__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_2__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_2__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__tdl_2__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_2__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_2__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_2__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_2__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_2__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__tdl_2__thread_header01_ready_port0__read; + counter->name = "Thread Header Ready on Slice0 Subslice1 Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 88; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__tdl_2__thread_header01_ready_port1__read; + counter->name = "Thread Header Ready on Slice0 Subslice1 Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 92; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_2__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_2__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bxt__tdl_2__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_2__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_2__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_2__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__tdl_2__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__tdl_2__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 140; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__tdl_2__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__tdl_2__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__tdl_2__thread_header02_ready_port1__read; + counter->name = "Thread Header Ready on Slice0 Subslice2 Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__tdl_2__thread_header02_ready_port0__read; + counter->name = "Thread Header Ready on Slice0 Subslice2 Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_2__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__tdl_2__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_2__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_2__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__tdl_2__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_2__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_2__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_2__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_2__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_2__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_2__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_2__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__tdl_2__thread_header00_ready_port0__read; + counter->name = "Thread Header Ready on Slice0 Subslice0 Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 256; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__tdl_2__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__tdl_2__thread_header00_ready_port1__read; + counter->name = "Thread Header Ready on Slice0 Subslice0 Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 272; + counter->size = sizeof(float); + } + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog bxt_compute_extra_mux_regs[37]; +static struct brw_perf_query_register_prog bxt_compute_extra_b_counter_regs[6]; +static struct brw_perf_query_register_prog bxt_compute_extra_flex_regs[7]; + +static struct brw_perf_query_counter bxt_compute_extra_query_counters[5]; +static struct brw_perf_query_info bxt_compute_extra_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics Extra Gen9", + .guid = "fa6ecf21-2cb8-4d0b-9308-6e4a7b4ca87a", + .counters = bxt_compute_extra_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bxt_compute_extra_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bxt_compute_extra_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = bxt_compute_extra_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +bxt_register_compute_extra_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bxt_compute_extra_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141A001F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143A001F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145A001F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E0094 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0F00E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2C0C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061A0063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06142000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C150100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C168000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x043A3180 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x023A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04348000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C350040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A368000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045A0063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04542000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C550010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08568000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900004 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00001000 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00003002 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00011010 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00050012 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00052051 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00000008 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_extra__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_extra__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_extra__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__compute_extra__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bxt__compute_extra__avg_gpu_core_frequency__max(brw); + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__compute_extra__fpu1_active_adjusted__read; + counter->name = "EU FPU1 Pipe Active including Ext Math"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing including Extended Math processing"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog bxt_gpu_busyness_mux_regs[30]; +static struct brw_perf_query_register_prog bxt_gpu_busyness_b_counter_regs[7]; + +static struct brw_perf_query_counter bxt_gpu_busyness_query_counters[8]; +static struct brw_perf_query_info bxt_gpu_busyness_query = { + .kind = OA_COUNTERS, + .name = "Gpu Rings Busyness", + .guid = "c9f5fa3a-d14f-400c-a89a-211206b00ee7", + .counters = bxt_gpu_busyness_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bxt_gpu_busyness_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bxt_gpu_busyness_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ +}; + +static void +bxt_register_gpu_busyness_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bxt_gpu_busyness_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13805800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05962C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19950016 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21C05800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07800035 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23810008 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07960025 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D960000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F960000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B934000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09948000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05950085 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11950000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B924000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D922000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F922000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0BC000A5 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900442 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00078000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00000FFF }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__gpu_busyness__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__gpu_busyness__vebox_busy__read; + counter->name = "Vebox Ring Busy"; + counter->desc = "The percentage of time when vebox command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__gpu_busyness__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__gpu_busyness__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bxt__gpu_busyness__avg_gpu_core_frequency__max(brw); + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__gpu_busyness__render_busy__read; + counter->name = "Render Ring Busy"; + counter->desc = "The percentage of time when render command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__gpu_busyness__vdbox0_busy__read; + counter->name = "Vdbox0 Ring Busy"; + counter->desc = "The percentage of time when Vdbox0 command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 36; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__gpu_busyness__blitter_busy__read; + counter->name = "Blitter Ring Busy"; + counter->desc = "The percentage of time when blitter command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = bxt__gpu_busyness__any_ring_busy__read; + counter->name = "AnyRingBusy"; + counter->desc = "The percentage of time when any command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 44; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog bxt_test_oa_mux_regs[12]; +static struct brw_perf_query_register_prog bxt_test_oa_b_counter_regs[22]; + +static struct brw_perf_query_counter bxt_test_oa_query_counters[12]; +static struct brw_perf_query_info bxt_test_oa_query = { + .kind = OA_COUNTERS, + .name = "MDAPI testing set Gen9", + .guid = "5ee72f5c-092f-421e-8b70-225f7c3e9612", + .counters = bxt_test_oa_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = bxt_test_oa_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = bxt_test_oa_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ +}; + +static void +bxt_register_test_oa_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &bxt_test_oa_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07800063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23810008 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F922000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000004 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000003 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000007 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFF7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00100082 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFEF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x001000C2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FFE7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00100001 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FFE7 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__test_oa__counter7__read; + counter->name = "TestCounter7"; + counter->desc = "HW test counter 7. Factor: 0.666"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__test_oa__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 8; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__test_oa__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__test_oa__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = bxt__test_oa__avg_gpu_core_frequency__max(brw); + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__test_oa__counter8__read; + counter->name = "TestCounter8"; + counter->desc = "HW test counter 8. Should be equal to 1."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__test_oa__counter4__read; + counter->name = "TestCounter4"; + counter->desc = "HW test counter 4. Factor: 0.333"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__test_oa__counter5__read; + counter->name = "TestCounter5"; + counter->desc = "HW test counter 5. Factor: 0.333"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__test_oa__counter6__read; + counter->name = "TestCounter6"; + counter->desc = "HW test counter 6. Factor: 0.166"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__test_oa__counter3__read; + counter->name = "TestCounter3"; + counter->desc = "HW test counter 3. Factor: 0.5"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__test_oa__counter0__read; + counter->name = "TestCounter0"; + counter->desc = "HW test counter 0. Factor: 0.0"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__test_oa__counter1__read; + counter->name = "TestCounter1"; + counter->desc = "HW test counter 1. Factor: 1.0"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = bxt__test_oa__counter2__read; + counter->name = "TestCounter2"; + counter->desc = "HW test counter 2. Factor: 1.0"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +void +brw_oa_register_queries_bxt(struct brw_context *brw) +{ + bxt_register_render_basic_counter_query(brw); + bxt_register_compute_basic_counter_query(brw); + bxt_register_render_pipe_profile_counter_query(brw); + bxt_register_memory_reads_counter_query(brw); + bxt_register_memory_writes_counter_query(brw); + bxt_register_compute_extended_counter_query(brw); + bxt_register_compute_l3_cache_counter_query(brw); + bxt_register_hdc_and_sf_counter_query(brw); + bxt_register_l3_1_counter_query(brw); + bxt_register_rasterizer_and_pixel_backend_counter_query(brw); + bxt_register_sampler_counter_query(brw); + bxt_register_tdl_1_counter_query(brw); + bxt_register_tdl_2_counter_query(brw); + bxt_register_compute_extra_counter_query(brw); + bxt_register_gpu_busyness_counter_query(brw); + bxt_register_test_oa_counter_query(brw); +} + +static struct brw_perf_query_register_prog kblgt2_render_basic_mux_regs[70]; +static struct brw_perf_query_register_prog kblgt2_render_basic_b_counter_regs[5]; +static struct brw_perf_query_register_prog kblgt2_render_basic_flex_regs[7]; + +static struct brw_perf_query_counter kblgt2_render_basic_query_counters[52]; +static struct brw_perf_query_info kblgt2_render_basic_query = { + .kind = OA_COUNTERS, + .name = "Render Metrics Basic Gen9", + .guid = "f8d677e9-ff6f-4df1-9310-0334c6efacce", + .counters = kblgt2_render_basic_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = kblgt2_render_basic_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = kblgt2_render_basic_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = kblgt2_render_basic_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +kblgt2_register_render_basic_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &kblgt2_render_basic_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C01E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12170280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12370280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11930317 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x159303DF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E0080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A6C0053 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C8400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F6600 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162C2200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00133000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08133000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00170020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08170021 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10170000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0633C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0833C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06370800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08370840 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10370000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D933031 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F933E3F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01933D00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0393073C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0593000E }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900157 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900158 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190001F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51904400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C21 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900061 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57904440 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900004 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53904444 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_basic__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__render_basic__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_basic__l3_misses__read; + counter->name = "L3 Misses"; + counter->desc = "The total number of L3 misses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_basic__gti_l3_throughput__read; + counter->name = "GTI L3 Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__render_basic__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_basic__sampler_l1_misses__read; + counter->name = "Sampler Cache Misses"; + counter->desc = "The total number of sampler cache misses in all LODs in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__render_basic__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x12) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__render_basic__sampler1_bottleneck__read; + counter->name = "Sampler 1 Bottleneck"; + counter->desc = "The percentage of time in which Sampler 1 has been slowing down the pipe when processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 52; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__render_basic__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_basic__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_basic__l3_sampler_throughput__read; + counter->name = "L3 Sampler Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_basic__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__render_basic__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 88; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_basic__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_basic__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x09) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__render_basic__sampler0_busy__read; + counter->name = "Sampler 0 Busy"; + counter->desc = "The percentage of time in which Sampler 0 has been processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 112; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x12) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__render_basic__sampler1_busy__read; + counter->name = "Sampler 1 Busy"; + counter->desc = "The percentage of time in which Sampler 1 has been processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 116; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__render_basic__samplers_busy__read; + counter->name = "Samplers Busy"; + counter->desc = "The percentage of time in which samplers have been processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 120; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_basic__gti_vf_throughput__read; + counter->name = "GTI Fixed Pipe Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between 3D Pipeline (Command Dispatch, Input Assembly and Stream Output) and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_basic__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x09) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__render_basic__sampler0_bottleneck__read; + counter->name = "Sampler 0 Bottleneck"; + counter->desc = "The percentage of time in which Sampler 0 has been slowing down the pipe when processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_basic__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_basic__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_basic__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_basic__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = kblgt2__render_basic__avg_gpu_core_frequency__max(brw); + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_basic__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_basic__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_basic__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_basic__l3_lookups__read; + counter->name = "L3 Lookup Accesses w/o IC"; + counter->desc = "The total number of L3 cache lookup accesses w/o IC."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_basic__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_basic__gti_read_throughput__read; + counter->name = "GTI Read Throughput"; + counter->desc = "The total number of GPU memory bytes read from GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__render_basic__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 232; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__render_basic__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 236; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_basic__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__render_basic__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 248; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_basic__gti_depth_throughput__read; + counter->name = "GTI Depth Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between depth caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__render_basic__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 264; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__render_basic__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 268; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_basic__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_basic__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__render_basic__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 288; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_basic__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_basic__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__render_basic__sampler_bottleneck__read; + counter->name = "Samplers Bottleneck"; + counter->desc = "The percentage of time in which samplers have been slowing down the pipe when processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 312; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_basic__gti_hdc_lookups_throughput__read; + counter->name = "GTI HDC TLB Lookup Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between GTI and HDC, when HDC is doing TLB lookups."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_basic__gti_rcc_throughput__read; + counter->name = "GTI RCC Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between render color caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 328; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_basic__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 336; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_basic__gti_write_throughput__read; + counter->name = "GTI Write Throughput"; + counter->desc = "The total number of GPU memory bytes written to GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 344; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_basic__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 352; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_basic__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 360; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_basic__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 368; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_basic__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 376; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog kblgt2_compute_basic_mux_regs[78]; +static struct brw_perf_query_register_prog kblgt2_compute_basic_b_counter_regs[5]; +static struct brw_perf_query_register_prog kblgt2_compute_basic_flex_regs[7]; + +static struct brw_perf_query_counter kblgt2_compute_basic_query_counters[39]; +static struct brw_perf_query_info kblgt2_compute_basic_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics Basic Gen9", + .guid = "e17fc42a-e614-41b6-90c4-1074841a6c77", + .counters = kblgt2_compute_basic_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = kblgt2_compute_basic_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = kblgt2_compute_basic_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = kblgt2_compute_basic_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +kblgt2_register_compute_basic_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &kblgt2_compute_basic_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F00E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124F1C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C00E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E0820 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F0900 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084F0032 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4F1891 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4F0E00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4F003C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004F0D80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024F003B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C0100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C6C000C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C0B00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0024 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C6000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C5C001B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0208 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CFB00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00BE }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19900157 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B900158 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900105 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900103 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900FFF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900821 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900802 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900802 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900422 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53904444 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_basic__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_basic__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_basic__untyped_bytes_read__read; + counter->name = "Untyped Bytes Read"; + counter->desc = "The total number of typed memory bytes read via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_basic__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_basic__typed_bytes_written__read; + counter->name = "Typed Bytes Written"; + counter->desc = "The total number of untyped memory bytes written via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_basic__fpu0_active__read; + counter->name = "EU FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_basic__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 44; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_basic__eu_avg_ipc_rate__read; + counter->name = "EU AVG IPC Rate"; + counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 2.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_basic__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_basic__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_basic__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_basic__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_basic__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_basic__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_basic__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_basic__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_basic__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = kblgt2__compute_basic__avg_gpu_core_frequency__max(brw); + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_basic__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_basic__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_basic__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_basic__gti_read_throughput__read; + counter->name = "GTI Read Throughput"; + counter->desc = "The total number of GPU memory bytes read from GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_basic__untyped_bytes_written__read; + counter->name = "Untyped Writes"; + counter->desc = "The total number of untyped memory bytes written via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_basic__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_basic__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_basic__typed_bytes_read__read; + counter->name = "Typed Bytes Read"; + counter->desc = "The total number of typed memory bytes read via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_basic__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_basic__eu_thread_occupancy__read; + counter->name = "EU Thread Occupancy"; + counter->desc = "The percentage of time in which hardware threads occupied EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_basic__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 204; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_basic__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_basic__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_basic__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_basic__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_basic__gti_write_throughput__read; + counter->name = "GTI Write Throughput"; + counter->desc = "The total number of GPU memory bytes written to GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_basic__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_basic__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_basic__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_basic__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_basic__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_basic__eu_send_active__read; + counter->name = "EU Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 288; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog kblgt2_render_pipe_profile_mux_regs[114]; +static struct brw_perf_query_register_prog kblgt2_render_pipe_profile_b_counter_regs[21]; +static struct brw_perf_query_register_prog kblgt2_render_pipe_profile_flex_regs[7]; + +static struct brw_perf_query_counter kblgt2_render_pipe_profile_query_counters[43]; +static struct brw_perf_query_info kblgt2_render_pipe_profile_query = { + .kind = OA_COUNTERS, + .name = "Render Metrics for 3D Pipeline Profile Gen9", + .guid = "d7a17a3a-ca71-40d2-a919-ace80d50633f", + .counters = kblgt2_render_pipe_profile_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = kblgt2_render_pipe_profile_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = kblgt2_render_pipe_profile_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = kblgt2_render_pipe_profile_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +kblgt2_register_render_pipe_profile_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &kblgt2_render_pipe_profile_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0E001F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10116800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178A03E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11824C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11830020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13840020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11850019 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11860007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01870C40 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17880000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020E5400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000E0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080F0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06104000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06110012 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06131000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01898000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D890100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03898000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A0075 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8A4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x138A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D81A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15818000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17818000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B820030 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07828000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D824000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F828000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05824000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D830003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0583000C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09830000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03838000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07838000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B840980 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03844D80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11840000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09850080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03850003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01850000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07860000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F860400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09870032 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01888052 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11880000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09884000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B931001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D930001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19934000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B958000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950094 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19958000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09E58000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0BE58000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E5C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0592C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B928000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D924000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F924000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11928000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1392C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09924000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01985000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07988000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09981000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B982000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D982000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F989000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05982000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190C080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900440 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C21 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900042 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900024 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900841 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900400 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFEA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFC }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007AFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F5FD }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00079FFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000F3FB }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007BF7A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F7E7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FEFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000F7CF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00077FFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000EFDF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0006FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000CFBF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0003FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x00005F7F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__render_pipe_profile__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__render_pipe_profile__vs_bottleneck__read; + counter->name = "VS Bottleneck"; + counter->desc = "The percentage of time in which vertex shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__render_pipe_profile__hi_depth_bottleneck__read; + counter->name = "Hi-Depth Bottleneck"; + counter->desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__render_pipe_profile__gs_bottleneck__read; + counter->name = "GS Bottleneck"; + counter->desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__render_pipe_profile__bc_bottleneck__read; + counter->name = "BC Bottleneck"; + counter->desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__render_pipe_profile__hs_stall__read; + counter->name = "HS Stall"; + counter->desc = "The percentage of time in which hull stall pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 60; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = kblgt2__render_pipe_profile__avg_gpu_core_frequency__max(brw); + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__render_pipe_profile__vf_bottleneck__read; + counter->name = "VF Bottleneck"; + counter->desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__render_pipe_profile__sf_bottleneck__read; + counter->name = "Strip-Fans Bottleneck"; + counter->desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__render_pipe_profile__sf_stall__read; + counter->name = "SF Stall"; + counter->desc = "The percentage of time in which strip-fans pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 140; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__render_pipe_profile__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__render_pipe_profile__hs_bottleneck__read; + counter->name = "HS Bottleneck"; + counter->desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__render_pipe_profile__cl_stall__read; + counter->name = "CL Stall"; + counter->desc = "The percentage of time in which clipper pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__render_pipe_profile__so_bottleneck__read; + counter->name = "SO Bottleneck"; + counter->desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__render_pipe_profile__ds_bottleneck__read; + counter->name = "DS Bottleneck"; + counter->desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__render_pipe_profile__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 188; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__render_pipe_profile__cl_bottleneck__read; + counter->name = "Clipper Bottleneck"; + counter->desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__render_pipe_profile__ds_stall__read; + counter->name = "DS Stall"; + counter->desc = "The percentage of time in which domain shader pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 196; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__render_pipe_profile__early_depth_bottleneck__read; + counter->name = "Early Depth Bottleneck"; + counter->desc = "The percentage of time in which early depth test pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__render_pipe_profile__so_stall__read; + counter->name = "SO Stall"; + counter->desc = "The percentage of time in which stream-output pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__render_pipe_profile__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog kblgt2_memory_reads_mux_regs[47]; +static struct brw_perf_query_register_prog kblgt2_memory_reads_b_counter_regs[32]; +static struct brw_perf_query_register_prog kblgt2_memory_reads_flex_regs[7]; + +static struct brw_perf_query_counter kblgt2_memory_reads_query_counters[41]; +static struct brw_perf_query_info kblgt2_memory_reads_query = { + .kind = OA_COUNTERS, + .name = "Memory Reads Distribution Gen9", + .guid = "57b59202-172b-477a-87de-33f85572c589", + .counters = kblgt2_memory_reads_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = kblgt2_memory_reads_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = kblgt2_memory_reads_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = kblgt2_memory_reads_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +kblgt2_register_memory_reads_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &kblgt2_memory_reads_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1381001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900064 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03811300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05811B12 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0781001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E58000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05E5C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900150 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21900151 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23900152 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25900153 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27900154 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B900156 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D900157 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F90015F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900105 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900103 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900101 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C63 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900C63 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000272C, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002728, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000271C, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002718, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F872 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_reads__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__memory_reads__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_reads__gti_l3_bank0_reads__read; + counter->name = "GtiL3Bank0Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 0 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_reads__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_reads__gti_ring_accesses__read; + counter->name = "GtiRingAccesses"; + counter->desc = "The total number of all accesses from GTI to the ring."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_reads__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_reads__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_reads__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_reads__gti_l3_bank3_reads__read; + counter->name = "GtiL3Bank3Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 3 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_reads__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_reads__gti_rs_memory_reads__read; + counter->name = "GtiRsMemoryReads"; + counter->desc = "The total number of GTI memory reads from Resource Streamer."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_reads__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_reads__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_reads__gti_hiz_memory_reads__read; + counter->name = "GtiHizMemoryReads"; + counter->desc = "The total number of GTI memory reads from Hierarchical Depth Cache (Hi-Depth Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_reads__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_reads__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = kblgt2__memory_reads__avg_gpu_core_frequency__max(brw); + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_reads__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_reads__gti_rcc_memory_reads__read; + counter->name = "GtiRccMemoryReads"; + counter->desc = "The total number of GTI memory reads from Render Color Cache (Render Color Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_reads__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_reads__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_reads__gti_l3_bank1_reads__read; + counter->name = "GtiL3Bank1Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 1 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__memory_reads__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_reads__gti_cmd_streamer_memory_reads__read; + counter->name = "GtiCmdStreamerMemoryReads"; + counter->desc = "The total number of GTI memory reads from Command Streamer."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_reads__gti_l3_bank2_reads__read; + counter->name = "GtiL3Bank2Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 2 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_reads__gti_memory_reads__read; + counter->name = "GtiMemoryReads"; + counter->desc = "The total number of GTI memory reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_reads__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_reads__gti_rcz_memory_reads__read; + counter->name = "GtiRczMemoryReads"; + counter->desc = "The total number of GTI memory reads from Render Depth Cache (Render Depth Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_reads__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_reads__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__memory_reads__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 232; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_reads__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_reads__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_reads__gti_msc_memory_reads__read; + counter->name = "GtiMscMemoryReads"; + counter->desc = "The total number of GTI memory reads from Multisampling Color Cache (Multisampling Color Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_reads__gti_vf_memory_reads__read; + counter->name = "GtiVfMemoryReads"; + counter->desc = "The total number of GTI memory reads from Vertex Fetch."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_reads__gti_stc_memory_reads__read; + counter->name = "GtiStcMemoryReads"; + counter->desc = "The total number of GTI memory reads from Stencil Cache (Stencil Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_reads__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_reads__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_reads__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_reads__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_reads__gti_l3_reads__read; + counter->name = "GtiL3Reads"; + counter->desc = "The total number of GTI memory reads from L3 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_reads__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog kblgt2_memory_writes_mux_regs[47]; +static struct brw_perf_query_register_prog kblgt2_memory_writes_b_counter_regs[32]; +static struct brw_perf_query_register_prog kblgt2_memory_writes_flex_regs[7]; + +static struct brw_perf_query_counter kblgt2_memory_writes_query_counters[41]; +static struct brw_perf_query_info kblgt2_memory_writes_query = { + .kind = OA_COUNTERS, + .name = "Memory Writes Distribution Gen9", + .guid = "3addf8ef-8e9b-40f5-a448-3dbb5d5128b0", + .counters = kblgt2_memory_writes_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = kblgt2_memory_writes_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = kblgt2_memory_writes_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = kblgt2_memory_writes_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +kblgt2_register_memory_writes_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &kblgt2_memory_writes_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1381001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F901000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03811300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05811B12 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0781001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E58000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05E5C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900160 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21900161 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23900162 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25900163 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27900164 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900165 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B900166 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D900167 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F900150 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900105 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900103 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900101 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C63 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900C63 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000272C, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002728, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000271C, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002718, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F822 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_writes__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__memory_writes__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_writes__gti_memory_writes__read; + counter->name = "GtiMemoryWrites"; + counter->desc = "The total number of GTI memory writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_writes__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_writes__gti_ring_accesses__read; + counter->name = "GtiRingAccesses"; + counter->desc = "The total number of all GTI accesses to the ring."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_writes__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_writes__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_writes__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_writes__gti_msc_memory_writes__read; + counter->name = "GtiMscMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Multisampling Color Cache (Multisampling Color Cache invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_writes__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_writes__gti_cmd_streamer_memory_writes__read; + counter->name = "GtiCmdStreamerMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Command Streamer."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_writes__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_writes__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_writes__gti_l3_bank0_writes__read; + counter->name = "GtiL3Bank0Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 0 (L3 Bank 0 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_writes__gti_l3_bank1_writes__read; + counter->name = "GtiL3Bank1Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 1 (L3 Bank 1 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_writes__gti_l3_bank2_writes__read; + counter->name = "GtiL3Bank2Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 2 (L3 Bank 2 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_writes__gti_l3_bank3_writes__read; + counter->name = "GtiL3Bank3Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 3 (L3 Bank 3 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_writes__gti_l3_writes__read; + counter->name = "GtiL3Writes"; + counter->desc = "The total number of GTI memory writes from L3 (L3 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_writes__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_writes__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = kblgt2__memory_writes__avg_gpu_core_frequency__max(brw); + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_writes__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_writes__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_writes__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_writes__gti_rcc_memory_writes__read; + counter->name = "GtiRccMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Render Color Cache (Render Color Cache invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_writes__gti_so_memory_writes__read; + counter->name = "GtiSoMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Stream Output."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__memory_writes__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_writes__gti_stc_memory_writes__read; + counter->name = "GtiStcMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Stencil Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_writes__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_writes__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_writes__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__memory_writes__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 240; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_writes__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_writes__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_writes__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_writes__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_writes__gti_rcz_memory_writes__read; + counter->name = "GtiRczMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Render Depth Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_writes__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_writes__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_writes__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_writes__gti_hiz_memory_writes__read; + counter->name = "GtiHizMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Hierarchical Depth Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__memory_writes__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog kblgt2_compute_extended_mux_regs[72]; +static struct brw_perf_query_register_prog kblgt2_compute_extended_b_counter_regs[21]; +static struct brw_perf_query_register_prog kblgt2_compute_extended_flex_regs[7]; + +static struct brw_perf_query_counter kblgt2_compute_extended_query_counters[38]; +static struct brw_perf_query_info kblgt2_compute_extended_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics Extended Gen9", + .guid = "4af0400a-81c3-47db-a6b6-deddbd75680e", + .counters = kblgt2_compute_extended_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = kblgt2_compute_extended_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = kblgt2_compute_extended_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = kblgt2_compute_extended_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +kblgt2_register_compute_extended_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &kblgt2_compute_extended_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C00E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8160 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C0120 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x184E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4EAAA0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C0B01 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C000C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001C0041 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061C4200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081C4443 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1C4645 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1C7647 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041C7357 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0030 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4CAA2A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C02AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5515 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CAA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11907FFF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900802 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FC2A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FC6A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007FC92 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007FCA2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FC32 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FC9A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007FE6A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007FE7A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000BF00 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_extended__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_extended__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_extended__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_extended__fpu0_active__read; + counter->name = "EU FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_extended__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_extended__eu_avg_ipc_rate__read; + counter->name = "EU AVG IPC Rate"; + counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 2.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_extended__typed_writes0__read; + counter->name = "Typed Writes 0"; + counter->desc = "The subslice 0 typed writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_extended__eu_typed_atomics0__read; + counter->name = "EuTypedAtomics0"; + counter->desc = "The subslice 0 EU Typed Atomics subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_extended__typed_atomics0__read; + counter->name = "Typed Atomics 0"; + counter->desc = "The subslice 0 typed atomics."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_extended__typed_atomics_per_cache_line__read; + counter->name = "TypedAtomicsPerCacheLine"; + counter->desc = "The ratio of EU typed atomics requests to L3 cache line writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_extended__eu_untyped_reads0__read; + counter->name = "EuUntypedReads0"; + counter->desc = "The subslice 0 EU Untyped Reads subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_extended__untyped_writes0__read; + counter->name = "Untyped Writes 0"; + counter->desc = "The subslice 0 untyped writes (including SLM writes)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_extended__eu_untyped_atomics0__read; + counter->name = "EuUntypedAtomics0"; + counter->desc = "The subslice 0 EU Untyped Atomics subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_extended__eu_untyped_writes0__read; + counter->name = "EuUntypedWrites0"; + counter->desc = "The subslice 0 EU Untyped Writes subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_extended__eu_a64_untyped_writes0__read; + counter->name = "EuA64UntypedWrites0"; + counter->desc = "The subslice 0 EU A64 Untyped Writes subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_extended__untyped_writes_per_cache_line__read; + counter->name = "UntypedWritesPerCacheLine"; + counter->desc = "The ratio of EU untyped write requests to L3 cache line writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_extended__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_extended__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_extended__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_extended__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = kblgt2__compute_extended__avg_gpu_core_frequency__max(brw); + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_extended__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_extended__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_extended__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_extended__eu_typed_writes0__read; + counter->name = "EuTypedWrites0"; + counter->desc = "The subslice 0 EU Typed Writes subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_extended__typed_writes_per_cache_line__read; + counter->name = "TypedWritesPerCacheLine"; + counter->desc = "The ratio of EU typed write requests to L3 cache line writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_extended__typed_reads0__read; + counter->name = "Typed Reads 0"; + counter->desc = "The subslice 0 typed reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_extended__untyped_reads0__read; + counter->name = "Untyped Reads 0"; + counter->desc = "The subslice 0 untyped reads (including SLM reads)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_extended__eu_a64_untyped_reads0__read; + counter->name = "EuA64UntypedReads0"; + counter->desc = "The subslice 0 EU A64 Untyped Reads subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_extended__eu_thread_occupancy__read; + counter->name = "EU Thread Occupancy"; + counter->desc = "The percentage of time in which hardware threads occupied EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 208; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_extended__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 212; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_extended__eu_typed_reads0__read; + counter->name = "EuTypedReads0"; + counter->desc = "The subslice 0 EU Typed Reads subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_extended__untyped_reads_per_cache_line__read; + counter->name = "UntypedReadsPerCacheLine"; + counter->desc = "The ratio of EU untyped read requests to L3 cache line reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_extended__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_extended__typed_reads_per_cache_line__read; + counter->name = "TypedReadsPerCacheLine"; + counter->desc = "The ratio of EU typed read requests to L3 cache line reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_extended__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_extended__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_extended__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_extended__eu_send_active__read; + counter->name = "EU Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 272; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog kblgt2_compute_l3_cache_mux_regs[60]; +static struct brw_perf_query_register_prog kblgt2_compute_l3_cache_b_counter_regs[13]; +static struct brw_perf_query_register_prog kblgt2_compute_l3_cache_flex_regs[7]; + +static struct brw_perf_query_counter kblgt2_compute_l3_cache_query_counters[54]; +static struct brw_perf_query_info kblgt2_compute_l3_cache_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics L3 Cache Gen9", + .guid = "0e22f995-79ca-4f67-83ab-e9d9772488d8", + .counters = kblgt2_compute_l3_cache_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = kblgt2_compute_l3_cache_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = kblgt2_compute_l3_cache_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = kblgt2_compute_l3_cache_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +kblgt2_register_compute_l3_cache_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &kblgt2_compute_l3_cache_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C0760 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1593001E }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x184E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E8020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0051 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C5C5D }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C5E5F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1CE000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0030 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C2A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F1500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0140 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162C0A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03933300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05930032 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900157 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900158 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190030F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900021 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53904444 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FEFE }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FEFD }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FBEF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FBDF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00101100 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00201200 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00301300 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00401400 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_l3_cache__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__l3_bank03_accesses__read; + counter->name = "L3 Bank 03 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 03."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__l3_accesses__read; + counter->name = "L3 Accesses"; + counter->desc = "The total number of L3 accesses from all entities."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_l3_cache__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__l3_sampler_throughput__read; + counter->name = "L3 Sampler Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_l3_cache__fpu0_active__read; + counter->name = "EU FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_l3_cache__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 52; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_l3_cache__eu_avg_ipc_rate__read; + counter->name = "EU AVG IPC Rate"; + counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 2.0; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_l3_cache__eu_binary_fpu0_instruction__read; + counter->name = "EU FPU0 Binary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 60; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_l3_cache__eu_hybrid_fpu0_instruction__read; + counter->name = "EU FPU0 Hybrid Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 104; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__l3_misses__read; + counter->name = "L3 Misses"; + counter->desc = "The total number of L3 misses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__l3_bank00_accesses__read; + counter->name = "L3 Bank 00 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 00."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_l3_cache__eu_move_fpu0_instruction__read; + counter->name = "EU FPU0 Move Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_l3_cache__eu_hybrid_fpu1_instruction__read; + counter->name = "EU FPU1 Hybrid Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = kblgt2__compute_l3_cache__avg_gpu_core_frequency__max(brw); + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__gti_read_throughput__read; + counter->name = "GTI Read Throughput"; + counter->desc = "The total number of GPU memory bytes read from GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__gti_l3_throughput__read; + counter->name = "GTI L3 Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__l3_bank00_ic_accesses__read; + counter->name = "L3 Bank 00 IC Accesses"; + counter->desc = "The total number of accesses to L3 Bank 00 from IC cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + } + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__l3_bank00_ic_hits__read; + counter->name = "L3 Bank 00 IC Hits"; + counter->desc = "The total number of hits in L3 Bank 00 from IC cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__sampler_accesses__read; + counter->name = "Sampler Accesses"; + counter->desc = "The total number of messages send to samplers."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__l3_bank01_accesses__read; + counter->name = "L3 Bank 01 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 01."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_l3_cache__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 256; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_l3_cache__eu_ternary_fpu0_instruction__read; + counter->name = "EU FPU0 Ternary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 260; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_l3_cache__eu_move_fpu1_instruction__read; + counter->name = "EU FPU1 Move Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 296; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_l3_cache__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 300; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__l3_bank02_accesses__read; + counter->name = "L3 Bank 02 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 02."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 328; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__l3_total_throughput__read; + counter->name = "L3 Total Throughput"; + counter->desc = "The total number of GPU memory bytes transferred via L3."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 336; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__gti_write_throughput__read; + counter->name = "GTI Write Throughput"; + counter->desc = "The total number of GPU memory bytes written to GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 344; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 352; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 360; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_l3_cache__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 368; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_l3_cache__eu_binary_fpu1_instruction__read; + counter->name = "EU FPU1 Binary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 376; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_l3_cache__eu_ternary_fpu1_instruction__read; + counter->name = "EU FPU1 Ternary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 380; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_l3_cache__eu_send_active__read; + counter->name = "EU Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 384; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog kblgt2_hdc_and_sf_mux_regs[54]; +static struct brw_perf_query_register_prog kblgt2_hdc_and_sf_b_counter_regs[8]; +static struct brw_perf_query_register_prog kblgt2_hdc_and_sf_flex_regs[7]; + +static struct brw_perf_query_counter kblgt2_hdc_and_sf_query_counters[39]; +static struct brw_perf_query_info kblgt2_hdc_and_sf_query = { + .kind = OA_COUNTERS, + .name = "Metric set HDCAndSF", + .guid = "bc2a00f7-cb8a-4ff2-8ad0-e241dad16937", + .counters = kblgt2_hdc_and_sf_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = kblgt2_hdc_and_sf_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = kblgt2_hdc_and_sf_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = kblgt2_hdc_and_sf_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +kblgt2_register_hdc_and_sf_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &kblgt2_hdc_and_sf_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F0232 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124F4640 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0232 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11834400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004F1880 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024F08BB }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044F001B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C0100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C000B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C1800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x165C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x185C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C00A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F828000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8305C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09830000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07830000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13928000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F988000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FDFF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__hdc_and_sf__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__hdc_and_sf__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__hdc_and_sf__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__hdc_and_sf__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__hdc_and_sf__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__hdc_and_sf__poly_data_ready__read; + counter->name = "Polygon Data Ready"; + counter->desc = "The percentage of time in which geometry pipeline output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = kblgt2__hdc_and_sf__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read; + counter->name = "HDC stalled by L3 (s0.ss1)"; + counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss1)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 120; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read; + counter->name = "HDC stalled by L3 (s0.ss2)"; + counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss2)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__hdc_and_sf__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__hdc_and_sf__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__hdc_and_sf__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__hdc_and_sf__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 164; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__hdc_and_sf__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__hdc_and_sf__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read; + counter->name = "HDC stalled by L3 (s0.ss0)"; + counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss0)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 264; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__hdc_and_sf__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog kblgt2_l3_1_mux_regs[71]; +static struct brw_perf_query_register_prog kblgt2_l3_1_b_counter_regs[22]; +static struct brw_perf_query_register_prog kblgt2_l3_1_flex_regs[7]; + +static struct brw_perf_query_counter kblgt2_l3_1_query_counters[39]; +static struct brw_perf_query_info kblgt2_l3_1_query = { + .kind = OA_COUNTERS, + .name = "Metric set L3_1", + .guid = "d2bbe790-f058-42d9-81c6-cdedcf655bc2", + .counters = kblgt2_l3_1_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = kblgt2_l3_1_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = kblgt2_l3_1_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = kblgt2_l3_1_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +kblgt2_register_l3_1_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &kblgt2_l3_1_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C7B40 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C0020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A603444 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A613400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4EA800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C6C5327 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C5425 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C2A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C285B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C005C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C003C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10600000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04600000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C610044 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10610000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06610000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C02A8 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0154 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FFC0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900420 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900021 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900421 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00014002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000C3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00010002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000C7FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00004002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000D3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100700 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FF1F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00001402 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FC3F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00001002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FC7F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00000402 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FD3F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_1__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_1__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_1__l30_bank1_active__read; + counter->name = "Slice0 L3 Bank1 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank1 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_1__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_1__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_1__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_1__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_1__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_1__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_1__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_1__l30_bank1_stalled__read; + counter->name = "Slice0 L3 Bank1 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank1 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_1__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_1__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_1__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_1__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_1__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_1__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = kblgt2__l3_1__avg_gpu_core_frequency__max(brw); + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_1__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_1__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_1__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_1__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_1__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_1__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_1__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_1__l30_bank0_active__read; + counter->name = "Slice0 L3 Bank0 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank0 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_1__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_1__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_1__l30_bank0_stalled__read; + counter->name = "Slice0 L3 Bank0 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank0 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 180; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_1__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_1__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_1__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_1__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_1__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_1__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_1__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_1__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_1__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_1__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_1__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog kblgt2_l3_2_mux_regs[44]; +static struct brw_perf_query_register_prog kblgt2_l3_2_b_counter_regs[14]; +static struct brw_perf_query_register_prog kblgt2_l3_2_flex_regs[7]; + +static struct brw_perf_query_counter kblgt2_l3_2_query_counters[37]; +static struct brw_perf_query_info kblgt2_l3_2_query = { + .kind = OA_COUNTERS, + .name = "Metric set L3_2", + .guid = "2f8e32e4-5956-46e2-af31-c8ea95887332", + .counters = kblgt2_l3_2_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = kblgt2_l3_2_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = kblgt2_l3_2_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = kblgt2_l3_2_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +kblgt2_register_l3_2_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &kblgt2_l3_2_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C02E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146C0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A623400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C3324 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C3422 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06614000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C620044 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10620000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06620000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190F800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00028002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x000087FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00020002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00008FFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00008002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000A7FF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_2__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_2__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_2__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_2__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_2__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_2__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_2__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_2__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_2__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_2__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_2__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_2__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_2__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_2__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_2__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = kblgt2__l3_2__avg_gpu_core_frequency__max(brw); + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_2__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_2__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_2__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_2__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 128; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_2__l30_bank2_stalled__read; + counter->name = "Slice0 L3 Bank2 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank2 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 132; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_2__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_2__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 140; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_2__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_2__l30_bank2_active__read; + counter->name = "Slice0 L3 Bank2 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank2 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_2__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_2__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_2__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_2__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_2__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 184; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_2__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_2__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_2__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_2__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_2__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_2__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_2__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_2__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog kblgt2_l3_3_mux_regs[43]; +static struct brw_perf_query_register_prog kblgt2_l3_3_b_counter_regs[14]; +static struct brw_perf_query_register_prog kblgt2_l3_3_flex_regs[7]; + +static struct brw_perf_query_counter kblgt2_l3_3_query_counters[37]; +static struct brw_perf_query_info kblgt2_l3_3_query = { + .kind = OA_COUNTERS, + .name = "Metric set L3_3", + .guid = "ca046aad-b5fb-4101-adce-6473ee6e5b14", + .counters = kblgt2_l3_3_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = kblgt2_l3_3_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = kblgt2_l3_3_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = kblgt2_l3_3_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +kblgt2_register_l3_3_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &kblgt2_l3_3_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C4E80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A633400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C3321 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C342F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C1800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06604000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C630044 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10630000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06630000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C00AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190F800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00028002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x000087FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00020002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00008FFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00008002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000A7FF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_3__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_3__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_3__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_3__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_3__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_3__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_3__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_3__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_3__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_3__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_3__l30_bank3_stalled__read; + counter->name = "Slice0 L3 Bank3 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank3 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_3__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_3__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_3__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_3__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_3__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = kblgt2__l3_3__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_3__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_3__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_3__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_3__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_3__l30_bank3_active__read; + counter->name = "Slice0 L3 Bank3 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank3 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 140; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_3__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_3__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_3__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_3__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_3__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_3__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_3__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__l3_3__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_3__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_3__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_3__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_3__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_3__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_3__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_3__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__l3_3__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog kblgt2_rasterizer_and_pixel_backend_mux_regs[31]; +static struct brw_perf_query_register_prog kblgt2_rasterizer_and_pixel_backend_b_counter_regs[10]; +static struct brw_perf_query_register_prog kblgt2_rasterizer_and_pixel_backend_flex_regs[7]; + +static struct brw_perf_query_counter kblgt2_rasterizer_and_pixel_backend_query_counters[40]; +static struct brw_perf_query_info kblgt2_rasterizer_and_pixel_backend_query = { + .kind = OA_COUNTERS, + .name = "Metric set RasterizerAndPixelBackend", + .guid = "605f388f-24bb-455c-88e3-8d57ae0d7e9f", + .counters = kblgt2_rasterizer_and_pixel_backend_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = kblgt2_rasterizer_and_pixel_backend_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = kblgt2_rasterizer_and_pixel_backend_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = kblgt2_rasterizer_and_pixel_backend_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +kblgt2_register_rasterizer_and_pixel_backend_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &kblgt2_rasterizer_and_pixel_backend_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102F3800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x144D0500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x120D03C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x140D03CF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0004 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F0480 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0090 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064D0027 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004D0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D0D40 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020D803F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040D8023 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100D0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020F0010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0050 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41901400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43901485 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000EFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00006000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F3FF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__rasterizer_and_pixel_backend__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__rasterizer_and_pixel_backend__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__rasterizer_and_pixel_backend__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__rasterizer_and_pixel_backend__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__rasterizer_and_pixel_backend__pixel_values0_ready__read; + counter->name = "Slice0 Pixel Values Ready"; + counter->desc = "The percentage of time in which slice0 pixel values are ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = kblgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__rasterizer_and_pixel_backend__rasterizer0_input_available__read; + counter->name = "Slice0 Rasterizer Input Available"; + counter->desc = "The percentage of time in which slice0 rasterizer input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 128; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__rasterizer_and_pixel_backend__pixel_data0_ready__read; + counter->name = "Slice0 Post-EarlyZ Pixel Data Ready"; + counter->desc = "The percentage of time in which slice0 post-EarlyZ pixel data is ready (after early Z tests have been applied)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 132; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__rasterizer_and_pixel_backend__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__rasterizer_and_pixel_backend__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__rasterizer_and_pixel_backend__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__rasterizer_and_pixel_backend__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__rasterizer_and_pixel_backend__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__rasterizer_and_pixel_backend__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__rasterizer_and_pixel_backend__rasterizer0_output_ready__read; + counter->name = "Slice0 Rasterizer Output Ready"; + counter->desc = "The percentage of time in which slice0 rasterizer output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 196; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__rasterizer_and_pixel_backend__ps_output0_available__read; + counter->name = "Slice0 PS Output Available"; + counter->desc = "The percentage of time in which slice0 PS output is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 256; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__rasterizer_and_pixel_backend__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog kblgt2_sampler_mux_regs[69]; +static struct brw_perf_query_register_prog kblgt2_sampler_b_counter_regs[12]; +static struct brw_perf_query_register_prog kblgt2_sampler_flex_regs[7]; + +static struct brw_perf_query_counter kblgt2_sampler_query_counters[41]; +static struct brw_perf_query_info kblgt2_sampler_query = { + .kind = OA_COUNTERS, + .name = "Metric set Sampler", + .guid = "31dd157c-bf4e-4bab-bf2b-f5c8174af1af", + .counters = kblgt2_sampler_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = kblgt2_sampler_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = kblgt2_sampler_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = kblgt2_sampler_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +kblgt2_register_sampler_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &kblgt2_sampler_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14152C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16150005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121600A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14352C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16350005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123600A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14552C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16550005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125600A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062F6000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0050 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0350 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FB000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F00DA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C0028 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C138000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E132000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0413C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C140018 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C157000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E150078 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10150000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04162180 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02160000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04174000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0233A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04333000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14348000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16348000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02357870 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10350000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04360043 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02360000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04371000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E538000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00538000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06533000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C540020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12548000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E557000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00557800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10550000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06560043 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02560000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06571000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FF80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900060 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900060 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x70800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0000C000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000E7FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00003000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F9FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000C00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE7F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__sampler__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__sampler__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__sampler__sampler02_input_available__read; + counter->name = "Slice0 Subslice2 Input Available"; + counter->desc = "The percentage of time in which slice0 subslice2 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__sampler__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__sampler__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__sampler__sampler00_input_available__read; + counter->name = "Slice0 Subslice0 Input Available"; + counter->desc = "The percentage of time in which slice0 subslice0 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__sampler__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 28; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__sampler__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__sampler__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__sampler__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__sampler__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__sampler__sampler02_output_ready__read; + counter->name = "Slice0 Subslice2 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice0 subslice2 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__sampler__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__sampler__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__sampler__sampler01_input_available__read; + counter->name = "Slice0 Subslice1 Input Available"; + counter->desc = "The percentage of time in which slice0 subslice1 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 88; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__sampler__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__sampler__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__sampler__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__sampler__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = kblgt2__sampler__avg_gpu_core_frequency__max(brw); + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__sampler__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__sampler__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__sampler__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__sampler__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__sampler__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__sampler__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__sampler__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 164; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__sampler__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__sampler__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__sampler__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__sampler__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__sampler__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__sampler__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__sampler__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__sampler__sampler00_output_ready__read; + counter->name = "Slice0 Subslice0 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice0 subslice0 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 224; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__sampler__sampler01_output_ready__read; + counter->name = "Slice0 Subslice1 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice0 subslice1 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 228; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__sampler__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__sampler__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__sampler__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__sampler__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__sampler__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__sampler__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog kblgt2_tdl_1_mux_regs[68]; +static struct brw_perf_query_register_prog kblgt2_tdl_1_b_counter_regs[18]; +static struct brw_perf_query_register_prog kblgt2_tdl_1_flex_regs[7]; + +static struct brw_perf_query_counter kblgt2_tdl_1_query_counters[41]; +static struct brw_perf_query_info kblgt2_tdl_1_query = { + .kind = OA_COUNTERS, + .name = "Metric set TDL_1", + .guid = "105db928-5542-466b-9128-e1f3c91426cb", + .counters = kblgt2_tdl_1_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = kblgt2_tdl_1_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = kblgt2_tdl_1_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = kblgt2_tdl_1_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +kblgt2_register_tdl_1_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &kblgt2_tdl_1_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12120000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12320000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12520000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F3000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F03A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FF000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0095 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02108000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0410C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02118000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0411C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02121880 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041219B5 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02134000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04135000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C308000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E304000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06304000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C318000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E314000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06314000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C321A80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E320033 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06320031 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00320000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C334000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E331000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06331000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E508000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00508000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02504000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E518000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00518000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02514000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E521880 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00521A80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02520033 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E534000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00534000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02531000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FF80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900062 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00009FFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000EFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FDFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE7F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_1__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__tdl_1__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__tdl_1__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__tdl_1__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__tdl_1__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_1__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_1__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__tdl_1__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_1__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_1__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__tdl_1__non_ps_thread02_ready_for_dispatch__read; + counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice2"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_1__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_1__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_1__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_1__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_1__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = kblgt2__tdl_1__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_1__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__tdl_1__non_ps_thread00_ready_for_dispatch__read; + counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice0"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 120; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_1__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_1__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__tdl_1__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__tdl_1__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__tdl_1__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__tdl_1__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__tdl_1__ps_thread00_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice0"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_1__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__tdl_1__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_1__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_1__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__tdl_1__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_1__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_1__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__tdl_1__ps_thread01_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice1"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 224; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_1__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_1__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__tdl_1__ps_thread02_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice2"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 248; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_1__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_1__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_1__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_1__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__tdl_1__non_ps_thread01_ready_for_dispatch__read; + counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice1"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 288; + counter->size = sizeof(float); + } + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog kblgt2_tdl_2_mux_regs[42]; +static struct brw_perf_query_register_prog kblgt2_tdl_2_b_counter_regs[6]; +static struct brw_perf_query_register_prog kblgt2_tdl_2_flex_regs[7]; + +static struct brw_perf_query_counter kblgt2_tdl_2_query_counters[41]; +static struct brw_perf_query_info kblgt2_tdl_2_query = { + .kind = OA_COUNTERS, + .name = "Metric set TDL_2", + .guid = "03db94d2-b37f-4c58-a791-0d2067b013bb", + .counters = kblgt2_tdl_2_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = kblgt2_tdl_2_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = kblgt2_tdl_2_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = kblgt2_tdl_2_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +kblgt2_register_tdl_2_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &kblgt2_tdl_2_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12124D60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12322E60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12524D60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F3000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0014 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FE000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0097 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0410C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0411C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04121FB7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04135000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00308000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06304000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00318000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06314000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00321B80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0632003F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00334000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06331000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0250C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0251C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02521FB7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00520000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02535000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_2__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__tdl_2__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__tdl_2__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__tdl_2__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__tdl_2__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_2__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_2__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__tdl_2__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_2__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_2__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_2__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_2__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_2__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__tdl_2__thread_header01_ready_port0__read; + counter->name = "Thread Header Ready on Slice0 Subslice1 Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 88; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__tdl_2__thread_header01_ready_port1__read; + counter->name = "Thread Header Ready on Slice0 Subslice1 Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 92; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_2__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_2__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = kblgt2__tdl_2__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_2__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_2__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_2__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__tdl_2__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__tdl_2__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 140; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__tdl_2__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__tdl_2__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__tdl_2__thread_header02_ready_port1__read; + counter->name = "Thread Header Ready on Slice0 Subslice2 Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__tdl_2__thread_header02_ready_port0__read; + counter->name = "Thread Header Ready on Slice0 Subslice2 Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_2__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__tdl_2__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_2__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_2__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__tdl_2__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_2__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_2__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_2__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_2__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_2__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_2__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_2__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__tdl_2__thread_header00_ready_port0__read; + counter->name = "Thread Header Ready on Slice0 Subslice0 Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 256; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__tdl_2__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__tdl_2__thread_header00_ready_port1__read; + counter->name = "Thread Header Ready on Slice0 Subslice0 Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 272; + counter->size = sizeof(float); + } + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog kblgt2_compute_extra_mux_regs[32]; +static struct brw_perf_query_register_prog kblgt2_compute_extra_b_counter_regs[6]; +static struct brw_perf_query_register_prog kblgt2_compute_extra_flex_regs[7]; + +static struct brw_perf_query_counter kblgt2_compute_extra_query_counters[5]; +static struct brw_perf_query_info kblgt2_compute_extra_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics Extra Gen9", + .guid = "aa7a3fb9-22fb-43ff-a32d-0ab6c13bbd16", + .counters = kblgt2_compute_extra_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = kblgt2_compute_extra_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = kblgt2_compute_extra_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = kblgt2_compute_extra_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +kblgt2_register_compute_extra_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &kblgt2_compute_extra_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121203E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123203E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125203E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F006C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06104000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06114000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06120033 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06131000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04308000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04318000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04321980 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00320000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04334000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04504000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04514000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04520033 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00520000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04531000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190E000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00001000 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00003002 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00011010 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00050012 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00052051 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00000008 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_extra__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_extra__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_extra__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__compute_extra__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = kblgt2__compute_extra__avg_gpu_core_frequency__max(brw); + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__compute_extra__fpu1_active_adjusted__read; + counter->name = "EU FPU1 Pipe Active including Ext Math"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing including Extended Math processing"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog kblgt2_vme_pipe_mux_regs[62]; +static struct brw_perf_query_register_prog kblgt2_vme_pipe_b_counter_regs[17]; +static struct brw_perf_query_register_prog kblgt2_vme_pipe_flex_regs[2]; + +static struct brw_perf_query_counter kblgt2_vme_pipe_query_counters[10]; +static struct brw_perf_query_info kblgt2_vme_pipe_query = { + .kind = OA_COUNTERS, + .name = "Media Vme Pipe Gen9", + .guid = "398a4268-ef6f-4ffc-b55f-3c7b5363ce61", + .counters = kblgt2_vme_pipe_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = kblgt2_vme_pipe_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = kblgt2_vme_pipe_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = kblgt2_vme_pipe_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +kblgt2_register_vme_pipe_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &kblgt2_vme_pipe_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141A5800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161A00C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12180240 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14180002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143A5800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x163A00C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12380240 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14380002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F3000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C1500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F9500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162C0A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04193000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081A28C1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00133000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0613C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0813F000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00172000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06178000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0817A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00180037 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06180940 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08180000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02180000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04183000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06393000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3A28C1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A33F000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C33F000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A37A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C37A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A380977 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08380000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04380000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06383000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x119000FF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47901000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900844 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100030 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF9 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FFFC }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FFF3 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100180 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFCF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FF3F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00008003 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__vme_pipe__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__vme_pipe__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__vme_pipe__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__vme_pipe__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__vme_pipe__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = kblgt2__vme_pipe__avg_gpu_core_frequency__max(brw); + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__vme_pipe__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__vme_pipe__eu_thread_occupancy__read; + counter->name = "EU Thread Occupancy"; + counter->desc = "The percentage of time in which hardware threads occupied EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__vme_pipe__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 44; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__vme_pipe__vme_busy__read; + counter->name = "VME Busy"; + counter->desc = "The percentage of time in which VME (IME or CRE) was actively processing data."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__vme_pipe__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 52; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog kblgt2_gpu_busyness_mux_regs[34]; +static struct brw_perf_query_register_prog kblgt2_gpu_busyness_b_counter_regs[7]; + +static struct brw_perf_query_counter kblgt2_gpu_busyness_query_counters[8]; +static struct brw_perf_query_info kblgt2_gpu_busyness_query = { + .kind = OA_COUNTERS, + .name = "Gpu Rings Busyness", + .guid = "6c66fe6e-2988-454a-bfae-7fca3bbcbec2", + .counters = kblgt2_gpu_busyness_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = kblgt2_gpu_busyness_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = kblgt2_gpu_busyness_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ +}; + +static void +kblgt2_register_gpu_busyness_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &kblgt2_gpu_busyness_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13805800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05962C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19950016 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19C05800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07800035 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07960025 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21960000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B964000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930062 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17948000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B940008 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05950075 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09924000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05982000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09978000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05C08500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25C00000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1BC00000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0BC54000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900C60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00078000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00000FFF }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__gpu_busyness__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__gpu_busyness__vebox_busy__read; + counter->name = "Vebox Ring Busy"; + counter->desc = "The percentage of time when vebox command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__gpu_busyness__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__gpu_busyness__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = kblgt2__gpu_busyness__avg_gpu_core_frequency__max(brw); + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__gpu_busyness__render_busy__read; + counter->name = "Render Ring Busy"; + counter->desc = "The percentage of time when render command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__gpu_busyness__vdbox0_busy__read; + counter->name = "Vdbox0 Ring Busy"; + counter->desc = "The percentage of time when Vdbox0 command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 36; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__gpu_busyness__blitter_busy__read; + counter->name = "Blitter Ring Busy"; + counter->desc = "The percentage of time when blitter command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt2__gpu_busyness__any_ring_busy__read; + counter->name = "AnyRingBusy"; + counter->desc = "The percentage of time when any command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 44; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog kblgt2_test_oa_mux_regs[13]; +static struct brw_perf_query_register_prog kblgt2_test_oa_b_counter_regs[22]; + +static struct brw_perf_query_counter kblgt2_test_oa_query_counters[12]; +static struct brw_perf_query_info kblgt2_test_oa_query = { + .kind = OA_COUNTERS, + .name = "MDAPI testing set Gen9.5", + .guid = "baa3c7e4-52b6-4b85-801e-465a94b746dd", + .counters = kblgt2_test_oa_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = kblgt2_test_oa_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = kblgt2_test_oa_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ +}; + +static void +kblgt2_register_test_oa_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &kblgt2_test_oa_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07810013 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000004 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000003 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000007 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFF7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00100082 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFEF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x001000C2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FFE7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00100001 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FFE7 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__test_oa__counter7__read; + counter->name = "TestCounter7"; + counter->desc = "HW test counter 7. Factor: 0.666"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__test_oa__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 8; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__test_oa__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__test_oa__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = kblgt2__test_oa__avg_gpu_core_frequency__max(brw); + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__test_oa__counter8__read; + counter->name = "TestCounter8"; + counter->desc = "HW test counter 8. Should be equal to 1."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__test_oa__counter4__read; + counter->name = "TestCounter4"; + counter->desc = "HW test counter 4. Factor: 0.333"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__test_oa__counter5__read; + counter->name = "TestCounter5"; + counter->desc = "HW test counter 5. Factor: 0.333"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__test_oa__counter6__read; + counter->name = "TestCounter6"; + counter->desc = "HW test counter 6. Factor: 0.166"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__test_oa__counter3__read; + counter->name = "TestCounter3"; + counter->desc = "HW test counter 3. Factor: 0.5"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__test_oa__counter0__read; + counter->name = "TestCounter0"; + counter->desc = "HW test counter 0. Factor: 0.0"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__test_oa__counter1__read; + counter->name = "TestCounter1"; + counter->desc = "HW test counter 1. Factor: 1.0"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt2__test_oa__counter2__read; + counter->name = "TestCounter2"; + counter->desc = "HW test counter 2. Factor: 1.0"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +void +brw_oa_register_queries_kblgt2(struct brw_context *brw) +{ + kblgt2_register_render_basic_counter_query(brw); + kblgt2_register_compute_basic_counter_query(brw); + kblgt2_register_render_pipe_profile_counter_query(brw); + kblgt2_register_memory_reads_counter_query(brw); + kblgt2_register_memory_writes_counter_query(brw); + kblgt2_register_compute_extended_counter_query(brw); + kblgt2_register_compute_l3_cache_counter_query(brw); + kblgt2_register_hdc_and_sf_counter_query(brw); + kblgt2_register_l3_1_counter_query(brw); + kblgt2_register_l3_2_counter_query(brw); + kblgt2_register_l3_3_counter_query(brw); + kblgt2_register_rasterizer_and_pixel_backend_counter_query(brw); + kblgt2_register_sampler_counter_query(brw); + kblgt2_register_tdl_1_counter_query(brw); + kblgt2_register_tdl_2_counter_query(brw); + kblgt2_register_compute_extra_counter_query(brw); + kblgt2_register_vme_pipe_counter_query(brw); + kblgt2_register_gpu_busyness_counter_query(brw); + kblgt2_register_test_oa_counter_query(brw); +} + +static struct brw_perf_query_register_prog kblgt3_render_basic_mux_regs[83]; +static struct brw_perf_query_register_prog kblgt3_render_basic_b_counter_regs[5]; +static struct brw_perf_query_register_prog kblgt3_render_basic_flex_regs[7]; + +static struct brw_perf_query_counter kblgt3_render_basic_query_counters[52]; +static struct brw_perf_query_info kblgt3_render_basic_query = { + .kind = OA_COUNTERS, + .name = "Render Metrics Basic Gen9", + .guid = "0286c920-2f6d-493b-b22d-7a5280df43de", + .counters = kblgt3_render_basic_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = kblgt3_render_basic_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = kblgt3_render_basic_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = kblgt3_render_basic_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +kblgt3_register_render_basic_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &kblgt3_render_basic_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C01E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12170280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12370280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16EC01E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11930317 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x159303DF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E0380 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A6C0053 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C8400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F6600 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CA200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00133000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08133000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00170020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08170021 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10170000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0633C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0833C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06370800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08370840 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10370000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ACE0200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AEC5300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10EC0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CEC0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A9B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C9C0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CCC0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A8D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x108F0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16AC8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D933031 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F933E3F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01933D00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0393073C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0593000E }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900157 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900158 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190003F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51902240 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900242 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900084 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47901400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57902220 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900C60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900C63 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53902222 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_basic__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__render_basic__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_basic__l3_misses__read; + counter->name = "L3 Misses"; + counter->desc = "The total number of L3 misses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_basic__gti_l3_throughput__read; + counter->name = "GTI L3 Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__render_basic__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_basic__sampler_l1_misses__read; + counter->name = "Sampler Cache Misses"; + counter->desc = "The total number of sampler cache misses in all LODs in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__render_basic__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x12) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__render_basic__sampler1_bottleneck__read; + counter->name = "Sampler 1 Bottleneck"; + counter->desc = "The percentage of time in which Sampler 1 has been slowing down the pipe when processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 52; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__render_basic__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_basic__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_basic__l3_sampler_throughput__read; + counter->name = "L3 Sampler Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_basic__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__render_basic__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 88; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_basic__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_basic__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x09) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__render_basic__sampler0_busy__read; + counter->name = "Sampler 0 Busy"; + counter->desc = "The percentage of time in which Sampler 0 has been processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 112; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x12) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__render_basic__sampler1_busy__read; + counter->name = "Sampler 1 Busy"; + counter->desc = "The percentage of time in which Sampler 1 has been processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 116; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__render_basic__samplers_busy__read; + counter->name = "Samplers Busy"; + counter->desc = "The percentage of time in which samplers have been processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 120; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_basic__gti_vf_throughput__read; + counter->name = "GTI Fixed Pipe Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between 3D Pipeline (Command Dispatch, Input Assembly and Stream Output) and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_basic__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x09) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__render_basic__sampler0_bottleneck__read; + counter->name = "Sampler 0 Bottleneck"; + counter->desc = "The percentage of time in which Sampler 0 has been slowing down the pipe when processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_basic__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_basic__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_basic__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_basic__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = kblgt3__render_basic__avg_gpu_core_frequency__max(brw); + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_basic__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_basic__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_basic__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_basic__l3_lookups__read; + counter->name = "L3 Lookup Accesses w/o IC"; + counter->desc = "The total number of L3 cache lookup accesses w/o IC."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_basic__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_basic__gti_read_throughput__read; + counter->name = "GTI Read Throughput"; + counter->desc = "The total number of GPU memory bytes read from GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__render_basic__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 232; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__render_basic__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 236; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_basic__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__render_basic__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 248; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_basic__gti_depth_throughput__read; + counter->name = "GTI Depth Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between depth caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__render_basic__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 264; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__render_basic__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 268; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_basic__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_basic__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__render_basic__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 288; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_basic__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_basic__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__render_basic__sampler_bottleneck__read; + counter->name = "Samplers Bottleneck"; + counter->desc = "The percentage of time in which samplers have been slowing down the pipe when processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 312; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_basic__gti_hdc_lookups_throughput__read; + counter->name = "GTI HDC TLB Lookup Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between GTI and HDC, when HDC is doing TLB lookups."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_basic__gti_rcc_throughput__read; + counter->name = "GTI RCC Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between render color caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 328; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_basic__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 336; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_basic__gti_write_throughput__read; + counter->name = "GTI Write Throughput"; + counter->desc = "The total number of GPU memory bytes written to GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 344; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_basic__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 352; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_basic__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 360; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_basic__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 368; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_basic__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 376; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog kblgt3_compute_basic_mux_regs[78]; +static struct brw_perf_query_register_prog kblgt3_compute_basic_b_counter_regs[5]; +static struct brw_perf_query_register_prog kblgt3_compute_basic_flex_regs[7]; + +static struct brw_perf_query_counter kblgt3_compute_basic_query_counters[39]; +static struct brw_perf_query_info kblgt3_compute_basic_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics Basic Gen9", + .guid = "9823aaa1-b06f-40ce-884b-cd798c79f0c2", + .counters = kblgt3_compute_basic_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = kblgt3_compute_basic_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = kblgt3_compute_basic_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = kblgt3_compute_basic_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +kblgt3_register_compute_basic_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &kblgt3_compute_basic_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F00E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124F1C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C00E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E0820 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F0900 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084F0032 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4F1891 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4F0E00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4F003C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004F0D80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024F003B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C0100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C6C000C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C0B00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0024 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C6000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C5C001B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0208 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CFB00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00BE }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19900157 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B900158 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900105 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900103 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900FFF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900821 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900802 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900802 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900422 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53904444 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_basic__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_basic__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_basic__untyped_bytes_read__read; + counter->name = "Untyped Bytes Read"; + counter->desc = "The total number of typed memory bytes read via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_basic__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_basic__typed_bytes_written__read; + counter->name = "Typed Bytes Written"; + counter->desc = "The total number of untyped memory bytes written via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_basic__fpu0_active__read; + counter->name = "EU FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_basic__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 44; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_basic__eu_avg_ipc_rate__read; + counter->name = "EU AVG IPC Rate"; + counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 2.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_basic__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_basic__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_basic__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_basic__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_basic__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_basic__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_basic__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_basic__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_basic__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = kblgt3__compute_basic__avg_gpu_core_frequency__max(brw); + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_basic__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_basic__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_basic__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_basic__gti_read_throughput__read; + counter->name = "GTI Read Throughput"; + counter->desc = "The total number of GPU memory bytes read from GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_basic__untyped_bytes_written__read; + counter->name = "Untyped Writes"; + counter->desc = "The total number of untyped memory bytes written via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_basic__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_basic__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_basic__typed_bytes_read__read; + counter->name = "Typed Bytes Read"; + counter->desc = "The total number of typed memory bytes read via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_basic__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_basic__eu_thread_occupancy__read; + counter->name = "EU Thread Occupancy"; + counter->desc = "The percentage of time in which hardware threads occupied EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_basic__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 204; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_basic__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_basic__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_basic__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_basic__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_basic__gti_write_throughput__read; + counter->name = "GTI Write Throughput"; + counter->desc = "The total number of GPU memory bytes written to GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_basic__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_basic__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_basic__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_basic__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_basic__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_basic__eu_send_active__read; + counter->name = "EU Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 288; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog kblgt3_render_pipe_profile_mux_regs[114]; +static struct brw_perf_query_register_prog kblgt3_render_pipe_profile_b_counter_regs[21]; +static struct brw_perf_query_register_prog kblgt3_render_pipe_profile_flex_regs[7]; + +static struct brw_perf_query_counter kblgt3_render_pipe_profile_query_counters[43]; +static struct brw_perf_query_info kblgt3_render_pipe_profile_query = { + .kind = OA_COUNTERS, + .name = "Render Metrics for 3D Pipeline Profile Gen9", + .guid = "c7c735f3-ce58-45cf-aa04-30b183f1faff", + .counters = kblgt3_render_pipe_profile_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = kblgt3_render_pipe_profile_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = kblgt3_render_pipe_profile_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = kblgt3_render_pipe_profile_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +kblgt3_register_render_pipe_profile_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &kblgt3_render_pipe_profile_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0E001F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10116800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178A03E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11824C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11830020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13840020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11850019 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11860007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01870C40 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17880000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020E5400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000E0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080F0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06104000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06110012 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06131000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01898000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D890100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03898000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A0075 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8A4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x138A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D81A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15818000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17818000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B820030 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07828000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D824000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F828000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05824000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D830003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0583000C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09830000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03838000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07838000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B840980 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03844D80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11840000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09850080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03850003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01850000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07860000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F860400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09870032 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01888052 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11880000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09884000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B931001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D930001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19934000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B958000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950094 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19958000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09E58000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0BE58000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E5C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0592C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B928000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D924000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F924000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11928000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1392C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09924000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01985000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07988000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09981000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B982000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D982000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F989000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05982000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190C080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900440 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C21 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900042 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900024 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900841 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900400 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFEA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFC }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007AFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F5FD }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00079FFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000F3FB }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007BF7A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F7E7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FEFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000F7CF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00077FFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000EFDF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0006FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000CFBF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0003FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x00005F7F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__render_pipe_profile__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__render_pipe_profile__vs_bottleneck__read; + counter->name = "VS Bottleneck"; + counter->desc = "The percentage of time in which vertex shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__render_pipe_profile__hi_depth_bottleneck__read; + counter->name = "Hi-Depth Bottleneck"; + counter->desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__render_pipe_profile__gs_bottleneck__read; + counter->name = "GS Bottleneck"; + counter->desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__render_pipe_profile__bc_bottleneck__read; + counter->name = "BC Bottleneck"; + counter->desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__render_pipe_profile__hs_stall__read; + counter->name = "HS Stall"; + counter->desc = "The percentage of time in which hull stall pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 60; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = kblgt3__render_pipe_profile__avg_gpu_core_frequency__max(brw); + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__render_pipe_profile__vf_bottleneck__read; + counter->name = "VF Bottleneck"; + counter->desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__render_pipe_profile__sf_bottleneck__read; + counter->name = "Strip-Fans Bottleneck"; + counter->desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__render_pipe_profile__sf_stall__read; + counter->name = "SF Stall"; + counter->desc = "The percentage of time in which strip-fans pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 140; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__render_pipe_profile__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__render_pipe_profile__hs_bottleneck__read; + counter->name = "HS Bottleneck"; + counter->desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__render_pipe_profile__cl_stall__read; + counter->name = "CL Stall"; + counter->desc = "The percentage of time in which clipper pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__render_pipe_profile__so_bottleneck__read; + counter->name = "SO Bottleneck"; + counter->desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__render_pipe_profile__ds_bottleneck__read; + counter->name = "DS Bottleneck"; + counter->desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__render_pipe_profile__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 188; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__render_pipe_profile__cl_bottleneck__read; + counter->name = "Clipper Bottleneck"; + counter->desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__render_pipe_profile__ds_stall__read; + counter->name = "DS Stall"; + counter->desc = "The percentage of time in which domain shader pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 196; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__render_pipe_profile__early_depth_bottleneck__read; + counter->name = "Early Depth Bottleneck"; + counter->desc = "The percentage of time in which early depth test pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__render_pipe_profile__so_stall__read; + counter->name = "SO Stall"; + counter->desc = "The percentage of time in which stream-output pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__render_pipe_profile__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog kblgt3_memory_reads_mux_regs[47]; +static struct brw_perf_query_register_prog kblgt3_memory_reads_b_counter_regs[32]; +static struct brw_perf_query_register_prog kblgt3_memory_reads_flex_regs[7]; + +static struct brw_perf_query_counter kblgt3_memory_reads_query_counters[41]; +static struct brw_perf_query_info kblgt3_memory_reads_query = { + .kind = OA_COUNTERS, + .name = "Memory Reads Distribution Gen9", + .guid = "96ec2219-040b-428a-856a-6bc03363a057", + .counters = kblgt3_memory_reads_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = kblgt3_memory_reads_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = kblgt3_memory_reads_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = kblgt3_memory_reads_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +kblgt3_register_memory_reads_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &kblgt3_memory_reads_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1381001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900064 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03811300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05811B12 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0781001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E58000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05E5C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900150 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21900151 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23900152 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25900153 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27900154 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B900156 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D900157 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F90015F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900105 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900103 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900101 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C63 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900C63 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000272C, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002728, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000271C, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002718, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F872 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_reads__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__memory_reads__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_reads__gti_l3_bank0_reads__read; + counter->name = "GtiL3Bank0Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 0 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_reads__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_reads__gti_ring_accesses__read; + counter->name = "GtiRingAccesses"; + counter->desc = "The total number of all accesses from GTI to the ring."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_reads__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_reads__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_reads__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_reads__gti_l3_bank3_reads__read; + counter->name = "GtiL3Bank3Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 3 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_reads__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_reads__gti_rs_memory_reads__read; + counter->name = "GtiRsMemoryReads"; + counter->desc = "The total number of GTI memory reads from Resource Streamer."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_reads__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_reads__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_reads__gti_hiz_memory_reads__read; + counter->name = "GtiHizMemoryReads"; + counter->desc = "The total number of GTI memory reads from Hierarchical Depth Cache (Hi-Depth Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_reads__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_reads__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = kblgt3__memory_reads__avg_gpu_core_frequency__max(brw); + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_reads__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_reads__gti_rcc_memory_reads__read; + counter->name = "GtiRccMemoryReads"; + counter->desc = "The total number of GTI memory reads from Render Color Cache (Render Color Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_reads__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_reads__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_reads__gti_l3_bank1_reads__read; + counter->name = "GtiL3Bank1Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 1 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__memory_reads__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_reads__gti_cmd_streamer_memory_reads__read; + counter->name = "GtiCmdStreamerMemoryReads"; + counter->desc = "The total number of GTI memory reads from Command Streamer."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_reads__gti_l3_bank2_reads__read; + counter->name = "GtiL3Bank2Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 2 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_reads__gti_memory_reads__read; + counter->name = "GtiMemoryReads"; + counter->desc = "The total number of GTI memory reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_reads__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_reads__gti_rcz_memory_reads__read; + counter->name = "GtiRczMemoryReads"; + counter->desc = "The total number of GTI memory reads from Render Depth Cache (Render Depth Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_reads__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_reads__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__memory_reads__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 232; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_reads__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_reads__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_reads__gti_msc_memory_reads__read; + counter->name = "GtiMscMemoryReads"; + counter->desc = "The total number of GTI memory reads from Multisampling Color Cache (Multisampling Color Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_reads__gti_vf_memory_reads__read; + counter->name = "GtiVfMemoryReads"; + counter->desc = "The total number of GTI memory reads from Vertex Fetch."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_reads__gti_stc_memory_reads__read; + counter->name = "GtiStcMemoryReads"; + counter->desc = "The total number of GTI memory reads from Stencil Cache (Stencil Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_reads__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_reads__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_reads__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_reads__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_reads__gti_l3_reads__read; + counter->name = "GtiL3Reads"; + counter->desc = "The total number of GTI memory reads from L3 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_reads__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog kblgt3_memory_writes_mux_regs[47]; +static struct brw_perf_query_register_prog kblgt3_memory_writes_b_counter_regs[32]; +static struct brw_perf_query_register_prog kblgt3_memory_writes_flex_regs[7]; + +static struct brw_perf_query_counter kblgt3_memory_writes_query_counters[41]; +static struct brw_perf_query_info kblgt3_memory_writes_query = { + .kind = OA_COUNTERS, + .name = "Memory Writes Distribution Gen9", + .guid = "03372b64-4996-4d3b-aa18-790e75eeb9c2", + .counters = kblgt3_memory_writes_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = kblgt3_memory_writes_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = kblgt3_memory_writes_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = kblgt3_memory_writes_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +kblgt3_register_memory_writes_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &kblgt3_memory_writes_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1381001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F901000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03811300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05811B12 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0781001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E58000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05E5C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900160 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21900161 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23900162 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25900163 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27900164 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900165 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B900166 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D900167 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F900150 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900105 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900103 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900101 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C63 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900C63 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000272C, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002728, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000271C, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002718, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F822 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_writes__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__memory_writes__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_writes__gti_memory_writes__read; + counter->name = "GtiMemoryWrites"; + counter->desc = "The total number of GTI memory writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_writes__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_writes__gti_ring_accesses__read; + counter->name = "GtiRingAccesses"; + counter->desc = "The total number of all GTI accesses to the ring."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_writes__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_writes__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_writes__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_writes__gti_msc_memory_writes__read; + counter->name = "GtiMscMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Multisampling Color Cache (Multisampling Color Cache invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_writes__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_writes__gti_cmd_streamer_memory_writes__read; + counter->name = "GtiCmdStreamerMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Command Streamer."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_writes__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_writes__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_writes__gti_l3_bank0_writes__read; + counter->name = "GtiL3Bank0Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 0 (L3 Bank 0 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_writes__gti_l3_bank1_writes__read; + counter->name = "GtiL3Bank1Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 1 (L3 Bank 1 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_writes__gti_l3_bank2_writes__read; + counter->name = "GtiL3Bank2Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 2 (L3 Bank 2 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_writes__gti_l3_bank3_writes__read; + counter->name = "GtiL3Bank3Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 3 (L3 Bank 3 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_writes__gti_l3_writes__read; + counter->name = "GtiL3Writes"; + counter->desc = "The total number of GTI memory writes from L3 (L3 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_writes__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_writes__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = kblgt3__memory_writes__avg_gpu_core_frequency__max(brw); + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_writes__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_writes__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_writes__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_writes__gti_rcc_memory_writes__read; + counter->name = "GtiRccMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Render Color Cache (Render Color Cache invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_writes__gti_so_memory_writes__read; + counter->name = "GtiSoMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Stream Output."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__memory_writes__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_writes__gti_stc_memory_writes__read; + counter->name = "GtiStcMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Stencil Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_writes__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_writes__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_writes__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__memory_writes__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 240; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_writes__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_writes__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_writes__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_writes__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_writes__gti_rcz_memory_writes__read; + counter->name = "GtiRczMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Render Depth Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_writes__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_writes__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_writes__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_writes__gti_hiz_memory_writes__read; + counter->name = "GtiHizMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Hierarchical Depth Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__memory_writes__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog kblgt3_compute_extended_mux_regs[72]; +static struct brw_perf_query_register_prog kblgt3_compute_extended_b_counter_regs[21]; +static struct brw_perf_query_register_prog kblgt3_compute_extended_flex_regs[7]; + +static struct brw_perf_query_counter kblgt3_compute_extended_query_counters[38]; +static struct brw_perf_query_info kblgt3_compute_extended_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics Extended Gen9", + .guid = "31b4ce5a-bd61-4c1f-bb5d-f2e731412150", + .counters = kblgt3_compute_extended_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = kblgt3_compute_extended_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = kblgt3_compute_extended_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = kblgt3_compute_extended_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +kblgt3_register_compute_extended_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &kblgt3_compute_extended_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C00E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8160 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C0120 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x184E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4EAAA0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C0B01 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C000C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001C0041 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061C4200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081C4443 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1C4645 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1C7647 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041C7357 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0030 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4CAA2A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C02AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5515 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CAA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11907FFF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900802 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FC2A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FC6A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007FC92 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007FCA2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FC32 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FC9A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007FE6A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007FE7A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000BF00 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_extended__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_extended__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_extended__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_extended__fpu0_active__read; + counter->name = "EU FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_extended__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_extended__eu_avg_ipc_rate__read; + counter->name = "EU AVG IPC Rate"; + counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 2.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_extended__typed_writes0__read; + counter->name = "Typed Writes 0"; + counter->desc = "The subslice 0 typed writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_extended__eu_typed_atomics0__read; + counter->name = "EuTypedAtomics0"; + counter->desc = "The subslice 0 EU Typed Atomics subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_extended__typed_atomics0__read; + counter->name = "Typed Atomics 0"; + counter->desc = "The subslice 0 typed atomics."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_extended__typed_atomics_per_cache_line__read; + counter->name = "TypedAtomicsPerCacheLine"; + counter->desc = "The ratio of EU typed atomics requests to L3 cache line writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_extended__eu_untyped_reads0__read; + counter->name = "EuUntypedReads0"; + counter->desc = "The subslice 0 EU Untyped Reads subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_extended__untyped_writes0__read; + counter->name = "Untyped Writes 0"; + counter->desc = "The subslice 0 untyped writes (including SLM writes)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_extended__eu_untyped_atomics0__read; + counter->name = "EuUntypedAtomics0"; + counter->desc = "The subslice 0 EU Untyped Atomics subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_extended__eu_untyped_writes0__read; + counter->name = "EuUntypedWrites0"; + counter->desc = "The subslice 0 EU Untyped Writes subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_extended__eu_a64_untyped_writes0__read; + counter->name = "EuA64UntypedWrites0"; + counter->desc = "The subslice 0 EU A64 Untyped Writes subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_extended__untyped_writes_per_cache_line__read; + counter->name = "UntypedWritesPerCacheLine"; + counter->desc = "The ratio of EU untyped write requests to L3 cache line writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_extended__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_extended__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_extended__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_extended__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = kblgt3__compute_extended__avg_gpu_core_frequency__max(brw); + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_extended__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_extended__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_extended__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_extended__eu_typed_writes0__read; + counter->name = "EuTypedWrites0"; + counter->desc = "The subslice 0 EU Typed Writes subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_extended__typed_writes_per_cache_line__read; + counter->name = "TypedWritesPerCacheLine"; + counter->desc = "The ratio of EU typed write requests to L3 cache line writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_extended__typed_reads0__read; + counter->name = "Typed Reads 0"; + counter->desc = "The subslice 0 typed reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_extended__untyped_reads0__read; + counter->name = "Untyped Reads 0"; + counter->desc = "The subslice 0 untyped reads (including SLM reads)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_extended__eu_a64_untyped_reads0__read; + counter->name = "EuA64UntypedReads0"; + counter->desc = "The subslice 0 EU A64 Untyped Reads subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_extended__eu_thread_occupancy__read; + counter->name = "EU Thread Occupancy"; + counter->desc = "The percentage of time in which hardware threads occupied EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 208; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_extended__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 212; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_extended__eu_typed_reads0__read; + counter->name = "EuTypedReads0"; + counter->desc = "The subslice 0 EU Typed Reads subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_extended__untyped_reads_per_cache_line__read; + counter->name = "UntypedReadsPerCacheLine"; + counter->desc = "The ratio of EU untyped read requests to L3 cache line reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_extended__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_extended__typed_reads_per_cache_line__read; + counter->name = "TypedReadsPerCacheLine"; + counter->desc = "The ratio of EU typed read requests to L3 cache line reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_extended__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_extended__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_extended__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_extended__eu_send_active__read; + counter->name = "EU Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 272; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog kblgt3_compute_l3_cache_mux_regs[60]; +static struct brw_perf_query_register_prog kblgt3_compute_l3_cache_b_counter_regs[13]; +static struct brw_perf_query_register_prog kblgt3_compute_l3_cache_flex_regs[7]; + +static struct brw_perf_query_counter kblgt3_compute_l3_cache_query_counters[54]; +static struct brw_perf_query_info kblgt3_compute_l3_cache_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics L3 Cache Gen9", + .guid = "2ce0911a-27fc-4887-96f0-11084fa807c3", + .counters = kblgt3_compute_l3_cache_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = kblgt3_compute_l3_cache_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = kblgt3_compute_l3_cache_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = kblgt3_compute_l3_cache_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +kblgt3_register_compute_l3_cache_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &kblgt3_compute_l3_cache_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C0760 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1593001E }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x184E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E8020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0051 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C5C5D }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C5E5F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1CE000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0030 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C2A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F1500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0140 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162C0A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03933300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05930032 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900157 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900158 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190030F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900021 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53904444 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FEFE }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FEFD }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FBEF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FBDF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00101100 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00201200 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00301300 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00401400 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_l3_cache__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__l3_bank03_accesses__read; + counter->name = "L3 Bank 03 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 03."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__l3_accesses__read; + counter->name = "L3 Accesses"; + counter->desc = "The total number of L3 accesses from all entities."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_l3_cache__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__l3_sampler_throughput__read; + counter->name = "L3 Sampler Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_l3_cache__fpu0_active__read; + counter->name = "EU FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_l3_cache__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 52; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_l3_cache__eu_avg_ipc_rate__read; + counter->name = "EU AVG IPC Rate"; + counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 2.0; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_l3_cache__eu_binary_fpu0_instruction__read; + counter->name = "EU FPU0 Binary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 60; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_l3_cache__eu_hybrid_fpu0_instruction__read; + counter->name = "EU FPU0 Hybrid Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 104; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__l3_misses__read; + counter->name = "L3 Misses"; + counter->desc = "The total number of L3 misses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__l3_bank00_accesses__read; + counter->name = "L3 Bank 00 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 00."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_l3_cache__eu_move_fpu0_instruction__read; + counter->name = "EU FPU0 Move Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_l3_cache__eu_hybrid_fpu1_instruction__read; + counter->name = "EU FPU1 Hybrid Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = kblgt3__compute_l3_cache__avg_gpu_core_frequency__max(brw); + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__gti_read_throughput__read; + counter->name = "GTI Read Throughput"; + counter->desc = "The total number of GPU memory bytes read from GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__gti_l3_throughput__read; + counter->name = "GTI L3 Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__l3_bank00_ic_accesses__read; + counter->name = "L3 Bank 00 IC Accesses"; + counter->desc = "The total number of accesses to L3 Bank 00 from IC cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + } + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__l3_bank00_ic_hits__read; + counter->name = "L3 Bank 00 IC Hits"; + counter->desc = "The total number of hits in L3 Bank 00 from IC cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__sampler_accesses__read; + counter->name = "Sampler Accesses"; + counter->desc = "The total number of messages send to samplers."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__l3_bank01_accesses__read; + counter->name = "L3 Bank 01 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 01."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_l3_cache__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 256; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_l3_cache__eu_ternary_fpu0_instruction__read; + counter->name = "EU FPU0 Ternary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 260; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_l3_cache__eu_move_fpu1_instruction__read; + counter->name = "EU FPU1 Move Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 296; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_l3_cache__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 300; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__l3_bank02_accesses__read; + counter->name = "L3 Bank 02 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 02."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 328; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__l3_total_throughput__read; + counter->name = "L3 Total Throughput"; + counter->desc = "The total number of GPU memory bytes transferred via L3."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 336; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__gti_write_throughput__read; + counter->name = "GTI Write Throughput"; + counter->desc = "The total number of GPU memory bytes written to GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 344; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 352; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 360; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_l3_cache__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 368; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_l3_cache__eu_binary_fpu1_instruction__read; + counter->name = "EU FPU1 Binary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 376; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_l3_cache__eu_ternary_fpu1_instruction__read; + counter->name = "EU FPU1 Ternary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 380; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_l3_cache__eu_send_active__read; + counter->name = "EU Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 384; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog kblgt3_hdc_and_sf_mux_regs[54]; +static struct brw_perf_query_register_prog kblgt3_hdc_and_sf_b_counter_regs[9]; +static struct brw_perf_query_register_prog kblgt3_hdc_and_sf_flex_regs[7]; + +static struct brw_perf_query_counter kblgt3_hdc_and_sf_query_counters[39]; +static struct brw_perf_query_info kblgt3_hdc_and_sf_query = { + .kind = OA_COUNTERS, + .name = "Metric set HDCAndSF", + .guid = "546c4c1d-99b8-42fb-a107-5aaabb5314a8", + .counters = kblgt3_hdc_and_sf_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = kblgt3_hdc_and_sf_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = kblgt3_hdc_and_sf_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = kblgt3_hdc_and_sf_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +kblgt3_register_hdc_and_sf_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &kblgt3_hdc_and_sf_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F0232 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124F4640 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0232 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11834400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004F1880 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024F08BB }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044F001B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C0100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C000B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C1800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x165C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x185C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C00A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F828000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8305C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09830000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07830000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13928000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F988000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FDFF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__hdc_and_sf__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__hdc_and_sf__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__hdc_and_sf__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__hdc_and_sf__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__hdc_and_sf__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__hdc_and_sf__poly_data_ready__read; + counter->name = "Polygon Data Ready"; + counter->desc = "The percentage of time in which geometry pipeline output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = kblgt3__hdc_and_sf__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read; + counter->name = "HDC stalled by L3 (s0.ss1)"; + counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss1)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 120; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read; + counter->name = "HDC stalled by L3 (s0.ss2)"; + counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss2)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__hdc_and_sf__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__hdc_and_sf__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__hdc_and_sf__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__hdc_and_sf__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 164; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__hdc_and_sf__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__hdc_and_sf__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read; + counter->name = "HDC stalled by L3 (s0.ss0)"; + counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss0)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 264; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__hdc_and_sf__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog kblgt3_l3_1_mux_regs[71]; +static struct brw_perf_query_register_prog kblgt3_l3_1_b_counter_regs[22]; +static struct brw_perf_query_register_prog kblgt3_l3_1_flex_regs[7]; + +static struct brw_perf_query_counter kblgt3_l3_1_query_counters[39]; +static struct brw_perf_query_info kblgt3_l3_1_query = { + .kind = OA_COUNTERS, + .name = "Metric set L3_1", + .guid = "4e93d156-9b39-4268-8544-a8e0480806d7", + .counters = kblgt3_l3_1_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = kblgt3_l3_1_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = kblgt3_l3_1_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = kblgt3_l3_1_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +kblgt3_register_l3_1_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &kblgt3_l3_1_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C7B40 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C0020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A603444 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A613400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4EA800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C6C5327 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C5425 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C2A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C285B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C005C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C003C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10600000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04600000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C610044 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10610000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06610000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C02A8 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0154 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FFC0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900420 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900021 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900421 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00014002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000C3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00010002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000C7FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00004002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000D3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100700 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FF1F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00001402 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FC3F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00001002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FC7F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00000402 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FD3F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_1__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_1__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_1__l30_bank1_active__read; + counter->name = "Slice0 L3 Bank1 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank1 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_1__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_1__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_1__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_1__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_1__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_1__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_1__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_1__l30_bank1_stalled__read; + counter->name = "Slice0 L3 Bank1 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank1 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_1__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_1__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_1__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_1__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_1__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_1__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = kblgt3__l3_1__avg_gpu_core_frequency__max(brw); + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_1__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_1__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_1__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_1__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_1__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_1__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_1__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_1__l30_bank0_active__read; + counter->name = "Slice0 L3 Bank0 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank0 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_1__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_1__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_1__l30_bank0_stalled__read; + counter->name = "Slice0 L3 Bank0 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank0 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 180; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_1__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_1__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_1__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_1__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_1__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_1__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_1__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_1__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_1__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_1__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_1__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog kblgt3_l3_2_mux_regs[44]; +static struct brw_perf_query_register_prog kblgt3_l3_2_b_counter_regs[14]; +static struct brw_perf_query_register_prog kblgt3_l3_2_flex_regs[7]; + +static struct brw_perf_query_counter kblgt3_l3_2_query_counters[37]; +static struct brw_perf_query_info kblgt3_l3_2_query = { + .kind = OA_COUNTERS, + .name = "Metric set L3_2", + .guid = "de1bec86-ca92-4b43-89fa-147653221cc0", + .counters = kblgt3_l3_2_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = kblgt3_l3_2_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = kblgt3_l3_2_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = kblgt3_l3_2_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +kblgt3_register_l3_2_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &kblgt3_l3_2_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C02E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146C0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A623400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C3324 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C3422 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06614000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C620044 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10620000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06620000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190F800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00028002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x000087FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00020002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00008FFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00008002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000A7FF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_2__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_2__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_2__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_2__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_2__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_2__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_2__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_2__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_2__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_2__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_2__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_2__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_2__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_2__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_2__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = kblgt3__l3_2__avg_gpu_core_frequency__max(brw); + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_2__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_2__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_2__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_2__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 128; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_2__l30_bank2_stalled__read; + counter->name = "Slice0 L3 Bank2 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank2 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 132; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_2__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_2__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 140; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_2__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_2__l30_bank2_active__read; + counter->name = "Slice0 L3 Bank2 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank2 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_2__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_2__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_2__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_2__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_2__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 184; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_2__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_2__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_2__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_2__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_2__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_2__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_2__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_2__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog kblgt3_l3_3_mux_regs[43]; +static struct brw_perf_query_register_prog kblgt3_l3_3_b_counter_regs[14]; +static struct brw_perf_query_register_prog kblgt3_l3_3_flex_regs[7]; + +static struct brw_perf_query_counter kblgt3_l3_3_query_counters[37]; +static struct brw_perf_query_info kblgt3_l3_3_query = { + .kind = OA_COUNTERS, + .name = "Metric set L3_3", + .guid = "e63537bb-10be-4d4a-92c4-c6b0c65e02ef", + .counters = kblgt3_l3_3_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = kblgt3_l3_3_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = kblgt3_l3_3_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = kblgt3_l3_3_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +kblgt3_register_l3_3_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &kblgt3_l3_3_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C4E80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A633400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C3321 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C342F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C1800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06604000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C630044 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10630000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06630000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C00AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190F800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00028002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x000087FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00020002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00008FFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00008002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000A7FF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_3__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_3__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_3__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_3__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_3__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_3__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_3__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_3__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_3__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_3__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_3__l30_bank3_stalled__read; + counter->name = "Slice0 L3 Bank3 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank3 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_3__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_3__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_3__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_3__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_3__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = kblgt3__l3_3__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_3__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_3__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_3__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_3__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_3__l30_bank3_active__read; + counter->name = "Slice0 L3 Bank3 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank3 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 140; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_3__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_3__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_3__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_3__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_3__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_3__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_3__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__l3_3__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_3__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_3__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_3__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_3__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_3__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_3__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_3__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__l3_3__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog kblgt3_rasterizer_and_pixel_backend_mux_regs[31]; +static struct brw_perf_query_register_prog kblgt3_rasterizer_and_pixel_backend_b_counter_regs[10]; +static struct brw_perf_query_register_prog kblgt3_rasterizer_and_pixel_backend_flex_regs[7]; + +static struct brw_perf_query_counter kblgt3_rasterizer_and_pixel_backend_query_counters[40]; +static struct brw_perf_query_info kblgt3_rasterizer_and_pixel_backend_query = { + .kind = OA_COUNTERS, + .name = "Metric set RasterizerAndPixelBackend", + .guid = "7a03a9f8-ec5e-46bb-8b67-1f0ff1476281", + .counters = kblgt3_rasterizer_and_pixel_backend_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = kblgt3_rasterizer_and_pixel_backend_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = kblgt3_rasterizer_and_pixel_backend_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = kblgt3_rasterizer_and_pixel_backend_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +kblgt3_register_rasterizer_and_pixel_backend_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &kblgt3_rasterizer_and_pixel_backend_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102F3800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x144D0500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x120D03C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x140D03CF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0004 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F0480 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0090 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064D0027 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004D0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D0D40 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020D803F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040D8023 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100D0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020F0010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0050 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41901400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43901485 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000EFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00006000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F3FF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__rasterizer_and_pixel_backend__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__rasterizer_and_pixel_backend__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__rasterizer_and_pixel_backend__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__rasterizer_and_pixel_backend__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__rasterizer_and_pixel_backend__pixel_values0_ready__read; + counter->name = "Slice0 Pixel Values Ready"; + counter->desc = "The percentage of time in which slice0 pixel values are ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = kblgt3__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__rasterizer_and_pixel_backend__rasterizer0_input_available__read; + counter->name = "Slice0 Rasterizer Input Available"; + counter->desc = "The percentage of time in which slice0 rasterizer input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 128; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__rasterizer_and_pixel_backend__pixel_data0_ready__read; + counter->name = "Slice0 Post-EarlyZ Pixel Data Ready"; + counter->desc = "The percentage of time in which slice0 post-EarlyZ pixel data is ready (after early Z tests have been applied)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 132; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__rasterizer_and_pixel_backend__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__rasterizer_and_pixel_backend__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__rasterizer_and_pixel_backend__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__rasterizer_and_pixel_backend__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__rasterizer_and_pixel_backend__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__rasterizer_and_pixel_backend__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__rasterizer_and_pixel_backend__rasterizer0_output_ready__read; + counter->name = "Slice0 Rasterizer Output Ready"; + counter->desc = "The percentage of time in which slice0 rasterizer output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 196; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__rasterizer_and_pixel_backend__ps_output0_available__read; + counter->name = "Slice0 PS Output Available"; + counter->desc = "The percentage of time in which slice0 PS output is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 256; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__rasterizer_and_pixel_backend__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog kblgt3_sampler_mux_regs[69]; +static struct brw_perf_query_register_prog kblgt3_sampler_b_counter_regs[12]; +static struct brw_perf_query_register_prog kblgt3_sampler_flex_regs[7]; + +static struct brw_perf_query_counter kblgt3_sampler_query_counters[41]; +static struct brw_perf_query_info kblgt3_sampler_query = { + .kind = OA_COUNTERS, + .name = "Metric set Sampler", + .guid = "b25d2ebf-a6e0-4b29-96be-a9b010edeeda", + .counters = kblgt3_sampler_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = kblgt3_sampler_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = kblgt3_sampler_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = kblgt3_sampler_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +kblgt3_register_sampler_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &kblgt3_sampler_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14152C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16150005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121600A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14352C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16350005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123600A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14552C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16550005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125600A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062F6000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0050 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0350 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FB000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F00DA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C0028 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C138000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E132000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0413C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C140018 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C157000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E150078 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10150000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04162180 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02160000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04174000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0233A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04333000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14348000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16348000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02357870 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10350000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04360043 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02360000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04371000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E538000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00538000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06533000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C540020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12548000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E557000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00557800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10550000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06560043 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02560000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06571000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FF80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900060 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900060 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x70800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0000C000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000E7FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00003000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F9FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000C00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE7F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__sampler__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__sampler__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__sampler__sampler02_input_available__read; + counter->name = "Slice0 Subslice2 Input Available"; + counter->desc = "The percentage of time in which slice0 subslice2 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__sampler__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__sampler__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__sampler__sampler00_input_available__read; + counter->name = "Slice0 Subslice0 Input Available"; + counter->desc = "The percentage of time in which slice0 subslice0 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__sampler__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 28; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__sampler__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__sampler__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__sampler__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__sampler__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__sampler__sampler02_output_ready__read; + counter->name = "Slice0 Subslice2 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice0 subslice2 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__sampler__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__sampler__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__sampler__sampler01_input_available__read; + counter->name = "Slice0 Subslice1 Input Available"; + counter->desc = "The percentage of time in which slice0 subslice1 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 88; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__sampler__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__sampler__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__sampler__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__sampler__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = kblgt3__sampler__avg_gpu_core_frequency__max(brw); + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__sampler__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__sampler__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__sampler__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__sampler__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__sampler__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__sampler__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__sampler__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 164; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__sampler__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__sampler__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__sampler__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__sampler__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__sampler__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__sampler__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__sampler__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__sampler__sampler00_output_ready__read; + counter->name = "Slice0 Subslice0 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice0 subslice0 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 224; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__sampler__sampler01_output_ready__read; + counter->name = "Slice0 Subslice1 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice0 subslice1 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 228; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__sampler__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__sampler__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__sampler__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__sampler__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__sampler__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__sampler__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog kblgt3_tdl_1_mux_regs[68]; +static struct brw_perf_query_register_prog kblgt3_tdl_1_b_counter_regs[18]; +static struct brw_perf_query_register_prog kblgt3_tdl_1_flex_regs[7]; + +static struct brw_perf_query_counter kblgt3_tdl_1_query_counters[41]; +static struct brw_perf_query_info kblgt3_tdl_1_query = { + .kind = OA_COUNTERS, + .name = "Metric set TDL_1", + .guid = "469a05e5-e299-46f7-9598-7b05f3c34991", + .counters = kblgt3_tdl_1_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = kblgt3_tdl_1_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = kblgt3_tdl_1_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = kblgt3_tdl_1_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +kblgt3_register_tdl_1_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &kblgt3_tdl_1_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12120000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12320000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12520000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F3000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F03A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FF000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0095 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02108000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0410C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02118000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0411C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02121880 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041219B5 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02134000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04135000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C308000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E304000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06304000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C318000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E314000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06314000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C321A80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E320033 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06320031 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00320000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C334000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E331000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06331000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E508000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00508000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02504000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E518000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00518000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02514000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E521880 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00521A80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02520033 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E534000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00534000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02531000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FF80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900062 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00009FFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000EFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FDFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE7F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_1__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__tdl_1__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__tdl_1__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__tdl_1__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__tdl_1__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_1__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_1__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__tdl_1__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_1__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_1__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__tdl_1__non_ps_thread02_ready_for_dispatch__read; + counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice2"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_1__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_1__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_1__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_1__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_1__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = kblgt3__tdl_1__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_1__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__tdl_1__non_ps_thread00_ready_for_dispatch__read; + counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice0"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 120; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_1__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_1__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__tdl_1__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__tdl_1__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__tdl_1__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__tdl_1__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__tdl_1__ps_thread00_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice0"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_1__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__tdl_1__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_1__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_1__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__tdl_1__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_1__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_1__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__tdl_1__ps_thread01_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice1"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 224; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_1__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_1__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__tdl_1__ps_thread02_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice2"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 248; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_1__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_1__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_1__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_1__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__tdl_1__non_ps_thread01_ready_for_dispatch__read; + counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice1"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 288; + counter->size = sizeof(float); + } + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog kblgt3_tdl_2_mux_regs[42]; +static struct brw_perf_query_register_prog kblgt3_tdl_2_b_counter_regs[6]; +static struct brw_perf_query_register_prog kblgt3_tdl_2_flex_regs[7]; + +static struct brw_perf_query_counter kblgt3_tdl_2_query_counters[41]; +static struct brw_perf_query_info kblgt3_tdl_2_query = { + .kind = OA_COUNTERS, + .name = "Metric set TDL_2", + .guid = "52f925c6-786a-4ec6-86ce-cba85c83453a", + .counters = kblgt3_tdl_2_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = kblgt3_tdl_2_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = kblgt3_tdl_2_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = kblgt3_tdl_2_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +kblgt3_register_tdl_2_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &kblgt3_tdl_2_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12124D60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12322E60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12524D60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F3000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0014 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FE000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0097 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0410C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0411C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04121FB7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04135000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00308000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06304000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00318000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06314000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00321B80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0632003F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00334000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06331000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0250C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0251C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02521FB7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00520000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02535000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_2__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__tdl_2__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__tdl_2__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__tdl_2__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__tdl_2__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_2__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_2__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__tdl_2__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_2__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_2__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_2__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_2__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_2__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__tdl_2__thread_header01_ready_port0__read; + counter->name = "Thread Header Ready on Slice0 Subslice1 Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 88; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__tdl_2__thread_header01_ready_port1__read; + counter->name = "Thread Header Ready on Slice0 Subslice1 Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 92; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_2__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_2__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = kblgt3__tdl_2__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_2__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_2__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_2__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__tdl_2__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__tdl_2__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 140; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__tdl_2__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__tdl_2__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__tdl_2__thread_header02_ready_port1__read; + counter->name = "Thread Header Ready on Slice0 Subslice2 Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__tdl_2__thread_header02_ready_port0__read; + counter->name = "Thread Header Ready on Slice0 Subslice2 Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_2__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__tdl_2__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_2__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_2__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__tdl_2__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_2__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_2__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_2__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_2__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_2__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_2__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_2__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__tdl_2__thread_header00_ready_port0__read; + counter->name = "Thread Header Ready on Slice0 Subslice0 Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 256; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__tdl_2__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__tdl_2__thread_header00_ready_port1__read; + counter->name = "Thread Header Ready on Slice0 Subslice0 Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 272; + counter->size = sizeof(float); + } + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog kblgt3_compute_extra_mux_regs[69]; + +static struct brw_perf_query_counter kblgt3_compute_extra_query_counters[5]; +static struct brw_perf_query_info kblgt3_compute_extra_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics Extra Gen9", + .guid = "efc497ac-884e-4ee4-a4a8-15fba22aaf21", + .counters = kblgt3_compute_extra_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = kblgt3_compute_extra_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ +}; + +static void +kblgt3_register_compute_extra_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &kblgt3_compute_extra_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121203E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123203E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125203E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x129203E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12B203E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12D203E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024EC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044EC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064EC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0042 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F006D }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06104000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06114000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06120033 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06131000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04308000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04318000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04321980 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00320000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04334000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04504000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04514000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04520033 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00520000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04531000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00AF8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ACC0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x008D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x028DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C8FB000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E8F0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06AC8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02AD4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02918000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02921980 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00920000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02934000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B04000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B14000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B20033 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B20000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B31000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D08000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D18000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D21980 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D34000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900420 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x459000A1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_extra__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_extra__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_extra__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__compute_extra__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = kblgt3__compute_extra__avg_gpu_core_frequency__max(brw); + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__compute_extra__fpu1_active_adjusted__read; + counter->name = "EU FPU1 Pipe Active including Ext Math"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing including Extended Math processing"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog kblgt3_vme_pipe_mux_regs[73]; +static struct brw_perf_query_register_prog kblgt3_vme_pipe_b_counter_regs[17]; +static struct brw_perf_query_register_prog kblgt3_vme_pipe_flex_regs[2]; + +static struct brw_perf_query_counter kblgt3_vme_pipe_query_counters[10]; +static struct brw_perf_query_info kblgt3_vme_pipe_query = { + .kind = OA_COUNTERS, + .name = "Media Vme Pipe Gen9", + .guid = "bfd9764d-2c5b-4c16-bfc1-89de3ca10917", + .counters = kblgt3_vme_pipe_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = kblgt3_vme_pipe_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = kblgt3_vme_pipe_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = kblgt3_vme_pipe_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +kblgt3_register_vme_pipe_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &kblgt3_vme_pipe_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141A5800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161A00C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12180240 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14180002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x149A5800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x169A00C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12980240 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14980002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E3FC0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F3000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C9500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CAA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C000A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04193000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081A28C1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00133000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0613C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0813F000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00172000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06178000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0817A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00180037 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06180940 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08180000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02180000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04183000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04AFC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06AF3000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ACC4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CCC0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E8F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x108F0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16ACA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18AC000A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06993000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9A28C1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x009A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A93F000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C93F000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A97A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C97A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A980977 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08980000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04980000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06983000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x119000FF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900004 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x479008A5 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100030 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF9 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FFFC }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FFF3 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100180 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFCF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FF3F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00008003 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__vme_pipe__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__vme_pipe__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__vme_pipe__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__vme_pipe__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__vme_pipe__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = kblgt3__vme_pipe__avg_gpu_core_frequency__max(brw); + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__vme_pipe__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__vme_pipe__eu_thread_occupancy__read; + counter->name = "EU Thread Occupancy"; + counter->desc = "The percentage of time in which hardware threads occupied EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__vme_pipe__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 44; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__vme_pipe__vme_busy__read; + counter->name = "VME Busy"; + counter->desc = "The percentage of time in which VME (IME or CRE) was actively processing data."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__vme_pipe__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 52; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog kblgt3_gpu_busyness_mux_regs[42]; +static struct brw_perf_query_register_prog kblgt3_gpu_busyness_b_counter_regs[7]; + +static struct brw_perf_query_counter kblgt3_gpu_busyness_query_counters[9]; +static struct brw_perf_query_info kblgt3_gpu_busyness_query = { + .kind = OA_COUNTERS, + .name = "Gpu Rings Busyness", + .guid = "b55ecba1-2aa9-422e-89ff-b9e30f03d447", + .counters = kblgt3_gpu_busyness_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = kblgt3_gpu_busyness_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = kblgt3_gpu_busyness_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ +}; + +static void +kblgt3_register_gpu_busyness_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &kblgt3_gpu_busyness_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19D05800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13805800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05962C25 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19950016 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19C05800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05D00085 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25D00000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09D54000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07800035 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21960000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0996C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B964000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930068 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15948000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B94000C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03957500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17950000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07928000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03988000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09978000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05C08500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25C00000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1BC00000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0BC54000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900463 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007C000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x000007FF }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__gpu_busyness__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__gpu_busyness__vebox_busy__read; + counter->name = "Vebox Ring Busy"; + counter->desc = "The percentage of time when vebox command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__gpu_busyness__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__gpu_busyness__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = kblgt3__gpu_busyness__avg_gpu_core_frequency__max(brw); + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__gpu_busyness__render_busy__read; + counter->name = "Render Ring Busy"; + counter->desc = "The percentage of time when render command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__gpu_busyness__vdbox0_busy__read; + counter->name = "Vdbox0 Ring Busy"; + counter->desc = "The percentage of time when Vdbox0 command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 36; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__gpu_busyness__blitter_busy__read; + counter->name = "Blitter Ring Busy"; + counter->desc = "The percentage of time when blitter command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__gpu_busyness__any_ring_busy__read; + counter->name = "AnyRingBusy"; + counter->desc = "The percentage of time when any command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 44; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = kblgt3__gpu_busyness__vdbox1_busy__read; + counter->name = "Vdbox1 Ring Busy"; + counter->desc = "The percentage of time when Vdbox1 command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog kblgt3_test_oa_mux_regs[13]; +static struct brw_perf_query_register_prog kblgt3_test_oa_b_counter_regs[22]; + +static struct brw_perf_query_counter kblgt3_test_oa_query_counters[12]; +static struct brw_perf_query_info kblgt3_test_oa_query = { + .kind = OA_COUNTERS, + .name = "MDAPI testing set Gen9", + .guid = "f1792f32-6db2-4b50-b4b2-557128f1688d", + .counters = kblgt3_test_oa_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = kblgt3_test_oa_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = kblgt3_test_oa_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ +}; + +static void +kblgt3_register_test_oa_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &kblgt3_test_oa_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07810013 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000004 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000003 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000007 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFF7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00100082 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFEF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x001000C2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FFE7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00100001 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FFE7 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__test_oa__counter7__read; + counter->name = "TestCounter7"; + counter->desc = "HW test counter 7. Factor: 0.666"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__test_oa__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 8; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__test_oa__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__test_oa__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = kblgt3__test_oa__avg_gpu_core_frequency__max(brw); + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__test_oa__counter8__read; + counter->name = "TestCounter8"; + counter->desc = "HW test counter 8. Should be equal to 1."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__test_oa__counter4__read; + counter->name = "TestCounter4"; + counter->desc = "HW test counter 4. Factor: 0.333"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__test_oa__counter5__read; + counter->name = "TestCounter5"; + counter->desc = "HW test counter 5. Factor: 0.333"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__test_oa__counter6__read; + counter->name = "TestCounter6"; + counter->desc = "HW test counter 6. Factor: 0.166"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__test_oa__counter3__read; + counter->name = "TestCounter3"; + counter->desc = "HW test counter 3. Factor: 0.5"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__test_oa__counter0__read; + counter->name = "TestCounter0"; + counter->desc = "HW test counter 0. Factor: 0.0"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__test_oa__counter1__read; + counter->name = "TestCounter1"; + counter->desc = "HW test counter 1. Factor: 1.0"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = kblgt3__test_oa__counter2__read; + counter->name = "TestCounter2"; + counter->desc = "HW test counter 2. Factor: 1.0"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +void +brw_oa_register_queries_kblgt3(struct brw_context *brw) +{ + kblgt3_register_render_basic_counter_query(brw); + kblgt3_register_compute_basic_counter_query(brw); + kblgt3_register_render_pipe_profile_counter_query(brw); + kblgt3_register_memory_reads_counter_query(brw); + kblgt3_register_memory_writes_counter_query(brw); + kblgt3_register_compute_extended_counter_query(brw); + kblgt3_register_compute_l3_cache_counter_query(brw); + kblgt3_register_hdc_and_sf_counter_query(brw); + kblgt3_register_l3_1_counter_query(brw); + kblgt3_register_l3_2_counter_query(brw); + kblgt3_register_l3_3_counter_query(brw); + kblgt3_register_rasterizer_and_pixel_backend_counter_query(brw); + kblgt3_register_sampler_counter_query(brw); + kblgt3_register_tdl_1_counter_query(brw); + kblgt3_register_tdl_2_counter_query(brw); + kblgt3_register_compute_extra_counter_query(brw); + kblgt3_register_vme_pipe_counter_query(brw); + kblgt3_register_gpu_busyness_counter_query(brw); + kblgt3_register_test_oa_counter_query(brw); +} + +static struct brw_perf_query_register_prog glk_render_basic_mux_regs[80]; +static struct brw_perf_query_register_prog glk_render_basic_b_counter_regs[5]; +static struct brw_perf_query_register_prog glk_render_basic_flex_regs[7]; + +static struct brw_perf_query_counter glk_render_basic_query_counters[52]; +static struct brw_perf_query_info glk_render_basic_query = { + .kind = OA_COUNTERS, + .name = "Render Metrics Basic Gen9", + .guid = "d72df5c7-5b4a-4274-a43f-00b0fd51fc68", + .counters = glk_render_basic_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = glk_render_basic_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = glk_render_basic_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = glk_render_basic_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +glk_register_render_basic_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &glk_render_basic_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C00F0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12120280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12320280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11930317 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x159303DF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x419000A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2D1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E0800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E5900 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4F0010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A6C0053 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0FCC00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C0F0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C2C0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00101000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04101000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00114000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08114000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08120021 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00141000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08141000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02308000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04302000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06318000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08318000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06320800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08320840 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00320000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06344000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08344000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D931831 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F939F3F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01939E80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x039303BC }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0593000E }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1993002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900177 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900187 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53901110 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900423 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900111 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C02 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59901111 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900421 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900821 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_basic__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__render_basic__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_basic__l3_misses__read; + counter->name = "L3 Misses"; + counter->desc = "The total number of L3 misses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_basic__gti_l3_throughput__read; + counter->name = "GTI L3 Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__render_basic__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_basic__sampler_l1_misses__read; + counter->name = "Sampler Cache Misses"; + counter->desc = "The total number of sampler cache misses in all LODs in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__render_basic__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x12) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__render_basic__sampler1_bottleneck__read; + counter->name = "Sampler 1 Bottleneck"; + counter->desc = "The percentage of time in which Sampler 1 has been slowing down the pipe when processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 52; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__render_basic__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_basic__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_basic__l3_sampler_throughput__read; + counter->name = "L3 Sampler Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_basic__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__render_basic__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 88; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_basic__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_basic__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x09) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__render_basic__sampler0_busy__read; + counter->name = "Sampler 0 Busy"; + counter->desc = "The percentage of time in which Sampler 0 has been processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 112; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x12) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__render_basic__sampler1_busy__read; + counter->name = "Sampler 1 Busy"; + counter->desc = "The percentage of time in which Sampler 1 has been processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 116; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__render_basic__samplers_busy__read; + counter->name = "Samplers Busy"; + counter->desc = "The percentage of time in which samplers have been processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 120; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_basic__gti_vf_throughput__read; + counter->name = "GTI Fixed Pipe Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between 3D Pipeline (Command Dispatch, Input Assembly and Stream Output) and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_basic__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x09) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__render_basic__sampler0_bottleneck__read; + counter->name = "Sampler 0 Bottleneck"; + counter->desc = "The percentage of time in which Sampler 0 has been slowing down the pipe when processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_basic__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_basic__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_basic__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_basic__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = glk__render_basic__avg_gpu_core_frequency__max(brw); + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_basic__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_basic__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_basic__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_basic__l3_lookups__read; + counter->name = "L3 Lookup Accesses w/o IC"; + counter->desc = "The total number of L3 cache lookup accesses w/o IC."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_basic__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_basic__gti_read_throughput__read; + counter->name = "GTI Read Throughput"; + counter->desc = "The total number of GPU memory bytes read from GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__render_basic__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 232; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__render_basic__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 236; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_basic__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__render_basic__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 248; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_basic__gti_depth_throughput__read; + counter->name = "GTI Depth Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between depth caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__render_basic__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 264; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__render_basic__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 268; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_basic__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_basic__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__render_basic__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 288; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_basic__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_basic__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__render_basic__sampler_bottleneck__read; + counter->name = "Samplers Bottleneck"; + counter->desc = "The percentage of time in which samplers have been slowing down the pipe when processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 312; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_basic__gti_hdc_lookups_throughput__read; + counter->name = "GTI HDC TLB Lookup Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between GTI and HDC, when HDC is doing TLB lookups."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_basic__gti_rcc_throughput__read; + counter->name = "GTI RCC Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between render color caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 328; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_basic__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 336; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_basic__gti_write_throughput__read; + counter->name = "GTI Write Throughput"; + counter->desc = "The total number of GPU memory bytes written to GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 344; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_basic__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 352; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_basic__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 360; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_basic__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 368; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_basic__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 376; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog glk_compute_basic_mux_regs[72]; +static struct brw_perf_query_register_prog glk_compute_basic_b_counter_regs[5]; +static struct brw_perf_query_register_prog glk_compute_basic_flex_regs[7]; + +static struct brw_perf_query_counter glk_compute_basic_query_counters[39]; +static struct brw_perf_query_info glk_compute_basic_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics Basic Gen9", + .guid = "814285f6-354d-41d2-ba49-e24e622714a0", + .counters = glk_compute_basic_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = glk_compute_basic_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = glk_compute_basic_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = glk_compute_basic_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +glk_register_compute_basic_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &glk_compute_basic_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F00E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124F1C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x39900340 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2D1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E1400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E5100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102E0114 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x164C2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004F6B42 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F6200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084F4100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4F0061 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4F6C4C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4F4B00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x180F5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0F8800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C0F08A2 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C2C1451 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E2C0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2C0010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19938A28 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19900177 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B900178 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900125 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900123 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53901000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900111 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_basic__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_basic__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_basic__untyped_bytes_read__read; + counter->name = "Untyped Bytes Read"; + counter->desc = "The total number of typed memory bytes read via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_basic__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_basic__typed_bytes_written__read; + counter->name = "Typed Bytes Written"; + counter->desc = "The total number of untyped memory bytes written via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_basic__fpu0_active__read; + counter->name = "EU FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_basic__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 44; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_basic__eu_avg_ipc_rate__read; + counter->name = "EU AVG IPC Rate"; + counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 2.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_basic__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_basic__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_basic__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_basic__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_basic__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_basic__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_basic__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_basic__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_basic__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = glk__compute_basic__avg_gpu_core_frequency__max(brw); + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_basic__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_basic__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_basic__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_basic__gti_read_throughput__read; + counter->name = "GTI Read Throughput"; + counter->desc = "The total number of GPU memory bytes read from GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_basic__untyped_bytes_written__read; + counter->name = "Untyped Writes"; + counter->desc = "The total number of untyped memory bytes written via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_basic__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_basic__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_basic__typed_bytes_read__read; + counter->name = "Typed Bytes Read"; + counter->desc = "The total number of typed memory bytes read via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_basic__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_basic__eu_thread_occupancy__read; + counter->name = "EU Thread Occupancy"; + counter->desc = "The percentage of time in which hardware threads occupied EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_basic__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 204; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_basic__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_basic__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_basic__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_basic__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_basic__gti_write_throughput__read; + counter->name = "GTI Write Throughput"; + counter->desc = "The total number of GPU memory bytes written to GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_basic__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_basic__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_basic__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_basic__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_basic__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_basic__eu_send_active__read; + counter->name = "EU Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 288; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog glk_render_pipe_profile_mux_regs[94]; +static struct brw_perf_query_register_prog glk_render_pipe_profile_b_counter_regs[21]; +static struct brw_perf_query_register_prog glk_render_pipe_profile_flex_regs[7]; + +static struct brw_perf_query_counter glk_render_pipe_profile_query_counters[43]; +static struct brw_perf_query_info glk_render_pipe_profile_query = { + .kind = OA_COUNTERS, + .name = "Render Metrics for 3D Pipeline Profile Gen9", + .guid = "07d397a6-b3e6-49f6-9433-a4f293d55978", + .counters = glk_render_pipe_profile_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = glk_render_pipe_profile_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = glk_render_pipe_profile_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = glk_render_pipe_profile_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +glk_register_render_pipe_profile_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &glk_render_pipe_profile_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E001F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10186800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810019 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15810013 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13820020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11830020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17840000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11860007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21860000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178703E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022E5400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002E0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E0080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082F0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06143000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06174000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06180012 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00180000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D804000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F804000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05804000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09810200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B810030 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03810003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21819140 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23819050 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25810018 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B820980 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03820D80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11820000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0182C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07828000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09824000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F828000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D830004 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0583000C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F831000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01848072 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11840000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09844000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07860000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09860092 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F860400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01869100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F870065 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01870000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19930800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B952000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D955055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F951455 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0992A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F928000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1192A800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1392028A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B92A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D922000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900C01 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900863 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900061 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C22 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFEA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFC }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007AFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F5FD }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00079FFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000F3FB }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007BF7A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F7E7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FEFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000F7CF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00077FFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000EFDF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0006FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000CFBF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0003FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x00005F7F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_pipe_profile__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__render_pipe_profile__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__render_pipe_profile__vs_bottleneck__read; + counter->name = "VS Bottleneck"; + counter->desc = "The percentage of time in which vertex shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__render_pipe_profile__hi_depth_bottleneck__read; + counter->name = "Hi-Depth Bottleneck"; + counter->desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__render_pipe_profile__gs_bottleneck__read; + counter->name = "GS Bottleneck"; + counter->desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_pipe_profile__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_pipe_profile__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_pipe_profile__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_pipe_profile__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__render_pipe_profile__bc_bottleneck__read; + counter->name = "BC Bottleneck"; + counter->desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__render_pipe_profile__hs_stall__read; + counter->name = "HS Stall"; + counter->desc = "The percentage of time in which hull stall pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 60; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_pipe_profile__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_pipe_profile__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_pipe_profile__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_pipe_profile__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_pipe_profile__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = glk__render_pipe_profile__avg_gpu_core_frequency__max(brw); + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_pipe_profile__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_pipe_profile__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__render_pipe_profile__vf_bottleneck__read; + counter->name = "VF Bottleneck"; + counter->desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_pipe_profile__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__render_pipe_profile__sf_bottleneck__read; + counter->name = "Strip-Fans Bottleneck"; + counter->desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__render_pipe_profile__sf_stall__read; + counter->name = "SF Stall"; + counter->desc = "The percentage of time in which strip-fans pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 140; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__render_pipe_profile__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__render_pipe_profile__hs_bottleneck__read; + counter->name = "HS Bottleneck"; + counter->desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__render_pipe_profile__cl_stall__read; + counter->name = "CL Stall"; + counter->desc = "The percentage of time in which clipper pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__render_pipe_profile__so_bottleneck__read; + counter->name = "SO Bottleneck"; + counter->desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_pipe_profile__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_pipe_profile__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_pipe_profile__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__render_pipe_profile__ds_bottleneck__read; + counter->name = "DS Bottleneck"; + counter->desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__render_pipe_profile__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 188; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__render_pipe_profile__cl_bottleneck__read; + counter->name = "Clipper Bottleneck"; + counter->desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__render_pipe_profile__ds_stall__read; + counter->name = "DS Stall"; + counter->desc = "The percentage of time in which domain shader pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 196; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__render_pipe_profile__early_depth_bottleneck__read; + counter->name = "Early Depth Bottleneck"; + counter->desc = "The percentage of time in which early depth test pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_pipe_profile__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_pipe_profile__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_pipe_profile__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_pipe_profile__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_pipe_profile__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_pipe_profile__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_pipe_profile__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__render_pipe_profile__so_stall__read; + counter->name = "SO Stall"; + counter->desc = "The percentage of time in which stream-output pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__render_pipe_profile__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog glk_memory_reads_mux_regs[44]; +static struct brw_perf_query_register_prog glk_memory_reads_b_counter_regs[32]; +static struct brw_perf_query_register_prog glk_memory_reads_flex_regs[7]; + +static struct brw_perf_query_counter glk_memory_reads_query_counters[41]; +static struct brw_perf_query_info glk_memory_reads_query = { + .kind = OA_COUNTERS, + .name = "Memory Reads Distribution Gen9", + .guid = "1a356946-5428-450b-a2f0-89f8783a302d", + .counters = glk_memory_reads_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = glk_memory_reads_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = glk_memory_reads_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = glk_memory_reads_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +glk_register_memory_reads_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &glk_memory_reads_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19800343 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x39900340 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F901000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03803180 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058035E2 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0780006A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2181A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2381000A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950550 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B928000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D92A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F922000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900170 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21900171 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23900172 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25900173 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27900174 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900175 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B900176 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D900177 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F90017F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900125 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900123 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900121 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43901084 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47901080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49901084 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B901084 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900004 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000272C, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002728, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000271C, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002718, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F872 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_reads__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__memory_reads__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_reads__gti_l3_bank0_reads__read; + counter->name = "GtiL3Bank0Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 0 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_reads__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_reads__gti_ring_accesses__read; + counter->name = "GtiRingAccesses"; + counter->desc = "The total number of all accesses from GTI to the ring."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_reads__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_reads__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_reads__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_reads__gti_l3_bank3_reads__read; + counter->name = "GtiL3Bank3Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 3 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_reads__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_reads__gti_rs_memory_reads__read; + counter->name = "GtiRsMemoryReads"; + counter->desc = "The total number of GTI memory reads from Resource Streamer."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_reads__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_reads__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_reads__gti_hiz_memory_reads__read; + counter->name = "GtiHizMemoryReads"; + counter->desc = "The total number of GTI memory reads from Hierarchical Depth Cache (Hi-Depth Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_reads__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_reads__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = glk__memory_reads__avg_gpu_core_frequency__max(brw); + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_reads__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_reads__gti_rcc_memory_reads__read; + counter->name = "GtiRccMemoryReads"; + counter->desc = "The total number of GTI memory reads from Render Color Cache (Render Color Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_reads__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_reads__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_reads__gti_l3_bank1_reads__read; + counter->name = "GtiL3Bank1Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 1 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__memory_reads__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_reads__gti_cmd_streamer_memory_reads__read; + counter->name = "GtiCmdStreamerMemoryReads"; + counter->desc = "The total number of GTI memory reads from Command Streamer."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_reads__gti_l3_bank2_reads__read; + counter->name = "GtiL3Bank2Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 2 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_reads__gti_memory_reads__read; + counter->name = "GtiMemoryReads"; + counter->desc = "The total number of GTI memory reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_reads__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_reads__gti_rcz_memory_reads__read; + counter->name = "GtiRczMemoryReads"; + counter->desc = "The total number of GTI memory reads from Render Depth Cache (Render Depth Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_reads__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_reads__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__memory_reads__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 232; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_reads__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_reads__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_reads__gti_msc_memory_reads__read; + counter->name = "GtiMscMemoryReads"; + counter->desc = "The total number of GTI memory reads from Multisampling Color Cache (Multisampling Color Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_reads__gti_vf_memory_reads__read; + counter->name = "GtiVfMemoryReads"; + counter->desc = "The total number of GTI memory reads from Vertex Fetch."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_reads__gti_stc_memory_reads__read; + counter->name = "GtiStcMemoryReads"; + counter->desc = "The total number of GTI memory reads from Stencil Cache (Stencil Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_reads__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_reads__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_reads__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_reads__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_reads__gti_l3_reads__read; + counter->name = "GtiL3Reads"; + counter->desc = "The total number of GTI memory reads from L3 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_reads__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog glk_memory_writes_mux_regs[44]; +static struct brw_perf_query_register_prog glk_memory_writes_b_counter_regs[32]; +static struct brw_perf_query_register_prog glk_memory_writes_flex_regs[7]; + +static struct brw_perf_query_counter glk_memory_writes_query_counters[41]; +static struct brw_perf_query_info glk_memory_writes_query = { + .kind = OA_COUNTERS, + .name = "Memory Writes Distribution Gen9", + .guid = "5299be9d-7a61-4c99-9f81-f87e6c5aaca9", + .counters = glk_memory_writes_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = glk_memory_writes_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = glk_memory_writes_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = glk_memory_writes_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +glk_register_memory_writes_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &glk_memory_writes_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19800343 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x39900340 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03803180 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x058035E2 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0780006A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2181A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2381000A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950550 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B928000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D92A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F922000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900180 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21900181 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23900182 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25900183 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27900184 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900185 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B900186 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D900187 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F900170 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900125 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900123 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900121 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43901084 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47901080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49901084 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B901084 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900004 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000272C, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002728, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000271C, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002718, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F822 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_writes__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__memory_writes__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_writes__gti_memory_writes__read; + counter->name = "GtiMemoryWrites"; + counter->desc = "The total number of GTI memory writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_writes__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_writes__gti_ring_accesses__read; + counter->name = "GtiRingAccesses"; + counter->desc = "The total number of all GTI accesses to the ring."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_writes__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_writes__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_writes__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_writes__gti_msc_memory_writes__read; + counter->name = "GtiMscMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Multisampling Color Cache (Multisampling Color Cache invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_writes__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_writes__gti_cmd_streamer_memory_writes__read; + counter->name = "GtiCmdStreamerMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Command Streamer."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_writes__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_writes__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_writes__gti_l3_bank0_writes__read; + counter->name = "GtiL3Bank0Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 0 (L3 Bank 0 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_writes__gti_l3_bank1_writes__read; + counter->name = "GtiL3Bank1Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 1 (L3 Bank 1 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_writes__gti_l3_bank2_writes__read; + counter->name = "GtiL3Bank2Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 2 (L3 Bank 2 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_writes__gti_l3_bank3_writes__read; + counter->name = "GtiL3Bank3Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 3 (L3 Bank 3 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_writes__gti_l3_writes__read; + counter->name = "GtiL3Writes"; + counter->desc = "The total number of GTI memory writes from L3 (L3 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_writes__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_writes__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = glk__memory_writes__avg_gpu_core_frequency__max(brw); + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_writes__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_writes__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_writes__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_writes__gti_rcc_memory_writes__read; + counter->name = "GtiRccMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Render Color Cache (Render Color Cache invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_writes__gti_so_memory_writes__read; + counter->name = "GtiSoMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Stream Output."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__memory_writes__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_writes__gti_stc_memory_writes__read; + counter->name = "GtiStcMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Stencil Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_writes__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_writes__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_writes__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__memory_writes__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 240; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_writes__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_writes__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_writes__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_writes__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_writes__gti_rcz_memory_writes__read; + counter->name = "GtiRczMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Render Depth Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_writes__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_writes__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_writes__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_writes__gti_hiz_memory_writes__read; + counter->name = "GtiHizMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Hierarchical Depth Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__memory_writes__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog glk_compute_extended_mux_regs[93]; +static struct brw_perf_query_register_prog glk_compute_extended_b_counter_regs[21]; +static struct brw_perf_query_register_prog glk_compute_extended_flex_regs[7]; + +static struct brw_perf_query_counter glk_compute_extended_query_counters[38]; +static struct brw_perf_query_info glk_compute_extended_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics Extended Gen9", + .guid = "bc9bcff2-459a-4cbc-986d-a84b077153f3", + .counters = glk_compute_extended_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = glk_compute_extended_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = glk_compute_extended_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = glk_compute_extended_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +glk_register_compute_extended_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &glk_compute_extended_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F00E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C0160 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C0120 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E5400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E5515 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102E0155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x144C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x164C2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4F4B41 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004F4200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024F404C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001C0031 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061C1900 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081C1A33 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1C1B35 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1C3337 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041C31C7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x180F5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0FA8AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C0F0AAA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C2C6AAA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E2C0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2C2950 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1993AAAA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900420 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900001 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FC2A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FC6A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007FC92 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007FCA2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FC32 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FC9A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007FE6A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007FE7A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000BF00 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_extended__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_extended__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_extended__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_extended__fpu0_active__read; + counter->name = "EU FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_extended__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_extended__eu_avg_ipc_rate__read; + counter->name = "EU AVG IPC Rate"; + counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 2.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_extended__typed_writes0__read; + counter->name = "Typed Writes 0"; + counter->desc = "The subslice 0 typed writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_extended__eu_typed_atomics0__read; + counter->name = "EuTypedAtomics0"; + counter->desc = "The subslice 0 EU Typed Atomics subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_extended__typed_atomics0__read; + counter->name = "Typed Atomics 0"; + counter->desc = "The subslice 0 typed atomics."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_extended__typed_atomics_per_cache_line__read; + counter->name = "TypedAtomicsPerCacheLine"; + counter->desc = "The ratio of EU typed atomics requests to L3 cache line writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_extended__eu_untyped_reads0__read; + counter->name = "EuUntypedReads0"; + counter->desc = "The subslice 0 EU Untyped Reads subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_extended__untyped_writes0__read; + counter->name = "Untyped Writes 0"; + counter->desc = "The subslice 0 untyped writes (including SLM writes)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_extended__eu_untyped_atomics0__read; + counter->name = "EuUntypedAtomics0"; + counter->desc = "The subslice 0 EU Untyped Atomics subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_extended__eu_untyped_writes0__read; + counter->name = "EuUntypedWrites0"; + counter->desc = "The subslice 0 EU Untyped Writes subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_extended__eu_a64_untyped_writes0__read; + counter->name = "EuA64UntypedWrites0"; + counter->desc = "The subslice 0 EU A64 Untyped Writes subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_extended__untyped_writes_per_cache_line__read; + counter->name = "UntypedWritesPerCacheLine"; + counter->desc = "The ratio of EU untyped write requests to L3 cache line writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_extended__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_extended__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_extended__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_extended__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = glk__compute_extended__avg_gpu_core_frequency__max(brw); + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_extended__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_extended__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_extended__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_extended__eu_typed_writes0__read; + counter->name = "EuTypedWrites0"; + counter->desc = "The subslice 0 EU Typed Writes subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_extended__typed_writes_per_cache_line__read; + counter->name = "TypedWritesPerCacheLine"; + counter->desc = "The ratio of EU typed write requests to L3 cache line writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_extended__typed_reads0__read; + counter->name = "Typed Reads 0"; + counter->desc = "The subslice 0 typed reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_extended__untyped_reads0__read; + counter->name = "Untyped Reads 0"; + counter->desc = "The subslice 0 untyped reads (including SLM reads)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_extended__eu_a64_untyped_reads0__read; + counter->name = "EuA64UntypedReads0"; + counter->desc = "The subslice 0 EU A64 Untyped Reads subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_extended__eu_thread_occupancy__read; + counter->name = "EU Thread Occupancy"; + counter->desc = "The percentage of time in which hardware threads occupied EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 208; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_extended__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 212; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_extended__eu_typed_reads0__read; + counter->name = "EuTypedReads0"; + counter->desc = "The subslice 0 EU Typed Reads subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_extended__untyped_reads_per_cache_line__read; + counter->name = "UntypedReadsPerCacheLine"; + counter->desc = "The ratio of EU untyped read requests to L3 cache line reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_extended__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_extended__typed_reads_per_cache_line__read; + counter->name = "TypedReadsPerCacheLine"; + counter->desc = "The ratio of EU typed read requests to L3 cache line reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_extended__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_extended__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_extended__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_extended__eu_send_active__read; + counter->name = "EU Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 272; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog glk_compute_l3_cache_mux_regs[68]; +static struct brw_perf_query_register_prog glk_compute_l3_cache_b_counter_regs[13]; +static struct brw_perf_query_register_prog glk_compute_l3_cache_flex_regs[7]; + +static struct brw_perf_query_counter glk_compute_l3_cache_query_counters[54]; +static struct brw_perf_query_info glk_compute_l3_cache_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics L3 Cache Gen9", + .guid = "88ec931f-5b4a-453a-9db6-a61232b6143d", + .counters = glk_compute_l3_cache_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = glk_compute_l3_cache_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = glk_compute_l3_cache_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = glk_compute_l3_cache_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +glk_register_compute_l3_cache_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &glk_compute_l3_cache_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C03B0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1593001E }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E0400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E1500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102E0140 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x144C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x164C2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4F4001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4F5005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0051 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C5C5D }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C5E5F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x180F1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0FA800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C0F0A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C2C4015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E2C0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03931980 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05930032 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1993A00A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900177 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900178 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53901000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900111 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900400 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FEFE }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FEFD }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FBEF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FBDF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00101100 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00201200 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00301300 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00401400 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_l3_cache__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_l3_cache__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_l3_cache__l3_bank03_accesses__read; + counter->name = "L3 Bank 03 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 03."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_l3_cache__l3_accesses__read; + counter->name = "L3 Accesses"; + counter->desc = "The total number of L3 accesses from all entities."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_l3_cache__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_l3_cache__l3_sampler_throughput__read; + counter->name = "L3 Sampler Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_l3_cache__fpu0_active__read; + counter->name = "EU FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_l3_cache__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 52; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_l3_cache__eu_avg_ipc_rate__read; + counter->name = "EU AVG IPC Rate"; + counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 2.0; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_l3_cache__eu_binary_fpu0_instruction__read; + counter->name = "EU FPU0 Binary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 60; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_l3_cache__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_l3_cache__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_l3_cache__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_l3_cache__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_l3_cache__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_l3_cache__eu_hybrid_fpu0_instruction__read; + counter->name = "EU FPU0 Hybrid Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 104; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_l3_cache__l3_misses__read; + counter->name = "L3 Misses"; + counter->desc = "The total number of L3 misses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_l3_cache__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_l3_cache__l3_bank00_accesses__read; + counter->name = "L3 Bank 00 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 00."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_l3_cache__eu_move_fpu0_instruction__read; + counter->name = "EU FPU0 Move Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_l3_cache__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_l3_cache__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_l3_cache__eu_hybrid_fpu1_instruction__read; + counter->name = "EU FPU1 Hybrid Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_l3_cache__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_l3_cache__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = glk__compute_l3_cache__avg_gpu_core_frequency__max(brw); + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_l3_cache__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_l3_cache__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_l3_cache__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_l3_cache__gti_read_throughput__read; + counter->name = "GTI Read Throughput"; + counter->desc = "The total number of GPU memory bytes read from GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_l3_cache__gti_l3_throughput__read; + counter->name = "GTI L3 Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_l3_cache__l3_bank00_ic_accesses__read; + counter->name = "L3 Bank 00 IC Accesses"; + counter->desc = "The total number of accesses to L3 Bank 00 from IC cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + } + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_l3_cache__l3_bank00_ic_hits__read; + counter->name = "L3 Bank 00 IC Hits"; + counter->desc = "The total number of hits in L3 Bank 00 from IC cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_l3_cache__sampler_accesses__read; + counter->name = "Sampler Accesses"; + counter->desc = "The total number of messages send to samplers."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_l3_cache__l3_bank01_accesses__read; + counter->name = "L3 Bank 01 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 01."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_l3_cache__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 256; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_l3_cache__eu_ternary_fpu0_instruction__read; + counter->name = "EU FPU0 Ternary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 260; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_l3_cache__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_l3_cache__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_l3_cache__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_l3_cache__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_l3_cache__eu_move_fpu1_instruction__read; + counter->name = "EU FPU1 Move Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 296; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_l3_cache__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 300; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_l3_cache__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_l3_cache__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_l3_cache__l3_bank02_accesses__read; + counter->name = "L3 Bank 02 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 02."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_l3_cache__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 328; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_l3_cache__l3_total_throughput__read; + counter->name = "L3 Total Throughput"; + counter->desc = "The total number of GPU memory bytes transferred via L3."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 336; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_l3_cache__gti_write_throughput__read; + counter->name = "GTI Write Throughput"; + counter->desc = "The total number of GPU memory bytes written to GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 344; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_l3_cache__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 352; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_l3_cache__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 360; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_l3_cache__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 368; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_l3_cache__eu_binary_fpu1_instruction__read; + counter->name = "EU FPU1 Binary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 376; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_l3_cache__eu_ternary_fpu1_instruction__read; + counter->name = "EU FPU1 Ternary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 380; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_l3_cache__eu_send_active__read; + counter->name = "EU Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 384; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog glk_hdc_and_sf_mux_regs[42]; +static struct brw_perf_query_register_prog glk_hdc_and_sf_b_counter_regs[8]; +static struct brw_perf_query_register_prog glk_hdc_and_sf_flex_regs[7]; + +static struct brw_perf_query_counter glk_hdc_and_sf_query_counters[38]; +static struct brw_perf_query_info glk_hdc_and_sf_query = { + .kind = OA_COUNTERS, + .name = "Metric set HDCAndSF", + .guid = "530d176d-2a18-4014-adf8-1500c6c60835", + .counters = glk_hdc_and_sf_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = glk_hdc_and_sf_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = glk_hdc_and_sf_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = glk_hdc_and_sf_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +glk_register_hdc_and_sf_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &glk_hdc_and_sf_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F0232 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124F4640 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11834400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E0055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024F6100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044F416B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F004B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0F02A8 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2C5500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25810020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8305C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F951000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13920200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FDFF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__hdc_and_sf__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__hdc_and_sf__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__hdc_and_sf__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__hdc_and_sf__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__hdc_and_sf__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__hdc_and_sf__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__hdc_and_sf__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__hdc_and_sf__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__hdc_and_sf__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__hdc_and_sf__poly_data_ready__read; + counter->name = "Polygon Data Ready"; + counter->desc = "The percentage of time in which geometry pipeline output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__hdc_and_sf__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__hdc_and_sf__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__hdc_and_sf__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__hdc_and_sf__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__hdc_and_sf__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__hdc_and_sf__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = glk__hdc_and_sf__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__hdc_and_sf__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read; + counter->name = "HDC stalled by L3 (s0.ss1)"; + counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss1)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 120; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__hdc_and_sf__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__hdc_and_sf__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__hdc_and_sf__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__hdc_and_sf__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__hdc_and_sf__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__hdc_and_sf__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__hdc_and_sf__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__hdc_and_sf__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__hdc_and_sf__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__hdc_and_sf__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__hdc_and_sf__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__hdc_and_sf__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__hdc_and_sf__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__hdc_and_sf__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__hdc_and_sf__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__hdc_and_sf__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__hdc_and_sf__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__hdc_and_sf__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read; + counter->name = "HDC stalled by L3 (s0.ss0)"; + counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss0)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 256; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__hdc_and_sf__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog glk_l3_1_mux_regs[77]; +static struct brw_perf_query_register_prog glk_l3_1_b_counter_regs[22]; +static struct brw_perf_query_register_prog glk_l3_1_flex_regs[7]; + +static struct brw_perf_query_counter glk_l3_1_query_counters[39]; +static struct brw_perf_query_info glk_l3_1_query = { + .kind = OA_COUNTERS, + .name = "Metric set L3_1", + .guid = "fdee5a5a-f23c-43d1-aa73-f6257c71671d", + .counters = glk_l3_1_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = glk_l3_1_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = glk_l3_1_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = glk_l3_1_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +glk_register_l3_1_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &glk_l3_1_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12643400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12653400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C6800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C001E }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C0010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102E0154 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E0055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x144C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x164C2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4F5500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4F1554 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A640024 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10640000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04640000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C650024 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10650000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06650000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C6C5327 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C5425 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C2A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C285B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C005C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0900 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C0F0AA0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x180F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0F02AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C2C5400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E2C0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2C5550 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1993AA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900421 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900420 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900021 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00014002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000C3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00010002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000C7FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00004002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000D3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100700 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FF1F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00001402 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FC3F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00001002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FC7F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00000402 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FD3F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__l3_1__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__l3_1__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__l3_1__l30_bank1_active__read; + counter->name = "Slice0 L3 Bank1 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank1 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__l3_1__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__l3_1__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__l3_1__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__l3_1__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__l3_1__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__l3_1__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__l3_1__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__l3_1__l30_bank1_stalled__read; + counter->name = "Slice0 L3 Bank1 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank1 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__l3_1__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__l3_1__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__l3_1__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__l3_1__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__l3_1__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__l3_1__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = glk__l3_1__avg_gpu_core_frequency__max(brw); + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__l3_1__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__l3_1__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__l3_1__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__l3_1__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__l3_1__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__l3_1__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__l3_1__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__l3_1__l30_bank0_active__read; + counter->name = "Slice0 L3 Bank0 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank0 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__l3_1__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__l3_1__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__l3_1__l30_bank0_stalled__read; + counter->name = "Slice0 L3 Bank0 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank0 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 180; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__l3_1__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__l3_1__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__l3_1__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__l3_1__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__l3_1__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__l3_1__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__l3_1__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__l3_1__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__l3_1__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__l3_1__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__l3_1__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog glk_rasterizer_and_pixel_backend_mux_regs[41]; +static struct brw_perf_query_register_prog glk_rasterizer_and_pixel_backend_b_counter_regs[10]; +static struct brw_perf_query_register_prog glk_rasterizer_and_pixel_backend_flex_regs[7]; + +static struct brw_perf_query_counter glk_rasterizer_and_pixel_backend_query_counters[40]; +static struct brw_perf_query_info glk_rasterizer_and_pixel_backend_query = { + .kind = OA_COUNTERS, + .name = "Metric set RasterizerAndPixelBackend", + .guid = "6617623e-ca73-4791-b2b7-ddedd0846a0c", + .counters = glk_rasterizer_and_pixel_backend_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = glk_rasterizer_and_pixel_backend_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = glk_rasterizer_and_pixel_backend_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = glk_rasterizer_and_pixel_backend_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +glk_register_rasterizer_and_pixel_backend_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &glk_rasterizer_and_pixel_backend_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102D7800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x122D79E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2F0004 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100E3800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x180F0005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D0940 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022D802F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D4013 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E0050 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F0010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040E0480 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000E0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060F0027 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0F0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x439014A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x459000A4 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000EFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00006000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F3FF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__rasterizer_and_pixel_backend__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__rasterizer_and_pixel_backend__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__rasterizer_and_pixel_backend__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__rasterizer_and_pixel_backend__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__rasterizer_and_pixel_backend__pixel_values0_ready__read; + counter->name = "Slice0 Pixel Values Ready"; + counter->desc = "The percentage of time in which slice0 pixel values are ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = glk__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__rasterizer_and_pixel_backend__rasterizer0_input_available__read; + counter->name = "Slice0 Rasterizer Input Available"; + counter->desc = "The percentage of time in which slice0 rasterizer input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 128; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__rasterizer_and_pixel_backend__pixel_data0_ready__read; + counter->name = "Slice0 Post-EarlyZ Pixel Data Ready"; + counter->desc = "The percentage of time in which slice0 post-EarlyZ pixel data is ready (after early Z tests have been applied)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 132; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__rasterizer_and_pixel_backend__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__rasterizer_and_pixel_backend__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__rasterizer_and_pixel_backend__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__rasterizer_and_pixel_backend__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__rasterizer_and_pixel_backend__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__rasterizer_and_pixel_backend__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__rasterizer_and_pixel_backend__rasterizer0_output_ready__read; + counter->name = "Slice0 Rasterizer Output Ready"; + counter->desc = "The percentage of time in which slice0 rasterizer output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 196; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__rasterizer_and_pixel_backend__ps_output0_available__read; + counter->name = "Slice0 PS Output Available"; + counter->desc = "The percentage of time in which slice0 PS output is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 256; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__rasterizer_and_pixel_backend__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog glk_sampler_mux_regs[93]; +static struct brw_perf_query_register_prog glk_sampler_b_counter_regs[12]; +static struct brw_perf_query_register_prog glk_sampler_flex_regs[7]; + +static struct brw_perf_query_counter glk_sampler_query_counters[41]; +static struct brw_perf_query_info glk_sampler_query = { + .kind = OA_COUNTERS, + .name = "Metric set Sampler", + .guid = "f3b2ea63-e82e-4234-b418-44dd20dd34d0", + .counters = glk_sampler_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = glk_sampler_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = glk_sampler_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = glk_sampler_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +glk_register_sampler_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &glk_sampler_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121300A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141600AB }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123300A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143600AB }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125300A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145600AB }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102E01A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E0065 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x164C2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C0F0800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x180F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0F023F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E2C0003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2CC030 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04132180 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02130000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C148000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E142000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04148000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E150140 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C150040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C163000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E160068 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10160000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18160000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A164000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04330043 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02330000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0234A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04342000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C350015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02363460 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10360000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04360000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06360000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08364000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06530043 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02530000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E548000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00548000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06542000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E550400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A552000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C550100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E563000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00563400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10560000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18560000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02560000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C564000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1993A800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B9014A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900820 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45901022 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x70800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0000C000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000E7FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00003000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F9FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000C00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE7F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__sampler__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__sampler__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__sampler__sampler02_input_available__read; + counter->name = "Slice0 Subslice2 Input Available"; + counter->desc = "The percentage of time in which slice0 subslice2 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__sampler__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__sampler__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__sampler__sampler00_input_available__read; + counter->name = "Slice0 Subslice0 Input Available"; + counter->desc = "The percentage of time in which slice0 subslice0 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__sampler__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 28; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__sampler__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__sampler__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__sampler__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__sampler__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__sampler__sampler02_output_ready__read; + counter->name = "Slice0 Subslice2 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice0 subslice2 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__sampler__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__sampler__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__sampler__sampler01_input_available__read; + counter->name = "Slice0 Subslice1 Input Available"; + counter->desc = "The percentage of time in which slice0 subslice1 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 88; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__sampler__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__sampler__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__sampler__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__sampler__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = glk__sampler__avg_gpu_core_frequency__max(brw); + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__sampler__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__sampler__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__sampler__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__sampler__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__sampler__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__sampler__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__sampler__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 164; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__sampler__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__sampler__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__sampler__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__sampler__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__sampler__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__sampler__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__sampler__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__sampler__sampler00_output_ready__read; + counter->name = "Slice0 Subslice0 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice0 subslice0 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 224; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__sampler__sampler01_output_ready__read; + counter->name = "Slice0 Subslice1 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice0 subslice1 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 228; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__sampler__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__sampler__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__sampler__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__sampler__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__sampler__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__sampler__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog glk_tdl_1_mux_regs[86]; +static struct brw_perf_query_register_prog glk_tdl_1_b_counter_regs[18]; +static struct brw_perf_query_register_prog glk_tdl_1_flex_regs[7]; + +static struct brw_perf_query_counter glk_tdl_1_query_counters[41]; +static struct brw_perf_query_info glk_tdl_1_query = { + .kind = OA_COUNTERS, + .name = "Metric set TDL_1", + .guid = "14411d35-cbf6-4f5e-b68b-190faf9a1a83", + .counters = glk_tdl_1_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = glk_tdl_1_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = glk_tdl_1_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = glk_tdl_1_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +glk_register_tdl_1_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &glk_tdl_1_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102E0150 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E006A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x144C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x164C2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024E2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C0F0BC0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x180F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0F0302 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E2C0003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2C00F0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021A3080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041A31E5 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02148000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0414A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C150054 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06168000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08168000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A168000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3A3280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E3A0063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x063A0061 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x023A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C348000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E342000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06342000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E350140 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C350100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18360028 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C368000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5A3080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005A3280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025A0063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E548000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00548000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02542000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E550400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A552000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C550001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18560080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02568000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04568000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1993A800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900420 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45901084 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900001 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00009FFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000EFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FDFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE7F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_1__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__tdl_1__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__tdl_1__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__tdl_1__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__tdl_1__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_1__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_1__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__tdl_1__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_1__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_1__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__tdl_1__non_ps_thread02_ready_for_dispatch__read; + counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice2"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_1__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_1__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_1__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_1__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_1__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = glk__tdl_1__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_1__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__tdl_1__non_ps_thread00_ready_for_dispatch__read; + counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice0"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 120; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_1__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_1__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__tdl_1__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__tdl_1__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__tdl_1__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__tdl_1__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__tdl_1__ps_thread00_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice0"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_1__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__tdl_1__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_1__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_1__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__tdl_1__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_1__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_1__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__tdl_1__ps_thread01_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice1"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 224; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_1__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_1__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__tdl_1__ps_thread02_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice2"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 248; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_1__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_1__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_1__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_1__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__tdl_1__non_ps_thread01_ready_for_dispatch__read; + counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice1"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 288; + counter->size = sizeof(float); + } + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog glk_tdl_2_mux_regs[58]; +static struct brw_perf_query_register_prog glk_tdl_2_b_counter_regs[6]; +static struct brw_perf_query_register_prog glk_tdl_2_flex_regs[7]; + +static struct brw_perf_query_counter glk_tdl_2_query_counters[41]; +static struct brw_perf_query_info glk_tdl_2_query = { + .kind = OA_COUNTERS, + .name = "Metric set TDL_2", + .guid = "ffa3f263-0478-4724-8c9f-c911c5ec0f1d", + .counters = glk_tdl_2_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = glk_tdl_2_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = glk_tdl_2_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = glk_tdl_2_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +glk_register_tdl_2_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &glk_tdl_2_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141A026B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143A0173 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145A026B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2E5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E0069 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x180F6000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0F030A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2C03C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041A37E7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0414A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C150050 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08168000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A168000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003A3380 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x063A006F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x023A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00348000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06342000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A352000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C350100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02368000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C368000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025A37E7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0254A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C550005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04568000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06568000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45901080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_2__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__tdl_2__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__tdl_2__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__tdl_2__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__tdl_2__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_2__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_2__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__tdl_2__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_2__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_2__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_2__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_2__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_2__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__tdl_2__thread_header01_ready_port0__read; + counter->name = "Thread Header Ready on Slice0 Subslice1 Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 88; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__tdl_2__thread_header01_ready_port1__read; + counter->name = "Thread Header Ready on Slice0 Subslice1 Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 92; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_2__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_2__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = glk__tdl_2__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_2__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_2__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_2__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__tdl_2__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__tdl_2__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 140; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__tdl_2__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__tdl_2__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__tdl_2__thread_header02_ready_port1__read; + counter->name = "Thread Header Ready on Slice0 Subslice2 Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__tdl_2__thread_header02_ready_port0__read; + counter->name = "Thread Header Ready on Slice0 Subslice2 Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_2__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__tdl_2__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_2__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_2__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__tdl_2__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_2__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_2__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_2__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_2__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_2__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_2__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_2__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__tdl_2__thread_header00_ready_port0__read; + counter->name = "Thread Header Ready on Slice0 Subslice0 Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 256; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__tdl_2__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__tdl_2__thread_header00_ready_port1__read; + counter->name = "Thread Header Ready on Slice0 Subslice0 Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 272; + counter->size = sizeof(float); + } + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog glk_compute_extra_mux_regs[37]; +static struct brw_perf_query_register_prog glk_compute_extra_b_counter_regs[6]; +static struct brw_perf_query_register_prog glk_compute_extra_flex_regs[7]; + +static struct brw_perf_query_counter glk_compute_extra_query_counters[5]; +static struct brw_perf_query_info glk_compute_extra_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics Extra Gen9", + .guid = "15274c82-27d2-4819-876a-7cb1a2c59ba4", + .counters = glk_compute_extra_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = glk_compute_extra_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = glk_compute_extra_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = glk_compute_extra_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +glk_register_compute_extra_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &glk_compute_extra_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141A001F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143A001F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145A001F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2E0094 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044EA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A0F00E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A2C0C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061A0063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06142000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C150100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C168000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x043A3180 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x023A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04348000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C350040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A368000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045A0063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04542000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C550010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08568000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900004 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00001000 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00003002 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00011010 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00050012 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00052051 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00000008 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_extra__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_extra__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_extra__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__compute_extra__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = glk__compute_extra__avg_gpu_core_frequency__max(brw); + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = glk__compute_extra__fpu1_active_adjusted__read; + counter->name = "EU FPU1 Pipe Active including Ext Math"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing including Extended Math processing"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog glk_test_oa_mux_regs[12]; +static struct brw_perf_query_register_prog glk_test_oa_b_counter_regs[22]; + +static struct brw_perf_query_counter glk_test_oa_query_counters[12]; +static struct brw_perf_query_info glk_test_oa_query = { + .kind = OA_COUNTERS, + .name = "MDAPI testing set Gen9", + .guid = "dd3fd789-e783-4204-8cd0-b671bbccb0cf", + .counters = glk_test_oa_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = glk_test_oa_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = glk_test_oa_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ +}; + +static void +glk_register_test_oa_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &glk_test_oa_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07800063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23810008 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F922000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000004 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000003 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000007 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFF7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00100082 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFEF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x001000C2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FFE7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00100001 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FFE7 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__test_oa__counter7__read; + counter->name = "TestCounter7"; + counter->desc = "HW test counter 7. Factor: 0.666"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__test_oa__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 8; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__test_oa__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__test_oa__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = glk__test_oa__avg_gpu_core_frequency__max(brw); + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__test_oa__counter8__read; + counter->name = "TestCounter8"; + counter->desc = "HW test counter 8. Should be equal to 1."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__test_oa__counter4__read; + counter->name = "TestCounter4"; + counter->desc = "HW test counter 4. Factor: 0.333"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__test_oa__counter5__read; + counter->name = "TestCounter5"; + counter->desc = "HW test counter 5. Factor: 0.333"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__test_oa__counter6__read; + counter->name = "TestCounter6"; + counter->desc = "HW test counter 6. Factor: 0.166"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__test_oa__counter3__read; + counter->name = "TestCounter3"; + counter->desc = "HW test counter 3. Factor: 0.5"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__test_oa__counter0__read; + counter->name = "TestCounter0"; + counter->desc = "HW test counter 0. Factor: 0.0"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__test_oa__counter1__read; + counter->name = "TestCounter1"; + counter->desc = "HW test counter 1. Factor: 1.0"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = glk__test_oa__counter2__read; + counter->name = "TestCounter2"; + counter->desc = "HW test counter 2. Factor: 1.0"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +void +brw_oa_register_queries_glk(struct brw_context *brw) +{ + glk_register_render_basic_counter_query(brw); + glk_register_compute_basic_counter_query(brw); + glk_register_render_pipe_profile_counter_query(brw); + glk_register_memory_reads_counter_query(brw); + glk_register_memory_writes_counter_query(brw); + glk_register_compute_extended_counter_query(brw); + glk_register_compute_l3_cache_counter_query(brw); + glk_register_hdc_and_sf_counter_query(brw); + glk_register_l3_1_counter_query(brw); + glk_register_rasterizer_and_pixel_backend_counter_query(brw); + glk_register_sampler_counter_query(brw); + glk_register_tdl_1_counter_query(brw); + glk_register_tdl_2_counter_query(brw); + glk_register_compute_extra_counter_query(brw); + glk_register_test_oa_counter_query(brw); +} + +static struct brw_perf_query_register_prog cflgt2_render_basic_mux_regs[70]; +static struct brw_perf_query_register_prog cflgt2_render_basic_b_counter_regs[5]; +static struct brw_perf_query_register_prog cflgt2_render_basic_flex_regs[7]; + +static struct brw_perf_query_counter cflgt2_render_basic_query_counters[52]; +static struct brw_perf_query_info cflgt2_render_basic_query = { + .kind = OA_COUNTERS, + .name = "Render Metrics Basic Gen9", + .guid = "2bceea0d-babc-48ba-9289-0d6997c93083", + .counters = cflgt2_render_basic_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cflgt2_render_basic_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cflgt2_render_basic_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cflgt2_render_basic_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cflgt2_register_render_basic_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cflgt2_render_basic_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C01E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12170280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12370280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11930317 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x159303DF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E0080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A6C0053 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C8400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F6600 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162C2200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00133000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08133000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00170020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08170021 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10170000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0633C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0833C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06370800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08370840 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10370000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D933031 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F933E3F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01933D00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0393073C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0593000E }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900157 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900158 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190001F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51904400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C21 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900061 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57904440 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900004 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53904444 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_basic__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__render_basic__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_basic__l3_misses__read; + counter->name = "L3 Misses"; + counter->desc = "The total number of L3 misses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_basic__gti_l3_throughput__read; + counter->name = "GTI L3 Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__render_basic__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_basic__sampler_l1_misses__read; + counter->name = "Sampler Cache Misses"; + counter->desc = "The total number of sampler cache misses in all LODs in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__render_basic__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x12) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__render_basic__sampler1_bottleneck__read; + counter->name = "Sampler 1 Bottleneck"; + counter->desc = "The percentage of time in which Sampler 1 has been slowing down the pipe when processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 52; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__render_basic__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_basic__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_basic__l3_sampler_throughput__read; + counter->name = "L3 Sampler Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_basic__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__render_basic__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 88; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_basic__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_basic__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x09) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__render_basic__sampler0_busy__read; + counter->name = "Sampler 0 Busy"; + counter->desc = "The percentage of time in which Sampler 0 has been processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 112; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x12) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__render_basic__sampler1_busy__read; + counter->name = "Sampler 1 Busy"; + counter->desc = "The percentage of time in which Sampler 1 has been processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 116; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__render_basic__samplers_busy__read; + counter->name = "Samplers Busy"; + counter->desc = "The percentage of time in which samplers have been processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 120; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_basic__gti_vf_throughput__read; + counter->name = "GTI Fixed Pipe Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between 3D Pipeline (Command Dispatch, Input Assembly and Stream Output) and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_basic__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x09) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__render_basic__sampler0_bottleneck__read; + counter->name = "Sampler 0 Bottleneck"; + counter->desc = "The percentage of time in which Sampler 0 has been slowing down the pipe when processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_basic__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_basic__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_basic__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_basic__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cflgt2__render_basic__avg_gpu_core_frequency__max(brw); + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_basic__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_basic__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_basic__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_basic__l3_lookups__read; + counter->name = "L3 Lookup Accesses w/o IC"; + counter->desc = "The total number of L3 cache lookup accesses w/o IC."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_basic__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_basic__gti_read_throughput__read; + counter->name = "GTI Read Throughput"; + counter->desc = "The total number of GPU memory bytes read from GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__render_basic__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 232; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__render_basic__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 236; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_basic__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__render_basic__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 248; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_basic__gti_depth_throughput__read; + counter->name = "GTI Depth Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between depth caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__render_basic__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 264; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__render_basic__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 268; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_basic__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_basic__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__render_basic__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 288; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_basic__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_basic__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__render_basic__sampler_bottleneck__read; + counter->name = "Samplers Bottleneck"; + counter->desc = "The percentage of time in which samplers have been slowing down the pipe when processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 312; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_basic__gti_hdc_lookups_throughput__read; + counter->name = "GTI HDC TLB Lookup Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between GTI and HDC, when HDC is doing TLB lookups."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_basic__gti_rcc_throughput__read; + counter->name = "GTI RCC Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between render color caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 328; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_basic__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 336; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_basic__gti_write_throughput__read; + counter->name = "GTI Write Throughput"; + counter->desc = "The total number of GPU memory bytes written to GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 344; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_basic__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 352; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_basic__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 360; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_basic__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 368; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_basic__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 376; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cflgt2_compute_basic_mux_regs[78]; +static struct brw_perf_query_register_prog cflgt2_compute_basic_b_counter_regs[5]; +static struct brw_perf_query_register_prog cflgt2_compute_basic_flex_regs[7]; + +static struct brw_perf_query_counter cflgt2_compute_basic_query_counters[39]; +static struct brw_perf_query_info cflgt2_compute_basic_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics Basic Gen9", + .guid = "dc8cf7ea-26b4-4478-ac93-dab174f92ac0", + .counters = cflgt2_compute_basic_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cflgt2_compute_basic_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cflgt2_compute_basic_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cflgt2_compute_basic_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cflgt2_register_compute_basic_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cflgt2_compute_basic_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F00E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124F1C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C00E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E0820 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F0900 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084F0032 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4F1891 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4F0E00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4F003C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004F0D80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024F003B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C0100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C6C000C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C0B00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0024 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C6000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C5C001B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0208 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CFB00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00BE }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19900157 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B900158 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900105 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900103 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900FFF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900821 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900802 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900802 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900422 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53904444 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_basic__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_basic__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_basic__untyped_bytes_read__read; + counter->name = "Untyped Bytes Read"; + counter->desc = "The total number of typed memory bytes read via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_basic__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_basic__typed_bytes_written__read; + counter->name = "Typed Bytes Written"; + counter->desc = "The total number of untyped memory bytes written via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_basic__fpu0_active__read; + counter->name = "EU FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_basic__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 44; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_basic__eu_avg_ipc_rate__read; + counter->name = "EU AVG IPC Rate"; + counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 2.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_basic__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_basic__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_basic__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_basic__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_basic__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_basic__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_basic__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_basic__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_basic__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cflgt2__compute_basic__avg_gpu_core_frequency__max(brw); + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_basic__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_basic__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_basic__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_basic__gti_read_throughput__read; + counter->name = "GTI Read Throughput"; + counter->desc = "The total number of GPU memory bytes read from GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_basic__untyped_bytes_written__read; + counter->name = "Untyped Writes"; + counter->desc = "The total number of untyped memory bytes written via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_basic__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_basic__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_basic__typed_bytes_read__read; + counter->name = "Typed Bytes Read"; + counter->desc = "The total number of typed memory bytes read via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_basic__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_basic__eu_thread_occupancy__read; + counter->name = "EU Thread Occupancy"; + counter->desc = "The percentage of time in which hardware threads occupied EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_basic__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 204; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_basic__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_basic__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_basic__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_basic__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_basic__gti_write_throughput__read; + counter->name = "GTI Write Throughput"; + counter->desc = "The total number of GPU memory bytes written to GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_basic__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_basic__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_basic__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_basic__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_basic__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_basic__eu_send_active__read; + counter->name = "EU Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 288; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cflgt2_render_pipe_profile_mux_regs[114]; +static struct brw_perf_query_register_prog cflgt2_render_pipe_profile_b_counter_regs[21]; +static struct brw_perf_query_register_prog cflgt2_render_pipe_profile_flex_regs[7]; + +static struct brw_perf_query_counter cflgt2_render_pipe_profile_query_counters[43]; +static struct brw_perf_query_info cflgt2_render_pipe_profile_query = { + .kind = OA_COUNTERS, + .name = "Render Metrics for 3D Pipeline Profile Gen9", + .guid = "2221e4d5-ed7b-445e-b2cc-3de1b97f4d42", + .counters = cflgt2_render_pipe_profile_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cflgt2_render_pipe_profile_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cflgt2_render_pipe_profile_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cflgt2_render_pipe_profile_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cflgt2_register_render_pipe_profile_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cflgt2_render_pipe_profile_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0E001F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10116800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178A03E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11824C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11830020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13840020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11850019 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11860007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01870C40 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17880000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020E5400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000E0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080F0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06104000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06110012 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06131000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01898000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D890100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03898000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A0075 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8A4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x138A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D81A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15818000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17818000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B820030 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07828000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D824000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F828000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05824000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D830003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0583000C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09830000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03838000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07838000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B840980 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03844D80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11840000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09850080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03850003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01850000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07860000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F860400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09870032 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01888052 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11880000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09884000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B931001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D930001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19934000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B958000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950094 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19958000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09E58000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0BE58000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E5C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0592C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B928000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D924000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F924000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11928000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1392C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09924000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01985000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07988000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09981000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B982000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D982000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F989000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05982000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190C080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900440 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C21 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900042 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900024 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900841 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900400 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFEA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFC }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007AFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F5FD }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00079FFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000F3FB }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007BF7A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F7E7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FEFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000F7CF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00077FFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000EFDF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0006FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000CFBF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0003FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x00005F7F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__render_pipe_profile__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__render_pipe_profile__vs_bottleneck__read; + counter->name = "VS Bottleneck"; + counter->desc = "The percentage of time in which vertex shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__render_pipe_profile__hi_depth_bottleneck__read; + counter->name = "Hi-Depth Bottleneck"; + counter->desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__render_pipe_profile__gs_bottleneck__read; + counter->name = "GS Bottleneck"; + counter->desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__render_pipe_profile__bc_bottleneck__read; + counter->name = "BC Bottleneck"; + counter->desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__render_pipe_profile__hs_stall__read; + counter->name = "HS Stall"; + counter->desc = "The percentage of time in which hull stall pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 60; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cflgt2__render_pipe_profile__avg_gpu_core_frequency__max(brw); + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__render_pipe_profile__vf_bottleneck__read; + counter->name = "VF Bottleneck"; + counter->desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__render_pipe_profile__sf_bottleneck__read; + counter->name = "Strip-Fans Bottleneck"; + counter->desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__render_pipe_profile__sf_stall__read; + counter->name = "SF Stall"; + counter->desc = "The percentage of time in which strip-fans pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 140; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__render_pipe_profile__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__render_pipe_profile__hs_bottleneck__read; + counter->name = "HS Bottleneck"; + counter->desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__render_pipe_profile__cl_stall__read; + counter->name = "CL Stall"; + counter->desc = "The percentage of time in which clipper pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__render_pipe_profile__so_bottleneck__read; + counter->name = "SO Bottleneck"; + counter->desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__render_pipe_profile__ds_bottleneck__read; + counter->name = "DS Bottleneck"; + counter->desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__render_pipe_profile__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 188; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__render_pipe_profile__cl_bottleneck__read; + counter->name = "Clipper Bottleneck"; + counter->desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__render_pipe_profile__ds_stall__read; + counter->name = "DS Stall"; + counter->desc = "The percentage of time in which domain shader pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 196; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__render_pipe_profile__early_depth_bottleneck__read; + counter->name = "Early Depth Bottleneck"; + counter->desc = "The percentage of time in which early depth test pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__render_pipe_profile__so_stall__read; + counter->name = "SO Stall"; + counter->desc = "The percentage of time in which stream-output pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__render_pipe_profile__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cflgt2_memory_reads_mux_regs[47]; +static struct brw_perf_query_register_prog cflgt2_memory_reads_b_counter_regs[32]; +static struct brw_perf_query_register_prog cflgt2_memory_reads_flex_regs[7]; + +static struct brw_perf_query_counter cflgt2_memory_reads_query_counters[41]; +static struct brw_perf_query_info cflgt2_memory_reads_query = { + .kind = OA_COUNTERS, + .name = "Memory Reads Distribution Gen9", + .guid = "82096a90-e2fa-4f38-ac14-562b2496933a", + .counters = cflgt2_memory_reads_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cflgt2_memory_reads_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cflgt2_memory_reads_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cflgt2_memory_reads_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cflgt2_register_memory_reads_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cflgt2_memory_reads_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1381001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900064 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03811300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05811B12 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0781001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E58000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05E5C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900150 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21900151 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23900152 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25900153 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27900154 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B900156 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D900157 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F90015F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900105 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900103 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900101 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C63 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900C63 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000272C, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002728, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000271C, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002718, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F872 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_reads__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__memory_reads__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_reads__gti_l3_bank0_reads__read; + counter->name = "GtiL3Bank0Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 0 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_reads__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_reads__gti_ring_accesses__read; + counter->name = "GtiRingAccesses"; + counter->desc = "The total number of all accesses from GTI to the ring."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_reads__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_reads__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_reads__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_reads__gti_l3_bank3_reads__read; + counter->name = "GtiL3Bank3Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 3 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_reads__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_reads__gti_rs_memory_reads__read; + counter->name = "GtiRsMemoryReads"; + counter->desc = "The total number of GTI memory reads from Resource Streamer."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_reads__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_reads__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_reads__gti_hiz_memory_reads__read; + counter->name = "GtiHizMemoryReads"; + counter->desc = "The total number of GTI memory reads from Hierarchical Depth Cache (Hi-Depth Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_reads__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_reads__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cflgt2__memory_reads__avg_gpu_core_frequency__max(brw); + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_reads__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_reads__gti_rcc_memory_reads__read; + counter->name = "GtiRccMemoryReads"; + counter->desc = "The total number of GTI memory reads from Render Color Cache (Render Color Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_reads__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_reads__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_reads__gti_l3_bank1_reads__read; + counter->name = "GtiL3Bank1Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 1 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__memory_reads__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_reads__gti_cmd_streamer_memory_reads__read; + counter->name = "GtiCmdStreamerMemoryReads"; + counter->desc = "The total number of GTI memory reads from Command Streamer."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_reads__gti_l3_bank2_reads__read; + counter->name = "GtiL3Bank2Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 2 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_reads__gti_memory_reads__read; + counter->name = "GtiMemoryReads"; + counter->desc = "The total number of GTI memory reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_reads__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_reads__gti_rcz_memory_reads__read; + counter->name = "GtiRczMemoryReads"; + counter->desc = "The total number of GTI memory reads from Render Depth Cache (Render Depth Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_reads__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_reads__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__memory_reads__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 232; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_reads__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_reads__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_reads__gti_msc_memory_reads__read; + counter->name = "GtiMscMemoryReads"; + counter->desc = "The total number of GTI memory reads from Multisampling Color Cache (Multisampling Color Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_reads__gti_vf_memory_reads__read; + counter->name = "GtiVfMemoryReads"; + counter->desc = "The total number of GTI memory reads from Vertex Fetch."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_reads__gti_stc_memory_reads__read; + counter->name = "GtiStcMemoryReads"; + counter->desc = "The total number of GTI memory reads from Stencil Cache (Stencil Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_reads__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_reads__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_reads__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_reads__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_reads__gti_l3_reads__read; + counter->name = "GtiL3Reads"; + counter->desc = "The total number of GTI memory reads from L3 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_reads__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cflgt2_memory_writes_mux_regs[47]; +static struct brw_perf_query_register_prog cflgt2_memory_writes_b_counter_regs[32]; +static struct brw_perf_query_register_prog cflgt2_memory_writes_flex_regs[7]; + +static struct brw_perf_query_counter cflgt2_memory_writes_query_counters[41]; +static struct brw_perf_query_info cflgt2_memory_writes_query = { + .kind = OA_COUNTERS, + .name = "Memory Writes Distribution Gen9", + .guid = "9f638880-02e9-4a8d-896a-7670a3bf0d35", + .counters = cflgt2_memory_writes_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cflgt2_memory_writes_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cflgt2_memory_writes_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cflgt2_memory_writes_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cflgt2_register_memory_writes_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cflgt2_memory_writes_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1381001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F901000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03811300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05811B12 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0781001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E58000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05E5C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900160 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21900161 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23900162 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25900163 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27900164 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900165 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B900166 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D900167 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F900150 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900105 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900103 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900101 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C63 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900C63 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000272C, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002728, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000271C, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002718, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F822 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_writes__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__memory_writes__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_writes__gti_memory_writes__read; + counter->name = "GtiMemoryWrites"; + counter->desc = "The total number of GTI memory writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_writes__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_writes__gti_ring_accesses__read; + counter->name = "GtiRingAccesses"; + counter->desc = "The total number of all GTI accesses to the ring."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_writes__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_writes__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_writes__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_writes__gti_msc_memory_writes__read; + counter->name = "GtiMscMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Multisampling Color Cache (Multisampling Color Cache invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_writes__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_writes__gti_cmd_streamer_memory_writes__read; + counter->name = "GtiCmdStreamerMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Command Streamer."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_writes__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_writes__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_writes__gti_l3_bank0_writes__read; + counter->name = "GtiL3Bank0Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 0 (L3 Bank 0 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_writes__gti_l3_bank1_writes__read; + counter->name = "GtiL3Bank1Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 1 (L3 Bank 1 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_writes__gti_l3_bank2_writes__read; + counter->name = "GtiL3Bank2Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 2 (L3 Bank 2 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_writes__gti_l3_bank3_writes__read; + counter->name = "GtiL3Bank3Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 3 (L3 Bank 3 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_writes__gti_l3_writes__read; + counter->name = "GtiL3Writes"; + counter->desc = "The total number of GTI memory writes from L3 (L3 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_writes__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_writes__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cflgt2__memory_writes__avg_gpu_core_frequency__max(brw); + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_writes__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_writes__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_writes__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_writes__gti_rcc_memory_writes__read; + counter->name = "GtiRccMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Render Color Cache (Render Color Cache invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_writes__gti_so_memory_writes__read; + counter->name = "GtiSoMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Stream Output."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__memory_writes__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_writes__gti_stc_memory_writes__read; + counter->name = "GtiStcMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Stencil Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_writes__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_writes__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_writes__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__memory_writes__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 240; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_writes__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_writes__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_writes__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_writes__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_writes__gti_rcz_memory_writes__read; + counter->name = "GtiRczMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Render Depth Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_writes__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_writes__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_writes__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_writes__gti_hiz_memory_writes__read; + counter->name = "GtiHizMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Hierarchical Depth Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__memory_writes__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cflgt2_compute_extended_mux_regs[72]; +static struct brw_perf_query_register_prog cflgt2_compute_extended_b_counter_regs[21]; +static struct brw_perf_query_register_prog cflgt2_compute_extended_flex_regs[7]; + +static struct brw_perf_query_counter cflgt2_compute_extended_query_counters[38]; +static struct brw_perf_query_info cflgt2_compute_extended_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics Extended Gen9", + .guid = "8d4ad934-7c16-43d5-845a-51067a4c8e2f", + .counters = cflgt2_compute_extended_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cflgt2_compute_extended_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cflgt2_compute_extended_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cflgt2_compute_extended_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cflgt2_register_compute_extended_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cflgt2_compute_extended_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C00E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8160 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C0120 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x184E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4EAAA0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C0B01 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C000C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001C0041 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061C4200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081C4443 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1C4645 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1C7647 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041C7357 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0030 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4CAA2A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C02AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5515 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CAA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11907FFF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900802 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FC2A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FC6A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007FC92 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007FCA2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FC32 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FC9A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007FE6A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007FE7A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000BF00 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_extended__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_extended__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_extended__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_extended__fpu0_active__read; + counter->name = "EU FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_extended__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_extended__eu_avg_ipc_rate__read; + counter->name = "EU AVG IPC Rate"; + counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 2.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_extended__typed_writes0__read; + counter->name = "Typed Writes 0"; + counter->desc = "The subslice 0 typed writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_extended__eu_typed_atomics0__read; + counter->name = "EuTypedAtomics0"; + counter->desc = "The subslice 0 EU Typed Atomics subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_extended__typed_atomics0__read; + counter->name = "Typed Atomics 0"; + counter->desc = "The subslice 0 typed atomics."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_extended__typed_atomics_per_cache_line__read; + counter->name = "TypedAtomicsPerCacheLine"; + counter->desc = "The ratio of EU typed atomics requests to L3 cache line writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_extended__eu_untyped_reads0__read; + counter->name = "EuUntypedReads0"; + counter->desc = "The subslice 0 EU Untyped Reads subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_extended__untyped_writes0__read; + counter->name = "Untyped Writes 0"; + counter->desc = "The subslice 0 untyped writes (including SLM writes)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_extended__eu_untyped_atomics0__read; + counter->name = "EuUntypedAtomics0"; + counter->desc = "The subslice 0 EU Untyped Atomics subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_extended__eu_untyped_writes0__read; + counter->name = "EuUntypedWrites0"; + counter->desc = "The subslice 0 EU Untyped Writes subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_extended__eu_a64_untyped_writes0__read; + counter->name = "EuA64UntypedWrites0"; + counter->desc = "The subslice 0 EU A64 Untyped Writes subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_extended__untyped_writes_per_cache_line__read; + counter->name = "UntypedWritesPerCacheLine"; + counter->desc = "The ratio of EU untyped write requests to L3 cache line writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_extended__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_extended__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_extended__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_extended__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cflgt2__compute_extended__avg_gpu_core_frequency__max(brw); + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_extended__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_extended__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_extended__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_extended__eu_typed_writes0__read; + counter->name = "EuTypedWrites0"; + counter->desc = "The subslice 0 EU Typed Writes subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_extended__typed_writes_per_cache_line__read; + counter->name = "TypedWritesPerCacheLine"; + counter->desc = "The ratio of EU typed write requests to L3 cache line writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_extended__typed_reads0__read; + counter->name = "Typed Reads 0"; + counter->desc = "The subslice 0 typed reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_extended__untyped_reads0__read; + counter->name = "Untyped Reads 0"; + counter->desc = "The subslice 0 untyped reads (including SLM reads)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_extended__eu_a64_untyped_reads0__read; + counter->name = "EuA64UntypedReads0"; + counter->desc = "The subslice 0 EU A64 Untyped Reads subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_extended__eu_thread_occupancy__read; + counter->name = "EU Thread Occupancy"; + counter->desc = "The percentage of time in which hardware threads occupied EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 208; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_extended__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 212; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_extended__eu_typed_reads0__read; + counter->name = "EuTypedReads0"; + counter->desc = "The subslice 0 EU Typed Reads subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_extended__untyped_reads_per_cache_line__read; + counter->name = "UntypedReadsPerCacheLine"; + counter->desc = "The ratio of EU untyped read requests to L3 cache line reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_extended__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_extended__typed_reads_per_cache_line__read; + counter->name = "TypedReadsPerCacheLine"; + counter->desc = "The ratio of EU typed read requests to L3 cache line reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_extended__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_extended__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_extended__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_extended__eu_send_active__read; + counter->name = "EU Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 272; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cflgt2_compute_l3_cache_mux_regs[60]; +static struct brw_perf_query_register_prog cflgt2_compute_l3_cache_b_counter_regs[13]; +static struct brw_perf_query_register_prog cflgt2_compute_l3_cache_flex_regs[7]; + +static struct brw_perf_query_counter cflgt2_compute_l3_cache_query_counters[54]; +static struct brw_perf_query_info cflgt2_compute_l3_cache_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics L3 Cache Gen9", + .guid = "4389cf07-1424-4963-b2d2-64fcec75406d", + .counters = cflgt2_compute_l3_cache_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cflgt2_compute_l3_cache_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cflgt2_compute_l3_cache_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cflgt2_compute_l3_cache_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cflgt2_register_compute_l3_cache_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cflgt2_compute_l3_cache_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C0760 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1593001E }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x184E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E8020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0051 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C5C5D }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C5E5F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1CE000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0030 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C2A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F1500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0140 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162C0A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03933300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05930032 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900157 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900158 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190030F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900021 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53904444 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FEFE }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FEFD }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FBEF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FBDF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00101100 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00201200 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00301300 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00401400 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_l3_cache__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__l3_bank03_accesses__read; + counter->name = "L3 Bank 03 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 03."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__l3_accesses__read; + counter->name = "L3 Accesses"; + counter->desc = "The total number of L3 accesses from all entities."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_l3_cache__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__l3_sampler_throughput__read; + counter->name = "L3 Sampler Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_l3_cache__fpu0_active__read; + counter->name = "EU FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_l3_cache__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 52; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_l3_cache__eu_avg_ipc_rate__read; + counter->name = "EU AVG IPC Rate"; + counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 2.0; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_l3_cache__eu_binary_fpu0_instruction__read; + counter->name = "EU FPU0 Binary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 60; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_l3_cache__eu_hybrid_fpu0_instruction__read; + counter->name = "EU FPU0 Hybrid Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 104; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__l3_misses__read; + counter->name = "L3 Misses"; + counter->desc = "The total number of L3 misses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__l3_bank00_accesses__read; + counter->name = "L3 Bank 00 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 00."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_l3_cache__eu_move_fpu0_instruction__read; + counter->name = "EU FPU0 Move Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_l3_cache__eu_hybrid_fpu1_instruction__read; + counter->name = "EU FPU1 Hybrid Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cflgt2__compute_l3_cache__avg_gpu_core_frequency__max(brw); + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__gti_read_throughput__read; + counter->name = "GTI Read Throughput"; + counter->desc = "The total number of GPU memory bytes read from GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__gti_l3_throughput__read; + counter->name = "GTI L3 Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__l3_bank00_ic_accesses__read; + counter->name = "L3 Bank 00 IC Accesses"; + counter->desc = "The total number of accesses to L3 Bank 00 from IC cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + } + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__l3_bank00_ic_hits__read; + counter->name = "L3 Bank 00 IC Hits"; + counter->desc = "The total number of hits in L3 Bank 00 from IC cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__sampler_accesses__read; + counter->name = "Sampler Accesses"; + counter->desc = "The total number of messages send to samplers."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__l3_bank01_accesses__read; + counter->name = "L3 Bank 01 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 01."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_l3_cache__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 256; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_l3_cache__eu_ternary_fpu0_instruction__read; + counter->name = "EU FPU0 Ternary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 260; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_l3_cache__eu_move_fpu1_instruction__read; + counter->name = "EU FPU1 Move Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 296; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_l3_cache__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 300; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__l3_bank02_accesses__read; + counter->name = "L3 Bank 02 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 02."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 328; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__l3_total_throughput__read; + counter->name = "L3 Total Throughput"; + counter->desc = "The total number of GPU memory bytes transferred via L3."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 336; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__gti_write_throughput__read; + counter->name = "GTI Write Throughput"; + counter->desc = "The total number of GPU memory bytes written to GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 344; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 352; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 360; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_l3_cache__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 368; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_l3_cache__eu_binary_fpu1_instruction__read; + counter->name = "EU FPU1 Binary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 376; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_l3_cache__eu_ternary_fpu1_instruction__read; + counter->name = "EU FPU1 Ternary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 380; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_l3_cache__eu_send_active__read; + counter->name = "EU Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 384; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cflgt2_hdc_and_sf_mux_regs[54]; +static struct brw_perf_query_register_prog cflgt2_hdc_and_sf_b_counter_regs[8]; +static struct brw_perf_query_register_prog cflgt2_hdc_and_sf_flex_regs[7]; + +static struct brw_perf_query_counter cflgt2_hdc_and_sf_query_counters[39]; +static struct brw_perf_query_info cflgt2_hdc_and_sf_query = { + .kind = OA_COUNTERS, + .name = "Metric set HDCAndSF", + .guid = "1c003bbe-ca7f-49d0-bb0f-2f0096147a00", + .counters = cflgt2_hdc_and_sf_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cflgt2_hdc_and_sf_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cflgt2_hdc_and_sf_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cflgt2_hdc_and_sf_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cflgt2_register_hdc_and_sf_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cflgt2_hdc_and_sf_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F0232 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124F4640 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0232 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11834400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004F1880 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024F08BB }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044F001B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C0100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C000B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C1800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x165C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x185C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C00A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F828000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8305C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09830000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07830000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13928000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F988000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FDFF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__hdc_and_sf__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__hdc_and_sf__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__hdc_and_sf__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__hdc_and_sf__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__hdc_and_sf__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__hdc_and_sf__poly_data_ready__read; + counter->name = "Polygon Data Ready"; + counter->desc = "The percentage of time in which geometry pipeline output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cflgt2__hdc_and_sf__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read; + counter->name = "HDC stalled by L3 (s0.ss1)"; + counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss1)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 120; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read; + counter->name = "HDC stalled by L3 (s0.ss2)"; + counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss2)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__hdc_and_sf__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__hdc_and_sf__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__hdc_and_sf__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__hdc_and_sf__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 164; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__hdc_and_sf__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__hdc_and_sf__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read; + counter->name = "HDC stalled by L3 (s0.ss0)"; + counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss0)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 264; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__hdc_and_sf__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cflgt2_l3_1_mux_regs[71]; +static struct brw_perf_query_register_prog cflgt2_l3_1_b_counter_regs[22]; +static struct brw_perf_query_register_prog cflgt2_l3_1_flex_regs[7]; + +static struct brw_perf_query_counter cflgt2_l3_1_query_counters[39]; +static struct brw_perf_query_info cflgt2_l3_1_query = { + .kind = OA_COUNTERS, + .name = "Metric set L3_1", + .guid = "2a208cb2-0f82-4518-844d-c4c4699659a1", + .counters = cflgt2_l3_1_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cflgt2_l3_1_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cflgt2_l3_1_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cflgt2_l3_1_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cflgt2_register_l3_1_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cflgt2_l3_1_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C7B40 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C0020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A603444 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A613400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4EA800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C6C5327 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C5425 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C2A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C285B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C005C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C003C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10600000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04600000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C610044 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10610000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06610000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C02A8 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0154 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FFC0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900420 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900021 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900421 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00014002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000C3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00010002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000C7FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00004002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000D3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100700 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FF1F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00001402 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FC3F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00001002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FC7F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00000402 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FD3F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_1__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_1__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_1__l30_bank1_active__read; + counter->name = "Slice0 L3 Bank1 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank1 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_1__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_1__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_1__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_1__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_1__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_1__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_1__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_1__l30_bank1_stalled__read; + counter->name = "Slice0 L3 Bank1 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank1 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_1__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_1__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_1__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_1__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_1__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_1__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cflgt2__l3_1__avg_gpu_core_frequency__max(brw); + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_1__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_1__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_1__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_1__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_1__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_1__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_1__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_1__l30_bank0_active__read; + counter->name = "Slice0 L3 Bank0 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank0 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_1__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_1__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_1__l30_bank0_stalled__read; + counter->name = "Slice0 L3 Bank0 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank0 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 180; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_1__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_1__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_1__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_1__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_1__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_1__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_1__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_1__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_1__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_1__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_1__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cflgt2_l3_2_mux_regs[44]; +static struct brw_perf_query_register_prog cflgt2_l3_2_b_counter_regs[14]; +static struct brw_perf_query_register_prog cflgt2_l3_2_flex_regs[7]; + +static struct brw_perf_query_counter cflgt2_l3_2_query_counters[37]; +static struct brw_perf_query_info cflgt2_l3_2_query = { + .kind = OA_COUNTERS, + .name = "Metric set L3_2", + .guid = "bf38efc7-7a5c-4cc9-87ff-cbb4b954b4ec", + .counters = cflgt2_l3_2_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cflgt2_l3_2_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cflgt2_l3_2_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cflgt2_l3_2_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cflgt2_register_l3_2_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cflgt2_l3_2_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C02E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146C0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A623400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C3324 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C3422 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06614000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C620044 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10620000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06620000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190F800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00028002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x000087FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00020002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00008FFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00008002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000A7FF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_2__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_2__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_2__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_2__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_2__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_2__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_2__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_2__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_2__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_2__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_2__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_2__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_2__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_2__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_2__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cflgt2__l3_2__avg_gpu_core_frequency__max(brw); + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_2__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_2__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_2__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_2__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 128; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_2__l30_bank2_stalled__read; + counter->name = "Slice0 L3 Bank2 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank2 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 132; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_2__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_2__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 140; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_2__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_2__l30_bank2_active__read; + counter->name = "Slice0 L3 Bank2 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank2 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_2__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_2__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_2__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_2__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_2__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 184; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_2__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_2__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_2__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_2__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_2__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_2__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_2__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_2__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cflgt2_l3_3_mux_regs[43]; +static struct brw_perf_query_register_prog cflgt2_l3_3_b_counter_regs[14]; +static struct brw_perf_query_register_prog cflgt2_l3_3_flex_regs[7]; + +static struct brw_perf_query_counter cflgt2_l3_3_query_counters[37]; +static struct brw_perf_query_info cflgt2_l3_3_query = { + .kind = OA_COUNTERS, + .name = "Metric set L3_3", + .guid = "a9cf8100-606e-4cb1-a509-e69f8588c050", + .counters = cflgt2_l3_3_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cflgt2_l3_3_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cflgt2_l3_3_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cflgt2_l3_3_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cflgt2_register_l3_3_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cflgt2_l3_3_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C4E80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A633400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C3321 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C342F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C1800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06604000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C630044 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10630000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06630000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C00AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190F800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00028002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x000087FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00020002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00008FFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00008002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000A7FF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_3__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_3__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_3__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_3__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_3__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_3__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_3__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_3__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_3__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_3__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_3__l30_bank3_stalled__read; + counter->name = "Slice0 L3 Bank3 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank3 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_3__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_3__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_3__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_3__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_3__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cflgt2__l3_3__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_3__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_3__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_3__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_3__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_3__l30_bank3_active__read; + counter->name = "Slice0 L3 Bank3 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank3 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 140; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_3__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_3__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_3__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_3__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_3__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_3__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_3__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__l3_3__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_3__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_3__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_3__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_3__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_3__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_3__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_3__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__l3_3__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cflgt2_rasterizer_and_pixel_backend_mux_regs[31]; +static struct brw_perf_query_register_prog cflgt2_rasterizer_and_pixel_backend_b_counter_regs[10]; +static struct brw_perf_query_register_prog cflgt2_rasterizer_and_pixel_backend_flex_regs[7]; + +static struct brw_perf_query_counter cflgt2_rasterizer_and_pixel_backend_query_counters[40]; +static struct brw_perf_query_info cflgt2_rasterizer_and_pixel_backend_query = { + .kind = OA_COUNTERS, + .name = "Metric set RasterizerAndPixelBackend", + .guid = "4905b811-fbb0-4f51-aacd-3d46555aad3d", + .counters = cflgt2_rasterizer_and_pixel_backend_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cflgt2_rasterizer_and_pixel_backend_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cflgt2_rasterizer_and_pixel_backend_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cflgt2_rasterizer_and_pixel_backend_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cflgt2_register_rasterizer_and_pixel_backend_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cflgt2_rasterizer_and_pixel_backend_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102F3800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x144D0500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x120D03C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x140D03CF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0004 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F0480 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0090 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064D0027 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004D0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D0D40 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020D803F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040D8023 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100D0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020F0010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0050 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41901400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43901485 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000EFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00006000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F3FF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__rasterizer_and_pixel_backend__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__rasterizer_and_pixel_backend__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__rasterizer_and_pixel_backend__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__rasterizer_and_pixel_backend__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__rasterizer_and_pixel_backend__pixel_values0_ready__read; + counter->name = "Slice0 Pixel Values Ready"; + counter->desc = "The percentage of time in which slice0 pixel values are ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cflgt2__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__rasterizer_and_pixel_backend__rasterizer0_input_available__read; + counter->name = "Slice0 Rasterizer Input Available"; + counter->desc = "The percentage of time in which slice0 rasterizer input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 128; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__rasterizer_and_pixel_backend__pixel_data0_ready__read; + counter->name = "Slice0 Post-EarlyZ Pixel Data Ready"; + counter->desc = "The percentage of time in which slice0 post-EarlyZ pixel data is ready (after early Z tests have been applied)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 132; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__rasterizer_and_pixel_backend__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__rasterizer_and_pixel_backend__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__rasterizer_and_pixel_backend__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__rasterizer_and_pixel_backend__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__rasterizer_and_pixel_backend__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__rasterizer_and_pixel_backend__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__rasterizer_and_pixel_backend__rasterizer0_output_ready__read; + counter->name = "Slice0 Rasterizer Output Ready"; + counter->desc = "The percentage of time in which slice0 rasterizer output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 196; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__rasterizer_and_pixel_backend__ps_output0_available__read; + counter->name = "Slice0 PS Output Available"; + counter->desc = "The percentage of time in which slice0 PS output is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 256; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__rasterizer_and_pixel_backend__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cflgt2_sampler_mux_regs[69]; +static struct brw_perf_query_register_prog cflgt2_sampler_b_counter_regs[12]; +static struct brw_perf_query_register_prog cflgt2_sampler_flex_regs[7]; + +static struct brw_perf_query_counter cflgt2_sampler_query_counters[41]; +static struct brw_perf_query_info cflgt2_sampler_query = { + .kind = OA_COUNTERS, + .name = "Metric set Sampler", + .guid = "00defd09-c283-4d34-a3c5-e2c4f9120adf", + .counters = cflgt2_sampler_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cflgt2_sampler_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cflgt2_sampler_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cflgt2_sampler_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cflgt2_register_sampler_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cflgt2_sampler_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14152C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16150005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121600A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14352C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16350005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123600A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14552C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16550005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125600A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062F6000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0050 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0350 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FB000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F00DA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C0028 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C138000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E132000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0413C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C140018 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C157000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E150078 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10150000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04162180 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02160000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04174000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0233A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04333000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14348000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16348000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02357870 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10350000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04360043 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02360000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04371000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E538000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00538000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06533000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C540020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12548000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E557000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00557800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10550000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06560043 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02560000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06571000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FF80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900060 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900060 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x70800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0000C000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000E7FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00003000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F9FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000C00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE7F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__sampler__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__sampler__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__sampler__sampler02_input_available__read; + counter->name = "Slice0 Subslice2 Input Available"; + counter->desc = "The percentage of time in which slice0 subslice2 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__sampler__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__sampler__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__sampler__sampler00_input_available__read; + counter->name = "Slice0 Subslice0 Input Available"; + counter->desc = "The percentage of time in which slice0 subslice0 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__sampler__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 28; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__sampler__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__sampler__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__sampler__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__sampler__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__sampler__sampler02_output_ready__read; + counter->name = "Slice0 Subslice2 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice0 subslice2 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__sampler__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__sampler__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__sampler__sampler01_input_available__read; + counter->name = "Slice0 Subslice1 Input Available"; + counter->desc = "The percentage of time in which slice0 subslice1 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 88; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__sampler__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__sampler__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__sampler__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__sampler__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cflgt2__sampler__avg_gpu_core_frequency__max(brw); + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__sampler__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__sampler__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__sampler__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__sampler__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__sampler__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__sampler__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__sampler__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 164; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__sampler__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__sampler__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__sampler__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__sampler__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__sampler__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__sampler__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__sampler__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__sampler__sampler00_output_ready__read; + counter->name = "Slice0 Subslice0 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice0 subslice0 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 224; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__sampler__sampler01_output_ready__read; + counter->name = "Slice0 Subslice1 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice0 subslice1 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 228; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__sampler__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__sampler__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__sampler__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__sampler__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__sampler__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__sampler__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cflgt2_tdl_1_mux_regs[68]; +static struct brw_perf_query_register_prog cflgt2_tdl_1_b_counter_regs[18]; +static struct brw_perf_query_register_prog cflgt2_tdl_1_flex_regs[7]; + +static struct brw_perf_query_counter cflgt2_tdl_1_query_counters[41]; +static struct brw_perf_query_info cflgt2_tdl_1_query = { + .kind = OA_COUNTERS, + .name = "Metric set TDL_1", + .guid = "87b33db5-ad38-4a08-a9e7-5f807dee1a45", + .counters = cflgt2_tdl_1_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cflgt2_tdl_1_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cflgt2_tdl_1_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cflgt2_tdl_1_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cflgt2_register_tdl_1_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cflgt2_tdl_1_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12120000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12320000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12520000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F3000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F03A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FF000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0095 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02108000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0410C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02118000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0411C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02121880 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041219B5 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02134000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04135000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C308000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E304000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06304000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C318000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E314000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06314000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C321A80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E320033 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06320031 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00320000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C334000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E331000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06331000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E508000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00508000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02504000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E518000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00518000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02514000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E521880 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00521A80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02520033 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E534000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00534000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02531000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FF80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900062 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00009FFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000EFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FDFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE7F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_1__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__tdl_1__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__tdl_1__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__tdl_1__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__tdl_1__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_1__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_1__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__tdl_1__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_1__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_1__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__tdl_1__non_ps_thread02_ready_for_dispatch__read; + counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice2"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_1__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_1__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_1__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_1__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_1__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cflgt2__tdl_1__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_1__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__tdl_1__non_ps_thread00_ready_for_dispatch__read; + counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice0"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 120; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_1__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_1__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__tdl_1__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__tdl_1__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__tdl_1__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__tdl_1__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__tdl_1__ps_thread00_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice0"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_1__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__tdl_1__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_1__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_1__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__tdl_1__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_1__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_1__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__tdl_1__ps_thread01_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice1"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 224; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_1__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_1__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__tdl_1__ps_thread02_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice2"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 248; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_1__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_1__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_1__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_1__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__tdl_1__non_ps_thread01_ready_for_dispatch__read; + counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice1"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 288; + counter->size = sizeof(float); + } + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cflgt2_tdl_2_mux_regs[42]; +static struct brw_perf_query_register_prog cflgt2_tdl_2_b_counter_regs[6]; +static struct brw_perf_query_register_prog cflgt2_tdl_2_flex_regs[7]; + +static struct brw_perf_query_counter cflgt2_tdl_2_query_counters[41]; +static struct brw_perf_query_info cflgt2_tdl_2_query = { + .kind = OA_COUNTERS, + .name = "Metric set TDL_2", + .guid = "fbf2fbc7-c1ce-4b7a-8f32-cf60eb947fa5", + .counters = cflgt2_tdl_2_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cflgt2_tdl_2_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cflgt2_tdl_2_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cflgt2_tdl_2_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cflgt2_register_tdl_2_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cflgt2_tdl_2_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12124D60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12322E60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12524D60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F3000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0014 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FE000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0097 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0410C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0411C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04121FB7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04135000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00308000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06304000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00318000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06314000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00321B80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0632003F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00334000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06331000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0250C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0251C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02521FB7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00520000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02535000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_2__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__tdl_2__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__tdl_2__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__tdl_2__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__tdl_2__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_2__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_2__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__tdl_2__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_2__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_2__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_2__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_2__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_2__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__tdl_2__thread_header01_ready_port0__read; + counter->name = "Thread Header Ready on Slice0 Subslice1 Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 88; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__tdl_2__thread_header01_ready_port1__read; + counter->name = "Thread Header Ready on Slice0 Subslice1 Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 92; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_2__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_2__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cflgt2__tdl_2__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_2__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_2__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_2__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__tdl_2__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__tdl_2__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 140; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__tdl_2__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__tdl_2__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__tdl_2__thread_header02_ready_port1__read; + counter->name = "Thread Header Ready on Slice0 Subslice2 Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__tdl_2__thread_header02_ready_port0__read; + counter->name = "Thread Header Ready on Slice0 Subslice2 Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_2__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__tdl_2__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_2__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_2__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__tdl_2__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_2__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_2__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_2__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_2__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_2__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_2__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_2__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__tdl_2__thread_header00_ready_port0__read; + counter->name = "Thread Header Ready on Slice0 Subslice0 Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 256; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__tdl_2__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__tdl_2__thread_header00_ready_port1__read; + counter->name = "Thread Header Ready on Slice0 Subslice0 Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 272; + counter->size = sizeof(float); + } + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cflgt2_compute_extra_mux_regs[32]; +static struct brw_perf_query_register_prog cflgt2_compute_extra_b_counter_regs[6]; +static struct brw_perf_query_register_prog cflgt2_compute_extra_flex_regs[7]; + +static struct brw_perf_query_counter cflgt2_compute_extra_query_counters[5]; +static struct brw_perf_query_info cflgt2_compute_extra_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics Extra Gen9", + .guid = "5f679fb0-909e-4c0e-b4b2-8e801f83e71b", + .counters = cflgt2_compute_extra_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cflgt2_compute_extra_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cflgt2_compute_extra_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cflgt2_compute_extra_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cflgt2_register_compute_extra_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cflgt2_compute_extra_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121203E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123203E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125203E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F006C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06104000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06114000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06120033 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06131000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04308000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04318000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04321980 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00320000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04334000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04504000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04514000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04520033 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00520000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04531000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190E000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00001000 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00003002 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00011010 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00050012 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00052051 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00000008 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_extra__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_extra__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_extra__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__compute_extra__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cflgt2__compute_extra__avg_gpu_core_frequency__max(brw); + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__compute_extra__fpu1_active_adjusted__read; + counter->name = "EU FPU1 Pipe Active including Ext Math"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing including Extended Math processing"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cflgt2_vme_pipe_mux_regs[62]; +static struct brw_perf_query_register_prog cflgt2_vme_pipe_b_counter_regs[17]; +static struct brw_perf_query_register_prog cflgt2_vme_pipe_flex_regs[2]; + +static struct brw_perf_query_counter cflgt2_vme_pipe_query_counters[10]; +static struct brw_perf_query_info cflgt2_vme_pipe_query = { + .kind = OA_COUNTERS, + .name = "Media Vme Pipe Gen9", + .guid = "0d09ba9a-1d1c-457d-83e2-74ac448014d6", + .counters = cflgt2_vme_pipe_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cflgt2_vme_pipe_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cflgt2_vme_pipe_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cflgt2_vme_pipe_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cflgt2_register_vme_pipe_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cflgt2_vme_pipe_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141A5800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161A00C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12180240 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14180002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x143A5800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x163A00C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12380240 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14380002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F3000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C1500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F9500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162C0A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04193000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081A28C1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00133000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0613C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0813F000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00172000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06178000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0817A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00180037 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06180940 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08180000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02180000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04183000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06393000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3A28C1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A33F000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C33F000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A37A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C37A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A380977 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08380000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04380000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06383000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x119000FF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47901000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900844 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100030 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF9 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FFFC }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FFF3 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100180 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFCF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FF3F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00008003 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__vme_pipe__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__vme_pipe__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__vme_pipe__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__vme_pipe__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__vme_pipe__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cflgt2__vme_pipe__avg_gpu_core_frequency__max(brw); + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__vme_pipe__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__vme_pipe__eu_thread_occupancy__read; + counter->name = "EU Thread Occupancy"; + counter->desc = "The percentage of time in which hardware threads occupied EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__vme_pipe__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 44; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__vme_pipe__vme_busy__read; + counter->name = "VME Busy"; + counter->desc = "The percentage of time in which VME (IME or CRE) was actively processing data."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt2__vme_pipe__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 52; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cflgt2_test_oa_mux_regs[13]; +static struct brw_perf_query_register_prog cflgt2_test_oa_b_counter_regs[22]; + +static struct brw_perf_query_counter cflgt2_test_oa_query_counters[12]; +static struct brw_perf_query_info cflgt2_test_oa_query = { + .kind = OA_COUNTERS, + .name = "MDAPI testing set Gen9.5", + .guid = "74fb4902-d3d3-4237-9e90-cbdc68d0a446", + .counters = cflgt2_test_oa_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cflgt2_test_oa_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cflgt2_test_oa_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ +}; + +static void +cflgt2_register_test_oa_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cflgt2_test_oa_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07810013 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000004 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000003 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000007 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFF7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00100082 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFEF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x001000C2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FFE7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00100001 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FFE7 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__test_oa__counter7__read; + counter->name = "TestCounter7"; + counter->desc = "HW test counter 7. Factor: 0.666"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__test_oa__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 8; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__test_oa__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__test_oa__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cflgt2__test_oa__avg_gpu_core_frequency__max(brw); + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__test_oa__counter8__read; + counter->name = "TestCounter8"; + counter->desc = "HW test counter 8. Should be equal to 1."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__test_oa__counter4__read; + counter->name = "TestCounter4"; + counter->desc = "HW test counter 4. Factor: 0.333"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__test_oa__counter5__read; + counter->name = "TestCounter5"; + counter->desc = "HW test counter 5. Factor: 0.333"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__test_oa__counter6__read; + counter->name = "TestCounter6"; + counter->desc = "HW test counter 6. Factor: 0.166"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__test_oa__counter3__read; + counter->name = "TestCounter3"; + counter->desc = "HW test counter 3. Factor: 0.5"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__test_oa__counter0__read; + counter->name = "TestCounter0"; + counter->desc = "HW test counter 0. Factor: 0.0"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__test_oa__counter1__read; + counter->name = "TestCounter1"; + counter->desc = "HW test counter 1. Factor: 1.0"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt2__test_oa__counter2__read; + counter->name = "TestCounter2"; + counter->desc = "HW test counter 2. Factor: 1.0"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +void +brw_oa_register_queries_cflgt2(struct brw_context *brw) +{ + cflgt2_register_render_basic_counter_query(brw); + cflgt2_register_compute_basic_counter_query(brw); + cflgt2_register_render_pipe_profile_counter_query(brw); + cflgt2_register_memory_reads_counter_query(brw); + cflgt2_register_memory_writes_counter_query(brw); + cflgt2_register_compute_extended_counter_query(brw); + cflgt2_register_compute_l3_cache_counter_query(brw); + cflgt2_register_hdc_and_sf_counter_query(brw); + cflgt2_register_l3_1_counter_query(brw); + cflgt2_register_l3_2_counter_query(brw); + cflgt2_register_l3_3_counter_query(brw); + cflgt2_register_rasterizer_and_pixel_backend_counter_query(brw); + cflgt2_register_sampler_counter_query(brw); + cflgt2_register_tdl_1_counter_query(brw); + cflgt2_register_tdl_2_counter_query(brw); + cflgt2_register_compute_extra_counter_query(brw); + cflgt2_register_vme_pipe_counter_query(brw); + cflgt2_register_test_oa_counter_query(brw); +} + +static struct brw_perf_query_register_prog cflgt3_render_basic_mux_regs[83]; +static struct brw_perf_query_register_prog cflgt3_render_basic_b_counter_regs[5]; +static struct brw_perf_query_register_prog cflgt3_render_basic_flex_regs[7]; + +static struct brw_perf_query_counter cflgt3_render_basic_query_counters[52]; +static struct brw_perf_query_info cflgt3_render_basic_query = { + .kind = OA_COUNTERS, + .name = "Render Metrics Basic Gen9", + .guid = "80b55814-32e9-4988-95fd-77aded3ac0fe", + .counters = cflgt3_render_basic_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cflgt3_render_basic_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cflgt3_render_basic_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cflgt3_render_basic_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cflgt3_register_render_basic_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cflgt3_render_basic_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C01E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12170280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12370280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16EC01E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11930317 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x159303DF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E0380 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A6C0053 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C8400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F6600 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CA200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00133000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08133000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00170020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08170021 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10170000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0633C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0833C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06370800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08370840 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10370000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1ACE0200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AEC5300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10EC0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CEC0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A9B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C9C0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CCC0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A8D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x108F0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16AC8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D933031 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F933E3F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01933D00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0393073C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0593000E }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900157 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900158 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190003F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51902240 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900242 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900084 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47901400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57902220 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900C60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900C63 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53902222 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_basic__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__render_basic__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_basic__l3_misses__read; + counter->name = "L3 Misses"; + counter->desc = "The total number of L3 misses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_basic__gti_l3_throughput__read; + counter->name = "GTI L3 Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__render_basic__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_basic__sampler_l1_misses__read; + counter->name = "Sampler Cache Misses"; + counter->desc = "The total number of sampler cache misses in all LODs in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__render_basic__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x12) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__render_basic__sampler1_bottleneck__read; + counter->name = "Sampler 1 Bottleneck"; + counter->desc = "The percentage of time in which Sampler 1 has been slowing down the pipe when processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 52; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__render_basic__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_basic__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_basic__l3_sampler_throughput__read; + counter->name = "L3 Sampler Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_basic__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__render_basic__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 88; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_basic__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_basic__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x09) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__render_basic__sampler0_busy__read; + counter->name = "Sampler 0 Busy"; + counter->desc = "The percentage of time in which Sampler 0 has been processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 112; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x12) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__render_basic__sampler1_busy__read; + counter->name = "Sampler 1 Busy"; + counter->desc = "The percentage of time in which Sampler 1 has been processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 116; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__render_basic__samplers_busy__read; + counter->name = "Samplers Busy"; + counter->desc = "The percentage of time in which samplers have been processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 120; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_basic__gti_vf_throughput__read; + counter->name = "GTI Fixed Pipe Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between 3D Pipeline (Command Dispatch, Input Assembly and Stream Output) and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_basic__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x09) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__render_basic__sampler0_bottleneck__read; + counter->name = "Sampler 0 Bottleneck"; + counter->desc = "The percentage of time in which Sampler 0 has been slowing down the pipe when processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_basic__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_basic__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_basic__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_basic__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cflgt3__render_basic__avg_gpu_core_frequency__max(brw); + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_basic__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_basic__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_basic__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_basic__l3_lookups__read; + counter->name = "L3 Lookup Accesses w/o IC"; + counter->desc = "The total number of L3 cache lookup accesses w/o IC."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_basic__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_basic__gti_read_throughput__read; + counter->name = "GTI Read Throughput"; + counter->desc = "The total number of GPU memory bytes read from GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__render_basic__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 232; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__render_basic__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 236; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_basic__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__render_basic__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 248; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_basic__gti_depth_throughput__read; + counter->name = "GTI Depth Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between depth caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__render_basic__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 264; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__render_basic__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 268; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_basic__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_basic__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__render_basic__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 288; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_basic__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_basic__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__render_basic__sampler_bottleneck__read; + counter->name = "Samplers Bottleneck"; + counter->desc = "The percentage of time in which samplers have been slowing down the pipe when processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 312; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_basic__gti_hdc_lookups_throughput__read; + counter->name = "GTI HDC TLB Lookup Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between GTI and HDC, when HDC is doing TLB lookups."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_basic__gti_rcc_throughput__read; + counter->name = "GTI RCC Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between render color caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 328; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_basic__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 336; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_basic__gti_write_throughput__read; + counter->name = "GTI Write Throughput"; + counter->desc = "The total number of GPU memory bytes written to GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 344; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_basic__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 352; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_basic__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 360; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_basic__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 368; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_basic__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 376; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cflgt3_compute_basic_mux_regs[78]; +static struct brw_perf_query_register_prog cflgt3_compute_basic_b_counter_regs[5]; +static struct brw_perf_query_register_prog cflgt3_compute_basic_flex_regs[7]; + +static struct brw_perf_query_counter cflgt3_compute_basic_query_counters[39]; +static struct brw_perf_query_info cflgt3_compute_basic_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics Basic Gen9", + .guid = "607f9cc8-e026-4d5f-bfad-45c77eabc150", + .counters = cflgt3_compute_basic_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cflgt3_compute_basic_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cflgt3_compute_basic_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cflgt3_compute_basic_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cflgt3_register_compute_basic_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cflgt3_compute_basic_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F00E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124F1C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C00E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E0820 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F0900 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084F0032 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4F1891 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4F0E00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4F003C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004F0D80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024F003B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C0100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C6C000C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C0B00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0024 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A5BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E5B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C6000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C5C001B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0208 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CFB00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00BE }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19900157 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B900158 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900105 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900103 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900FFF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900821 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900802 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900802 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900422 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53904444 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_basic__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_basic__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_basic__untyped_bytes_read__read; + counter->name = "Untyped Bytes Read"; + counter->desc = "The total number of typed memory bytes read via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_basic__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_basic__typed_bytes_written__read; + counter->name = "Typed Bytes Written"; + counter->desc = "The total number of untyped memory bytes written via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_basic__fpu0_active__read; + counter->name = "EU FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_basic__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 44; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_basic__eu_avg_ipc_rate__read; + counter->name = "EU AVG IPC Rate"; + counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 2.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_basic__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_basic__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_basic__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_basic__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_basic__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_basic__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_basic__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_basic__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_basic__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cflgt3__compute_basic__avg_gpu_core_frequency__max(brw); + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_basic__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_basic__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_basic__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_basic__gti_read_throughput__read; + counter->name = "GTI Read Throughput"; + counter->desc = "The total number of GPU memory bytes read from GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_basic__untyped_bytes_written__read; + counter->name = "Untyped Writes"; + counter->desc = "The total number of untyped memory bytes written via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_basic__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_basic__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_basic__typed_bytes_read__read; + counter->name = "Typed Bytes Read"; + counter->desc = "The total number of typed memory bytes read via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_basic__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_basic__eu_thread_occupancy__read; + counter->name = "EU Thread Occupancy"; + counter->desc = "The percentage of time in which hardware threads occupied EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_basic__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 204; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_basic__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_basic__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_basic__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_basic__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_basic__gti_write_throughput__read; + counter->name = "GTI Write Throughput"; + counter->desc = "The total number of GPU memory bytes written to GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_basic__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_basic__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_basic__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_basic__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_basic__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_basic__eu_send_active__read; + counter->name = "EU Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 288; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cflgt3_render_pipe_profile_mux_regs[114]; +static struct brw_perf_query_register_prog cflgt3_render_pipe_profile_b_counter_regs[21]; +static struct brw_perf_query_register_prog cflgt3_render_pipe_profile_flex_regs[7]; + +static struct brw_perf_query_counter cflgt3_render_pipe_profile_query_counters[43]; +static struct brw_perf_query_info cflgt3_render_pipe_profile_query = { + .kind = OA_COUNTERS, + .name = "Render Metrics for 3D Pipeline Profile Gen9", + .guid = "9875e050-b1bc-45e6-a6ab-665594601df9", + .counters = cflgt3_render_pipe_profile_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cflgt3_render_pipe_profile_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cflgt3_render_pipe_profile_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cflgt3_render_pipe_profile_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cflgt3_register_render_pipe_profile_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cflgt3_render_pipe_profile_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0E001F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10116800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x178A03E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11824C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11830020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13840020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11850019 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11860007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01870C40 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17880000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020E5400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000E0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080F0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06104000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06110012 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06131000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01898000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D890100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03898000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B808000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0380C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8A0075 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D8A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x118A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B8A4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x138A8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D81A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15818000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17818000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B820030 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07828000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D824000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F828000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05824000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D830003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0583000C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09830000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03838000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07838000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B840980 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03844D80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11840000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09848000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09850080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03850003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01850000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07860000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F860400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09870032 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01888052 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11880000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09884000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B931001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D930001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19934000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B958000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950094 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19958000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09E58000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0BE58000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E5C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0592C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B928000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D924000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F924000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11928000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1392C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09924000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01985000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07988000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09981000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B982000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D982000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F989000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05982000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190C080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900440 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C21 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900042 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900024 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900841 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900400 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFEA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFC }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007AFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F5FD }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00079FFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000F3FB }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007BF7A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F7E7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FEFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000F7CF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00077FFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000EFDF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0006FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000CFBF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0003FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x00005F7F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__render_pipe_profile__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__render_pipe_profile__vs_bottleneck__read; + counter->name = "VS Bottleneck"; + counter->desc = "The percentage of time in which vertex shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__render_pipe_profile__hi_depth_bottleneck__read; + counter->name = "Hi-Depth Bottleneck"; + counter->desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__render_pipe_profile__gs_bottleneck__read; + counter->name = "GS Bottleneck"; + counter->desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__render_pipe_profile__bc_bottleneck__read; + counter->name = "BC Bottleneck"; + counter->desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__render_pipe_profile__hs_stall__read; + counter->name = "HS Stall"; + counter->desc = "The percentage of time in which hull stall pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 60; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cflgt3__render_pipe_profile__avg_gpu_core_frequency__max(brw); + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__render_pipe_profile__vf_bottleneck__read; + counter->name = "VF Bottleneck"; + counter->desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__render_pipe_profile__sf_bottleneck__read; + counter->name = "Strip-Fans Bottleneck"; + counter->desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__render_pipe_profile__sf_stall__read; + counter->name = "SF Stall"; + counter->desc = "The percentage of time in which strip-fans pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 140; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__render_pipe_profile__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__render_pipe_profile__hs_bottleneck__read; + counter->name = "HS Bottleneck"; + counter->desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__render_pipe_profile__cl_stall__read; + counter->name = "CL Stall"; + counter->desc = "The percentage of time in which clipper pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__render_pipe_profile__so_bottleneck__read; + counter->name = "SO Bottleneck"; + counter->desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__render_pipe_profile__ds_bottleneck__read; + counter->name = "DS Bottleneck"; + counter->desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__render_pipe_profile__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 188; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__render_pipe_profile__cl_bottleneck__read; + counter->name = "Clipper Bottleneck"; + counter->desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__render_pipe_profile__ds_stall__read; + counter->name = "DS Stall"; + counter->desc = "The percentage of time in which domain shader pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 196; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__render_pipe_profile__early_depth_bottleneck__read; + counter->name = "Early Depth Bottleneck"; + counter->desc = "The percentage of time in which early depth test pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__render_pipe_profile__so_stall__read; + counter->name = "SO Stall"; + counter->desc = "The percentage of time in which stream-output pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__render_pipe_profile__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cflgt3_memory_reads_mux_regs[47]; +static struct brw_perf_query_register_prog cflgt3_memory_reads_b_counter_regs[32]; +static struct brw_perf_query_register_prog cflgt3_memory_reads_flex_regs[7]; + +static struct brw_perf_query_counter cflgt3_memory_reads_query_counters[41]; +static struct brw_perf_query_info cflgt3_memory_reads_query = { + .kind = OA_COUNTERS, + .name = "Memory Reads Distribution Gen9", + .guid = "49c65f34-e625-4ca4-86b7-88693e624d4c", + .counters = cflgt3_memory_reads_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cflgt3_memory_reads_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cflgt3_memory_reads_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cflgt3_memory_reads_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cflgt3_register_memory_reads_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cflgt3_memory_reads_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1381001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900064 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03811300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05811B12 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0781001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E58000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05E5C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900150 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21900151 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23900152 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25900153 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27900154 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B900156 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D900157 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F90015F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900105 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900103 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900101 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C63 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900C63 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000272C, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002728, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000271C, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002718, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F872 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_reads__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__memory_reads__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_reads__gti_l3_bank0_reads__read; + counter->name = "GtiL3Bank0Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 0 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_reads__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_reads__gti_ring_accesses__read; + counter->name = "GtiRingAccesses"; + counter->desc = "The total number of all accesses from GTI to the ring."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_reads__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_reads__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_reads__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_reads__gti_l3_bank3_reads__read; + counter->name = "GtiL3Bank3Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 3 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_reads__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_reads__gti_rs_memory_reads__read; + counter->name = "GtiRsMemoryReads"; + counter->desc = "The total number of GTI memory reads from Resource Streamer."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_reads__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_reads__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_reads__gti_hiz_memory_reads__read; + counter->name = "GtiHizMemoryReads"; + counter->desc = "The total number of GTI memory reads from Hierarchical Depth Cache (Hi-Depth Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_reads__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_reads__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cflgt3__memory_reads__avg_gpu_core_frequency__max(brw); + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_reads__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_reads__gti_rcc_memory_reads__read; + counter->name = "GtiRccMemoryReads"; + counter->desc = "The total number of GTI memory reads from Render Color Cache (Render Color Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_reads__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_reads__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_reads__gti_l3_bank1_reads__read; + counter->name = "GtiL3Bank1Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 1 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__memory_reads__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_reads__gti_cmd_streamer_memory_reads__read; + counter->name = "GtiCmdStreamerMemoryReads"; + counter->desc = "The total number of GTI memory reads from Command Streamer."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_reads__gti_l3_bank2_reads__read; + counter->name = "GtiL3Bank2Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 2 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_reads__gti_memory_reads__read; + counter->name = "GtiMemoryReads"; + counter->desc = "The total number of GTI memory reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_reads__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_reads__gti_rcz_memory_reads__read; + counter->name = "GtiRczMemoryReads"; + counter->desc = "The total number of GTI memory reads from Render Depth Cache (Render Depth Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_reads__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_reads__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__memory_reads__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 232; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_reads__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_reads__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_reads__gti_msc_memory_reads__read; + counter->name = "GtiMscMemoryReads"; + counter->desc = "The total number of GTI memory reads from Multisampling Color Cache (Multisampling Color Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_reads__gti_vf_memory_reads__read; + counter->name = "GtiVfMemoryReads"; + counter->desc = "The total number of GTI memory reads from Vertex Fetch."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_reads__gti_stc_memory_reads__read; + counter->name = "GtiStcMemoryReads"; + counter->desc = "The total number of GTI memory reads from Stencil Cache (Stencil Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_reads__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_reads__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_reads__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_reads__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_reads__gti_l3_reads__read; + counter->name = "GtiL3Reads"; + counter->desc = "The total number of GTI memory reads from L3 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_reads__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cflgt3_memory_writes_mux_regs[47]; +static struct brw_perf_query_register_prog cflgt3_memory_writes_b_counter_regs[32]; +static struct brw_perf_query_register_prog cflgt3_memory_writes_flex_regs[7]; + +static struct brw_perf_query_counter cflgt3_memory_writes_query_counters[41]; +static struct brw_perf_query_info cflgt3_memory_writes_query = { + .kind = OA_COUNTERS, + .name = "Memory Writes Distribution Gen9", + .guid = "45c9e8ee-2998-4d83-88e8-9cb7e03287bf", + .counters = cflgt3_memory_writes_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cflgt3_memory_writes_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cflgt3_memory_writes_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cflgt3_memory_writes_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cflgt3_register_memory_writes_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cflgt3_memory_writes_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1381001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37906800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F901000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03811300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05811B12 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0781001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03E58000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05E5C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13900160 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21900161 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23900162 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25900163 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27900164 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29900165 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B900166 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D900167 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F900150 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31900105 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15900103 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17900101 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900C63 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900C63 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000272C, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002728, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000271C, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002718, .val = 0xFFFFFFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002758, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00006465 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002750, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007F81A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007F82A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007F822 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007F8BA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007F87A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007F8EA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007F8E2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007F8F2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00025024 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00035034 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00045044 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00055054 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00065064 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_writes__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__memory_writes__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_writes__gti_memory_writes__read; + counter->name = "GtiMemoryWrites"; + counter->desc = "The total number of GTI memory writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_writes__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_writes__gti_ring_accesses__read; + counter->name = "GtiRingAccesses"; + counter->desc = "The total number of all GTI accesses to the ring."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_writes__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_writes__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_writes__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_writes__gti_msc_memory_writes__read; + counter->name = "GtiMscMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Multisampling Color Cache (Multisampling Color Cache invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_writes__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_writes__gti_cmd_streamer_memory_writes__read; + counter->name = "GtiCmdStreamerMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Command Streamer."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_writes__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_writes__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_writes__gti_l3_bank0_writes__read; + counter->name = "GtiL3Bank0Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 0 (L3 Bank 0 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_writes__gti_l3_bank1_writes__read; + counter->name = "GtiL3Bank1Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 1 (L3 Bank 1 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_writes__gti_l3_bank2_writes__read; + counter->name = "GtiL3Bank2Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 2 (L3 Bank 2 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_writes__gti_l3_bank3_writes__read; + counter->name = "GtiL3Bank3Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 3 (L3 Bank 3 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_writes__gti_l3_writes__read; + counter->name = "GtiL3Writes"; + counter->desc = "The total number of GTI memory writes from L3 (L3 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_writes__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_writes__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cflgt3__memory_writes__avg_gpu_core_frequency__max(brw); + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_writes__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_writes__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_writes__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_writes__gti_rcc_memory_writes__read; + counter->name = "GtiRccMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Render Color Cache (Render Color Cache invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_writes__gti_so_memory_writes__read; + counter->name = "GtiSoMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Stream Output."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__memory_writes__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_writes__gti_stc_memory_writes__read; + counter->name = "GtiStcMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Stencil Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_writes__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_writes__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_writes__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__memory_writes__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 240; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_writes__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_writes__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_writes__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_writes__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_writes__gti_rcz_memory_writes__read; + counter->name = "GtiRczMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Render Depth Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_writes__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_writes__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_writes__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_writes__gti_hiz_memory_writes__read; + counter->name = "GtiHizMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Hierarchical Depth Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__memory_writes__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cflgt3_compute_extended_mux_regs[72]; +static struct brw_perf_query_register_prog cflgt3_compute_extended_b_counter_regs[21]; +static struct brw_perf_query_register_prog cflgt3_compute_extended_flex_regs[7]; + +static struct brw_perf_query_counter cflgt3_compute_extended_query_counters[38]; +static struct brw_perf_query_info cflgt3_compute_extended_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics Extended Gen9", + .guid = "bac415ce-d7a2-4f8d-9b16-834deba7330e", + .counters = cflgt3_compute_extended_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cflgt3_compute_extended_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cflgt3_compute_extended_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cflgt3_compute_extended_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cflgt3_register_compute_extended_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cflgt3_compute_extended_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C00E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8160 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C0120 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x184E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4EAAA0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C0B01 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C000C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001C0041 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061C4200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081C4443 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1C4645 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1C7647 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041C7357 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0030 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4CAA2A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C02AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5515 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0155 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CAA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11907FFF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900802 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FC2A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FC6A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x0007FC92 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0007FCA2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FC32 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FC9A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x0007FE6A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000BF00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x0007FE7A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000BF00 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00778008 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00088078 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00808708 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00A08908 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_extended__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_extended__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_extended__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_extended__fpu0_active__read; + counter->name = "EU FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_extended__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_extended__eu_avg_ipc_rate__read; + counter->name = "EU AVG IPC Rate"; + counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 2.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_extended__typed_writes0__read; + counter->name = "Typed Writes 0"; + counter->desc = "The subslice 0 typed writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_extended__eu_typed_atomics0__read; + counter->name = "EuTypedAtomics0"; + counter->desc = "The subslice 0 EU Typed Atomics subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_extended__typed_atomics0__read; + counter->name = "Typed Atomics 0"; + counter->desc = "The subslice 0 typed atomics."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_extended__typed_atomics_per_cache_line__read; + counter->name = "TypedAtomicsPerCacheLine"; + counter->desc = "The ratio of EU typed atomics requests to L3 cache line writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_extended__eu_untyped_reads0__read; + counter->name = "EuUntypedReads0"; + counter->desc = "The subslice 0 EU Untyped Reads subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_extended__untyped_writes0__read; + counter->name = "Untyped Writes 0"; + counter->desc = "The subslice 0 untyped writes (including SLM writes)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_extended__eu_untyped_atomics0__read; + counter->name = "EuUntypedAtomics0"; + counter->desc = "The subslice 0 EU Untyped Atomics subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_extended__eu_untyped_writes0__read; + counter->name = "EuUntypedWrites0"; + counter->desc = "The subslice 0 EU Untyped Writes subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_extended__eu_a64_untyped_writes0__read; + counter->name = "EuA64UntypedWrites0"; + counter->desc = "The subslice 0 EU A64 Untyped Writes subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_extended__untyped_writes_per_cache_line__read; + counter->name = "UntypedWritesPerCacheLine"; + counter->desc = "The ratio of EU untyped write requests to L3 cache line writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_extended__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_extended__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_extended__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_extended__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cflgt3__compute_extended__avg_gpu_core_frequency__max(brw); + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_extended__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_extended__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_extended__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_extended__eu_typed_writes0__read; + counter->name = "EuTypedWrites0"; + counter->desc = "The subslice 0 EU Typed Writes subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_extended__typed_writes_per_cache_line__read; + counter->name = "TypedWritesPerCacheLine"; + counter->desc = "The ratio of EU typed write requests to L3 cache line writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_extended__typed_reads0__read; + counter->name = "Typed Reads 0"; + counter->desc = "The subslice 0 typed reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_extended__untyped_reads0__read; + counter->name = "Untyped Reads 0"; + counter->desc = "The subslice 0 untyped reads (including SLM reads)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_extended__eu_a64_untyped_reads0__read; + counter->name = "EuA64UntypedReads0"; + counter->desc = "The subslice 0 EU A64 Untyped Reads subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_extended__eu_thread_occupancy__read; + counter->name = "EU Thread Occupancy"; + counter->desc = "The percentage of time in which hardware threads occupied EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 208; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_extended__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 212; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_extended__eu_typed_reads0__read; + counter->name = "EuTypedReads0"; + counter->desc = "The subslice 0 EU Typed Reads subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_extended__untyped_reads_per_cache_line__read; + counter->name = "UntypedReadsPerCacheLine"; + counter->desc = "The ratio of EU untyped read requests to L3 cache line reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_extended__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_extended__typed_reads_per_cache_line__read; + counter->name = "TypedReadsPerCacheLine"; + counter->desc = "The ratio of EU typed read requests to L3 cache line reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_extended__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_extended__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_extended__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_extended__eu_send_active__read; + counter->name = "EU Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 272; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cflgt3_compute_l3_cache_mux_regs[60]; +static struct brw_perf_query_register_prog cflgt3_compute_l3_cache_b_counter_regs[13]; +static struct brw_perf_query_register_prog cflgt3_compute_l3_cache_flex_regs[7]; + +static struct brw_perf_query_counter cflgt3_compute_l3_cache_query_counters[54]; +static struct brw_perf_query_info cflgt3_compute_l3_cache_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics L3 Cache Gen9", + .guid = "a8cfca44-0e74-4338-9e57-3daad98957dd", + .counters = cflgt3_compute_l3_cache_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cflgt3_compute_l3_cache_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cflgt3_compute_l3_cache_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cflgt3_compute_l3_cache_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cflgt3_register_compute_l3_cache_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cflgt3_compute_l3_cache_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C0760 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1593001E }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x184E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E8020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0051 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C5C5D }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C5E5F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1CE000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C0030 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C2A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F1500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0140 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162C0A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03933300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05930032 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D900157 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F900158 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190030F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900021 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53904444 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FEFE }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FEFD }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FBEF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x0007FFFA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FBDF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00101100 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00201200 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00301300 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00401400 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_l3_cache__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__l3_bank03_accesses__read; + counter->name = "L3 Bank 03 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 03."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__l3_accesses__read; + counter->name = "L3 Accesses"; + counter->desc = "The total number of L3 accesses from all entities."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_l3_cache__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__l3_sampler_throughput__read; + counter->name = "L3 Sampler Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_l3_cache__fpu0_active__read; + counter->name = "EU FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_l3_cache__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 52; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_l3_cache__eu_avg_ipc_rate__read; + counter->name = "EU AVG IPC Rate"; + counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 2.0; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_l3_cache__eu_binary_fpu0_instruction__read; + counter->name = "EU FPU0 Binary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 60; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_l3_cache__eu_hybrid_fpu0_instruction__read; + counter->name = "EU FPU0 Hybrid Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 104; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__l3_misses__read; + counter->name = "L3 Misses"; + counter->desc = "The total number of L3 misses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__l3_bank00_accesses__read; + counter->name = "L3 Bank 00 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 00."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_l3_cache__eu_move_fpu0_instruction__read; + counter->name = "EU FPU0 Move Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_l3_cache__eu_hybrid_fpu1_instruction__read; + counter->name = "EU FPU1 Hybrid Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cflgt3__compute_l3_cache__avg_gpu_core_frequency__max(brw); + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__gti_read_throughput__read; + counter->name = "GTI Read Throughput"; + counter->desc = "The total number of GPU memory bytes read from GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__gti_l3_throughput__read; + counter->name = "GTI L3 Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__l3_bank00_ic_accesses__read; + counter->name = "L3 Bank 00 IC Accesses"; + counter->desc = "The total number of accesses to L3 Bank 00 from IC cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + } + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__l3_bank00_ic_hits__read; + counter->name = "L3 Bank 00 IC Hits"; + counter->desc = "The total number of hits in L3 Bank 00 from IC cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__sampler_accesses__read; + counter->name = "Sampler Accesses"; + counter->desc = "The total number of messages send to samplers."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__l3_bank01_accesses__read; + counter->name = "L3 Bank 01 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 01."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_l3_cache__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 256; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_l3_cache__eu_ternary_fpu0_instruction__read; + counter->name = "EU FPU0 Ternary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 260; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_l3_cache__eu_move_fpu1_instruction__read; + counter->name = "EU FPU1 Move Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 296; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_l3_cache__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 300; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x01) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__l3_bank02_accesses__read; + counter->name = "L3 Bank 02 Accesses"; + counter->desc = "The total number of accesses to L3 Bank 02."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 328; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__l3_total_throughput__read; + counter->name = "L3 Total Throughput"; + counter->desc = "The total number of GPU memory bytes transferred via L3."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 336; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__gti_write_throughput__read; + counter->name = "GTI Write Throughput"; + counter->desc = "The total number of GPU memory bytes written to GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 344; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 352; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 360; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_l3_cache__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 368; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_l3_cache__eu_binary_fpu1_instruction__read; + counter->name = "EU FPU1 Binary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 376; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_l3_cache__eu_ternary_fpu1_instruction__read; + counter->name = "EU FPU1 Ternary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 380; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_l3_cache__eu_send_active__read; + counter->name = "EU Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 384; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cflgt3_hdc_and_sf_mux_regs[54]; +static struct brw_perf_query_register_prog cflgt3_hdc_and_sf_b_counter_regs[9]; +static struct brw_perf_query_register_prog cflgt3_hdc_and_sf_flex_regs[7]; + +static struct brw_perf_query_counter cflgt3_hdc_and_sf_query_counters[39]; +static struct brw_perf_query_info cflgt3_hdc_and_sf_query = { + .kind = OA_COUNTERS, + .name = "Metric set HDCAndSF", + .guid = "3d9acca5-8d39-4c34-89ee-f921848d8562", + .counters = cflgt3_hdc_and_sf_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cflgt3_hdc_and_sf_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cflgt3_hdc_and_sf_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cflgt3_hdc_and_sf_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cflgt3_register_hdc_and_sf_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cflgt3_hdc_and_sf_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x104F0232 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x124F4640 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0232 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11834400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004F1880 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024F08BB }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044F001B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C0100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C000B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C1800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x045B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x145C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x165C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x185C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C00A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F828000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F8305C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09830000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07830000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13928000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F988000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FDFF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__hdc_and_sf__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__hdc_and_sf__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__hdc_and_sf__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__hdc_and_sf__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__hdc_and_sf__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__hdc_and_sf__poly_data_ready__read; + counter->name = "Polygon Data Ready"; + counter->desc = "The percentage of time in which geometry pipeline output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cflgt3__hdc_and_sf__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read; + counter->name = "HDC stalled by L3 (s0.ss1)"; + counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss1)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 120; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read; + counter->name = "HDC stalled by L3 (s0.ss2)"; + counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss2)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__hdc_and_sf__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__hdc_and_sf__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__hdc_and_sf__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__hdc_and_sf__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 164; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__hdc_and_sf__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__hdc_and_sf__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read; + counter->name = "HDC stalled by L3 (s0.ss0)"; + counter->desc = "Percentage of time when HDC has messges to L3, but it's stalled due to lack of credits (s0.ss0)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 264; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__hdc_and_sf__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cflgt3_l3_1_mux_regs[71]; +static struct brw_perf_query_register_prog cflgt3_l3_1_b_counter_regs[22]; +static struct brw_perf_query_register_prog cflgt3_l3_1_flex_regs[7]; + +static struct brw_perf_query_counter cflgt3_l3_1_query_counters[39]; +static struct brw_perf_query_info cflgt3_l3_1_query = { + .kind = OA_COUNTERS, + .name = "Metric set L3_1", + .guid = "93e582ea-de69-46e3-81b5-73386164c047", + .counters = cflgt3_l3_1_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cflgt3_l3_1_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cflgt3_l3_1_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cflgt3_l3_1_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cflgt3_register_l3_1_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cflgt3_l3_1_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C7B40 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C0020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A603444 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A613400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4EA800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C4E0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C6C5327 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C5425 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C2A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C285B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C005C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1C003C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10600000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04600000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C610044 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10610000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06610000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C02A8 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0154 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C00AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FFC0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900420 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900021 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900421 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00014002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000C3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00010002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000C7FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00004002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000D3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100700 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FF1F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00001402 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FC3F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00001002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FC7F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00000402 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FD3F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_1__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_1__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_1__l30_bank1_active__read; + counter->name = "Slice0 L3 Bank1 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank1 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_1__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_1__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_1__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_1__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_1__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_1__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_1__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_1__l30_bank1_stalled__read; + counter->name = "Slice0 L3 Bank1 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank1 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_1__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_1__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_1__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_1__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_1__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_1__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cflgt3__l3_1__avg_gpu_core_frequency__max(brw); + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_1__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_1__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_1__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_1__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_1__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_1__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_1__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_1__l30_bank0_active__read; + counter->name = "Slice0 L3 Bank0 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank0 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_1__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_1__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_1__l30_bank0_stalled__read; + counter->name = "Slice0 L3 Bank0 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank0 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 180; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_1__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_1__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_1__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_1__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_1__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_1__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_1__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_1__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_1__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_1__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_1__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cflgt3_l3_2_mux_regs[44]; +static struct brw_perf_query_register_prog cflgt3_l3_2_b_counter_regs[14]; +static struct brw_perf_query_register_prog cflgt3_l3_2_flex_regs[7]; + +static struct brw_perf_query_counter cflgt3_l3_2_query_counters[37]; +static struct brw_perf_query_info cflgt3_l3_2_query = { + .kind = OA_COUNTERS, + .name = "Metric set L3_2", + .guid = "6e3680f3-8347-4e26-b930-3900d18d1322", + .counters = cflgt3_l3_2_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cflgt3_l3_2_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cflgt3_l3_2_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cflgt3_l3_2_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cflgt3_register_l3_2_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cflgt3_l3_2_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C02E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146C0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A623400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C3324 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C3422 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C0800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x065B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A5C1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06614000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C620044 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10620000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06620000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190F800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00028002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x000087FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00020002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00008FFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00008002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000A7FF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_2__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_2__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_2__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_2__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_2__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_2__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_2__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_2__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_2__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_2__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_2__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_2__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_2__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_2__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_2__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cflgt3__l3_2__avg_gpu_core_frequency__max(brw); + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_2__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_2__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_2__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_2__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 128; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_2__l30_bank2_stalled__read; + counter->name = "Slice0 L3 Bank2 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank2 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 132; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_2__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_2__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 140; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_2__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_2__l30_bank2_active__read; + counter->name = "Slice0 L3 Bank2 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank2 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_2__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_2__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_2__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_2__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_2__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 184; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_2__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_2__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_2__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_2__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_2__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_2__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_2__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_2__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cflgt3_l3_3_mux_regs[43]; +static struct brw_perf_query_register_prog cflgt3_l3_3_b_counter_regs[14]; +static struct brw_perf_query_register_prog cflgt3_l3_3_flex_regs[7]; + +static struct brw_perf_query_counter cflgt3_l3_3_query_counters[37]; +static struct brw_perf_query_info cflgt3_l3_3_query = { + .kind = OA_COUNTERS, + .name = "Metric set L3_3", + .guid = "1f513186-11d6-422d-a879-be86f2d08414", + .counters = cflgt3_l3_3_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cflgt3_l3_3_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cflgt3_l3_3_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cflgt3_l3_3_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cflgt3_register_l3_3_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cflgt3_l3_3_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C4E80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A633400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C3321 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x046C342F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x181C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1C1800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06604000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C630044 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10630000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06630000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C00AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0055 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190F800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100070 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF1 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00028002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x000087FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00020002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00008FFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00008002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000A7FF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_3__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_3__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_3__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_3__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_3__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_3__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_3__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_3__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_3__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_3__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_3__l30_bank3_stalled__read; + counter->name = "Slice0 L3 Bank3 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank3 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_3__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_3__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_3__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_3__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_3__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cflgt3__l3_3__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_3__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_3__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_3__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_3__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_3__l30_bank3_active__read; + counter->name = "Slice0 L3 Bank3 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank3 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 140; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_3__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_3__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_3__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_3__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_3__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_3__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_3__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__l3_3__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_3__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_3__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_3__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_3__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_3__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_3__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_3__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__l3_3__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cflgt3_rasterizer_and_pixel_backend_mux_regs[31]; +static struct brw_perf_query_register_prog cflgt3_rasterizer_and_pixel_backend_b_counter_regs[10]; +static struct brw_perf_query_register_prog cflgt3_rasterizer_and_pixel_backend_flex_regs[7]; + +static struct brw_perf_query_counter cflgt3_rasterizer_and_pixel_backend_query_counters[40]; +static struct brw_perf_query_info cflgt3_rasterizer_and_pixel_backend_query = { + .kind = OA_COUNTERS, + .name = "Metric set RasterizerAndPixelBackend", + .guid = "d37d4266-b749-48b2-9652-c24b91784fc6", + .counters = cflgt3_rasterizer_and_pixel_backend_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cflgt3_rasterizer_and_pixel_backend_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cflgt3_rasterizer_and_pixel_backend_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cflgt3_rasterizer_and_pixel_backend_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cflgt3_register_rasterizer_and_pixel_backend_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cflgt3_rasterizer_and_pixel_backend_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x102F3800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x144D0500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x120D03C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x140D03CF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0004 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4E4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F0480 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0090 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064D0027 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004D0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D0D40 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020D803F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040D8023 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100D0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020F0010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0050 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41901400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43901485 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000EFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00006000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F3FF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__rasterizer_and_pixel_backend__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__rasterizer_and_pixel_backend__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__rasterizer_and_pixel_backend__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__rasterizer_and_pixel_backend__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__rasterizer_and_pixel_backend__pixel_values0_ready__read; + counter->name = "Slice0 Pixel Values Ready"; + counter->desc = "The percentage of time in which slice0 pixel values are ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cflgt3__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__rasterizer_and_pixel_backend__rasterizer0_input_available__read; + counter->name = "Slice0 Rasterizer Input Available"; + counter->desc = "The percentage of time in which slice0 rasterizer input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 128; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__rasterizer_and_pixel_backend__pixel_data0_ready__read; + counter->name = "Slice0 Post-EarlyZ Pixel Data Ready"; + counter->desc = "The percentage of time in which slice0 post-EarlyZ pixel data is ready (after early Z tests have been applied)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 132; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__rasterizer_and_pixel_backend__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__rasterizer_and_pixel_backend__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__rasterizer_and_pixel_backend__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__rasterizer_and_pixel_backend__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__rasterizer_and_pixel_backend__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__rasterizer_and_pixel_backend__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__rasterizer_and_pixel_backend__rasterizer0_output_ready__read; + counter->name = "Slice0 Rasterizer Output Ready"; + counter->desc = "The percentage of time in which slice0 rasterizer output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 196; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__rasterizer_and_pixel_backend__ps_output0_available__read; + counter->name = "Slice0 PS Output Available"; + counter->desc = "The percentage of time in which slice0 PS output is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 256; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__rasterizer_and_pixel_backend__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cflgt3_sampler_mux_regs[69]; +static struct brw_perf_query_register_prog cflgt3_sampler_b_counter_regs[12]; +static struct brw_perf_query_register_prog cflgt3_sampler_flex_regs[7]; + +static struct brw_perf_query_counter cflgt3_sampler_query_counters[41]; +static struct brw_perf_query_info cflgt3_sampler_query = { + .kind = OA_COUNTERS, + .name = "Metric set Sampler", + .guid = "5951c1d7-feef-4981-b0b5-4e4983023119", + .counters = cflgt3_sampler_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cflgt3_sampler_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cflgt3_sampler_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cflgt3_sampler_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cflgt3_register_sampler_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cflgt3_sampler_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14152C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16150005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121600A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14352C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16350005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123600A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14552C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16550005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125600A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062F6000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C0050 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0350 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FB000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F00DA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C0028 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022DC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C138000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E132000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0413C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C140018 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C157000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E150078 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10150000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04162180 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02160000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04174000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0233A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04333000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14348000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16348000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02357870 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10350000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04360043 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02360000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04371000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E538000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00538000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06533000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C540020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12548000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E557000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00557800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10550000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06560043 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02560000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06571000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FF80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900060 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900060 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x70800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0000C000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000E7FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00003000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F9FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000C00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE7F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__sampler__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__sampler__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__sampler__sampler02_input_available__read; + counter->name = "Slice0 Subslice2 Input Available"; + counter->desc = "The percentage of time in which slice0 subslice2 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__sampler__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__sampler__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__sampler__sampler00_input_available__read; + counter->name = "Slice0 Subslice0 Input Available"; + counter->desc = "The percentage of time in which slice0 subslice0 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__sampler__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 28; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__sampler__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__sampler__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__sampler__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__sampler__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__sampler__sampler02_output_ready__read; + counter->name = "Slice0 Subslice2 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice0 subslice2 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__sampler__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__sampler__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__sampler__sampler01_input_available__read; + counter->name = "Slice0 Subslice1 Input Available"; + counter->desc = "The percentage of time in which slice0 subslice1 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 88; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__sampler__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__sampler__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__sampler__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__sampler__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cflgt3__sampler__avg_gpu_core_frequency__max(brw); + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__sampler__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__sampler__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__sampler__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__sampler__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__sampler__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__sampler__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__sampler__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 164; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__sampler__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__sampler__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__sampler__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__sampler__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__sampler__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__sampler__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__sampler__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__sampler__sampler00_output_ready__read; + counter->name = "Slice0 Subslice0 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice0 subslice0 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 224; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__sampler__sampler01_output_ready__read; + counter->name = "Slice0 Subslice1 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice0 subslice1 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 228; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__sampler__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__sampler__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__sampler__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__sampler__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__sampler__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__sampler__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cflgt3_tdl_1_mux_regs[68]; +static struct brw_perf_query_register_prog cflgt3_tdl_1_b_counter_regs[18]; +static struct brw_perf_query_register_prog cflgt3_tdl_1_flex_regs[7]; + +static struct brw_perf_query_counter cflgt3_tdl_1_query_counters[41]; +static struct brw_perf_query_info cflgt3_tdl_1_query = { + .kind = OA_COUNTERS, + .name = "Metric set TDL_1", + .guid = "bf279ed6-b3dd-43f3-9810-cb55cb78fc62", + .counters = cflgt3_tdl_1_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cflgt3_tdl_1_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cflgt3_tdl_1_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cflgt3_tdl_1_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cflgt3_register_tdl_1_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cflgt3_tdl_1_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12120000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12320000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12520000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F3000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F03A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FF000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0095 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02108000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0410C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02118000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0411C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02121880 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041219B5 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02134000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04135000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C308000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E304000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06304000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C318000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E314000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06314000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C321A80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E320033 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06320031 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00320000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C334000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E331000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06331000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E508000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00508000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02504000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E518000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00518000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02514000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E521880 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00521A80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02520033 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E534000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00534000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02531000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FF80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B900062 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x59900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00007FFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00009FFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000EFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000F3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FDFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE7F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_1__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__tdl_1__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__tdl_1__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__tdl_1__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__tdl_1__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_1__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_1__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__tdl_1__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_1__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_1__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__tdl_1__non_ps_thread02_ready_for_dispatch__read; + counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice2"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_1__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_1__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_1__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_1__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_1__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cflgt3__tdl_1__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_1__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__tdl_1__non_ps_thread00_ready_for_dispatch__read; + counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice0"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 120; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_1__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_1__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__tdl_1__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__tdl_1__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__tdl_1__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__tdl_1__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__tdl_1__ps_thread00_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice0"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_1__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__tdl_1__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_1__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_1__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__tdl_1__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_1__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_1__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__tdl_1__ps_thread01_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice1"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 224; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_1__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_1__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__tdl_1__ps_thread02_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice2"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 248; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_1__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_1__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_1__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_1__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__tdl_1__non_ps_thread01_ready_for_dispatch__read; + counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice1"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 288; + counter->size = sizeof(float); + } + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cflgt3_tdl_2_mux_regs[42]; +static struct brw_perf_query_register_prog cflgt3_tdl_2_b_counter_regs[6]; +static struct brw_perf_query_register_prog cflgt3_tdl_2_flex_regs[7]; + +static struct brw_perf_query_counter cflgt3_tdl_2_query_counters[41]; +static struct brw_perf_query_info cflgt3_tdl_2_query = { + .kind = OA_COUNTERS, + .name = "Metric set TDL_2", + .guid = "a70c3fa2-e705-4f5a-8883-2ebd0feef1d2", + .counters = cflgt3_tdl_2_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cflgt3_tdl_2_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cflgt3_tdl_2_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cflgt3_tdl_2_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cflgt3_register_tdl_2_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cflgt3_tdl_2_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12124D60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12322E60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12524D60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F3000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0014 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0FE000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F0097 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x082C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062D4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0410C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0411C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04121FB7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04135000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00308000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06304000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00318000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06314000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00321B80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0632003F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00334000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06331000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0250C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0251C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02521FB7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00520000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02535000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900063 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00015014 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00055054 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_2__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__tdl_2__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__tdl_2__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__tdl_2__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__tdl_2__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_2__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_2__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__tdl_2__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_2__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_2__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_2__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_2__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_2__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__tdl_2__thread_header01_ready_port0__read; + counter->name = "Thread Header Ready on Slice0 Subslice1 Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 88; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__tdl_2__thread_header01_ready_port1__read; + counter->name = "Thread Header Ready on Slice0 Subslice1 Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 92; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_2__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_2__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cflgt3__tdl_2__avg_gpu_core_frequency__max(brw); + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_2__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_2__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_2__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__tdl_2__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__tdl_2__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 140; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__tdl_2__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__tdl_2__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__tdl_2__thread_header02_ready_port1__read; + counter->name = "Thread Header Ready on Slice0 Subslice2 Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 0x4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__tdl_2__thread_header02_ready_port0__read; + counter->name = "Thread Header Ready on Slice0 Subslice2 Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_2__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__tdl_2__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_2__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_2__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__tdl_2__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_2__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_2__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_2__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_2__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_2__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_2__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_2__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__tdl_2__thread_header00_ready_port0__read; + counter->name = "Thread Header Ready on Slice0 Subslice0 Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 256; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__tdl_2__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 0x1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__tdl_2__thread_header00_ready_port1__read; + counter->name = "Thread Header Ready on Slice0 Subslice0 Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 272; + counter->size = sizeof(float); + } + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cflgt3_compute_extra_mux_regs[69]; + +static struct brw_perf_query_counter cflgt3_compute_extra_query_counters[5]; +static struct brw_perf_query_info cflgt3_compute_extra_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics Extra Gen9", + .guid = "e61ae394-9d9e-4204-a735-1dad7e44d953", + .counters = cflgt3_compute_extra_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cflgt3_compute_extra_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ +}; + +static void +cflgt3_register_compute_extra_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cflgt3_compute_extra_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121203E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123203E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125203E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x129203E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12B203E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12D203E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x024EC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x044EC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x064EC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x084CA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C0042 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x020DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x040DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F006D }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x062C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06104000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06114000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06120033 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00120000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06131000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04308000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04318000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04321980 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00320000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04334000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04504000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04514000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04520033 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00520000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04531000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00AF8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ACC0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x008D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x028DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C8FB000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E8F0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06AC8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02AD4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02918000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02921980 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00920000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02934000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B04000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B14000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B20033 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00B20000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B31000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D08000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D18000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D21980 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00D34000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1190FC00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900420 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x459000A1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_extra__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_extra__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_extra__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__compute_extra__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cflgt3__compute_extra__avg_gpu_core_frequency__max(brw); + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__compute_extra__fpu1_active_adjusted__read; + counter->name = "EU FPU1 Pipe Active including Ext Math"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing including Extended Math processing"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cflgt3_vme_pipe_mux_regs[73]; +static struct brw_perf_query_register_prog cflgt3_vme_pipe_b_counter_regs[17]; +static struct brw_perf_query_register_prog cflgt3_vme_pipe_flex_regs[2]; + +static struct brw_perf_query_counter cflgt3_vme_pipe_query_counters[10]; +static struct brw_perf_query_info cflgt3_vme_pipe_query = { + .kind = OA_COUNTERS, + .name = "Media Vme Pipe Gen9", + .guid = "94272ad9-45ee-4e34-b7a7-51546cd6405c", + .counters = cflgt3_vme_pipe_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cflgt3_vme_pipe_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cflgt3_vme_pipe_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cflgt3_vme_pipe_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cflgt3_register_vme_pipe_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cflgt3_vme_pipe_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x141A5800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161A00C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12180240 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14180002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x149A5800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x169A00C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12980240 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14980002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A4E3FC0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002F1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x022F8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x042F3000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x004C4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A4C9500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C4C002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x000D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x060D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x080DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C0F0400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E0F5500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x100F0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x002C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E2C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x162CAA00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x182C000A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04193000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081A28C1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00133000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0613C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0813F000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00172000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06178000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0817A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00180037 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06180940 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08180000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02180000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04183000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04AFC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06AF3000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ACC4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CCC0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C8DA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E8F4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x108F0015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16ACA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18AC000A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06993000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C9A28C1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x009A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A93F000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C93F000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A97A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C97A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A980977 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08980000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04980000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06983000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x119000FF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41900020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x55900004 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x479008A5 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x57900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49900002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00100030 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFF9 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FFFC }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FFF3 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100180 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFCF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FF3F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00008003 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__vme_pipe__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__vme_pipe__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__vme_pipe__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__vme_pipe__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__vme_pipe__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cflgt3__vme_pipe__avg_gpu_core_frequency__max(brw); + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__vme_pipe__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__vme_pipe__eu_thread_occupancy__read; + counter->name = "EU Thread Occupancy"; + counter->desc = "The percentage of time in which hardware threads occupied EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__vme_pipe__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 44; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__vme_pipe__vme_busy__read; + counter->name = "VME Busy"; + counter->desc = "The percentage of time in which VME (IME or CRE) was actively processing data."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__vme_pipe__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 52; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cflgt3_gpu_busyness_mux_regs[42]; +static struct brw_perf_query_register_prog cflgt3_gpu_busyness_b_counter_regs[7]; + +static struct brw_perf_query_counter cflgt3_gpu_busyness_query_counters[9]; +static struct brw_perf_query_info cflgt3_gpu_busyness_query = { + .kind = OA_COUNTERS, + .name = "Gpu Rings Busyness", + .guid = "22b7e0c2-cade-425f-b099-34479768c72a", + .counters = cflgt3_gpu_busyness_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cflgt3_gpu_busyness_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cflgt3_gpu_busyness_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ +}; + +static void +cflgt3_register_gpu_busyness_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cflgt3_gpu_busyness_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19D05800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13805800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05962C25 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19950016 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19C05800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05D00085 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25D00000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09D54000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07800035 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11800000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21960000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0996C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B964000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19938000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930068 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15948000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B94000C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03957500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D950000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17950000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07928000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03988000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19904000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09978000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05C08500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25C00000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1BC00000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0BC54000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x51900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43900463 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0007C000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x000007FF }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__gpu_busyness__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__gpu_busyness__vebox_busy__read; + counter->name = "Vebox Ring Busy"; + counter->desc = "The percentage of time when vebox command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__gpu_busyness__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__gpu_busyness__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cflgt3__gpu_busyness__avg_gpu_core_frequency__max(brw); + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__gpu_busyness__render_busy__read; + counter->name = "Render Ring Busy"; + counter->desc = "The percentage of time when render command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__gpu_busyness__vdbox0_busy__read; + counter->name = "Vdbox0 Ring Busy"; + counter->desc = "The percentage of time when Vdbox0 command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 36; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__gpu_busyness__blitter_busy__read; + counter->name = "Blitter Ring Busy"; + counter->desc = "The percentage of time when blitter command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__gpu_busyness__any_ring_busy__read; + counter->name = "AnyRingBusy"; + counter->desc = "The percentage of time when any command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 44; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cflgt3__gpu_busyness__vdbox1_busy__read; + counter->name = "Vdbox1 Ring Busy"; + counter->desc = "The percentage of time when Vdbox1 command streamer was busy."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cflgt3_test_oa_mux_regs[13]; +static struct brw_perf_query_register_prog cflgt3_test_oa_b_counter_regs[22]; + +static struct brw_perf_query_counter cflgt3_test_oa_query_counters[12]; +static struct brw_perf_query_info cflgt3_test_oa_query = { + .kind = OA_COUNTERS, + .name = "MDAPI testing set Gen9", + .guid = "577e8e2c-3fa0-4875-8743-3538d585e3b0", + .counters = cflgt3_test_oa_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cflgt3_test_oa_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cflgt3_test_oa_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ +}; + +static void +cflgt3_register_test_oa_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cflgt3_test_oa_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07810013 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D810000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B930040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07E54000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F908000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x37900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x53900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x45900000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33900000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000004 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000003 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000007 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFF7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00100082 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFEF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x001000C2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FFE7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00100001 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FFE7 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__test_oa__counter7__read; + counter->name = "TestCounter7"; + counter->desc = "HW test counter 7. Factor: 0.666"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__test_oa__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 8; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__test_oa__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__test_oa__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cflgt3__test_oa__avg_gpu_core_frequency__max(brw); + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__test_oa__counter8__read; + counter->name = "TestCounter8"; + counter->desc = "HW test counter 8. Should be equal to 1."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__test_oa__counter4__read; + counter->name = "TestCounter4"; + counter->desc = "HW test counter 4. Factor: 0.333"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__test_oa__counter5__read; + counter->name = "TestCounter5"; + counter->desc = "HW test counter 5. Factor: 0.333"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__test_oa__counter6__read; + counter->name = "TestCounter6"; + counter->desc = "HW test counter 6. Factor: 0.166"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__test_oa__counter3__read; + counter->name = "TestCounter3"; + counter->desc = "HW test counter 3. Factor: 0.5"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__test_oa__counter0__read; + counter->name = "TestCounter0"; + counter->desc = "HW test counter 0. Factor: 0.0"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__test_oa__counter1__read; + counter->name = "TestCounter1"; + counter->desc = "HW test counter 1. Factor: 1.0"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cflgt3__test_oa__counter2__read; + counter->name = "TestCounter2"; + counter->desc = "HW test counter 2. Factor: 1.0"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +void +brw_oa_register_queries_cflgt3(struct brw_context *brw) +{ + cflgt3_register_render_basic_counter_query(brw); + cflgt3_register_compute_basic_counter_query(brw); + cflgt3_register_render_pipe_profile_counter_query(brw); + cflgt3_register_memory_reads_counter_query(brw); + cflgt3_register_memory_writes_counter_query(brw); + cflgt3_register_compute_extended_counter_query(brw); + cflgt3_register_compute_l3_cache_counter_query(brw); + cflgt3_register_hdc_and_sf_counter_query(brw); + cflgt3_register_l3_1_counter_query(brw); + cflgt3_register_l3_2_counter_query(brw); + cflgt3_register_l3_3_counter_query(brw); + cflgt3_register_rasterizer_and_pixel_backend_counter_query(brw); + cflgt3_register_sampler_counter_query(brw); + cflgt3_register_tdl_1_counter_query(brw); + cflgt3_register_tdl_2_counter_query(brw); + cflgt3_register_compute_extra_counter_query(brw); + cflgt3_register_vme_pipe_counter_query(brw); + cflgt3_register_gpu_busyness_counter_query(brw); + cflgt3_register_test_oa_counter_query(brw); +} + +static struct brw_perf_query_register_prog cnl_render_basic_mux_regs[98]; +static struct brw_perf_query_register_prog cnl_render_basic_b_counter_regs[7]; +static struct brw_perf_query_register_prog cnl_render_basic_flex_regs[5]; + +static struct brw_perf_query_counter cnl_render_basic_query_counters[51]; +static struct brw_perf_query_info cnl_render_basic_query = { + .kind = OA_COUNTERS, + .name = "Render Metrics Basic Gen10", + .guid = "ee9f2b17-a8b3-44c3-bf0c-2608b9665e23", + .counters = cnl_render_basic_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cnl_render_basic_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cnl_render_basic_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cnl_render_basic_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cnl_register_render_basic_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cnl_render_basic_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146C0008 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18110014 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14EC0008 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18910014 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A6C0054 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0444 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02738000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0473E000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04742000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C742000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04752000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C752000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C760800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E760800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0077C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E778000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1477C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x167702A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00194000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A190020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00110060 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08110061 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E110000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10110000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18144000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C140400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AEC5400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10EC0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1AEC0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04F38000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AF48000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CF48000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AF58000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CF58000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EF62200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EF7C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16F70230 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E994000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A990080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06916000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08916100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E910000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C941100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B086F4F }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D080001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D073800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F070140 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09081E93 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01083160 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x030801A6 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11080000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F080000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D095000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F095000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01094000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03095000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05091000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13040154 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09044000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B045000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D049000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F042000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0507E700 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x070700D7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25070000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B070000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1100C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2100C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2300C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2500C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2700C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47003331 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x390018C1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49000333 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D000407 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B001101 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F000120 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D003333 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x410018C6 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43000006 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3B001CC6 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x40800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00000202 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FF3F }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_basic__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__render_basic__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_basic__l3_misses__read; + counter->name = "L3 Misses"; + counter->desc = "The total number of L3 misses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_basic__gti_l3_throughput__read; + counter->name = "GTI L3 Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__render_basic__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_basic__sampler_l1_misses__read; + counter->name = "Sampler Cache Misses"; + counter->desc = "The total number of sampler cache misses in all LODs in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__render_basic__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__render_basic__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 52; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_basic__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_basic__l3_sampler_throughput__read; + counter->name = "L3 Sampler Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_basic__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__render_basic__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 80; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_basic__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_basic__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__render_basic__sampler00_busy__read; + counter->name = "Sampler00 Busy"; + counter->desc = "The percentage of time in which Slice0 Sampler0 has been processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 104; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 8) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__render_basic__sampler10_busy__read; + counter->name = "Sampler10 Busy"; + counter->desc = "The percentage of time in which Slice1 Sampler0 has been processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 108; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 9) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__render_basic__samplers_busy__read; + counter->name = "Samplers Busy"; + counter->desc = "The percentage of time in which samplers have been processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 112; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_basic__gti_vf_throughput__read; + counter->name = "GTI Fixed Pipe Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between 3D Pipeline (Command Dispatch, Input Assembly and Stream Output) and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_basic__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_basic__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_basic__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_basic__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_basic__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cnl__render_basic__avg_gpu_core_frequency__max(brw); + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_basic__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_basic__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_basic__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_basic__l3_lookups__read; + counter->name = "L3 Lookup Accesses w/o IC"; + counter->desc = "The total number of L3 cache lookup accesses w/o IC."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__render_basic__sampler00_bottleneck__read; + counter->name = "Sampler00 Bottleneck"; + counter->desc = "The percentage of time in which Slice0 Sampler0 has been slowing down the pipe when processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_basic__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_basic__gti_read_throughput__read; + counter->name = "GTI Read Throughput"; + counter->desc = "The total number of GPU memory bytes read from GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__render_basic__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 224; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__render_basic__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 228; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_basic__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__render_basic__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 240; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_basic__gti_depth_throughput__read; + counter->name = "GTI Depth Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between depth caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__render_basic__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 256; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__render_basic__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 260; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_basic__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_basic__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__render_basic__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 280; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_basic__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_basic__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 8) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__render_basic__sampler10_bottleneck__read; + counter->name = "Sampler10 Bottleneck"; + counter->desc = "The percentage of time in which Slice1 Sampler0 has been slowing down the pipe when processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 304; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 9) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__render_basic__sampler_bottleneck__read; + counter->name = "Samplers Bottleneck"; + counter->desc = "The percentage of time in which samplers have been slowing down the pipe when processing EU requests."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 308; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_basic__gti_rcc_throughput__read; + counter->name = "GTI RCC Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between render color caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_basic__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_basic__gti_write_throughput__read; + counter->name = "GTI Write Throughput"; + counter->desc = "The total number of GPU memory bytes written to GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 328; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_basic__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 336; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_basic__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 344; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_basic__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 352; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_basic__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 360; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cnl_compute_basic_mux_regs[129]; +static struct brw_perf_query_register_prog cnl_compute_basic_b_counter_regs[5]; +static struct brw_perf_query_register_prog cnl_compute_basic_flex_regs[4]; + +static struct brw_perf_query_counter cnl_compute_basic_query_counters[39]; +static struct brw_perf_query_info cnl_compute_basic_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics Basic Gen10", + .guid = "eed14f91-5f03-4e3a-8281-ac38030ac573", + .counters = cnl_compute_basic_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cnl_compute_basic_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cnl_compute_basic_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cnl_compute_basic_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cnl_register_compute_basic_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cnl_compute_basic_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101A0007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x129A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x109A0007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12BA0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0140 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C0880 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04736000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0673C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00734000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02731000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0474A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E748000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06748000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0475A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E758000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06758000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C762800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10760002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E760002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0077C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E774000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14774000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x167797A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18770002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0277C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04778000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0677C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08778000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A7B0A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C7B0028 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E7C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x147C0C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x167C0038 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C7D2000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E7D0080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0019C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A191800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0219C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0619C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001A2E52 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1A2880 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021A2D80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E39C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A396000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x063A2900 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C3A0051 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CF48000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12F40400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06F42000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08F42000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CF58000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14F50020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06F52000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08F52000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EF62008 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10F60080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CF68000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16F7C070 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18F70001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04F7C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08F7C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AFB8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CFB0200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14FC8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16FC0200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1EFD2008 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A990180 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C99000C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0499C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0899C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x089A2900 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9A0051 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x029A005C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x049A005B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x009A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1AB90600 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CB90030 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0ABA0052 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EBA2880 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00BA0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A590060 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C590003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x085A0052 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5A2880 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D073800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F070140 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D048000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F042000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0507E700 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x070700D7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25070000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B070000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1100C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2100C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2300C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2500C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2700C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2900C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1300C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1500C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1700C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1900C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47001011 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x39000021 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49001330 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D001026 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B001000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F000400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D000001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41000081 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3B001801 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00000008 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_basic__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__compute_basic__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 9) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_basic__untyped_bytes_read__read; + counter->name = "Untyped Bytes Read"; + counter->desc = "The total number of typed memory bytes read via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__compute_basic__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_basic__typed_bytes_written__read; + counter->name = "Typed Bytes Written"; + counter->desc = "The total number of untyped memory bytes written via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__compute_basic__eu_avg_ipc_rate__read; + counter->name = "EU AVG IPC Rate"; + counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 2.0; + counter->offset = 40; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_basic__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_basic__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_basic__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_basic__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__compute_basic__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 80; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__compute_basic__fpu0_active__read; + counter->name = "EU FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 84; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_basic__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_basic__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_basic__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_basic__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_basic__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cnl__compute_basic__avg_gpu_core_frequency__max(brw); + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_basic__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_basic__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_basic__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_basic__gti_read_throughput__read; + counter->name = "GTI Read Throughput"; + counter->desc = "The total number of GPU memory bytes read from GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 9) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_basic__untyped_bytes_written__read; + counter->name = "Untyped Writes"; + counter->desc = "The total number of untyped memory bytes written via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__compute_basic__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_basic__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_basic__typed_bytes_read__read; + counter->name = "Typed Bytes Read"; + counter->desc = "The total number of typed memory bytes read via Data Port."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_basic__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__compute_basic__eu_thread_occupancy__read; + counter->name = "EU Thread Occupancy"; + counter->desc = "The percentage of time in which hardware threads occupied EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__compute_basic__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 204; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_basic__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_basic__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_basic__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_basic__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_basic__gti_write_throughput__read; + counter->name = "GTI Write Throughput"; + counter->desc = "The total number of GPU memory bytes written to GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_basic__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_basic__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_basic__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_basic__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_basic__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__compute_basic__eu_send_active__read; + counter->name = "EU Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 288; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cnl_render_pipe_profile_mux_regs[123]; +static struct brw_perf_query_register_prog cnl_render_pipe_profile_b_counter_regs[5]; +static struct brw_perf_query_register_prog cnl_render_pipe_profile_flex_regs[1]; + +static struct brw_perf_query_counter cnl_render_pipe_profile_query_counters[43]; +static struct brw_perf_query_info cnl_render_pipe_profile_query = { + .kind = OA_COUNTERS, + .name = "Render Metrics for 3D Pipeline Profile Gen10", + .guid = "0666ccac-f5aa-4dc2-aa12-c6e058f383f3", + .counters = cnl_render_pipe_profile_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cnl_render_pipe_profile_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cnl_render_pipe_profile_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cnl_render_pipe_profile_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cnl_register_render_pipe_profile_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cnl_render_pipe_profile_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A7003E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A710000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1017001E }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06700015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00700000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06710800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00710000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C746000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C75A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E754000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E762800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10760002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1477C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16770330 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A190040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08170001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C170000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01160031 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11177C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11187C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05190000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x110E7800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x130F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15120000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11130019 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F160C80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B160000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07162000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03168000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x071705C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x011704C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05170000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B180015 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01185000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07185000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D185000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F185000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03186000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05185000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03190022 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F190000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09190000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D0E8023 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x030E1100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x050E4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D0F0180 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x050F0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x010F0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B100054 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07104000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09104000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B104000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D104000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B114000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D110006 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07118000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09118000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B114000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D114000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05127100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07120073 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21120001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F120000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F130002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01130000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B144000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F144025 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11140025 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D145200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11158000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F158080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13158000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0109A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0709A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B092000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D09A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F09A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0309A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0509A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x010BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x070BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B0B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D0BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F0BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x030BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x050BC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09045000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F045000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11044000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13040154 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B045000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D045000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2100C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2300C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2700C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x19004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47001111 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x39001022 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49001111 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D000021 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B000100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F0018A5 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D001111 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41000001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43000002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3B000401 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_pipe_profile__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__render_pipe_profile__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__render_pipe_profile__vs_bottleneck__read; + counter->name = "VS Bottleneck"; + counter->desc = "The percentage of time in which vertex shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__render_pipe_profile__hi_depth_bottleneck__read; + counter->name = "Hi-Depth Bottleneck"; + counter->desc = "The percentage of time in which early hierarchical depth test pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__render_pipe_profile__gs_bottleneck__read; + counter->name = "GS Bottleneck"; + counter->desc = "The percentage of time in which geometry shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_pipe_profile__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_pipe_profile__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_pipe_profile__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_pipe_profile__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__render_pipe_profile__bc_bottleneck__read; + counter->name = "BC Bottleneck"; + counter->desc = "The percentage of time in which barycentric coordinates calculation pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 56; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__render_pipe_profile__hs_stall__read; + counter->name = "HS Stall"; + counter->desc = "The percentage of time in which hull stall pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 60; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_pipe_profile__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_pipe_profile__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_pipe_profile__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_pipe_profile__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_pipe_profile__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cnl__render_pipe_profile__avg_gpu_core_frequency__max(brw); + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_pipe_profile__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_pipe_profile__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__render_pipe_profile__vf_bottleneck__read; + counter->name = "VF Bottleneck"; + counter->desc = "The percentage of time in which vertex fetch pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 120; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_pipe_profile__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__render_pipe_profile__sf_bottleneck__read; + counter->name = "Strip-Fans Bottleneck"; + counter->desc = "The percentage of time in which strip-fans pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__render_pipe_profile__sf_stall__read; + counter->name = "SF Stall"; + counter->desc = "The percentage of time in which strip-fans pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 140; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__render_pipe_profile__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__render_pipe_profile__hs_bottleneck__read; + counter->name = "HS Bottleneck"; + counter->desc = "The percentage of time in which hull shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__render_pipe_profile__cl_stall__read; + counter->name = "CL Stall"; + counter->desc = "The percentage of time in which clipper pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__render_pipe_profile__so_bottleneck__read; + counter->name = "SO Bottleneck"; + counter->desc = "The percentage of time in which stream output pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_pipe_profile__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_pipe_profile__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_pipe_profile__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__render_pipe_profile__ds_bottleneck__read; + counter->name = "DS Bottleneck"; + counter->desc = "The percentage of time in which domain shader pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 184; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__render_pipe_profile__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 188; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__render_pipe_profile__cl_bottleneck__read; + counter->name = "Clipper Bottleneck"; + counter->desc = "The percentage of time in which clipper pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__render_pipe_profile__ds_stall__read; + counter->name = "DS Stall"; + counter->desc = "The percentage of time in which domain shader pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 196; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__render_pipe_profile__early_depth_bottleneck__read; + counter->name = "Early Depth Bottleneck"; + counter->desc = "The percentage of time in which early depth test pipeline stage was slowing down the 3D pipeline."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_pipe_profile__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_pipe_profile__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_pipe_profile__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_pipe_profile__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_pipe_profile__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_pipe_profile__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_pipe_profile__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__render_pipe_profile__so_stall__read; + counter->name = "SO Stall"; + counter->desc = "The percentage of time in which stream-output pipeline stage was stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 264; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__render_pipe_profile__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cnl_memory_reads_mux_regs[56]; +static struct brw_perf_query_register_prog cnl_memory_reads_b_counter_regs[26]; +static struct brw_perf_query_register_prog cnl_memory_reads_flex_regs[1]; + +static struct brw_perf_query_counter cnl_memory_reads_query_counters[40]; +static struct brw_perf_query_info cnl_memory_reads_query = { + .kind = OA_COUNTERS, + .name = "Memory Reads Distribution Gen10", + .guid = "3500dcfd-837b-4ec8-b5cf-fe58b966263f", + .counters = cnl_memory_reads_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cnl_memory_reads_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cnl_memory_reads_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cnl_memory_reads_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cnl_register_memory_reads_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cnl_memory_reads_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17066860 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15070017 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F072920 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B038000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D038000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F034000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F063180 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01063100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0306006B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05060000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11080100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D085000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F094000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01094000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03091000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09046000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F04A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1104A800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x130401AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B041000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x010700E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0707E153 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0907E3E2 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B07E5E4 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D07E7E6 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F0700EF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25070000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11070000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23070000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D070000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x39000003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D000C63 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F000C63 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41000C63 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43000000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0000081A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x0000082A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000872 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x000008BA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x0000087A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x000008EA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x000008E2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x000008F2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x00006667 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002748, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x86543210 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002754, .val = 0x00000065 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_reads__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__memory_reads__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_reads__gti_l3_bank0_reads__read; + counter->name = "GtiL3Bank0Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 0 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_reads__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_reads__gti_ring_accesses__read; + counter->name = "GtiRingAccesses"; + counter->desc = "The total number of all accesses from GTI to the ring."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_reads__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_reads__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_reads__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_reads__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_reads__gti_rs_memory_reads__read; + counter->name = "GtiRsMemoryReads"; + counter->desc = "The total number of GTI memory reads from Resource Streamer."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_reads__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_reads__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_reads__gti_hiz_memory_reads__read; + counter->name = "GtiHizMemoryReads"; + counter->desc = "The total number of GTI memory reads from Hierarchical Depth Cache (Hi-Depth Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_reads__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_reads__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cnl__memory_reads__avg_gpu_core_frequency__max(brw); + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_reads__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_reads__gti_rcc_memory_reads__read; + counter->name = "GtiRccMemoryReads"; + counter->desc = "The total number of GTI memory reads from Render Color Cache (Render Color Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_reads__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_reads__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_reads__gti_l3_bank1_reads__read; + counter->name = "GtiL3Bank1Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 1 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__memory_reads__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_reads__gti_cmd_streamer_memory_reads__read; + counter->name = "GtiCmdStreamerMemoryReads"; + counter->desc = "The total number of GTI memory reads from Command Streamer."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_reads__gti_l3_bank2_reads__read; + counter->name = "GtiL3Bank2Reads"; + counter->desc = "The total number of GTI memory reads from L3 Bank 2 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_reads__gti_memory_reads__read; + counter->name = "GtiMemoryReads"; + counter->desc = "The total number of GTI memory reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_reads__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_reads__gti_rcz_memory_reads__read; + counter->name = "GtiRczMemoryReads"; + counter->desc = "The total number of GTI memory reads from Render Depth Cache (Render Depth Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_reads__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_reads__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__memory_reads__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 224; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_reads__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_reads__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_reads__gti_msc_memory_reads__read; + counter->name = "GtiMscMemoryReads"; + counter->desc = "The total number of GTI memory reads from Multisampling Color Cache (Multisampling Color Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_reads__gti_vf_memory_reads__read; + counter->name = "GtiVfMemoryReads"; + counter->desc = "The total number of GTI memory reads from Vertex Fetch."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_reads__gti_stc_memory_reads__read; + counter->name = "GtiStcMemoryReads"; + counter->desc = "The total number of GTI memory reads from Stencil Cache (Stencil Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_reads__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_reads__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_reads__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_reads__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_reads__gti_l3_reads__read; + counter->name = "GtiL3Reads"; + counter->desc = "The total number of GTI memory reads from L3 (L3 Cache misses)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_reads__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cnl_memory_writes_mux_regs[56]; +static struct brw_perf_query_register_prog cnl_memory_writes_b_counter_regs[24]; +static struct brw_perf_query_register_prog cnl_memory_writes_flex_regs[1]; + +static struct brw_perf_query_counter cnl_memory_writes_query_counters[40]; +static struct brw_perf_query_info cnl_memory_writes_query = { + .kind = OA_COUNTERS, + .name = "Memory Writes Distribution Gen10", + .guid = "63d18ead-3cfc-4972-a640-5e98b688dfee", + .counters = cnl_memory_writes_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cnl_memory_writes_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cnl_memory_writes_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cnl_memory_writes_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cnl_register_memory_writes_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cnl_memory_writes_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17066860 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15070017 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D073C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F07000E }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B038000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D038000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F034000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F063180 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01063100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0306006B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05060000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11080100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D085000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F094000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01094000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03091000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09046000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F04A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1104A800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x130401AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B041000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x010700D0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0707D153 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0907D3D2 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B07D5D4 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D07D7D6 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F0700DF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25070000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11070000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23070000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x23004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x29004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x39000003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D000C63 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F000C63 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41000C63 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43000000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x70800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x0000081A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000822 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x000008BA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x0000087A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x000008EA }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x000008E2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x000008F2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000274C, .val = 0x65432108 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002744, .val = 0x0000CCCE }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002748, .val = 0x65432108 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000275C, .val = 0x65432108 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002754, .val = 0x000000CA }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_writes__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__memory_writes__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_writes__gti_memory_writes__read; + counter->name = "GtiMemoryWrites"; + counter->desc = "The total number of GTI memory writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_writes__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_writes__gti_ring_accesses__read; + counter->name = "GtiRingAccesses"; + counter->desc = "The total number of all accesses from GTI to the ring."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_writes__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_writes__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_writes__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_writes__gti_msc_memory_writes__read; + counter->name = "GtiMscMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Multisampling Color Cache (Multisampling Color Cache invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_writes__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_writes__gti_cmd_streamer_memory_writes__read; + counter->name = "GtiCmdStreamerMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Command Streamer."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_writes__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_writes__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_writes__gti_l3_bank0_writes__read; + counter->name = "GtiL3Bank0Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 0 (L3 Bank 0 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_writes__gti_l3_bank1_writes__read; + counter->name = "GtiL3Bank1Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 1 (L3 Bank 1 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_writes__gti_l3_bank2_writes__read; + counter->name = "GtiL3Bank2Writes"; + counter->desc = "The total number of GTI memory writes from L3 Bank 2 (L3 Bank 2 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_writes__gti_l3_writes__read; + counter->name = "GtiL3Writes"; + counter->desc = "The total number of GTI memory writes from L3 (L3 invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_writes__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_writes__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cnl__memory_writes__avg_gpu_core_frequency__max(brw); + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_writes__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_writes__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_writes__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_writes__gti_rcc_memory_writes__read; + counter->name = "GtiRccMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Render Color Cache (Render Color Cache invalidations)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_writes__gti_so_memory_writes__read; + counter->name = "GtiSoMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Stream Output."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__memory_writes__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_writes__gti_stc_memory_writes__read; + counter->name = "GtiStcMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Stencil Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_writes__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_writes__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_writes__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__memory_writes__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 232; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_writes__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_writes__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_writes__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_writes__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_writes__gti_rcz_memory_writes__read; + counter->name = "GtiRczMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Render Depth Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_writes__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_writes__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_writes__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_writes__gti_hiz_memory_writes__read; + counter->name = "GtiHizMemoryWrites"; + counter->desc = "The total number of GTI memory writes from Hierarchical Depth Cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__memory_writes__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cnl_compute_extended_mux_regs[80]; +static struct brw_perf_query_register_prog cnl_compute_extended_b_counter_regs[21]; +static struct brw_perf_query_register_prog cnl_compute_extended_flex_regs[4]; + +static struct brw_perf_query_counter cnl_compute_extended_query_counters[38]; +static struct brw_perf_query_info cnl_compute_extended_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics Extended Gen10", + .guid = "1b4d1280-6bbd-4d57-90c6-a03ed6059688", + .counters = cnl_compute_extended_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cnl_compute_extended_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cnl_compute_extended_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cnl_compute_extended_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cnl_register_compute_extended_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cnl_compute_extended_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + if (brw->perfquery.sys_vars.subslice_mask & 1) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121A0007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121B000B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x161B0009 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0474A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A748000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C74A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E74A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12741540 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0674A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08742000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0475A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A758000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C75A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E75A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x147500AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0675A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08752000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C76A800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E76AA0A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x107602AA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0077C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E77C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1477C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1677FFF0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18770003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0277C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0477C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0677C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0877C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00198000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E198000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A195540 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C19003A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0219C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0419C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0619C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0819C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1A2A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001A2980 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x021A2CDA }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x041A0058 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001B0011 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x061B0900 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081B0A13 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1B0B15 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C1B2317 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E1B0043 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x101B0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10178000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C1701FE }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1100C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2100C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2300C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2500C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2700C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2900C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1300C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1500C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1700C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1900C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x39000420 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43000001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3B000021 }; + } + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000C2A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000C6A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000C32 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000E6A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000E7A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000C92 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x00000CA2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FE00 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00000C9A }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FE00 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00000008 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_extended__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__compute_extended__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__compute_extended__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__compute_extended__eu_avg_ipc_rate__read; + counter->name = "EU AVG IPC Rate"; + counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 2.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_extended__typed_writes0__read; + counter->name = "Typed Writes 0"; + counter->desc = "The subslice 0 typed writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_extended__eu_typed_atomics0__read; + counter->name = "EuTypedAtomics0"; + counter->desc = "The subslice 0 EU Typed Atomics subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_extended__typed_atomics0__read; + counter->name = "Typed Atomics 0"; + counter->desc = "The subslice 0 typed atomics."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__compute_extended__typed_atomics_per_cache_line__read; + counter->name = "TypedAtomicsPerCacheLine"; + counter->desc = "The ratio of EU typed atomics requests to L3 cache line writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_extended__eu_untyped_reads0__read; + counter->name = "EuUntypedReads0"; + counter->desc = "The subslice 0 EU Untyped Reads subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_extended__untyped_writes0__read; + counter->name = "Untyped Writes 0"; + counter->desc = "The subslice 0 untyped writes (including SLM writes)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__compute_extended__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 72; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__compute_extended__fpu0_active__read; + counter->name = "EU FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 76; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_extended__eu_untyped_atomics0__read; + counter->name = "EuUntypedAtomics0"; + counter->desc = "The subslice 0 EU Untyped Atomics subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_extended__eu_untyped_writes0__read; + counter->name = "EuUntypedWrites0"; + counter->desc = "The subslice 0 EU Untyped Writes subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_extended__eu_a64_untyped_writes0__read; + counter->name = "EuA64UntypedWrites0"; + counter->desc = "The subslice 0 EU A64 Untyped Writes subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__compute_extended__untyped_writes_per_cache_line__read; + counter->name = "UntypedWritesPerCacheLine"; + counter->desc = "The ratio of EU untyped write requests to L3 cache line writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_extended__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_extended__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_extended__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_extended__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cnl__compute_extended__avg_gpu_core_frequency__max(brw); + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_extended__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_extended__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_extended__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_extended__eu_typed_writes0__read; + counter->name = "EuTypedWrites0"; + counter->desc = "The subslice 0 EU Typed Writes subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__compute_extended__typed_writes_per_cache_line__read; + counter->name = "TypedWritesPerCacheLine"; + counter->desc = "The ratio of EU typed write requests to L3 cache line writes."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_extended__typed_reads0__read; + counter->name = "Typed Reads 0"; + counter->desc = "The subslice 0 typed reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_extended__untyped_reads0__read; + counter->name = "Untyped Reads 0"; + counter->desc = "The subslice 0 untyped reads (including SLM reads)."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_extended__eu_a64_untyped_reads0__read; + counter->name = "EuA64UntypedReads0"; + counter->desc = "The subslice 0 EU A64 Untyped Reads subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__compute_extended__eu_thread_occupancy__read; + counter->name = "EU Thread Occupancy"; + counter->desc = "The percentage of time in which hardware threads occupied EUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 208; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__compute_extended__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 212; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_extended__eu_typed_reads0__read; + counter->name = "EuTypedReads0"; + counter->desc = "The subslice 0 EU Typed Reads subslice 0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__compute_extended__untyped_reads_per_cache_line__read; + counter->name = "UntypedReadsPerCacheLine"; + counter->desc = "The ratio of EU untyped read requests to L3 cache line reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_extended__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__compute_extended__typed_reads_per_cache_line__read; + counter->name = "TypedReadsPerCacheLine"; + counter->desc = "The ratio of EU typed read requests to L3 cache line reads."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_extended__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_extended__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_extended__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__compute_extended__eu_send_active__read; + counter->name = "EU Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 272; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cnl_compute_l3_cache_mux_regs[67]; +static struct brw_perf_query_register_prog cnl_compute_l3_cache_b_counter_regs[5]; +static struct brw_perf_query_register_prog cnl_compute_l3_cache_flex_regs[7]; + +static struct brw_perf_query_counter cnl_compute_l3_cache_query_counters[55]; +static struct brw_perf_query_info cnl_compute_l3_cache_query = { + .kind = OA_COUNTERS, + .name = "Compute Metrics L3 Cache Gen10", + .guid = "f3b31b5a-00b3-4fb4-81fd-6446e505534c", + .counters = cnl_compute_l3_cache_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cnl_compute_l3_cache_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cnl_compute_l3_cache_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cnl_compute_l3_cache_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cnl_register_compute_l3_cache_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cnl_compute_l3_cache_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x146C0080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14EC0080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0050 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C5100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C0052 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x026C5C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C0800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0540 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00739000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02739000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0473F000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00778000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E778000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14778000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x167702A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06778000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08778000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08EC5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AEC5251 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04EC005C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10EC0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1AEC0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18EC0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04F3E000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02F31000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16F702A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08F78000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B080360 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D073800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F070140 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01081060 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D080000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01094000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x03091000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09044000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B041000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0D048000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F042000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0507E700 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x070700D7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x25070000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B070000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1100C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2100C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2300C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2500C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2700C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x15004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1700C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1900C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47001111 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x39002101 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49001110 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D000429 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B000001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3B002401 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00000003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00002001 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E758, .val = 0x00101100 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00201200 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00301300 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E65C, .val = 0x00401400 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__compute_l3_cache__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__l3_misses__read; + counter->name = "L3 Misses"; + counter->desc = "The total number of L3 misses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__gti_l3_throughput__read; + counter->name = "GTI L3 Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between L3 caches and GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 24; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__l3_bank00_accesses__read; + counter->name = "Slice0 L3 Bank0 Accesses"; + counter->desc = "The total number of accesses to Slice0 L3 Bank0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + } + + if (brw->perfquery.sys_vars.slice_mask & 1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__l3_bank01_accesses__read; + counter->name = "Slice0 L3 Bank1 Accesses"; + counter->desc = "The total number of accesses to Slice0 L3 Bank1."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + } + + if (brw->perfquery.sys_vars.slice_mask & 1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__l3_bank02_accesses__read; + counter->name = "Slice0 L3 Bank2 Accesses"; + counter->desc = "The total number of accesses to Slice0 L3 Bank2."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + } + + if (brw->perfquery.sys_vars.slice_mask & 2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__l3_bank10_accesses__read; + counter->name = "Slice1 L3 Bank0 Accesses"; + counter->desc = "The total number of accesses to Slice1 L3 Bank0."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + } + + if (brw->perfquery.sys_vars.slice_mask & 2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__l3_bank11_accesses__read; + counter->name = "Slice1 L3 Bank1 Accesses"; + counter->desc = "The total number of accesses to Slice1 L3 Bank1."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + } + + if (brw->perfquery.sys_vars.slice_mask & 2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__l3_bank12_accesses__read; + counter->name = "Slice1 L3 Bank2 Accesses"; + counter->desc = "The total number of accesses to Slice1 L3 Bank2."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__l3_accesses__read; + counter->name = "L3 Accesses"; + counter->desc = "The total number of L3 accesses from all entities."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__compute_l3_cache__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 88; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__l3_sampler_throughput__read; + counter->name = "L3 Sampler Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between samplers and L3 caches."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__compute_l3_cache__eu_avg_ipc_rate__read; + counter->name = "EU AVG IPC Rate"; + counter->desc = "The average rate of IPC calculated for 2 FPU pipelines."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 2.0; + counter->offset = 104; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__compute_l3_cache__eu_binary_fpu0_instruction__read; + counter->name = "EU FPU0 Binary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 108; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__compute_l3_cache__eu_hybrid_fpu0_instruction__read; + counter->name = "EU FPU0 Hybrid Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__compute_l3_cache__fpu1_active__read; + counter->name = "EU FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__compute_l3_cache__fpu0_active__read; + counter->name = "EU FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__compute_l3_cache__eu_move_fpu0_instruction__read; + counter->name = "EU FPU0 Move Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__sampler_accesses__read; + counter->name = "Sampler Accesses"; + counter->desc = "The total number of messages send to samplers."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__compute_l3_cache__eu_hybrid_fpu1_instruction__read; + counter->name = "EU FPU1 Hybrid Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing hybrid instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cnl__compute_l3_cache__avg_gpu_core_frequency__max(brw); + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__l3_lookups__read; + counter->name = "L3 Lookup Accesses w/o IC"; + counter->desc = "The total number of L3 cache lookup accesses w/o IC."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__gti_read_throughput__read; + counter->name = "GTI Read Throughput"; + counter->desc = "The total number of GPU memory bytes read from GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__compute_l3_cache__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 264; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__compute_l3_cache__eu_ternary_fpu0_instruction__read; + counter->name = "EU FPU0 Ternary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU0."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 268; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__compute_l3_cache__eu_move_fpu1_instruction__read; + counter->name = "EU FPU1 Move Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing move instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 304; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__compute_l3_cache__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 308; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 320; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 328; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 336; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__l3_total_throughput__read; + counter->name = "L3 Total Throughput"; + counter->desc = "The total number of GPU memory bytes transferred via L3."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 344; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__gti_write_throughput__read; + counter->name = "GTI Write Throughput"; + counter->desc = "The total number of GPU memory bytes written to GTI."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 352; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 360; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 368; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__compute_l3_cache__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 376; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__compute_l3_cache__eu_binary_fpu1_instruction__read; + counter->name = "EU FPU1 Binary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing binary instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 384; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__compute_l3_cache__eu_ternary_fpu1_instruction__read; + counter->name = "EU FPU1 Ternary Instruction"; + counter->desc = "The percentage of time in which execution units were actively processing ternary instructions on FPU1."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 388; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__compute_l3_cache__eu_send_active__read; + counter->name = "EU Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 392; + counter->size = sizeof(float); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cnl_hdc_and_sf_mux_regs[87]; +static struct brw_perf_query_register_prog cnl_hdc_and_sf_b_counter_regs[7]; +static struct brw_perf_query_register_prog cnl_hdc_and_sf_flex_regs[5]; + +static struct brw_perf_query_counter cnl_hdc_and_sf_query_counters[42]; +static struct brw_perf_query_info cnl_hdc_and_sf_query = { + .kind = OA_COUNTERS, + .name = "Metric set HDCAndSF", + .guid = "890094c5-8615-4f69-a8b9-706c5bcbd713", + .counters = cnl_hdc_and_sf_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cnl_hdc_and_sf_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cnl_hdc_and_sf_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cnl_hdc_and_sf_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cnl_register_hdc_and_sf_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cnl_hdc_and_sf_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x121A0011 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x123A0011 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x129A0011 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12BA0011 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x125A0011 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C00A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0673C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00736000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C74A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C75A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E762800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1477C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16779570 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18770002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02778000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04778000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A7B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C7B002A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x147C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x167C003E }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E7D0028 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A1901E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x081A2B50 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x001A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A391E00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A3A2B50 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x003A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12F41400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14F500A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10F60280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16F7C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18F70003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02F74000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04F74000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08FBA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02FC8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04FC8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CFD000A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C99003C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E9A2B50 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x009A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B9C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B9C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00BA2800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02BA0056 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A596000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C590003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C5A2B50 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x005A0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x130E03C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2100F000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01181000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x010E0030 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x110E0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01104000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01118000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0B142000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x01092000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x010B4000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x09041000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D000071 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x11004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2300C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2500C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2700C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2900C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1300C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1500C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47000003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x39000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B001111 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D000408 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F000421 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41000084 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49000300 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x10800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFFE }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__hdc_and_sf__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__hdc_and_sf__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__hdc_and_sf__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__hdc_and_sf__gt_request_queue_full__read; + counter->name = "SQ is full"; + counter->desc = "The percentage of time when SQ is filled above a threshold (usually 48 entries)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__hdc_and_sf__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__hdc_and_sf__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__hdc_and_sf__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__hdc_and_sf__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__hdc_and_sf__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__hdc_and_sf__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__hdc_and_sf__poly_data_ready__read; + counter->name = "Polygon Data Ready"; + counter->desc = "The percentage of time in which geometry pipeline output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__hdc_and_sf__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__hdc_and_sf__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__hdc_and_sf__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__hdc_and_sf__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__hdc_and_sf__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__hdc_and_sf__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cnl__hdc_and_sf__avg_gpu_core_frequency__max(brw); + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__hdc_and_sf__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__hdc_and_sf__non_sampler_shader01_access_stalled_on_l3__read; + counter->name = "Slice0 Subslice1 Non-sampler Shader Access Stalled On L3"; + counter->desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Subslice1)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 128; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__hdc_and_sf__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__hdc_and_sf__non_sampler_shader02_access_stalled_on_l3__read; + counter->name = "Slice0 Subslice2 Non-sampler Shader Access Stalled On L3"; + counter->desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Subslice2)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__hdc_and_sf__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__hdc_and_sf__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__hdc_and_sf__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 164; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__hdc_and_sf__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__hdc_and_sf__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 172; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 8) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__hdc_and_sf__non_sampler_shader10_access_stalled_on_l3__read; + counter->name = "Slice1 Subslice0 Non-sampler Shader Access Stalled On L3"; + counter->desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice1 Subslice0)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__hdc_and_sf__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__hdc_and_sf__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__hdc_and_sf__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__hdc_and_sf__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__hdc_and_sf__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 216; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__hdc_and_sf__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__hdc_and_sf__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__hdc_and_sf__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__hdc_and_sf__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 16) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__hdc_and_sf__non_sampler_shader11_access_stalled_on_l3__read; + counter->name = "Slice1 Subslice1 Non-sampler Shader Access Stalled On L3"; + counter->desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice1 Subslice1)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 256; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__hdc_and_sf__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__hdc_and_sf__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__hdc_and_sf__non_sampler_shader00_access_stalled_on_l3__read; + counter->name = "Slice0 Subslice0 Non-sampler Shader Access Stalled On L3"; + counter->desc = "Percentage of time when HDC has messages to L3, but it's stalled due to lack of credits (Slice0 Subslice0)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 280; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__hdc_and_sf__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__hdc_and_sf__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cnl_l3_1_mux_regs[81]; +static struct brw_perf_query_register_prog cnl_l3_1_b_counter_regs[11]; +static struct brw_perf_query_register_prog cnl_l3_1_flex_regs[5]; + +static struct brw_perf_query_counter cnl_l3_1_query_counters[42]; +static struct brw_perf_query_info cnl_l3_1_query = { + .kind = OA_COUNTERS, + .name = "Metric set L3_1", + .guid = "e56f7dd7-ff55-4bae-89a1-a526a2e3b0d6", + .counters = cnl_l3_1_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cnl_l3_1_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cnl_l3_1_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cnl_l3_1_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cnl_register_l3_1_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cnl_l3_1_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1661001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1665001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1669001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C1C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x126C0004 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C001D }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10EC0400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16EC0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02610024 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10610000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E610000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02652400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10650000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E650000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04690024 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10690000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E690000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C0020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x066C2800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A6C2820 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E6C3832 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C05A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C1010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186D8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A6E1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0073F000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02738000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0473D000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0673D000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00778000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E778000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14778000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16778A80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18770002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02778000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04778000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06778000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08774000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04784000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A7B0004 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08EC0020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CEC0020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00EC3600 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1AEC0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18EC0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04F31000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06F31000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00F32000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14F78000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16F70800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02F78000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2100F000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D000071 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1100C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2500C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2700C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2900C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1300C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1500C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1700C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1900C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47000101 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x39000001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49001300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D000021 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B001100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F000420 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D001100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41000400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43000001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3B0000C7 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x70800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x20000801 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0111FEEE }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x40001001 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0222FDDD }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x80002002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0444FBBB }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_1__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__l3_1__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__l3_1__l30_bank1_active__read; + counter->name = "Slice0 L3 Bank1 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank1 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__l3_1__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__l3_1__gt_request_queue_full__read; + counter->name = "SQ is full"; + counter->desc = "The percentage of time when SQ is filled above a threshold (usually 48 entries)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__l3_1__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__l3_1__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 28; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_1__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_1__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__l3_1__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_1__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__l3_1__l30_bank1_stalled__read; + counter->name = "Slice0 L3 Bank1 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank1 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_1__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_1__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_1__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_1__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_1__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_1__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cnl__l3_1__avg_gpu_core_frequency__max(brw); + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_1__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_1__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_1__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__l3_1__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__l3_1__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__l3_1__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__l3_1__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__l3_1__l30_bank2_active__read; + counter->name = "Slice0 L3 Bank2 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank2 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.slice_mask & 1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__l3_1__l30_bank0_active__read; + counter->name = "Slice0 L3 Bank0 Active"; + counter->desc = "The percentage of time in which slice0 L3 bank0 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 164; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_1__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__l3_1__l31_bank2_stalled__read; + counter->name = "Slice1 L3 Bank2 Stalled"; + counter->desc = "The percentage of time in which slice1 L3 bank2 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__l3_1__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 180; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__l3_1__l30_bank0_stalled__read; + counter->name = "Slice0 L3 Bank0 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank0 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 184; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_1__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_1__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__l3_1__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 208; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_1__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_1__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_1__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_1__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_1__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_1__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_1__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_1__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cnl_l3_2_mux_regs[87]; +static struct brw_perf_query_register_prog cnl_l3_2_b_counter_regs[11]; +static struct brw_perf_query_register_prog cnl_l3_2_flex_regs[5]; + +static struct brw_perf_query_counter cnl_l3_2_query_counters[42]; +static struct brw_perf_query_info cnl_l3_2_query = { + .kind = OA_COUNTERS, + .name = "Metric set L3_2", + .guid = "918834e2-a1a4-4d77-9f3a-0c229f8d803f", + .counters = cnl_l3_2_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cnl_l3_2_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cnl_l3_2_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cnl_l3_2_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cnl_register_l3_2_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cnl_l3_2_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x106C0400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x166C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16E1001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16E5001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16E9001A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10EC1C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12EC0004 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16EC001D }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x086C0020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C6C0020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x006C3600 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C0A88 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0504 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0073F000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02739000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0473D000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0673D000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00778000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E778000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14778000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16778A80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18770002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02778000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04778000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06778000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08778000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02E10024 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10E10000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1EE10000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02E52400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10E50000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1EE50000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04E90024 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10E90000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1EE90000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00EC0020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06EC2800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AEC2820 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EEC3832 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18EC0580 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1AEC0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CEC0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18ED8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AEE1000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00F3D000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02F38000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04F3C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06F3C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00F78000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EF78000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16F78280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18F70002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04F78000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06F78000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08F74000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04F84000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AFB0004 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2100F000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D000071 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1100C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2500C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2700C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2900C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1300C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1500C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1700C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1900C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47000010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x39000883 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49000300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D001064 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B000001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F000C60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D000001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41000C04 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43000003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3B000001 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x70800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x20000801 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0111FEEE }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x40001001 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0222FDDD }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x80002002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0444FBBB }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_2__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__l3_2__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__l3_2__l31_bank1_stalled__read; + counter->name = "Slice1 L3 Bank1 Stalled"; + counter->desc = "The percentage of time in which slice1 L3 bank1 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__l3_2__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__l3_2__gt_request_queue_full__read; + counter->name = "SQ is full"; + counter->desc = "The percentage of time when SQ is filled above a threshold (usually 48 entries)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__l3_2__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__l3_2__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 28; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_2__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_2__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__l3_2__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_2__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_2__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_2__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__l3_2__l31_bank0_stalled__read; + counter->name = "Slice1 L3 Bank0 Stalled"; + counter->desc = "The percentage of time in which slice1 L3 bank0 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 80; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_2__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_2__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_2__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_2__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cnl__l3_2__avg_gpu_core_frequency__max(brw); + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_2__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_2__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_2__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__l3_2__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__l3_2__l30_bank2_stalled__read; + counter->name = "Slice0 L3 Bank2 Stalled"; + counter->desc = "The percentage of time in which slice0 L3 bank2 is stalled"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 148; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__l3_2__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__l3_2__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__l3_2__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__l3_2__l31_bank2_active__read; + counter->name = "Slice1 L3 Bank2 Active"; + counter->desc = "The percentage of time in which slice1 L3 bank2 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 164; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_2__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 168; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__l3_2__l31_bank1_active__read; + counter->name = "Slice1 L3 Bank1 Active"; + counter->desc = "The percentage of time in which slice1 L3 bank1 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__l3_2__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 180; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_2__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_2__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__l3_2__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__l3_2__l31_bank0_active__read; + counter->name = "Slice1 L3 Bank0 Active"; + counter->desc = "The percentage of time in which slice1 L3 bank0 is active"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 204; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_2__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_2__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_2__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_2__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_2__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_2__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_2__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__l3_2__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cnl_rasterizer_and_pixel_backend_mux_regs[93]; +static struct brw_perf_query_register_prog cnl_rasterizer_and_pixel_backend_b_counter_regs[13]; +static struct brw_perf_query_register_prog cnl_rasterizer_and_pixel_backend_flex_regs[5]; + +static struct brw_perf_query_counter cnl_rasterizer_and_pixel_backend_query_counters[46]; +static struct brw_perf_query_info cnl_rasterizer_and_pixel_backend_query = { + .kind = OA_COUNTERS, + .name = "Metric set RasterizerAndPixelBackend", + .guid = "2e95713a-c6d8-47a9-9207-eba3e208be51", + .counters = cnl_rasterizer_and_pixel_backend_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cnl_rasterizer_and_pixel_backend_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cnl_rasterizer_and_pixel_backend_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cnl_rasterizer_and_pixel_backend_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cnl_register_rasterizer_and_pixel_backend_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cnl_rasterizer_and_pixel_backend_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C710004 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10747000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12756800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04795000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x127C01C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CF10004 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10F47000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12F56800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04F95000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12FC01C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C4044 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0004 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C00A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00710010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02738000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04732000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0673A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00736000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08740037 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C740000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A750F36 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10750000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04751000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C752000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E750000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C760800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E768800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10760002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0077C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E778000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1477C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x167767E0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18770002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02778000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04778000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C790017 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08790000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C7B0088 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E7C0032 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x107C0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x167C0004 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04F10200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00F10000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08F40DC0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CF40000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00F50D80 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02F5003C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10F50000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AF54000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CF58000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04F50000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06F50000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EF62200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CF6A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EF7C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16F71030 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18F70001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02F7C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04F7C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CF905C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08F90000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CFB0220 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EFC1900 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10FC0000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16FC0010 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2100F000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D000071 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1100C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2300C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2500C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2700C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2900C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1300C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1500C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47000001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x39000421 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49000300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D000402 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B001101 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F000840 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D000101 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41000801 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43000001 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x30800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000180 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFCF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00006000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000F3FF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFFE }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00000002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFFD }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__rasterizer1_input_available__read; + counter->name = "Slice1 Rasterizer Input Available"; + counter->desc = "The percentage of time in which slice1 rasterizer input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__pixel_values0_ready__read; + counter->name = "Slice0 Pixel Values Ready"; + counter->desc = "The percentage of time in which slice0 pixel values are ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 72; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cnl__rasterizer_and_pixel_backend__avg_gpu_core_frequency__max(brw); + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__rasterizer0_input_available__read; + counter->name = "Slice0 Rasterizer Input Available"; + counter->desc = "The percentage of time in which slice0 rasterizer input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__pixel_data0_ready__read; + counter->name = "Slice0 Post-EarlyZ Pixel Data Ready"; + counter->desc = "The percentage of time in which slice0 post-EarlyZ pixel data is ready (after early Z tests have been applied)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 140; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 164; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__pixel_values1_ready__read; + counter->name = "Slice1 Pixel Values Ready"; + counter->desc = "The percentage of time in which slice1 pixel values are ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.slice_mask & 2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__ps_output1_available__read; + counter->name = "Slice1 PS Output Available"; + counter->desc = "The percentage of time in which slice1 PS output is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 172; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 176; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 184; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 208; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.slice_mask & 1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__rasterizer0_output_ready__read; + counter->name = "Slice0 Rasterizer Output Ready"; + counter->desc = "The percentage of time in which slice0 rasterizer output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 212; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__rasterizer1_output_ready__read; + counter->name = "Slice1 Rasterizer Output Ready"; + counter->desc = "The percentage of time in which slice1 rasterizer output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 232; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__pixel_data1_ready__read; + counter->name = "Slice1 Post-EarlyZ Pixel Data Ready"; + counter->desc = "The percentage of time in which slice1 post-EarlyZ pixel data is ready (after early Z tests have been applied)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 236; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__gt_request_queue_full__read; + counter->name = "SQ is full"; + counter->desc = "The percentage of time when SQ is filled above a threshold (usually 48 entries)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 248; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.slice_mask & 1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__rasterizer_and_pixel_backend__ps_output0_available__read; + counter->name = "Slice0 PS Output Available"; + counter->desc = "The percentage of time in which slice0 PS output is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 288; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__rasterizer_and_pixel_backend__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cnl_sampler_mux_regs[144]; +static struct brw_perf_query_register_prog cnl_sampler_b_counter_regs[15]; +static struct brw_perf_query_register_prog cnl_sampler_flex_regs[5]; + +static struct brw_perf_query_counter cnl_sampler_query_counters[46]; +static struct brw_perf_query_info cnl_sampler_query = { + .kind = OA_COUNTERS, + .name = "Metric set Sampler", + .guid = "9bcf4ff2-c15f-4bea-8ec8-8db87791942e", + .counters = cnl_sampler_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cnl_sampler_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cnl_sampler_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cnl_sampler_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cnl_register_sampler_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cnl_sampler_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14141400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1614000B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14161400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14341400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1634000B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14361400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14941400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1694000B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14961400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14B41400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16B4000B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14B61400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14541400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1654000B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14561400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C0280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0673F000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0073C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04742000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A74A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04752000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A75A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C760800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E760280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0077C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E77C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14774000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1677A950 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18770002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04778000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06778000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08774000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A774000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C77C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A7BA828 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C7B0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x147CE800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x167C0003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x087CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A7C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C7D8200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E7D0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00194000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E194000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C194000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00140050 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06145800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10140000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18140000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C140080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A150001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06160043 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10160000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C160000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A3900A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A394000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08345850 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10340000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C340020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08358000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04362180 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10360000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A360000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12F40140 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06F48000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14F5000A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06F58000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10F60028 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EF60002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16F77C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18F70001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04F74000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06F7C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CFB0280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08FB8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16FC0280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04FC8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1EFD2800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CFD0008 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A992000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C990001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06994000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C945850 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10940000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E940000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C940002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08952000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02962180 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10960000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06960000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CB90014 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B94000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB45850 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B40000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1EB40000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1AB48000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B51000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02B60043 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B60000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B60000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A590A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08594000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A545850 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10540000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C540008 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E540000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08554000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04560043 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10560000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08560000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2100F000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13000071 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1100C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2300C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2500C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2700C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2900C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1500C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1700C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1900C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47000031 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x39000143 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49001110 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D000C61 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B000011 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F0018C3 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41000842 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43000002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3B000480 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x10800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000018 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFFC }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000060 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FFF3 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000180 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FFCF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000600 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FF3F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00001800 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FCFF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__sampler__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__sampler__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__sampler__sampler02_input_available__read; + counter->name = "Slice0 Subslice2 Input Available"; + counter->desc = "The percentage of time in which slice0 subslice2 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__sampler__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__sampler__gt_request_queue_full__read; + counter->name = "SQ is full"; + counter->desc = "The percentage of time when SQ is filled above a threshold (usually 48 entries)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__sampler__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__sampler__sampler00_input_available__read; + counter->name = "Slice0 Subslice0 Input Available"; + counter->desc = "The percentage of time in which slice0 subslice0 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 28; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__sampler__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 32; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__sampler__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 8) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__sampler__sampler10_input_available__read; + counter->name = "Slice1 Subslice0 Input Available"; + counter->desc = "The percentage of time in which slice1 subslice0 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__sampler__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__sampler__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__sampler__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__sampler__sampler02_output_ready__read; + counter->name = "Slice0 Subslice2 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice0 subslice2 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 80; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__sampler__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__sampler__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__sampler__sampler01_input_available__read; + counter->name = "Slice0 Subslice1 Input Available"; + counter->desc = "The percentage of time in which slice0 subslice1 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 104; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__sampler__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__sampler__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__sampler__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__sampler__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cnl__sampler__avg_gpu_core_frequency__max(brw); + counter->offset = 136; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__sampler__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__sampler__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__sampler__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__sampler__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__sampler__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 172; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__sampler__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__sampler__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 180; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 16) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__sampler__sampler11_input_available__read; + counter->name = "Slice1 Subslice1 Input Available"; + counter->desc = "The percentage of time in which slice1 subslice1 sampler input is available"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 184; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__sampler__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__sampler__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__sampler__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__sampler__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__sampler__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 224; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__sampler__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__sampler__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__sampler__sampler00_output_ready__read; + counter->name = "Slice0 Subslice0 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice0 subslice0 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 248; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 8) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__sampler__sampler10_output_ready__read; + counter->name = "Slice1 Subslice0 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice1 subslice0 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 252; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__sampler__sampler01_output_ready__read; + counter->name = "Slice0 Subslice1 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice0 subslice1 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 256; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__sampler__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 16) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__sampler__sampler11_output_ready__read; + counter->name = "Slice1 Subslice1 Sampler Output Ready"; + counter->desc = "The percentage of time in which slice1 subslice1 sampler output is ready"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 272; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__sampler__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 280; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__sampler__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__sampler__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__sampler__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__sampler__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cnl_tdl_1_mux_regs[143]; +static struct brw_perf_query_register_prog cnl_tdl_1_b_counter_regs[15]; +static struct brw_perf_query_register_prog cnl_tdl_1_flex_regs[5]; + +static struct brw_perf_query_counter cnl_tdl_1_query_counters[46]; +static struct brw_perf_query_info cnl_tdl_1_query = { + .kind = OA_COUNTERS, + .name = "Metric set TDL_1", + .guid = "c46c7bb5-f26d-4634-b491-902394af85b1", + .counters = cnl_tdl_1_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cnl_tdl_1_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cnl_tdl_1_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cnl_tdl_1_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cnl_register_tdl_1_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cnl_tdl_1_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12180000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12380000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12980000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12B80000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12580000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C5000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C6C0005 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C2800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0673F000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02733000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0474A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A748000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0475A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A758000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C762800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E760200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0077C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E77C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14774000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1677A950 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18770002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0277C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04774000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06774000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08778000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A778000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A7BA802 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C7B0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x087B8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x147CE800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x167C0003 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x047C8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x067CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C7D8008 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E7D0002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00194000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E194000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02194000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18148000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C140200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A142000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0015C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A150002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00168000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E168000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02168000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0018A1A3 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0618A500 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10180000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A3900A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04394000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C342800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A348000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A35000C }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08351000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A360140 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04368000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0838A5A3 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x023800A1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10380000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12F40140 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08F42000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x14F5000A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08F52000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10F60028 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EF60008 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16F77C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18F70001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08F7C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AF74000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CFB0280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AFB0020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16FC0280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AFC8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1EFD2800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CFD0200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A992000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C990001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08994000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E940028 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C940008 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A9500C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08954000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A964000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C960002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08968000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C98A5A3 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x049800A1 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10980000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CB90014 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB94000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1EB40280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CB40020 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB50300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B58000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CB60028 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB68000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EB8A5A3 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B8A100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B80000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A590A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06594000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C548002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E540002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A550030 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08552000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A561400 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06568000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A58A5A3 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0258A100 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10580000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2100F000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D000071 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1100C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1F00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2300C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2500C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2700C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2900C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1300C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1500C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1700C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1900C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47000111 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x39000421 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49001300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D00042B }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B000011 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F001081 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3B000004 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x10800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFFC }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FFF3 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FFCF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FF3F }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FCFF }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_1__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_1__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_1__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_1__gt_request_queue_full__read; + counter->name = "SQ is full"; + counter->desc = "The percentage of time when SQ is filled above a threshold (usually 48 entries)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_1__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_1__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_1__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_1__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_1__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_1__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 16) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_1__ps_thread11_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice1 Subslice1"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice1 subslice1 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 64; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_1__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_1__non_ps_thread02_ready_for_dispatch__read; + counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice2"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 80; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_1__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_1__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 96; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_1__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 8) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_1__non_ps_thread10_ready_for_dispatch__read; + counter->name = "NonPS Thread Ready For Dispatch on Slice1 Subslice0"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice1 subslice0 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 112; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_1__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_1__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cnl__tdl_1__avg_gpu_core_frequency__max(brw); + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_1__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 136; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_1__non_ps_thread00_ready_for_dispatch__read; + counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice0"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 144; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_1__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 152; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_1__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 160; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_1__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_1__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 172; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_1__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_1__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 180; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_1__ps_thread00_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice0"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice0 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 184; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_1__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 192; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_1__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 200; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_1__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_1__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 216; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_1__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 224; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_1__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_1__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_1__ps_thread01_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice1"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 248; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 8) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_1__ps_thread10_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice1 Subslice0"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice1 subslice0 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 252; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 16) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_1__non_ps_thread11_ready_for_dispatch__read; + counter->name = "NonPS Thread Ready For Dispatch on Slice1 Subslice1"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice1 subslice1 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 256; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_1__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_1__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_1__ps_thread02_ready_for_dispatch__read; + counter->name = "PS Thread Ready For Dispatch on Slice0 Subslice2"; + counter->desc = "The percentage of time in which PS thread is ready for dispatch on slice0 subslice2 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 280; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_1__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_1__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 296; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_1__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 304; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_1__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 312; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_1__non_ps_thread01_ready_for_dispatch__read; + counter->name = "NonPS Thread Ready For Dispatch on Slice0 Subslice1"; + counter->desc = "The percentage of time in which non-PS thread is ready for dispatch on slice0 subslice1 thread dispatcher"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 320; + counter->size = sizeof(float); + } + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cnl_tdl_2_mux_regs[110]; +static struct brw_perf_query_register_prog cnl_tdl_2_b_counter_regs[5]; +static struct brw_perf_query_register_prog cnl_tdl_2_flex_regs[5]; + +static struct brw_perf_query_counter cnl_tdl_2_query_counters[46]; +static struct brw_perf_query_info cnl_tdl_2_query = { + .kind = OA_COUNTERS, + .name = "Metric set TDL_2", + .guid = "aa2d6ab4-99b3-42f8-94d6-4a9aa2baedaf", + .counters = cnl_tdl_2_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cnl_tdl_2_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cnl_tdl_2_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ + .flex_regs = cnl_tdl_2_flex_regs, + .n_flex_regs = 0, /* Determined at runtime */ +}; + +static void +cnl_register_tdl_2_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cnl_tdl_2_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12184D60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12384D60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12984D60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12B84D60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12584D60 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x186C2A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A6C0001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00738000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02737000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x12740140 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1475000A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10760028 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x16777C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x18770001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02774000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04774000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06778000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08778000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A778000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C778000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C7B0280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x087BA000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x167C0280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x027CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x047CC000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E7D2800 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A192000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C190001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E140028 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A1500C0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A164000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C160002 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0C18AFA7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10180000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C390014 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1E340280 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0A350300 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C360028 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0E38AFA7 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10380000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06F48000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08F42000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06F58000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08F52000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0EF6000A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06F7C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08F7C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AF74000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CF74000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AFB00A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AFC8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CFC8000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CFD0A00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06994000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08994000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1C94000A }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08956000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06968000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08968000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0298A700 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x049800AF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10980000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB94000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB94000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1CB400A0 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08B58000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB50001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0AB68000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0CB68000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04B8A700 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x06B800AF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10B80000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02594000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04594000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1A54A000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x00558000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x08551000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x02568000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x04568000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0058A700 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x025800AF }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x10580000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x21003000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x27000071 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x33000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2900C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2B00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2D00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x2F00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1300C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1500C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1700C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1900C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1B00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D00C000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4B003000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3F002C00 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x4D001111 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x41000421 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x43000001 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x47000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x39001080 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3B000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D000000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0x00800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0x00800000 }; + + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E458, .val = 0x00005004 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E558, .val = 0x00010003 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E658, .val = 0x00012011 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E45C, .val = 0x00051050 }; + query->flex_regs[query->n_flex_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000E55C, .val = 0x00053052 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_2__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_2__eu_active__read; + counter->name = "EU Active"; + counter->desc = "The percentage of time in which the Execution Units were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 8; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_2__eu_fpu_both_active__read; + counter->name = "EU Both FPU Pipes Active"; + counter->desc = "The percentage of time in which both EU FPU pipelines were actively processing."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 12; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 16) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_2__thread_header11_ready_port1__read; + counter->name = "Thread Header Ready on Slice1 Subslice1 Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice1 subslice1 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 16; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_2__vs_send_active__read; + counter->name = "VS Send Pipe Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 20; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_2__vs_fpu1_active__read; + counter->name = "VS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 24; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_2__gs_threads__read; + counter->name = "GS Threads Dispatched"; + counter->desc = "The total number of geometry shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_2__hi_depth_test_fails__read; + counter->name = "Early Hi-Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early hierarchical depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_2__ps_eu_both_fpu_active__read; + counter->name = "FS Both FPU Active"; + counter->desc = "The percentage of time in which fragment shaders were processed actively on the both FPUs."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 48; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_2__vs_threads__read; + counter->name = "VS Threads Dispatched"; + counter->desc = "The total number of vertex shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_2__ps_threads__read; + counter->name = "FS Threads Dispatched"; + counter->desc = "The total number of fragment shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_2__shader_barriers__read; + counter->name = "Shader Barrier Messages"; + counter->desc = "The total number of shader barrier messages."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_2__sampler_texels__read; + counter->name = "Sampler Texels"; + counter->desc = "The total number of texels seen on input (with 2x2 accuracy) in all sampler units."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_2__pixels_failing_post_ps_tests__read; + counter->name = "Pixels Failing Tests"; + counter->desc = "The total number of pixels dropped on post-FS alpha, stencil, or depth tests."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_2__thread_header01_ready_port0__read; + counter->name = "Thread Header Ready on Slice0 Subslice1 Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 96; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 2) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_2__thread_header01_ready_port1__read; + counter->name = "Thread Header Ready on Slice0 Subslice1 Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice1 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 100; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_2__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 104; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_2__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cnl__tdl_2__avg_gpu_core_frequency__max(brw); + counter->offset = 112; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_2__sampler_texel_misses__read; + counter->name = "Sampler Texels Misses"; + counter->desc = "The total number of texels lookups (with 2x2 accuracy) that missed L1 sampler cache."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 120; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_2__cs_threads__read; + counter->name = "CS Threads Dispatched"; + counter->desc = "The total number of compute shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 128; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_2__gt_request_queue_full__read; + counter->name = "SQ is full"; + counter->desc = "The percentage of time when SQ is filled above a threshold (usually 48 entries)"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 136; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_2__slm_bytes_read__read; + counter->name = "SLM Bytes Read"; + counter->desc = "The total number of GPU memory bytes read from shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 144; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 16) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_2__thread_header11_ready_port0__read; + counter->name = "Thread Header Ready on Slice1 Subslice1 Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice1 subslice1 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 152; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_2__ps_fpu1_active__read; + counter->name = "PS FPU1 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU1 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 156; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_2__ps_send_active__read; + counter->name = "PS Send Pipeline Active"; + counter->desc = "The percentage of time in which EU send pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 160; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_2__vs_fpu0_active__read; + counter->name = "VS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a vertex shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 164; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_2__gpu_busy__read; + counter->name = "GPU Busy"; + counter->desc = "The percentage of time in which the GPU has been processing GPU commands."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 168; + counter->size = sizeof(float); + + if (brw->perfquery.sys_vars.subslice_mask & 4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_2__thread_header02_ready_port1__read; + counter->name = "Thread Header Ready on Slice0 Subslice2 Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 172; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 4) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_2__thread_header02_ready_port0__read; + counter->name = "Thread Header Ready on Slice0 Subslice2 Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice2 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 176; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_2__rasterized_pixels__read; + counter->name = "Rasterized Pixels"; + counter->desc = "The total number of rasterized pixels."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 184; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_2__ps_fpu0_active__read; + counter->name = "PS FPU0 Pipe Active"; + counter->desc = "The percentage of time in which EU FPU0 pipeline was actively processing a pixel shader instruction."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 192; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_2__ds_threads__read; + counter->name = "DS Threads Dispatched"; + counter->desc = "The total number of domain shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 200; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_2__samples_written__read; + counter->name = "Samples Written"; + counter->desc = "The total number of samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 208; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 8) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_2__thread_header10_ready_port1__read; + counter->name = "Thread Header Ready on Slice1 Subslice0 Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice1 subslice0 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 216; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_2__eu_stall__read; + counter->name = "EU Stall"; + counter->desc = "The percentage of time in which the Execution Units were stalled."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 220; + counter->size = sizeof(float); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_2__samples_blended__read; + counter->name = "Samples Blended"; + counter->desc = "The total number of blended samples or pixels written to all render targets."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 224; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_2__early_depth_test_fails__read; + counter->name = "Early Depth Test Fails"; + counter->desc = "The total number of pixels dropped on early depth test."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 232; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_2__shader_memory_accesses__read; + counter->name = "Shader Memory Accesses"; + counter->desc = "The total number of shader memory accesses to L3."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 240; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_2__hs_threads__read; + counter->name = "HS Threads Dispatched"; + counter->desc = "The total number of hull shader hardware threads dispatched."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 248; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_2__l3_shader_throughput__read; + counter->name = "L3 Shader Throughput"; + counter->desc = "The total number of GPU memory bytes transferred between shaders and L3 caches w/o URB."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 256; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_2__samples_killed_in_ps__read; + counter->name = "Samples Killed in FS"; + counter->desc = "The total number of samples or pixels dropped in fragment shaders."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 264; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_2__slm_bytes_written__read; + counter->name = "SLM Bytes Written"; + counter->desc = "The total number of GPU memory bytes written into shared local memory."; + counter->type = GL_PERFQUERY_COUNTER_THROUGHPUT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* unsupported (varies over time) */; + counter->offset = 272; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 8) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_2__thread_header10_ready_port0__read; + counter->name = "Thread Header Ready on Slice1 Subslice0 Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice1 subslice0 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 280; + counter->size = sizeof(float); + } + + if (brw->perfquery.sys_vars.subslice_mask & 1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_2__thread_header00_ready_port0__read; + counter->name = "Thread Header Ready on Slice0 Subslice0 Port 0"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 0"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 284; + counter->size = sizeof(float); + } + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__tdl_2__shader_atomics__read; + counter->name = "Shader Atomic Memory Accesses"; + counter->desc = "The total number of shader atomic memory accesses."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 288; + counter->size = sizeof(uint64_t); + + if (brw->perfquery.sys_vars.subslice_mask & 1) { + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_float = cnl__tdl_2__thread_header00_ready_port1__read; + counter->name = "Thread Header Ready on Slice0 Subslice0 Port 1"; + counter->desc = "The percentage of time in which thread header is ready on slice0 subslice0 thread dispatcher port 1"; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_FLOAT_INTEL; + counter->raw_max = 100.0; + counter->offset = 296; + counter->size = sizeof(float); + } + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +static struct brw_perf_query_register_prog cnl_test_oa_mux_regs[26]; +static struct brw_perf_query_register_prog cnl_test_oa_b_counter_regs[21]; + +static struct brw_perf_query_counter cnl_test_oa_query_counters[12]; +static struct brw_perf_query_info cnl_test_oa_query = { + .kind = OA_COUNTERS, + .name = "Metric set TestOa", + .guid = "db41edd4-d8e7-4730-ad11-b9a2d6833503", + .counters = cnl_test_oa_query_counters, + .n_counters = 0, + .oa_metrics_set_id = 0, /* determined at runtime, via sysfs */ + .oa_format = I915_OA_FORMAT_A32u40_A4u32_B8_C8, + + /* Accumulation buffer offsets... */ + .gpu_time_offset = 0, + .gpu_clock_offset = 1, + .a_offset = 2, + .b_offset = 38, + .c_offset = 46, + .mux_regs = cnl_test_oa_mux_regs, + .n_mux_regs = 0, /* Determined at runtime */ + .b_counter_regs = cnl_test_oa_b_counter_regs, + .n_b_counter_regs = 0, /* Determined at runtime */ +}; + +static void +cnl_register_test_oa_counter_query(struct brw_context *brw) +{ + static struct brw_perf_query_info *query = &cnl_test_oa_query; + struct brw_perf_query_counter *counter; + + /* Note: we're assuming there can't be any variation in the definition + * of a query between contexts so it's ok to describe a query within a + * global variable which only needs to be initialized once... */ + + if (!query->data_size) { + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00000D04, .val = 0x00000200 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x17060000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009840, .val = 0x00000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x13034000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07060066 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x05060000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F080040 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x07091000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x0F041000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x1D004000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x35000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x49000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x3D000000 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009884, .val = 0x00000007 }; + query->mux_regs[query->n_mux_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00009888, .val = 0x31000000 }; + + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002740, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002710, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002714, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002720, .val = 0x00000000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002724, .val = 0xF0800000 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002770, .val = 0x00000004 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002774, .val = 0x0000FFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002778, .val = 0x00000003 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000277C, .val = 0x0000FFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002780, .val = 0x00000007 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002784, .val = 0x0000FFFF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002788, .val = 0x00100002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000278C, .val = 0x0000FFF7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002790, .val = 0x00100002 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002794, .val = 0x0000FFCF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x00002798, .val = 0x00100082 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x0000279C, .val = 0x0000FFEF }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A0, .val = 0x001000C2 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A4, .val = 0x0000FFE7 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027A8, .val = 0x00100001 }; + query->b_counter_regs[query->n_b_counter_regs++] = (struct brw_perf_query_register_prog) { .reg = 0x000027AC, .val = 0x0000FFE7 }; + + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__test_oa__counter7__read; + counter->name = "TestCounter7"; + counter->desc = "HW test counter 7. Factor: 0.6666"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 0; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__test_oa__gpu_time__read; + counter->name = "GPU Time Elapsed"; + counter->desc = "Time elapsed on the GPU during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_RAW_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 8; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__test_oa__gpu_core_clocks__read; + counter->name = "GPU Core Clocks"; + counter->desc = "The total number of GPU core clocks elapsed during the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 16; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__test_oa__avg_gpu_core_frequency__read; + counter->name = "AVG GPU Core Frequency"; + counter->desc = "Average GPU Core Frequency in the measurement."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = cnl__test_oa__avg_gpu_core_frequency__max(brw); + counter->offset = 24; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__test_oa__counter8__read; + counter->name = "TestCounter8"; + counter->desc = "HW test counter 8. Should be equal to 1."; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 32; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__test_oa__counter4__read; + counter->name = "TestCounter4"; + counter->desc = "HW test counter 4. Factor: 0.3333"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 40; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__test_oa__counter5__read; + counter->name = "TestCounter5"; + counter->desc = "HW test counter 5. Factor: 0.3333"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 48; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__test_oa__counter6__read; + counter->name = "TestCounter6"; + counter->desc = "HW test counter 6. Factor: 0.16666"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 56; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__test_oa__counter3__read; + counter->name = "TestCounter3"; + counter->desc = "HW test counter 3. Factor: 0.5"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 64; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__test_oa__counter0__read; + counter->name = "TestCounter0"; + counter->desc = "HW test counter 0. Factor: 0.0"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 72; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__test_oa__counter1__read; + counter->name = "TestCounter1"; + counter->desc = "HW test counter 1. Factor: 1.0"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 80; + counter->size = sizeof(uint64_t); + + counter = &query->counters[query->n_counters++]; + counter->oa_counter_read_uint64 = cnl__test_oa__counter2__read; + counter->name = "TestCounter2"; + counter->desc = "HW test counter 2. Factor: 1.0"; + counter->type = GL_PERFQUERY_COUNTER_EVENT_INTEL; + counter->data_type = GL_PERFQUERY_COUNTER_DATA_UINT64_INTEL; + counter->raw_max = 0 /* undefined */; + counter->offset = 88; + counter->size = sizeof(uint64_t); + + query->data_size = counter->offset + counter->size; + } + + _mesa_hash_table_insert(brw->perfquery.oa_metrics_table, query->guid, query); +} + +void +brw_oa_register_queries_cnl(struct brw_context *brw) +{ + cnl_register_render_basic_counter_query(brw); + cnl_register_compute_basic_counter_query(brw); + cnl_register_render_pipe_profile_counter_query(brw); + cnl_register_memory_reads_counter_query(brw); + cnl_register_memory_writes_counter_query(brw); + cnl_register_compute_extended_counter_query(brw); + cnl_register_compute_l3_cache_counter_query(brw); + cnl_register_hdc_and_sf_counter_query(brw); + cnl_register_l3_1_counter_query(brw); + cnl_register_l3_2_counter_query(brw); + cnl_register_rasterizer_and_pixel_backend_counter_query(brw); + cnl_register_sampler_counter_query(brw); + cnl_register_tdl_1_counter_query(brw); + cnl_register_tdl_2_counter_query(brw); + cnl_register_test_oa_counter_query(brw); +} diff --git a/prebuilt-intermediates/i965_dri_intermediates/brw_oa_metrics.h b/prebuilt-intermediates/i965_dri_intermediates/brw_oa_metrics.h new file mode 100644 index 00000000000..ff3cd3fb9d7 --- /dev/null +++ b/prebuilt-intermediates/i965_dri_intermediates/brw_oa_metrics.h @@ -0,0 +1,41 @@ +/* Autogenerated file, DO NOT EDIT manually! generated by brw_oa.py + * + * Copyright (c) 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +#pragma once + +struct brw_context; + +void brw_oa_register_queries_hsw(struct brw_context *brw); +void brw_oa_register_queries_bdw(struct brw_context *brw); +void brw_oa_register_queries_chv(struct brw_context *brw); +void brw_oa_register_queries_sklgt2(struct brw_context *brw); +void brw_oa_register_queries_sklgt3(struct brw_context *brw); +void brw_oa_register_queries_sklgt4(struct brw_context *brw); +void brw_oa_register_queries_bxt(struct brw_context *brw); +void brw_oa_register_queries_kblgt2(struct brw_context *brw); +void brw_oa_register_queries_kblgt3(struct brw_context *brw); +void brw_oa_register_queries_glk(struct brw_context *brw); +void brw_oa_register_queries_cflgt2(struct brw_context *brw); +void brw_oa_register_queries_cflgt3(struct brw_context *brw); +void brw_oa_register_queries_cnl(struct brw_context *brw); diff --git a/prebuilt-intermediates/isl/isl_format_layout.c b/prebuilt-intermediates/isl/isl_format_layout.c new file mode 100644 index 00000000000..d7d65a9b949 --- /dev/null +++ b/prebuilt-intermediates/isl/isl_format_layout.c @@ -0,0 +1,5677 @@ +/* This file is autogenerated by gen_format_layout.py. DO NOT EDIT! */ + +/* + * Copyright 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#include "isl/isl.h" + +const struct isl_format_layout +isl_format_layouts[] = { + [ISL_FORMAT_R32G32B32A32_FLOAT] = { + .format = ISL_FORMAT_R32G32B32A32_FLOAT, + .name = "ISL_FORMAT_R32G32B32A32_FLOAT", + .bpb = 128, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 0, 32 }, + .g = { ISL_SFLOAT, 32, 32 }, + .b = { ISL_SFLOAT, 64, 32 }, + .a = { ISL_SFLOAT, 96, 32 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32B32A32_SINT] = { + .format = ISL_FORMAT_R32G32B32A32_SINT, + .name = "ISL_FORMAT_R32G32B32A32_SINT", + .bpb = 128, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SINT, 0, 32 }, + .g = { ISL_SINT, 32, 32 }, + .b = { ISL_SINT, 64, 32 }, + .a = { ISL_SINT, 96, 32 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32B32A32_UINT] = { + .format = ISL_FORMAT_R32G32B32A32_UINT, + .name = "ISL_FORMAT_R32G32B32A32_UINT", + .bpb = 128, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UINT, 0, 32 }, + .g = { ISL_UINT, 32, 32 }, + .b = { ISL_UINT, 64, 32 }, + .a = { ISL_UINT, 96, 32 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32B32A32_UNORM] = { + .format = ISL_FORMAT_R32G32B32A32_UNORM, + .name = "ISL_FORMAT_R32G32B32A32_UNORM", + .bpb = 128, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 0, 32 }, + .g = { ISL_UNORM, 32, 32 }, + .b = { ISL_UNORM, 64, 32 }, + .a = { ISL_UNORM, 96, 32 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32B32A32_SNORM] = { + .format = ISL_FORMAT_R32G32B32A32_SNORM, + .name = "ISL_FORMAT_R32G32B32A32_SNORM", + .bpb = 128, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 0, 32 }, + .g = { ISL_SNORM, 32, 32 }, + .b = { ISL_SNORM, 64, 32 }, + .a = { ISL_SNORM, 96, 32 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R64G64_FLOAT] = { + .format = ISL_FORMAT_R64G64_FLOAT, + .name = "ISL_FORMAT_R64G64_FLOAT", + .bpb = 128, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 0, 64 }, + .g = { ISL_SFLOAT, 64, 64 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32B32X32_FLOAT] = { + .format = ISL_FORMAT_R32G32B32X32_FLOAT, + .name = "ISL_FORMAT_R32G32B32X32_FLOAT", + .bpb = 128, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 0, 32 }, + .g = { ISL_SFLOAT, 32, 32 }, + .b = { ISL_SFLOAT, 64, 32 }, + .a = { ISL_VOID, 96, 32 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32B32A32_SSCALED] = { + .format = ISL_FORMAT_R32G32B32A32_SSCALED, + .name = "ISL_FORMAT_R32G32B32A32_SSCALED", + .bpb = 128, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SSCALED, 0, 32 }, + .g = { ISL_SSCALED, 32, 32 }, + .b = { ISL_SSCALED, 64, 32 }, + .a = { ISL_SSCALED, 96, 32 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32B32A32_USCALED] = { + .format = ISL_FORMAT_R32G32B32A32_USCALED, + .name = "ISL_FORMAT_R32G32B32A32_USCALED", + .bpb = 128, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_USCALED, 0, 32 }, + .g = { ISL_USCALED, 32, 32 }, + .b = { ISL_USCALED, 64, 32 }, + .a = { ISL_USCALED, 96, 32 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32B32A32_SFIXED] = { + .format = ISL_FORMAT_R32G32B32A32_SFIXED, + .name = "ISL_FORMAT_R32G32B32A32_SFIXED", + .bpb = 128, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFIXED, 0, 32 }, + .g = { ISL_SFIXED, 32, 32 }, + .b = { ISL_SFIXED, 64, 32 }, + .a = { ISL_SFIXED, 96, 32 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R64G64_PASSTHRU] = { + .format = ISL_FORMAT_R64G64_PASSTHRU, + .name = "ISL_FORMAT_R64G64_PASSTHRU", + .bpb = 128, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_RAW, 0, 64 }, + .g = { ISL_RAW, 64, 64 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32B32_FLOAT] = { + .format = ISL_FORMAT_R32G32B32_FLOAT, + .name = "ISL_FORMAT_R32G32B32_FLOAT", + .bpb = 96, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 0, 32 }, + .g = { ISL_SFLOAT, 32, 32 }, + .b = { ISL_SFLOAT, 64, 32 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32B32_SINT] = { + .format = ISL_FORMAT_R32G32B32_SINT, + .name = "ISL_FORMAT_R32G32B32_SINT", + .bpb = 96, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SINT, 0, 32 }, + .g = { ISL_SINT, 32, 32 }, + .b = { ISL_SINT, 64, 32 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32B32_UINT] = { + .format = ISL_FORMAT_R32G32B32_UINT, + .name = "ISL_FORMAT_R32G32B32_UINT", + .bpb = 96, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UINT, 0, 32 }, + .g = { ISL_UINT, 32, 32 }, + .b = { ISL_UINT, 64, 32 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32B32_UNORM] = { + .format = ISL_FORMAT_R32G32B32_UNORM, + .name = "ISL_FORMAT_R32G32B32_UNORM", + .bpb = 96, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 0, 32 }, + .g = { ISL_UNORM, 32, 32 }, + .b = { ISL_UNORM, 64, 32 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32B32_SNORM] = { + .format = ISL_FORMAT_R32G32B32_SNORM, + .name = "ISL_FORMAT_R32G32B32_SNORM", + .bpb = 96, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 0, 32 }, + .g = { ISL_SNORM, 32, 32 }, + .b = { ISL_SNORM, 64, 32 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32B32_SSCALED] = { + .format = ISL_FORMAT_R32G32B32_SSCALED, + .name = "ISL_FORMAT_R32G32B32_SSCALED", + .bpb = 96, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SSCALED, 0, 32 }, + .g = { ISL_SSCALED, 32, 32 }, + .b = { ISL_SSCALED, 64, 32 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32B32_USCALED] = { + .format = ISL_FORMAT_R32G32B32_USCALED, + .name = "ISL_FORMAT_R32G32B32_USCALED", + .bpb = 96, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_USCALED, 0, 32 }, + .g = { ISL_USCALED, 32, 32 }, + .b = { ISL_USCALED, 64, 32 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32B32_SFIXED] = { + .format = ISL_FORMAT_R32G32B32_SFIXED, + .name = "ISL_FORMAT_R32G32B32_SFIXED", + .bpb = 96, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFIXED, 0, 32 }, + .g = { ISL_SFIXED, 32, 32 }, + .b = { ISL_SFIXED, 64, 32 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16B16A16_UNORM] = { + .format = ISL_FORMAT_R16G16B16A16_UNORM, + .name = "ISL_FORMAT_R16G16B16A16_UNORM", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 0, 16 }, + .g = { ISL_UNORM, 16, 16 }, + .b = { ISL_UNORM, 32, 16 }, + .a = { ISL_UNORM, 48, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16B16A16_SNORM] = { + .format = ISL_FORMAT_R16G16B16A16_SNORM, + .name = "ISL_FORMAT_R16G16B16A16_SNORM", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 0, 16 }, + .g = { ISL_SNORM, 16, 16 }, + .b = { ISL_SNORM, 32, 16 }, + .a = { ISL_SNORM, 48, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16B16A16_SINT] = { + .format = ISL_FORMAT_R16G16B16A16_SINT, + .name = "ISL_FORMAT_R16G16B16A16_SINT", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SINT, 0, 16 }, + .g = { ISL_SINT, 16, 16 }, + .b = { ISL_SINT, 32, 16 }, + .a = { ISL_SINT, 48, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16B16A16_UINT] = { + .format = ISL_FORMAT_R16G16B16A16_UINT, + .name = "ISL_FORMAT_R16G16B16A16_UINT", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UINT, 0, 16 }, + .g = { ISL_UINT, 16, 16 }, + .b = { ISL_UINT, 32, 16 }, + .a = { ISL_UINT, 48, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16B16A16_FLOAT] = { + .format = ISL_FORMAT_R16G16B16A16_FLOAT, + .name = "ISL_FORMAT_R16G16B16A16_FLOAT", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 0, 16 }, + .g = { ISL_SFLOAT, 16, 16 }, + .b = { ISL_SFLOAT, 32, 16 }, + .a = { ISL_SFLOAT, 48, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32_FLOAT] = { + .format = ISL_FORMAT_R32G32_FLOAT, + .name = "ISL_FORMAT_R32G32_FLOAT", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 0, 32 }, + .g = { ISL_SFLOAT, 32, 32 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32_SINT] = { + .format = ISL_FORMAT_R32G32_SINT, + .name = "ISL_FORMAT_R32G32_SINT", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SINT, 0, 32 }, + .g = { ISL_SINT, 32, 32 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32_UINT] = { + .format = ISL_FORMAT_R32G32_UINT, + .name = "ISL_FORMAT_R32G32_UINT", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UINT, 0, 32 }, + .g = { ISL_UINT, 32, 32 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS] = { + .format = ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS, + .name = "ISL_FORMAT_R32_FLOAT_X8X24_TYPELESS", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 0, 32 }, + .g = { ISL_VOID, 32, 8 }, + .b = { ISL_VOID, 40, 24 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_X32_TYPELESS_G8X24_UINT] = { + .format = ISL_FORMAT_X32_TYPELESS_G8X24_UINT, + .name = "ISL_FORMAT_X32_TYPELESS_G8X24_UINT", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_VOID, 0, 32 }, + .g = { ISL_UINT, 32, 8 }, + .b = { ISL_VOID, 40, 24 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_L32A32_FLOAT] = { + .format = ISL_FORMAT_L32A32_FLOAT, + .name = "ISL_FORMAT_L32A32_FLOAT", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_SFLOAT, 32, 32 }, + .l = { ISL_SFLOAT, 0, 32 }, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32_UNORM] = { + .format = ISL_FORMAT_R32G32_UNORM, + .name = "ISL_FORMAT_R32G32_UNORM", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 0, 32 }, + .g = { ISL_UNORM, 32, 32 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32_SNORM] = { + .format = ISL_FORMAT_R32G32_SNORM, + .name = "ISL_FORMAT_R32G32_SNORM", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 0, 32 }, + .g = { ISL_SNORM, 32, 32 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R64_FLOAT] = { + .format = ISL_FORMAT_R64_FLOAT, + .name = "ISL_FORMAT_R64_FLOAT", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 0, 64 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16B16X16_UNORM] = { + .format = ISL_FORMAT_R16G16B16X16_UNORM, + .name = "ISL_FORMAT_R16G16B16X16_UNORM", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 0, 16 }, + .g = { ISL_UNORM, 16, 16 }, + .b = { ISL_UNORM, 32, 16 }, + .a = { ISL_VOID, 48, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16B16X16_FLOAT] = { + .format = ISL_FORMAT_R16G16B16X16_FLOAT, + .name = "ISL_FORMAT_R16G16B16X16_FLOAT", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 0, 16 }, + .g = { ISL_SFLOAT, 16, 16 }, + .b = { ISL_SFLOAT, 32, 16 }, + .a = { ISL_VOID, 48, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_A32X32_FLOAT] = { + .format = ISL_FORMAT_A32X32_FLOAT, + .name = "ISL_FORMAT_A32X32_FLOAT", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_SFLOAT, 0, 32 }, + .l = { ISL_VOID, 32, 32 }, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_L32X32_FLOAT] = { + .format = ISL_FORMAT_L32X32_FLOAT, + .name = "ISL_FORMAT_L32X32_FLOAT", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_VOID, 32, 32 }, + .l = { ISL_SFLOAT, 0, 32 }, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_I32X32_FLOAT] = { + .format = ISL_FORMAT_I32X32_FLOAT, + .name = "ISL_FORMAT_I32X32_FLOAT", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_VOID, 32, 32 }, + .l = {}, + .i = { ISL_SFLOAT, 0, 32 }, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16B16A16_SSCALED] = { + .format = ISL_FORMAT_R16G16B16A16_SSCALED, + .name = "ISL_FORMAT_R16G16B16A16_SSCALED", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SSCALED, 0, 16 }, + .g = { ISL_SSCALED, 16, 16 }, + .b = { ISL_SSCALED, 32, 16 }, + .a = { ISL_SSCALED, 48, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16B16A16_USCALED] = { + .format = ISL_FORMAT_R16G16B16A16_USCALED, + .name = "ISL_FORMAT_R16G16B16A16_USCALED", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_USCALED, 0, 16 }, + .g = { ISL_USCALED, 16, 16 }, + .b = { ISL_USCALED, 32, 16 }, + .a = { ISL_USCALED, 48, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32_SSCALED] = { + .format = ISL_FORMAT_R32G32_SSCALED, + .name = "ISL_FORMAT_R32G32_SSCALED", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SSCALED, 0, 32 }, + .g = { ISL_SSCALED, 32, 32 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32_USCALED] = { + .format = ISL_FORMAT_R32G32_USCALED, + .name = "ISL_FORMAT_R32G32_USCALED", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_USCALED, 0, 32 }, + .g = { ISL_USCALED, 32, 32 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32_FLOAT_LD] = { + .format = ISL_FORMAT_R32G32_FLOAT_LD, + .name = "ISL_FORMAT_R32G32_FLOAT_LD", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 0, 32 }, + .g = { ISL_SFLOAT, 32, 32 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32G32_SFIXED] = { + .format = ISL_FORMAT_R32G32_SFIXED, + .name = "ISL_FORMAT_R32G32_SFIXED", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFIXED, 0, 32 }, + .g = { ISL_SFIXED, 32, 32 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R64_PASSTHRU] = { + .format = ISL_FORMAT_R64_PASSTHRU, + .name = "ISL_FORMAT_R64_PASSTHRU", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_RAW, 0, 64 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B8G8R8A8_UNORM] = { + .format = ISL_FORMAT_B8G8R8A8_UNORM, + .name = "ISL_FORMAT_B8G8R8A8_UNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 16, 8 }, + .g = { ISL_UNORM, 8, 8 }, + .b = { ISL_UNORM, 0, 8 }, + .a = { ISL_UNORM, 24, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B8G8R8A8_UNORM_SRGB] = { + .format = ISL_FORMAT_B8G8R8A8_UNORM_SRGB, + .name = "ISL_FORMAT_B8G8R8A8_UNORM_SRGB", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 16, 8 }, + .g = { ISL_UNORM, 8, 8 }, + .b = { ISL_UNORM, 0, 8 }, + .a = { ISL_UNORM, 24, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R10G10B10A2_UNORM] = { + .format = ISL_FORMAT_R10G10B10A2_UNORM, + .name = "ISL_FORMAT_R10G10B10A2_UNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 0, 10 }, + .g = { ISL_UNORM, 10, 10 }, + .b = { ISL_UNORM, 20, 10 }, + .a = { ISL_UNORM, 30, 2 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R10G10B10A2_UNORM_SRGB] = { + .format = ISL_FORMAT_R10G10B10A2_UNORM_SRGB, + .name = "ISL_FORMAT_R10G10B10A2_UNORM_SRGB", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 0, 10 }, + .g = { ISL_UNORM, 10, 10 }, + .b = { ISL_UNORM, 20, 10 }, + .a = { ISL_UNORM, 30, 2 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R10G10B10A2_UINT] = { + .format = ISL_FORMAT_R10G10B10A2_UINT, + .name = "ISL_FORMAT_R10G10B10A2_UINT", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UINT, 0, 10 }, + .g = { ISL_UINT, 10, 10 }, + .b = { ISL_UINT, 20, 10 }, + .a = { ISL_UINT, 30, 2 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R10G10B10_SNORM_A2_UNORM] = { + .format = ISL_FORMAT_R10G10B10_SNORM_A2_UNORM, + .name = "ISL_FORMAT_R10G10B10_SNORM_A2_UNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 0, 10 }, + .g = { ISL_SNORM, 10, 10 }, + .b = { ISL_SNORM, 20, 10 }, + .a = { ISL_UNORM, 30, 2 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8B8A8_UNORM] = { + .format = ISL_FORMAT_R8G8B8A8_UNORM, + .name = "ISL_FORMAT_R8G8B8A8_UNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 0, 8 }, + .g = { ISL_UNORM, 8, 8 }, + .b = { ISL_UNORM, 16, 8 }, + .a = { ISL_UNORM, 24, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8B8A8_UNORM_SRGB] = { + .format = ISL_FORMAT_R8G8B8A8_UNORM_SRGB, + .name = "ISL_FORMAT_R8G8B8A8_UNORM_SRGB", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 0, 8 }, + .g = { ISL_UNORM, 8, 8 }, + .b = { ISL_UNORM, 16, 8 }, + .a = { ISL_UNORM, 24, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8B8A8_SNORM] = { + .format = ISL_FORMAT_R8G8B8A8_SNORM, + .name = "ISL_FORMAT_R8G8B8A8_SNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 0, 8 }, + .g = { ISL_SNORM, 8, 8 }, + .b = { ISL_SNORM, 16, 8 }, + .a = { ISL_SNORM, 24, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8B8A8_SINT] = { + .format = ISL_FORMAT_R8G8B8A8_SINT, + .name = "ISL_FORMAT_R8G8B8A8_SINT", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SINT, 0, 8 }, + .g = { ISL_SINT, 8, 8 }, + .b = { ISL_SINT, 16, 8 }, + .a = { ISL_SINT, 24, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8B8A8_UINT] = { + .format = ISL_FORMAT_R8G8B8A8_UINT, + .name = "ISL_FORMAT_R8G8B8A8_UINT", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UINT, 0, 8 }, + .g = { ISL_UINT, 8, 8 }, + .b = { ISL_UINT, 16, 8 }, + .a = { ISL_UINT, 24, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16_UNORM] = { + .format = ISL_FORMAT_R16G16_UNORM, + .name = "ISL_FORMAT_R16G16_UNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 0, 16 }, + .g = { ISL_UNORM, 16, 16 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16_SNORM] = { + .format = ISL_FORMAT_R16G16_SNORM, + .name = "ISL_FORMAT_R16G16_SNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 0, 16 }, + .g = { ISL_SNORM, 16, 16 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16_SINT] = { + .format = ISL_FORMAT_R16G16_SINT, + .name = "ISL_FORMAT_R16G16_SINT", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SINT, 0, 16 }, + .g = { ISL_SINT, 16, 16 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16_UINT] = { + .format = ISL_FORMAT_R16G16_UINT, + .name = "ISL_FORMAT_R16G16_UINT", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UINT, 0, 16 }, + .g = { ISL_UINT, 16, 16 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16_FLOAT] = { + .format = ISL_FORMAT_R16G16_FLOAT, + .name = "ISL_FORMAT_R16G16_FLOAT", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 0, 16 }, + .g = { ISL_SFLOAT, 16, 16 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B10G10R10A2_UNORM] = { + .format = ISL_FORMAT_B10G10R10A2_UNORM, + .name = "ISL_FORMAT_B10G10R10A2_UNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 20, 10 }, + .g = { ISL_UNORM, 10, 10 }, + .b = { ISL_UNORM, 0, 10 }, + .a = { ISL_UNORM, 30, 2 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B10G10R10A2_UNORM_SRGB] = { + .format = ISL_FORMAT_B10G10R10A2_UNORM_SRGB, + .name = "ISL_FORMAT_B10G10R10A2_UNORM_SRGB", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 20, 10 }, + .g = { ISL_UNORM, 10, 10 }, + .b = { ISL_UNORM, 0, 10 }, + .a = { ISL_UNORM, 30, 2 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R11G11B10_FLOAT] = { + .format = ISL_FORMAT_R11G11B10_FLOAT, + .name = "ISL_FORMAT_R11G11B10_FLOAT", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UFLOAT, 0, 11 }, + .g = { ISL_UFLOAT, 11, 11 }, + .b = { ISL_UFLOAT, 22, 10 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32_SINT] = { + .format = ISL_FORMAT_R32_SINT, + .name = "ISL_FORMAT_R32_SINT", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SINT, 0, 32 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32_UINT] = { + .format = ISL_FORMAT_R32_UINT, + .name = "ISL_FORMAT_R32_UINT", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UINT, 0, 32 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32_FLOAT] = { + .format = ISL_FORMAT_R32_FLOAT, + .name = "ISL_FORMAT_R32_FLOAT", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 0, 32 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R24_UNORM_X8_TYPELESS] = { + .format = ISL_FORMAT_R24_UNORM_X8_TYPELESS, + .name = "ISL_FORMAT_R24_UNORM_X8_TYPELESS", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 0, 24 }, + .g = { ISL_VOID, 24, 8 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_X24_TYPELESS_G8_UINT] = { + .format = ISL_FORMAT_X24_TYPELESS_G8_UINT, + .name = "ISL_FORMAT_X24_TYPELESS_G8_UINT", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_VOID, 0, 24 }, + .g = { ISL_UINT, 24, 8 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_L32_UNORM] = { + .format = ISL_FORMAT_L32_UNORM, + .name = "ISL_FORMAT_L32_UNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = { ISL_UNORM, 0, 32 }, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_A32_UNORM] = { + .format = ISL_FORMAT_A32_UNORM, + .name = "ISL_FORMAT_A32_UNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_UNORM, 0, 32 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_L16A16_UNORM] = { + .format = ISL_FORMAT_L16A16_UNORM, + .name = "ISL_FORMAT_L16A16_UNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_UNORM, 16, 16 }, + .l = { ISL_UNORM, 0, 16 }, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_I24X8_UNORM] = { + .format = ISL_FORMAT_I24X8_UNORM, + .name = "ISL_FORMAT_I24X8_UNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_VOID, 24, 8 }, + .l = {}, + .i = { ISL_UNORM, 0, 24 }, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_L24X8_UNORM] = { + .format = ISL_FORMAT_L24X8_UNORM, + .name = "ISL_FORMAT_L24X8_UNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_VOID, 24, 8 }, + .l = { ISL_UNORM, 0, 24 }, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_A24X8_UNORM] = { + .format = ISL_FORMAT_A24X8_UNORM, + .name = "ISL_FORMAT_A24X8_UNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_UNORM, 0, 24 }, + .l = { ISL_VOID, 24, 8 }, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_I32_FLOAT] = { + .format = ISL_FORMAT_I32_FLOAT, + .name = "ISL_FORMAT_I32_FLOAT", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = { ISL_SFLOAT, 0, 32 }, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_L32_FLOAT] = { + .format = ISL_FORMAT_L32_FLOAT, + .name = "ISL_FORMAT_L32_FLOAT", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = { ISL_SFLOAT, 0, 32 }, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_A32_FLOAT] = { + .format = ISL_FORMAT_A32_FLOAT, + .name = "ISL_FORMAT_A32_FLOAT", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_SFLOAT, 0, 32 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_X8B8_UNORM_G8R8_SNORM] = { + .format = ISL_FORMAT_X8B8_UNORM_G8R8_SNORM, + .name = "ISL_FORMAT_X8B8_UNORM_G8R8_SNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 24, 8 }, + .g = { ISL_SNORM, 16, 8 }, + .b = { ISL_UNORM, 8, 8 }, + .a = { ISL_VOID, 0, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_A8X8_UNORM_G8R8_SNORM] = { + .format = ISL_FORMAT_A8X8_UNORM_G8R8_SNORM, + .name = "ISL_FORMAT_A8X8_UNORM_G8R8_SNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 24, 8 }, + .g = { ISL_SNORM, 16, 8 }, + .b = { ISL_VOID, 8, 8 }, + .a = { ISL_UNORM, 0, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B8X8_UNORM_G8R8_SNORM] = { + .format = ISL_FORMAT_B8X8_UNORM_G8R8_SNORM, + .name = "ISL_FORMAT_B8X8_UNORM_G8R8_SNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 24, 8 }, + .g = { ISL_SNORM, 16, 8 }, + .b = { ISL_UNORM, 0, 8 }, + .a = { ISL_VOID, 8, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B8G8R8X8_UNORM] = { + .format = ISL_FORMAT_B8G8R8X8_UNORM, + .name = "ISL_FORMAT_B8G8R8X8_UNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 16, 8 }, + .g = { ISL_UNORM, 8, 8 }, + .b = { ISL_UNORM, 0, 8 }, + .a = { ISL_VOID, 24, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B8G8R8X8_UNORM_SRGB] = { + .format = ISL_FORMAT_B8G8R8X8_UNORM_SRGB, + .name = "ISL_FORMAT_B8G8R8X8_UNORM_SRGB", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 16, 8 }, + .g = { ISL_UNORM, 8, 8 }, + .b = { ISL_UNORM, 0, 8 }, + .a = { ISL_VOID, 24, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8B8X8_UNORM] = { + .format = ISL_FORMAT_R8G8B8X8_UNORM, + .name = "ISL_FORMAT_R8G8B8X8_UNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 0, 8 }, + .g = { ISL_UNORM, 8, 8 }, + .b = { ISL_UNORM, 16, 8 }, + .a = { ISL_VOID, 24, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8B8X8_UNORM_SRGB] = { + .format = ISL_FORMAT_R8G8B8X8_UNORM_SRGB, + .name = "ISL_FORMAT_R8G8B8X8_UNORM_SRGB", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 0, 8 }, + .g = { ISL_UNORM, 8, 8 }, + .b = { ISL_UNORM, 16, 8 }, + .a = { ISL_VOID, 24, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R9G9B9E5_SHAREDEXP] = { + .format = ISL_FORMAT_R9G9B9E5_SHAREDEXP, + .name = "ISL_FORMAT_R9G9B9E5_SHAREDEXP", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UFLOAT, 0, 9 }, + .g = { ISL_UFLOAT, 9, 9 }, + .b = { ISL_UFLOAT, 18, 9 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B10G10R10X2_UNORM] = { + .format = ISL_FORMAT_B10G10R10X2_UNORM, + .name = "ISL_FORMAT_B10G10R10X2_UNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 20, 10 }, + .g = { ISL_UNORM, 10, 10 }, + .b = { ISL_UNORM, 0, 10 }, + .a = { ISL_VOID, 30, 2 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_L16A16_FLOAT] = { + .format = ISL_FORMAT_L16A16_FLOAT, + .name = "ISL_FORMAT_L16A16_FLOAT", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_SFLOAT, 16, 16 }, + .l = { ISL_SFLOAT, 0, 16 }, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32_UNORM] = { + .format = ISL_FORMAT_R32_UNORM, + .name = "ISL_FORMAT_R32_UNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 0, 32 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32_SNORM] = { + .format = ISL_FORMAT_R32_SNORM, + .name = "ISL_FORMAT_R32_SNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 0, 32 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R10G10B10X2_USCALED] = { + .format = ISL_FORMAT_R10G10B10X2_USCALED, + .name = "ISL_FORMAT_R10G10B10X2_USCALED", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_USCALED, 0, 10 }, + .g = { ISL_USCALED, 10, 10 }, + .b = { ISL_USCALED, 20, 10 }, + .a = { ISL_VOID, 30, 2 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8B8A8_SSCALED] = { + .format = ISL_FORMAT_R8G8B8A8_SSCALED, + .name = "ISL_FORMAT_R8G8B8A8_SSCALED", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SSCALED, 0, 8 }, + .g = { ISL_SSCALED, 8, 8 }, + .b = { ISL_SSCALED, 16, 8 }, + .a = { ISL_SSCALED, 24, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8B8A8_USCALED] = { + .format = ISL_FORMAT_R8G8B8A8_USCALED, + .name = "ISL_FORMAT_R8G8B8A8_USCALED", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_USCALED, 0, 8 }, + .g = { ISL_USCALED, 8, 8 }, + .b = { ISL_USCALED, 16, 8 }, + .a = { ISL_USCALED, 24, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16_SSCALED] = { + .format = ISL_FORMAT_R16G16_SSCALED, + .name = "ISL_FORMAT_R16G16_SSCALED", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SSCALED, 0, 16 }, + .g = { ISL_SSCALED, 16, 6 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16_USCALED] = { + .format = ISL_FORMAT_R16G16_USCALED, + .name = "ISL_FORMAT_R16G16_USCALED", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_USCALED, 0, 16 }, + .g = { ISL_USCALED, 16, 16 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32_SSCALED] = { + .format = ISL_FORMAT_R32_SSCALED, + .name = "ISL_FORMAT_R32_SSCALED", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SSCALED, 0, 32 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32_USCALED] = { + .format = ISL_FORMAT_R32_USCALED, + .name = "ISL_FORMAT_R32_USCALED", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_USCALED, 0, 32 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B5G6R5_UNORM] = { + .format = ISL_FORMAT_B5G6R5_UNORM, + .name = "ISL_FORMAT_B5G6R5_UNORM", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 11, 5 }, + .g = { ISL_UNORM, 5, 6 }, + .b = { ISL_UNORM, 0, 5 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B5G6R5_UNORM_SRGB] = { + .format = ISL_FORMAT_B5G6R5_UNORM_SRGB, + .name = "ISL_FORMAT_B5G6R5_UNORM_SRGB", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 11, 5 }, + .g = { ISL_UNORM, 5, 6 }, + .b = { ISL_UNORM, 0, 5 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B5G5R5A1_UNORM] = { + .format = ISL_FORMAT_B5G5R5A1_UNORM, + .name = "ISL_FORMAT_B5G5R5A1_UNORM", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 10, 5 }, + .g = { ISL_UNORM, 5, 5 }, + .b = { ISL_UNORM, 0, 5 }, + .a = { ISL_UNORM, 15, 1 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B5G5R5A1_UNORM_SRGB] = { + .format = ISL_FORMAT_B5G5R5A1_UNORM_SRGB, + .name = "ISL_FORMAT_B5G5R5A1_UNORM_SRGB", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 10, 5 }, + .g = { ISL_UNORM, 5, 5 }, + .b = { ISL_UNORM, 0, 5 }, + .a = { ISL_UNORM, 15, 1 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B4G4R4A4_UNORM] = { + .format = ISL_FORMAT_B4G4R4A4_UNORM, + .name = "ISL_FORMAT_B4G4R4A4_UNORM", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8, 4 }, + .g = { ISL_UNORM, 4, 4 }, + .b = { ISL_UNORM, 0, 4 }, + .a = { ISL_UNORM, 12, 4 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B4G4R4A4_UNORM_SRGB] = { + .format = ISL_FORMAT_B4G4R4A4_UNORM_SRGB, + .name = "ISL_FORMAT_B4G4R4A4_UNORM_SRGB", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 8, 4 }, + .g = { ISL_UNORM, 4, 4 }, + .b = { ISL_UNORM, 0, 4 }, + .a = { ISL_UNORM, 12, 4 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8_UNORM] = { + .format = ISL_FORMAT_R8G8_UNORM, + .name = "ISL_FORMAT_R8G8_UNORM", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 0, 8 }, + .g = { ISL_UNORM, 8, 8 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8_SNORM] = { + .format = ISL_FORMAT_R8G8_SNORM, + .name = "ISL_FORMAT_R8G8_SNORM", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 0, 8 }, + .g = { ISL_SNORM, 8, 8 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8_SINT] = { + .format = ISL_FORMAT_R8G8_SINT, + .name = "ISL_FORMAT_R8G8_SINT", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SINT, 0, 8 }, + .g = { ISL_SINT, 8, 8 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8_UINT] = { + .format = ISL_FORMAT_R8G8_UINT, + .name = "ISL_FORMAT_R8G8_UINT", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UINT, 0, 8 }, + .g = { ISL_UINT, 8, 8 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16_UNORM] = { + .format = ISL_FORMAT_R16_UNORM, + .name = "ISL_FORMAT_R16_UNORM", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 0, 16 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16_SNORM] = { + .format = ISL_FORMAT_R16_SNORM, + .name = "ISL_FORMAT_R16_SNORM", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 0, 16 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16_SINT] = { + .format = ISL_FORMAT_R16_SINT, + .name = "ISL_FORMAT_R16_SINT", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SINT, 0, 16 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16_UINT] = { + .format = ISL_FORMAT_R16_UINT, + .name = "ISL_FORMAT_R16_UINT", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UINT, 0, 16 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16_FLOAT] = { + .format = ISL_FORMAT_R16_FLOAT, + .name = "ISL_FORMAT_R16_FLOAT", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 0, 16 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_A8P8_UNORM_PALETTE0] = { + .format = ISL_FORMAT_A8P8_UNORM_PALETTE0, + .name = "ISL_FORMAT_A8P8_UNORM_PALETTE0", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_UNORM, 0, 8 }, + .l = {}, + .i = {}, + .p = { ISL_UNORM, 8, 8 }, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_A8P8_UNORM_PALETTE1] = { + .format = ISL_FORMAT_A8P8_UNORM_PALETTE1, + .name = "ISL_FORMAT_A8P8_UNORM_PALETTE1", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_UNORM, 0, 8 }, + .l = {}, + .i = {}, + .p = { ISL_UNORM, 8, 8 }, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_I16_UNORM] = { + .format = ISL_FORMAT_I16_UNORM, + .name = "ISL_FORMAT_I16_UNORM", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = { ISL_UNORM, 0, 16 }, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_L16_UNORM] = { + .format = ISL_FORMAT_L16_UNORM, + .name = "ISL_FORMAT_L16_UNORM", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = { ISL_UNORM, 0, 16 }, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_A16_UNORM] = { + .format = ISL_FORMAT_A16_UNORM, + .name = "ISL_FORMAT_A16_UNORM", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_UNORM, 0, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_L8A8_UNORM] = { + .format = ISL_FORMAT_L8A8_UNORM, + .name = "ISL_FORMAT_L8A8_UNORM", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_UNORM, 8, 8 }, + .l = { ISL_UNORM, 0, 8 }, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_I16_FLOAT] = { + .format = ISL_FORMAT_I16_FLOAT, + .name = "ISL_FORMAT_I16_FLOAT", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = { ISL_SFLOAT, 0, 16 }, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_L16_FLOAT] = { + .format = ISL_FORMAT_L16_FLOAT, + .name = "ISL_FORMAT_L16_FLOAT", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = { ISL_SFLOAT, 0, 16 }, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_A16_FLOAT] = { + .format = ISL_FORMAT_A16_FLOAT, + .name = "ISL_FORMAT_A16_FLOAT", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_SFLOAT, 0, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_L8A8_UNORM_SRGB] = { + .format = ISL_FORMAT_L8A8_UNORM_SRGB, + .name = "ISL_FORMAT_L8A8_UNORM_SRGB", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_UNORM, 8, 8 }, + .l = { ISL_UNORM, 0, 8 }, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R5G5_SNORM_B6_UNORM] = { + .format = ISL_FORMAT_R5G5_SNORM_B6_UNORM, + .name = "ISL_FORMAT_R5G5_SNORM_B6_UNORM", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 0, 5 }, + .g = { ISL_SNORM, 5, 5 }, + .b = { ISL_UNORM, 10, 6 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B5G5R5X1_UNORM] = { + .format = ISL_FORMAT_B5G5R5X1_UNORM, + .name = "ISL_FORMAT_B5G5R5X1_UNORM", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 10, 5 }, + .g = { ISL_UNORM, 5, 5 }, + .b = { ISL_UNORM, 0, 5 }, + .a = { ISL_VOID, 15, 1 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B5G5R5X1_UNORM_SRGB] = { + .format = ISL_FORMAT_B5G5R5X1_UNORM_SRGB, + .name = "ISL_FORMAT_B5G5R5X1_UNORM_SRGB", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 10, 5 }, + .g = { ISL_UNORM, 5, 5 }, + .b = { ISL_UNORM, 0, 5 }, + .a = { ISL_VOID, 15, 1 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8_SSCALED] = { + .format = ISL_FORMAT_R8G8_SSCALED, + .name = "ISL_FORMAT_R8G8_SSCALED", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SSCALED, 0, 8 }, + .g = { ISL_SSCALED, 8, 8 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8_USCALED] = { + .format = ISL_FORMAT_R8G8_USCALED, + .name = "ISL_FORMAT_R8G8_USCALED", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_USCALED, 0, 8 }, + .g = { ISL_USCALED, 8, 8 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16_SSCALED] = { + .format = ISL_FORMAT_R16_SSCALED, + .name = "ISL_FORMAT_R16_SSCALED", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SSCALED, 0, 16 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16_USCALED] = { + .format = ISL_FORMAT_R16_USCALED, + .name = "ISL_FORMAT_R16_USCALED", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_USCALED, 0, 16 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_P8A8_UNORM_PALETTE0] = { + .format = ISL_FORMAT_P8A8_UNORM_PALETTE0, + .name = "ISL_FORMAT_P8A8_UNORM_PALETTE0", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_UNORM, 8, 8 }, + .l = {}, + .i = {}, + .p = { ISL_UNORM, 0, 8 }, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_P8A8_UNORM_PALETTE1] = { + .format = ISL_FORMAT_P8A8_UNORM_PALETTE1, + .name = "ISL_FORMAT_P8A8_UNORM_PALETTE1", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_UNORM, 8, 8 }, + .l = {}, + .i = {}, + .p = { ISL_UNORM, 0, 8 }, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_A1B5G5R5_UNORM] = { + .format = ISL_FORMAT_A1B5G5R5_UNORM, + .name = "ISL_FORMAT_A1B5G5R5_UNORM", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 11, 5 }, + .g = { ISL_UNORM, 6, 5 }, + .b = { ISL_UNORM, 1, 5 }, + .a = { ISL_UNORM, 0, 1 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_A4B4G4R4_UNORM] = { + .format = ISL_FORMAT_A4B4G4R4_UNORM, + .name = "ISL_FORMAT_A4B4G4R4_UNORM", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 12, 4 }, + .g = { ISL_UNORM, 8, 4 }, + .b = { ISL_UNORM, 4, 4 }, + .a = { ISL_UNORM, 0, 4 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_L8A8_UINT] = { + .format = ISL_FORMAT_L8A8_UINT, + .name = "ISL_FORMAT_L8A8_UINT", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_UINT, 8, 8 }, + .l = { ISL_UINT, 0, 8 }, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_L8A8_SINT] = { + .format = ISL_FORMAT_L8A8_SINT, + .name = "ISL_FORMAT_L8A8_SINT", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_SINT, 8, 8 }, + .l = { ISL_SINT, 0, 8 }, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8_UNORM] = { + .format = ISL_FORMAT_R8_UNORM, + .name = "ISL_FORMAT_R8_UNORM", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 0, 8 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8_SNORM] = { + .format = ISL_FORMAT_R8_SNORM, + .name = "ISL_FORMAT_R8_SNORM", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 0, 8 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8_SINT] = { + .format = ISL_FORMAT_R8_SINT, + .name = "ISL_FORMAT_R8_SINT", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SINT, 0, 8 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8_UINT] = { + .format = ISL_FORMAT_R8_UINT, + .name = "ISL_FORMAT_R8_UINT", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UINT, 0, 8 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_A8_UNORM] = { + .format = ISL_FORMAT_A8_UNORM, + .name = "ISL_FORMAT_A8_UNORM", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_UNORM, 0, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_I8_UNORM] = { + .format = ISL_FORMAT_I8_UNORM, + .name = "ISL_FORMAT_I8_UNORM", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = { ISL_UNORM, 0, 8 }, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_L8_UNORM] = { + .format = ISL_FORMAT_L8_UNORM, + .name = "ISL_FORMAT_L8_UNORM", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = { ISL_UNORM, 0, 8 }, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_P4A4_UNORM_PALETTE0] = { + .format = ISL_FORMAT_P4A4_UNORM_PALETTE0, + .name = "ISL_FORMAT_P4A4_UNORM_PALETTE0", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_UNORM, 4, 4 }, + .l = {}, + .i = {}, + .p = { ISL_UNORM, 0, 4 }, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_A4P4_UNORM_PALETTE0] = { + .format = ISL_FORMAT_A4P4_UNORM_PALETTE0, + .name = "ISL_FORMAT_A4P4_UNORM_PALETTE0", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_UNORM, 0, 4 }, + .l = {}, + .i = {}, + .p = { ISL_UNORM, 4, 4 }, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8_SSCALED] = { + .format = ISL_FORMAT_R8_SSCALED, + .name = "ISL_FORMAT_R8_SSCALED", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SSCALED, 0, 8 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8_USCALED] = { + .format = ISL_FORMAT_R8_USCALED, + .name = "ISL_FORMAT_R8_USCALED", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_USCALED, 0, 8 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_P8_UNORM_PALETTE0] = { + .format = ISL_FORMAT_P8_UNORM_PALETTE0, + .name = "ISL_FORMAT_P8_UNORM_PALETTE0", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = { ISL_UNORM, 0, 8 }, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_L8_UNORM_SRGB] = { + .format = ISL_FORMAT_L8_UNORM_SRGB, + .name = "ISL_FORMAT_L8_UNORM_SRGB", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = { ISL_UNORM, 0, 8 }, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_P8_UNORM_PALETTE1] = { + .format = ISL_FORMAT_P8_UNORM_PALETTE1, + .name = "ISL_FORMAT_P8_UNORM_PALETTE1", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = { ISL_UNORM, 0, 8 }, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_P4A4_UNORM_PALETTE1] = { + .format = ISL_FORMAT_P4A4_UNORM_PALETTE1, + .name = "ISL_FORMAT_P4A4_UNORM_PALETTE1", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_UNORM, 4, 4 }, + .l = {}, + .i = {}, + .p = { ISL_UNORM, 0, 4 }, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_A4P4_UNORM_PALETTE1] = { + .format = ISL_FORMAT_A4P4_UNORM_PALETTE1, + .name = "ISL_FORMAT_A4P4_UNORM_PALETTE1", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = { ISL_UNORM, 0, 4 }, + .l = {}, + .i = {}, + .p = { ISL_UNORM, 4, 4 }, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_Y8_UNORM] = { + .format = ISL_FORMAT_Y8_UNORM, + .name = "ISL_FORMAT_Y8_UNORM", + .bpb = 0, + .bw = 0, + .bh = 0, + .bd = 0, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_YUV, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_L8_UINT] = { + .format = ISL_FORMAT_L8_UINT, + .name = "ISL_FORMAT_L8_UINT", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = { ISL_UINT, 0, 8 }, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_L8_SINT] = { + .format = ISL_FORMAT_L8_SINT, + .name = "ISL_FORMAT_L8_SINT", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = { ISL_SINT, 0, 8 }, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_I8_UINT] = { + .format = ISL_FORMAT_I8_UINT, + .name = "ISL_FORMAT_I8_UINT", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = { ISL_UINT, 0, 8 }, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_I8_SINT] = { + .format = ISL_FORMAT_I8_SINT, + .name = "ISL_FORMAT_I8_SINT", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = { ISL_SINT, 0, 8 }, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_DXT1_RGB_SRGB] = { + .format = ISL_FORMAT_DXT1_RGB_SRGB, + .name = "ISL_FORMAT_DXT1_RGB_SRGB", + .bpb = 64, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 4 }, + .g = { ISL_UNORM, -1, 4 }, + .b = { ISL_UNORM, -1, 4 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_DXT1, + }, + + [ISL_FORMAT_R1_UNORM] = { + .format = ISL_FORMAT_R1_UNORM, + .name = "ISL_FORMAT_R1_UNORM", + .bpb = 1, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 0, 1 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_YCRCB_NORMAL] = { + .format = ISL_FORMAT_YCRCB_NORMAL, + .name = "ISL_FORMAT_YCRCB_NORMAL", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 8 }, + .g = { ISL_UNORM, -1, 8 }, + .b = { ISL_UNORM, -1, 8 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_YUV, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_YCRCB_SWAPUVY] = { + .format = ISL_FORMAT_YCRCB_SWAPUVY, + .name = "ISL_FORMAT_YCRCB_SWAPUVY", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 8 }, + .g = { ISL_UNORM, -1, 8 }, + .b = { ISL_UNORM, -1, 8 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_YUV, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_P2_UNORM_PALETTE0] = { + .format = ISL_FORMAT_P2_UNORM_PALETTE0, + .name = "ISL_FORMAT_P2_UNORM_PALETTE0", + .bpb = 2, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = { ISL_UNORM, 0, 2 }, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_P2_UNORM_PALETTE1] = { + .format = ISL_FORMAT_P2_UNORM_PALETTE1, + .name = "ISL_FORMAT_P2_UNORM_PALETTE1", + .bpb = 2, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = { ISL_UNORM, 0, 2 }, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_BC1_UNORM] = { + .format = ISL_FORMAT_BC1_UNORM, + .name = "ISL_FORMAT_BC1_UNORM", + .bpb = 64, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 4 }, + .g = { ISL_UNORM, -1, 4 }, + .b = { ISL_UNORM, -1, 4 }, + .a = { ISL_UNORM, -1, 4 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_DXT1, + }, + + [ISL_FORMAT_BC2_UNORM] = { + .format = ISL_FORMAT_BC2_UNORM, + .name = "ISL_FORMAT_BC2_UNORM", + .bpb = 128, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 4 }, + .g = { ISL_UNORM, -1, 4 }, + .b = { ISL_UNORM, -1, 4 }, + .a = { ISL_UNORM, -1, 4 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_DXT3, + }, + + [ISL_FORMAT_BC3_UNORM] = { + .format = ISL_FORMAT_BC3_UNORM, + .name = "ISL_FORMAT_BC3_UNORM", + .bpb = 128, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 4 }, + .g = { ISL_UNORM, -1, 4 }, + .b = { ISL_UNORM, -1, 4 }, + .a = { ISL_UNORM, -1, 4 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_DXT5, + }, + + [ISL_FORMAT_BC4_UNORM] = { + .format = ISL_FORMAT_BC4_UNORM, + .name = "ISL_FORMAT_BC4_UNORM", + .bpb = 64, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 8 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_RGTC1, + }, + + [ISL_FORMAT_BC5_UNORM] = { + .format = ISL_FORMAT_BC5_UNORM, + .name = "ISL_FORMAT_BC5_UNORM", + .bpb = 128, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 8 }, + .g = { ISL_UNORM, -1, 8 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_RGTC2, + }, + + [ISL_FORMAT_BC1_UNORM_SRGB] = { + .format = ISL_FORMAT_BC1_UNORM_SRGB, + .name = "ISL_FORMAT_BC1_UNORM_SRGB", + .bpb = 64, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 4 }, + .g = { ISL_UNORM, -1, 4 }, + .b = { ISL_UNORM, -1, 4 }, + .a = { ISL_UNORM, -1, 4 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_DXT1, + }, + + [ISL_FORMAT_BC2_UNORM_SRGB] = { + .format = ISL_FORMAT_BC2_UNORM_SRGB, + .name = "ISL_FORMAT_BC2_UNORM_SRGB", + .bpb = 128, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 4 }, + .g = { ISL_UNORM, -1, 4 }, + .b = { ISL_UNORM, -1, 4 }, + .a = { ISL_UNORM, -1, 4 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_DXT3, + }, + + [ISL_FORMAT_BC3_UNORM_SRGB] = { + .format = ISL_FORMAT_BC3_UNORM_SRGB, + .name = "ISL_FORMAT_BC3_UNORM_SRGB", + .bpb = 128, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 4 }, + .g = { ISL_UNORM, -1, 4 }, + .b = { ISL_UNORM, -1, 4 }, + .a = { ISL_UNORM, -1, 4 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_DXT5, + }, + + [ISL_FORMAT_MONO8] = { + .format = ISL_FORMAT_MONO8, + .name = "ISL_FORMAT_MONO8", + .bpb = 1, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_YCRCB_SWAPUV] = { + .format = ISL_FORMAT_YCRCB_SWAPUV, + .name = "ISL_FORMAT_YCRCB_SWAPUV", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 8 }, + .g = { ISL_UNORM, -1, 8 }, + .b = { ISL_UNORM, -1, 8 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_YUV, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_YCRCB_SWAPY] = { + .format = ISL_FORMAT_YCRCB_SWAPY, + .name = "ISL_FORMAT_YCRCB_SWAPY", + .bpb = 16, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 8 }, + .g = { ISL_UNORM, -1, 8 }, + .b = { ISL_UNORM, -1, 8 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_YUV, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_DXT1_RGB] = { + .format = ISL_FORMAT_DXT1_RGB, + .name = "ISL_FORMAT_DXT1_RGB", + .bpb = 64, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 4 }, + .g = { ISL_UNORM, -1, 4 }, + .b = { ISL_UNORM, -1, 4 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_DXT1, + }, + + [ISL_FORMAT_FXT1] = { + .format = ISL_FORMAT_FXT1, + .name = "ISL_FORMAT_FXT1", + .bpb = 128, + .bw = 8, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 4 }, + .g = { ISL_UNORM, -1, 4 }, + .b = { ISL_UNORM, -1, 4 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_FXT1, + }, + + [ISL_FORMAT_R8G8B8_UNORM] = { + .format = ISL_FORMAT_R8G8B8_UNORM, + .name = "ISL_FORMAT_R8G8B8_UNORM", + .bpb = 24, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 0, 8 }, + .g = { ISL_UNORM, 8, 8 }, + .b = { ISL_UNORM, 16, 8 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8B8_SNORM] = { + .format = ISL_FORMAT_R8G8B8_SNORM, + .name = "ISL_FORMAT_R8G8B8_SNORM", + .bpb = 24, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 0, 8 }, + .g = { ISL_SNORM, 8, 8 }, + .b = { ISL_SNORM, 16, 8 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8B8_SSCALED] = { + .format = ISL_FORMAT_R8G8B8_SSCALED, + .name = "ISL_FORMAT_R8G8B8_SSCALED", + .bpb = 24, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SSCALED, 0, 8 }, + .g = { ISL_SSCALED, 8, 8 }, + .b = { ISL_SSCALED, 16, 8 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8B8_USCALED] = { + .format = ISL_FORMAT_R8G8B8_USCALED, + .name = "ISL_FORMAT_R8G8B8_USCALED", + .bpb = 24, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_USCALED, 0, 8 }, + .g = { ISL_USCALED, 8, 8 }, + .b = { ISL_USCALED, 16, 8 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R64G64B64A64_FLOAT] = { + .format = ISL_FORMAT_R64G64B64A64_FLOAT, + .name = "ISL_FORMAT_R64G64B64A64_FLOAT", + .bpb = 256, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 0, 64 }, + .g = { ISL_SFLOAT, 64, 64 }, + .b = { ISL_SFLOAT, 128, 64 }, + .a = { ISL_SFLOAT, 192, 64 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R64G64B64_FLOAT] = { + .format = ISL_FORMAT_R64G64B64_FLOAT, + .name = "ISL_FORMAT_R64G64B64_FLOAT", + .bpb = 196, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 0, 64 }, + .g = { ISL_SFLOAT, 64, 64 }, + .b = { ISL_SFLOAT, 128, 64 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_BC4_SNORM] = { + .format = ISL_FORMAT_BC4_SNORM, + .name = "ISL_FORMAT_BC4_SNORM", + .bpb = 64, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_SNORM, -1, 8 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_RGTC1, + }, + + [ISL_FORMAT_BC5_SNORM] = { + .format = ISL_FORMAT_BC5_SNORM, + .name = "ISL_FORMAT_BC5_SNORM", + .bpb = 128, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_SNORM, -1, 8 }, + .g = { ISL_SNORM, -1, 8 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_RGTC2, + }, + + [ISL_FORMAT_R16G16B16_FLOAT] = { + .format = ISL_FORMAT_R16G16B16_FLOAT, + .name = "ISL_FORMAT_R16G16B16_FLOAT", + .bpb = 48, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, 0, 16 }, + .g = { ISL_SFLOAT, 16, 16 }, + .b = { ISL_SFLOAT, 32, 16 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16B16_UNORM] = { + .format = ISL_FORMAT_R16G16B16_UNORM, + .name = "ISL_FORMAT_R16G16B16_UNORM", + .bpb = 48, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 0, 16 }, + .g = { ISL_UNORM, 16, 16 }, + .b = { ISL_UNORM, 32, 16 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16B16_SNORM] = { + .format = ISL_FORMAT_R16G16B16_SNORM, + .name = "ISL_FORMAT_R16G16B16_SNORM", + .bpb = 48, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 0, 16 }, + .g = { ISL_SNORM, 16, 16 }, + .b = { ISL_SNORM, 32, 16 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16B16_SSCALED] = { + .format = ISL_FORMAT_R16G16B16_SSCALED, + .name = "ISL_FORMAT_R16G16B16_SSCALED", + .bpb = 48, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SSCALED, 0, 16 }, + .g = { ISL_SSCALED, 16, 16 }, + .b = { ISL_SSCALED, 32, 16 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16B16_USCALED] = { + .format = ISL_FORMAT_R16G16B16_USCALED, + .name = "ISL_FORMAT_R16G16B16_USCALED", + .bpb = 48, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_USCALED, 0, 16 }, + .g = { ISL_USCALED, 16, 16 }, + .b = { ISL_USCALED, 32, 16 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_BC6H_SF16] = { + .format = ISL_FORMAT_BC6H_SF16, + .name = "ISL_FORMAT_BC6H_SF16", + .bpb = 128, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, -1, 16 }, + .g = { ISL_SFLOAT, -1, 16 }, + .b = { ISL_SFLOAT, -1, 16 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_BPTC, + }, + + [ISL_FORMAT_BC7_UNORM] = { + .format = ISL_FORMAT_BC7_UNORM, + .name = "ISL_FORMAT_BC7_UNORM", + .bpb = 128, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 8 }, + .g = { ISL_UNORM, -1, 8 }, + .b = { ISL_UNORM, -1, 8 }, + .a = { ISL_UNORM, -1, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_BPTC, + }, + + [ISL_FORMAT_BC7_UNORM_SRGB] = { + .format = ISL_FORMAT_BC7_UNORM_SRGB, + .name = "ISL_FORMAT_BC7_UNORM_SRGB", + .bpb = 128, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 8 }, + .g = { ISL_UNORM, -1, 8 }, + .b = { ISL_UNORM, -1, 8 }, + .a = { ISL_UNORM, -1, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_BPTC, + }, + + [ISL_FORMAT_BC6H_UF16] = { + .format = ISL_FORMAT_BC6H_UF16, + .name = "ISL_FORMAT_BC6H_UF16", + .bpb = 128, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UFLOAT, -1, 16 }, + .g = { ISL_UFLOAT, -1, 16 }, + .b = { ISL_UFLOAT, -1, 16 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_BPTC, + }, + + [ISL_FORMAT_PLANAR_420_8] = { + .format = ISL_FORMAT_PLANAR_420_8, + .name = "ISL_FORMAT_PLANAR_420_8", + .bpb = 0, + .bw = 0, + .bh = 0, + .bd = 0, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_YUV, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8B8_UNORM_SRGB] = { + .format = ISL_FORMAT_R8G8B8_UNORM_SRGB, + .name = "ISL_FORMAT_R8G8B8_UNORM_SRGB", + .bpb = 24, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UNORM, 0, 8 }, + .g = { ISL_UNORM, 8, 8 }, + .b = { ISL_UNORM, 16, 8 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_ETC1_RGB8] = { + .format = ISL_FORMAT_ETC1_RGB8, + .name = "ISL_FORMAT_ETC1_RGB8", + .bpb = 64, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 8 }, + .g = { ISL_UNORM, -1, 8 }, + .b = { ISL_UNORM, -1, 8 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ETC1, + }, + + [ISL_FORMAT_ETC2_RGB8] = { + .format = ISL_FORMAT_ETC2_RGB8, + .name = "ISL_FORMAT_ETC2_RGB8", + .bpb = 64, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 8 }, + .g = { ISL_UNORM, -1, 8 }, + .b = { ISL_UNORM, -1, 8 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ETC2, + }, + + [ISL_FORMAT_EAC_R11] = { + .format = ISL_FORMAT_EAC_R11, + .name = "ISL_FORMAT_EAC_R11", + .bpb = 64, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 11 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ETC2, + }, + + [ISL_FORMAT_EAC_RG11] = { + .format = ISL_FORMAT_EAC_RG11, + .name = "ISL_FORMAT_EAC_RG11", + .bpb = 128, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 11 }, + .g = { ISL_UNORM, -1, 11 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ETC2, + }, + + [ISL_FORMAT_EAC_SIGNED_R11] = { + .format = ISL_FORMAT_EAC_SIGNED_R11, + .name = "ISL_FORMAT_EAC_SIGNED_R11", + .bpb = 64, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_SNORM, -1, 11 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ETC2, + }, + + [ISL_FORMAT_EAC_SIGNED_RG11] = { + .format = ISL_FORMAT_EAC_SIGNED_RG11, + .name = "ISL_FORMAT_EAC_SIGNED_RG11", + .bpb = 128, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_SNORM, -1, 11 }, + .g = { ISL_SNORM, -1, 11 }, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ETC2, + }, + + [ISL_FORMAT_ETC2_SRGB8] = { + .format = ISL_FORMAT_ETC2_SRGB8, + .name = "ISL_FORMAT_ETC2_SRGB8", + .bpb = 64, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 8 }, + .g = { ISL_UNORM, -1, 8 }, + .b = { ISL_UNORM, -1, 8 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_ETC2, + }, + + [ISL_FORMAT_R16G16B16_UINT] = { + .format = ISL_FORMAT_R16G16B16_UINT, + .name = "ISL_FORMAT_R16G16B16_UINT", + .bpb = 48, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UINT, 0, 16 }, + .g = { ISL_UINT, 16, 16 }, + .b = { ISL_UINT, 32, 16 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R16G16B16_SINT] = { + .format = ISL_FORMAT_R16G16B16_SINT, + .name = "ISL_FORMAT_R16G16B16_SINT", + .bpb = 48, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SINT, 0, 16 }, + .g = { ISL_SINT, 16, 16 }, + .b = { ISL_SINT, 32, 16 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R32_SFIXED] = { + .format = ISL_FORMAT_R32_SFIXED, + .name = "ISL_FORMAT_R32_SFIXED", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SFIXED, 0, 16 }, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R10G10B10A2_SNORM] = { + .format = ISL_FORMAT_R10G10B10A2_SNORM, + .name = "ISL_FORMAT_R10G10B10A2_SNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 0, 10 }, + .g = { ISL_SNORM, 10, 10 }, + .b = { ISL_SNORM, 20, 10 }, + .a = { ISL_SNORM, 30, 2 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R10G10B10A2_USCALED] = { + .format = ISL_FORMAT_R10G10B10A2_USCALED, + .name = "ISL_FORMAT_R10G10B10A2_USCALED", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_USCALED, 0, 10 }, + .g = { ISL_USCALED, 10, 10 }, + .b = { ISL_USCALED, 20, 10 }, + .a = { ISL_USCALED, 30, 2 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R10G10B10A2_SSCALED] = { + .format = ISL_FORMAT_R10G10B10A2_SSCALED, + .name = "ISL_FORMAT_R10G10B10A2_SSCALED", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SSCALED, 0, 10 }, + .g = { ISL_SSCALED, 10, 10 }, + .b = { ISL_SSCALED, 20, 10 }, + .a = { ISL_SSCALED, 30, 2 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R10G10B10A2_SINT] = { + .format = ISL_FORMAT_R10G10B10A2_SINT, + .name = "ISL_FORMAT_R10G10B10A2_SINT", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SINT, 0, 10 }, + .g = { ISL_SINT, 10, 10 }, + .b = { ISL_SINT, 20, 10 }, + .a = { ISL_SINT, 30, 2 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B10G10R10A2_SNORM] = { + .format = ISL_FORMAT_B10G10R10A2_SNORM, + .name = "ISL_FORMAT_B10G10R10A2_SNORM", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SNORM, 0, 10 }, + .g = { ISL_SNORM, 10, 10 }, + .b = { ISL_SNORM, 20, 10 }, + .a = { ISL_SNORM, 30, 2 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B10G10R10A2_USCALED] = { + .format = ISL_FORMAT_B10G10R10A2_USCALED, + .name = "ISL_FORMAT_B10G10R10A2_USCALED", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_USCALED, 0, 10 }, + .g = { ISL_USCALED, 10, 10 }, + .b = { ISL_USCALED, 20, 10 }, + .a = { ISL_USCALED, 30, 2 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B10G10R10A2_SSCALED] = { + .format = ISL_FORMAT_B10G10R10A2_SSCALED, + .name = "ISL_FORMAT_B10G10R10A2_SSCALED", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SSCALED, 0, 10 }, + .g = { ISL_SSCALED, 10, 10 }, + .b = { ISL_SSCALED, 20, 10 }, + .a = { ISL_SSCALED, 30, 2 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B10G10R10A2_UINT] = { + .format = ISL_FORMAT_B10G10R10A2_UINT, + .name = "ISL_FORMAT_B10G10R10A2_UINT", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UINT, 0, 10 }, + .g = { ISL_UINT, 10, 10 }, + .b = { ISL_UINT, 20, 10 }, + .a = { ISL_UINT, 30, 2 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_B10G10R10A2_SINT] = { + .format = ISL_FORMAT_B10G10R10A2_SINT, + .name = "ISL_FORMAT_B10G10R10A2_SINT", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SINT, 0, 10 }, + .g = { ISL_SINT, 10, 10 }, + .b = { ISL_SINT, 20, 10 }, + .a = { ISL_SINT, 30, 2 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R64G64B64A64_PASSTHRU] = { + .format = ISL_FORMAT_R64G64B64A64_PASSTHRU, + .name = "ISL_FORMAT_R64G64B64A64_PASSTHRU", + .bpb = 256, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_RAW, 0, 64 }, + .g = { ISL_RAW, 64, 64 }, + .b = { ISL_RAW, 128, 64 }, + .a = { ISL_RAW, 192, 64 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R64G64B64_PASSTHRU] = { + .format = ISL_FORMAT_R64G64B64_PASSTHRU, + .name = "ISL_FORMAT_R64G64B64_PASSTHRU", + .bpb = 192, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_RAW, 0, 64 }, + .g = { ISL_RAW, 64, 64 }, + .b = { ISL_RAW, 128, 64 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_ETC2_RGB8_PTA] = { + .format = ISL_FORMAT_ETC2_RGB8_PTA, + .name = "ISL_FORMAT_ETC2_RGB8_PTA", + .bpb = 64, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 8 }, + .g = { ISL_UNORM, -1, 8 }, + .b = { ISL_UNORM, -1, 8 }, + .a = { ISL_UNORM, -1, 1 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ETC2, + }, + + [ISL_FORMAT_ETC2_SRGB8_PTA] = { + .format = ISL_FORMAT_ETC2_SRGB8_PTA, + .name = "ISL_FORMAT_ETC2_SRGB8_PTA", + .bpb = 64, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 8 }, + .g = { ISL_UNORM, -1, 8 }, + .b = { ISL_UNORM, -1, 8 }, + .a = { ISL_UNORM, -1, 1 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_ETC2, + }, + + [ISL_FORMAT_ETC2_EAC_RGBA8] = { + .format = ISL_FORMAT_ETC2_EAC_RGBA8, + .name = "ISL_FORMAT_ETC2_EAC_RGBA8", + .bpb = 128, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 8 }, + .g = { ISL_UNORM, -1, 8 }, + .b = { ISL_UNORM, -1, 8 }, + .a = { ISL_UNORM, -1, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ETC2, + }, + + [ISL_FORMAT_ETC2_EAC_SRGB8_A8] = { + .format = ISL_FORMAT_ETC2_EAC_SRGB8_A8, + .name = "ISL_FORMAT_ETC2_EAC_SRGB8_A8", + .bpb = 128, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 8 }, + .g = { ISL_UNORM, -1, 8 }, + .b = { ISL_UNORM, -1, 8 }, + .a = { ISL_UNORM, -1, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_ETC2, + }, + + [ISL_FORMAT_R8G8B8_UINT] = { + .format = ISL_FORMAT_R8G8B8_UINT, + .name = "ISL_FORMAT_R8G8B8_UINT", + .bpb = 24, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_UINT, 0, 8 }, + .g = { ISL_UINT, 8, 8 }, + .b = { ISL_UINT, 16, 8 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_R8G8B8_SINT] = { + .format = ISL_FORMAT_R8G8B8_SINT, + .name = "ISL_FORMAT_R8G8B8_SINT", + .bpb = 24, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = { ISL_SINT, 0, 8 }, + .g = { ISL_SINT, 8, 8 }, + .b = { ISL_SINT, 16, 8 }, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_RAW] = { + .format = ISL_FORMAT_RAW, + .name = "ISL_FORMAT_RAW", + .bpb = 0, + .bw = 0, + .bh = 0, + .bd = 0, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_NONE, + }, + + [ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB] = { + .format = ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB, + .name = "ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB", + .bpb = 128, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 8 }, + .g = { ISL_UNORM, -1, 8 }, + .b = { ISL_UNORM, -1, 8 }, + .a = { ISL_UNORM, -1, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB] = { + .format = ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB, + .name = "ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB", + .bpb = 128, + .bw = 5, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 8 }, + .g = { ISL_UNORM, -1, 8 }, + .b = { ISL_UNORM, -1, 8 }, + .a = { ISL_UNORM, -1, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB] = { + .format = ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB, + .name = "ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB", + .bpb = 128, + .bw = 5, + .bh = 5, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 8 }, + .g = { ISL_UNORM, -1, 8 }, + .b = { ISL_UNORM, -1, 8 }, + .a = { ISL_UNORM, -1, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB] = { + .format = ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB, + .name = "ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB", + .bpb = 128, + .bw = 6, + .bh = 5, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 8 }, + .g = { ISL_UNORM, -1, 8 }, + .b = { ISL_UNORM, -1, 8 }, + .a = { ISL_UNORM, -1, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB] = { + .format = ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB, + .name = "ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB", + .bpb = 128, + .bw = 6, + .bh = 6, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 8 }, + .g = { ISL_UNORM, -1, 8 }, + .b = { ISL_UNORM, -1, 8 }, + .a = { ISL_UNORM, -1, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB] = { + .format = ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB, + .name = "ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB", + .bpb = 128, + .bw = 8, + .bh = 5, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 8 }, + .g = { ISL_UNORM, -1, 8 }, + .b = { ISL_UNORM, -1, 8 }, + .a = { ISL_UNORM, -1, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB] = { + .format = ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB, + .name = "ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB", + .bpb = 128, + .bw = 8, + .bh = 6, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 8 }, + .g = { ISL_UNORM, -1, 8 }, + .b = { ISL_UNORM, -1, 8 }, + .a = { ISL_UNORM, -1, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB] = { + .format = ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB, + .name = "ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB", + .bpb = 128, + .bw = 8, + .bh = 8, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 8 }, + .g = { ISL_UNORM, -1, 8 }, + .b = { ISL_UNORM, -1, 8 }, + .a = { ISL_UNORM, -1, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB] = { + .format = ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB, + .name = "ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB", + .bpb = 128, + .bw = 10, + .bh = 5, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 8 }, + .g = { ISL_UNORM, -1, 8 }, + .b = { ISL_UNORM, -1, 8 }, + .a = { ISL_UNORM, -1, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB] = { + .format = ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB, + .name = "ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB", + .bpb = 128, + .bw = 10, + .bh = 6, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 8 }, + .g = { ISL_UNORM, -1, 8 }, + .b = { ISL_UNORM, -1, 8 }, + .a = { ISL_UNORM, -1, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB] = { + .format = ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB, + .name = "ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB", + .bpb = 128, + .bw = 10, + .bh = 8, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 8 }, + .g = { ISL_UNORM, -1, 8 }, + .b = { ISL_UNORM, -1, 8 }, + .a = { ISL_UNORM, -1, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB] = { + .format = ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB, + .name = "ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB", + .bpb = 128, + .bw = 10, + .bh = 10, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 8 }, + .g = { ISL_UNORM, -1, 8 }, + .b = { ISL_UNORM, -1, 8 }, + .a = { ISL_UNORM, -1, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB] = { + .format = ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB, + .name = "ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB", + .bpb = 128, + .bw = 12, + .bh = 10, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 8 }, + .g = { ISL_UNORM, -1, 8 }, + .b = { ISL_UNORM, -1, 8 }, + .a = { ISL_UNORM, -1, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB] = { + .format = ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB, + .name = "ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB", + .bpb = 128, + .bw = 12, + .bh = 12, + .bd = 1, + .channels = { + .r = { ISL_UNORM, -1, 8 }, + .g = { ISL_UNORM, -1, 8 }, + .b = { ISL_UNORM, -1, 8 }, + .a = { ISL_UNORM, -1, 8 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_SRGB, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16] = { + .format = ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16, + .name = "ISL_FORMAT_ASTC_LDR_2D_4X4_FLT16", + .bpb = 128, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, -1, 16 }, + .g = { ISL_SFLOAT, -1, 16 }, + .b = { ISL_SFLOAT, -1, 16 }, + .a = { ISL_SFLOAT, -1, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16] = { + .format = ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16, + .name = "ISL_FORMAT_ASTC_LDR_2D_5X4_FLT16", + .bpb = 128, + .bw = 5, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, -1, 16 }, + .g = { ISL_SFLOAT, -1, 16 }, + .b = { ISL_SFLOAT, -1, 16 }, + .a = { ISL_SFLOAT, -1, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16] = { + .format = ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16, + .name = "ISL_FORMAT_ASTC_LDR_2D_5X5_FLT16", + .bpb = 128, + .bw = 5, + .bh = 5, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, -1, 16 }, + .g = { ISL_SFLOAT, -1, 16 }, + .b = { ISL_SFLOAT, -1, 16 }, + .a = { ISL_SFLOAT, -1, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16] = { + .format = ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16, + .name = "ISL_FORMAT_ASTC_LDR_2D_6X5_FLT16", + .bpb = 128, + .bw = 6, + .bh = 5, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, -1, 16 }, + .g = { ISL_SFLOAT, -1, 16 }, + .b = { ISL_SFLOAT, -1, 16 }, + .a = { ISL_SFLOAT, -1, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16] = { + .format = ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16, + .name = "ISL_FORMAT_ASTC_LDR_2D_6X6_FLT16", + .bpb = 128, + .bw = 6, + .bh = 6, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, -1, 16 }, + .g = { ISL_SFLOAT, -1, 16 }, + .b = { ISL_SFLOAT, -1, 16 }, + .a = { ISL_SFLOAT, -1, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16] = { + .format = ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16, + .name = "ISL_FORMAT_ASTC_LDR_2D_8X5_FLT16", + .bpb = 128, + .bw = 8, + .bh = 5, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, -1, 16 }, + .g = { ISL_SFLOAT, -1, 16 }, + .b = { ISL_SFLOAT, -1, 16 }, + .a = { ISL_SFLOAT, -1, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16] = { + .format = ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16, + .name = "ISL_FORMAT_ASTC_LDR_2D_8X6_FLT16", + .bpb = 128, + .bw = 8, + .bh = 6, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, -1, 16 }, + .g = { ISL_SFLOAT, -1, 16 }, + .b = { ISL_SFLOAT, -1, 16 }, + .a = { ISL_SFLOAT, -1, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16] = { + .format = ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16, + .name = "ISL_FORMAT_ASTC_LDR_2D_8X8_FLT16", + .bpb = 128, + .bw = 8, + .bh = 8, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, -1, 16 }, + .g = { ISL_SFLOAT, -1, 16 }, + .b = { ISL_SFLOAT, -1, 16 }, + .a = { ISL_SFLOAT, -1, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16] = { + .format = ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16, + .name = "ISL_FORMAT_ASTC_LDR_2D_10X5_FLT16", + .bpb = 128, + .bw = 10, + .bh = 5, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, -1, 16 }, + .g = { ISL_SFLOAT, -1, 16 }, + .b = { ISL_SFLOAT, -1, 16 }, + .a = { ISL_SFLOAT, -1, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16] = { + .format = ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16, + .name = "ISL_FORMAT_ASTC_LDR_2D_10X6_FLT16", + .bpb = 128, + .bw = 10, + .bh = 6, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, -1, 16 }, + .g = { ISL_SFLOAT, -1, 16 }, + .b = { ISL_SFLOAT, -1, 16 }, + .a = { ISL_SFLOAT, -1, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16] = { + .format = ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16, + .name = "ISL_FORMAT_ASTC_LDR_2D_10X8_FLT16", + .bpb = 128, + .bw = 10, + .bh = 8, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, -1, 16 }, + .g = { ISL_SFLOAT, -1, 16 }, + .b = { ISL_SFLOAT, -1, 16 }, + .a = { ISL_SFLOAT, -1, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16] = { + .format = ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16, + .name = "ISL_FORMAT_ASTC_LDR_2D_10X10_FLT16", + .bpb = 128, + .bw = 10, + .bh = 10, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, -1, 16 }, + .g = { ISL_SFLOAT, -1, 16 }, + .b = { ISL_SFLOAT, -1, 16 }, + .a = { ISL_SFLOAT, -1, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16] = { + .format = ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16, + .name = "ISL_FORMAT_ASTC_LDR_2D_12X10_FLT16", + .bpb = 128, + .bw = 12, + .bh = 10, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, -1, 16 }, + .g = { ISL_SFLOAT, -1, 16 }, + .b = { ISL_SFLOAT, -1, 16 }, + .a = { ISL_SFLOAT, -1, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16] = { + .format = ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16, + .name = "ISL_FORMAT_ASTC_LDR_2D_12X12_FLT16", + .bpb = 128, + .bw = 12, + .bh = 12, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, -1, 16 }, + .g = { ISL_SFLOAT, -1, 16 }, + .b = { ISL_SFLOAT, -1, 16 }, + .a = { ISL_SFLOAT, -1, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_HDR_2D_4X4_FLT16] = { + .format = ISL_FORMAT_ASTC_HDR_2D_4X4_FLT16, + .name = "ISL_FORMAT_ASTC_HDR_2D_4X4_FLT16", + .bpb = 128, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, -1, 16 }, + .g = { ISL_SFLOAT, -1, 16 }, + .b = { ISL_SFLOAT, -1, 16 }, + .a = { ISL_SFLOAT, -1, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_HDR_2D_5X4_FLT16] = { + .format = ISL_FORMAT_ASTC_HDR_2D_5X4_FLT16, + .name = "ISL_FORMAT_ASTC_HDR_2D_5X4_FLT16", + .bpb = 128, + .bw = 5, + .bh = 4, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, -1, 16 }, + .g = { ISL_SFLOAT, -1, 16 }, + .b = { ISL_SFLOAT, -1, 16 }, + .a = { ISL_SFLOAT, -1, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_HDR_2D_5X5_FLT16] = { + .format = ISL_FORMAT_ASTC_HDR_2D_5X5_FLT16, + .name = "ISL_FORMAT_ASTC_HDR_2D_5X5_FLT16", + .bpb = 128, + .bw = 5, + .bh = 5, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, -1, 16 }, + .g = { ISL_SFLOAT, -1, 16 }, + .b = { ISL_SFLOAT, -1, 16 }, + .a = { ISL_SFLOAT, -1, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_HDR_2D_6X5_FLT16] = { + .format = ISL_FORMAT_ASTC_HDR_2D_6X5_FLT16, + .name = "ISL_FORMAT_ASTC_HDR_2D_6X5_FLT16", + .bpb = 128, + .bw = 6, + .bh = 5, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, -1, 16 }, + .g = { ISL_SFLOAT, -1, 16 }, + .b = { ISL_SFLOAT, -1, 16 }, + .a = { ISL_SFLOAT, -1, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_HDR_2D_6X6_FLT16] = { + .format = ISL_FORMAT_ASTC_HDR_2D_6X6_FLT16, + .name = "ISL_FORMAT_ASTC_HDR_2D_6X6_FLT16", + .bpb = 128, + .bw = 6, + .bh = 6, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, -1, 16 }, + .g = { ISL_SFLOAT, -1, 16 }, + .b = { ISL_SFLOAT, -1, 16 }, + .a = { ISL_SFLOAT, -1, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_HDR_2D_8X5_FLT16] = { + .format = ISL_FORMAT_ASTC_HDR_2D_8X5_FLT16, + .name = "ISL_FORMAT_ASTC_HDR_2D_8X5_FLT16", + .bpb = 128, + .bw = 8, + .bh = 5, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, -1, 16 }, + .g = { ISL_SFLOAT, -1, 16 }, + .b = { ISL_SFLOAT, -1, 16 }, + .a = { ISL_SFLOAT, -1, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_HDR_2D_8X6_FLT16] = { + .format = ISL_FORMAT_ASTC_HDR_2D_8X6_FLT16, + .name = "ISL_FORMAT_ASTC_HDR_2D_8X6_FLT16", + .bpb = 128, + .bw = 8, + .bh = 6, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, -1, 16 }, + .g = { ISL_SFLOAT, -1, 16 }, + .b = { ISL_SFLOAT, -1, 16 }, + .a = { ISL_SFLOAT, -1, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_HDR_2D_8X8_FLT16] = { + .format = ISL_FORMAT_ASTC_HDR_2D_8X8_FLT16, + .name = "ISL_FORMAT_ASTC_HDR_2D_8X8_FLT16", + .bpb = 128, + .bw = 8, + .bh = 8, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, -1, 16 }, + .g = { ISL_SFLOAT, -1, 16 }, + .b = { ISL_SFLOAT, -1, 16 }, + .a = { ISL_SFLOAT, -1, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_HDR_2D_10X5_FLT16] = { + .format = ISL_FORMAT_ASTC_HDR_2D_10X5_FLT16, + .name = "ISL_FORMAT_ASTC_HDR_2D_10X5_FLT16", + .bpb = 128, + .bw = 10, + .bh = 5, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, -1, 16 }, + .g = { ISL_SFLOAT, -1, 16 }, + .b = { ISL_SFLOAT, -1, 16 }, + .a = { ISL_SFLOAT, -1, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_HDR_2D_10X6_FLT16] = { + .format = ISL_FORMAT_ASTC_HDR_2D_10X6_FLT16, + .name = "ISL_FORMAT_ASTC_HDR_2D_10X6_FLT16", + .bpb = 128, + .bw = 10, + .bh = 6, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, -1, 16 }, + .g = { ISL_SFLOAT, -1, 16 }, + .b = { ISL_SFLOAT, -1, 16 }, + .a = { ISL_SFLOAT, -1, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_HDR_2D_10X8_FLT16] = { + .format = ISL_FORMAT_ASTC_HDR_2D_10X8_FLT16, + .name = "ISL_FORMAT_ASTC_HDR_2D_10X8_FLT16", + .bpb = 128, + .bw = 10, + .bh = 8, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, -1, 16 }, + .g = { ISL_SFLOAT, -1, 16 }, + .b = { ISL_SFLOAT, -1, 16 }, + .a = { ISL_SFLOAT, -1, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_HDR_2D_10X10_FLT16] = { + .format = ISL_FORMAT_ASTC_HDR_2D_10X10_FLT16, + .name = "ISL_FORMAT_ASTC_HDR_2D_10X10_FLT16", + .bpb = 128, + .bw = 10, + .bh = 10, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, -1, 16 }, + .g = { ISL_SFLOAT, -1, 16 }, + .b = { ISL_SFLOAT, -1, 16 }, + .a = { ISL_SFLOAT, -1, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_HDR_2D_12X10_FLT16] = { + .format = ISL_FORMAT_ASTC_HDR_2D_12X10_FLT16, + .name = "ISL_FORMAT_ASTC_HDR_2D_12X10_FLT16", + .bpb = 128, + .bw = 12, + .bh = 10, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, -1, 16 }, + .g = { ISL_SFLOAT, -1, 16 }, + .b = { ISL_SFLOAT, -1, 16 }, + .a = { ISL_SFLOAT, -1, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_ASTC_HDR_2D_12X12_FLT16] = { + .format = ISL_FORMAT_ASTC_HDR_2D_12X12_FLT16, + .name = "ISL_FORMAT_ASTC_HDR_2D_12X12_FLT16", + .bpb = 128, + .bw = 12, + .bh = 12, + .bd = 1, + .channels = { + .r = { ISL_SFLOAT, -1, 16 }, + .g = { ISL_SFLOAT, -1, 16 }, + .b = { ISL_SFLOAT, -1, 16 }, + .a = { ISL_SFLOAT, -1, 16 }, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_LINEAR, + .txc = ISL_TXC_ASTC, + }, + + [ISL_FORMAT_HIZ] = { + .format = ISL_FORMAT_HIZ, + .name = "ISL_FORMAT_HIZ", + .bpb = 128, + .bw = 8, + .bh = 4, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_HIZ, + }, + + [ISL_FORMAT_MCS_2X] = { + .format = ISL_FORMAT_MCS_2X, + .name = "ISL_FORMAT_MCS_2X", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_MCS, + }, + + [ISL_FORMAT_MCS_4X] = { + .format = ISL_FORMAT_MCS_4X, + .name = "ISL_FORMAT_MCS_4X", + .bpb = 8, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_MCS, + }, + + [ISL_FORMAT_MCS_8X] = { + .format = ISL_FORMAT_MCS_8X, + .name = "ISL_FORMAT_MCS_8X", + .bpb = 32, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_MCS, + }, + + [ISL_FORMAT_MCS_16X] = { + .format = ISL_FORMAT_MCS_16X, + .name = "ISL_FORMAT_MCS_16X", + .bpb = 64, + .bw = 1, + .bh = 1, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_MCS, + }, + + [ISL_FORMAT_GEN7_CCS_32BPP_X] = { + .format = ISL_FORMAT_GEN7_CCS_32BPP_X, + .name = "ISL_FORMAT_GEN7_CCS_32BPP_X", + .bpb = 1, + .bw = 16, + .bh = 2, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_CCS, + }, + + [ISL_FORMAT_GEN7_CCS_64BPP_X] = { + .format = ISL_FORMAT_GEN7_CCS_64BPP_X, + .name = "ISL_FORMAT_GEN7_CCS_64BPP_X", + .bpb = 1, + .bw = 8, + .bh = 2, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_CCS, + }, + + [ISL_FORMAT_GEN7_CCS_128BPP_X] = { + .format = ISL_FORMAT_GEN7_CCS_128BPP_X, + .name = "ISL_FORMAT_GEN7_CCS_128BPP_X", + .bpb = 1, + .bw = 4, + .bh = 2, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_CCS, + }, + + [ISL_FORMAT_GEN7_CCS_32BPP_Y] = { + .format = ISL_FORMAT_GEN7_CCS_32BPP_Y, + .name = "ISL_FORMAT_GEN7_CCS_32BPP_Y", + .bpb = 1, + .bw = 8, + .bh = 4, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_CCS, + }, + + [ISL_FORMAT_GEN7_CCS_64BPP_Y] = { + .format = ISL_FORMAT_GEN7_CCS_64BPP_Y, + .name = "ISL_FORMAT_GEN7_CCS_64BPP_Y", + .bpb = 1, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_CCS, + }, + + [ISL_FORMAT_GEN7_CCS_128BPP_Y] = { + .format = ISL_FORMAT_GEN7_CCS_128BPP_Y, + .name = "ISL_FORMAT_GEN7_CCS_128BPP_Y", + .bpb = 1, + .bw = 2, + .bh = 4, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_CCS, + }, + + [ISL_FORMAT_GEN9_CCS_32BPP] = { + .format = ISL_FORMAT_GEN9_CCS_32BPP, + .name = "ISL_FORMAT_GEN9_CCS_32BPP", + .bpb = 2, + .bw = 8, + .bh = 4, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_CCS, + }, + + [ISL_FORMAT_GEN9_CCS_64BPP] = { + .format = ISL_FORMAT_GEN9_CCS_64BPP, + .name = "ISL_FORMAT_GEN9_CCS_64BPP", + .bpb = 2, + .bw = 4, + .bh = 4, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_CCS, + }, + + [ISL_FORMAT_GEN9_CCS_128BPP] = { + .format = ISL_FORMAT_GEN9_CCS_128BPP, + .name = "ISL_FORMAT_GEN9_CCS_128BPP", + .bpb = 2, + .bw = 2, + .bh = 4, + .bd = 1, + .channels = { + .r = {}, + .g = {}, + .b = {}, + .a = {}, + .l = {}, + .i = {}, + .p = {}, + }, + .colorspace = ISL_COLORSPACE_NONE, + .txc = ISL_TXC_CCS, + }, + +}; + +bool +isl_format_is_valid(enum isl_format format) +{ + if (format >= sizeof(isl_format_layouts) / sizeof(isl_format_layouts[0])) + return false; + return isl_format_layouts[format].name; +} + +enum isl_format +isl_format_srgb_to_linear(enum isl_format format) +{ + switch (format) { + case ISL_FORMAT_B8G8R8A8_UNORM_SRGB: + return ISL_FORMAT_B8G8R8A8_UNORM; + case ISL_FORMAT_R10G10B10A2_UNORM_SRGB: + return ISL_FORMAT_R10G10B10A2_UNORM; + case ISL_FORMAT_R8G8B8A8_UNORM_SRGB: + return ISL_FORMAT_R8G8B8A8_UNORM; + case ISL_FORMAT_B10G10R10A2_UNORM_SRGB: + return ISL_FORMAT_B10G10R10A2_UNORM; + case ISL_FORMAT_B8G8R8X8_UNORM_SRGB: + return ISL_FORMAT_B8G8R8X8_UNORM; + case ISL_FORMAT_R8G8B8X8_UNORM_SRGB: + return ISL_FORMAT_R8G8B8X8_UNORM; + case ISL_FORMAT_B5G6R5_UNORM_SRGB: + return ISL_FORMAT_B5G6R5_UNORM; + case ISL_FORMAT_B5G5R5A1_UNORM_SRGB: + return ISL_FORMAT_B5G5R5A1_UNORM; + case ISL_FORMAT_B4G4R4A4_UNORM_SRGB: + return ISL_FORMAT_B4G4R4A4_UNORM; + case ISL_FORMAT_L8A8_UNORM_SRGB: + return ISL_FORMAT_L8A8_UNORM; + case ISL_FORMAT_B5G5R5X1_UNORM_SRGB: + return ISL_FORMAT_B5G5R5X1_UNORM; + case ISL_FORMAT_L8_UNORM_SRGB: + return ISL_FORMAT_L8_UNORM; + case ISL_FORMAT_DXT1_RGB_SRGB: + return ISL_FORMAT_DXT1_RGB; + case ISL_FORMAT_BC1_UNORM_SRGB: + return ISL_FORMAT_BC1_UNORM; + case ISL_FORMAT_BC2_UNORM_SRGB: + return ISL_FORMAT_BC2_UNORM; + case ISL_FORMAT_BC3_UNORM_SRGB: + return ISL_FORMAT_BC3_UNORM; + case ISL_FORMAT_BC7_UNORM_SRGB: + return ISL_FORMAT_BC7_UNORM; + case ISL_FORMAT_R8G8B8_UNORM_SRGB: + return ISL_FORMAT_R8G8B8_UNORM; + case ISL_FORMAT_ETC2_SRGB8: + return ISL_FORMAT_ETC2_RGB8; + case ISL_FORMAT_ETC2_SRGB8_PTA: + return ISL_FORMAT_ETC2_RGB8_PTA; + case ISL_FORMAT_ETC2_EAC_SRGB8_A8: + return ISL_FORMAT_ETC2_EAC_SRGB8_A8; + case ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB: + return ISL_FORMAT_ASTC_LDR_2D_4X4_U8SRGB; + case ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB: + return ISL_FORMAT_ASTC_LDR_2D_5X4_U8SRGB; + case ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB: + return ISL_FORMAT_ASTC_LDR_2D_5X5_U8SRGB; + case ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB: + return ISL_FORMAT_ASTC_LDR_2D_6X5_U8SRGB; + case ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB: + return ISL_FORMAT_ASTC_LDR_2D_6X6_U8SRGB; + case ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB: + return ISL_FORMAT_ASTC_LDR_2D_8X5_U8SRGB; + case ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB: + return ISL_FORMAT_ASTC_LDR_2D_8X6_U8SRGB; + case ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB: + return ISL_FORMAT_ASTC_LDR_2D_8X8_U8SRGB; + case ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB: + return ISL_FORMAT_ASTC_LDR_2D_10X5_U8SRGB; + case ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB: + return ISL_FORMAT_ASTC_LDR_2D_10X6_U8SRGB; + case ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB: + return ISL_FORMAT_ASTC_LDR_2D_10X8_U8SRGB; + case ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB: + return ISL_FORMAT_ASTC_LDR_2D_10X10_U8SRGB; + case ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB: + return ISL_FORMAT_ASTC_LDR_2D_12X10_U8SRGB; + case ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB: + return ISL_FORMAT_ASTC_LDR_2D_12X12_U8SRGB; + default: + return format; + } +} diff --git a/prebuilt-intermediates/main/format_fallback.c b/prebuilt-intermediates/main/format_fallback.c new file mode 100644 index 00000000000..ec68a8e4711 --- /dev/null +++ b/prebuilt-intermediates/main/format_fallback.c @@ -0,0 +1,352 @@ +/* + * Copyright 2017 Google + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "formats.h" +#include "util/macros.h" + +/** + * For an sRGB format, return the corresponding linear color space format. + * For non-sRGB formats, return the format as-is. + */ +mesa_format +_mesa_get_srgb_format_linear(mesa_format format) +{ + switch (format) { + case MESA_FORMAT_A8B8G8R8_SRGB: + return MESA_FORMAT_A8B8G8R8_UNORM; + case MESA_FORMAT_B8G8R8A8_SRGB: + return MESA_FORMAT_B8G8R8A8_UNORM; + case MESA_FORMAT_A8R8G8B8_SRGB: + return MESA_FORMAT_A8R8G8B8_UNORM; + case MESA_FORMAT_B8G8R8X8_SRGB: + return MESA_FORMAT_B8G8R8X8_UNORM; + case MESA_FORMAT_X8R8G8B8_SRGB: + return MESA_FORMAT_X8R8G8B8_UNORM; + case MESA_FORMAT_R8G8B8A8_SRGB: + return MESA_FORMAT_R8G8B8A8_UNORM; + case MESA_FORMAT_R8G8B8X8_SRGB: + return MESA_FORMAT_R8G8B8X8_UNORM; + case MESA_FORMAT_X8B8G8R8_SRGB: + return MESA_FORMAT_X8B8G8R8_UNORM; + case MESA_FORMAT_L8A8_SRGB: + return MESA_FORMAT_L8A8_UNORM; + case MESA_FORMAT_A8L8_SRGB: + return MESA_FORMAT_A8L8_UNORM; + case MESA_FORMAT_R_SRGB8: + return MESA_FORMAT_R_UNORM8; + case MESA_FORMAT_L_SRGB8: + return MESA_FORMAT_L_UNORM8; + case MESA_FORMAT_BGR_SRGB8: + return MESA_FORMAT_BGR_UNORM8; + case MESA_FORMAT_SRGB_DXT1: + return MESA_FORMAT_RGB_DXT1; + case MESA_FORMAT_SRGBA_DXT1: + return MESA_FORMAT_RGBA_DXT1; + case MESA_FORMAT_SRGBA_DXT3: + return MESA_FORMAT_RGBA_DXT3; + case MESA_FORMAT_SRGBA_DXT5: + return MESA_FORMAT_RGBA_DXT5; + case MESA_FORMAT_ETC2_SRGB8: + return MESA_FORMAT_ETC2_RGB8; + case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC: + return MESA_FORMAT_ETC2_RGBA8_EAC; + case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1: + return MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1; + case MESA_FORMAT_BPTC_SRGB_ALPHA_UNORM: + return MESA_FORMAT_BPTC_RGBA_UNORM; + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x4: + return MESA_FORMAT_RGBA_ASTC_4x4; + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x4: + return MESA_FORMAT_RGBA_ASTC_5x4; + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5: + return MESA_FORMAT_RGBA_ASTC_5x5; + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x5: + return MESA_FORMAT_RGBA_ASTC_6x5; + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x6: + return MESA_FORMAT_RGBA_ASTC_6x6; + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_8x5: + return MESA_FORMAT_RGBA_ASTC_8x5; + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_8x6: + return MESA_FORMAT_RGBA_ASTC_8x6; + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_8x8: + return MESA_FORMAT_RGBA_ASTC_8x8; + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x5: + return MESA_FORMAT_RGBA_ASTC_10x5; + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x6: + return MESA_FORMAT_RGBA_ASTC_10x6; + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x8: + return MESA_FORMAT_RGBA_ASTC_10x8; + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x10: + return MESA_FORMAT_RGBA_ASTC_10x10; + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_12x10: + return MESA_FORMAT_RGBA_ASTC_12x10; + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_12x12: + return MESA_FORMAT_RGBA_ASTC_12x12; + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_3x3x3: + return MESA_FORMAT_RGBA_ASTC_3x3x3; + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x3x3: + return MESA_FORMAT_RGBA_ASTC_4x3x3; + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x4x3: + return MESA_FORMAT_RGBA_ASTC_4x4x3; + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x4x4: + return MESA_FORMAT_RGBA_ASTC_4x4x4; + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x4x4: + return MESA_FORMAT_RGBA_ASTC_5x4x4; + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5x4: + return MESA_FORMAT_RGBA_ASTC_5x5x4; + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5x5: + return MESA_FORMAT_RGBA_ASTC_5x5x5; + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x5x5: + return MESA_FORMAT_RGBA_ASTC_6x5x5; + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x6x5: + return MESA_FORMAT_RGBA_ASTC_6x6x5; + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x6x6: + return MESA_FORMAT_RGBA_ASTC_6x6x6; + default: + return format; + } +} + +/** + * For a linear format, return the corresponding sRGB color space format. + * For an sRGB format, return the format as-is. + * Assert-fails if the format is not sRGB and does not have an sRGB equivalent. + */ +mesa_format +_mesa_get_linear_format_srgb(mesa_format format) +{ + switch (format) { + case MESA_FORMAT_A8B8G8R8_UNORM: + return MESA_FORMAT_A8B8G8R8_SRGB; + case MESA_FORMAT_B8G8R8A8_UNORM: + return MESA_FORMAT_B8G8R8A8_SRGB; + case MESA_FORMAT_A8R8G8B8_UNORM: + return MESA_FORMAT_A8R8G8B8_SRGB; + case MESA_FORMAT_B8G8R8X8_UNORM: + return MESA_FORMAT_B8G8R8X8_SRGB; + case MESA_FORMAT_X8R8G8B8_UNORM: + return MESA_FORMAT_X8R8G8B8_SRGB; + case MESA_FORMAT_R8G8B8A8_UNORM: + return MESA_FORMAT_R8G8B8A8_SRGB; + case MESA_FORMAT_R8G8B8X8_UNORM: + return MESA_FORMAT_R8G8B8X8_SRGB; + case MESA_FORMAT_X8B8G8R8_UNORM: + return MESA_FORMAT_X8B8G8R8_SRGB; + case MESA_FORMAT_L8A8_UNORM: + return MESA_FORMAT_L8A8_SRGB; + case MESA_FORMAT_A8L8_UNORM: + return MESA_FORMAT_A8L8_SRGB; + case MESA_FORMAT_R_UNORM8: + return MESA_FORMAT_R_SRGB8; + case MESA_FORMAT_L_UNORM8: + return MESA_FORMAT_L_SRGB8; + case MESA_FORMAT_BGR_UNORM8: + return MESA_FORMAT_BGR_SRGB8; + case MESA_FORMAT_RGB_DXT1: + return MESA_FORMAT_SRGB_DXT1; + case MESA_FORMAT_RGBA_DXT1: + return MESA_FORMAT_SRGBA_DXT1; + case MESA_FORMAT_RGBA_DXT3: + return MESA_FORMAT_SRGBA_DXT3; + case MESA_FORMAT_RGBA_DXT5: + return MESA_FORMAT_SRGBA_DXT5; + case MESA_FORMAT_ETC2_RGB8: + return MESA_FORMAT_ETC2_SRGB8; + case MESA_FORMAT_ETC2_RGBA8_EAC: + return MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC; + case MESA_FORMAT_ETC2_RGB8_PUNCHTHROUGH_ALPHA1: + return MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1; + case MESA_FORMAT_BPTC_RGBA_UNORM: + return MESA_FORMAT_BPTC_SRGB_ALPHA_UNORM; + case MESA_FORMAT_RGBA_ASTC_4x4: + return MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x4; + case MESA_FORMAT_RGBA_ASTC_5x4: + return MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x4; + case MESA_FORMAT_RGBA_ASTC_5x5: + return MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5; + case MESA_FORMAT_RGBA_ASTC_6x5: + return MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x5; + case MESA_FORMAT_RGBA_ASTC_6x6: + return MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x6; + case MESA_FORMAT_RGBA_ASTC_8x5: + return MESA_FORMAT_SRGB8_ALPHA8_ASTC_8x5; + case MESA_FORMAT_RGBA_ASTC_8x6: + return MESA_FORMAT_SRGB8_ALPHA8_ASTC_8x6; + case MESA_FORMAT_RGBA_ASTC_8x8: + return MESA_FORMAT_SRGB8_ALPHA8_ASTC_8x8; + case MESA_FORMAT_RGBA_ASTC_10x5: + return MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x5; + case MESA_FORMAT_RGBA_ASTC_10x6: + return MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x6; + case MESA_FORMAT_RGBA_ASTC_10x8: + return MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x8; + case MESA_FORMAT_RGBA_ASTC_10x10: + return MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x10; + case MESA_FORMAT_RGBA_ASTC_12x10: + return MESA_FORMAT_SRGB8_ALPHA8_ASTC_12x10; + case MESA_FORMAT_RGBA_ASTC_12x12: + return MESA_FORMAT_SRGB8_ALPHA8_ASTC_12x12; + case MESA_FORMAT_RGBA_ASTC_3x3x3: + return MESA_FORMAT_SRGB8_ALPHA8_ASTC_3x3x3; + case MESA_FORMAT_RGBA_ASTC_4x3x3: + return MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x3x3; + case MESA_FORMAT_RGBA_ASTC_4x4x3: + return MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x4x3; + case MESA_FORMAT_RGBA_ASTC_4x4x4: + return MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x4x4; + case MESA_FORMAT_RGBA_ASTC_5x4x4: + return MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x4x4; + case MESA_FORMAT_RGBA_ASTC_5x5x4: + return MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5x4; + case MESA_FORMAT_RGBA_ASTC_5x5x5: + return MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5x5; + case MESA_FORMAT_RGBA_ASTC_6x5x5: + return MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x5x5; + case MESA_FORMAT_RGBA_ASTC_6x6x5: + return MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x6x5; + case MESA_FORMAT_RGBA_ASTC_6x6x6: + return MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x6x6; + case MESA_FORMAT_A8B8G8R8_SRGB: + case MESA_FORMAT_B8G8R8A8_SRGB: + case MESA_FORMAT_A8R8G8B8_SRGB: + case MESA_FORMAT_B8G8R8X8_SRGB: + case MESA_FORMAT_X8R8G8B8_SRGB: + case MESA_FORMAT_R8G8B8A8_SRGB: + case MESA_FORMAT_R8G8B8X8_SRGB: + case MESA_FORMAT_X8B8G8R8_SRGB: + case MESA_FORMAT_L8A8_SRGB: + case MESA_FORMAT_A8L8_SRGB: + case MESA_FORMAT_R_SRGB8: + case MESA_FORMAT_L_SRGB8: + case MESA_FORMAT_BGR_SRGB8: + case MESA_FORMAT_SRGB_DXT1: + case MESA_FORMAT_SRGBA_DXT1: + case MESA_FORMAT_SRGBA_DXT3: + case MESA_FORMAT_SRGBA_DXT5: + case MESA_FORMAT_ETC2_SRGB8: + case MESA_FORMAT_ETC2_SRGB8_ALPHA8_EAC: + case MESA_FORMAT_ETC2_SRGB8_PUNCHTHROUGH_ALPHA1: + case MESA_FORMAT_BPTC_SRGB_ALPHA_UNORM: + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x4: + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x4: + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5: + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x5: + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x6: + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_8x5: + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_8x6: + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_8x8: + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x5: + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x6: + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x8: + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_10x10: + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_12x10: + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_12x12: + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_3x3x3: + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x3x3: + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x4x3: + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_4x4x4: + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x4x4: + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5x4: + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_5x5x5: + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x5x5: + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x6x5: + case MESA_FORMAT_SRGB8_ALPHA8_ASTC_6x6x6: + return format; + default: + unreachable("Given format does not have an sRGB equivalent"); + } +} + +/** + * If the format has an alpha channel, and there exists a non-alpha + * variant of the format with an identical bit layout, then return + * the non-alpha format. Otherwise return the original format. + * + * Examples: + * Fallback exists: + * MESA_FORMAT_R8G8B8X8_UNORM -> MESA_FORMAT_R8G8B8A8_UNORM + * MESA_FORMAT_RGBX_UNORM16 -> MESA_FORMAT_RGBA_UNORM16 + * + * No fallback: + * MESA_FORMAT_R8G8B8A8_UNORM -> MESA_FORMAT_R8G8B8A8_UNORM + * MESA_FORMAT_Z_FLOAT32 -> MESA_FORMAT_Z_FLOAT32 + */ +mesa_format +_mesa_format_fallback_rgbx_to_rgba(mesa_format format) +{ + switch (format) { + case MESA_FORMAT_X8B8G8R8_UNORM: + return MESA_FORMAT_A8B8G8R8_UNORM; + case MESA_FORMAT_R8G8B8X8_UNORM: + return MESA_FORMAT_R8G8B8A8_UNORM; + case MESA_FORMAT_B8G8R8X8_UNORM: + return MESA_FORMAT_B8G8R8A8_UNORM; + case MESA_FORMAT_X8R8G8B8_UNORM: + return MESA_FORMAT_A8R8G8B8_UNORM; + case MESA_FORMAT_B4G4R4X4_UNORM: + return MESA_FORMAT_B4G4R4A4_UNORM; + case MESA_FORMAT_X1B5G5R5_UNORM: + return MESA_FORMAT_A1B5G5R5_UNORM; + case MESA_FORMAT_B5G5R5X1_UNORM: + return MESA_FORMAT_B5G5R5A1_UNORM; + case MESA_FORMAT_B10G10R10X2_UNORM: + return MESA_FORMAT_B10G10R10A2_UNORM; + case MESA_FORMAT_R10G10B10X2_UNORM: + return MESA_FORMAT_R10G10B10A2_UNORM; + case MESA_FORMAT_RGBX_UNORM16: + return MESA_FORMAT_RGBA_UNORM16; + case MESA_FORMAT_X8B8G8R8_SNORM: + return MESA_FORMAT_A8B8G8R8_SNORM; + case MESA_FORMAT_R8G8B8X8_SNORM: + return MESA_FORMAT_R8G8B8A8_SNORM; + case MESA_FORMAT_RGBX_SNORM16: + return MESA_FORMAT_RGBA_SNORM16; + case MESA_FORMAT_B8G8R8X8_SRGB: + return MESA_FORMAT_B8G8R8A8_SRGB; + case MESA_FORMAT_X8R8G8B8_SRGB: + return MESA_FORMAT_A8R8G8B8_SRGB; + case MESA_FORMAT_R8G8B8X8_SRGB: + return MESA_FORMAT_R8G8B8A8_SRGB; + case MESA_FORMAT_X8B8G8R8_SRGB: + return MESA_FORMAT_A8B8G8R8_SRGB; + case MESA_FORMAT_RGBX_FLOAT16: + return MESA_FORMAT_RGBA_FLOAT16; + case MESA_FORMAT_RGBX_FLOAT32: + return MESA_FORMAT_RGBA_FLOAT32; + case MESA_FORMAT_RGBX_UINT8: + return MESA_FORMAT_RGBA_UINT8; + case MESA_FORMAT_RGBX_UINT16: + return MESA_FORMAT_RGBA_UINT16; + case MESA_FORMAT_RGBX_UINT32: + return MESA_FORMAT_RGBA_UINT32; + case MESA_FORMAT_RGBX_SINT8: + return MESA_FORMAT_RGBA_SINT8; + case MESA_FORMAT_RGBX_SINT16: + return MESA_FORMAT_RGBA_SINT16; + case MESA_FORMAT_RGBX_SINT32: + return MESA_FORMAT_RGBA_SINT32; + default: + return format; + } +} diff --git a/prebuilt-intermediates/main/format_pack.c b/prebuilt-intermediates/main/format_pack.c new file mode 100644 index 00000000000..3430f360f2e --- /dev/null +++ b/prebuilt-intermediates/main/format_pack.c @@ -0,0 +1,11288 @@ +/* + * Mesa 3-D graphics library + * + * Copyright (c) 2011 VMware, Inc. + * Copyright (c) 2014 Intel Corporation. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + + +/** + * Color, depth, stencil packing functions. + * Used to pack basic color, depth and stencil formats to specific + * hardware formats. + * + * There are both per-pixel and per-row packing functions: + * - The former will be used by swrast to write values to the color, depth, + * stencil buffers when drawing points, lines and masked spans. + * - The later will be used for image-oriented functions like glDrawPixels, + * glAccum, and glTexImage. + */ + +#include + +#include "config.h" +#include "errors.h" +#include "format_pack.h" +#include "format_utils.h" +#include "macros.h" +#include "util/format_rgb9e5.h" +#include "util/format_r11g11b10f.h" +#include "util/format_srgb.h" + +#define UNPACK(SRC, OFFSET, BITS) (((SRC) >> (OFFSET)) & MAX_UINT(BITS)) +#define PACK(SRC, OFFSET, BITS) (((SRC) & MAX_UINT(BITS)) << (OFFSET)) + + + +/* ubyte packing functions */ + + +static inline void +pack_ubyte_a8b8g8r8_unorm(const GLubyte src[4], void *dst) +{ + + + uint8_t a = + _mesa_unorm_to_unorm(src[3], 8, 8); + + + uint8_t b = + _mesa_unorm_to_unorm(src[2], 8, 8); + + + uint8_t g = + _mesa_unorm_to_unorm(src[1], 8, 8); + + + uint8_t r = + _mesa_unorm_to_unorm(src[0], 8, 8); + + uint32_t d = 0; + d |= PACK(a, 0, 8); + d |= PACK(b, 8, 8); + d |= PACK(g, 16, 8); + d |= PACK(r, 24, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_x8b8g8r8_unorm(const GLubyte src[4], void *dst) +{ + + + + uint8_t b = + _mesa_unorm_to_unorm(src[2], 8, 8); + + + uint8_t g = + _mesa_unorm_to_unorm(src[1], 8, 8); + + + uint8_t r = + _mesa_unorm_to_unorm(src[0], 8, 8); + + uint32_t d = 0; + d |= PACK(b, 8, 8); + d |= PACK(g, 16, 8); + d |= PACK(r, 24, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_r8g8b8a8_unorm(const GLubyte src[4], void *dst) +{ + + + uint8_t r = + _mesa_unorm_to_unorm(src[0], 8, 8); + + + uint8_t g = + _mesa_unorm_to_unorm(src[1], 8, 8); + + + uint8_t b = + _mesa_unorm_to_unorm(src[2], 8, 8); + + + uint8_t a = + _mesa_unorm_to_unorm(src[3], 8, 8); + + uint32_t d = 0; + d |= PACK(r, 0, 8); + d |= PACK(g, 8, 8); + d |= PACK(b, 16, 8); + d |= PACK(a, 24, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_r8g8b8x8_unorm(const GLubyte src[4], void *dst) +{ + + + uint8_t r = + _mesa_unorm_to_unorm(src[0], 8, 8); + + + uint8_t g = + _mesa_unorm_to_unorm(src[1], 8, 8); + + + uint8_t b = + _mesa_unorm_to_unorm(src[2], 8, 8); + + + uint32_t d = 0; + d |= PACK(r, 0, 8); + d |= PACK(g, 8, 8); + d |= PACK(b, 16, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_b8g8r8a8_unorm(const GLubyte src[4], void *dst) +{ + + + uint8_t b = + _mesa_unorm_to_unorm(src[2], 8, 8); + + + uint8_t g = + _mesa_unorm_to_unorm(src[1], 8, 8); + + + uint8_t r = + _mesa_unorm_to_unorm(src[0], 8, 8); + + + uint8_t a = + _mesa_unorm_to_unorm(src[3], 8, 8); + + uint32_t d = 0; + d |= PACK(b, 0, 8); + d |= PACK(g, 8, 8); + d |= PACK(r, 16, 8); + d |= PACK(a, 24, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_b8g8r8x8_unorm(const GLubyte src[4], void *dst) +{ + + + uint8_t b = + _mesa_unorm_to_unorm(src[2], 8, 8); + + + uint8_t g = + _mesa_unorm_to_unorm(src[1], 8, 8); + + + uint8_t r = + _mesa_unorm_to_unorm(src[0], 8, 8); + + + uint32_t d = 0; + d |= PACK(b, 0, 8); + d |= PACK(g, 8, 8); + d |= PACK(r, 16, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_a8r8g8b8_unorm(const GLubyte src[4], void *dst) +{ + + + uint8_t a = + _mesa_unorm_to_unorm(src[3], 8, 8); + + + uint8_t r = + _mesa_unorm_to_unorm(src[0], 8, 8); + + + uint8_t g = + _mesa_unorm_to_unorm(src[1], 8, 8); + + + uint8_t b = + _mesa_unorm_to_unorm(src[2], 8, 8); + + uint32_t d = 0; + d |= PACK(a, 0, 8); + d |= PACK(r, 8, 8); + d |= PACK(g, 16, 8); + d |= PACK(b, 24, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_x8r8g8b8_unorm(const GLubyte src[4], void *dst) +{ + + + + uint8_t r = + _mesa_unorm_to_unorm(src[0], 8, 8); + + + uint8_t g = + _mesa_unorm_to_unorm(src[1], 8, 8); + + + uint8_t b = + _mesa_unorm_to_unorm(src[2], 8, 8); + + uint32_t d = 0; + d |= PACK(r, 8, 8); + d |= PACK(g, 16, 8); + d |= PACK(b, 24, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_l16a16_unorm(const GLubyte src[4], void *dst) +{ + + + uint16_t l = + _mesa_unorm_to_unorm(src[0], 8, 16); + + + uint16_t a = + _mesa_unorm_to_unorm(src[3], 8, 16); + + uint32_t d = 0; + d |= PACK(l, 0, 16); + d |= PACK(a, 16, 16); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_a16l16_unorm(const GLubyte src[4], void *dst) +{ + + + uint16_t a = + _mesa_unorm_to_unorm(src[3], 8, 16); + + + uint16_t l = + _mesa_unorm_to_unorm(src[0], 8, 16); + + uint32_t d = 0; + d |= PACK(a, 0, 16); + d |= PACK(l, 16, 16); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_b5g6r5_unorm(const GLubyte src[4], void *dst) +{ + + + uint8_t b = + _mesa_unorm_to_unorm(src[2], 8, 5); + + + uint8_t g = + _mesa_unorm_to_unorm(src[1], 8, 6); + + + uint8_t r = + _mesa_unorm_to_unorm(src[0], 8, 5); + + uint16_t d = 0; + d |= PACK(b, 0, 5); + d |= PACK(g, 5, 6); + d |= PACK(r, 11, 5); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_ubyte_r5g6b5_unorm(const GLubyte src[4], void *dst) +{ + + + uint8_t r = + _mesa_unorm_to_unorm(src[0], 8, 5); + + + uint8_t g = + _mesa_unorm_to_unorm(src[1], 8, 6); + + + uint8_t b = + _mesa_unorm_to_unorm(src[2], 8, 5); + + uint16_t d = 0; + d |= PACK(r, 0, 5); + d |= PACK(g, 5, 6); + d |= PACK(b, 11, 5); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_ubyte_b4g4r4a4_unorm(const GLubyte src[4], void *dst) +{ + + + uint8_t b = + _mesa_unorm_to_unorm(src[2], 8, 4); + + + uint8_t g = + _mesa_unorm_to_unorm(src[1], 8, 4); + + + uint8_t r = + _mesa_unorm_to_unorm(src[0], 8, 4); + + + uint8_t a = + _mesa_unorm_to_unorm(src[3], 8, 4); + + uint16_t d = 0; + d |= PACK(b, 0, 4); + d |= PACK(g, 4, 4); + d |= PACK(r, 8, 4); + d |= PACK(a, 12, 4); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_ubyte_b4g4r4x4_unorm(const GLubyte src[4], void *dst) +{ + + + uint8_t b = + _mesa_unorm_to_unorm(src[2], 8, 4); + + + uint8_t g = + _mesa_unorm_to_unorm(src[1], 8, 4); + + + uint8_t r = + _mesa_unorm_to_unorm(src[0], 8, 4); + + + uint16_t d = 0; + d |= PACK(b, 0, 4); + d |= PACK(g, 4, 4); + d |= PACK(r, 8, 4); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_ubyte_a4r4g4b4_unorm(const GLubyte src[4], void *dst) +{ + + + uint8_t a = + _mesa_unorm_to_unorm(src[3], 8, 4); + + + uint8_t r = + _mesa_unorm_to_unorm(src[0], 8, 4); + + + uint8_t g = + _mesa_unorm_to_unorm(src[1], 8, 4); + + + uint8_t b = + _mesa_unorm_to_unorm(src[2], 8, 4); + + uint16_t d = 0; + d |= PACK(a, 0, 4); + d |= PACK(r, 4, 4); + d |= PACK(g, 8, 4); + d |= PACK(b, 12, 4); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_ubyte_a1b5g5r5_unorm(const GLubyte src[4], void *dst) +{ + + + uint8_t a = + _mesa_unorm_to_unorm(src[3], 8, 1); + + + uint8_t b = + _mesa_unorm_to_unorm(src[2], 8, 5); + + + uint8_t g = + _mesa_unorm_to_unorm(src[1], 8, 5); + + + uint8_t r = + _mesa_unorm_to_unorm(src[0], 8, 5); + + uint16_t d = 0; + d |= PACK(a, 0, 1); + d |= PACK(b, 1, 5); + d |= PACK(g, 6, 5); + d |= PACK(r, 11, 5); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_ubyte_x1b5g5r5_unorm(const GLubyte src[4], void *dst) +{ + + + + uint8_t b = + _mesa_unorm_to_unorm(src[2], 8, 5); + + + uint8_t g = + _mesa_unorm_to_unorm(src[1], 8, 5); + + + uint8_t r = + _mesa_unorm_to_unorm(src[0], 8, 5); + + uint16_t d = 0; + d |= PACK(b, 1, 5); + d |= PACK(g, 6, 5); + d |= PACK(r, 11, 5); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_ubyte_b5g5r5a1_unorm(const GLubyte src[4], void *dst) +{ + + + uint8_t b = + _mesa_unorm_to_unorm(src[2], 8, 5); + + + uint8_t g = + _mesa_unorm_to_unorm(src[1], 8, 5); + + + uint8_t r = + _mesa_unorm_to_unorm(src[0], 8, 5); + + + uint8_t a = + _mesa_unorm_to_unorm(src[3], 8, 1); + + uint16_t d = 0; + d |= PACK(b, 0, 5); + d |= PACK(g, 5, 5); + d |= PACK(r, 10, 5); + d |= PACK(a, 15, 1); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_ubyte_b5g5r5x1_unorm(const GLubyte src[4], void *dst) +{ + + + uint8_t b = + _mesa_unorm_to_unorm(src[2], 8, 5); + + + uint8_t g = + _mesa_unorm_to_unorm(src[1], 8, 5); + + + uint8_t r = + _mesa_unorm_to_unorm(src[0], 8, 5); + + + uint16_t d = 0; + d |= PACK(b, 0, 5); + d |= PACK(g, 5, 5); + d |= PACK(r, 10, 5); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_ubyte_a1r5g5b5_unorm(const GLubyte src[4], void *dst) +{ + + + uint8_t a = + _mesa_unorm_to_unorm(src[3], 8, 1); + + + uint8_t r = + _mesa_unorm_to_unorm(src[0], 8, 5); + + + uint8_t g = + _mesa_unorm_to_unorm(src[1], 8, 5); + + + uint8_t b = + _mesa_unorm_to_unorm(src[2], 8, 5); + + uint16_t d = 0; + d |= PACK(a, 0, 1); + d |= PACK(r, 1, 5); + d |= PACK(g, 6, 5); + d |= PACK(b, 11, 5); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_ubyte_l8a8_unorm(const GLubyte src[4], void *dst) +{ + + + uint8_t l = + _mesa_unorm_to_unorm(src[0], 8, 8); + + + uint8_t a = + _mesa_unorm_to_unorm(src[3], 8, 8); + + uint16_t d = 0; + d |= PACK(l, 0, 8); + d |= PACK(a, 8, 8); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_ubyte_a8l8_unorm(const GLubyte src[4], void *dst) +{ + + + uint8_t a = + _mesa_unorm_to_unorm(src[3], 8, 8); + + + uint8_t l = + _mesa_unorm_to_unorm(src[0], 8, 8); + + uint16_t d = 0; + d |= PACK(a, 0, 8); + d |= PACK(l, 8, 8); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_ubyte_r8g8_unorm(const GLubyte src[4], void *dst) +{ + + + uint8_t r = + _mesa_unorm_to_unorm(src[0], 8, 8); + + + uint8_t g = + _mesa_unorm_to_unorm(src[1], 8, 8); + + uint16_t d = 0; + d |= PACK(r, 0, 8); + d |= PACK(g, 8, 8); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_ubyte_g8r8_unorm(const GLubyte src[4], void *dst) +{ + + + uint8_t g = + _mesa_unorm_to_unorm(src[1], 8, 8); + + + uint8_t r = + _mesa_unorm_to_unorm(src[0], 8, 8); + + uint16_t d = 0; + d |= PACK(g, 0, 8); + d |= PACK(r, 8, 8); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_ubyte_l4a4_unorm(const GLubyte src[4], void *dst) +{ + + + uint8_t l = + _mesa_unorm_to_unorm(src[0], 8, 4); + + + uint8_t a = + _mesa_unorm_to_unorm(src[3], 8, 4); + + uint8_t d = 0; + d |= PACK(l, 0, 4); + d |= PACK(a, 4, 4); + (*(uint8_t *)dst) = d; +} + +static inline void +pack_ubyte_b2g3r3_unorm(const GLubyte src[4], void *dst) +{ + + + uint8_t b = + _mesa_unorm_to_unorm(src[2], 8, 2); + + + uint8_t g = + _mesa_unorm_to_unorm(src[1], 8, 3); + + + uint8_t r = + _mesa_unorm_to_unorm(src[0], 8, 3); + + uint8_t d = 0; + d |= PACK(b, 0, 2); + d |= PACK(g, 2, 3); + d |= PACK(r, 5, 3); + (*(uint8_t *)dst) = d; +} + +static inline void +pack_ubyte_r16g16_unorm(const GLubyte src[4], void *dst) +{ + + + uint16_t r = + _mesa_unorm_to_unorm(src[0], 8, 16); + + + uint16_t g = + _mesa_unorm_to_unorm(src[1], 8, 16); + + uint32_t d = 0; + d |= PACK(r, 0, 16); + d |= PACK(g, 16, 16); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_g16r16_unorm(const GLubyte src[4], void *dst) +{ + + + uint16_t g = + _mesa_unorm_to_unorm(src[1], 8, 16); + + + uint16_t r = + _mesa_unorm_to_unorm(src[0], 8, 16); + + uint32_t d = 0; + d |= PACK(g, 0, 16); + d |= PACK(r, 16, 16); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_b10g10r10a2_unorm(const GLubyte src[4], void *dst) +{ + + + uint16_t b = + _mesa_unorm_to_unorm(src[2], 8, 10); + + + uint16_t g = + _mesa_unorm_to_unorm(src[1], 8, 10); + + + uint16_t r = + _mesa_unorm_to_unorm(src[0], 8, 10); + + + uint8_t a = + _mesa_unorm_to_unorm(src[3], 8, 2); + + uint32_t d = 0; + d |= PACK(b, 0, 10); + d |= PACK(g, 10, 10); + d |= PACK(r, 20, 10); + d |= PACK(a, 30, 2); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_b10g10r10x2_unorm(const GLubyte src[4], void *dst) +{ + + + uint16_t b = + _mesa_unorm_to_unorm(src[2], 8, 10); + + + uint16_t g = + _mesa_unorm_to_unorm(src[1], 8, 10); + + + uint16_t r = + _mesa_unorm_to_unorm(src[0], 8, 10); + + + uint32_t d = 0; + d |= PACK(b, 0, 10); + d |= PACK(g, 10, 10); + d |= PACK(r, 20, 10); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_r10g10b10a2_unorm(const GLubyte src[4], void *dst) +{ + + + uint16_t r = + _mesa_unorm_to_unorm(src[0], 8, 10); + + + uint16_t g = + _mesa_unorm_to_unorm(src[1], 8, 10); + + + uint16_t b = + _mesa_unorm_to_unorm(src[2], 8, 10); + + + uint8_t a = + _mesa_unorm_to_unorm(src[3], 8, 2); + + uint32_t d = 0; + d |= PACK(r, 0, 10); + d |= PACK(g, 10, 10); + d |= PACK(b, 20, 10); + d |= PACK(a, 30, 2); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_r10g10b10x2_unorm(const GLubyte src[4], void *dst) +{ + + + uint16_t r = + _mesa_unorm_to_unorm(src[0], 8, 10); + + + uint16_t g = + _mesa_unorm_to_unorm(src[1], 8, 10); + + + uint16_t b = + _mesa_unorm_to_unorm(src[2], 8, 10); + + + uint32_t d = 0; + d |= PACK(r, 0, 10); + d |= PACK(g, 10, 10); + d |= PACK(b, 20, 10); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_r3g3b2_unorm(const GLubyte src[4], void *dst) +{ + + + uint8_t r = + _mesa_unorm_to_unorm(src[0], 8, 3); + + + uint8_t g = + _mesa_unorm_to_unorm(src[1], 8, 3); + + + uint8_t b = + _mesa_unorm_to_unorm(src[2], 8, 2); + + uint8_t d = 0; + d |= PACK(r, 0, 3); + d |= PACK(g, 3, 3); + d |= PACK(b, 6, 2); + (*(uint8_t *)dst) = d; +} + +static inline void +pack_ubyte_a4b4g4r4_unorm(const GLubyte src[4], void *dst) +{ + + + uint8_t a = + _mesa_unorm_to_unorm(src[3], 8, 4); + + + uint8_t b = + _mesa_unorm_to_unorm(src[2], 8, 4); + + + uint8_t g = + _mesa_unorm_to_unorm(src[1], 8, 4); + + + uint8_t r = + _mesa_unorm_to_unorm(src[0], 8, 4); + + uint16_t d = 0; + d |= PACK(a, 0, 4); + d |= PACK(b, 4, 4); + d |= PACK(g, 8, 4); + d |= PACK(r, 12, 4); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_ubyte_r4g4b4a4_unorm(const GLubyte src[4], void *dst) +{ + + + uint8_t r = + _mesa_unorm_to_unorm(src[0], 8, 4); + + + uint8_t g = + _mesa_unorm_to_unorm(src[1], 8, 4); + + + uint8_t b = + _mesa_unorm_to_unorm(src[2], 8, 4); + + + uint8_t a = + _mesa_unorm_to_unorm(src[3], 8, 4); + + uint16_t d = 0; + d |= PACK(r, 0, 4); + d |= PACK(g, 4, 4); + d |= PACK(b, 8, 4); + d |= PACK(a, 12, 4); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_ubyte_r5g5b5a1_unorm(const GLubyte src[4], void *dst) +{ + + + uint8_t r = + _mesa_unorm_to_unorm(src[0], 8, 5); + + + uint8_t g = + _mesa_unorm_to_unorm(src[1], 8, 5); + + + uint8_t b = + _mesa_unorm_to_unorm(src[2], 8, 5); + + + uint8_t a = + _mesa_unorm_to_unorm(src[3], 8, 1); + + uint16_t d = 0; + d |= PACK(r, 0, 5); + d |= PACK(g, 5, 5); + d |= PACK(b, 10, 5); + d |= PACK(a, 15, 1); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_ubyte_a2b10g10r10_unorm(const GLubyte src[4], void *dst) +{ + + + uint8_t a = + _mesa_unorm_to_unorm(src[3], 8, 2); + + + uint16_t b = + _mesa_unorm_to_unorm(src[2], 8, 10); + + + uint16_t g = + _mesa_unorm_to_unorm(src[1], 8, 10); + + + uint16_t r = + _mesa_unorm_to_unorm(src[0], 8, 10); + + uint32_t d = 0; + d |= PACK(a, 0, 2); + d |= PACK(b, 2, 10); + d |= PACK(g, 12, 10); + d |= PACK(r, 22, 10); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_a2r10g10b10_unorm(const GLubyte src[4], void *dst) +{ + + + uint8_t a = + _mesa_unorm_to_unorm(src[3], 8, 2); + + + uint16_t r = + _mesa_unorm_to_unorm(src[0], 8, 10); + + + uint16_t g = + _mesa_unorm_to_unorm(src[1], 8, 10); + + + uint16_t b = + _mesa_unorm_to_unorm(src[2], 8, 10); + + uint32_t d = 0; + d |= PACK(a, 0, 2); + d |= PACK(r, 2, 10); + d |= PACK(g, 12, 10); + d |= PACK(b, 22, 10); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_a_unorm8(const GLubyte src[4], void *dst) +{ + + + uint8_t a = + _mesa_unorm_to_unorm(src[3], 8, 8); + + uint8_t *d = (uint8_t *)dst; + d[0] = a; +} + +static inline void +pack_ubyte_a_unorm16(const GLubyte src[4], void *dst) +{ + + + uint16_t a = + _mesa_unorm_to_unorm(src[3], 8, 16); + + uint16_t *d = (uint16_t *)dst; + d[0] = a; +} + +static inline void +pack_ubyte_l_unorm8(const GLubyte src[4], void *dst) +{ + + + uint8_t l = + _mesa_unorm_to_unorm(src[0], 8, 8); + + uint8_t *d = (uint8_t *)dst; + d[0] = l; +} + +static inline void +pack_ubyte_l_unorm16(const GLubyte src[4], void *dst) +{ + + + uint16_t l = + _mesa_unorm_to_unorm(src[0], 8, 16); + + uint16_t *d = (uint16_t *)dst; + d[0] = l; +} + +static inline void +pack_ubyte_i_unorm8(const GLubyte src[4], void *dst) +{ + + + uint8_t i = + _mesa_unorm_to_unorm(src[0], 8, 8); + + uint8_t *d = (uint8_t *)dst; + d[0] = i; +} + +static inline void +pack_ubyte_i_unorm16(const GLubyte src[4], void *dst) +{ + + + uint16_t i = + _mesa_unorm_to_unorm(src[0], 8, 16); + + uint16_t *d = (uint16_t *)dst; + d[0] = i; +} + +static inline void +pack_ubyte_r_unorm8(const GLubyte src[4], void *dst) +{ + + + uint8_t r = + _mesa_unorm_to_unorm(src[0], 8, 8); + + uint8_t *d = (uint8_t *)dst; + d[0] = r; +} + +static inline void +pack_ubyte_r_unorm16(const GLubyte src[4], void *dst) +{ + + + uint16_t r = + _mesa_unorm_to_unorm(src[0], 8, 16); + + uint16_t *d = (uint16_t *)dst; + d[0] = r; +} + +static inline void +pack_ubyte_bgr_unorm8(const GLubyte src[4], void *dst) +{ + + + uint8_t b = + _mesa_unorm_to_unorm(src[2], 8, 8); + + + uint8_t g = + _mesa_unorm_to_unorm(src[1], 8, 8); + + + uint8_t r = + _mesa_unorm_to_unorm(src[0], 8, 8); + + uint8_t *d = (uint8_t *)dst; + d[0] = b; + d[1] = g; + d[2] = r; +} + +static inline void +pack_ubyte_rgb_unorm8(const GLubyte src[4], void *dst) +{ + + + uint8_t r = + _mesa_unorm_to_unorm(src[0], 8, 8); + + + uint8_t g = + _mesa_unorm_to_unorm(src[1], 8, 8); + + + uint8_t b = + _mesa_unorm_to_unorm(src[2], 8, 8); + + uint8_t *d = (uint8_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; +} + +static inline void +pack_ubyte_rgba_unorm16(const GLubyte src[4], void *dst) +{ + + + uint16_t r = + _mesa_unorm_to_unorm(src[0], 8, 16); + + + uint16_t g = + _mesa_unorm_to_unorm(src[1], 8, 16); + + + uint16_t b = + _mesa_unorm_to_unorm(src[2], 8, 16); + + + uint16_t a = + _mesa_unorm_to_unorm(src[3], 8, 16); + + uint16_t *d = (uint16_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + d[3] = a; +} + +static inline void +pack_ubyte_rgbx_unorm16(const GLubyte src[4], void *dst) +{ + + + uint16_t r = + _mesa_unorm_to_unorm(src[0], 8, 16); + + + uint16_t g = + _mesa_unorm_to_unorm(src[1], 8, 16); + + + uint16_t b = + _mesa_unorm_to_unorm(src[2], 8, 16); + + + uint16_t *d = (uint16_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + } + +static inline void +pack_ubyte_a8b8g8r8_snorm(const GLubyte src[4], void *dst) +{ + + + int8_t a = + _mesa_unorm_to_snorm(src[3], 8, 8); + + + int8_t b = + _mesa_unorm_to_snorm(src[2], 8, 8); + + + int8_t g = + _mesa_unorm_to_snorm(src[1], 8, 8); + + + int8_t r = + _mesa_unorm_to_snorm(src[0], 8, 8); + + uint32_t d = 0; + d |= PACK(a, 0, 8); + d |= PACK(b, 8, 8); + d |= PACK(g, 16, 8); + d |= PACK(r, 24, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_x8b8g8r8_snorm(const GLubyte src[4], void *dst) +{ + + + + int8_t b = + _mesa_unorm_to_snorm(src[2], 8, 8); + + + int8_t g = + _mesa_unorm_to_snorm(src[1], 8, 8); + + + int8_t r = + _mesa_unorm_to_snorm(src[0], 8, 8); + + uint32_t d = 0; + d |= PACK(b, 8, 8); + d |= PACK(g, 16, 8); + d |= PACK(r, 24, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_r8g8b8a8_snorm(const GLubyte src[4], void *dst) +{ + + + int8_t r = + _mesa_unorm_to_snorm(src[0], 8, 8); + + + int8_t g = + _mesa_unorm_to_snorm(src[1], 8, 8); + + + int8_t b = + _mesa_unorm_to_snorm(src[2], 8, 8); + + + int8_t a = + _mesa_unorm_to_snorm(src[3], 8, 8); + + uint32_t d = 0; + d |= PACK(r, 0, 8); + d |= PACK(g, 8, 8); + d |= PACK(b, 16, 8); + d |= PACK(a, 24, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_r8g8b8x8_snorm(const GLubyte src[4], void *dst) +{ + + + int8_t r = + _mesa_unorm_to_snorm(src[0], 8, 8); + + + int8_t g = + _mesa_unorm_to_snorm(src[1], 8, 8); + + + int8_t b = + _mesa_unorm_to_snorm(src[2], 8, 8); + + + uint32_t d = 0; + d |= PACK(r, 0, 8); + d |= PACK(g, 8, 8); + d |= PACK(b, 16, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_r16g16_snorm(const GLubyte src[4], void *dst) +{ + + + int16_t r = + _mesa_unorm_to_snorm(src[0], 8, 16); + + + int16_t g = + _mesa_unorm_to_snorm(src[1], 8, 16); + + uint32_t d = 0; + d |= PACK(r, 0, 16); + d |= PACK(g, 16, 16); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_g16r16_snorm(const GLubyte src[4], void *dst) +{ + + + int16_t g = + _mesa_unorm_to_snorm(src[1], 8, 16); + + + int16_t r = + _mesa_unorm_to_snorm(src[0], 8, 16); + + uint32_t d = 0; + d |= PACK(g, 0, 16); + d |= PACK(r, 16, 16); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_r8g8_snorm(const GLubyte src[4], void *dst) +{ + + + int8_t r = + _mesa_unorm_to_snorm(src[0], 8, 8); + + + int8_t g = + _mesa_unorm_to_snorm(src[1], 8, 8); + + uint16_t d = 0; + d |= PACK(r, 0, 8); + d |= PACK(g, 8, 8); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_ubyte_g8r8_snorm(const GLubyte src[4], void *dst) +{ + + + int8_t g = + _mesa_unorm_to_snorm(src[1], 8, 8); + + + int8_t r = + _mesa_unorm_to_snorm(src[0], 8, 8); + + uint16_t d = 0; + d |= PACK(g, 0, 8); + d |= PACK(r, 8, 8); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_ubyte_l8a8_snorm(const GLubyte src[4], void *dst) +{ + + + int8_t l = + _mesa_unorm_to_snorm(src[0], 8, 8); + + + int8_t a = + _mesa_unorm_to_snorm(src[3], 8, 8); + + uint16_t d = 0; + d |= PACK(l, 0, 8); + d |= PACK(a, 8, 8); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_ubyte_a8l8_snorm(const GLubyte src[4], void *dst) +{ + + + int8_t a = + _mesa_unorm_to_snorm(src[3], 8, 8); + + + int8_t l = + _mesa_unorm_to_snorm(src[0], 8, 8); + + uint16_t d = 0; + d |= PACK(a, 0, 8); + d |= PACK(l, 8, 8); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_ubyte_a_snorm8(const GLubyte src[4], void *dst) +{ + + + int8_t a = + _mesa_unorm_to_snorm(src[3], 8, 8); + + int8_t *d = (int8_t *)dst; + d[0] = a; +} + +static inline void +pack_ubyte_a_snorm16(const GLubyte src[4], void *dst) +{ + + + int16_t a = + _mesa_unorm_to_snorm(src[3], 8, 16); + + int16_t *d = (int16_t *)dst; + d[0] = a; +} + +static inline void +pack_ubyte_l_snorm8(const GLubyte src[4], void *dst) +{ + + + int8_t l = + _mesa_unorm_to_snorm(src[0], 8, 8); + + int8_t *d = (int8_t *)dst; + d[0] = l; +} + +static inline void +pack_ubyte_l_snorm16(const GLubyte src[4], void *dst) +{ + + + int16_t l = + _mesa_unorm_to_snorm(src[0], 8, 16); + + int16_t *d = (int16_t *)dst; + d[0] = l; +} + +static inline void +pack_ubyte_i_snorm8(const GLubyte src[4], void *dst) +{ + + + int8_t i = + _mesa_unorm_to_snorm(src[0], 8, 8); + + int8_t *d = (int8_t *)dst; + d[0] = i; +} + +static inline void +pack_ubyte_i_snorm16(const GLubyte src[4], void *dst) +{ + + + int16_t i = + _mesa_unorm_to_snorm(src[0], 8, 16); + + int16_t *d = (int16_t *)dst; + d[0] = i; +} + +static inline void +pack_ubyte_r_snorm8(const GLubyte src[4], void *dst) +{ + + + int8_t r = + _mesa_unorm_to_snorm(src[0], 8, 8); + + int8_t *d = (int8_t *)dst; + d[0] = r; +} + +static inline void +pack_ubyte_r_snorm16(const GLubyte src[4], void *dst) +{ + + + int16_t r = + _mesa_unorm_to_snorm(src[0], 8, 16); + + int16_t *d = (int16_t *)dst; + d[0] = r; +} + +static inline void +pack_ubyte_la_snorm16(const GLubyte src[4], void *dst) +{ + + + int16_t l = + _mesa_unorm_to_snorm(src[0], 8, 16); + + + int16_t a = + _mesa_unorm_to_snorm(src[3], 8, 16); + + int16_t *d = (int16_t *)dst; + d[0] = l; + d[1] = a; +} + +static inline void +pack_ubyte_rgb_snorm16(const GLubyte src[4], void *dst) +{ + + + int16_t r = + _mesa_unorm_to_snorm(src[0], 8, 16); + + + int16_t g = + _mesa_unorm_to_snorm(src[1], 8, 16); + + + int16_t b = + _mesa_unorm_to_snorm(src[2], 8, 16); + + int16_t *d = (int16_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; +} + +static inline void +pack_ubyte_rgba_snorm16(const GLubyte src[4], void *dst) +{ + + + int16_t r = + _mesa_unorm_to_snorm(src[0], 8, 16); + + + int16_t g = + _mesa_unorm_to_snorm(src[1], 8, 16); + + + int16_t b = + _mesa_unorm_to_snorm(src[2], 8, 16); + + + int16_t a = + _mesa_unorm_to_snorm(src[3], 8, 16); + + int16_t *d = (int16_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + d[3] = a; +} + +static inline void +pack_ubyte_rgbx_snorm16(const GLubyte src[4], void *dst) +{ + + + int16_t r = + _mesa_unorm_to_snorm(src[0], 8, 16); + + + int16_t g = + _mesa_unorm_to_snorm(src[1], 8, 16); + + + int16_t b = + _mesa_unorm_to_snorm(src[2], 8, 16); + + + int16_t *d = (int16_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + } + +static inline void +pack_ubyte_a8b8g8r8_srgb(const GLubyte src[4], void *dst) +{ + + + uint8_t a = + _mesa_unorm_to_unorm(src[3], 8, 8); + + + uint8_t b = + + util_format_linear_to_srgb_8unorm(src[2]); + + + uint8_t g = + + util_format_linear_to_srgb_8unorm(src[1]); + + + uint8_t r = + + util_format_linear_to_srgb_8unorm(src[0]); + + uint32_t d = 0; + d |= PACK(a, 0, 8); + d |= PACK(b, 8, 8); + d |= PACK(g, 16, 8); + d |= PACK(r, 24, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_b8g8r8a8_srgb(const GLubyte src[4], void *dst) +{ + + + uint8_t b = + + util_format_linear_to_srgb_8unorm(src[2]); + + + uint8_t g = + + util_format_linear_to_srgb_8unorm(src[1]); + + + uint8_t r = + + util_format_linear_to_srgb_8unorm(src[0]); + + + uint8_t a = + _mesa_unorm_to_unorm(src[3], 8, 8); + + uint32_t d = 0; + d |= PACK(b, 0, 8); + d |= PACK(g, 8, 8); + d |= PACK(r, 16, 8); + d |= PACK(a, 24, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_a8r8g8b8_srgb(const GLubyte src[4], void *dst) +{ + + + uint8_t a = + _mesa_unorm_to_unorm(src[3], 8, 8); + + + uint8_t r = + + util_format_linear_to_srgb_8unorm(src[0]); + + + uint8_t g = + + util_format_linear_to_srgb_8unorm(src[1]); + + + uint8_t b = + + util_format_linear_to_srgb_8unorm(src[2]); + + uint32_t d = 0; + d |= PACK(a, 0, 8); + d |= PACK(r, 8, 8); + d |= PACK(g, 16, 8); + d |= PACK(b, 24, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_b8g8r8x8_srgb(const GLubyte src[4], void *dst) +{ + + + uint8_t b = + + util_format_linear_to_srgb_8unorm(src[2]); + + + uint8_t g = + + util_format_linear_to_srgb_8unorm(src[1]); + + + uint8_t r = + + util_format_linear_to_srgb_8unorm(src[0]); + + + uint32_t d = 0; + d |= PACK(b, 0, 8); + d |= PACK(g, 8, 8); + d |= PACK(r, 16, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_x8r8g8b8_srgb(const GLubyte src[4], void *dst) +{ + + + + uint8_t r = + + util_format_linear_to_srgb_8unorm(src[0]); + + + uint8_t g = + + util_format_linear_to_srgb_8unorm(src[1]); + + + uint8_t b = + + util_format_linear_to_srgb_8unorm(src[2]); + + uint32_t d = 0; + d |= PACK(r, 8, 8); + d |= PACK(g, 16, 8); + d |= PACK(b, 24, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_r8g8b8a8_srgb(const GLubyte src[4], void *dst) +{ + + + uint8_t r = + + util_format_linear_to_srgb_8unorm(src[0]); + + + uint8_t g = + + util_format_linear_to_srgb_8unorm(src[1]); + + + uint8_t b = + + util_format_linear_to_srgb_8unorm(src[2]); + + + uint8_t a = + _mesa_unorm_to_unorm(src[3], 8, 8); + + uint32_t d = 0; + d |= PACK(r, 0, 8); + d |= PACK(g, 8, 8); + d |= PACK(b, 16, 8); + d |= PACK(a, 24, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_r8g8b8x8_srgb(const GLubyte src[4], void *dst) +{ + + + uint8_t r = + + util_format_linear_to_srgb_8unorm(src[0]); + + + uint8_t g = + + util_format_linear_to_srgb_8unorm(src[1]); + + + uint8_t b = + + util_format_linear_to_srgb_8unorm(src[2]); + + + uint32_t d = 0; + d |= PACK(r, 0, 8); + d |= PACK(g, 8, 8); + d |= PACK(b, 16, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_x8b8g8r8_srgb(const GLubyte src[4], void *dst) +{ + + + + uint8_t b = + + util_format_linear_to_srgb_8unorm(src[2]); + + + uint8_t g = + + util_format_linear_to_srgb_8unorm(src[1]); + + + uint8_t r = + + util_format_linear_to_srgb_8unorm(src[0]); + + uint32_t d = 0; + d |= PACK(b, 8, 8); + d |= PACK(g, 16, 8); + d |= PACK(r, 24, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_l8a8_srgb(const GLubyte src[4], void *dst) +{ + + + uint8_t l = + _mesa_unorm_to_unorm(src[0], 8, 8); + + + uint8_t a = + _mesa_unorm_to_unorm(src[3], 8, 8); + + uint16_t d = 0; + d |= PACK(l, 0, 8); + d |= PACK(a, 8, 8); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_ubyte_a8l8_srgb(const GLubyte src[4], void *dst) +{ + + + uint8_t a = + _mesa_unorm_to_unorm(src[3], 8, 8); + + + uint8_t l = + _mesa_unorm_to_unorm(src[0], 8, 8); + + uint16_t d = 0; + d |= PACK(a, 0, 8); + d |= PACK(l, 8, 8); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_ubyte_r_srgb8(const GLubyte src[4], void *dst) +{ + + + uint8_t r = + + util_format_linear_to_srgb_8unorm(src[0]); + + uint8_t *d = (uint8_t *)dst; + d[0] = r; +} + +static inline void +pack_ubyte_l_srgb8(const GLubyte src[4], void *dst) +{ + + + uint8_t l = + _mesa_unorm_to_unorm(src[0], 8, 8); + + uint8_t *d = (uint8_t *)dst; + d[0] = l; +} + +static inline void +pack_ubyte_bgr_srgb8(const GLubyte src[4], void *dst) +{ + + + uint8_t b = + + util_format_linear_to_srgb_8unorm(src[2]); + + + uint8_t g = + + util_format_linear_to_srgb_8unorm(src[1]); + + + uint8_t r = + + util_format_linear_to_srgb_8unorm(src[0]); + + uint8_t *d = (uint8_t *)dst; + d[0] = b; + d[1] = g; + d[2] = r; +} + +static inline void +pack_ubyte_a_float16(const GLubyte src[4], void *dst) +{ + + + uint16_t a = + _mesa_unorm_to_half(src[3], 8); + + uint16_t *d = (uint16_t *)dst; + d[0] = a; +} + +static inline void +pack_ubyte_a_float32(const GLubyte src[4], void *dst) +{ + + + float a = + _mesa_unorm_to_float(src[3], 8); + + float *d = (float *)dst; + d[0] = a; +} + +static inline void +pack_ubyte_l_float16(const GLubyte src[4], void *dst) +{ + + + uint16_t l = + _mesa_unorm_to_half(src[0], 8); + + uint16_t *d = (uint16_t *)dst; + d[0] = l; +} + +static inline void +pack_ubyte_l_float32(const GLubyte src[4], void *dst) +{ + + + float l = + _mesa_unorm_to_float(src[0], 8); + + float *d = (float *)dst; + d[0] = l; +} + +static inline void +pack_ubyte_la_float16(const GLubyte src[4], void *dst) +{ + + + uint16_t l = + _mesa_unorm_to_half(src[0], 8); + + + uint16_t a = + _mesa_unorm_to_half(src[3], 8); + + uint16_t *d = (uint16_t *)dst; + d[0] = l; + d[1] = a; +} + +static inline void +pack_ubyte_la_float32(const GLubyte src[4], void *dst) +{ + + + float l = + _mesa_unorm_to_float(src[0], 8); + + + float a = + _mesa_unorm_to_float(src[3], 8); + + float *d = (float *)dst; + d[0] = l; + d[1] = a; +} + +static inline void +pack_ubyte_i_float16(const GLubyte src[4], void *dst) +{ + + + uint16_t i = + _mesa_unorm_to_half(src[0], 8); + + uint16_t *d = (uint16_t *)dst; + d[0] = i; +} + +static inline void +pack_ubyte_i_float32(const GLubyte src[4], void *dst) +{ + + + float i = + _mesa_unorm_to_float(src[0], 8); + + float *d = (float *)dst; + d[0] = i; +} + +static inline void +pack_ubyte_r_float16(const GLubyte src[4], void *dst) +{ + + + uint16_t r = + _mesa_unorm_to_half(src[0], 8); + + uint16_t *d = (uint16_t *)dst; + d[0] = r; +} + +static inline void +pack_ubyte_r_float32(const GLubyte src[4], void *dst) +{ + + + float r = + _mesa_unorm_to_float(src[0], 8); + + float *d = (float *)dst; + d[0] = r; +} + +static inline void +pack_ubyte_rg_float16(const GLubyte src[4], void *dst) +{ + + + uint16_t r = + _mesa_unorm_to_half(src[0], 8); + + + uint16_t g = + _mesa_unorm_to_half(src[1], 8); + + uint16_t *d = (uint16_t *)dst; + d[0] = r; + d[1] = g; +} + +static inline void +pack_ubyte_rg_float32(const GLubyte src[4], void *dst) +{ + + + float r = + _mesa_unorm_to_float(src[0], 8); + + + float g = + _mesa_unorm_to_float(src[1], 8); + + float *d = (float *)dst; + d[0] = r; + d[1] = g; +} + +static inline void +pack_ubyte_rgb_float16(const GLubyte src[4], void *dst) +{ + + + uint16_t r = + _mesa_unorm_to_half(src[0], 8); + + + uint16_t g = + _mesa_unorm_to_half(src[1], 8); + + + uint16_t b = + _mesa_unorm_to_half(src[2], 8); + + uint16_t *d = (uint16_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; +} + +static inline void +pack_ubyte_rgb_float32(const GLubyte src[4], void *dst) +{ + + + float r = + _mesa_unorm_to_float(src[0], 8); + + + float g = + _mesa_unorm_to_float(src[1], 8); + + + float b = + _mesa_unorm_to_float(src[2], 8); + + float *d = (float *)dst; + d[0] = r; + d[1] = g; + d[2] = b; +} + +static inline void +pack_ubyte_rgba_float16(const GLubyte src[4], void *dst) +{ + + + uint16_t r = + _mesa_unorm_to_half(src[0], 8); + + + uint16_t g = + _mesa_unorm_to_half(src[1], 8); + + + uint16_t b = + _mesa_unorm_to_half(src[2], 8); + + + uint16_t a = + _mesa_unorm_to_half(src[3], 8); + + uint16_t *d = (uint16_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + d[3] = a; +} + +static inline void +pack_ubyte_rgba_float32(const GLubyte src[4], void *dst) +{ + + + float r = + _mesa_unorm_to_float(src[0], 8); + + + float g = + _mesa_unorm_to_float(src[1], 8); + + + float b = + _mesa_unorm_to_float(src[2], 8); + + + float a = + _mesa_unorm_to_float(src[3], 8); + + float *d = (float *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + d[3] = a; +} + +static inline void +pack_ubyte_rgbx_float16(const GLubyte src[4], void *dst) +{ + + + uint16_t r = + _mesa_unorm_to_half(src[0], 8); + + + uint16_t g = + _mesa_unorm_to_half(src[1], 8); + + + uint16_t b = + _mesa_unorm_to_half(src[2], 8); + + + uint16_t *d = (uint16_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + } + +static inline void +pack_ubyte_rgbx_float32(const GLubyte src[4], void *dst) +{ + + + float r = + _mesa_unorm_to_float(src[0], 8); + + + float g = + _mesa_unorm_to_float(src[1], 8); + + + float b = + _mesa_unorm_to_float(src[2], 8); + + + float *d = (float *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + } + +static inline void +pack_ubyte_a8b8g8r8_uint(const GLubyte src[4], void *dst) +{ + + + uint8_t a = + _mesa_unsigned_to_unsigned(src[3], 8); + + + uint8_t b = + _mesa_unsigned_to_unsigned(src[2], 8); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 8); + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 8); + + uint32_t d = 0; + d |= PACK(a, 0, 8); + d |= PACK(b, 8, 8); + d |= PACK(g, 16, 8); + d |= PACK(r, 24, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_a8r8g8b8_uint(const GLubyte src[4], void *dst) +{ + + + uint8_t a = + _mesa_unsigned_to_unsigned(src[3], 8); + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 8); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 8); + + + uint8_t b = + _mesa_unsigned_to_unsigned(src[2], 8); + + uint32_t d = 0; + d |= PACK(a, 0, 8); + d |= PACK(r, 8, 8); + d |= PACK(g, 16, 8); + d |= PACK(b, 24, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_r8g8b8a8_uint(const GLubyte src[4], void *dst) +{ + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 8); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 8); + + + uint8_t b = + _mesa_unsigned_to_unsigned(src[2], 8); + + + uint8_t a = + _mesa_unsigned_to_unsigned(src[3], 8); + + uint32_t d = 0; + d |= PACK(r, 0, 8); + d |= PACK(g, 8, 8); + d |= PACK(b, 16, 8); + d |= PACK(a, 24, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_b8g8r8a8_uint(const GLubyte src[4], void *dst) +{ + + + uint8_t b = + _mesa_unsigned_to_unsigned(src[2], 8); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 8); + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 8); + + + uint8_t a = + _mesa_unsigned_to_unsigned(src[3], 8); + + uint32_t d = 0; + d |= PACK(b, 0, 8); + d |= PACK(g, 8, 8); + d |= PACK(r, 16, 8); + d |= PACK(a, 24, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_b10g10r10a2_uint(const GLubyte src[4], void *dst) +{ + + + uint16_t b = + _mesa_unsigned_to_unsigned(src[2], 10); + + + uint16_t g = + _mesa_unsigned_to_unsigned(src[1], 10); + + + uint16_t r = + _mesa_unsigned_to_unsigned(src[0], 10); + + + uint8_t a = + _mesa_unsigned_to_unsigned(src[3], 2); + + uint32_t d = 0; + d |= PACK(b, 0, 10); + d |= PACK(g, 10, 10); + d |= PACK(r, 20, 10); + d |= PACK(a, 30, 2); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_r10g10b10a2_uint(const GLubyte src[4], void *dst) +{ + + + uint16_t r = + _mesa_unsigned_to_unsigned(src[0], 10); + + + uint16_t g = + _mesa_unsigned_to_unsigned(src[1], 10); + + + uint16_t b = + _mesa_unsigned_to_unsigned(src[2], 10); + + + uint8_t a = + _mesa_unsigned_to_unsigned(src[3], 2); + + uint32_t d = 0; + d |= PACK(r, 0, 10); + d |= PACK(g, 10, 10); + d |= PACK(b, 20, 10); + d |= PACK(a, 30, 2); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_a2b10g10r10_uint(const GLubyte src[4], void *dst) +{ + + + uint8_t a = + _mesa_unsigned_to_unsigned(src[3], 2); + + + uint16_t b = + _mesa_unsigned_to_unsigned(src[2], 10); + + + uint16_t g = + _mesa_unsigned_to_unsigned(src[1], 10); + + + uint16_t r = + _mesa_unsigned_to_unsigned(src[0], 10); + + uint32_t d = 0; + d |= PACK(a, 0, 2); + d |= PACK(b, 2, 10); + d |= PACK(g, 12, 10); + d |= PACK(r, 22, 10); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_a2r10g10b10_uint(const GLubyte src[4], void *dst) +{ + + + uint8_t a = + _mesa_unsigned_to_unsigned(src[3], 2); + + + uint16_t r = + _mesa_unsigned_to_unsigned(src[0], 10); + + + uint16_t g = + _mesa_unsigned_to_unsigned(src[1], 10); + + + uint16_t b = + _mesa_unsigned_to_unsigned(src[2], 10); + + uint32_t d = 0; + d |= PACK(a, 0, 2); + d |= PACK(r, 2, 10); + d |= PACK(g, 12, 10); + d |= PACK(b, 22, 10); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_ubyte_b5g6r5_uint(const GLubyte src[4], void *dst) +{ + + + uint8_t b = + _mesa_unsigned_to_unsigned(src[2], 5); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 6); + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 5); + + uint16_t d = 0; + d |= PACK(b, 0, 5); + d |= PACK(g, 5, 6); + d |= PACK(r, 11, 5); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_ubyte_r5g6b5_uint(const GLubyte src[4], void *dst) +{ + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 5); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 6); + + + uint8_t b = + _mesa_unsigned_to_unsigned(src[2], 5); + + uint16_t d = 0; + d |= PACK(r, 0, 5); + d |= PACK(g, 5, 6); + d |= PACK(b, 11, 5); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_ubyte_b2g3r3_uint(const GLubyte src[4], void *dst) +{ + + + uint8_t b = + _mesa_unsigned_to_unsigned(src[2], 2); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 3); + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 3); + + uint8_t d = 0; + d |= PACK(b, 0, 2); + d |= PACK(g, 2, 3); + d |= PACK(r, 5, 3); + (*(uint8_t *)dst) = d; +} + +static inline void +pack_ubyte_r3g3b2_uint(const GLubyte src[4], void *dst) +{ + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 3); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 3); + + + uint8_t b = + _mesa_unsigned_to_unsigned(src[2], 2); + + uint8_t d = 0; + d |= PACK(r, 0, 3); + d |= PACK(g, 3, 3); + d |= PACK(b, 6, 2); + (*(uint8_t *)dst) = d; +} + +static inline void +pack_ubyte_a4b4g4r4_uint(const GLubyte src[4], void *dst) +{ + + + uint8_t a = + _mesa_unsigned_to_unsigned(src[3], 4); + + + uint8_t b = + _mesa_unsigned_to_unsigned(src[2], 4); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 4); + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 4); + + uint16_t d = 0; + d |= PACK(a, 0, 4); + d |= PACK(b, 4, 4); + d |= PACK(g, 8, 4); + d |= PACK(r, 12, 4); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_ubyte_r4g4b4a4_uint(const GLubyte src[4], void *dst) +{ + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 4); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 4); + + + uint8_t b = + _mesa_unsigned_to_unsigned(src[2], 4); + + + uint8_t a = + _mesa_unsigned_to_unsigned(src[3], 4); + + uint16_t d = 0; + d |= PACK(r, 0, 4); + d |= PACK(g, 4, 4); + d |= PACK(b, 8, 4); + d |= PACK(a, 12, 4); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_ubyte_b4g4r4a4_uint(const GLubyte src[4], void *dst) +{ + + + uint8_t b = + _mesa_unsigned_to_unsigned(src[2], 4); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 4); + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 4); + + + uint8_t a = + _mesa_unsigned_to_unsigned(src[3], 4); + + uint16_t d = 0; + d |= PACK(b, 0, 4); + d |= PACK(g, 4, 4); + d |= PACK(r, 8, 4); + d |= PACK(a, 12, 4); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_ubyte_a4r4g4b4_uint(const GLubyte src[4], void *dst) +{ + + + uint8_t a = + _mesa_unsigned_to_unsigned(src[3], 4); + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 4); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 4); + + + uint8_t b = + _mesa_unsigned_to_unsigned(src[2], 4); + + uint16_t d = 0; + d |= PACK(a, 0, 4); + d |= PACK(r, 4, 4); + d |= PACK(g, 8, 4); + d |= PACK(b, 12, 4); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_ubyte_a1b5g5r5_uint(const GLubyte src[4], void *dst) +{ + + + uint8_t a = + _mesa_unsigned_to_unsigned(src[3], 1); + + + uint8_t b = + _mesa_unsigned_to_unsigned(src[2], 5); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 5); + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 5); + + uint16_t d = 0; + d |= PACK(a, 0, 1); + d |= PACK(b, 1, 5); + d |= PACK(g, 6, 5); + d |= PACK(r, 11, 5); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_ubyte_b5g5r5a1_uint(const GLubyte src[4], void *dst) +{ + + + uint8_t b = + _mesa_unsigned_to_unsigned(src[2], 5); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 5); + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 5); + + + uint8_t a = + _mesa_unsigned_to_unsigned(src[3], 1); + + uint16_t d = 0; + d |= PACK(b, 0, 5); + d |= PACK(g, 5, 5); + d |= PACK(r, 10, 5); + d |= PACK(a, 15, 1); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_ubyte_a1r5g5b5_uint(const GLubyte src[4], void *dst) +{ + + + uint8_t a = + _mesa_unsigned_to_unsigned(src[3], 1); + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 5); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 5); + + + uint8_t b = + _mesa_unsigned_to_unsigned(src[2], 5); + + uint16_t d = 0; + d |= PACK(a, 0, 1); + d |= PACK(r, 1, 5); + d |= PACK(g, 6, 5); + d |= PACK(b, 11, 5); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_ubyte_r5g5b5a1_uint(const GLubyte src[4], void *dst) +{ + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 5); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 5); + + + uint8_t b = + _mesa_unsigned_to_unsigned(src[2], 5); + + + uint8_t a = + _mesa_unsigned_to_unsigned(src[3], 1); + + uint16_t d = 0; + d |= PACK(r, 0, 5); + d |= PACK(g, 5, 5); + d |= PACK(b, 10, 5); + d |= PACK(a, 15, 1); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_ubyte_a_uint8(const GLubyte src[4], void *dst) +{ + + + uint8_t a = + _mesa_unsigned_to_unsigned(src[3], 8); + + uint8_t *d = (uint8_t *)dst; + d[0] = a; +} + +static inline void +pack_ubyte_a_uint16(const GLubyte src[4], void *dst) +{ + + + uint16_t a = + _mesa_unsigned_to_unsigned(src[3], 16); + + uint16_t *d = (uint16_t *)dst; + d[0] = a; +} + +static inline void +pack_ubyte_a_uint32(const GLubyte src[4], void *dst) +{ + + + uint32_t a = + _mesa_unsigned_to_unsigned(src[3], 32); + + uint32_t *d = (uint32_t *)dst; + d[0] = a; +} + +static inline void +pack_ubyte_a_sint8(const GLubyte src[4], void *dst) +{ + + + int8_t a = + _mesa_unsigned_to_signed(src[3], 8); + + int8_t *d = (int8_t *)dst; + d[0] = a; +} + +static inline void +pack_ubyte_a_sint16(const GLubyte src[4], void *dst) +{ + + + int16_t a = + _mesa_unsigned_to_signed(src[3], 16); + + int16_t *d = (int16_t *)dst; + d[0] = a; +} + +static inline void +pack_ubyte_a_sint32(const GLubyte src[4], void *dst) +{ + + + int32_t a = + _mesa_unsigned_to_signed(src[3], 32); + + int32_t *d = (int32_t *)dst; + d[0] = a; +} + +static inline void +pack_ubyte_i_uint8(const GLubyte src[4], void *dst) +{ + + + uint8_t i = + _mesa_unsigned_to_unsigned(src[0], 8); + + uint8_t *d = (uint8_t *)dst; + d[0] = i; +} + +static inline void +pack_ubyte_i_uint16(const GLubyte src[4], void *dst) +{ + + + uint16_t i = + _mesa_unsigned_to_unsigned(src[0], 16); + + uint16_t *d = (uint16_t *)dst; + d[0] = i; +} + +static inline void +pack_ubyte_i_uint32(const GLubyte src[4], void *dst) +{ + + + uint32_t i = + _mesa_unsigned_to_unsigned(src[0], 32); + + uint32_t *d = (uint32_t *)dst; + d[0] = i; +} + +static inline void +pack_ubyte_i_sint8(const GLubyte src[4], void *dst) +{ + + + int8_t i = + _mesa_unsigned_to_signed(src[0], 8); + + int8_t *d = (int8_t *)dst; + d[0] = i; +} + +static inline void +pack_ubyte_i_sint16(const GLubyte src[4], void *dst) +{ + + + int16_t i = + _mesa_unsigned_to_signed(src[0], 16); + + int16_t *d = (int16_t *)dst; + d[0] = i; +} + +static inline void +pack_ubyte_i_sint32(const GLubyte src[4], void *dst) +{ + + + int32_t i = + _mesa_unsigned_to_signed(src[0], 32); + + int32_t *d = (int32_t *)dst; + d[0] = i; +} + +static inline void +pack_ubyte_l_uint8(const GLubyte src[4], void *dst) +{ + + + uint8_t l = + _mesa_unsigned_to_unsigned(src[0], 8); + + uint8_t *d = (uint8_t *)dst; + d[0] = l; +} + +static inline void +pack_ubyte_l_uint16(const GLubyte src[4], void *dst) +{ + + + uint16_t l = + _mesa_unsigned_to_unsigned(src[0], 16); + + uint16_t *d = (uint16_t *)dst; + d[0] = l; +} + +static inline void +pack_ubyte_l_uint32(const GLubyte src[4], void *dst) +{ + + + uint32_t l = + _mesa_unsigned_to_unsigned(src[0], 32); + + uint32_t *d = (uint32_t *)dst; + d[0] = l; +} + +static inline void +pack_ubyte_l_sint8(const GLubyte src[4], void *dst) +{ + + + int8_t l = + _mesa_unsigned_to_signed(src[0], 8); + + int8_t *d = (int8_t *)dst; + d[0] = l; +} + +static inline void +pack_ubyte_l_sint16(const GLubyte src[4], void *dst) +{ + + + int16_t l = + _mesa_unsigned_to_signed(src[0], 16); + + int16_t *d = (int16_t *)dst; + d[0] = l; +} + +static inline void +pack_ubyte_l_sint32(const GLubyte src[4], void *dst) +{ + + + int32_t l = + _mesa_unsigned_to_signed(src[0], 32); + + int32_t *d = (int32_t *)dst; + d[0] = l; +} + +static inline void +pack_ubyte_la_uint8(const GLubyte src[4], void *dst) +{ + + + uint8_t l = + _mesa_unsigned_to_unsigned(src[0], 8); + + + uint8_t a = + _mesa_unsigned_to_unsigned(src[3], 8); + + uint8_t *d = (uint8_t *)dst; + d[0] = l; + d[1] = a; +} + +static inline void +pack_ubyte_la_uint16(const GLubyte src[4], void *dst) +{ + + + uint16_t l = + _mesa_unsigned_to_unsigned(src[0], 16); + + + uint16_t a = + _mesa_unsigned_to_unsigned(src[3], 16); + + uint16_t *d = (uint16_t *)dst; + d[0] = l; + d[1] = a; +} + +static inline void +pack_ubyte_la_uint32(const GLubyte src[4], void *dst) +{ + + + uint32_t l = + _mesa_unsigned_to_unsigned(src[0], 32); + + + uint32_t a = + _mesa_unsigned_to_unsigned(src[3], 32); + + uint32_t *d = (uint32_t *)dst; + d[0] = l; + d[1] = a; +} + +static inline void +pack_ubyte_la_sint8(const GLubyte src[4], void *dst) +{ + + + int8_t l = + _mesa_unsigned_to_signed(src[0], 8); + + + int8_t a = + _mesa_unsigned_to_signed(src[3], 8); + + int8_t *d = (int8_t *)dst; + d[0] = l; + d[1] = a; +} + +static inline void +pack_ubyte_la_sint16(const GLubyte src[4], void *dst) +{ + + + int16_t l = + _mesa_unsigned_to_signed(src[0], 16); + + + int16_t a = + _mesa_unsigned_to_signed(src[3], 16); + + int16_t *d = (int16_t *)dst; + d[0] = l; + d[1] = a; +} + +static inline void +pack_ubyte_la_sint32(const GLubyte src[4], void *dst) +{ + + + int32_t l = + _mesa_unsigned_to_signed(src[0], 32); + + + int32_t a = + _mesa_unsigned_to_signed(src[3], 32); + + int32_t *d = (int32_t *)dst; + d[0] = l; + d[1] = a; +} + +static inline void +pack_ubyte_r_uint8(const GLubyte src[4], void *dst) +{ + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 8); + + uint8_t *d = (uint8_t *)dst; + d[0] = r; +} + +static inline void +pack_ubyte_r_uint16(const GLubyte src[4], void *dst) +{ + + + uint16_t r = + _mesa_unsigned_to_unsigned(src[0], 16); + + uint16_t *d = (uint16_t *)dst; + d[0] = r; +} + +static inline void +pack_ubyte_r_uint32(const GLubyte src[4], void *dst) +{ + + + uint32_t r = + _mesa_unsigned_to_unsigned(src[0], 32); + + uint32_t *d = (uint32_t *)dst; + d[0] = r; +} + +static inline void +pack_ubyte_r_sint8(const GLubyte src[4], void *dst) +{ + + + int8_t r = + _mesa_unsigned_to_signed(src[0], 8); + + int8_t *d = (int8_t *)dst; + d[0] = r; +} + +static inline void +pack_ubyte_r_sint16(const GLubyte src[4], void *dst) +{ + + + int16_t r = + _mesa_unsigned_to_signed(src[0], 16); + + int16_t *d = (int16_t *)dst; + d[0] = r; +} + +static inline void +pack_ubyte_r_sint32(const GLubyte src[4], void *dst) +{ + + + int32_t r = + _mesa_unsigned_to_signed(src[0], 32); + + int32_t *d = (int32_t *)dst; + d[0] = r; +} + +static inline void +pack_ubyte_rg_uint8(const GLubyte src[4], void *dst) +{ + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 8); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 8); + + uint8_t *d = (uint8_t *)dst; + d[0] = r; + d[1] = g; +} + +static inline void +pack_ubyte_rg_uint16(const GLubyte src[4], void *dst) +{ + + + uint16_t r = + _mesa_unsigned_to_unsigned(src[0], 16); + + + uint16_t g = + _mesa_unsigned_to_unsigned(src[1], 16); + + uint16_t *d = (uint16_t *)dst; + d[0] = r; + d[1] = g; +} + +static inline void +pack_ubyte_rg_uint32(const GLubyte src[4], void *dst) +{ + + + uint32_t r = + _mesa_unsigned_to_unsigned(src[0], 32); + + + uint32_t g = + _mesa_unsigned_to_unsigned(src[1], 32); + + uint32_t *d = (uint32_t *)dst; + d[0] = r; + d[1] = g; +} + +static inline void +pack_ubyte_rg_sint8(const GLubyte src[4], void *dst) +{ + + + int8_t r = + _mesa_unsigned_to_signed(src[0], 8); + + + int8_t g = + _mesa_unsigned_to_signed(src[1], 8); + + int8_t *d = (int8_t *)dst; + d[0] = r; + d[1] = g; +} + +static inline void +pack_ubyte_rg_sint16(const GLubyte src[4], void *dst) +{ + + + int16_t r = + _mesa_unsigned_to_signed(src[0], 16); + + + int16_t g = + _mesa_unsigned_to_signed(src[1], 16); + + int16_t *d = (int16_t *)dst; + d[0] = r; + d[1] = g; +} + +static inline void +pack_ubyte_rg_sint32(const GLubyte src[4], void *dst) +{ + + + int32_t r = + _mesa_unsigned_to_signed(src[0], 32); + + + int32_t g = + _mesa_unsigned_to_signed(src[1], 32); + + int32_t *d = (int32_t *)dst; + d[0] = r; + d[1] = g; +} + +static inline void +pack_ubyte_rgb_uint8(const GLubyte src[4], void *dst) +{ + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 8); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 8); + + + uint8_t b = + _mesa_unsigned_to_unsigned(src[2], 8); + + uint8_t *d = (uint8_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; +} + +static inline void +pack_ubyte_rgb_uint16(const GLubyte src[4], void *dst) +{ + + + uint16_t r = + _mesa_unsigned_to_unsigned(src[0], 16); + + + uint16_t g = + _mesa_unsigned_to_unsigned(src[1], 16); + + + uint16_t b = + _mesa_unsigned_to_unsigned(src[2], 16); + + uint16_t *d = (uint16_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; +} + +static inline void +pack_ubyte_rgb_uint32(const GLubyte src[4], void *dst) +{ + + + uint32_t r = + _mesa_unsigned_to_unsigned(src[0], 32); + + + uint32_t g = + _mesa_unsigned_to_unsigned(src[1], 32); + + + uint32_t b = + _mesa_unsigned_to_unsigned(src[2], 32); + + uint32_t *d = (uint32_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; +} + +static inline void +pack_ubyte_rgb_sint8(const GLubyte src[4], void *dst) +{ + + + int8_t r = + _mesa_unsigned_to_signed(src[0], 8); + + + int8_t g = + _mesa_unsigned_to_signed(src[1], 8); + + + int8_t b = + _mesa_unsigned_to_signed(src[2], 8); + + int8_t *d = (int8_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; +} + +static inline void +pack_ubyte_rgb_sint16(const GLubyte src[4], void *dst) +{ + + + int16_t r = + _mesa_unsigned_to_signed(src[0], 16); + + + int16_t g = + _mesa_unsigned_to_signed(src[1], 16); + + + int16_t b = + _mesa_unsigned_to_signed(src[2], 16); + + int16_t *d = (int16_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; +} + +static inline void +pack_ubyte_rgb_sint32(const GLubyte src[4], void *dst) +{ + + + int32_t r = + _mesa_unsigned_to_signed(src[0], 32); + + + int32_t g = + _mesa_unsigned_to_signed(src[1], 32); + + + int32_t b = + _mesa_unsigned_to_signed(src[2], 32); + + int32_t *d = (int32_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; +} + +static inline void +pack_ubyte_rgba_uint8(const GLubyte src[4], void *dst) +{ + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 8); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 8); + + + uint8_t b = + _mesa_unsigned_to_unsigned(src[2], 8); + + + uint8_t a = + _mesa_unsigned_to_unsigned(src[3], 8); + + uint8_t *d = (uint8_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + d[3] = a; +} + +static inline void +pack_ubyte_rgba_uint16(const GLubyte src[4], void *dst) +{ + + + uint16_t r = + _mesa_unsigned_to_unsigned(src[0], 16); + + + uint16_t g = + _mesa_unsigned_to_unsigned(src[1], 16); + + + uint16_t b = + _mesa_unsigned_to_unsigned(src[2], 16); + + + uint16_t a = + _mesa_unsigned_to_unsigned(src[3], 16); + + uint16_t *d = (uint16_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + d[3] = a; +} + +static inline void +pack_ubyte_rgba_uint32(const GLubyte src[4], void *dst) +{ + + + uint32_t r = + _mesa_unsigned_to_unsigned(src[0], 32); + + + uint32_t g = + _mesa_unsigned_to_unsigned(src[1], 32); + + + uint32_t b = + _mesa_unsigned_to_unsigned(src[2], 32); + + + uint32_t a = + _mesa_unsigned_to_unsigned(src[3], 32); + + uint32_t *d = (uint32_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + d[3] = a; +} + +static inline void +pack_ubyte_rgba_sint8(const GLubyte src[4], void *dst) +{ + + + int8_t r = + _mesa_unsigned_to_signed(src[0], 8); + + + int8_t g = + _mesa_unsigned_to_signed(src[1], 8); + + + int8_t b = + _mesa_unsigned_to_signed(src[2], 8); + + + int8_t a = + _mesa_unsigned_to_signed(src[3], 8); + + int8_t *d = (int8_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + d[3] = a; +} + +static inline void +pack_ubyte_rgba_sint16(const GLubyte src[4], void *dst) +{ + + + int16_t r = + _mesa_unsigned_to_signed(src[0], 16); + + + int16_t g = + _mesa_unsigned_to_signed(src[1], 16); + + + int16_t b = + _mesa_unsigned_to_signed(src[2], 16); + + + int16_t a = + _mesa_unsigned_to_signed(src[3], 16); + + int16_t *d = (int16_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + d[3] = a; +} + +static inline void +pack_ubyte_rgba_sint32(const GLubyte src[4], void *dst) +{ + + + int32_t r = + _mesa_unsigned_to_signed(src[0], 32); + + + int32_t g = + _mesa_unsigned_to_signed(src[1], 32); + + + int32_t b = + _mesa_unsigned_to_signed(src[2], 32); + + + int32_t a = + _mesa_unsigned_to_signed(src[3], 32); + + int32_t *d = (int32_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + d[3] = a; +} + +static inline void +pack_ubyte_rgbx_uint8(const GLubyte src[4], void *dst) +{ + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 8); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 8); + + + uint8_t b = + _mesa_unsigned_to_unsigned(src[2], 8); + + + uint8_t *d = (uint8_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + } + +static inline void +pack_ubyte_rgbx_uint16(const GLubyte src[4], void *dst) +{ + + + uint16_t r = + _mesa_unsigned_to_unsigned(src[0], 16); + + + uint16_t g = + _mesa_unsigned_to_unsigned(src[1], 16); + + + uint16_t b = + _mesa_unsigned_to_unsigned(src[2], 16); + + + uint16_t *d = (uint16_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + } + +static inline void +pack_ubyte_rgbx_uint32(const GLubyte src[4], void *dst) +{ + + + uint32_t r = + _mesa_unsigned_to_unsigned(src[0], 32); + + + uint32_t g = + _mesa_unsigned_to_unsigned(src[1], 32); + + + uint32_t b = + _mesa_unsigned_to_unsigned(src[2], 32); + + + uint32_t *d = (uint32_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + } + +static inline void +pack_ubyte_rgbx_sint8(const GLubyte src[4], void *dst) +{ + + + int8_t r = + _mesa_unsigned_to_signed(src[0], 8); + + + int8_t g = + _mesa_unsigned_to_signed(src[1], 8); + + + int8_t b = + _mesa_unsigned_to_signed(src[2], 8); + + + int8_t *d = (int8_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + } + +static inline void +pack_ubyte_rgbx_sint16(const GLubyte src[4], void *dst) +{ + + + int16_t r = + _mesa_unsigned_to_signed(src[0], 16); + + + int16_t g = + _mesa_unsigned_to_signed(src[1], 16); + + + int16_t b = + _mesa_unsigned_to_signed(src[2], 16); + + + int16_t *d = (int16_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + } + +static inline void +pack_ubyte_rgbx_sint32(const GLubyte src[4], void *dst) +{ + + + int32_t r = + _mesa_unsigned_to_signed(src[0], 32); + + + int32_t g = + _mesa_unsigned_to_signed(src[1], 32); + + + int32_t b = + _mesa_unsigned_to_signed(src[2], 32); + + + int32_t *d = (int32_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + } + +static inline void +pack_ubyte_r9g9b9e5_float(const GLubyte src[4], void *dst) +{ + GLuint *d = (GLuint *) dst; + GLfloat rgb[3]; + rgb[0] = _mesa_unorm_to_float(src[RCOMP], 8); + rgb[1] = _mesa_unorm_to_float(src[GCOMP], 8); + rgb[2] = _mesa_unorm_to_float(src[BCOMP], 8); + *d = float3_to_rgb9e5(rgb); +} + +static inline void +pack_ubyte_r11g11b10_float(const GLubyte src[4], void *dst) +{ + GLuint *d = (GLuint *) dst; + GLfloat rgb[3]; + rgb[0] = _mesa_unorm_to_float(src[RCOMP], 8); + rgb[1] = _mesa_unorm_to_float(src[GCOMP], 8); + rgb[2] = _mesa_unorm_to_float(src[BCOMP], 8); + *d = float3_to_r11g11b10f(rgb); +} + +/* uint packing functions */ + + +static inline void +pack_uint_a8b8g8r8_uint(const GLuint src[4], void *dst) +{ + + + uint8_t a = + _mesa_unsigned_to_unsigned(src[3], 8); + + + uint8_t b = + _mesa_unsigned_to_unsigned(src[2], 8); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 8); + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 8); + + uint32_t d = 0; + d |= PACK(a, 0, 8); + d |= PACK(b, 8, 8); + d |= PACK(g, 16, 8); + d |= PACK(r, 24, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_uint_a8r8g8b8_uint(const GLuint src[4], void *dst) +{ + + + uint8_t a = + _mesa_unsigned_to_unsigned(src[3], 8); + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 8); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 8); + + + uint8_t b = + _mesa_unsigned_to_unsigned(src[2], 8); + + uint32_t d = 0; + d |= PACK(a, 0, 8); + d |= PACK(r, 8, 8); + d |= PACK(g, 16, 8); + d |= PACK(b, 24, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_uint_r8g8b8a8_uint(const GLuint src[4], void *dst) +{ + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 8); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 8); + + + uint8_t b = + _mesa_unsigned_to_unsigned(src[2], 8); + + + uint8_t a = + _mesa_unsigned_to_unsigned(src[3], 8); + + uint32_t d = 0; + d |= PACK(r, 0, 8); + d |= PACK(g, 8, 8); + d |= PACK(b, 16, 8); + d |= PACK(a, 24, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_uint_b8g8r8a8_uint(const GLuint src[4], void *dst) +{ + + + uint8_t b = + _mesa_unsigned_to_unsigned(src[2], 8); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 8); + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 8); + + + uint8_t a = + _mesa_unsigned_to_unsigned(src[3], 8); + + uint32_t d = 0; + d |= PACK(b, 0, 8); + d |= PACK(g, 8, 8); + d |= PACK(r, 16, 8); + d |= PACK(a, 24, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_uint_b10g10r10a2_uint(const GLuint src[4], void *dst) +{ + + + uint16_t b = + _mesa_unsigned_to_unsigned(src[2], 10); + + + uint16_t g = + _mesa_unsigned_to_unsigned(src[1], 10); + + + uint16_t r = + _mesa_unsigned_to_unsigned(src[0], 10); + + + uint8_t a = + _mesa_unsigned_to_unsigned(src[3], 2); + + uint32_t d = 0; + d |= PACK(b, 0, 10); + d |= PACK(g, 10, 10); + d |= PACK(r, 20, 10); + d |= PACK(a, 30, 2); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_uint_r10g10b10a2_uint(const GLuint src[4], void *dst) +{ + + + uint16_t r = + _mesa_unsigned_to_unsigned(src[0], 10); + + + uint16_t g = + _mesa_unsigned_to_unsigned(src[1], 10); + + + uint16_t b = + _mesa_unsigned_to_unsigned(src[2], 10); + + + uint8_t a = + _mesa_unsigned_to_unsigned(src[3], 2); + + uint32_t d = 0; + d |= PACK(r, 0, 10); + d |= PACK(g, 10, 10); + d |= PACK(b, 20, 10); + d |= PACK(a, 30, 2); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_uint_a2b10g10r10_uint(const GLuint src[4], void *dst) +{ + + + uint8_t a = + _mesa_unsigned_to_unsigned(src[3], 2); + + + uint16_t b = + _mesa_unsigned_to_unsigned(src[2], 10); + + + uint16_t g = + _mesa_unsigned_to_unsigned(src[1], 10); + + + uint16_t r = + _mesa_unsigned_to_unsigned(src[0], 10); + + uint32_t d = 0; + d |= PACK(a, 0, 2); + d |= PACK(b, 2, 10); + d |= PACK(g, 12, 10); + d |= PACK(r, 22, 10); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_uint_a2r10g10b10_uint(const GLuint src[4], void *dst) +{ + + + uint8_t a = + _mesa_unsigned_to_unsigned(src[3], 2); + + + uint16_t r = + _mesa_unsigned_to_unsigned(src[0], 10); + + + uint16_t g = + _mesa_unsigned_to_unsigned(src[1], 10); + + + uint16_t b = + _mesa_unsigned_to_unsigned(src[2], 10); + + uint32_t d = 0; + d |= PACK(a, 0, 2); + d |= PACK(r, 2, 10); + d |= PACK(g, 12, 10); + d |= PACK(b, 22, 10); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_uint_b5g6r5_uint(const GLuint src[4], void *dst) +{ + + + uint8_t b = + _mesa_unsigned_to_unsigned(src[2], 5); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 6); + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 5); + + uint16_t d = 0; + d |= PACK(b, 0, 5); + d |= PACK(g, 5, 6); + d |= PACK(r, 11, 5); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_uint_r5g6b5_uint(const GLuint src[4], void *dst) +{ + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 5); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 6); + + + uint8_t b = + _mesa_unsigned_to_unsigned(src[2], 5); + + uint16_t d = 0; + d |= PACK(r, 0, 5); + d |= PACK(g, 5, 6); + d |= PACK(b, 11, 5); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_uint_b2g3r3_uint(const GLuint src[4], void *dst) +{ + + + uint8_t b = + _mesa_unsigned_to_unsigned(src[2], 2); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 3); + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 3); + + uint8_t d = 0; + d |= PACK(b, 0, 2); + d |= PACK(g, 2, 3); + d |= PACK(r, 5, 3); + (*(uint8_t *)dst) = d; +} + +static inline void +pack_uint_r3g3b2_uint(const GLuint src[4], void *dst) +{ + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 3); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 3); + + + uint8_t b = + _mesa_unsigned_to_unsigned(src[2], 2); + + uint8_t d = 0; + d |= PACK(r, 0, 3); + d |= PACK(g, 3, 3); + d |= PACK(b, 6, 2); + (*(uint8_t *)dst) = d; +} + +static inline void +pack_uint_a4b4g4r4_uint(const GLuint src[4], void *dst) +{ + + + uint8_t a = + _mesa_unsigned_to_unsigned(src[3], 4); + + + uint8_t b = + _mesa_unsigned_to_unsigned(src[2], 4); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 4); + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 4); + + uint16_t d = 0; + d |= PACK(a, 0, 4); + d |= PACK(b, 4, 4); + d |= PACK(g, 8, 4); + d |= PACK(r, 12, 4); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_uint_r4g4b4a4_uint(const GLuint src[4], void *dst) +{ + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 4); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 4); + + + uint8_t b = + _mesa_unsigned_to_unsigned(src[2], 4); + + + uint8_t a = + _mesa_unsigned_to_unsigned(src[3], 4); + + uint16_t d = 0; + d |= PACK(r, 0, 4); + d |= PACK(g, 4, 4); + d |= PACK(b, 8, 4); + d |= PACK(a, 12, 4); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_uint_b4g4r4a4_uint(const GLuint src[4], void *dst) +{ + + + uint8_t b = + _mesa_unsigned_to_unsigned(src[2], 4); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 4); + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 4); + + + uint8_t a = + _mesa_unsigned_to_unsigned(src[3], 4); + + uint16_t d = 0; + d |= PACK(b, 0, 4); + d |= PACK(g, 4, 4); + d |= PACK(r, 8, 4); + d |= PACK(a, 12, 4); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_uint_a4r4g4b4_uint(const GLuint src[4], void *dst) +{ + + + uint8_t a = + _mesa_unsigned_to_unsigned(src[3], 4); + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 4); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 4); + + + uint8_t b = + _mesa_unsigned_to_unsigned(src[2], 4); + + uint16_t d = 0; + d |= PACK(a, 0, 4); + d |= PACK(r, 4, 4); + d |= PACK(g, 8, 4); + d |= PACK(b, 12, 4); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_uint_a1b5g5r5_uint(const GLuint src[4], void *dst) +{ + + + uint8_t a = + _mesa_unsigned_to_unsigned(src[3], 1); + + + uint8_t b = + _mesa_unsigned_to_unsigned(src[2], 5); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 5); + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 5); + + uint16_t d = 0; + d |= PACK(a, 0, 1); + d |= PACK(b, 1, 5); + d |= PACK(g, 6, 5); + d |= PACK(r, 11, 5); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_uint_b5g5r5a1_uint(const GLuint src[4], void *dst) +{ + + + uint8_t b = + _mesa_unsigned_to_unsigned(src[2], 5); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 5); + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 5); + + + uint8_t a = + _mesa_unsigned_to_unsigned(src[3], 1); + + uint16_t d = 0; + d |= PACK(b, 0, 5); + d |= PACK(g, 5, 5); + d |= PACK(r, 10, 5); + d |= PACK(a, 15, 1); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_uint_a1r5g5b5_uint(const GLuint src[4], void *dst) +{ + + + uint8_t a = + _mesa_unsigned_to_unsigned(src[3], 1); + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 5); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 5); + + + uint8_t b = + _mesa_unsigned_to_unsigned(src[2], 5); + + uint16_t d = 0; + d |= PACK(a, 0, 1); + d |= PACK(r, 1, 5); + d |= PACK(g, 6, 5); + d |= PACK(b, 11, 5); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_uint_r5g5b5a1_uint(const GLuint src[4], void *dst) +{ + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 5); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 5); + + + uint8_t b = + _mesa_unsigned_to_unsigned(src[2], 5); + + + uint8_t a = + _mesa_unsigned_to_unsigned(src[3], 1); + + uint16_t d = 0; + d |= PACK(r, 0, 5); + d |= PACK(g, 5, 5); + d |= PACK(b, 10, 5); + d |= PACK(a, 15, 1); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_uint_a_uint8(const GLuint src[4], void *dst) +{ + + + uint8_t a = + _mesa_unsigned_to_unsigned(src[3], 8); + + uint8_t *d = (uint8_t *)dst; + d[0] = a; +} + +static inline void +pack_uint_a_uint16(const GLuint src[4], void *dst) +{ + + + uint16_t a = + _mesa_unsigned_to_unsigned(src[3], 16); + + uint16_t *d = (uint16_t *)dst; + d[0] = a; +} + +static inline void +pack_uint_a_uint32(const GLuint src[4], void *dst) +{ + + + uint32_t a = + _mesa_unsigned_to_unsigned(src[3], 32); + + uint32_t *d = (uint32_t *)dst; + d[0] = a; +} + +static inline void +pack_uint_a_sint8(const GLuint src[4], void *dst) +{ + + + int8_t a = + _mesa_signed_to_signed(src[3], 8); + + int8_t *d = (int8_t *)dst; + d[0] = a; +} + +static inline void +pack_uint_a_sint16(const GLuint src[4], void *dst) +{ + + + int16_t a = + _mesa_signed_to_signed(src[3], 16); + + int16_t *d = (int16_t *)dst; + d[0] = a; +} + +static inline void +pack_uint_a_sint32(const GLuint src[4], void *dst) +{ + + + int32_t a = + _mesa_signed_to_signed(src[3], 32); + + int32_t *d = (int32_t *)dst; + d[0] = a; +} + +static inline void +pack_uint_i_uint8(const GLuint src[4], void *dst) +{ + + + uint8_t i = + _mesa_unsigned_to_unsigned(src[0], 8); + + uint8_t *d = (uint8_t *)dst; + d[0] = i; +} + +static inline void +pack_uint_i_uint16(const GLuint src[4], void *dst) +{ + + + uint16_t i = + _mesa_unsigned_to_unsigned(src[0], 16); + + uint16_t *d = (uint16_t *)dst; + d[0] = i; +} + +static inline void +pack_uint_i_uint32(const GLuint src[4], void *dst) +{ + + + uint32_t i = + _mesa_unsigned_to_unsigned(src[0], 32); + + uint32_t *d = (uint32_t *)dst; + d[0] = i; +} + +static inline void +pack_uint_i_sint8(const GLuint src[4], void *dst) +{ + + + int8_t i = + _mesa_signed_to_signed(src[0], 8); + + int8_t *d = (int8_t *)dst; + d[0] = i; +} + +static inline void +pack_uint_i_sint16(const GLuint src[4], void *dst) +{ + + + int16_t i = + _mesa_signed_to_signed(src[0], 16); + + int16_t *d = (int16_t *)dst; + d[0] = i; +} + +static inline void +pack_uint_i_sint32(const GLuint src[4], void *dst) +{ + + + int32_t i = + _mesa_signed_to_signed(src[0], 32); + + int32_t *d = (int32_t *)dst; + d[0] = i; +} + +static inline void +pack_uint_l_uint8(const GLuint src[4], void *dst) +{ + + + uint8_t l = + _mesa_unsigned_to_unsigned(src[0], 8); + + uint8_t *d = (uint8_t *)dst; + d[0] = l; +} + +static inline void +pack_uint_l_uint16(const GLuint src[4], void *dst) +{ + + + uint16_t l = + _mesa_unsigned_to_unsigned(src[0], 16); + + uint16_t *d = (uint16_t *)dst; + d[0] = l; +} + +static inline void +pack_uint_l_uint32(const GLuint src[4], void *dst) +{ + + + uint32_t l = + _mesa_unsigned_to_unsigned(src[0], 32); + + uint32_t *d = (uint32_t *)dst; + d[0] = l; +} + +static inline void +pack_uint_l_sint8(const GLuint src[4], void *dst) +{ + + + int8_t l = + _mesa_signed_to_signed(src[0], 8); + + int8_t *d = (int8_t *)dst; + d[0] = l; +} + +static inline void +pack_uint_l_sint16(const GLuint src[4], void *dst) +{ + + + int16_t l = + _mesa_signed_to_signed(src[0], 16); + + int16_t *d = (int16_t *)dst; + d[0] = l; +} + +static inline void +pack_uint_l_sint32(const GLuint src[4], void *dst) +{ + + + int32_t l = + _mesa_signed_to_signed(src[0], 32); + + int32_t *d = (int32_t *)dst; + d[0] = l; +} + +static inline void +pack_uint_la_uint8(const GLuint src[4], void *dst) +{ + + + uint8_t l = + _mesa_unsigned_to_unsigned(src[0], 8); + + + uint8_t a = + _mesa_unsigned_to_unsigned(src[3], 8); + + uint8_t *d = (uint8_t *)dst; + d[0] = l; + d[1] = a; +} + +static inline void +pack_uint_la_uint16(const GLuint src[4], void *dst) +{ + + + uint16_t l = + _mesa_unsigned_to_unsigned(src[0], 16); + + + uint16_t a = + _mesa_unsigned_to_unsigned(src[3], 16); + + uint16_t *d = (uint16_t *)dst; + d[0] = l; + d[1] = a; +} + +static inline void +pack_uint_la_uint32(const GLuint src[4], void *dst) +{ + + + uint32_t l = + _mesa_unsigned_to_unsigned(src[0], 32); + + + uint32_t a = + _mesa_unsigned_to_unsigned(src[3], 32); + + uint32_t *d = (uint32_t *)dst; + d[0] = l; + d[1] = a; +} + +static inline void +pack_uint_la_sint8(const GLuint src[4], void *dst) +{ + + + int8_t l = + _mesa_signed_to_signed(src[0], 8); + + + int8_t a = + _mesa_signed_to_signed(src[3], 8); + + int8_t *d = (int8_t *)dst; + d[0] = l; + d[1] = a; +} + +static inline void +pack_uint_la_sint16(const GLuint src[4], void *dst) +{ + + + int16_t l = + _mesa_signed_to_signed(src[0], 16); + + + int16_t a = + _mesa_signed_to_signed(src[3], 16); + + int16_t *d = (int16_t *)dst; + d[0] = l; + d[1] = a; +} + +static inline void +pack_uint_la_sint32(const GLuint src[4], void *dst) +{ + + + int32_t l = + _mesa_signed_to_signed(src[0], 32); + + + int32_t a = + _mesa_signed_to_signed(src[3], 32); + + int32_t *d = (int32_t *)dst; + d[0] = l; + d[1] = a; +} + +static inline void +pack_uint_r_uint8(const GLuint src[4], void *dst) +{ + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 8); + + uint8_t *d = (uint8_t *)dst; + d[0] = r; +} + +static inline void +pack_uint_r_uint16(const GLuint src[4], void *dst) +{ + + + uint16_t r = + _mesa_unsigned_to_unsigned(src[0], 16); + + uint16_t *d = (uint16_t *)dst; + d[0] = r; +} + +static inline void +pack_uint_r_uint32(const GLuint src[4], void *dst) +{ + + + uint32_t r = + _mesa_unsigned_to_unsigned(src[0], 32); + + uint32_t *d = (uint32_t *)dst; + d[0] = r; +} + +static inline void +pack_uint_r_sint8(const GLuint src[4], void *dst) +{ + + + int8_t r = + _mesa_signed_to_signed(src[0], 8); + + int8_t *d = (int8_t *)dst; + d[0] = r; +} + +static inline void +pack_uint_r_sint16(const GLuint src[4], void *dst) +{ + + + int16_t r = + _mesa_signed_to_signed(src[0], 16); + + int16_t *d = (int16_t *)dst; + d[0] = r; +} + +static inline void +pack_uint_r_sint32(const GLuint src[4], void *dst) +{ + + + int32_t r = + _mesa_signed_to_signed(src[0], 32); + + int32_t *d = (int32_t *)dst; + d[0] = r; +} + +static inline void +pack_uint_rg_uint8(const GLuint src[4], void *dst) +{ + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 8); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 8); + + uint8_t *d = (uint8_t *)dst; + d[0] = r; + d[1] = g; +} + +static inline void +pack_uint_rg_uint16(const GLuint src[4], void *dst) +{ + + + uint16_t r = + _mesa_unsigned_to_unsigned(src[0], 16); + + + uint16_t g = + _mesa_unsigned_to_unsigned(src[1], 16); + + uint16_t *d = (uint16_t *)dst; + d[0] = r; + d[1] = g; +} + +static inline void +pack_uint_rg_uint32(const GLuint src[4], void *dst) +{ + + + uint32_t r = + _mesa_unsigned_to_unsigned(src[0], 32); + + + uint32_t g = + _mesa_unsigned_to_unsigned(src[1], 32); + + uint32_t *d = (uint32_t *)dst; + d[0] = r; + d[1] = g; +} + +static inline void +pack_uint_rg_sint8(const GLuint src[4], void *dst) +{ + + + int8_t r = + _mesa_signed_to_signed(src[0], 8); + + + int8_t g = + _mesa_signed_to_signed(src[1], 8); + + int8_t *d = (int8_t *)dst; + d[0] = r; + d[1] = g; +} + +static inline void +pack_uint_rg_sint16(const GLuint src[4], void *dst) +{ + + + int16_t r = + _mesa_signed_to_signed(src[0], 16); + + + int16_t g = + _mesa_signed_to_signed(src[1], 16); + + int16_t *d = (int16_t *)dst; + d[0] = r; + d[1] = g; +} + +static inline void +pack_uint_rg_sint32(const GLuint src[4], void *dst) +{ + + + int32_t r = + _mesa_signed_to_signed(src[0], 32); + + + int32_t g = + _mesa_signed_to_signed(src[1], 32); + + int32_t *d = (int32_t *)dst; + d[0] = r; + d[1] = g; +} + +static inline void +pack_uint_rgb_uint8(const GLuint src[4], void *dst) +{ + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 8); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 8); + + + uint8_t b = + _mesa_unsigned_to_unsigned(src[2], 8); + + uint8_t *d = (uint8_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; +} + +static inline void +pack_uint_rgb_uint16(const GLuint src[4], void *dst) +{ + + + uint16_t r = + _mesa_unsigned_to_unsigned(src[0], 16); + + + uint16_t g = + _mesa_unsigned_to_unsigned(src[1], 16); + + + uint16_t b = + _mesa_unsigned_to_unsigned(src[2], 16); + + uint16_t *d = (uint16_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; +} + +static inline void +pack_uint_rgb_uint32(const GLuint src[4], void *dst) +{ + + + uint32_t r = + _mesa_unsigned_to_unsigned(src[0], 32); + + + uint32_t g = + _mesa_unsigned_to_unsigned(src[1], 32); + + + uint32_t b = + _mesa_unsigned_to_unsigned(src[2], 32); + + uint32_t *d = (uint32_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; +} + +static inline void +pack_uint_rgb_sint8(const GLuint src[4], void *dst) +{ + + + int8_t r = + _mesa_signed_to_signed(src[0], 8); + + + int8_t g = + _mesa_signed_to_signed(src[1], 8); + + + int8_t b = + _mesa_signed_to_signed(src[2], 8); + + int8_t *d = (int8_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; +} + +static inline void +pack_uint_rgb_sint16(const GLuint src[4], void *dst) +{ + + + int16_t r = + _mesa_signed_to_signed(src[0], 16); + + + int16_t g = + _mesa_signed_to_signed(src[1], 16); + + + int16_t b = + _mesa_signed_to_signed(src[2], 16); + + int16_t *d = (int16_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; +} + +static inline void +pack_uint_rgb_sint32(const GLuint src[4], void *dst) +{ + + + int32_t r = + _mesa_signed_to_signed(src[0], 32); + + + int32_t g = + _mesa_signed_to_signed(src[1], 32); + + + int32_t b = + _mesa_signed_to_signed(src[2], 32); + + int32_t *d = (int32_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; +} + +static inline void +pack_uint_rgba_uint8(const GLuint src[4], void *dst) +{ + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 8); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 8); + + + uint8_t b = + _mesa_unsigned_to_unsigned(src[2], 8); + + + uint8_t a = + _mesa_unsigned_to_unsigned(src[3], 8); + + uint8_t *d = (uint8_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + d[3] = a; +} + +static inline void +pack_uint_rgba_uint16(const GLuint src[4], void *dst) +{ + + + uint16_t r = + _mesa_unsigned_to_unsigned(src[0], 16); + + + uint16_t g = + _mesa_unsigned_to_unsigned(src[1], 16); + + + uint16_t b = + _mesa_unsigned_to_unsigned(src[2], 16); + + + uint16_t a = + _mesa_unsigned_to_unsigned(src[3], 16); + + uint16_t *d = (uint16_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + d[3] = a; +} + +static inline void +pack_uint_rgba_uint32(const GLuint src[4], void *dst) +{ + + + uint32_t r = + _mesa_unsigned_to_unsigned(src[0], 32); + + + uint32_t g = + _mesa_unsigned_to_unsigned(src[1], 32); + + + uint32_t b = + _mesa_unsigned_to_unsigned(src[2], 32); + + + uint32_t a = + _mesa_unsigned_to_unsigned(src[3], 32); + + uint32_t *d = (uint32_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + d[3] = a; +} + +static inline void +pack_uint_rgba_sint8(const GLuint src[4], void *dst) +{ + + + int8_t r = + _mesa_signed_to_signed(src[0], 8); + + + int8_t g = + _mesa_signed_to_signed(src[1], 8); + + + int8_t b = + _mesa_signed_to_signed(src[2], 8); + + + int8_t a = + _mesa_signed_to_signed(src[3], 8); + + int8_t *d = (int8_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + d[3] = a; +} + +static inline void +pack_uint_rgba_sint16(const GLuint src[4], void *dst) +{ + + + int16_t r = + _mesa_signed_to_signed(src[0], 16); + + + int16_t g = + _mesa_signed_to_signed(src[1], 16); + + + int16_t b = + _mesa_signed_to_signed(src[2], 16); + + + int16_t a = + _mesa_signed_to_signed(src[3], 16); + + int16_t *d = (int16_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + d[3] = a; +} + +static inline void +pack_uint_rgba_sint32(const GLuint src[4], void *dst) +{ + + + int32_t r = + _mesa_signed_to_signed(src[0], 32); + + + int32_t g = + _mesa_signed_to_signed(src[1], 32); + + + int32_t b = + _mesa_signed_to_signed(src[2], 32); + + + int32_t a = + _mesa_signed_to_signed(src[3], 32); + + int32_t *d = (int32_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + d[3] = a; +} + +static inline void +pack_uint_rgbx_uint8(const GLuint src[4], void *dst) +{ + + + uint8_t r = + _mesa_unsigned_to_unsigned(src[0], 8); + + + uint8_t g = + _mesa_unsigned_to_unsigned(src[1], 8); + + + uint8_t b = + _mesa_unsigned_to_unsigned(src[2], 8); + + + uint8_t *d = (uint8_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + } + +static inline void +pack_uint_rgbx_uint16(const GLuint src[4], void *dst) +{ + + + uint16_t r = + _mesa_unsigned_to_unsigned(src[0], 16); + + + uint16_t g = + _mesa_unsigned_to_unsigned(src[1], 16); + + + uint16_t b = + _mesa_unsigned_to_unsigned(src[2], 16); + + + uint16_t *d = (uint16_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + } + +static inline void +pack_uint_rgbx_uint32(const GLuint src[4], void *dst) +{ + + + uint32_t r = + _mesa_unsigned_to_unsigned(src[0], 32); + + + uint32_t g = + _mesa_unsigned_to_unsigned(src[1], 32); + + + uint32_t b = + _mesa_unsigned_to_unsigned(src[2], 32); + + + uint32_t *d = (uint32_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + } + +static inline void +pack_uint_rgbx_sint8(const GLuint src[4], void *dst) +{ + + + int8_t r = + _mesa_signed_to_signed(src[0], 8); + + + int8_t g = + _mesa_signed_to_signed(src[1], 8); + + + int8_t b = + _mesa_signed_to_signed(src[2], 8); + + + int8_t *d = (int8_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + } + +static inline void +pack_uint_rgbx_sint16(const GLuint src[4], void *dst) +{ + + + int16_t r = + _mesa_signed_to_signed(src[0], 16); + + + int16_t g = + _mesa_signed_to_signed(src[1], 16); + + + int16_t b = + _mesa_signed_to_signed(src[2], 16); + + + int16_t *d = (int16_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + } + +static inline void +pack_uint_rgbx_sint32(const GLuint src[4], void *dst) +{ + + + int32_t r = + _mesa_signed_to_signed(src[0], 32); + + + int32_t g = + _mesa_signed_to_signed(src[1], 32); + + + int32_t b = + _mesa_signed_to_signed(src[2], 32); + + + int32_t *d = (int32_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + } + +/* float packing functions */ + + +static inline void +pack_float_a8b8g8r8_unorm(const GLfloat src[4], void *dst) +{ + + + uint8_t a = + _mesa_float_to_unorm(src[3], 8); + + + uint8_t b = + _mesa_float_to_unorm(src[2], 8); + + + uint8_t g = + _mesa_float_to_unorm(src[1], 8); + + + uint8_t r = + _mesa_float_to_unorm(src[0], 8); + + uint32_t d = 0; + d |= PACK(a, 0, 8); + d |= PACK(b, 8, 8); + d |= PACK(g, 16, 8); + d |= PACK(r, 24, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_float_x8b8g8r8_unorm(const GLfloat src[4], void *dst) +{ + + + + uint8_t b = + _mesa_float_to_unorm(src[2], 8); + + + uint8_t g = + _mesa_float_to_unorm(src[1], 8); + + + uint8_t r = + _mesa_float_to_unorm(src[0], 8); + + uint32_t d = 0; + d |= PACK(b, 8, 8); + d |= PACK(g, 16, 8); + d |= PACK(r, 24, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_float_r8g8b8a8_unorm(const GLfloat src[4], void *dst) +{ + + + uint8_t r = + _mesa_float_to_unorm(src[0], 8); + + + uint8_t g = + _mesa_float_to_unorm(src[1], 8); + + + uint8_t b = + _mesa_float_to_unorm(src[2], 8); + + + uint8_t a = + _mesa_float_to_unorm(src[3], 8); + + uint32_t d = 0; + d |= PACK(r, 0, 8); + d |= PACK(g, 8, 8); + d |= PACK(b, 16, 8); + d |= PACK(a, 24, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_float_r8g8b8x8_unorm(const GLfloat src[4], void *dst) +{ + + + uint8_t r = + _mesa_float_to_unorm(src[0], 8); + + + uint8_t g = + _mesa_float_to_unorm(src[1], 8); + + + uint8_t b = + _mesa_float_to_unorm(src[2], 8); + + + uint32_t d = 0; + d |= PACK(r, 0, 8); + d |= PACK(g, 8, 8); + d |= PACK(b, 16, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_float_b8g8r8a8_unorm(const GLfloat src[4], void *dst) +{ + + + uint8_t b = + _mesa_float_to_unorm(src[2], 8); + + + uint8_t g = + _mesa_float_to_unorm(src[1], 8); + + + uint8_t r = + _mesa_float_to_unorm(src[0], 8); + + + uint8_t a = + _mesa_float_to_unorm(src[3], 8); + + uint32_t d = 0; + d |= PACK(b, 0, 8); + d |= PACK(g, 8, 8); + d |= PACK(r, 16, 8); + d |= PACK(a, 24, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_float_b8g8r8x8_unorm(const GLfloat src[4], void *dst) +{ + + + uint8_t b = + _mesa_float_to_unorm(src[2], 8); + + + uint8_t g = + _mesa_float_to_unorm(src[1], 8); + + + uint8_t r = + _mesa_float_to_unorm(src[0], 8); + + + uint32_t d = 0; + d |= PACK(b, 0, 8); + d |= PACK(g, 8, 8); + d |= PACK(r, 16, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_float_a8r8g8b8_unorm(const GLfloat src[4], void *dst) +{ + + + uint8_t a = + _mesa_float_to_unorm(src[3], 8); + + + uint8_t r = + _mesa_float_to_unorm(src[0], 8); + + + uint8_t g = + _mesa_float_to_unorm(src[1], 8); + + + uint8_t b = + _mesa_float_to_unorm(src[2], 8); + + uint32_t d = 0; + d |= PACK(a, 0, 8); + d |= PACK(r, 8, 8); + d |= PACK(g, 16, 8); + d |= PACK(b, 24, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_float_x8r8g8b8_unorm(const GLfloat src[4], void *dst) +{ + + + + uint8_t r = + _mesa_float_to_unorm(src[0], 8); + + + uint8_t g = + _mesa_float_to_unorm(src[1], 8); + + + uint8_t b = + _mesa_float_to_unorm(src[2], 8); + + uint32_t d = 0; + d |= PACK(r, 8, 8); + d |= PACK(g, 16, 8); + d |= PACK(b, 24, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_float_l16a16_unorm(const GLfloat src[4], void *dst) +{ + + + uint16_t l = + _mesa_float_to_unorm(src[0], 16); + + + uint16_t a = + _mesa_float_to_unorm(src[3], 16); + + uint32_t d = 0; + d |= PACK(l, 0, 16); + d |= PACK(a, 16, 16); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_float_a16l16_unorm(const GLfloat src[4], void *dst) +{ + + + uint16_t a = + _mesa_float_to_unorm(src[3], 16); + + + uint16_t l = + _mesa_float_to_unorm(src[0], 16); + + uint32_t d = 0; + d |= PACK(a, 0, 16); + d |= PACK(l, 16, 16); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_float_b5g6r5_unorm(const GLfloat src[4], void *dst) +{ + + + uint8_t b = + _mesa_float_to_unorm(src[2], 5); + + + uint8_t g = + _mesa_float_to_unorm(src[1], 6); + + + uint8_t r = + _mesa_float_to_unorm(src[0], 5); + + uint16_t d = 0; + d |= PACK(b, 0, 5); + d |= PACK(g, 5, 6); + d |= PACK(r, 11, 5); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_float_r5g6b5_unorm(const GLfloat src[4], void *dst) +{ + + + uint8_t r = + _mesa_float_to_unorm(src[0], 5); + + + uint8_t g = + _mesa_float_to_unorm(src[1], 6); + + + uint8_t b = + _mesa_float_to_unorm(src[2], 5); + + uint16_t d = 0; + d |= PACK(r, 0, 5); + d |= PACK(g, 5, 6); + d |= PACK(b, 11, 5); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_float_b4g4r4a4_unorm(const GLfloat src[4], void *dst) +{ + + + uint8_t b = + _mesa_float_to_unorm(src[2], 4); + + + uint8_t g = + _mesa_float_to_unorm(src[1], 4); + + + uint8_t r = + _mesa_float_to_unorm(src[0], 4); + + + uint8_t a = + _mesa_float_to_unorm(src[3], 4); + + uint16_t d = 0; + d |= PACK(b, 0, 4); + d |= PACK(g, 4, 4); + d |= PACK(r, 8, 4); + d |= PACK(a, 12, 4); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_float_b4g4r4x4_unorm(const GLfloat src[4], void *dst) +{ + + + uint8_t b = + _mesa_float_to_unorm(src[2], 4); + + + uint8_t g = + _mesa_float_to_unorm(src[1], 4); + + + uint8_t r = + _mesa_float_to_unorm(src[0], 4); + + + uint16_t d = 0; + d |= PACK(b, 0, 4); + d |= PACK(g, 4, 4); + d |= PACK(r, 8, 4); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_float_a4r4g4b4_unorm(const GLfloat src[4], void *dst) +{ + + + uint8_t a = + _mesa_float_to_unorm(src[3], 4); + + + uint8_t r = + _mesa_float_to_unorm(src[0], 4); + + + uint8_t g = + _mesa_float_to_unorm(src[1], 4); + + + uint8_t b = + _mesa_float_to_unorm(src[2], 4); + + uint16_t d = 0; + d |= PACK(a, 0, 4); + d |= PACK(r, 4, 4); + d |= PACK(g, 8, 4); + d |= PACK(b, 12, 4); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_float_a1b5g5r5_unorm(const GLfloat src[4], void *dst) +{ + + + uint8_t a = + _mesa_float_to_unorm(src[3], 1); + + + uint8_t b = + _mesa_float_to_unorm(src[2], 5); + + + uint8_t g = + _mesa_float_to_unorm(src[1], 5); + + + uint8_t r = + _mesa_float_to_unorm(src[0], 5); + + uint16_t d = 0; + d |= PACK(a, 0, 1); + d |= PACK(b, 1, 5); + d |= PACK(g, 6, 5); + d |= PACK(r, 11, 5); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_float_x1b5g5r5_unorm(const GLfloat src[4], void *dst) +{ + + + + uint8_t b = + _mesa_float_to_unorm(src[2], 5); + + + uint8_t g = + _mesa_float_to_unorm(src[1], 5); + + + uint8_t r = + _mesa_float_to_unorm(src[0], 5); + + uint16_t d = 0; + d |= PACK(b, 1, 5); + d |= PACK(g, 6, 5); + d |= PACK(r, 11, 5); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_float_b5g5r5a1_unorm(const GLfloat src[4], void *dst) +{ + + + uint8_t b = + _mesa_float_to_unorm(src[2], 5); + + + uint8_t g = + _mesa_float_to_unorm(src[1], 5); + + + uint8_t r = + _mesa_float_to_unorm(src[0], 5); + + + uint8_t a = + _mesa_float_to_unorm(src[3], 1); + + uint16_t d = 0; + d |= PACK(b, 0, 5); + d |= PACK(g, 5, 5); + d |= PACK(r, 10, 5); + d |= PACK(a, 15, 1); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_float_b5g5r5x1_unorm(const GLfloat src[4], void *dst) +{ + + + uint8_t b = + _mesa_float_to_unorm(src[2], 5); + + + uint8_t g = + _mesa_float_to_unorm(src[1], 5); + + + uint8_t r = + _mesa_float_to_unorm(src[0], 5); + + + uint16_t d = 0; + d |= PACK(b, 0, 5); + d |= PACK(g, 5, 5); + d |= PACK(r, 10, 5); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_float_a1r5g5b5_unorm(const GLfloat src[4], void *dst) +{ + + + uint8_t a = + _mesa_float_to_unorm(src[3], 1); + + + uint8_t r = + _mesa_float_to_unorm(src[0], 5); + + + uint8_t g = + _mesa_float_to_unorm(src[1], 5); + + + uint8_t b = + _mesa_float_to_unorm(src[2], 5); + + uint16_t d = 0; + d |= PACK(a, 0, 1); + d |= PACK(r, 1, 5); + d |= PACK(g, 6, 5); + d |= PACK(b, 11, 5); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_float_l8a8_unorm(const GLfloat src[4], void *dst) +{ + + + uint8_t l = + _mesa_float_to_unorm(src[0], 8); + + + uint8_t a = + _mesa_float_to_unorm(src[3], 8); + + uint16_t d = 0; + d |= PACK(l, 0, 8); + d |= PACK(a, 8, 8); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_float_a8l8_unorm(const GLfloat src[4], void *dst) +{ + + + uint8_t a = + _mesa_float_to_unorm(src[3], 8); + + + uint8_t l = + _mesa_float_to_unorm(src[0], 8); + + uint16_t d = 0; + d |= PACK(a, 0, 8); + d |= PACK(l, 8, 8); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_float_r8g8_unorm(const GLfloat src[4], void *dst) +{ + + + uint8_t r = + _mesa_float_to_unorm(src[0], 8); + + + uint8_t g = + _mesa_float_to_unorm(src[1], 8); + + uint16_t d = 0; + d |= PACK(r, 0, 8); + d |= PACK(g, 8, 8); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_float_g8r8_unorm(const GLfloat src[4], void *dst) +{ + + + uint8_t g = + _mesa_float_to_unorm(src[1], 8); + + + uint8_t r = + _mesa_float_to_unorm(src[0], 8); + + uint16_t d = 0; + d |= PACK(g, 0, 8); + d |= PACK(r, 8, 8); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_float_l4a4_unorm(const GLfloat src[4], void *dst) +{ + + + uint8_t l = + _mesa_float_to_unorm(src[0], 4); + + + uint8_t a = + _mesa_float_to_unorm(src[3], 4); + + uint8_t d = 0; + d |= PACK(l, 0, 4); + d |= PACK(a, 4, 4); + (*(uint8_t *)dst) = d; +} + +static inline void +pack_float_b2g3r3_unorm(const GLfloat src[4], void *dst) +{ + + + uint8_t b = + _mesa_float_to_unorm(src[2], 2); + + + uint8_t g = + _mesa_float_to_unorm(src[1], 3); + + + uint8_t r = + _mesa_float_to_unorm(src[0], 3); + + uint8_t d = 0; + d |= PACK(b, 0, 2); + d |= PACK(g, 2, 3); + d |= PACK(r, 5, 3); + (*(uint8_t *)dst) = d; +} + +static inline void +pack_float_r16g16_unorm(const GLfloat src[4], void *dst) +{ + + + uint16_t r = + _mesa_float_to_unorm(src[0], 16); + + + uint16_t g = + _mesa_float_to_unorm(src[1], 16); + + uint32_t d = 0; + d |= PACK(r, 0, 16); + d |= PACK(g, 16, 16); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_float_g16r16_unorm(const GLfloat src[4], void *dst) +{ + + + uint16_t g = + _mesa_float_to_unorm(src[1], 16); + + + uint16_t r = + _mesa_float_to_unorm(src[0], 16); + + uint32_t d = 0; + d |= PACK(g, 0, 16); + d |= PACK(r, 16, 16); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_float_b10g10r10a2_unorm(const GLfloat src[4], void *dst) +{ + + + uint16_t b = + _mesa_float_to_unorm(src[2], 10); + + + uint16_t g = + _mesa_float_to_unorm(src[1], 10); + + + uint16_t r = + _mesa_float_to_unorm(src[0], 10); + + + uint8_t a = + _mesa_float_to_unorm(src[3], 2); + + uint32_t d = 0; + d |= PACK(b, 0, 10); + d |= PACK(g, 10, 10); + d |= PACK(r, 20, 10); + d |= PACK(a, 30, 2); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_float_b10g10r10x2_unorm(const GLfloat src[4], void *dst) +{ + + + uint16_t b = + _mesa_float_to_unorm(src[2], 10); + + + uint16_t g = + _mesa_float_to_unorm(src[1], 10); + + + uint16_t r = + _mesa_float_to_unorm(src[0], 10); + + + uint32_t d = 0; + d |= PACK(b, 0, 10); + d |= PACK(g, 10, 10); + d |= PACK(r, 20, 10); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_float_r10g10b10a2_unorm(const GLfloat src[4], void *dst) +{ + + + uint16_t r = + _mesa_float_to_unorm(src[0], 10); + + + uint16_t g = + _mesa_float_to_unorm(src[1], 10); + + + uint16_t b = + _mesa_float_to_unorm(src[2], 10); + + + uint8_t a = + _mesa_float_to_unorm(src[3], 2); + + uint32_t d = 0; + d |= PACK(r, 0, 10); + d |= PACK(g, 10, 10); + d |= PACK(b, 20, 10); + d |= PACK(a, 30, 2); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_float_r10g10b10x2_unorm(const GLfloat src[4], void *dst) +{ + + + uint16_t r = + _mesa_float_to_unorm(src[0], 10); + + + uint16_t g = + _mesa_float_to_unorm(src[1], 10); + + + uint16_t b = + _mesa_float_to_unorm(src[2], 10); + + + uint32_t d = 0; + d |= PACK(r, 0, 10); + d |= PACK(g, 10, 10); + d |= PACK(b, 20, 10); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_float_r3g3b2_unorm(const GLfloat src[4], void *dst) +{ + + + uint8_t r = + _mesa_float_to_unorm(src[0], 3); + + + uint8_t g = + _mesa_float_to_unorm(src[1], 3); + + + uint8_t b = + _mesa_float_to_unorm(src[2], 2); + + uint8_t d = 0; + d |= PACK(r, 0, 3); + d |= PACK(g, 3, 3); + d |= PACK(b, 6, 2); + (*(uint8_t *)dst) = d; +} + +static inline void +pack_float_a4b4g4r4_unorm(const GLfloat src[4], void *dst) +{ + + + uint8_t a = + _mesa_float_to_unorm(src[3], 4); + + + uint8_t b = + _mesa_float_to_unorm(src[2], 4); + + + uint8_t g = + _mesa_float_to_unorm(src[1], 4); + + + uint8_t r = + _mesa_float_to_unorm(src[0], 4); + + uint16_t d = 0; + d |= PACK(a, 0, 4); + d |= PACK(b, 4, 4); + d |= PACK(g, 8, 4); + d |= PACK(r, 12, 4); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_float_r4g4b4a4_unorm(const GLfloat src[4], void *dst) +{ + + + uint8_t r = + _mesa_float_to_unorm(src[0], 4); + + + uint8_t g = + _mesa_float_to_unorm(src[1], 4); + + + uint8_t b = + _mesa_float_to_unorm(src[2], 4); + + + uint8_t a = + _mesa_float_to_unorm(src[3], 4); + + uint16_t d = 0; + d |= PACK(r, 0, 4); + d |= PACK(g, 4, 4); + d |= PACK(b, 8, 4); + d |= PACK(a, 12, 4); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_float_r5g5b5a1_unorm(const GLfloat src[4], void *dst) +{ + + + uint8_t r = + _mesa_float_to_unorm(src[0], 5); + + + uint8_t g = + _mesa_float_to_unorm(src[1], 5); + + + uint8_t b = + _mesa_float_to_unorm(src[2], 5); + + + uint8_t a = + _mesa_float_to_unorm(src[3], 1); + + uint16_t d = 0; + d |= PACK(r, 0, 5); + d |= PACK(g, 5, 5); + d |= PACK(b, 10, 5); + d |= PACK(a, 15, 1); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_float_a2b10g10r10_unorm(const GLfloat src[4], void *dst) +{ + + + uint8_t a = + _mesa_float_to_unorm(src[3], 2); + + + uint16_t b = + _mesa_float_to_unorm(src[2], 10); + + + uint16_t g = + _mesa_float_to_unorm(src[1], 10); + + + uint16_t r = + _mesa_float_to_unorm(src[0], 10); + + uint32_t d = 0; + d |= PACK(a, 0, 2); + d |= PACK(b, 2, 10); + d |= PACK(g, 12, 10); + d |= PACK(r, 22, 10); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_float_a2r10g10b10_unorm(const GLfloat src[4], void *dst) +{ + + + uint8_t a = + _mesa_float_to_unorm(src[3], 2); + + + uint16_t r = + _mesa_float_to_unorm(src[0], 10); + + + uint16_t g = + _mesa_float_to_unorm(src[1], 10); + + + uint16_t b = + _mesa_float_to_unorm(src[2], 10); + + uint32_t d = 0; + d |= PACK(a, 0, 2); + d |= PACK(r, 2, 10); + d |= PACK(g, 12, 10); + d |= PACK(b, 22, 10); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_float_a_unorm8(const GLfloat src[4], void *dst) +{ + + + uint8_t a = + _mesa_float_to_unorm(src[3], 8); + + uint8_t *d = (uint8_t *)dst; + d[0] = a; +} + +static inline void +pack_float_a_unorm16(const GLfloat src[4], void *dst) +{ + + + uint16_t a = + _mesa_float_to_unorm(src[3], 16); + + uint16_t *d = (uint16_t *)dst; + d[0] = a; +} + +static inline void +pack_float_l_unorm8(const GLfloat src[4], void *dst) +{ + + + uint8_t l = + _mesa_float_to_unorm(src[0], 8); + + uint8_t *d = (uint8_t *)dst; + d[0] = l; +} + +static inline void +pack_float_l_unorm16(const GLfloat src[4], void *dst) +{ + + + uint16_t l = + _mesa_float_to_unorm(src[0], 16); + + uint16_t *d = (uint16_t *)dst; + d[0] = l; +} + +static inline void +pack_float_i_unorm8(const GLfloat src[4], void *dst) +{ + + + uint8_t i = + _mesa_float_to_unorm(src[0], 8); + + uint8_t *d = (uint8_t *)dst; + d[0] = i; +} + +static inline void +pack_float_i_unorm16(const GLfloat src[4], void *dst) +{ + + + uint16_t i = + _mesa_float_to_unorm(src[0], 16); + + uint16_t *d = (uint16_t *)dst; + d[0] = i; +} + +static inline void +pack_float_r_unorm8(const GLfloat src[4], void *dst) +{ + + + uint8_t r = + _mesa_float_to_unorm(src[0], 8); + + uint8_t *d = (uint8_t *)dst; + d[0] = r; +} + +static inline void +pack_float_r_unorm16(const GLfloat src[4], void *dst) +{ + + + uint16_t r = + _mesa_float_to_unorm(src[0], 16); + + uint16_t *d = (uint16_t *)dst; + d[0] = r; +} + +static inline void +pack_float_bgr_unorm8(const GLfloat src[4], void *dst) +{ + + + uint8_t b = + _mesa_float_to_unorm(src[2], 8); + + + uint8_t g = + _mesa_float_to_unorm(src[1], 8); + + + uint8_t r = + _mesa_float_to_unorm(src[0], 8); + + uint8_t *d = (uint8_t *)dst; + d[0] = b; + d[1] = g; + d[2] = r; +} + +static inline void +pack_float_rgb_unorm8(const GLfloat src[4], void *dst) +{ + + + uint8_t r = + _mesa_float_to_unorm(src[0], 8); + + + uint8_t g = + _mesa_float_to_unorm(src[1], 8); + + + uint8_t b = + _mesa_float_to_unorm(src[2], 8); + + uint8_t *d = (uint8_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; +} + +static inline void +pack_float_rgba_unorm16(const GLfloat src[4], void *dst) +{ + + + uint16_t r = + _mesa_float_to_unorm(src[0], 16); + + + uint16_t g = + _mesa_float_to_unorm(src[1], 16); + + + uint16_t b = + _mesa_float_to_unorm(src[2], 16); + + + uint16_t a = + _mesa_float_to_unorm(src[3], 16); + + uint16_t *d = (uint16_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + d[3] = a; +} + +static inline void +pack_float_rgbx_unorm16(const GLfloat src[4], void *dst) +{ + + + uint16_t r = + _mesa_float_to_unorm(src[0], 16); + + + uint16_t g = + _mesa_float_to_unorm(src[1], 16); + + + uint16_t b = + _mesa_float_to_unorm(src[2], 16); + + + uint16_t *d = (uint16_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + } + +static inline void +pack_float_a8b8g8r8_snorm(const GLfloat src[4], void *dst) +{ + + + int8_t a = + _mesa_float_to_snorm(src[3], 8); + + + int8_t b = + _mesa_float_to_snorm(src[2], 8); + + + int8_t g = + _mesa_float_to_snorm(src[1], 8); + + + int8_t r = + _mesa_float_to_snorm(src[0], 8); + + uint32_t d = 0; + d |= PACK(a, 0, 8); + d |= PACK(b, 8, 8); + d |= PACK(g, 16, 8); + d |= PACK(r, 24, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_float_x8b8g8r8_snorm(const GLfloat src[4], void *dst) +{ + + + + int8_t b = + _mesa_float_to_snorm(src[2], 8); + + + int8_t g = + _mesa_float_to_snorm(src[1], 8); + + + int8_t r = + _mesa_float_to_snorm(src[0], 8); + + uint32_t d = 0; + d |= PACK(b, 8, 8); + d |= PACK(g, 16, 8); + d |= PACK(r, 24, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_float_r8g8b8a8_snorm(const GLfloat src[4], void *dst) +{ + + + int8_t r = + _mesa_float_to_snorm(src[0], 8); + + + int8_t g = + _mesa_float_to_snorm(src[1], 8); + + + int8_t b = + _mesa_float_to_snorm(src[2], 8); + + + int8_t a = + _mesa_float_to_snorm(src[3], 8); + + uint32_t d = 0; + d |= PACK(r, 0, 8); + d |= PACK(g, 8, 8); + d |= PACK(b, 16, 8); + d |= PACK(a, 24, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_float_r8g8b8x8_snorm(const GLfloat src[4], void *dst) +{ + + + int8_t r = + _mesa_float_to_snorm(src[0], 8); + + + int8_t g = + _mesa_float_to_snorm(src[1], 8); + + + int8_t b = + _mesa_float_to_snorm(src[2], 8); + + + uint32_t d = 0; + d |= PACK(r, 0, 8); + d |= PACK(g, 8, 8); + d |= PACK(b, 16, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_float_r16g16_snorm(const GLfloat src[4], void *dst) +{ + + + int16_t r = + _mesa_float_to_snorm(src[0], 16); + + + int16_t g = + _mesa_float_to_snorm(src[1], 16); + + uint32_t d = 0; + d |= PACK(r, 0, 16); + d |= PACK(g, 16, 16); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_float_g16r16_snorm(const GLfloat src[4], void *dst) +{ + + + int16_t g = + _mesa_float_to_snorm(src[1], 16); + + + int16_t r = + _mesa_float_to_snorm(src[0], 16); + + uint32_t d = 0; + d |= PACK(g, 0, 16); + d |= PACK(r, 16, 16); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_float_r8g8_snorm(const GLfloat src[4], void *dst) +{ + + + int8_t r = + _mesa_float_to_snorm(src[0], 8); + + + int8_t g = + _mesa_float_to_snorm(src[1], 8); + + uint16_t d = 0; + d |= PACK(r, 0, 8); + d |= PACK(g, 8, 8); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_float_g8r8_snorm(const GLfloat src[4], void *dst) +{ + + + int8_t g = + _mesa_float_to_snorm(src[1], 8); + + + int8_t r = + _mesa_float_to_snorm(src[0], 8); + + uint16_t d = 0; + d |= PACK(g, 0, 8); + d |= PACK(r, 8, 8); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_float_l8a8_snorm(const GLfloat src[4], void *dst) +{ + + + int8_t l = + _mesa_float_to_snorm(src[0], 8); + + + int8_t a = + _mesa_float_to_snorm(src[3], 8); + + uint16_t d = 0; + d |= PACK(l, 0, 8); + d |= PACK(a, 8, 8); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_float_a8l8_snorm(const GLfloat src[4], void *dst) +{ + + + int8_t a = + _mesa_float_to_snorm(src[3], 8); + + + int8_t l = + _mesa_float_to_snorm(src[0], 8); + + uint16_t d = 0; + d |= PACK(a, 0, 8); + d |= PACK(l, 8, 8); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_float_a_snorm8(const GLfloat src[4], void *dst) +{ + + + int8_t a = + _mesa_float_to_snorm(src[3], 8); + + int8_t *d = (int8_t *)dst; + d[0] = a; +} + +static inline void +pack_float_a_snorm16(const GLfloat src[4], void *dst) +{ + + + int16_t a = + _mesa_float_to_snorm(src[3], 16); + + int16_t *d = (int16_t *)dst; + d[0] = a; +} + +static inline void +pack_float_l_snorm8(const GLfloat src[4], void *dst) +{ + + + int8_t l = + _mesa_float_to_snorm(src[0], 8); + + int8_t *d = (int8_t *)dst; + d[0] = l; +} + +static inline void +pack_float_l_snorm16(const GLfloat src[4], void *dst) +{ + + + int16_t l = + _mesa_float_to_snorm(src[0], 16); + + int16_t *d = (int16_t *)dst; + d[0] = l; +} + +static inline void +pack_float_i_snorm8(const GLfloat src[4], void *dst) +{ + + + int8_t i = + _mesa_float_to_snorm(src[0], 8); + + int8_t *d = (int8_t *)dst; + d[0] = i; +} + +static inline void +pack_float_i_snorm16(const GLfloat src[4], void *dst) +{ + + + int16_t i = + _mesa_float_to_snorm(src[0], 16); + + int16_t *d = (int16_t *)dst; + d[0] = i; +} + +static inline void +pack_float_r_snorm8(const GLfloat src[4], void *dst) +{ + + + int8_t r = + _mesa_float_to_snorm(src[0], 8); + + int8_t *d = (int8_t *)dst; + d[0] = r; +} + +static inline void +pack_float_r_snorm16(const GLfloat src[4], void *dst) +{ + + + int16_t r = + _mesa_float_to_snorm(src[0], 16); + + int16_t *d = (int16_t *)dst; + d[0] = r; +} + +static inline void +pack_float_la_snorm16(const GLfloat src[4], void *dst) +{ + + + int16_t l = + _mesa_float_to_snorm(src[0], 16); + + + int16_t a = + _mesa_float_to_snorm(src[3], 16); + + int16_t *d = (int16_t *)dst; + d[0] = l; + d[1] = a; +} + +static inline void +pack_float_rgb_snorm16(const GLfloat src[4], void *dst) +{ + + + int16_t r = + _mesa_float_to_snorm(src[0], 16); + + + int16_t g = + _mesa_float_to_snorm(src[1], 16); + + + int16_t b = + _mesa_float_to_snorm(src[2], 16); + + int16_t *d = (int16_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; +} + +static inline void +pack_float_rgba_snorm16(const GLfloat src[4], void *dst) +{ + + + int16_t r = + _mesa_float_to_snorm(src[0], 16); + + + int16_t g = + _mesa_float_to_snorm(src[1], 16); + + + int16_t b = + _mesa_float_to_snorm(src[2], 16); + + + int16_t a = + _mesa_float_to_snorm(src[3], 16); + + int16_t *d = (int16_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + d[3] = a; +} + +static inline void +pack_float_rgbx_snorm16(const GLfloat src[4], void *dst) +{ + + + int16_t r = + _mesa_float_to_snorm(src[0], 16); + + + int16_t g = + _mesa_float_to_snorm(src[1], 16); + + + int16_t b = + _mesa_float_to_snorm(src[2], 16); + + + int16_t *d = (int16_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + } + +static inline void +pack_float_a8b8g8r8_srgb(const GLfloat src[4], void *dst) +{ + + + uint8_t a = + _mesa_float_to_unorm(src[3], 8); + + + uint8_t b = + + util_format_linear_float_to_srgb_8unorm(src[2]); + + + uint8_t g = + + util_format_linear_float_to_srgb_8unorm(src[1]); + + + uint8_t r = + + util_format_linear_float_to_srgb_8unorm(src[0]); + + uint32_t d = 0; + d |= PACK(a, 0, 8); + d |= PACK(b, 8, 8); + d |= PACK(g, 16, 8); + d |= PACK(r, 24, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_float_b8g8r8a8_srgb(const GLfloat src[4], void *dst) +{ + + + uint8_t b = + + util_format_linear_float_to_srgb_8unorm(src[2]); + + + uint8_t g = + + util_format_linear_float_to_srgb_8unorm(src[1]); + + + uint8_t r = + + util_format_linear_float_to_srgb_8unorm(src[0]); + + + uint8_t a = + _mesa_float_to_unorm(src[3], 8); + + uint32_t d = 0; + d |= PACK(b, 0, 8); + d |= PACK(g, 8, 8); + d |= PACK(r, 16, 8); + d |= PACK(a, 24, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_float_a8r8g8b8_srgb(const GLfloat src[4], void *dst) +{ + + + uint8_t a = + _mesa_float_to_unorm(src[3], 8); + + + uint8_t r = + + util_format_linear_float_to_srgb_8unorm(src[0]); + + + uint8_t g = + + util_format_linear_float_to_srgb_8unorm(src[1]); + + + uint8_t b = + + util_format_linear_float_to_srgb_8unorm(src[2]); + + uint32_t d = 0; + d |= PACK(a, 0, 8); + d |= PACK(r, 8, 8); + d |= PACK(g, 16, 8); + d |= PACK(b, 24, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_float_b8g8r8x8_srgb(const GLfloat src[4], void *dst) +{ + + + uint8_t b = + + util_format_linear_float_to_srgb_8unorm(src[2]); + + + uint8_t g = + + util_format_linear_float_to_srgb_8unorm(src[1]); + + + uint8_t r = + + util_format_linear_float_to_srgb_8unorm(src[0]); + + + uint32_t d = 0; + d |= PACK(b, 0, 8); + d |= PACK(g, 8, 8); + d |= PACK(r, 16, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_float_x8r8g8b8_srgb(const GLfloat src[4], void *dst) +{ + + + + uint8_t r = + + util_format_linear_float_to_srgb_8unorm(src[0]); + + + uint8_t g = + + util_format_linear_float_to_srgb_8unorm(src[1]); + + + uint8_t b = + + util_format_linear_float_to_srgb_8unorm(src[2]); + + uint32_t d = 0; + d |= PACK(r, 8, 8); + d |= PACK(g, 16, 8); + d |= PACK(b, 24, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_float_r8g8b8a8_srgb(const GLfloat src[4], void *dst) +{ + + + uint8_t r = + + util_format_linear_float_to_srgb_8unorm(src[0]); + + + uint8_t g = + + util_format_linear_float_to_srgb_8unorm(src[1]); + + + uint8_t b = + + util_format_linear_float_to_srgb_8unorm(src[2]); + + + uint8_t a = + _mesa_float_to_unorm(src[3], 8); + + uint32_t d = 0; + d |= PACK(r, 0, 8); + d |= PACK(g, 8, 8); + d |= PACK(b, 16, 8); + d |= PACK(a, 24, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_float_r8g8b8x8_srgb(const GLfloat src[4], void *dst) +{ + + + uint8_t r = + + util_format_linear_float_to_srgb_8unorm(src[0]); + + + uint8_t g = + + util_format_linear_float_to_srgb_8unorm(src[1]); + + + uint8_t b = + + util_format_linear_float_to_srgb_8unorm(src[2]); + + + uint32_t d = 0; + d |= PACK(r, 0, 8); + d |= PACK(g, 8, 8); + d |= PACK(b, 16, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_float_x8b8g8r8_srgb(const GLfloat src[4], void *dst) +{ + + + + uint8_t b = + + util_format_linear_float_to_srgb_8unorm(src[2]); + + + uint8_t g = + + util_format_linear_float_to_srgb_8unorm(src[1]); + + + uint8_t r = + + util_format_linear_float_to_srgb_8unorm(src[0]); + + uint32_t d = 0; + d |= PACK(b, 8, 8); + d |= PACK(g, 16, 8); + d |= PACK(r, 24, 8); + (*(uint32_t *)dst) = d; +} + +static inline void +pack_float_l8a8_srgb(const GLfloat src[4], void *dst) +{ + + + uint8_t l = + _mesa_float_to_unorm(src[0], 8); + + + uint8_t a = + _mesa_float_to_unorm(src[3], 8); + + uint16_t d = 0; + d |= PACK(l, 0, 8); + d |= PACK(a, 8, 8); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_float_a8l8_srgb(const GLfloat src[4], void *dst) +{ + + + uint8_t a = + _mesa_float_to_unorm(src[3], 8); + + + uint8_t l = + _mesa_float_to_unorm(src[0], 8); + + uint16_t d = 0; + d |= PACK(a, 0, 8); + d |= PACK(l, 8, 8); + (*(uint16_t *)dst) = d; +} + +static inline void +pack_float_r_srgb8(const GLfloat src[4], void *dst) +{ + + + uint8_t r = + + util_format_linear_float_to_srgb_8unorm(src[0]); + + uint8_t *d = (uint8_t *)dst; + d[0] = r; +} + +static inline void +pack_float_l_srgb8(const GLfloat src[4], void *dst) +{ + + + uint8_t l = + _mesa_float_to_unorm(src[0], 8); + + uint8_t *d = (uint8_t *)dst; + d[0] = l; +} + +static inline void +pack_float_bgr_srgb8(const GLfloat src[4], void *dst) +{ + + + uint8_t b = + + util_format_linear_float_to_srgb_8unorm(src[2]); + + + uint8_t g = + + util_format_linear_float_to_srgb_8unorm(src[1]); + + + uint8_t r = + + util_format_linear_float_to_srgb_8unorm(src[0]); + + uint8_t *d = (uint8_t *)dst; + d[0] = b; + d[1] = g; + d[2] = r; +} + +static inline void +pack_float_a_float16(const GLfloat src[4], void *dst) +{ + + + uint16_t a = + _mesa_float_to_half(src[3]); + + uint16_t *d = (uint16_t *)dst; + d[0] = a; +} + +static inline void +pack_float_a_float32(const GLfloat src[4], void *dst) +{ + + + float a = + src[3]; + + float *d = (float *)dst; + d[0] = a; +} + +static inline void +pack_float_l_float16(const GLfloat src[4], void *dst) +{ + + + uint16_t l = + _mesa_float_to_half(src[0]); + + uint16_t *d = (uint16_t *)dst; + d[0] = l; +} + +static inline void +pack_float_l_float32(const GLfloat src[4], void *dst) +{ + + + float l = + src[0]; + + float *d = (float *)dst; + d[0] = l; +} + +static inline void +pack_float_la_float16(const GLfloat src[4], void *dst) +{ + + + uint16_t l = + _mesa_float_to_half(src[0]); + + + uint16_t a = + _mesa_float_to_half(src[3]); + + uint16_t *d = (uint16_t *)dst; + d[0] = l; + d[1] = a; +} + +static inline void +pack_float_la_float32(const GLfloat src[4], void *dst) +{ + + + float l = + src[0]; + + + float a = + src[3]; + + float *d = (float *)dst; + d[0] = l; + d[1] = a; +} + +static inline void +pack_float_i_float16(const GLfloat src[4], void *dst) +{ + + + uint16_t i = + _mesa_float_to_half(src[0]); + + uint16_t *d = (uint16_t *)dst; + d[0] = i; +} + +static inline void +pack_float_i_float32(const GLfloat src[4], void *dst) +{ + + + float i = + src[0]; + + float *d = (float *)dst; + d[0] = i; +} + +static inline void +pack_float_r_float16(const GLfloat src[4], void *dst) +{ + + + uint16_t r = + _mesa_float_to_half(src[0]); + + uint16_t *d = (uint16_t *)dst; + d[0] = r; +} + +static inline void +pack_float_r_float32(const GLfloat src[4], void *dst) +{ + + + float r = + src[0]; + + float *d = (float *)dst; + d[0] = r; +} + +static inline void +pack_float_rg_float16(const GLfloat src[4], void *dst) +{ + + + uint16_t r = + _mesa_float_to_half(src[0]); + + + uint16_t g = + _mesa_float_to_half(src[1]); + + uint16_t *d = (uint16_t *)dst; + d[0] = r; + d[1] = g; +} + +static inline void +pack_float_rg_float32(const GLfloat src[4], void *dst) +{ + + + float r = + src[0]; + + + float g = + src[1]; + + float *d = (float *)dst; + d[0] = r; + d[1] = g; +} + +static inline void +pack_float_rgb_float16(const GLfloat src[4], void *dst) +{ + + + uint16_t r = + _mesa_float_to_half(src[0]); + + + uint16_t g = + _mesa_float_to_half(src[1]); + + + uint16_t b = + _mesa_float_to_half(src[2]); + + uint16_t *d = (uint16_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; +} + +static inline void +pack_float_rgb_float32(const GLfloat src[4], void *dst) +{ + + + float r = + src[0]; + + + float g = + src[1]; + + + float b = + src[2]; + + float *d = (float *)dst; + d[0] = r; + d[1] = g; + d[2] = b; +} + +static inline void +pack_float_rgba_float16(const GLfloat src[4], void *dst) +{ + + + uint16_t r = + _mesa_float_to_half(src[0]); + + + uint16_t g = + _mesa_float_to_half(src[1]); + + + uint16_t b = + _mesa_float_to_half(src[2]); + + + uint16_t a = + _mesa_float_to_half(src[3]); + + uint16_t *d = (uint16_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + d[3] = a; +} + +static inline void +pack_float_rgba_float32(const GLfloat src[4], void *dst) +{ + + + float r = + src[0]; + + + float g = + src[1]; + + + float b = + src[2]; + + + float a = + src[3]; + + float *d = (float *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + d[3] = a; +} + +static inline void +pack_float_rgbx_float16(const GLfloat src[4], void *dst) +{ + + + uint16_t r = + _mesa_float_to_half(src[0]); + + + uint16_t g = + _mesa_float_to_half(src[1]); + + + uint16_t b = + _mesa_float_to_half(src[2]); + + + uint16_t *d = (uint16_t *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + } + +static inline void +pack_float_rgbx_float32(const GLfloat src[4], void *dst) +{ + + + float r = + src[0]; + + + float g = + src[1]; + + + float b = + src[2]; + + + float *d = (float *)dst; + d[0] = r; + d[1] = g; + d[2] = b; + } + +static inline void +pack_float_r9g9b9e5_float(const GLfloat src[4], void *dst) +{ + GLuint *d = (GLuint *) dst; + *d = float3_to_rgb9e5(src); +} + +static inline void +pack_float_r11g11b10_float(const GLfloat src[4], void *dst) +{ + GLuint *d = (GLuint *) dst; + *d = float3_to_r11g11b10f(src); +} + +/** + * Return a function that can pack a GLubyte rgba[4] color. + */ +gl_pack_ubyte_rgba_func +_mesa_get_pack_ubyte_rgba_function(mesa_format format) +{ + switch (format) { + + case MESA_FORMAT_A8B8G8R8_UNORM: + return pack_ubyte_a8b8g8r8_unorm; + + case MESA_FORMAT_X8B8G8R8_UNORM: + return pack_ubyte_x8b8g8r8_unorm; + + case MESA_FORMAT_R8G8B8A8_UNORM: + return pack_ubyte_r8g8b8a8_unorm; + + case MESA_FORMAT_R8G8B8X8_UNORM: + return pack_ubyte_r8g8b8x8_unorm; + + case MESA_FORMAT_B8G8R8A8_UNORM: + return pack_ubyte_b8g8r8a8_unorm; + + case MESA_FORMAT_B8G8R8X8_UNORM: + return pack_ubyte_b8g8r8x8_unorm; + + case MESA_FORMAT_A8R8G8B8_UNORM: + return pack_ubyte_a8r8g8b8_unorm; + + case MESA_FORMAT_X8R8G8B8_UNORM: + return pack_ubyte_x8r8g8b8_unorm; + + case MESA_FORMAT_L16A16_UNORM: + return pack_ubyte_l16a16_unorm; + + case MESA_FORMAT_A16L16_UNORM: + return pack_ubyte_a16l16_unorm; + + case MESA_FORMAT_B5G6R5_UNORM: + return pack_ubyte_b5g6r5_unorm; + + case MESA_FORMAT_R5G6B5_UNORM: + return pack_ubyte_r5g6b5_unorm; + + case MESA_FORMAT_B4G4R4A4_UNORM: + return pack_ubyte_b4g4r4a4_unorm; + + case MESA_FORMAT_B4G4R4X4_UNORM: + return pack_ubyte_b4g4r4x4_unorm; + + case MESA_FORMAT_A4R4G4B4_UNORM: + return pack_ubyte_a4r4g4b4_unorm; + + case MESA_FORMAT_A1B5G5R5_UNORM: + return pack_ubyte_a1b5g5r5_unorm; + + case MESA_FORMAT_X1B5G5R5_UNORM: + return pack_ubyte_x1b5g5r5_unorm; + + case MESA_FORMAT_B5G5R5A1_UNORM: + return pack_ubyte_b5g5r5a1_unorm; + + case MESA_FORMAT_B5G5R5X1_UNORM: + return pack_ubyte_b5g5r5x1_unorm; + + case MESA_FORMAT_A1R5G5B5_UNORM: + return pack_ubyte_a1r5g5b5_unorm; + + case MESA_FORMAT_L8A8_UNORM: + return pack_ubyte_l8a8_unorm; + + case MESA_FORMAT_A8L8_UNORM: + return pack_ubyte_a8l8_unorm; + + case MESA_FORMAT_R8G8_UNORM: + return pack_ubyte_r8g8_unorm; + + case MESA_FORMAT_G8R8_UNORM: + return pack_ubyte_g8r8_unorm; + + case MESA_FORMAT_L4A4_UNORM: + return pack_ubyte_l4a4_unorm; + + case MESA_FORMAT_B2G3R3_UNORM: + return pack_ubyte_b2g3r3_unorm; + + case MESA_FORMAT_R16G16_UNORM: + return pack_ubyte_r16g16_unorm; + + case MESA_FORMAT_G16R16_UNORM: + return pack_ubyte_g16r16_unorm; + + case MESA_FORMAT_B10G10R10A2_UNORM: + return pack_ubyte_b10g10r10a2_unorm; + + case MESA_FORMAT_B10G10R10X2_UNORM: + return pack_ubyte_b10g10r10x2_unorm; + + case MESA_FORMAT_R10G10B10A2_UNORM: + return pack_ubyte_r10g10b10a2_unorm; + + case MESA_FORMAT_R10G10B10X2_UNORM: + return pack_ubyte_r10g10b10x2_unorm; + + case MESA_FORMAT_R3G3B2_UNORM: + return pack_ubyte_r3g3b2_unorm; + + case MESA_FORMAT_A4B4G4R4_UNORM: + return pack_ubyte_a4b4g4r4_unorm; + + case MESA_FORMAT_R4G4B4A4_UNORM: + return pack_ubyte_r4g4b4a4_unorm; + + case MESA_FORMAT_R5G5B5A1_UNORM: + return pack_ubyte_r5g5b5a1_unorm; + + case MESA_FORMAT_A2B10G10R10_UNORM: + return pack_ubyte_a2b10g10r10_unorm; + + case MESA_FORMAT_A2R10G10B10_UNORM: + return pack_ubyte_a2r10g10b10_unorm; + + case MESA_FORMAT_A_UNORM8: + return pack_ubyte_a_unorm8; + + case MESA_FORMAT_A_UNORM16: + return pack_ubyte_a_unorm16; + + case MESA_FORMAT_L_UNORM8: + return pack_ubyte_l_unorm8; + + case MESA_FORMAT_L_UNORM16: + return pack_ubyte_l_unorm16; + + case MESA_FORMAT_I_UNORM8: + return pack_ubyte_i_unorm8; + + case MESA_FORMAT_I_UNORM16: + return pack_ubyte_i_unorm16; + + case MESA_FORMAT_R_UNORM8: + return pack_ubyte_r_unorm8; + + case MESA_FORMAT_R_UNORM16: + return pack_ubyte_r_unorm16; + + case MESA_FORMAT_BGR_UNORM8: + return pack_ubyte_bgr_unorm8; + + case MESA_FORMAT_RGB_UNORM8: + return pack_ubyte_rgb_unorm8; + + case MESA_FORMAT_RGBA_UNORM16: + return pack_ubyte_rgba_unorm16; + + case MESA_FORMAT_RGBX_UNORM16: + return pack_ubyte_rgbx_unorm16; + + case MESA_FORMAT_A8B8G8R8_SNORM: + return pack_ubyte_a8b8g8r8_snorm; + + case MESA_FORMAT_X8B8G8R8_SNORM: + return pack_ubyte_x8b8g8r8_snorm; + + case MESA_FORMAT_R8G8B8A8_SNORM: + return pack_ubyte_r8g8b8a8_snorm; + + case MESA_FORMAT_R8G8B8X8_SNORM: + return pack_ubyte_r8g8b8x8_snorm; + + case MESA_FORMAT_R16G16_SNORM: + return pack_ubyte_r16g16_snorm; + + case MESA_FORMAT_G16R16_SNORM: + return pack_ubyte_g16r16_snorm; + + case MESA_FORMAT_R8G8_SNORM: + return pack_ubyte_r8g8_snorm; + + case MESA_FORMAT_G8R8_SNORM: + return pack_ubyte_g8r8_snorm; + + case MESA_FORMAT_L8A8_SNORM: + return pack_ubyte_l8a8_snorm; + + case MESA_FORMAT_A8L8_SNORM: + return pack_ubyte_a8l8_snorm; + + case MESA_FORMAT_A_SNORM8: + return pack_ubyte_a_snorm8; + + case MESA_FORMAT_A_SNORM16: + return pack_ubyte_a_snorm16; + + case MESA_FORMAT_L_SNORM8: + return pack_ubyte_l_snorm8; + + case MESA_FORMAT_L_SNORM16: + return pack_ubyte_l_snorm16; + + case MESA_FORMAT_I_SNORM8: + return pack_ubyte_i_snorm8; + + case MESA_FORMAT_I_SNORM16: + return pack_ubyte_i_snorm16; + + case MESA_FORMAT_R_SNORM8: + return pack_ubyte_r_snorm8; + + case MESA_FORMAT_R_SNORM16: + return pack_ubyte_r_snorm16; + + case MESA_FORMAT_LA_SNORM16: + return pack_ubyte_la_snorm16; + + case MESA_FORMAT_RGB_SNORM16: + return pack_ubyte_rgb_snorm16; + + case MESA_FORMAT_RGBA_SNORM16: + return pack_ubyte_rgba_snorm16; + + case MESA_FORMAT_RGBX_SNORM16: + return pack_ubyte_rgbx_snorm16; + + case MESA_FORMAT_A8B8G8R8_SRGB: + return pack_ubyte_a8b8g8r8_srgb; + + case MESA_FORMAT_B8G8R8A8_SRGB: + return pack_ubyte_b8g8r8a8_srgb; + + case MESA_FORMAT_A8R8G8B8_SRGB: + return pack_ubyte_a8r8g8b8_srgb; + + case MESA_FORMAT_B8G8R8X8_SRGB: + return pack_ubyte_b8g8r8x8_srgb; + + case MESA_FORMAT_X8R8G8B8_SRGB: + return pack_ubyte_x8r8g8b8_srgb; + + case MESA_FORMAT_R8G8B8A8_SRGB: + return pack_ubyte_r8g8b8a8_srgb; + + case MESA_FORMAT_R8G8B8X8_SRGB: + return pack_ubyte_r8g8b8x8_srgb; + + case MESA_FORMAT_X8B8G8R8_SRGB: + return pack_ubyte_x8b8g8r8_srgb; + + case MESA_FORMAT_L8A8_SRGB: + return pack_ubyte_l8a8_srgb; + + case MESA_FORMAT_A8L8_SRGB: + return pack_ubyte_a8l8_srgb; + + case MESA_FORMAT_R_SRGB8: + return pack_ubyte_r_srgb8; + + case MESA_FORMAT_L_SRGB8: + return pack_ubyte_l_srgb8; + + case MESA_FORMAT_BGR_SRGB8: + return pack_ubyte_bgr_srgb8; + + case MESA_FORMAT_R9G9B9E5_FLOAT: + return pack_ubyte_r9g9b9e5_float; + + case MESA_FORMAT_R11G11B10_FLOAT: + return pack_ubyte_r11g11b10_float; + + case MESA_FORMAT_A_FLOAT16: + return pack_ubyte_a_float16; + + case MESA_FORMAT_A_FLOAT32: + return pack_ubyte_a_float32; + + case MESA_FORMAT_L_FLOAT16: + return pack_ubyte_l_float16; + + case MESA_FORMAT_L_FLOAT32: + return pack_ubyte_l_float32; + + case MESA_FORMAT_LA_FLOAT16: + return pack_ubyte_la_float16; + + case MESA_FORMAT_LA_FLOAT32: + return pack_ubyte_la_float32; + + case MESA_FORMAT_I_FLOAT16: + return pack_ubyte_i_float16; + + case MESA_FORMAT_I_FLOAT32: + return pack_ubyte_i_float32; + + case MESA_FORMAT_R_FLOAT16: + return pack_ubyte_r_float16; + + case MESA_FORMAT_R_FLOAT32: + return pack_ubyte_r_float32; + + case MESA_FORMAT_RG_FLOAT16: + return pack_ubyte_rg_float16; + + case MESA_FORMAT_RG_FLOAT32: + return pack_ubyte_rg_float32; + + case MESA_FORMAT_RGB_FLOAT16: + return pack_ubyte_rgb_float16; + + case MESA_FORMAT_RGB_FLOAT32: + return pack_ubyte_rgb_float32; + + case MESA_FORMAT_RGBA_FLOAT16: + return pack_ubyte_rgba_float16; + + case MESA_FORMAT_RGBA_FLOAT32: + return pack_ubyte_rgba_float32; + + case MESA_FORMAT_RGBX_FLOAT16: + return pack_ubyte_rgbx_float16; + + case MESA_FORMAT_RGBX_FLOAT32: + return pack_ubyte_rgbx_float32; + + case MESA_FORMAT_A8B8G8R8_UINT: + return pack_ubyte_a8b8g8r8_uint; + + case MESA_FORMAT_A8R8G8B8_UINT: + return pack_ubyte_a8r8g8b8_uint; + + case MESA_FORMAT_R8G8B8A8_UINT: + return pack_ubyte_r8g8b8a8_uint; + + case MESA_FORMAT_B8G8R8A8_UINT: + return pack_ubyte_b8g8r8a8_uint; + + case MESA_FORMAT_B10G10R10A2_UINT: + return pack_ubyte_b10g10r10a2_uint; + + case MESA_FORMAT_R10G10B10A2_UINT: + return pack_ubyte_r10g10b10a2_uint; + + case MESA_FORMAT_A2B10G10R10_UINT: + return pack_ubyte_a2b10g10r10_uint; + + case MESA_FORMAT_A2R10G10B10_UINT: + return pack_ubyte_a2r10g10b10_uint; + + case MESA_FORMAT_B5G6R5_UINT: + return pack_ubyte_b5g6r5_uint; + + case MESA_FORMAT_R5G6B5_UINT: + return pack_ubyte_r5g6b5_uint; + + case MESA_FORMAT_B2G3R3_UINT: + return pack_ubyte_b2g3r3_uint; + + case MESA_FORMAT_R3G3B2_UINT: + return pack_ubyte_r3g3b2_uint; + + case MESA_FORMAT_A4B4G4R4_UINT: + return pack_ubyte_a4b4g4r4_uint; + + case MESA_FORMAT_R4G4B4A4_UINT: + return pack_ubyte_r4g4b4a4_uint; + + case MESA_FORMAT_B4G4R4A4_UINT: + return pack_ubyte_b4g4r4a4_uint; + + case MESA_FORMAT_A4R4G4B4_UINT: + return pack_ubyte_a4r4g4b4_uint; + + case MESA_FORMAT_A1B5G5R5_UINT: + return pack_ubyte_a1b5g5r5_uint; + + case MESA_FORMAT_B5G5R5A1_UINT: + return pack_ubyte_b5g5r5a1_uint; + + case MESA_FORMAT_A1R5G5B5_UINT: + return pack_ubyte_a1r5g5b5_uint; + + case MESA_FORMAT_R5G5B5A1_UINT: + return pack_ubyte_r5g5b5a1_uint; + + case MESA_FORMAT_A_UINT8: + return pack_ubyte_a_uint8; + + case MESA_FORMAT_A_UINT16: + return pack_ubyte_a_uint16; + + case MESA_FORMAT_A_UINT32: + return pack_ubyte_a_uint32; + + case MESA_FORMAT_A_SINT8: + return pack_ubyte_a_sint8; + + case MESA_FORMAT_A_SINT16: + return pack_ubyte_a_sint16; + + case MESA_FORMAT_A_SINT32: + return pack_ubyte_a_sint32; + + case MESA_FORMAT_I_UINT8: + return pack_ubyte_i_uint8; + + case MESA_FORMAT_I_UINT16: + return pack_ubyte_i_uint16; + + case MESA_FORMAT_I_UINT32: + return pack_ubyte_i_uint32; + + case MESA_FORMAT_I_SINT8: + return pack_ubyte_i_sint8; + + case MESA_FORMAT_I_SINT16: + return pack_ubyte_i_sint16; + + case MESA_FORMAT_I_SINT32: + return pack_ubyte_i_sint32; + + case MESA_FORMAT_L_UINT8: + return pack_ubyte_l_uint8; + + case MESA_FORMAT_L_UINT16: + return pack_ubyte_l_uint16; + + case MESA_FORMAT_L_UINT32: + return pack_ubyte_l_uint32; + + case MESA_FORMAT_L_SINT8: + return pack_ubyte_l_sint8; + + case MESA_FORMAT_L_SINT16: + return pack_ubyte_l_sint16; + + case MESA_FORMAT_L_SINT32: + return pack_ubyte_l_sint32; + + case MESA_FORMAT_LA_UINT8: + return pack_ubyte_la_uint8; + + case MESA_FORMAT_LA_UINT16: + return pack_ubyte_la_uint16; + + case MESA_FORMAT_LA_UINT32: + return pack_ubyte_la_uint32; + + case MESA_FORMAT_LA_SINT8: + return pack_ubyte_la_sint8; + + case MESA_FORMAT_LA_SINT16: + return pack_ubyte_la_sint16; + + case MESA_FORMAT_LA_SINT32: + return pack_ubyte_la_sint32; + + case MESA_FORMAT_R_UINT8: + return pack_ubyte_r_uint8; + + case MESA_FORMAT_R_UINT16: + return pack_ubyte_r_uint16; + + case MESA_FORMAT_R_UINT32: + return pack_ubyte_r_uint32; + + case MESA_FORMAT_R_SINT8: + return pack_ubyte_r_sint8; + + case MESA_FORMAT_R_SINT16: + return pack_ubyte_r_sint16; + + case MESA_FORMAT_R_SINT32: + return pack_ubyte_r_sint32; + + case MESA_FORMAT_RG_UINT8: + return pack_ubyte_rg_uint8; + + case MESA_FORMAT_RG_UINT16: + return pack_ubyte_rg_uint16; + + case MESA_FORMAT_RG_UINT32: + return pack_ubyte_rg_uint32; + + case MESA_FORMAT_RG_SINT8: + return pack_ubyte_rg_sint8; + + case MESA_FORMAT_RG_SINT16: + return pack_ubyte_rg_sint16; + + case MESA_FORMAT_RG_SINT32: + return pack_ubyte_rg_sint32; + + case MESA_FORMAT_RGB_UINT8: + return pack_ubyte_rgb_uint8; + + case MESA_FORMAT_RGB_UINT16: + return pack_ubyte_rgb_uint16; + + case MESA_FORMAT_RGB_UINT32: + return pack_ubyte_rgb_uint32; + + case MESA_FORMAT_RGB_SINT8: + return pack_ubyte_rgb_sint8; + + case MESA_FORMAT_RGB_SINT16: + return pack_ubyte_rgb_sint16; + + case MESA_FORMAT_RGB_SINT32: + return pack_ubyte_rgb_sint32; + + case MESA_FORMAT_RGBA_UINT8: + return pack_ubyte_rgba_uint8; + + case MESA_FORMAT_RGBA_UINT16: + return pack_ubyte_rgba_uint16; + + case MESA_FORMAT_RGBA_UINT32: + return pack_ubyte_rgba_uint32; + + case MESA_FORMAT_RGBA_SINT8: + return pack_ubyte_rgba_sint8; + + case MESA_FORMAT_RGBA_SINT16: + return pack_ubyte_rgba_sint16; + + case MESA_FORMAT_RGBA_SINT32: + return pack_ubyte_rgba_sint32; + + case MESA_FORMAT_RGBX_UINT8: + return pack_ubyte_rgbx_uint8; + + case MESA_FORMAT_RGBX_UINT16: + return pack_ubyte_rgbx_uint16; + + case MESA_FORMAT_RGBX_UINT32: + return pack_ubyte_rgbx_uint32; + + case MESA_FORMAT_RGBX_SINT8: + return pack_ubyte_rgbx_sint8; + + case MESA_FORMAT_RGBX_SINT16: + return pack_ubyte_rgbx_sint16; + + case MESA_FORMAT_RGBX_SINT32: + return pack_ubyte_rgbx_sint32; + default: + return NULL; + } +} + +/** + * Return a function that can pack a GLfloat rgba[4] color. + */ +gl_pack_float_rgba_func +_mesa_get_pack_float_rgba_function(mesa_format format) +{ + switch (format) { + + case MESA_FORMAT_A8B8G8R8_UNORM: + return pack_float_a8b8g8r8_unorm; + + case MESA_FORMAT_X8B8G8R8_UNORM: + return pack_float_x8b8g8r8_unorm; + + case MESA_FORMAT_R8G8B8A8_UNORM: + return pack_float_r8g8b8a8_unorm; + + case MESA_FORMAT_R8G8B8X8_UNORM: + return pack_float_r8g8b8x8_unorm; + + case MESA_FORMAT_B8G8R8A8_UNORM: + return pack_float_b8g8r8a8_unorm; + + case MESA_FORMAT_B8G8R8X8_UNORM: + return pack_float_b8g8r8x8_unorm; + + case MESA_FORMAT_A8R8G8B8_UNORM: + return pack_float_a8r8g8b8_unorm; + + case MESA_FORMAT_X8R8G8B8_UNORM: + return pack_float_x8r8g8b8_unorm; + + case MESA_FORMAT_L16A16_UNORM: + return pack_float_l16a16_unorm; + + case MESA_FORMAT_A16L16_UNORM: + return pack_float_a16l16_unorm; + + case MESA_FORMAT_B5G6R5_UNORM: + return pack_float_b5g6r5_unorm; + + case MESA_FORMAT_R5G6B5_UNORM: + return pack_float_r5g6b5_unorm; + + case MESA_FORMAT_B4G4R4A4_UNORM: + return pack_float_b4g4r4a4_unorm; + + case MESA_FORMAT_B4G4R4X4_UNORM: + return pack_float_b4g4r4x4_unorm; + + case MESA_FORMAT_A4R4G4B4_UNORM: + return pack_float_a4r4g4b4_unorm; + + case MESA_FORMAT_A1B5G5R5_UNORM: + return pack_float_a1b5g5r5_unorm; + + case MESA_FORMAT_X1B5G5R5_UNORM: + return pack_float_x1b5g5r5_unorm; + + case MESA_FORMAT_B5G5R5A1_UNORM: + return pack_float_b5g5r5a1_unorm; + + case MESA_FORMAT_B5G5R5X1_UNORM: + return pack_float_b5g5r5x1_unorm; + + case MESA_FORMAT_A1R5G5B5_UNORM: + return pack_float_a1r5g5b5_unorm; + + case MESA_FORMAT_L8A8_UNORM: + return pack_float_l8a8_unorm; + + case MESA_FORMAT_A8L8_UNORM: + return pack_float_a8l8_unorm; + + case MESA_FORMAT_R8G8_UNORM: + return pack_float_r8g8_unorm; + + case MESA_FORMAT_G8R8_UNORM: + return pack_float_g8r8_unorm; + + case MESA_FORMAT_L4A4_UNORM: + return pack_float_l4a4_unorm; + + case MESA_FORMAT_B2G3R3_UNORM: + return pack_float_b2g3r3_unorm; + + case MESA_FORMAT_R16G16_UNORM: + return pack_float_r16g16_unorm; + + case MESA_FORMAT_G16R16_UNORM: + return pack_float_g16r16_unorm; + + case MESA_FORMAT_B10G10R10A2_UNORM: + return pack_float_b10g10r10a2_unorm; + + case MESA_FORMAT_B10G10R10X2_UNORM: + return pack_float_b10g10r10x2_unorm; + + case MESA_FORMAT_R10G10B10A2_UNORM: + return pack_float_r10g10b10a2_unorm; + + case MESA_FORMAT_R10G10B10X2_UNORM: + return pack_float_r10g10b10x2_unorm; + + case MESA_FORMAT_R3G3B2_UNORM: + return pack_float_r3g3b2_unorm; + + case MESA_FORMAT_A4B4G4R4_UNORM: + return pack_float_a4b4g4r4_unorm; + + case MESA_FORMAT_R4G4B4A4_UNORM: + return pack_float_r4g4b4a4_unorm; + + case MESA_FORMAT_R5G5B5A1_UNORM: + return pack_float_r5g5b5a1_unorm; + + case MESA_FORMAT_A2B10G10R10_UNORM: + return pack_float_a2b10g10r10_unorm; + + case MESA_FORMAT_A2R10G10B10_UNORM: + return pack_float_a2r10g10b10_unorm; + + case MESA_FORMAT_A_UNORM8: + return pack_float_a_unorm8; + + case MESA_FORMAT_A_UNORM16: + return pack_float_a_unorm16; + + case MESA_FORMAT_L_UNORM8: + return pack_float_l_unorm8; + + case MESA_FORMAT_L_UNORM16: + return pack_float_l_unorm16; + + case MESA_FORMAT_I_UNORM8: + return pack_float_i_unorm8; + + case MESA_FORMAT_I_UNORM16: + return pack_float_i_unorm16; + + case MESA_FORMAT_R_UNORM8: + return pack_float_r_unorm8; + + case MESA_FORMAT_R_UNORM16: + return pack_float_r_unorm16; + + case MESA_FORMAT_BGR_UNORM8: + return pack_float_bgr_unorm8; + + case MESA_FORMAT_RGB_UNORM8: + return pack_float_rgb_unorm8; + + case MESA_FORMAT_RGBA_UNORM16: + return pack_float_rgba_unorm16; + + case MESA_FORMAT_RGBX_UNORM16: + return pack_float_rgbx_unorm16; + + case MESA_FORMAT_A8B8G8R8_SNORM: + return pack_float_a8b8g8r8_snorm; + + case MESA_FORMAT_X8B8G8R8_SNORM: + return pack_float_x8b8g8r8_snorm; + + case MESA_FORMAT_R8G8B8A8_SNORM: + return pack_float_r8g8b8a8_snorm; + + case MESA_FORMAT_R8G8B8X8_SNORM: + return pack_float_r8g8b8x8_snorm; + + case MESA_FORMAT_R16G16_SNORM: + return pack_float_r16g16_snorm; + + case MESA_FORMAT_G16R16_SNORM: + return pack_float_g16r16_snorm; + + case MESA_FORMAT_R8G8_SNORM: + return pack_float_r8g8_snorm; + + case MESA_FORMAT_G8R8_SNORM: + return pack_float_g8r8_snorm; + + case MESA_FORMAT_L8A8_SNORM: + return pack_float_l8a8_snorm; + + case MESA_FORMAT_A8L8_SNORM: + return pack_float_a8l8_snorm; + + case MESA_FORMAT_A_SNORM8: + return pack_float_a_snorm8; + + case MESA_FORMAT_A_SNORM16: + return pack_float_a_snorm16; + + case MESA_FORMAT_L_SNORM8: + return pack_float_l_snorm8; + + case MESA_FORMAT_L_SNORM16: + return pack_float_l_snorm16; + + case MESA_FORMAT_I_SNORM8: + return pack_float_i_snorm8; + + case MESA_FORMAT_I_SNORM16: + return pack_float_i_snorm16; + + case MESA_FORMAT_R_SNORM8: + return pack_float_r_snorm8; + + case MESA_FORMAT_R_SNORM16: + return pack_float_r_snorm16; + + case MESA_FORMAT_LA_SNORM16: + return pack_float_la_snorm16; + + case MESA_FORMAT_RGB_SNORM16: + return pack_float_rgb_snorm16; + + case MESA_FORMAT_RGBA_SNORM16: + return pack_float_rgba_snorm16; + + case MESA_FORMAT_RGBX_SNORM16: + return pack_float_rgbx_snorm16; + + case MESA_FORMAT_A8B8G8R8_SRGB: + return pack_float_a8b8g8r8_srgb; + + case MESA_FORMAT_B8G8R8A8_SRGB: + return pack_float_b8g8r8a8_srgb; + + case MESA_FORMAT_A8R8G8B8_SRGB: + return pack_float_a8r8g8b8_srgb; + + case MESA_FORMAT_B8G8R8X8_SRGB: + return pack_float_b8g8r8x8_srgb; + + case MESA_FORMAT_X8R8G8B8_SRGB: + return pack_float_x8r8g8b8_srgb; + + case MESA_FORMAT_R8G8B8A8_SRGB: + return pack_float_r8g8b8a8_srgb; + + case MESA_FORMAT_R8G8B8X8_SRGB: + return pack_float_r8g8b8x8_srgb; + + case MESA_FORMAT_X8B8G8R8_SRGB: + return pack_float_x8b8g8r8_srgb; + + case MESA_FORMAT_L8A8_SRGB: + return pack_float_l8a8_srgb; + + case MESA_FORMAT_A8L8_SRGB: + return pack_float_a8l8_srgb; + + case MESA_FORMAT_R_SRGB8: + return pack_float_r_srgb8; + + case MESA_FORMAT_L_SRGB8: + return pack_float_l_srgb8; + + case MESA_FORMAT_BGR_SRGB8: + return pack_float_bgr_srgb8; + + case MESA_FORMAT_R9G9B9E5_FLOAT: + return pack_float_r9g9b9e5_float; + + case MESA_FORMAT_R11G11B10_FLOAT: + return pack_float_r11g11b10_float; + + case MESA_FORMAT_A_FLOAT16: + return pack_float_a_float16; + + case MESA_FORMAT_A_FLOAT32: + return pack_float_a_float32; + + case MESA_FORMAT_L_FLOAT16: + return pack_float_l_float16; + + case MESA_FORMAT_L_FLOAT32: + return pack_float_l_float32; + + case MESA_FORMAT_LA_FLOAT16: + return pack_float_la_float16; + + case MESA_FORMAT_LA_FLOAT32: + return pack_float_la_float32; + + case MESA_FORMAT_I_FLOAT16: + return pack_float_i_float16; + + case MESA_FORMAT_I_FLOAT32: + return pack_float_i_float32; + + case MESA_FORMAT_R_FLOAT16: + return pack_float_r_float16; + + case MESA_FORMAT_R_FLOAT32: + return pack_float_r_float32; + + case MESA_FORMAT_RG_FLOAT16: + return pack_float_rg_float16; + + case MESA_FORMAT_RG_FLOAT32: + return pack_float_rg_float32; + + case MESA_FORMAT_RGB_FLOAT16: + return pack_float_rgb_float16; + + case MESA_FORMAT_RGB_FLOAT32: + return pack_float_rgb_float32; + + case MESA_FORMAT_RGBA_FLOAT16: + return pack_float_rgba_float16; + + case MESA_FORMAT_RGBA_FLOAT32: + return pack_float_rgba_float32; + + case MESA_FORMAT_RGBX_FLOAT16: + return pack_float_rgbx_float16; + + case MESA_FORMAT_RGBX_FLOAT32: + return pack_float_rgbx_float32; + default: + return NULL; + } +} + +/** + * Pack a row of GLubyte rgba[4] values to the destination. + */ +void +_mesa_pack_ubyte_rgba_row(mesa_format format, GLuint n, + const GLubyte src[][4], void *dst) +{ + GLuint i; + GLubyte *d = dst; + + switch (format) { + + case MESA_FORMAT_A8B8G8R8_UNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_a8b8g8r8_unorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_X8B8G8R8_UNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_x8b8g8r8_unorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_R8G8B8A8_UNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_r8g8b8a8_unorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_R8G8B8X8_UNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_r8g8b8x8_unorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_B8G8R8A8_UNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_b8g8r8a8_unorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_B8G8R8X8_UNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_b8g8r8x8_unorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_A8R8G8B8_UNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_a8r8g8b8_unorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_X8R8G8B8_UNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_x8r8g8b8_unorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_L16A16_UNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_l16a16_unorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_A16L16_UNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_a16l16_unorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_B5G6R5_UNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_b5g6r5_unorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_R5G6B5_UNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_r5g6b5_unorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_B4G4R4A4_UNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_b4g4r4a4_unorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_B4G4R4X4_UNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_b4g4r4x4_unorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_A4R4G4B4_UNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_a4r4g4b4_unorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_A1B5G5R5_UNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_a1b5g5r5_unorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_X1B5G5R5_UNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_x1b5g5r5_unorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_B5G5R5A1_UNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_b5g5r5a1_unorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_B5G5R5X1_UNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_b5g5r5x1_unorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_A1R5G5B5_UNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_a1r5g5b5_unorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_L8A8_UNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_l8a8_unorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_A8L8_UNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_a8l8_unorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_R8G8_UNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_r8g8_unorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_G8R8_UNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_g8r8_unorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_L4A4_UNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_l4a4_unorm(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_B2G3R3_UNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_b2g3r3_unorm(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_R16G16_UNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_r16g16_unorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_G16R16_UNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_g16r16_unorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_B10G10R10A2_UNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_b10g10r10a2_unorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_B10G10R10X2_UNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_b10g10r10x2_unorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_R10G10B10A2_UNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_r10g10b10a2_unorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_R10G10B10X2_UNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_r10g10b10x2_unorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_R3G3B2_UNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_r3g3b2_unorm(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_A4B4G4R4_UNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_a4b4g4r4_unorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_R4G4B4A4_UNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_r4g4b4a4_unorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_R5G5B5A1_UNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_r5g5b5a1_unorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_A2B10G10R10_UNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_a2b10g10r10_unorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_A2R10G10B10_UNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_a2r10g10b10_unorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_A_UNORM8: + for (i = 0; i < n; ++i) { + pack_ubyte_a_unorm8(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_A_UNORM16: + for (i = 0; i < n; ++i) { + pack_ubyte_a_unorm16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_L_UNORM8: + for (i = 0; i < n; ++i) { + pack_ubyte_l_unorm8(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_L_UNORM16: + for (i = 0; i < n; ++i) { + pack_ubyte_l_unorm16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_I_UNORM8: + for (i = 0; i < n; ++i) { + pack_ubyte_i_unorm8(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_I_UNORM16: + for (i = 0; i < n; ++i) { + pack_ubyte_i_unorm16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_R_UNORM8: + for (i = 0; i < n; ++i) { + pack_ubyte_r_unorm8(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_R_UNORM16: + for (i = 0; i < n; ++i) { + pack_ubyte_r_unorm16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_BGR_UNORM8: + for (i = 0; i < n; ++i) { + pack_ubyte_bgr_unorm8(src[i], d); + d += 3; + } + break; + + case MESA_FORMAT_RGB_UNORM8: + for (i = 0; i < n; ++i) { + pack_ubyte_rgb_unorm8(src[i], d); + d += 3; + } + break; + + case MESA_FORMAT_RGBA_UNORM16: + for (i = 0; i < n; ++i) { + pack_ubyte_rgba_unorm16(src[i], d); + d += 8; + } + break; + + case MESA_FORMAT_RGBX_UNORM16: + for (i = 0; i < n; ++i) { + pack_ubyte_rgbx_unorm16(src[i], d); + d += 8; + } + break; + + case MESA_FORMAT_A8B8G8R8_SNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_a8b8g8r8_snorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_X8B8G8R8_SNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_x8b8g8r8_snorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_R8G8B8A8_SNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_r8g8b8a8_snorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_R8G8B8X8_SNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_r8g8b8x8_snorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_R16G16_SNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_r16g16_snorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_G16R16_SNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_g16r16_snorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_R8G8_SNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_r8g8_snorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_G8R8_SNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_g8r8_snorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_L8A8_SNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_l8a8_snorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_A8L8_SNORM: + for (i = 0; i < n; ++i) { + pack_ubyte_a8l8_snorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_A_SNORM8: + for (i = 0; i < n; ++i) { + pack_ubyte_a_snorm8(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_A_SNORM16: + for (i = 0; i < n; ++i) { + pack_ubyte_a_snorm16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_L_SNORM8: + for (i = 0; i < n; ++i) { + pack_ubyte_l_snorm8(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_L_SNORM16: + for (i = 0; i < n; ++i) { + pack_ubyte_l_snorm16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_I_SNORM8: + for (i = 0; i < n; ++i) { + pack_ubyte_i_snorm8(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_I_SNORM16: + for (i = 0; i < n; ++i) { + pack_ubyte_i_snorm16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_R_SNORM8: + for (i = 0; i < n; ++i) { + pack_ubyte_r_snorm8(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_R_SNORM16: + for (i = 0; i < n; ++i) { + pack_ubyte_r_snorm16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_LA_SNORM16: + for (i = 0; i < n; ++i) { + pack_ubyte_la_snorm16(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_RGB_SNORM16: + for (i = 0; i < n; ++i) { + pack_ubyte_rgb_snorm16(src[i], d); + d += 6; + } + break; + + case MESA_FORMAT_RGBA_SNORM16: + for (i = 0; i < n; ++i) { + pack_ubyte_rgba_snorm16(src[i], d); + d += 8; + } + break; + + case MESA_FORMAT_RGBX_SNORM16: + for (i = 0; i < n; ++i) { + pack_ubyte_rgbx_snorm16(src[i], d); + d += 8; + } + break; + + case MESA_FORMAT_A8B8G8R8_SRGB: + for (i = 0; i < n; ++i) { + pack_ubyte_a8b8g8r8_srgb(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_B8G8R8A8_SRGB: + for (i = 0; i < n; ++i) { + pack_ubyte_b8g8r8a8_srgb(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_A8R8G8B8_SRGB: + for (i = 0; i < n; ++i) { + pack_ubyte_a8r8g8b8_srgb(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_B8G8R8X8_SRGB: + for (i = 0; i < n; ++i) { + pack_ubyte_b8g8r8x8_srgb(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_X8R8G8B8_SRGB: + for (i = 0; i < n; ++i) { + pack_ubyte_x8r8g8b8_srgb(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_R8G8B8A8_SRGB: + for (i = 0; i < n; ++i) { + pack_ubyte_r8g8b8a8_srgb(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_R8G8B8X8_SRGB: + for (i = 0; i < n; ++i) { + pack_ubyte_r8g8b8x8_srgb(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_X8B8G8R8_SRGB: + for (i = 0; i < n; ++i) { + pack_ubyte_x8b8g8r8_srgb(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_L8A8_SRGB: + for (i = 0; i < n; ++i) { + pack_ubyte_l8a8_srgb(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_A8L8_SRGB: + for (i = 0; i < n; ++i) { + pack_ubyte_a8l8_srgb(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_R_SRGB8: + for (i = 0; i < n; ++i) { + pack_ubyte_r_srgb8(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_L_SRGB8: + for (i = 0; i < n; ++i) { + pack_ubyte_l_srgb8(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_BGR_SRGB8: + for (i = 0; i < n; ++i) { + pack_ubyte_bgr_srgb8(src[i], d); + d += 3; + } + break; + + case MESA_FORMAT_R9G9B9E5_FLOAT: + for (i = 0; i < n; ++i) { + pack_ubyte_r9g9b9e5_float(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_R11G11B10_FLOAT: + for (i = 0; i < n; ++i) { + pack_ubyte_r11g11b10_float(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_A_FLOAT16: + for (i = 0; i < n; ++i) { + pack_ubyte_a_float16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_A_FLOAT32: + for (i = 0; i < n; ++i) { + pack_ubyte_a_float32(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_L_FLOAT16: + for (i = 0; i < n; ++i) { + pack_ubyte_l_float16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_L_FLOAT32: + for (i = 0; i < n; ++i) { + pack_ubyte_l_float32(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_LA_FLOAT16: + for (i = 0; i < n; ++i) { + pack_ubyte_la_float16(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_LA_FLOAT32: + for (i = 0; i < n; ++i) { + pack_ubyte_la_float32(src[i], d); + d += 8; + } + break; + + case MESA_FORMAT_I_FLOAT16: + for (i = 0; i < n; ++i) { + pack_ubyte_i_float16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_I_FLOAT32: + for (i = 0; i < n; ++i) { + pack_ubyte_i_float32(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_R_FLOAT16: + for (i = 0; i < n; ++i) { + pack_ubyte_r_float16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_R_FLOAT32: + for (i = 0; i < n; ++i) { + pack_ubyte_r_float32(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_RG_FLOAT16: + for (i = 0; i < n; ++i) { + pack_ubyte_rg_float16(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_RG_FLOAT32: + for (i = 0; i < n; ++i) { + pack_ubyte_rg_float32(src[i], d); + d += 8; + } + break; + + case MESA_FORMAT_RGB_FLOAT16: + for (i = 0; i < n; ++i) { + pack_ubyte_rgb_float16(src[i], d); + d += 6; + } + break; + + case MESA_FORMAT_RGB_FLOAT32: + for (i = 0; i < n; ++i) { + pack_ubyte_rgb_float32(src[i], d); + d += 12; + } + break; + + case MESA_FORMAT_RGBA_FLOAT16: + for (i = 0; i < n; ++i) { + pack_ubyte_rgba_float16(src[i], d); + d += 8; + } + break; + + case MESA_FORMAT_RGBA_FLOAT32: + for (i = 0; i < n; ++i) { + pack_ubyte_rgba_float32(src[i], d); + d += 16; + } + break; + + case MESA_FORMAT_RGBX_FLOAT16: + for (i = 0; i < n; ++i) { + pack_ubyte_rgbx_float16(src[i], d); + d += 8; + } + break; + + case MESA_FORMAT_RGBX_FLOAT32: + for (i = 0; i < n; ++i) { + pack_ubyte_rgbx_float32(src[i], d); + d += 16; + } + break; + + case MESA_FORMAT_A8B8G8R8_UINT: + for (i = 0; i < n; ++i) { + pack_ubyte_a8b8g8r8_uint(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_A8R8G8B8_UINT: + for (i = 0; i < n; ++i) { + pack_ubyte_a8r8g8b8_uint(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_R8G8B8A8_UINT: + for (i = 0; i < n; ++i) { + pack_ubyte_r8g8b8a8_uint(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_B8G8R8A8_UINT: + for (i = 0; i < n; ++i) { + pack_ubyte_b8g8r8a8_uint(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_B10G10R10A2_UINT: + for (i = 0; i < n; ++i) { + pack_ubyte_b10g10r10a2_uint(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_R10G10B10A2_UINT: + for (i = 0; i < n; ++i) { + pack_ubyte_r10g10b10a2_uint(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_A2B10G10R10_UINT: + for (i = 0; i < n; ++i) { + pack_ubyte_a2b10g10r10_uint(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_A2R10G10B10_UINT: + for (i = 0; i < n; ++i) { + pack_ubyte_a2r10g10b10_uint(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_B5G6R5_UINT: + for (i = 0; i < n; ++i) { + pack_ubyte_b5g6r5_uint(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_R5G6B5_UINT: + for (i = 0; i < n; ++i) { + pack_ubyte_r5g6b5_uint(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_B2G3R3_UINT: + for (i = 0; i < n; ++i) { + pack_ubyte_b2g3r3_uint(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_R3G3B2_UINT: + for (i = 0; i < n; ++i) { + pack_ubyte_r3g3b2_uint(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_A4B4G4R4_UINT: + for (i = 0; i < n; ++i) { + pack_ubyte_a4b4g4r4_uint(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_R4G4B4A4_UINT: + for (i = 0; i < n; ++i) { + pack_ubyte_r4g4b4a4_uint(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_B4G4R4A4_UINT: + for (i = 0; i < n; ++i) { + pack_ubyte_b4g4r4a4_uint(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_A4R4G4B4_UINT: + for (i = 0; i < n; ++i) { + pack_ubyte_a4r4g4b4_uint(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_A1B5G5R5_UINT: + for (i = 0; i < n; ++i) { + pack_ubyte_a1b5g5r5_uint(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_B5G5R5A1_UINT: + for (i = 0; i < n; ++i) { + pack_ubyte_b5g5r5a1_uint(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_A1R5G5B5_UINT: + for (i = 0; i < n; ++i) { + pack_ubyte_a1r5g5b5_uint(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_R5G5B5A1_UINT: + for (i = 0; i < n; ++i) { + pack_ubyte_r5g5b5a1_uint(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_A_UINT8: + for (i = 0; i < n; ++i) { + pack_ubyte_a_uint8(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_A_UINT16: + for (i = 0; i < n; ++i) { + pack_ubyte_a_uint16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_A_UINT32: + for (i = 0; i < n; ++i) { + pack_ubyte_a_uint32(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_A_SINT8: + for (i = 0; i < n; ++i) { + pack_ubyte_a_sint8(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_A_SINT16: + for (i = 0; i < n; ++i) { + pack_ubyte_a_sint16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_A_SINT32: + for (i = 0; i < n; ++i) { + pack_ubyte_a_sint32(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_I_UINT8: + for (i = 0; i < n; ++i) { + pack_ubyte_i_uint8(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_I_UINT16: + for (i = 0; i < n; ++i) { + pack_ubyte_i_uint16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_I_UINT32: + for (i = 0; i < n; ++i) { + pack_ubyte_i_uint32(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_I_SINT8: + for (i = 0; i < n; ++i) { + pack_ubyte_i_sint8(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_I_SINT16: + for (i = 0; i < n; ++i) { + pack_ubyte_i_sint16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_I_SINT32: + for (i = 0; i < n; ++i) { + pack_ubyte_i_sint32(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_L_UINT8: + for (i = 0; i < n; ++i) { + pack_ubyte_l_uint8(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_L_UINT16: + for (i = 0; i < n; ++i) { + pack_ubyte_l_uint16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_L_UINT32: + for (i = 0; i < n; ++i) { + pack_ubyte_l_uint32(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_L_SINT8: + for (i = 0; i < n; ++i) { + pack_ubyte_l_sint8(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_L_SINT16: + for (i = 0; i < n; ++i) { + pack_ubyte_l_sint16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_L_SINT32: + for (i = 0; i < n; ++i) { + pack_ubyte_l_sint32(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_LA_UINT8: + for (i = 0; i < n; ++i) { + pack_ubyte_la_uint8(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_LA_UINT16: + for (i = 0; i < n; ++i) { + pack_ubyte_la_uint16(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_LA_UINT32: + for (i = 0; i < n; ++i) { + pack_ubyte_la_uint32(src[i], d); + d += 8; + } + break; + + case MESA_FORMAT_LA_SINT8: + for (i = 0; i < n; ++i) { + pack_ubyte_la_sint8(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_LA_SINT16: + for (i = 0; i < n; ++i) { + pack_ubyte_la_sint16(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_LA_SINT32: + for (i = 0; i < n; ++i) { + pack_ubyte_la_sint32(src[i], d); + d += 8; + } + break; + + case MESA_FORMAT_R_UINT8: + for (i = 0; i < n; ++i) { + pack_ubyte_r_uint8(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_R_UINT16: + for (i = 0; i < n; ++i) { + pack_ubyte_r_uint16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_R_UINT32: + for (i = 0; i < n; ++i) { + pack_ubyte_r_uint32(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_R_SINT8: + for (i = 0; i < n; ++i) { + pack_ubyte_r_sint8(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_R_SINT16: + for (i = 0; i < n; ++i) { + pack_ubyte_r_sint16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_R_SINT32: + for (i = 0; i < n; ++i) { + pack_ubyte_r_sint32(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_RG_UINT8: + for (i = 0; i < n; ++i) { + pack_ubyte_rg_uint8(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_RG_UINT16: + for (i = 0; i < n; ++i) { + pack_ubyte_rg_uint16(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_RG_UINT32: + for (i = 0; i < n; ++i) { + pack_ubyte_rg_uint32(src[i], d); + d += 8; + } + break; + + case MESA_FORMAT_RG_SINT8: + for (i = 0; i < n; ++i) { + pack_ubyte_rg_sint8(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_RG_SINT16: + for (i = 0; i < n; ++i) { + pack_ubyte_rg_sint16(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_RG_SINT32: + for (i = 0; i < n; ++i) { + pack_ubyte_rg_sint32(src[i], d); + d += 8; + } + break; + + case MESA_FORMAT_RGB_UINT8: + for (i = 0; i < n; ++i) { + pack_ubyte_rgb_uint8(src[i], d); + d += 3; + } + break; + + case MESA_FORMAT_RGB_UINT16: + for (i = 0; i < n; ++i) { + pack_ubyte_rgb_uint16(src[i], d); + d += 6; + } + break; + + case MESA_FORMAT_RGB_UINT32: + for (i = 0; i < n; ++i) { + pack_ubyte_rgb_uint32(src[i], d); + d += 12; + } + break; + + case MESA_FORMAT_RGB_SINT8: + for (i = 0; i < n; ++i) { + pack_ubyte_rgb_sint8(src[i], d); + d += 3; + } + break; + + case MESA_FORMAT_RGB_SINT16: + for (i = 0; i < n; ++i) { + pack_ubyte_rgb_sint16(src[i], d); + d += 6; + } + break; + + case MESA_FORMAT_RGB_SINT32: + for (i = 0; i < n; ++i) { + pack_ubyte_rgb_sint32(src[i], d); + d += 12; + } + break; + + case MESA_FORMAT_RGBA_UINT8: + for (i = 0; i < n; ++i) { + pack_ubyte_rgba_uint8(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_RGBA_UINT16: + for (i = 0; i < n; ++i) { + pack_ubyte_rgba_uint16(src[i], d); + d += 8; + } + break; + + case MESA_FORMAT_RGBA_UINT32: + for (i = 0; i < n; ++i) { + pack_ubyte_rgba_uint32(src[i], d); + d += 16; + } + break; + + case MESA_FORMAT_RGBA_SINT8: + for (i = 0; i < n; ++i) { + pack_ubyte_rgba_sint8(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_RGBA_SINT16: + for (i = 0; i < n; ++i) { + pack_ubyte_rgba_sint16(src[i], d); + d += 8; + } + break; + + case MESA_FORMAT_RGBA_SINT32: + for (i = 0; i < n; ++i) { + pack_ubyte_rgba_sint32(src[i], d); + d += 16; + } + break; + + case MESA_FORMAT_RGBX_UINT8: + for (i = 0; i < n; ++i) { + pack_ubyte_rgbx_uint8(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_RGBX_UINT16: + for (i = 0; i < n; ++i) { + pack_ubyte_rgbx_uint16(src[i], d); + d += 8; + } + break; + + case MESA_FORMAT_RGBX_UINT32: + for (i = 0; i < n; ++i) { + pack_ubyte_rgbx_uint32(src[i], d); + d += 16; + } + break; + + case MESA_FORMAT_RGBX_SINT8: + for (i = 0; i < n; ++i) { + pack_ubyte_rgbx_sint8(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_RGBX_SINT16: + for (i = 0; i < n; ++i) { + pack_ubyte_rgbx_sint16(src[i], d); + d += 8; + } + break; + + case MESA_FORMAT_RGBX_SINT32: + for (i = 0; i < n; ++i) { + pack_ubyte_rgbx_sint32(src[i], d); + d += 16; + } + break; + default: + assert(!"Invalid format"); + } +} + +/** + * Pack a row of GLuint rgba[4] values to the destination. + */ +void +_mesa_pack_uint_rgba_row(mesa_format format, GLuint n, + const GLuint src[][4], void *dst) +{ + GLuint i; + GLubyte *d = dst; + + switch (format) { + + case MESA_FORMAT_A8B8G8R8_UINT: + for (i = 0; i < n; ++i) { + pack_uint_a8b8g8r8_uint(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_A8R8G8B8_UINT: + for (i = 0; i < n; ++i) { + pack_uint_a8r8g8b8_uint(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_R8G8B8A8_UINT: + for (i = 0; i < n; ++i) { + pack_uint_r8g8b8a8_uint(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_B8G8R8A8_UINT: + for (i = 0; i < n; ++i) { + pack_uint_b8g8r8a8_uint(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_B10G10R10A2_UINT: + for (i = 0; i < n; ++i) { + pack_uint_b10g10r10a2_uint(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_R10G10B10A2_UINT: + for (i = 0; i < n; ++i) { + pack_uint_r10g10b10a2_uint(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_A2B10G10R10_UINT: + for (i = 0; i < n; ++i) { + pack_uint_a2b10g10r10_uint(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_A2R10G10B10_UINT: + for (i = 0; i < n; ++i) { + pack_uint_a2r10g10b10_uint(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_B5G6R5_UINT: + for (i = 0; i < n; ++i) { + pack_uint_b5g6r5_uint(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_R5G6B5_UINT: + for (i = 0; i < n; ++i) { + pack_uint_r5g6b5_uint(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_B2G3R3_UINT: + for (i = 0; i < n; ++i) { + pack_uint_b2g3r3_uint(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_R3G3B2_UINT: + for (i = 0; i < n; ++i) { + pack_uint_r3g3b2_uint(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_A4B4G4R4_UINT: + for (i = 0; i < n; ++i) { + pack_uint_a4b4g4r4_uint(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_R4G4B4A4_UINT: + for (i = 0; i < n; ++i) { + pack_uint_r4g4b4a4_uint(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_B4G4R4A4_UINT: + for (i = 0; i < n; ++i) { + pack_uint_b4g4r4a4_uint(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_A4R4G4B4_UINT: + for (i = 0; i < n; ++i) { + pack_uint_a4r4g4b4_uint(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_A1B5G5R5_UINT: + for (i = 0; i < n; ++i) { + pack_uint_a1b5g5r5_uint(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_B5G5R5A1_UINT: + for (i = 0; i < n; ++i) { + pack_uint_b5g5r5a1_uint(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_A1R5G5B5_UINT: + for (i = 0; i < n; ++i) { + pack_uint_a1r5g5b5_uint(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_R5G5B5A1_UINT: + for (i = 0; i < n; ++i) { + pack_uint_r5g5b5a1_uint(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_A_UINT8: + for (i = 0; i < n; ++i) { + pack_uint_a_uint8(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_A_UINT16: + for (i = 0; i < n; ++i) { + pack_uint_a_uint16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_A_UINT32: + for (i = 0; i < n; ++i) { + pack_uint_a_uint32(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_A_SINT8: + for (i = 0; i < n; ++i) { + pack_uint_a_sint8(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_A_SINT16: + for (i = 0; i < n; ++i) { + pack_uint_a_sint16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_A_SINT32: + for (i = 0; i < n; ++i) { + pack_uint_a_sint32(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_I_UINT8: + for (i = 0; i < n; ++i) { + pack_uint_i_uint8(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_I_UINT16: + for (i = 0; i < n; ++i) { + pack_uint_i_uint16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_I_UINT32: + for (i = 0; i < n; ++i) { + pack_uint_i_uint32(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_I_SINT8: + for (i = 0; i < n; ++i) { + pack_uint_i_sint8(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_I_SINT16: + for (i = 0; i < n; ++i) { + pack_uint_i_sint16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_I_SINT32: + for (i = 0; i < n; ++i) { + pack_uint_i_sint32(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_L_UINT8: + for (i = 0; i < n; ++i) { + pack_uint_l_uint8(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_L_UINT16: + for (i = 0; i < n; ++i) { + pack_uint_l_uint16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_L_UINT32: + for (i = 0; i < n; ++i) { + pack_uint_l_uint32(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_L_SINT8: + for (i = 0; i < n; ++i) { + pack_uint_l_sint8(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_L_SINT16: + for (i = 0; i < n; ++i) { + pack_uint_l_sint16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_L_SINT32: + for (i = 0; i < n; ++i) { + pack_uint_l_sint32(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_LA_UINT8: + for (i = 0; i < n; ++i) { + pack_uint_la_uint8(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_LA_UINT16: + for (i = 0; i < n; ++i) { + pack_uint_la_uint16(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_LA_UINT32: + for (i = 0; i < n; ++i) { + pack_uint_la_uint32(src[i], d); + d += 8; + } + break; + + case MESA_FORMAT_LA_SINT8: + for (i = 0; i < n; ++i) { + pack_uint_la_sint8(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_LA_SINT16: + for (i = 0; i < n; ++i) { + pack_uint_la_sint16(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_LA_SINT32: + for (i = 0; i < n; ++i) { + pack_uint_la_sint32(src[i], d); + d += 8; + } + break; + + case MESA_FORMAT_R_UINT8: + for (i = 0; i < n; ++i) { + pack_uint_r_uint8(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_R_UINT16: + for (i = 0; i < n; ++i) { + pack_uint_r_uint16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_R_UINT32: + for (i = 0; i < n; ++i) { + pack_uint_r_uint32(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_R_SINT8: + for (i = 0; i < n; ++i) { + pack_uint_r_sint8(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_R_SINT16: + for (i = 0; i < n; ++i) { + pack_uint_r_sint16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_R_SINT32: + for (i = 0; i < n; ++i) { + pack_uint_r_sint32(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_RG_UINT8: + for (i = 0; i < n; ++i) { + pack_uint_rg_uint8(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_RG_UINT16: + for (i = 0; i < n; ++i) { + pack_uint_rg_uint16(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_RG_UINT32: + for (i = 0; i < n; ++i) { + pack_uint_rg_uint32(src[i], d); + d += 8; + } + break; + + case MESA_FORMAT_RG_SINT8: + for (i = 0; i < n; ++i) { + pack_uint_rg_sint8(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_RG_SINT16: + for (i = 0; i < n; ++i) { + pack_uint_rg_sint16(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_RG_SINT32: + for (i = 0; i < n; ++i) { + pack_uint_rg_sint32(src[i], d); + d += 8; + } + break; + + case MESA_FORMAT_RGB_UINT8: + for (i = 0; i < n; ++i) { + pack_uint_rgb_uint8(src[i], d); + d += 3; + } + break; + + case MESA_FORMAT_RGB_UINT16: + for (i = 0; i < n; ++i) { + pack_uint_rgb_uint16(src[i], d); + d += 6; + } + break; + + case MESA_FORMAT_RGB_UINT32: + for (i = 0; i < n; ++i) { + pack_uint_rgb_uint32(src[i], d); + d += 12; + } + break; + + case MESA_FORMAT_RGB_SINT8: + for (i = 0; i < n; ++i) { + pack_uint_rgb_sint8(src[i], d); + d += 3; + } + break; + + case MESA_FORMAT_RGB_SINT16: + for (i = 0; i < n; ++i) { + pack_uint_rgb_sint16(src[i], d); + d += 6; + } + break; + + case MESA_FORMAT_RGB_SINT32: + for (i = 0; i < n; ++i) { + pack_uint_rgb_sint32(src[i], d); + d += 12; + } + break; + + case MESA_FORMAT_RGBA_UINT8: + for (i = 0; i < n; ++i) { + pack_uint_rgba_uint8(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_RGBA_UINT16: + for (i = 0; i < n; ++i) { + pack_uint_rgba_uint16(src[i], d); + d += 8; + } + break; + + case MESA_FORMAT_RGBA_UINT32: + for (i = 0; i < n; ++i) { + pack_uint_rgba_uint32(src[i], d); + d += 16; + } + break; + + case MESA_FORMAT_RGBA_SINT8: + for (i = 0; i < n; ++i) { + pack_uint_rgba_sint8(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_RGBA_SINT16: + for (i = 0; i < n; ++i) { + pack_uint_rgba_sint16(src[i], d); + d += 8; + } + break; + + case MESA_FORMAT_RGBA_SINT32: + for (i = 0; i < n; ++i) { + pack_uint_rgba_sint32(src[i], d); + d += 16; + } + break; + + case MESA_FORMAT_RGBX_UINT8: + for (i = 0; i < n; ++i) { + pack_uint_rgbx_uint8(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_RGBX_UINT16: + for (i = 0; i < n; ++i) { + pack_uint_rgbx_uint16(src[i], d); + d += 8; + } + break; + + case MESA_FORMAT_RGBX_UINT32: + for (i = 0; i < n; ++i) { + pack_uint_rgbx_uint32(src[i], d); + d += 16; + } + break; + + case MESA_FORMAT_RGBX_SINT8: + for (i = 0; i < n; ++i) { + pack_uint_rgbx_sint8(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_RGBX_SINT16: + for (i = 0; i < n; ++i) { + pack_uint_rgbx_sint16(src[i], d); + d += 8; + } + break; + + case MESA_FORMAT_RGBX_SINT32: + for (i = 0; i < n; ++i) { + pack_uint_rgbx_sint32(src[i], d); + d += 16; + } + break; + default: + assert(!"Invalid format"); + } +} + +/** + * Pack a row of GLfloat rgba[4] values to the destination. + */ +void +_mesa_pack_float_rgba_row(mesa_format format, GLuint n, + const GLfloat src[][4], void *dst) +{ + GLuint i; + GLubyte *d = dst; + + switch (format) { + + case MESA_FORMAT_A8B8G8R8_UNORM: + for (i = 0; i < n; ++i) { + pack_float_a8b8g8r8_unorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_X8B8G8R8_UNORM: + for (i = 0; i < n; ++i) { + pack_float_x8b8g8r8_unorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_R8G8B8A8_UNORM: + for (i = 0; i < n; ++i) { + pack_float_r8g8b8a8_unorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_R8G8B8X8_UNORM: + for (i = 0; i < n; ++i) { + pack_float_r8g8b8x8_unorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_B8G8R8A8_UNORM: + for (i = 0; i < n; ++i) { + pack_float_b8g8r8a8_unorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_B8G8R8X8_UNORM: + for (i = 0; i < n; ++i) { + pack_float_b8g8r8x8_unorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_A8R8G8B8_UNORM: + for (i = 0; i < n; ++i) { + pack_float_a8r8g8b8_unorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_X8R8G8B8_UNORM: + for (i = 0; i < n; ++i) { + pack_float_x8r8g8b8_unorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_L16A16_UNORM: + for (i = 0; i < n; ++i) { + pack_float_l16a16_unorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_A16L16_UNORM: + for (i = 0; i < n; ++i) { + pack_float_a16l16_unorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_B5G6R5_UNORM: + for (i = 0; i < n; ++i) { + pack_float_b5g6r5_unorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_R5G6B5_UNORM: + for (i = 0; i < n; ++i) { + pack_float_r5g6b5_unorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_B4G4R4A4_UNORM: + for (i = 0; i < n; ++i) { + pack_float_b4g4r4a4_unorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_B4G4R4X4_UNORM: + for (i = 0; i < n; ++i) { + pack_float_b4g4r4x4_unorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_A4R4G4B4_UNORM: + for (i = 0; i < n; ++i) { + pack_float_a4r4g4b4_unorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_A1B5G5R5_UNORM: + for (i = 0; i < n; ++i) { + pack_float_a1b5g5r5_unorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_X1B5G5R5_UNORM: + for (i = 0; i < n; ++i) { + pack_float_x1b5g5r5_unorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_B5G5R5A1_UNORM: + for (i = 0; i < n; ++i) { + pack_float_b5g5r5a1_unorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_B5G5R5X1_UNORM: + for (i = 0; i < n; ++i) { + pack_float_b5g5r5x1_unorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_A1R5G5B5_UNORM: + for (i = 0; i < n; ++i) { + pack_float_a1r5g5b5_unorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_L8A8_UNORM: + for (i = 0; i < n; ++i) { + pack_float_l8a8_unorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_A8L8_UNORM: + for (i = 0; i < n; ++i) { + pack_float_a8l8_unorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_R8G8_UNORM: + for (i = 0; i < n; ++i) { + pack_float_r8g8_unorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_G8R8_UNORM: + for (i = 0; i < n; ++i) { + pack_float_g8r8_unorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_L4A4_UNORM: + for (i = 0; i < n; ++i) { + pack_float_l4a4_unorm(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_B2G3R3_UNORM: + for (i = 0; i < n; ++i) { + pack_float_b2g3r3_unorm(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_R16G16_UNORM: + for (i = 0; i < n; ++i) { + pack_float_r16g16_unorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_G16R16_UNORM: + for (i = 0; i < n; ++i) { + pack_float_g16r16_unorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_B10G10R10A2_UNORM: + for (i = 0; i < n; ++i) { + pack_float_b10g10r10a2_unorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_B10G10R10X2_UNORM: + for (i = 0; i < n; ++i) { + pack_float_b10g10r10x2_unorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_R10G10B10A2_UNORM: + for (i = 0; i < n; ++i) { + pack_float_r10g10b10a2_unorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_R10G10B10X2_UNORM: + for (i = 0; i < n; ++i) { + pack_float_r10g10b10x2_unorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_R3G3B2_UNORM: + for (i = 0; i < n; ++i) { + pack_float_r3g3b2_unorm(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_A4B4G4R4_UNORM: + for (i = 0; i < n; ++i) { + pack_float_a4b4g4r4_unorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_R4G4B4A4_UNORM: + for (i = 0; i < n; ++i) { + pack_float_r4g4b4a4_unorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_R5G5B5A1_UNORM: + for (i = 0; i < n; ++i) { + pack_float_r5g5b5a1_unorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_A2B10G10R10_UNORM: + for (i = 0; i < n; ++i) { + pack_float_a2b10g10r10_unorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_A2R10G10B10_UNORM: + for (i = 0; i < n; ++i) { + pack_float_a2r10g10b10_unorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_A_UNORM8: + for (i = 0; i < n; ++i) { + pack_float_a_unorm8(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_A_UNORM16: + for (i = 0; i < n; ++i) { + pack_float_a_unorm16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_L_UNORM8: + for (i = 0; i < n; ++i) { + pack_float_l_unorm8(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_L_UNORM16: + for (i = 0; i < n; ++i) { + pack_float_l_unorm16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_I_UNORM8: + for (i = 0; i < n; ++i) { + pack_float_i_unorm8(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_I_UNORM16: + for (i = 0; i < n; ++i) { + pack_float_i_unorm16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_R_UNORM8: + for (i = 0; i < n; ++i) { + pack_float_r_unorm8(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_R_UNORM16: + for (i = 0; i < n; ++i) { + pack_float_r_unorm16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_BGR_UNORM8: + for (i = 0; i < n; ++i) { + pack_float_bgr_unorm8(src[i], d); + d += 3; + } + break; + + case MESA_FORMAT_RGB_UNORM8: + for (i = 0; i < n; ++i) { + pack_float_rgb_unorm8(src[i], d); + d += 3; + } + break; + + case MESA_FORMAT_RGBA_UNORM16: + for (i = 0; i < n; ++i) { + pack_float_rgba_unorm16(src[i], d); + d += 8; + } + break; + + case MESA_FORMAT_RGBX_UNORM16: + for (i = 0; i < n; ++i) { + pack_float_rgbx_unorm16(src[i], d); + d += 8; + } + break; + + case MESA_FORMAT_A8B8G8R8_SNORM: + for (i = 0; i < n; ++i) { + pack_float_a8b8g8r8_snorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_X8B8G8R8_SNORM: + for (i = 0; i < n; ++i) { + pack_float_x8b8g8r8_snorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_R8G8B8A8_SNORM: + for (i = 0; i < n; ++i) { + pack_float_r8g8b8a8_snorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_R8G8B8X8_SNORM: + for (i = 0; i < n; ++i) { + pack_float_r8g8b8x8_snorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_R16G16_SNORM: + for (i = 0; i < n; ++i) { + pack_float_r16g16_snorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_G16R16_SNORM: + for (i = 0; i < n; ++i) { + pack_float_g16r16_snorm(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_R8G8_SNORM: + for (i = 0; i < n; ++i) { + pack_float_r8g8_snorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_G8R8_SNORM: + for (i = 0; i < n; ++i) { + pack_float_g8r8_snorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_L8A8_SNORM: + for (i = 0; i < n; ++i) { + pack_float_l8a8_snorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_A8L8_SNORM: + for (i = 0; i < n; ++i) { + pack_float_a8l8_snorm(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_A_SNORM8: + for (i = 0; i < n; ++i) { + pack_float_a_snorm8(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_A_SNORM16: + for (i = 0; i < n; ++i) { + pack_float_a_snorm16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_L_SNORM8: + for (i = 0; i < n; ++i) { + pack_float_l_snorm8(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_L_SNORM16: + for (i = 0; i < n; ++i) { + pack_float_l_snorm16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_I_SNORM8: + for (i = 0; i < n; ++i) { + pack_float_i_snorm8(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_I_SNORM16: + for (i = 0; i < n; ++i) { + pack_float_i_snorm16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_R_SNORM8: + for (i = 0; i < n; ++i) { + pack_float_r_snorm8(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_R_SNORM16: + for (i = 0; i < n; ++i) { + pack_float_r_snorm16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_LA_SNORM16: + for (i = 0; i < n; ++i) { + pack_float_la_snorm16(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_RGB_SNORM16: + for (i = 0; i < n; ++i) { + pack_float_rgb_snorm16(src[i], d); + d += 6; + } + break; + + case MESA_FORMAT_RGBA_SNORM16: + for (i = 0; i < n; ++i) { + pack_float_rgba_snorm16(src[i], d); + d += 8; + } + break; + + case MESA_FORMAT_RGBX_SNORM16: + for (i = 0; i < n; ++i) { + pack_float_rgbx_snorm16(src[i], d); + d += 8; + } + break; + + case MESA_FORMAT_A8B8G8R8_SRGB: + for (i = 0; i < n; ++i) { + pack_float_a8b8g8r8_srgb(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_B8G8R8A8_SRGB: + for (i = 0; i < n; ++i) { + pack_float_b8g8r8a8_srgb(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_A8R8G8B8_SRGB: + for (i = 0; i < n; ++i) { + pack_float_a8r8g8b8_srgb(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_B8G8R8X8_SRGB: + for (i = 0; i < n; ++i) { + pack_float_b8g8r8x8_srgb(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_X8R8G8B8_SRGB: + for (i = 0; i < n; ++i) { + pack_float_x8r8g8b8_srgb(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_R8G8B8A8_SRGB: + for (i = 0; i < n; ++i) { + pack_float_r8g8b8a8_srgb(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_R8G8B8X8_SRGB: + for (i = 0; i < n; ++i) { + pack_float_r8g8b8x8_srgb(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_X8B8G8R8_SRGB: + for (i = 0; i < n; ++i) { + pack_float_x8b8g8r8_srgb(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_L8A8_SRGB: + for (i = 0; i < n; ++i) { + pack_float_l8a8_srgb(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_A8L8_SRGB: + for (i = 0; i < n; ++i) { + pack_float_a8l8_srgb(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_R_SRGB8: + for (i = 0; i < n; ++i) { + pack_float_r_srgb8(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_L_SRGB8: + for (i = 0; i < n; ++i) { + pack_float_l_srgb8(src[i], d); + d += 1; + } + break; + + case MESA_FORMAT_BGR_SRGB8: + for (i = 0; i < n; ++i) { + pack_float_bgr_srgb8(src[i], d); + d += 3; + } + break; + + case MESA_FORMAT_R9G9B9E5_FLOAT: + for (i = 0; i < n; ++i) { + pack_float_r9g9b9e5_float(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_R11G11B10_FLOAT: + for (i = 0; i < n; ++i) { + pack_float_r11g11b10_float(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_A_FLOAT16: + for (i = 0; i < n; ++i) { + pack_float_a_float16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_A_FLOAT32: + for (i = 0; i < n; ++i) { + pack_float_a_float32(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_L_FLOAT16: + for (i = 0; i < n; ++i) { + pack_float_l_float16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_L_FLOAT32: + for (i = 0; i < n; ++i) { + pack_float_l_float32(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_LA_FLOAT16: + for (i = 0; i < n; ++i) { + pack_float_la_float16(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_LA_FLOAT32: + for (i = 0; i < n; ++i) { + pack_float_la_float32(src[i], d); + d += 8; + } + break; + + case MESA_FORMAT_I_FLOAT16: + for (i = 0; i < n; ++i) { + pack_float_i_float16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_I_FLOAT32: + for (i = 0; i < n; ++i) { + pack_float_i_float32(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_R_FLOAT16: + for (i = 0; i < n; ++i) { + pack_float_r_float16(src[i], d); + d += 2; + } + break; + + case MESA_FORMAT_R_FLOAT32: + for (i = 0; i < n; ++i) { + pack_float_r_float32(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_RG_FLOAT16: + for (i = 0; i < n; ++i) { + pack_float_rg_float16(src[i], d); + d += 4; + } + break; + + case MESA_FORMAT_RG_FLOAT32: + for (i = 0; i < n; ++i) { + pack_float_rg_float32(src[i], d); + d += 8; + } + break; + + case MESA_FORMAT_RGB_FLOAT16: + for (i = 0; i < n; ++i) { + pack_float_rgb_float16(src[i], d); + d += 6; + } + break; + + case MESA_FORMAT_RGB_FLOAT32: + for (i = 0; i < n; ++i) { + pack_float_rgb_float32(src[i], d); + d += 12; + } + break; + + case MESA_FORMAT_RGBA_FLOAT16: + for (i = 0; i < n; ++i) { + pack_float_rgba_float16(src[i], d); + d += 8; + } + break; + + case MESA_FORMAT_RGBA_FLOAT32: + for (i = 0; i < n; ++i) { + pack_float_rgba_float32(src[i], d); + d += 16; + } + break; + + case MESA_FORMAT_RGBX_FLOAT16: + for (i = 0; i < n; ++i) { + pack_float_rgbx_float16(src[i], d); + d += 8; + } + break; + + case MESA_FORMAT_RGBX_FLOAT32: + for (i = 0; i < n; ++i) { + pack_float_rgbx_float32(src[i], d); + d += 16; + } + break; + default: + assert(!"Invalid format"); + } +} + +/** + * Pack a 2D image of ubyte RGBA pixels in the given format. + * \param srcRowStride source image row stride in bytes + * \param dstRowStride destination image row stride in bytes + */ +void +_mesa_pack_ubyte_rgba_rect(mesa_format format, GLuint width, GLuint height, + const GLubyte *src, GLint srcRowStride, + void *dst, GLint dstRowStride) +{ + GLubyte *dstUB = dst; + GLuint i; + + if (srcRowStride == width * 4 * sizeof(GLubyte) && + dstRowStride == _mesa_format_row_stride(format, width)) { + /* do whole image at once */ + _mesa_pack_ubyte_rgba_row(format, width * height, + (const GLubyte (*)[4]) src, dst); + } + else { + /* row by row */ + for (i = 0; i < height; i++) { + _mesa_pack_ubyte_rgba_row(format, width, + (const GLubyte (*)[4]) src, dstUB); + src += srcRowStride; + dstUB += dstRowStride; + } + } +} + + +/** Helper struct for MESA_FORMAT_Z32_FLOAT_S8X24_UINT */ +struct z32f_x24s8 +{ + float z; + uint32_t x24s8; +}; + + +/** + ** Pack float Z pixels + **/ + +static void +pack_float_S8_UINT_Z24_UNORM(const GLfloat *src, void *dst) +{ + /* don't disturb the stencil values */ + GLuint *d = ((GLuint *) dst); + const GLdouble scale = (GLdouble) 0xffffff; + GLuint s = *d & 0xff; + GLuint z = (GLuint) (*src * scale); + assert(z <= 0xffffff); + *d = (z << 8) | s; +} + +static void +pack_float_Z24_UNORM_S8_UINT(const GLfloat *src, void *dst) +{ + /* don't disturb the stencil values */ + GLuint *d = ((GLuint *) dst); + const GLdouble scale = (GLdouble) 0xffffff; + GLuint s = *d & 0xff000000; + GLuint z = (GLuint) (*src * scale); + assert(z <= 0xffffff); + *d = s | z; +} + +static void +pack_float_Z_UNORM16(const GLfloat *src, void *dst) +{ + GLushort *d = ((GLushort *) dst); + const GLfloat scale = (GLfloat) 0xffff; + *d = (GLushort) (*src * scale); +} + +static void +pack_float_Z_UNORM32(const GLfloat *src, void *dst) +{ + GLuint *d = ((GLuint *) dst); + const GLdouble scale = (GLdouble) 0xffffffff; + *d = (GLuint) (*src * scale); +} + +/** + ** Pack float to Z_FLOAT32 or Z_FLOAT32_X24S8. + **/ + +static void +pack_float_Z_FLOAT32(const GLfloat *src, void *dst) +{ + GLfloat *d = (GLfloat *) dst; + *d = *src; +} + +gl_pack_float_z_func +_mesa_get_pack_float_z_func(mesa_format format) +{ + switch (format) { + case MESA_FORMAT_S8_UINT_Z24_UNORM: + case MESA_FORMAT_X8_UINT_Z24_UNORM: + return pack_float_S8_UINT_Z24_UNORM; + case MESA_FORMAT_Z24_UNORM_S8_UINT: + case MESA_FORMAT_Z24_UNORM_X8_UINT: + return pack_float_Z24_UNORM_S8_UINT; + case MESA_FORMAT_Z_UNORM16: + return pack_float_Z_UNORM16; + case MESA_FORMAT_Z_UNORM32: + return pack_float_Z_UNORM32; + case MESA_FORMAT_Z_FLOAT32: + case MESA_FORMAT_Z32_FLOAT_S8X24_UINT: + return pack_float_Z_FLOAT32; + default: + _mesa_problem(NULL, + "unexpected format in _mesa_get_pack_float_z_func()"); + return NULL; + } +} + + + +/** + ** Pack uint Z pixels. The incoming src value is always in + ** the range [0, 2^32-1]. + **/ + +static void +pack_uint_S8_UINT_Z24_UNORM(const GLuint *src, void *dst) +{ + /* don't disturb the stencil values */ + GLuint *d = ((GLuint *) dst); + GLuint s = *d & 0xff; + GLuint z = *src & 0xffffff00; + *d = z | s; +} + +static void +pack_uint_Z24_UNORM_S8_UINT(const GLuint *src, void *dst) +{ + /* don't disturb the stencil values */ + GLuint *d = ((GLuint *) dst); + GLuint s = *d & 0xff000000; + GLuint z = *src >> 8; + *d = s | z; +} + +static void +pack_uint_Z_UNORM16(const GLuint *src, void *dst) +{ + GLushort *d = ((GLushort *) dst); + *d = *src >> 16; +} + +static void +pack_uint_Z_UNORM32(const GLuint *src, void *dst) +{ + GLuint *d = ((GLuint *) dst); + *d = *src; +} + +/** + ** Pack uint to Z_FLOAT32 or Z_FLOAT32_X24S8. + **/ + +static void +pack_uint_Z_FLOAT32(const GLuint *src, void *dst) +{ + GLfloat *d = ((GLfloat *) dst); + const GLdouble scale = 1.0 / (GLdouble) 0xffffffff; + *d = (GLfloat) (*src * scale); + assert(*d >= 0.0f); + assert(*d <= 1.0f); +} + +gl_pack_uint_z_func +_mesa_get_pack_uint_z_func(mesa_format format) +{ + switch (format) { + case MESA_FORMAT_S8_UINT_Z24_UNORM: + case MESA_FORMAT_X8_UINT_Z24_UNORM: + return pack_uint_S8_UINT_Z24_UNORM; + case MESA_FORMAT_Z24_UNORM_S8_UINT: + case MESA_FORMAT_Z24_UNORM_X8_UINT: + return pack_uint_Z24_UNORM_S8_UINT; + case MESA_FORMAT_Z_UNORM16: + return pack_uint_Z_UNORM16; + case MESA_FORMAT_Z_UNORM32: + return pack_uint_Z_UNORM32; + case MESA_FORMAT_Z_FLOAT32: + case MESA_FORMAT_Z32_FLOAT_S8X24_UINT: + return pack_uint_Z_FLOAT32; + default: + _mesa_problem(NULL, "unexpected format in _mesa_get_pack_uint_z_func()"); + return NULL; + } +} + + +/** + ** Pack ubyte stencil pixels + **/ + +static void +pack_ubyte_stencil_Z24_S8(const GLubyte *src, void *dst) +{ + /* don't disturb the Z values */ + GLuint *d = ((GLuint *) dst); + GLuint s = *src; + GLuint z = *d & 0xffffff00; + *d = z | s; +} + +static void +pack_ubyte_stencil_S8_Z24(const GLubyte *src, void *dst) +{ + /* don't disturb the Z values */ + GLuint *d = ((GLuint *) dst); + GLuint s = *src << 24; + GLuint z = *d & 0xffffff; + *d = s | z; +} + +static void +pack_ubyte_stencil_S8(const GLubyte *src, void *dst) +{ + GLubyte *d = (GLubyte *) dst; + *d = *src; +} + +static void +pack_ubyte_stencil_Z32_FLOAT_X24S8(const GLubyte *src, void *dst) +{ + GLfloat *d = ((GLfloat *) dst); + d[1] = *src; +} + + +gl_pack_ubyte_stencil_func +_mesa_get_pack_ubyte_stencil_func(mesa_format format) +{ + switch (format) { + case MESA_FORMAT_S8_UINT_Z24_UNORM: + return pack_ubyte_stencil_Z24_S8; + case MESA_FORMAT_Z24_UNORM_S8_UINT: + return pack_ubyte_stencil_S8_Z24; + case MESA_FORMAT_S_UINT8: + return pack_ubyte_stencil_S8; + case MESA_FORMAT_Z32_FLOAT_S8X24_UINT: + return pack_ubyte_stencil_Z32_FLOAT_X24S8; + default: + _mesa_problem(NULL, + "unexpected format in _mesa_pack_ubyte_stencil_func()"); + return NULL; + } +} + + + +void +_mesa_pack_float_z_row(mesa_format format, GLuint n, + const GLfloat *src, void *dst) +{ + switch (format) { + case MESA_FORMAT_S8_UINT_Z24_UNORM: + case MESA_FORMAT_X8_UINT_Z24_UNORM: + { + /* don't disturb the stencil values */ + GLuint *d = ((GLuint *) dst); + const GLdouble scale = (GLdouble) 0xffffff; + GLuint i; + for (i = 0; i < n; i++) { + GLuint s = d[i] & 0xff; + GLuint z = (GLuint) (src[i] * scale); + assert(z <= 0xffffff); + d[i] = (z << 8) | s; + } + } + break; + case MESA_FORMAT_Z24_UNORM_S8_UINT: + case MESA_FORMAT_Z24_UNORM_X8_UINT: + { + /* don't disturb the stencil values */ + GLuint *d = ((GLuint *) dst); + const GLdouble scale = (GLdouble) 0xffffff; + GLuint i; + for (i = 0; i < n; i++) { + GLuint s = d[i] & 0xff000000; + GLuint z = (GLuint) (src[i] * scale); + assert(z <= 0xffffff); + d[i] = s | z; + } + } + break; + case MESA_FORMAT_Z_UNORM16: + { + GLushort *d = ((GLushort *) dst); + const GLfloat scale = (GLfloat) 0xffff; + GLuint i; + for (i = 0; i < n; i++) { + d[i] = (GLushort) (src[i] * scale); + } + } + break; + case MESA_FORMAT_Z_UNORM32: + { + GLuint *d = ((GLuint *) dst); + const GLdouble scale = (GLdouble) 0xffffffff; + GLuint i; + for (i = 0; i < n; i++) { + d[i] = (GLuint) (src[i] * scale); + } + } + break; + case MESA_FORMAT_Z_FLOAT32: + memcpy(dst, src, n * sizeof(GLfloat)); + break; + case MESA_FORMAT_Z32_FLOAT_S8X24_UINT: + { + struct z32f_x24s8 *d = (struct z32f_x24s8 *) dst; + GLuint i; + for (i = 0; i < n; i++) { + d[i].z = src[i]; + } + } + break; + default: + _mesa_problem(NULL, "unexpected format in _mesa_pack_float_z_row()"); + } +} + + +/** + * The incoming Z values are always in the range [0, 0xffffffff]. + */ +void +_mesa_pack_uint_z_row(mesa_format format, GLuint n, + const GLuint *src, void *dst) +{ + switch (format) { + case MESA_FORMAT_S8_UINT_Z24_UNORM: + case MESA_FORMAT_X8_UINT_Z24_UNORM: + { + /* don't disturb the stencil values */ + GLuint *d = ((GLuint *) dst); + GLuint i; + for (i = 0; i < n; i++) { + GLuint s = d[i] & 0xff; + GLuint z = src[i] & 0xffffff00; + d[i] = z | s; + } + } + break; + case MESA_FORMAT_Z24_UNORM_S8_UINT: + case MESA_FORMAT_Z24_UNORM_X8_UINT: + { + /* don't disturb the stencil values */ + GLuint *d = ((GLuint *) dst); + GLuint i; + for (i = 0; i < n; i++) { + GLuint s = d[i] & 0xff000000; + GLuint z = src[i] >> 8; + d[i] = s | z; + } + } + break; + case MESA_FORMAT_Z_UNORM16: + { + GLushort *d = ((GLushort *) dst); + GLuint i; + for (i = 0; i < n; i++) { + d[i] = src[i] >> 16; + } + } + break; + case MESA_FORMAT_Z_UNORM32: + memcpy(dst, src, n * sizeof(GLfloat)); + break; + case MESA_FORMAT_Z_FLOAT32: + { + GLuint *d = ((GLuint *) dst); + const GLdouble scale = 1.0 / (GLdouble) 0xffffffff; + GLuint i; + for (i = 0; i < n; i++) { + d[i] = (GLuint) (src[i] * scale); + assert(d[i] >= 0.0f); + assert(d[i] <= 1.0f); + } + } + break; + case MESA_FORMAT_Z32_FLOAT_S8X24_UINT: + { + struct z32f_x24s8 *d = (struct z32f_x24s8 *) dst; + const GLdouble scale = 1.0 / (GLdouble) 0xffffffff; + GLuint i; + for (i = 0; i < n; i++) { + d[i].z = (GLfloat) (src[i] * scale); + assert(d[i].z >= 0.0f); + assert(d[i].z <= 1.0f); + } + } + break; + default: + _mesa_problem(NULL, "unexpected format in _mesa_pack_uint_z_row()"); + } +} + + +void +_mesa_pack_ubyte_stencil_row(mesa_format format, GLuint n, + const GLubyte *src, void *dst) +{ + switch (format) { + case MESA_FORMAT_S8_UINT_Z24_UNORM: + { + /* don't disturb the Z values */ + GLuint *d = ((GLuint *) dst); + GLuint i; + for (i = 0; i < n; i++) { + GLuint s = src[i]; + GLuint z = d[i] & 0xffffff00; + d[i] = z | s; + } + } + break; + case MESA_FORMAT_Z24_UNORM_S8_UINT: + { + /* don't disturb the Z values */ + GLuint *d = ((GLuint *) dst); + GLuint i; + for (i = 0; i < n; i++) { + GLuint s = src[i] << 24; + GLuint z = d[i] & 0xffffff; + d[i] = s | z; + } + } + break; + case MESA_FORMAT_S_UINT8: + memcpy(dst, src, n * sizeof(GLubyte)); + break; + case MESA_FORMAT_Z32_FLOAT_S8X24_UINT: + { + struct z32f_x24s8 *d = (struct z32f_x24s8 *) dst; + GLuint i; + for (i = 0; i < n; i++) { + d[i].x24s8 = src[i]; + } + } + break; + default: + _mesa_problem(NULL, "unexpected format in _mesa_pack_ubyte_stencil_row()"); + } +} + + +/** + * Incoming Z/stencil values are always in uint_24_8 format. + */ +void +_mesa_pack_uint_24_8_depth_stencil_row(mesa_format format, GLuint n, + const GLuint *src, void *dst) +{ + switch (format) { + case MESA_FORMAT_S8_UINT_Z24_UNORM: + memcpy(dst, src, n * sizeof(GLuint)); + break; + case MESA_FORMAT_Z24_UNORM_S8_UINT: + { + GLuint *d = ((GLuint *) dst); + GLuint i; + for (i = 0; i < n; i++) { + GLuint s = src[i] << 24; + GLuint z = src[i] >> 8; + d[i] = s | z; + } + } + break; + case MESA_FORMAT_Z32_FLOAT_S8X24_UINT: + { + const GLdouble scale = 1.0 / (GLdouble) 0xffffff; + struct z32f_x24s8 *d = (struct z32f_x24s8 *) dst; + GLuint i; + for (i = 0; i < n; i++) { + GLfloat z = (GLfloat) ((src[i] >> 8) * scale); + d[i].z = z; + d[i].x24s8 = src[i]; + } + } + break; + default: + _mesa_problem(NULL, "bad format %s in _mesa_pack_ubyte_s_row", + _mesa_get_format_name(format)); + return; + } +} + + + +/** + * Convert a boolean color mask to a packed color where each channel of + * the packed value at dst will be 0 or ~0 depending on the colorMask. + */ +void +_mesa_pack_colormask(mesa_format format, const GLubyte colorMask[4], void *dst) +{ + GLfloat maskColor[4]; + + switch (_mesa_get_format_datatype(format)) { + case GL_UNSIGNED_NORMALIZED: + /* simple: 1.0 will convert to ~0 in the right bit positions */ + maskColor[0] = colorMask[0] ? 1.0f : 0.0f; + maskColor[1] = colorMask[1] ? 1.0f : 0.0f; + maskColor[2] = colorMask[2] ? 1.0f : 0.0f; + maskColor[3] = colorMask[3] ? 1.0f : 0.0f; + _mesa_pack_float_rgba_row(format, 1, + (const GLfloat (*)[4]) maskColor, dst); + break; + case GL_SIGNED_NORMALIZED: + case GL_FLOAT: + /* These formats are harder because it's hard to know the floating + * point values that will convert to ~0 for each color channel's bits. + * This solution just generates a non-zero value for each color channel + * then fixes up the non-zero values to be ~0. + * Note: we'll need to add special case code if we ever have to deal + * with formats with unequal color channel sizes, like R11_G11_B10. + * We issue a warning below for channel sizes other than 8,16,32. + */ + { + GLuint bits = _mesa_get_format_max_bits(format); /* bits per chan */ + GLuint bytes = _mesa_get_format_bytes(format); + GLuint i; + + /* this should put non-zero values into the channels of dst */ + maskColor[0] = colorMask[0] ? -1.0f : 0.0f; + maskColor[1] = colorMask[1] ? -1.0f : 0.0f; + maskColor[2] = colorMask[2] ? -1.0f : 0.0f; + maskColor[3] = colorMask[3] ? -1.0f : 0.0f; + _mesa_pack_float_rgba_row(format, 1, + (const GLfloat (*)[4]) maskColor, dst); + + /* fix-up the dst channels by converting non-zero values to ~0 */ + if (bits == 8) { + GLubyte *d = (GLubyte *) dst; + for (i = 0; i < bytes; i++) { + d[i] = d[i] ? 0xff : 0x0; + } + } + else if (bits == 16) { + GLushort *d = (GLushort *) dst; + for (i = 0; i < bytes / 2; i++) { + d[i] = d[i] ? 0xffff : 0x0; + } + } + else if (bits == 32) { + GLuint *d = (GLuint *) dst; + for (i = 0; i < bytes / 4; i++) { + d[i] = d[i] ? 0xffffffffU : 0x0; + } + } + else { + _mesa_problem(NULL, "unexpected size in _mesa_pack_colormask()"); + return; + } + } + break; + default: + _mesa_problem(NULL, "unexpected format data type in gen_color_mask()"); + return; + } +} + diff --git a/prebuilt-intermediates/main/format_unpack.c b/prebuilt-intermediates/main/format_unpack.c new file mode 100644 index 00000000000..d3527d6e834 --- /dev/null +++ b/prebuilt-intermediates/main/format_unpack.c @@ -0,0 +1,7654 @@ +/* + * Mesa 3-D graphics library + * + * Copyright (c) 2011 VMware, Inc. + * Copyright (c) 2014 Intel Corporation. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included + * in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ + + +/** + * Color, depth, stencil packing functions. + * Used to pack basic color, depth and stencil formats to specific + * hardware formats. + * + * There are both per-pixel and per-row packing functions: + * - The former will be used by swrast to write values to the color, depth, + * stencil buffers when drawing points, lines and masked spans. + * - The later will be used for image-oriented functions like glDrawPixels, + * glAccum, and glTexImage. + */ + +#include + +#include "errors.h" +#include "format_unpack.h" +#include "format_utils.h" +#include "macros.h" +#include "util/format_rgb9e5.h" +#include "util/format_r11g11b10f.h" +#include "util/format_srgb.h" + +#define UNPACK(SRC, OFFSET, BITS) (((SRC) >> (OFFSET)) & MAX_UINT(BITS)) + + + +/* float unpacking functions */ + + +static inline void +unpack_float_a8b8g8r8_unorm(const void *void_src, GLfloat dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t a = UNPACK(*src, 0, 8); + uint8_t b = UNPACK(*src, 8, 8); + uint8_t g = UNPACK(*src, 16, 8); + uint8_t r = UNPACK(*src, 24, 8); + + + + dst[0] = _mesa_unorm_to_float(r, 8); + + + dst[1] = _mesa_unorm_to_float(g, 8); + + + dst[2] = _mesa_unorm_to_float(b, 8); + + + dst[3] = _mesa_unorm_to_float(a, 8); +} + +static inline void +unpack_float_x8b8g8r8_unorm(const void *void_src, GLfloat dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t b = UNPACK(*src, 8, 8); + uint8_t g = UNPACK(*src, 16, 8); + uint8_t r = UNPACK(*src, 24, 8); + + + + dst[0] = _mesa_unorm_to_float(r, 8); + + + dst[1] = _mesa_unorm_to_float(g, 8); + + + dst[2] = _mesa_unorm_to_float(b, 8); + + dst[3] = 1.0f; +} + +static inline void +unpack_float_r8g8b8a8_unorm(const void *void_src, GLfloat dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t r = UNPACK(*src, 0, 8); + uint8_t g = UNPACK(*src, 8, 8); + uint8_t b = UNPACK(*src, 16, 8); + uint8_t a = UNPACK(*src, 24, 8); + + + + dst[0] = _mesa_unorm_to_float(r, 8); + + + dst[1] = _mesa_unorm_to_float(g, 8); + + + dst[2] = _mesa_unorm_to_float(b, 8); + + + dst[3] = _mesa_unorm_to_float(a, 8); +} + +static inline void +unpack_float_r8g8b8x8_unorm(const void *void_src, GLfloat dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t r = UNPACK(*src, 0, 8); + uint8_t g = UNPACK(*src, 8, 8); + uint8_t b = UNPACK(*src, 16, 8); + + + + dst[0] = _mesa_unorm_to_float(r, 8); + + + dst[1] = _mesa_unorm_to_float(g, 8); + + + dst[2] = _mesa_unorm_to_float(b, 8); + + dst[3] = 1.0f; +} + +static inline void +unpack_float_b8g8r8a8_unorm(const void *void_src, GLfloat dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t b = UNPACK(*src, 0, 8); + uint8_t g = UNPACK(*src, 8, 8); + uint8_t r = UNPACK(*src, 16, 8); + uint8_t a = UNPACK(*src, 24, 8); + + + + dst[0] = _mesa_unorm_to_float(r, 8); + + + dst[1] = _mesa_unorm_to_float(g, 8); + + + dst[2] = _mesa_unorm_to_float(b, 8); + + + dst[3] = _mesa_unorm_to_float(a, 8); +} + +static inline void +unpack_float_b8g8r8x8_unorm(const void *void_src, GLfloat dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t b = UNPACK(*src, 0, 8); + uint8_t g = UNPACK(*src, 8, 8); + uint8_t r = UNPACK(*src, 16, 8); + + + + dst[0] = _mesa_unorm_to_float(r, 8); + + + dst[1] = _mesa_unorm_to_float(g, 8); + + + dst[2] = _mesa_unorm_to_float(b, 8); + + dst[3] = 1.0f; +} + +static inline void +unpack_float_a8r8g8b8_unorm(const void *void_src, GLfloat dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t a = UNPACK(*src, 0, 8); + uint8_t r = UNPACK(*src, 8, 8); + uint8_t g = UNPACK(*src, 16, 8); + uint8_t b = UNPACK(*src, 24, 8); + + + + dst[0] = _mesa_unorm_to_float(r, 8); + + + dst[1] = _mesa_unorm_to_float(g, 8); + + + dst[2] = _mesa_unorm_to_float(b, 8); + + + dst[3] = _mesa_unorm_to_float(a, 8); +} + +static inline void +unpack_float_x8r8g8b8_unorm(const void *void_src, GLfloat dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t r = UNPACK(*src, 8, 8); + uint8_t g = UNPACK(*src, 16, 8); + uint8_t b = UNPACK(*src, 24, 8); + + + + dst[0] = _mesa_unorm_to_float(r, 8); + + + dst[1] = _mesa_unorm_to_float(g, 8); + + + dst[2] = _mesa_unorm_to_float(b, 8); + + dst[3] = 1.0f; +} + +static inline void +unpack_float_l16a16_unorm(const void *void_src, GLfloat dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint16_t l = UNPACK(*src, 0, 16); + uint16_t a = UNPACK(*src, 16, 16); + + + + dst[0] = _mesa_unorm_to_float(l, 16); + + + dst[1] = _mesa_unorm_to_float(l, 16); + + + dst[2] = _mesa_unorm_to_float(l, 16); + + + dst[3] = _mesa_unorm_to_float(a, 16); +} + +static inline void +unpack_float_a16l16_unorm(const void *void_src, GLfloat dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint16_t a = UNPACK(*src, 0, 16); + uint16_t l = UNPACK(*src, 16, 16); + + + + dst[0] = _mesa_unorm_to_float(l, 16); + + + dst[1] = _mesa_unorm_to_float(l, 16); + + + dst[2] = _mesa_unorm_to_float(l, 16); + + + dst[3] = _mesa_unorm_to_float(a, 16); +} + +static inline void +unpack_float_b5g6r5_unorm(const void *void_src, GLfloat dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t b = UNPACK(*src, 0, 5); + uint8_t g = UNPACK(*src, 5, 6); + uint8_t r = UNPACK(*src, 11, 5); + + + + dst[0] = _mesa_unorm_to_float(r, 5); + + + dst[1] = _mesa_unorm_to_float(g, 6); + + + dst[2] = _mesa_unorm_to_float(b, 5); + + dst[3] = 1.0f; +} + +static inline void +unpack_float_r5g6b5_unorm(const void *void_src, GLfloat dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t r = UNPACK(*src, 0, 5); + uint8_t g = UNPACK(*src, 5, 6); + uint8_t b = UNPACK(*src, 11, 5); + + + + dst[0] = _mesa_unorm_to_float(r, 5); + + + dst[1] = _mesa_unorm_to_float(g, 6); + + + dst[2] = _mesa_unorm_to_float(b, 5); + + dst[3] = 1.0f; +} + +static inline void +unpack_float_b4g4r4a4_unorm(const void *void_src, GLfloat dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t b = UNPACK(*src, 0, 4); + uint8_t g = UNPACK(*src, 4, 4); + uint8_t r = UNPACK(*src, 8, 4); + uint8_t a = UNPACK(*src, 12, 4); + + + + dst[0] = _mesa_unorm_to_float(r, 4); + + + dst[1] = _mesa_unorm_to_float(g, 4); + + + dst[2] = _mesa_unorm_to_float(b, 4); + + + dst[3] = _mesa_unorm_to_float(a, 4); +} + +static inline void +unpack_float_b4g4r4x4_unorm(const void *void_src, GLfloat dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t b = UNPACK(*src, 0, 4); + uint8_t g = UNPACK(*src, 4, 4); + uint8_t r = UNPACK(*src, 8, 4); + + + + dst[0] = _mesa_unorm_to_float(r, 4); + + + dst[1] = _mesa_unorm_to_float(g, 4); + + + dst[2] = _mesa_unorm_to_float(b, 4); + + dst[3] = 1.0f; +} + +static inline void +unpack_float_a4r4g4b4_unorm(const void *void_src, GLfloat dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t a = UNPACK(*src, 0, 4); + uint8_t r = UNPACK(*src, 4, 4); + uint8_t g = UNPACK(*src, 8, 4); + uint8_t b = UNPACK(*src, 12, 4); + + + + dst[0] = _mesa_unorm_to_float(r, 4); + + + dst[1] = _mesa_unorm_to_float(g, 4); + + + dst[2] = _mesa_unorm_to_float(b, 4); + + + dst[3] = _mesa_unorm_to_float(a, 4); +} + +static inline void +unpack_float_a1b5g5r5_unorm(const void *void_src, GLfloat dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t a = UNPACK(*src, 0, 1); + uint8_t b = UNPACK(*src, 1, 5); + uint8_t g = UNPACK(*src, 6, 5); + uint8_t r = UNPACK(*src, 11, 5); + + + + dst[0] = _mesa_unorm_to_float(r, 5); + + + dst[1] = _mesa_unorm_to_float(g, 5); + + + dst[2] = _mesa_unorm_to_float(b, 5); + + + dst[3] = _mesa_unorm_to_float(a, 1); +} + +static inline void +unpack_float_x1b5g5r5_unorm(const void *void_src, GLfloat dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t b = UNPACK(*src, 1, 5); + uint8_t g = UNPACK(*src, 6, 5); + uint8_t r = UNPACK(*src, 11, 5); + + + + dst[0] = _mesa_unorm_to_float(r, 5); + + + dst[1] = _mesa_unorm_to_float(g, 5); + + + dst[2] = _mesa_unorm_to_float(b, 5); + + dst[3] = 1.0f; +} + +static inline void +unpack_float_b5g5r5a1_unorm(const void *void_src, GLfloat dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t b = UNPACK(*src, 0, 5); + uint8_t g = UNPACK(*src, 5, 5); + uint8_t r = UNPACK(*src, 10, 5); + uint8_t a = UNPACK(*src, 15, 1); + + + + dst[0] = _mesa_unorm_to_float(r, 5); + + + dst[1] = _mesa_unorm_to_float(g, 5); + + + dst[2] = _mesa_unorm_to_float(b, 5); + + + dst[3] = _mesa_unorm_to_float(a, 1); +} + +static inline void +unpack_float_b5g5r5x1_unorm(const void *void_src, GLfloat dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t b = UNPACK(*src, 0, 5); + uint8_t g = UNPACK(*src, 5, 5); + uint8_t r = UNPACK(*src, 10, 5); + + + + dst[0] = _mesa_unorm_to_float(r, 5); + + + dst[1] = _mesa_unorm_to_float(g, 5); + + + dst[2] = _mesa_unorm_to_float(b, 5); + + dst[3] = 1.0f; +} + +static inline void +unpack_float_a1r5g5b5_unorm(const void *void_src, GLfloat dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t a = UNPACK(*src, 0, 1); + uint8_t r = UNPACK(*src, 1, 5); + uint8_t g = UNPACK(*src, 6, 5); + uint8_t b = UNPACK(*src, 11, 5); + + + + dst[0] = _mesa_unorm_to_float(r, 5); + + + dst[1] = _mesa_unorm_to_float(g, 5); + + + dst[2] = _mesa_unorm_to_float(b, 5); + + + dst[3] = _mesa_unorm_to_float(a, 1); +} + +static inline void +unpack_float_l8a8_unorm(const void *void_src, GLfloat dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t l = UNPACK(*src, 0, 8); + uint8_t a = UNPACK(*src, 8, 8); + + + + dst[0] = _mesa_unorm_to_float(l, 8); + + + dst[1] = _mesa_unorm_to_float(l, 8); + + + dst[2] = _mesa_unorm_to_float(l, 8); + + + dst[3] = _mesa_unorm_to_float(a, 8); +} + +static inline void +unpack_float_a8l8_unorm(const void *void_src, GLfloat dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t a = UNPACK(*src, 0, 8); + uint8_t l = UNPACK(*src, 8, 8); + + + + dst[0] = _mesa_unorm_to_float(l, 8); + + + dst[1] = _mesa_unorm_to_float(l, 8); + + + dst[2] = _mesa_unorm_to_float(l, 8); + + + dst[3] = _mesa_unorm_to_float(a, 8); +} + +static inline void +unpack_float_r8g8_unorm(const void *void_src, GLfloat dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t r = UNPACK(*src, 0, 8); + uint8_t g = UNPACK(*src, 8, 8); + + + + dst[0] = _mesa_unorm_to_float(r, 8); + + + dst[1] = _mesa_unorm_to_float(g, 8); + + dst[2] = 0.0f; + + dst[3] = 1.0f; +} + +static inline void +unpack_float_g8r8_unorm(const void *void_src, GLfloat dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t g = UNPACK(*src, 0, 8); + uint8_t r = UNPACK(*src, 8, 8); + + + + dst[0] = _mesa_unorm_to_float(r, 8); + + + dst[1] = _mesa_unorm_to_float(g, 8); + + dst[2] = 0.0f; + + dst[3] = 1.0f; +} + +static inline void +unpack_float_l4a4_unorm(const void *void_src, GLfloat dst[4]) +{ + uint8_t *src = (uint8_t *)void_src; + uint8_t l = UNPACK(*src, 0, 4); + uint8_t a = UNPACK(*src, 4, 4); + + + + dst[0] = _mesa_unorm_to_float(l, 4); + + + dst[1] = _mesa_unorm_to_float(l, 4); + + + dst[2] = _mesa_unorm_to_float(l, 4); + + + dst[3] = _mesa_unorm_to_float(a, 4); +} + +static inline void +unpack_float_b2g3r3_unorm(const void *void_src, GLfloat dst[4]) +{ + uint8_t *src = (uint8_t *)void_src; + uint8_t b = UNPACK(*src, 0, 2); + uint8_t g = UNPACK(*src, 2, 3); + uint8_t r = UNPACK(*src, 5, 3); + + + + dst[0] = _mesa_unorm_to_float(r, 3); + + + dst[1] = _mesa_unorm_to_float(g, 3); + + + dst[2] = _mesa_unorm_to_float(b, 2); + + dst[3] = 1.0f; +} + +static inline void +unpack_float_r16g16_unorm(const void *void_src, GLfloat dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint16_t r = UNPACK(*src, 0, 16); + uint16_t g = UNPACK(*src, 16, 16); + + + + dst[0] = _mesa_unorm_to_float(r, 16); + + + dst[1] = _mesa_unorm_to_float(g, 16); + + dst[2] = 0.0f; + + dst[3] = 1.0f; +} + +static inline void +unpack_float_g16r16_unorm(const void *void_src, GLfloat dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint16_t g = UNPACK(*src, 0, 16); + uint16_t r = UNPACK(*src, 16, 16); + + + + dst[0] = _mesa_unorm_to_float(r, 16); + + + dst[1] = _mesa_unorm_to_float(g, 16); + + dst[2] = 0.0f; + + dst[3] = 1.0f; +} + +static inline void +unpack_float_b10g10r10a2_unorm(const void *void_src, GLfloat dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint16_t b = UNPACK(*src, 0, 10); + uint16_t g = UNPACK(*src, 10, 10); + uint16_t r = UNPACK(*src, 20, 10); + uint8_t a = UNPACK(*src, 30, 2); + + + + dst[0] = _mesa_unorm_to_float(r, 10); + + + dst[1] = _mesa_unorm_to_float(g, 10); + + + dst[2] = _mesa_unorm_to_float(b, 10); + + + dst[3] = _mesa_unorm_to_float(a, 2); +} + +static inline void +unpack_float_b10g10r10x2_unorm(const void *void_src, GLfloat dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint16_t b = UNPACK(*src, 0, 10); + uint16_t g = UNPACK(*src, 10, 10); + uint16_t r = UNPACK(*src, 20, 10); + + + + dst[0] = _mesa_unorm_to_float(r, 10); + + + dst[1] = _mesa_unorm_to_float(g, 10); + + + dst[2] = _mesa_unorm_to_float(b, 10); + + dst[3] = 1.0f; +} + +static inline void +unpack_float_r10g10b10a2_unorm(const void *void_src, GLfloat dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint16_t r = UNPACK(*src, 0, 10); + uint16_t g = UNPACK(*src, 10, 10); + uint16_t b = UNPACK(*src, 20, 10); + uint8_t a = UNPACK(*src, 30, 2); + + + + dst[0] = _mesa_unorm_to_float(r, 10); + + + dst[1] = _mesa_unorm_to_float(g, 10); + + + dst[2] = _mesa_unorm_to_float(b, 10); + + + dst[3] = _mesa_unorm_to_float(a, 2); +} + +static inline void +unpack_float_r10g10b10x2_unorm(const void *void_src, GLfloat dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint16_t r = UNPACK(*src, 0, 10); + uint16_t g = UNPACK(*src, 10, 10); + uint16_t b = UNPACK(*src, 20, 10); + + + + dst[0] = _mesa_unorm_to_float(r, 10); + + + dst[1] = _mesa_unorm_to_float(g, 10); + + + dst[2] = _mesa_unorm_to_float(b, 10); + + dst[3] = 1.0f; +} + +static inline void +unpack_float_r3g3b2_unorm(const void *void_src, GLfloat dst[4]) +{ + uint8_t *src = (uint8_t *)void_src; + uint8_t r = UNPACK(*src, 0, 3); + uint8_t g = UNPACK(*src, 3, 3); + uint8_t b = UNPACK(*src, 6, 2); + + + + dst[0] = _mesa_unorm_to_float(r, 3); + + + dst[1] = _mesa_unorm_to_float(g, 3); + + + dst[2] = _mesa_unorm_to_float(b, 2); + + dst[3] = 1.0f; +} + +static inline void +unpack_float_a4b4g4r4_unorm(const void *void_src, GLfloat dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t a = UNPACK(*src, 0, 4); + uint8_t b = UNPACK(*src, 4, 4); + uint8_t g = UNPACK(*src, 8, 4); + uint8_t r = UNPACK(*src, 12, 4); + + + + dst[0] = _mesa_unorm_to_float(r, 4); + + + dst[1] = _mesa_unorm_to_float(g, 4); + + + dst[2] = _mesa_unorm_to_float(b, 4); + + + dst[3] = _mesa_unorm_to_float(a, 4); +} + +static inline void +unpack_float_r4g4b4a4_unorm(const void *void_src, GLfloat dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t r = UNPACK(*src, 0, 4); + uint8_t g = UNPACK(*src, 4, 4); + uint8_t b = UNPACK(*src, 8, 4); + uint8_t a = UNPACK(*src, 12, 4); + + + + dst[0] = _mesa_unorm_to_float(r, 4); + + + dst[1] = _mesa_unorm_to_float(g, 4); + + + dst[2] = _mesa_unorm_to_float(b, 4); + + + dst[3] = _mesa_unorm_to_float(a, 4); +} + +static inline void +unpack_float_r5g5b5a1_unorm(const void *void_src, GLfloat dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t r = UNPACK(*src, 0, 5); + uint8_t g = UNPACK(*src, 5, 5); + uint8_t b = UNPACK(*src, 10, 5); + uint8_t a = UNPACK(*src, 15, 1); + + + + dst[0] = _mesa_unorm_to_float(r, 5); + + + dst[1] = _mesa_unorm_to_float(g, 5); + + + dst[2] = _mesa_unorm_to_float(b, 5); + + + dst[3] = _mesa_unorm_to_float(a, 1); +} + +static inline void +unpack_float_a2b10g10r10_unorm(const void *void_src, GLfloat dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t a = UNPACK(*src, 0, 2); + uint16_t b = UNPACK(*src, 2, 10); + uint16_t g = UNPACK(*src, 12, 10); + uint16_t r = UNPACK(*src, 22, 10); + + + + dst[0] = _mesa_unorm_to_float(r, 10); + + + dst[1] = _mesa_unorm_to_float(g, 10); + + + dst[2] = _mesa_unorm_to_float(b, 10); + + + dst[3] = _mesa_unorm_to_float(a, 2); +} + +static inline void +unpack_float_a2r10g10b10_unorm(const void *void_src, GLfloat dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t a = UNPACK(*src, 0, 2); + uint16_t r = UNPACK(*src, 2, 10); + uint16_t g = UNPACK(*src, 12, 10); + uint16_t b = UNPACK(*src, 22, 10); + + + + dst[0] = _mesa_unorm_to_float(r, 10); + + + dst[1] = _mesa_unorm_to_float(g, 10); + + + dst[2] = _mesa_unorm_to_float(b, 10); + + + dst[3] = _mesa_unorm_to_float(a, 2); +} + +static inline void +unpack_float_a_unorm8(const void *void_src, GLfloat dst[4]) +{ + uint8_t *src = (uint8_t *)void_src; + uint8_t a = src[0]; + + + dst[0] = 0.0f; + + dst[1] = 0.0f; + + dst[2] = 0.0f; + + + dst[3] = _mesa_unorm_to_float(a, 8); +} + +static inline void +unpack_float_a_unorm16(const void *void_src, GLfloat dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint16_t a = src[0]; + + + dst[0] = 0.0f; + + dst[1] = 0.0f; + + dst[2] = 0.0f; + + + dst[3] = _mesa_unorm_to_float(a, 16); +} + +static inline void +unpack_float_l_unorm8(const void *void_src, GLfloat dst[4]) +{ + uint8_t *src = (uint8_t *)void_src; + uint8_t l = src[0]; + + + + dst[0] = _mesa_unorm_to_float(l, 8); + + + dst[1] = _mesa_unorm_to_float(l, 8); + + + dst[2] = _mesa_unorm_to_float(l, 8); + + dst[3] = 1.0f; +} + +static inline void +unpack_float_l_unorm16(const void *void_src, GLfloat dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint16_t l = src[0]; + + + + dst[0] = _mesa_unorm_to_float(l, 16); + + + dst[1] = _mesa_unorm_to_float(l, 16); + + + dst[2] = _mesa_unorm_to_float(l, 16); + + dst[3] = 1.0f; +} + +static inline void +unpack_float_i_unorm8(const void *void_src, GLfloat dst[4]) +{ + uint8_t *src = (uint8_t *)void_src; + uint8_t i = src[0]; + + + + dst[0] = _mesa_unorm_to_float(i, 8); + + + dst[1] = _mesa_unorm_to_float(i, 8); + + + dst[2] = _mesa_unorm_to_float(i, 8); + + + dst[3] = _mesa_unorm_to_float(i, 8); +} + +static inline void +unpack_float_i_unorm16(const void *void_src, GLfloat dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint16_t i = src[0]; + + + + dst[0] = _mesa_unorm_to_float(i, 16); + + + dst[1] = _mesa_unorm_to_float(i, 16); + + + dst[2] = _mesa_unorm_to_float(i, 16); + + + dst[3] = _mesa_unorm_to_float(i, 16); +} + +static inline void +unpack_float_r_unorm8(const void *void_src, GLfloat dst[4]) +{ + uint8_t *src = (uint8_t *)void_src; + uint8_t r = src[0]; + + + + dst[0] = _mesa_unorm_to_float(r, 8); + + dst[1] = 0.0f; + + dst[2] = 0.0f; + + dst[3] = 1.0f; +} + +static inline void +unpack_float_r_unorm16(const void *void_src, GLfloat dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint16_t r = src[0]; + + + + dst[0] = _mesa_unorm_to_float(r, 16); + + dst[1] = 0.0f; + + dst[2] = 0.0f; + + dst[3] = 1.0f; +} + +static inline void +unpack_float_bgr_unorm8(const void *void_src, GLfloat dst[4]) +{ + uint8_t *src = (uint8_t *)void_src; + uint8_t b = src[0]; + uint8_t g = src[1]; + uint8_t r = src[2]; + + + + dst[0] = _mesa_unorm_to_float(r, 8); + + + dst[1] = _mesa_unorm_to_float(g, 8); + + + dst[2] = _mesa_unorm_to_float(b, 8); + + dst[3] = 1.0f; +} + +static inline void +unpack_float_rgb_unorm8(const void *void_src, GLfloat dst[4]) +{ + uint8_t *src = (uint8_t *)void_src; + uint8_t r = src[0]; + uint8_t g = src[1]; + uint8_t b = src[2]; + + + + dst[0] = _mesa_unorm_to_float(r, 8); + + + dst[1] = _mesa_unorm_to_float(g, 8); + + + dst[2] = _mesa_unorm_to_float(b, 8); + + dst[3] = 1.0f; +} + +static inline void +unpack_float_rgba_unorm16(const void *void_src, GLfloat dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint16_t r = src[0]; + uint16_t g = src[1]; + uint16_t b = src[2]; + uint16_t a = src[3]; + + + + dst[0] = _mesa_unorm_to_float(r, 16); + + + dst[1] = _mesa_unorm_to_float(g, 16); + + + dst[2] = _mesa_unorm_to_float(b, 16); + + + dst[3] = _mesa_unorm_to_float(a, 16); +} + +static inline void +unpack_float_rgbx_unorm16(const void *void_src, GLfloat dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint16_t r = src[0]; + uint16_t g = src[1]; + uint16_t b = src[2]; + + + + dst[0] = _mesa_unorm_to_float(r, 16); + + + dst[1] = _mesa_unorm_to_float(g, 16); + + + dst[2] = _mesa_unorm_to_float(b, 16); + + dst[3] = 1.0f; +} + +static inline void +unpack_float_a8b8g8r8_snorm(const void *void_src, GLfloat dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + int8_t a = UNPACK(*src, 0, 8); + int8_t b = UNPACK(*src, 8, 8); + int8_t g = UNPACK(*src, 16, 8); + int8_t r = UNPACK(*src, 24, 8); + + + + dst[0] = _mesa_snorm_to_float(r, 8); + + + dst[1] = _mesa_snorm_to_float(g, 8); + + + dst[2] = _mesa_snorm_to_float(b, 8); + + + dst[3] = _mesa_snorm_to_float(a, 8); +} + +static inline void +unpack_float_x8b8g8r8_snorm(const void *void_src, GLfloat dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + int8_t b = UNPACK(*src, 8, 8); + int8_t g = UNPACK(*src, 16, 8); + int8_t r = UNPACK(*src, 24, 8); + + + + dst[0] = _mesa_snorm_to_float(r, 8); + + + dst[1] = _mesa_snorm_to_float(g, 8); + + + dst[2] = _mesa_snorm_to_float(b, 8); + + dst[3] = 1.0f; +} + +static inline void +unpack_float_r8g8b8a8_snorm(const void *void_src, GLfloat dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + int8_t r = UNPACK(*src, 0, 8); + int8_t g = UNPACK(*src, 8, 8); + int8_t b = UNPACK(*src, 16, 8); + int8_t a = UNPACK(*src, 24, 8); + + + + dst[0] = _mesa_snorm_to_float(r, 8); + + + dst[1] = _mesa_snorm_to_float(g, 8); + + + dst[2] = _mesa_snorm_to_float(b, 8); + + + dst[3] = _mesa_snorm_to_float(a, 8); +} + +static inline void +unpack_float_r8g8b8x8_snorm(const void *void_src, GLfloat dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + int8_t r = UNPACK(*src, 0, 8); + int8_t g = UNPACK(*src, 8, 8); + int8_t b = UNPACK(*src, 16, 8); + + + + dst[0] = _mesa_snorm_to_float(r, 8); + + + dst[1] = _mesa_snorm_to_float(g, 8); + + + dst[2] = _mesa_snorm_to_float(b, 8); + + dst[3] = 1.0f; +} + +static inline void +unpack_float_r16g16_snorm(const void *void_src, GLfloat dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + int16_t r = UNPACK(*src, 0, 16); + int16_t g = UNPACK(*src, 16, 16); + + + + dst[0] = _mesa_snorm_to_float(r, 16); + + + dst[1] = _mesa_snorm_to_float(g, 16); + + dst[2] = 0.0f; + + dst[3] = 1.0f; +} + +static inline void +unpack_float_g16r16_snorm(const void *void_src, GLfloat dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + int16_t g = UNPACK(*src, 0, 16); + int16_t r = UNPACK(*src, 16, 16); + + + + dst[0] = _mesa_snorm_to_float(r, 16); + + + dst[1] = _mesa_snorm_to_float(g, 16); + + dst[2] = 0.0f; + + dst[3] = 1.0f; +} + +static inline void +unpack_float_r8g8_snorm(const void *void_src, GLfloat dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + int8_t r = UNPACK(*src, 0, 8); + int8_t g = UNPACK(*src, 8, 8); + + + + dst[0] = _mesa_snorm_to_float(r, 8); + + + dst[1] = _mesa_snorm_to_float(g, 8); + + dst[2] = 0.0f; + + dst[3] = 1.0f; +} + +static inline void +unpack_float_g8r8_snorm(const void *void_src, GLfloat dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + int8_t g = UNPACK(*src, 0, 8); + int8_t r = UNPACK(*src, 8, 8); + + + + dst[0] = _mesa_snorm_to_float(r, 8); + + + dst[1] = _mesa_snorm_to_float(g, 8); + + dst[2] = 0.0f; + + dst[3] = 1.0f; +} + +static inline void +unpack_float_l8a8_snorm(const void *void_src, GLfloat dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + int8_t l = UNPACK(*src, 0, 8); + int8_t a = UNPACK(*src, 8, 8); + + + + dst[0] = _mesa_snorm_to_float(l, 8); + + + dst[1] = _mesa_snorm_to_float(l, 8); + + + dst[2] = _mesa_snorm_to_float(l, 8); + + + dst[3] = _mesa_snorm_to_float(a, 8); +} + +static inline void +unpack_float_a8l8_snorm(const void *void_src, GLfloat dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + int8_t a = UNPACK(*src, 0, 8); + int8_t l = UNPACK(*src, 8, 8); + + + + dst[0] = _mesa_snorm_to_float(l, 8); + + + dst[1] = _mesa_snorm_to_float(l, 8); + + + dst[2] = _mesa_snorm_to_float(l, 8); + + + dst[3] = _mesa_snorm_to_float(a, 8); +} + +static inline void +unpack_float_a_snorm8(const void *void_src, GLfloat dst[4]) +{ + int8_t *src = (int8_t *)void_src; + int8_t a = src[0]; + + + dst[0] = 0.0f; + + dst[1] = 0.0f; + + dst[2] = 0.0f; + + + dst[3] = _mesa_snorm_to_float(a, 8); +} + +static inline void +unpack_float_a_snorm16(const void *void_src, GLfloat dst[4]) +{ + int16_t *src = (int16_t *)void_src; + int16_t a = src[0]; + + + dst[0] = 0.0f; + + dst[1] = 0.0f; + + dst[2] = 0.0f; + + + dst[3] = _mesa_snorm_to_float(a, 16); +} + +static inline void +unpack_float_l_snorm8(const void *void_src, GLfloat dst[4]) +{ + int8_t *src = (int8_t *)void_src; + int8_t l = src[0]; + + + + dst[0] = _mesa_snorm_to_float(l, 8); + + + dst[1] = _mesa_snorm_to_float(l, 8); + + + dst[2] = _mesa_snorm_to_float(l, 8); + + dst[3] = 1.0f; +} + +static inline void +unpack_float_l_snorm16(const void *void_src, GLfloat dst[4]) +{ + int16_t *src = (int16_t *)void_src; + int16_t l = src[0]; + + + + dst[0] = _mesa_snorm_to_float(l, 16); + + + dst[1] = _mesa_snorm_to_float(l, 16); + + + dst[2] = _mesa_snorm_to_float(l, 16); + + dst[3] = 1.0f; +} + +static inline void +unpack_float_i_snorm8(const void *void_src, GLfloat dst[4]) +{ + int8_t *src = (int8_t *)void_src; + int8_t i = src[0]; + + + + dst[0] = _mesa_snorm_to_float(i, 8); + + + dst[1] = _mesa_snorm_to_float(i, 8); + + + dst[2] = _mesa_snorm_to_float(i, 8); + + + dst[3] = _mesa_snorm_to_float(i, 8); +} + +static inline void +unpack_float_i_snorm16(const void *void_src, GLfloat dst[4]) +{ + int16_t *src = (int16_t *)void_src; + int16_t i = src[0]; + + + + dst[0] = _mesa_snorm_to_float(i, 16); + + + dst[1] = _mesa_snorm_to_float(i, 16); + + + dst[2] = _mesa_snorm_to_float(i, 16); + + + dst[3] = _mesa_snorm_to_float(i, 16); +} + +static inline void +unpack_float_r_snorm8(const void *void_src, GLfloat dst[4]) +{ + int8_t *src = (int8_t *)void_src; + int8_t r = src[0]; + + + + dst[0] = _mesa_snorm_to_float(r, 8); + + dst[1] = 0.0f; + + dst[2] = 0.0f; + + dst[3] = 1.0f; +} + +static inline void +unpack_float_r_snorm16(const void *void_src, GLfloat dst[4]) +{ + int16_t *src = (int16_t *)void_src; + int16_t r = src[0]; + + + + dst[0] = _mesa_snorm_to_float(r, 16); + + dst[1] = 0.0f; + + dst[2] = 0.0f; + + dst[3] = 1.0f; +} + +static inline void +unpack_float_la_snorm16(const void *void_src, GLfloat dst[4]) +{ + int16_t *src = (int16_t *)void_src; + int16_t l = src[0]; + int16_t a = src[1]; + + + + dst[0] = _mesa_snorm_to_float(l, 16); + + + dst[1] = _mesa_snorm_to_float(l, 16); + + + dst[2] = _mesa_snorm_to_float(l, 16); + + + dst[3] = _mesa_snorm_to_float(a, 16); +} + +static inline void +unpack_float_rgb_snorm16(const void *void_src, GLfloat dst[4]) +{ + int16_t *src = (int16_t *)void_src; + int16_t r = src[0]; + int16_t g = src[1]; + int16_t b = src[2]; + + + + dst[0] = _mesa_snorm_to_float(r, 16); + + + dst[1] = _mesa_snorm_to_float(g, 16); + + + dst[2] = _mesa_snorm_to_float(b, 16); + + dst[3] = 1.0f; +} + +static inline void +unpack_float_rgba_snorm16(const void *void_src, GLfloat dst[4]) +{ + int16_t *src = (int16_t *)void_src; + int16_t r = src[0]; + int16_t g = src[1]; + int16_t b = src[2]; + int16_t a = src[3]; + + + + dst[0] = _mesa_snorm_to_float(r, 16); + + + dst[1] = _mesa_snorm_to_float(g, 16); + + + dst[2] = _mesa_snorm_to_float(b, 16); + + + dst[3] = _mesa_snorm_to_float(a, 16); +} + +static inline void +unpack_float_rgbx_snorm16(const void *void_src, GLfloat dst[4]) +{ + int16_t *src = (int16_t *)void_src; + int16_t r = src[0]; + int16_t g = src[1]; + int16_t b = src[2]; + + + + dst[0] = _mesa_snorm_to_float(r, 16); + + + dst[1] = _mesa_snorm_to_float(g, 16); + + + dst[2] = _mesa_snorm_to_float(b, 16); + + dst[3] = 1.0f; +} + +static inline void +unpack_float_a8b8g8r8_srgb(const void *void_src, GLfloat dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t a = UNPACK(*src, 0, 8); + uint8_t b = UNPACK(*src, 8, 8); + uint8_t g = UNPACK(*src, 16, 8); + uint8_t r = UNPACK(*src, 24, 8); + + + + + dst[0] = util_format_srgb_8unorm_to_linear_float(r); + + + + dst[1] = util_format_srgb_8unorm_to_linear_float(g); + + + + dst[2] = util_format_srgb_8unorm_to_linear_float(b); + + + dst[3] = _mesa_unorm_to_float(a, 8); +} + +static inline void +unpack_float_b8g8r8a8_srgb(const void *void_src, GLfloat dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t b = UNPACK(*src, 0, 8); + uint8_t g = UNPACK(*src, 8, 8); + uint8_t r = UNPACK(*src, 16, 8); + uint8_t a = UNPACK(*src, 24, 8); + + + + + dst[0] = util_format_srgb_8unorm_to_linear_float(r); + + + + dst[1] = util_format_srgb_8unorm_to_linear_float(g); + + + + dst[2] = util_format_srgb_8unorm_to_linear_float(b); + + + dst[3] = _mesa_unorm_to_float(a, 8); +} + +static inline void +unpack_float_a8r8g8b8_srgb(const void *void_src, GLfloat dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t a = UNPACK(*src, 0, 8); + uint8_t r = UNPACK(*src, 8, 8); + uint8_t g = UNPACK(*src, 16, 8); + uint8_t b = UNPACK(*src, 24, 8); + + + + + dst[0] = util_format_srgb_8unorm_to_linear_float(r); + + + + dst[1] = util_format_srgb_8unorm_to_linear_float(g); + + + + dst[2] = util_format_srgb_8unorm_to_linear_float(b); + + + dst[3] = _mesa_unorm_to_float(a, 8); +} + +static inline void +unpack_float_b8g8r8x8_srgb(const void *void_src, GLfloat dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t b = UNPACK(*src, 0, 8); + uint8_t g = UNPACK(*src, 8, 8); + uint8_t r = UNPACK(*src, 16, 8); + + + + + dst[0] = util_format_srgb_8unorm_to_linear_float(r); + + + + dst[1] = util_format_srgb_8unorm_to_linear_float(g); + + + + dst[2] = util_format_srgb_8unorm_to_linear_float(b); + + dst[3] = 1.0f; +} + +static inline void +unpack_float_x8r8g8b8_srgb(const void *void_src, GLfloat dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t r = UNPACK(*src, 8, 8); + uint8_t g = UNPACK(*src, 16, 8); + uint8_t b = UNPACK(*src, 24, 8); + + + + + dst[0] = util_format_srgb_8unorm_to_linear_float(r); + + + + dst[1] = util_format_srgb_8unorm_to_linear_float(g); + + + + dst[2] = util_format_srgb_8unorm_to_linear_float(b); + + dst[3] = 1.0f; +} + +static inline void +unpack_float_r8g8b8a8_srgb(const void *void_src, GLfloat dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t r = UNPACK(*src, 0, 8); + uint8_t g = UNPACK(*src, 8, 8); + uint8_t b = UNPACK(*src, 16, 8); + uint8_t a = UNPACK(*src, 24, 8); + + + + + dst[0] = util_format_srgb_8unorm_to_linear_float(r); + + + + dst[1] = util_format_srgb_8unorm_to_linear_float(g); + + + + dst[2] = util_format_srgb_8unorm_to_linear_float(b); + + + dst[3] = _mesa_unorm_to_float(a, 8); +} + +static inline void +unpack_float_r8g8b8x8_srgb(const void *void_src, GLfloat dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t r = UNPACK(*src, 0, 8); + uint8_t g = UNPACK(*src, 8, 8); + uint8_t b = UNPACK(*src, 16, 8); + + + + + dst[0] = util_format_srgb_8unorm_to_linear_float(r); + + + + dst[1] = util_format_srgb_8unorm_to_linear_float(g); + + + + dst[2] = util_format_srgb_8unorm_to_linear_float(b); + + dst[3] = 1.0f; +} + +static inline void +unpack_float_x8b8g8r8_srgb(const void *void_src, GLfloat dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t b = UNPACK(*src, 8, 8); + uint8_t g = UNPACK(*src, 16, 8); + uint8_t r = UNPACK(*src, 24, 8); + + + + + dst[0] = util_format_srgb_8unorm_to_linear_float(r); + + + + dst[1] = util_format_srgb_8unorm_to_linear_float(g); + + + + dst[2] = util_format_srgb_8unorm_to_linear_float(b); + + dst[3] = 1.0f; +} + +static inline void +unpack_float_l8a8_srgb(const void *void_src, GLfloat dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t l = UNPACK(*src, 0, 8); + uint8_t a = UNPACK(*src, 8, 8); + + + + dst[0] = _mesa_unorm_to_float(l, 8); + + + dst[1] = _mesa_unorm_to_float(l, 8); + + + dst[2] = _mesa_unorm_to_float(l, 8); + + + dst[3] = _mesa_unorm_to_float(a, 8); +} + +static inline void +unpack_float_a8l8_srgb(const void *void_src, GLfloat dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t a = UNPACK(*src, 0, 8); + uint8_t l = UNPACK(*src, 8, 8); + + + + dst[0] = _mesa_unorm_to_float(l, 8); + + + dst[1] = _mesa_unorm_to_float(l, 8); + + + dst[2] = _mesa_unorm_to_float(l, 8); + + + dst[3] = _mesa_unorm_to_float(a, 8); +} + +static inline void +unpack_float_r_srgb8(const void *void_src, GLfloat dst[4]) +{ + uint8_t *src = (uint8_t *)void_src; + uint8_t r = src[0]; + + + + + dst[0] = util_format_srgb_8unorm_to_linear_float(r); + + dst[1] = 0.0f; + + dst[2] = 0.0f; + + dst[3] = 1.0f; +} + +static inline void +unpack_float_l_srgb8(const void *void_src, GLfloat dst[4]) +{ + uint8_t *src = (uint8_t *)void_src; + uint8_t l = src[0]; + + + + dst[0] = _mesa_unorm_to_float(l, 8); + + + dst[1] = _mesa_unorm_to_float(l, 8); + + + dst[2] = _mesa_unorm_to_float(l, 8); + + dst[3] = 1.0f; +} + +static inline void +unpack_float_bgr_srgb8(const void *void_src, GLfloat dst[4]) +{ + uint8_t *src = (uint8_t *)void_src; + uint8_t b = src[0]; + uint8_t g = src[1]; + uint8_t r = src[2]; + + + + + dst[0] = util_format_srgb_8unorm_to_linear_float(r); + + + + dst[1] = util_format_srgb_8unorm_to_linear_float(g); + + + + dst[2] = util_format_srgb_8unorm_to_linear_float(b); + + dst[3] = 1.0f; +} + +static inline void +unpack_float_a_float16(const void *void_src, GLfloat dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint16_t a = src[0]; + + + dst[0] = 0.0f; + + dst[1] = 0.0f; + + dst[2] = 0.0f; + + + dst[3] = _mesa_half_to_float(a); +} + +static inline void +unpack_float_a_float32(const void *void_src, GLfloat dst[4]) +{ + float *src = (float *)void_src; + float a = src[0]; + + + dst[0] = 0.0f; + + dst[1] = 0.0f; + + dst[2] = 0.0f; + + + dst[3] = a; +} + +static inline void +unpack_float_l_float16(const void *void_src, GLfloat dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint16_t l = src[0]; + + + + dst[0] = _mesa_half_to_float(l); + + + dst[1] = _mesa_half_to_float(l); + + + dst[2] = _mesa_half_to_float(l); + + dst[3] = 1.0f; +} + +static inline void +unpack_float_l_float32(const void *void_src, GLfloat dst[4]) +{ + float *src = (float *)void_src; + float l = src[0]; + + + + dst[0] = l; + + + dst[1] = l; + + + dst[2] = l; + + dst[3] = 1.0f; +} + +static inline void +unpack_float_la_float16(const void *void_src, GLfloat dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint16_t l = src[0]; + uint16_t a = src[1]; + + + + dst[0] = _mesa_half_to_float(l); + + + dst[1] = _mesa_half_to_float(l); + + + dst[2] = _mesa_half_to_float(l); + + + dst[3] = _mesa_half_to_float(a); +} + +static inline void +unpack_float_la_float32(const void *void_src, GLfloat dst[4]) +{ + float *src = (float *)void_src; + float l = src[0]; + float a = src[1]; + + + + dst[0] = l; + + + dst[1] = l; + + + dst[2] = l; + + + dst[3] = a; +} + +static inline void +unpack_float_i_float16(const void *void_src, GLfloat dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint16_t i = src[0]; + + + + dst[0] = _mesa_half_to_float(i); + + + dst[1] = _mesa_half_to_float(i); + + + dst[2] = _mesa_half_to_float(i); + + + dst[3] = _mesa_half_to_float(i); +} + +static inline void +unpack_float_i_float32(const void *void_src, GLfloat dst[4]) +{ + float *src = (float *)void_src; + float i = src[0]; + + + + dst[0] = i; + + + dst[1] = i; + + + dst[2] = i; + + + dst[3] = i; +} + +static inline void +unpack_float_r_float16(const void *void_src, GLfloat dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint16_t r = src[0]; + + + + dst[0] = _mesa_half_to_float(r); + + dst[1] = 0.0f; + + dst[2] = 0.0f; + + dst[3] = 1.0f; +} + +static inline void +unpack_float_r_float32(const void *void_src, GLfloat dst[4]) +{ + float *src = (float *)void_src; + float r = src[0]; + + + + dst[0] = r; + + dst[1] = 0.0f; + + dst[2] = 0.0f; + + dst[3] = 1.0f; +} + +static inline void +unpack_float_rg_float16(const void *void_src, GLfloat dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint16_t r = src[0]; + uint16_t g = src[1]; + + + + dst[0] = _mesa_half_to_float(r); + + + dst[1] = _mesa_half_to_float(g); + + dst[2] = 0.0f; + + dst[3] = 1.0f; +} + +static inline void +unpack_float_rg_float32(const void *void_src, GLfloat dst[4]) +{ + float *src = (float *)void_src; + float r = src[0]; + float g = src[1]; + + + + dst[0] = r; + + + dst[1] = g; + + dst[2] = 0.0f; + + dst[3] = 1.0f; +} + +static inline void +unpack_float_rgb_float16(const void *void_src, GLfloat dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint16_t r = src[0]; + uint16_t g = src[1]; + uint16_t b = src[2]; + + + + dst[0] = _mesa_half_to_float(r); + + + dst[1] = _mesa_half_to_float(g); + + + dst[2] = _mesa_half_to_float(b); + + dst[3] = 1.0f; +} + +static inline void +unpack_float_rgb_float32(const void *void_src, GLfloat dst[4]) +{ + float *src = (float *)void_src; + float r = src[0]; + float g = src[1]; + float b = src[2]; + + + + dst[0] = r; + + + dst[1] = g; + + + dst[2] = b; + + dst[3] = 1.0f; +} + +static inline void +unpack_float_rgba_float16(const void *void_src, GLfloat dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint16_t r = src[0]; + uint16_t g = src[1]; + uint16_t b = src[2]; + uint16_t a = src[3]; + + + + dst[0] = _mesa_half_to_float(r); + + + dst[1] = _mesa_half_to_float(g); + + + dst[2] = _mesa_half_to_float(b); + + + dst[3] = _mesa_half_to_float(a); +} + +static inline void +unpack_float_rgba_float32(const void *void_src, GLfloat dst[4]) +{ + float *src = (float *)void_src; + float r = src[0]; + float g = src[1]; + float b = src[2]; + float a = src[3]; + + + + dst[0] = r; + + + dst[1] = g; + + + dst[2] = b; + + + dst[3] = a; +} + +static inline void +unpack_float_rgbx_float16(const void *void_src, GLfloat dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint16_t r = src[0]; + uint16_t g = src[1]; + uint16_t b = src[2]; + + + + dst[0] = _mesa_half_to_float(r); + + + dst[1] = _mesa_half_to_float(g); + + + dst[2] = _mesa_half_to_float(b); + + dst[3] = 1.0f; +} + +static inline void +unpack_float_rgbx_float32(const void *void_src, GLfloat dst[4]) +{ + float *src = (float *)void_src; + float r = src[0]; + float g = src[1]; + float b = src[2]; + + + + dst[0] = r; + + + dst[1] = g; + + + dst[2] = b; + + dst[3] = 1.0f; +} + +static void +unpack_float_r9g9b9e5_float(const void *src, GLfloat dst[4]) +{ + rgb9e5_to_float3(*(const GLuint *)src, dst); + dst[3] = 1.0f; +} + +static void +unpack_float_r11g11b10_float(const void *src, GLfloat dst[4]) +{ + r11g11b10f_to_float3(*(const GLuint *)src, dst); + dst[3] = 1.0f; +} + +static void +unpack_float_ycbcr(const void *src, GLfloat dst[][4], GLuint n) +{ + GLuint i; + for (i = 0; i < n; i++) { + const GLushort *src0 = ((const GLushort *) src) + i * 2; /* even */ + const GLushort *src1 = src0 + 1; /* odd */ + const GLubyte y0 = (*src0 >> 8) & 0xff; /* luminance */ + const GLubyte cb = *src0 & 0xff; /* chroma U */ + const GLubyte y1 = (*src1 >> 8) & 0xff; /* luminance */ + const GLubyte cr = *src1 & 0xff; /* chroma V */ + const GLubyte y = (i & 1) ? y1 : y0; /* choose even/odd luminance */ + GLfloat r = 1.164F * (y - 16) + 1.596F * (cr - 128); + GLfloat g = 1.164F * (y - 16) - 0.813F * (cr - 128) - 0.391F * (cb - 128); + GLfloat b = 1.164F * (y - 16) + 2.018F * (cb - 128); + r *= (1.0F / 255.0F); + g *= (1.0F / 255.0F); + b *= (1.0F / 255.0F); + dst[i][0] = CLAMP(r, 0.0F, 1.0F); + dst[i][1] = CLAMP(g, 0.0F, 1.0F); + dst[i][2] = CLAMP(b, 0.0F, 1.0F); + dst[i][3] = 1.0F; + } +} + +static void +unpack_float_ycbcr_rev(const void *src, GLfloat dst[][4], GLuint n) +{ + GLuint i; + for (i = 0; i < n; i++) { + const GLushort *src0 = ((const GLushort *) src) + i * 2; /* even */ + const GLushort *src1 = src0 + 1; /* odd */ + const GLubyte y0 = *src0 & 0xff; /* luminance */ + const GLubyte cr = (*src0 >> 8) & 0xff; /* chroma V */ + const GLubyte y1 = *src1 & 0xff; /* luminance */ + const GLubyte cb = (*src1 >> 8) & 0xff; /* chroma U */ + const GLubyte y = (i & 1) ? y1 : y0; /* choose even/odd luminance */ + GLfloat r = 1.164F * (y - 16) + 1.596F * (cr - 128); + GLfloat g = 1.164F * (y - 16) - 0.813F * (cr - 128) - 0.391F * (cb - 128); + GLfloat b = 1.164F * (y - 16) + 2.018F * (cb - 128); + r *= (1.0F / 255.0F); + g *= (1.0F / 255.0F); + b *= (1.0F / 255.0F); + dst[i][0] = CLAMP(r, 0.0F, 1.0F); + dst[i][1] = CLAMP(g, 0.0F, 1.0F); + dst[i][2] = CLAMP(b, 0.0F, 1.0F); + dst[i][3] = 1.0F; + } +} + +/* ubyte packing functions */ + + +static inline void +unpack_ubyte_a8b8g8r8_unorm(const void *void_src, GLubyte dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t a = UNPACK(*src, 0, 8); + uint8_t b = UNPACK(*src, 8, 8); + uint8_t g = UNPACK(*src, 16, 8); + uint8_t r = UNPACK(*src, 24, 8); + + + + dst[0] = _mesa_unorm_to_unorm(r, 8, 8); + + + dst[1] = _mesa_unorm_to_unorm(g, 8, 8); + + + dst[2] = _mesa_unorm_to_unorm(b, 8, 8); + + + dst[3] = _mesa_unorm_to_unorm(a, 8, 8); +} + +static inline void +unpack_ubyte_x8b8g8r8_unorm(const void *void_src, GLubyte dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t b = UNPACK(*src, 8, 8); + uint8_t g = UNPACK(*src, 16, 8); + uint8_t r = UNPACK(*src, 24, 8); + + + + dst[0] = _mesa_unorm_to_unorm(r, 8, 8); + + + dst[1] = _mesa_unorm_to_unorm(g, 8, 8); + + + dst[2] = _mesa_unorm_to_unorm(b, 8, 8); + + dst[3] = 255; +} + +static inline void +unpack_ubyte_r8g8b8a8_unorm(const void *void_src, GLubyte dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t r = UNPACK(*src, 0, 8); + uint8_t g = UNPACK(*src, 8, 8); + uint8_t b = UNPACK(*src, 16, 8); + uint8_t a = UNPACK(*src, 24, 8); + + + + dst[0] = _mesa_unorm_to_unorm(r, 8, 8); + + + dst[1] = _mesa_unorm_to_unorm(g, 8, 8); + + + dst[2] = _mesa_unorm_to_unorm(b, 8, 8); + + + dst[3] = _mesa_unorm_to_unorm(a, 8, 8); +} + +static inline void +unpack_ubyte_r8g8b8x8_unorm(const void *void_src, GLubyte dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t r = UNPACK(*src, 0, 8); + uint8_t g = UNPACK(*src, 8, 8); + uint8_t b = UNPACK(*src, 16, 8); + + + + dst[0] = _mesa_unorm_to_unorm(r, 8, 8); + + + dst[1] = _mesa_unorm_to_unorm(g, 8, 8); + + + dst[2] = _mesa_unorm_to_unorm(b, 8, 8); + + dst[3] = 255; +} + +static inline void +unpack_ubyte_b8g8r8a8_unorm(const void *void_src, GLubyte dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t b = UNPACK(*src, 0, 8); + uint8_t g = UNPACK(*src, 8, 8); + uint8_t r = UNPACK(*src, 16, 8); + uint8_t a = UNPACK(*src, 24, 8); + + + + dst[0] = _mesa_unorm_to_unorm(r, 8, 8); + + + dst[1] = _mesa_unorm_to_unorm(g, 8, 8); + + + dst[2] = _mesa_unorm_to_unorm(b, 8, 8); + + + dst[3] = _mesa_unorm_to_unorm(a, 8, 8); +} + +static inline void +unpack_ubyte_b8g8r8x8_unorm(const void *void_src, GLubyte dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t b = UNPACK(*src, 0, 8); + uint8_t g = UNPACK(*src, 8, 8); + uint8_t r = UNPACK(*src, 16, 8); + + + + dst[0] = _mesa_unorm_to_unorm(r, 8, 8); + + + dst[1] = _mesa_unorm_to_unorm(g, 8, 8); + + + dst[2] = _mesa_unorm_to_unorm(b, 8, 8); + + dst[3] = 255; +} + +static inline void +unpack_ubyte_a8r8g8b8_unorm(const void *void_src, GLubyte dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t a = UNPACK(*src, 0, 8); + uint8_t r = UNPACK(*src, 8, 8); + uint8_t g = UNPACK(*src, 16, 8); + uint8_t b = UNPACK(*src, 24, 8); + + + + dst[0] = _mesa_unorm_to_unorm(r, 8, 8); + + + dst[1] = _mesa_unorm_to_unorm(g, 8, 8); + + + dst[2] = _mesa_unorm_to_unorm(b, 8, 8); + + + dst[3] = _mesa_unorm_to_unorm(a, 8, 8); +} + +static inline void +unpack_ubyte_x8r8g8b8_unorm(const void *void_src, GLubyte dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t r = UNPACK(*src, 8, 8); + uint8_t g = UNPACK(*src, 16, 8); + uint8_t b = UNPACK(*src, 24, 8); + + + + dst[0] = _mesa_unorm_to_unorm(r, 8, 8); + + + dst[1] = _mesa_unorm_to_unorm(g, 8, 8); + + + dst[2] = _mesa_unorm_to_unorm(b, 8, 8); + + dst[3] = 255; +} + +static inline void +unpack_ubyte_l16a16_unorm(const void *void_src, GLubyte dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint16_t l = UNPACK(*src, 0, 16); + uint16_t a = UNPACK(*src, 16, 16); + + + + dst[0] = _mesa_unorm_to_unorm(l, 16, 8); + + + dst[1] = _mesa_unorm_to_unorm(l, 16, 8); + + + dst[2] = _mesa_unorm_to_unorm(l, 16, 8); + + + dst[3] = _mesa_unorm_to_unorm(a, 16, 8); +} + +static inline void +unpack_ubyte_a16l16_unorm(const void *void_src, GLubyte dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint16_t a = UNPACK(*src, 0, 16); + uint16_t l = UNPACK(*src, 16, 16); + + + + dst[0] = _mesa_unorm_to_unorm(l, 16, 8); + + + dst[1] = _mesa_unorm_to_unorm(l, 16, 8); + + + dst[2] = _mesa_unorm_to_unorm(l, 16, 8); + + + dst[3] = _mesa_unorm_to_unorm(a, 16, 8); +} + +static inline void +unpack_ubyte_b5g6r5_unorm(const void *void_src, GLubyte dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t b = UNPACK(*src, 0, 5); + uint8_t g = UNPACK(*src, 5, 6); + uint8_t r = UNPACK(*src, 11, 5); + + + + dst[0] = _mesa_unorm_to_unorm(r, 5, 8); + + + dst[1] = _mesa_unorm_to_unorm(g, 6, 8); + + + dst[2] = _mesa_unorm_to_unorm(b, 5, 8); + + dst[3] = 255; +} + +static inline void +unpack_ubyte_r5g6b5_unorm(const void *void_src, GLubyte dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t r = UNPACK(*src, 0, 5); + uint8_t g = UNPACK(*src, 5, 6); + uint8_t b = UNPACK(*src, 11, 5); + + + + dst[0] = _mesa_unorm_to_unorm(r, 5, 8); + + + dst[1] = _mesa_unorm_to_unorm(g, 6, 8); + + + dst[2] = _mesa_unorm_to_unorm(b, 5, 8); + + dst[3] = 255; +} + +static inline void +unpack_ubyte_b4g4r4a4_unorm(const void *void_src, GLubyte dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t b = UNPACK(*src, 0, 4); + uint8_t g = UNPACK(*src, 4, 4); + uint8_t r = UNPACK(*src, 8, 4); + uint8_t a = UNPACK(*src, 12, 4); + + + + dst[0] = _mesa_unorm_to_unorm(r, 4, 8); + + + dst[1] = _mesa_unorm_to_unorm(g, 4, 8); + + + dst[2] = _mesa_unorm_to_unorm(b, 4, 8); + + + dst[3] = _mesa_unorm_to_unorm(a, 4, 8); +} + +static inline void +unpack_ubyte_b4g4r4x4_unorm(const void *void_src, GLubyte dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t b = UNPACK(*src, 0, 4); + uint8_t g = UNPACK(*src, 4, 4); + uint8_t r = UNPACK(*src, 8, 4); + + + + dst[0] = _mesa_unorm_to_unorm(r, 4, 8); + + + dst[1] = _mesa_unorm_to_unorm(g, 4, 8); + + + dst[2] = _mesa_unorm_to_unorm(b, 4, 8); + + dst[3] = 255; +} + +static inline void +unpack_ubyte_a4r4g4b4_unorm(const void *void_src, GLubyte dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t a = UNPACK(*src, 0, 4); + uint8_t r = UNPACK(*src, 4, 4); + uint8_t g = UNPACK(*src, 8, 4); + uint8_t b = UNPACK(*src, 12, 4); + + + + dst[0] = _mesa_unorm_to_unorm(r, 4, 8); + + + dst[1] = _mesa_unorm_to_unorm(g, 4, 8); + + + dst[2] = _mesa_unorm_to_unorm(b, 4, 8); + + + dst[3] = _mesa_unorm_to_unorm(a, 4, 8); +} + +static inline void +unpack_ubyte_a1b5g5r5_unorm(const void *void_src, GLubyte dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t a = UNPACK(*src, 0, 1); + uint8_t b = UNPACK(*src, 1, 5); + uint8_t g = UNPACK(*src, 6, 5); + uint8_t r = UNPACK(*src, 11, 5); + + + + dst[0] = _mesa_unorm_to_unorm(r, 5, 8); + + + dst[1] = _mesa_unorm_to_unorm(g, 5, 8); + + + dst[2] = _mesa_unorm_to_unorm(b, 5, 8); + + + dst[3] = _mesa_unorm_to_unorm(a, 1, 8); +} + +static inline void +unpack_ubyte_x1b5g5r5_unorm(const void *void_src, GLubyte dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t b = UNPACK(*src, 1, 5); + uint8_t g = UNPACK(*src, 6, 5); + uint8_t r = UNPACK(*src, 11, 5); + + + + dst[0] = _mesa_unorm_to_unorm(r, 5, 8); + + + dst[1] = _mesa_unorm_to_unorm(g, 5, 8); + + + dst[2] = _mesa_unorm_to_unorm(b, 5, 8); + + dst[3] = 255; +} + +static inline void +unpack_ubyte_b5g5r5a1_unorm(const void *void_src, GLubyte dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t b = UNPACK(*src, 0, 5); + uint8_t g = UNPACK(*src, 5, 5); + uint8_t r = UNPACK(*src, 10, 5); + uint8_t a = UNPACK(*src, 15, 1); + + + + dst[0] = _mesa_unorm_to_unorm(r, 5, 8); + + + dst[1] = _mesa_unorm_to_unorm(g, 5, 8); + + + dst[2] = _mesa_unorm_to_unorm(b, 5, 8); + + + dst[3] = _mesa_unorm_to_unorm(a, 1, 8); +} + +static inline void +unpack_ubyte_b5g5r5x1_unorm(const void *void_src, GLubyte dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t b = UNPACK(*src, 0, 5); + uint8_t g = UNPACK(*src, 5, 5); + uint8_t r = UNPACK(*src, 10, 5); + + + + dst[0] = _mesa_unorm_to_unorm(r, 5, 8); + + + dst[1] = _mesa_unorm_to_unorm(g, 5, 8); + + + dst[2] = _mesa_unorm_to_unorm(b, 5, 8); + + dst[3] = 255; +} + +static inline void +unpack_ubyte_a1r5g5b5_unorm(const void *void_src, GLubyte dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t a = UNPACK(*src, 0, 1); + uint8_t r = UNPACK(*src, 1, 5); + uint8_t g = UNPACK(*src, 6, 5); + uint8_t b = UNPACK(*src, 11, 5); + + + + dst[0] = _mesa_unorm_to_unorm(r, 5, 8); + + + dst[1] = _mesa_unorm_to_unorm(g, 5, 8); + + + dst[2] = _mesa_unorm_to_unorm(b, 5, 8); + + + dst[3] = _mesa_unorm_to_unorm(a, 1, 8); +} + +static inline void +unpack_ubyte_l8a8_unorm(const void *void_src, GLubyte dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t l = UNPACK(*src, 0, 8); + uint8_t a = UNPACK(*src, 8, 8); + + + + dst[0] = _mesa_unorm_to_unorm(l, 8, 8); + + + dst[1] = _mesa_unorm_to_unorm(l, 8, 8); + + + dst[2] = _mesa_unorm_to_unorm(l, 8, 8); + + + dst[3] = _mesa_unorm_to_unorm(a, 8, 8); +} + +static inline void +unpack_ubyte_a8l8_unorm(const void *void_src, GLubyte dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t a = UNPACK(*src, 0, 8); + uint8_t l = UNPACK(*src, 8, 8); + + + + dst[0] = _mesa_unorm_to_unorm(l, 8, 8); + + + dst[1] = _mesa_unorm_to_unorm(l, 8, 8); + + + dst[2] = _mesa_unorm_to_unorm(l, 8, 8); + + + dst[3] = _mesa_unorm_to_unorm(a, 8, 8); +} + +static inline void +unpack_ubyte_r8g8_unorm(const void *void_src, GLubyte dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t r = UNPACK(*src, 0, 8); + uint8_t g = UNPACK(*src, 8, 8); + + + + dst[0] = _mesa_unorm_to_unorm(r, 8, 8); + + + dst[1] = _mesa_unorm_to_unorm(g, 8, 8); + + dst[2] = 0; + + dst[3] = 255; +} + +static inline void +unpack_ubyte_g8r8_unorm(const void *void_src, GLubyte dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t g = UNPACK(*src, 0, 8); + uint8_t r = UNPACK(*src, 8, 8); + + + + dst[0] = _mesa_unorm_to_unorm(r, 8, 8); + + + dst[1] = _mesa_unorm_to_unorm(g, 8, 8); + + dst[2] = 0; + + dst[3] = 255; +} + +static inline void +unpack_ubyte_l4a4_unorm(const void *void_src, GLubyte dst[4]) +{ + uint8_t *src = (uint8_t *)void_src; + uint8_t l = UNPACK(*src, 0, 4); + uint8_t a = UNPACK(*src, 4, 4); + + + + dst[0] = _mesa_unorm_to_unorm(l, 4, 8); + + + dst[1] = _mesa_unorm_to_unorm(l, 4, 8); + + + dst[2] = _mesa_unorm_to_unorm(l, 4, 8); + + + dst[3] = _mesa_unorm_to_unorm(a, 4, 8); +} + +static inline void +unpack_ubyte_b2g3r3_unorm(const void *void_src, GLubyte dst[4]) +{ + uint8_t *src = (uint8_t *)void_src; + uint8_t b = UNPACK(*src, 0, 2); + uint8_t g = UNPACK(*src, 2, 3); + uint8_t r = UNPACK(*src, 5, 3); + + + + dst[0] = _mesa_unorm_to_unorm(r, 3, 8); + + + dst[1] = _mesa_unorm_to_unorm(g, 3, 8); + + + dst[2] = _mesa_unorm_to_unorm(b, 2, 8); + + dst[3] = 255; +} + +static inline void +unpack_ubyte_r16g16_unorm(const void *void_src, GLubyte dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint16_t r = UNPACK(*src, 0, 16); + uint16_t g = UNPACK(*src, 16, 16); + + + + dst[0] = _mesa_unorm_to_unorm(r, 16, 8); + + + dst[1] = _mesa_unorm_to_unorm(g, 16, 8); + + dst[2] = 0; + + dst[3] = 255; +} + +static inline void +unpack_ubyte_g16r16_unorm(const void *void_src, GLubyte dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint16_t g = UNPACK(*src, 0, 16); + uint16_t r = UNPACK(*src, 16, 16); + + + + dst[0] = _mesa_unorm_to_unorm(r, 16, 8); + + + dst[1] = _mesa_unorm_to_unorm(g, 16, 8); + + dst[2] = 0; + + dst[3] = 255; +} + +static inline void +unpack_ubyte_b10g10r10a2_unorm(const void *void_src, GLubyte dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint16_t b = UNPACK(*src, 0, 10); + uint16_t g = UNPACK(*src, 10, 10); + uint16_t r = UNPACK(*src, 20, 10); + uint8_t a = UNPACK(*src, 30, 2); + + + + dst[0] = _mesa_unorm_to_unorm(r, 10, 8); + + + dst[1] = _mesa_unorm_to_unorm(g, 10, 8); + + + dst[2] = _mesa_unorm_to_unorm(b, 10, 8); + + + dst[3] = _mesa_unorm_to_unorm(a, 2, 8); +} + +static inline void +unpack_ubyte_b10g10r10x2_unorm(const void *void_src, GLubyte dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint16_t b = UNPACK(*src, 0, 10); + uint16_t g = UNPACK(*src, 10, 10); + uint16_t r = UNPACK(*src, 20, 10); + + + + dst[0] = _mesa_unorm_to_unorm(r, 10, 8); + + + dst[1] = _mesa_unorm_to_unorm(g, 10, 8); + + + dst[2] = _mesa_unorm_to_unorm(b, 10, 8); + + dst[3] = 255; +} + +static inline void +unpack_ubyte_r10g10b10a2_unorm(const void *void_src, GLubyte dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint16_t r = UNPACK(*src, 0, 10); + uint16_t g = UNPACK(*src, 10, 10); + uint16_t b = UNPACK(*src, 20, 10); + uint8_t a = UNPACK(*src, 30, 2); + + + + dst[0] = _mesa_unorm_to_unorm(r, 10, 8); + + + dst[1] = _mesa_unorm_to_unorm(g, 10, 8); + + + dst[2] = _mesa_unorm_to_unorm(b, 10, 8); + + + dst[3] = _mesa_unorm_to_unorm(a, 2, 8); +} + +static inline void +unpack_ubyte_r10g10b10x2_unorm(const void *void_src, GLubyte dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint16_t r = UNPACK(*src, 0, 10); + uint16_t g = UNPACK(*src, 10, 10); + uint16_t b = UNPACK(*src, 20, 10); + + + + dst[0] = _mesa_unorm_to_unorm(r, 10, 8); + + + dst[1] = _mesa_unorm_to_unorm(g, 10, 8); + + + dst[2] = _mesa_unorm_to_unorm(b, 10, 8); + + dst[3] = 255; +} + +static inline void +unpack_ubyte_r3g3b2_unorm(const void *void_src, GLubyte dst[4]) +{ + uint8_t *src = (uint8_t *)void_src; + uint8_t r = UNPACK(*src, 0, 3); + uint8_t g = UNPACK(*src, 3, 3); + uint8_t b = UNPACK(*src, 6, 2); + + + + dst[0] = _mesa_unorm_to_unorm(r, 3, 8); + + + dst[1] = _mesa_unorm_to_unorm(g, 3, 8); + + + dst[2] = _mesa_unorm_to_unorm(b, 2, 8); + + dst[3] = 255; +} + +static inline void +unpack_ubyte_a4b4g4r4_unorm(const void *void_src, GLubyte dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t a = UNPACK(*src, 0, 4); + uint8_t b = UNPACK(*src, 4, 4); + uint8_t g = UNPACK(*src, 8, 4); + uint8_t r = UNPACK(*src, 12, 4); + + + + dst[0] = _mesa_unorm_to_unorm(r, 4, 8); + + + dst[1] = _mesa_unorm_to_unorm(g, 4, 8); + + + dst[2] = _mesa_unorm_to_unorm(b, 4, 8); + + + dst[3] = _mesa_unorm_to_unorm(a, 4, 8); +} + +static inline void +unpack_ubyte_r4g4b4a4_unorm(const void *void_src, GLubyte dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t r = UNPACK(*src, 0, 4); + uint8_t g = UNPACK(*src, 4, 4); + uint8_t b = UNPACK(*src, 8, 4); + uint8_t a = UNPACK(*src, 12, 4); + + + + dst[0] = _mesa_unorm_to_unorm(r, 4, 8); + + + dst[1] = _mesa_unorm_to_unorm(g, 4, 8); + + + dst[2] = _mesa_unorm_to_unorm(b, 4, 8); + + + dst[3] = _mesa_unorm_to_unorm(a, 4, 8); +} + +static inline void +unpack_ubyte_r5g5b5a1_unorm(const void *void_src, GLubyte dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t r = UNPACK(*src, 0, 5); + uint8_t g = UNPACK(*src, 5, 5); + uint8_t b = UNPACK(*src, 10, 5); + uint8_t a = UNPACK(*src, 15, 1); + + + + dst[0] = _mesa_unorm_to_unorm(r, 5, 8); + + + dst[1] = _mesa_unorm_to_unorm(g, 5, 8); + + + dst[2] = _mesa_unorm_to_unorm(b, 5, 8); + + + dst[3] = _mesa_unorm_to_unorm(a, 1, 8); +} + +static inline void +unpack_ubyte_a2b10g10r10_unorm(const void *void_src, GLubyte dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t a = UNPACK(*src, 0, 2); + uint16_t b = UNPACK(*src, 2, 10); + uint16_t g = UNPACK(*src, 12, 10); + uint16_t r = UNPACK(*src, 22, 10); + + + + dst[0] = _mesa_unorm_to_unorm(r, 10, 8); + + + dst[1] = _mesa_unorm_to_unorm(g, 10, 8); + + + dst[2] = _mesa_unorm_to_unorm(b, 10, 8); + + + dst[3] = _mesa_unorm_to_unorm(a, 2, 8); +} + +static inline void +unpack_ubyte_a2r10g10b10_unorm(const void *void_src, GLubyte dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t a = UNPACK(*src, 0, 2); + uint16_t r = UNPACK(*src, 2, 10); + uint16_t g = UNPACK(*src, 12, 10); + uint16_t b = UNPACK(*src, 22, 10); + + + + dst[0] = _mesa_unorm_to_unorm(r, 10, 8); + + + dst[1] = _mesa_unorm_to_unorm(g, 10, 8); + + + dst[2] = _mesa_unorm_to_unorm(b, 10, 8); + + + dst[3] = _mesa_unorm_to_unorm(a, 2, 8); +} + +static inline void +unpack_ubyte_a_unorm8(const void *void_src, GLubyte dst[4]) +{ + uint8_t *src = (uint8_t *)void_src; + uint8_t a = src[0]; + + + dst[0] = 0; + + dst[1] = 0; + + dst[2] = 0; + + + dst[3] = _mesa_unorm_to_unorm(a, 8, 8); +} + +static inline void +unpack_ubyte_a_unorm16(const void *void_src, GLubyte dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint16_t a = src[0]; + + + dst[0] = 0; + + dst[1] = 0; + + dst[2] = 0; + + + dst[3] = _mesa_unorm_to_unorm(a, 16, 8); +} + +static inline void +unpack_ubyte_l_unorm8(const void *void_src, GLubyte dst[4]) +{ + uint8_t *src = (uint8_t *)void_src; + uint8_t l = src[0]; + + + + dst[0] = _mesa_unorm_to_unorm(l, 8, 8); + + + dst[1] = _mesa_unorm_to_unorm(l, 8, 8); + + + dst[2] = _mesa_unorm_to_unorm(l, 8, 8); + + dst[3] = 255; +} + +static inline void +unpack_ubyte_l_unorm16(const void *void_src, GLubyte dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint16_t l = src[0]; + + + + dst[0] = _mesa_unorm_to_unorm(l, 16, 8); + + + dst[1] = _mesa_unorm_to_unorm(l, 16, 8); + + + dst[2] = _mesa_unorm_to_unorm(l, 16, 8); + + dst[3] = 255; +} + +static inline void +unpack_ubyte_i_unorm8(const void *void_src, GLubyte dst[4]) +{ + uint8_t *src = (uint8_t *)void_src; + uint8_t i = src[0]; + + + + dst[0] = _mesa_unorm_to_unorm(i, 8, 8); + + + dst[1] = _mesa_unorm_to_unorm(i, 8, 8); + + + dst[2] = _mesa_unorm_to_unorm(i, 8, 8); + + + dst[3] = _mesa_unorm_to_unorm(i, 8, 8); +} + +static inline void +unpack_ubyte_i_unorm16(const void *void_src, GLubyte dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint16_t i = src[0]; + + + + dst[0] = _mesa_unorm_to_unorm(i, 16, 8); + + + dst[1] = _mesa_unorm_to_unorm(i, 16, 8); + + + dst[2] = _mesa_unorm_to_unorm(i, 16, 8); + + + dst[3] = _mesa_unorm_to_unorm(i, 16, 8); +} + +static inline void +unpack_ubyte_r_unorm8(const void *void_src, GLubyte dst[4]) +{ + uint8_t *src = (uint8_t *)void_src; + uint8_t r = src[0]; + + + + dst[0] = _mesa_unorm_to_unorm(r, 8, 8); + + dst[1] = 0; + + dst[2] = 0; + + dst[3] = 255; +} + +static inline void +unpack_ubyte_r_unorm16(const void *void_src, GLubyte dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint16_t r = src[0]; + + + + dst[0] = _mesa_unorm_to_unorm(r, 16, 8); + + dst[1] = 0; + + dst[2] = 0; + + dst[3] = 255; +} + +static inline void +unpack_ubyte_bgr_unorm8(const void *void_src, GLubyte dst[4]) +{ + uint8_t *src = (uint8_t *)void_src; + uint8_t b = src[0]; + uint8_t g = src[1]; + uint8_t r = src[2]; + + + + dst[0] = _mesa_unorm_to_unorm(r, 8, 8); + + + dst[1] = _mesa_unorm_to_unorm(g, 8, 8); + + + dst[2] = _mesa_unorm_to_unorm(b, 8, 8); + + dst[3] = 255; +} + +static inline void +unpack_ubyte_rgb_unorm8(const void *void_src, GLubyte dst[4]) +{ + uint8_t *src = (uint8_t *)void_src; + uint8_t r = src[0]; + uint8_t g = src[1]; + uint8_t b = src[2]; + + + + dst[0] = _mesa_unorm_to_unorm(r, 8, 8); + + + dst[1] = _mesa_unorm_to_unorm(g, 8, 8); + + + dst[2] = _mesa_unorm_to_unorm(b, 8, 8); + + dst[3] = 255; +} + +static inline void +unpack_ubyte_rgba_unorm16(const void *void_src, GLubyte dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint16_t r = src[0]; + uint16_t g = src[1]; + uint16_t b = src[2]; + uint16_t a = src[3]; + + + + dst[0] = _mesa_unorm_to_unorm(r, 16, 8); + + + dst[1] = _mesa_unorm_to_unorm(g, 16, 8); + + + dst[2] = _mesa_unorm_to_unorm(b, 16, 8); + + + dst[3] = _mesa_unorm_to_unorm(a, 16, 8); +} + +static inline void +unpack_ubyte_rgbx_unorm16(const void *void_src, GLubyte dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint16_t r = src[0]; + uint16_t g = src[1]; + uint16_t b = src[2]; + + + + dst[0] = _mesa_unorm_to_unorm(r, 16, 8); + + + dst[1] = _mesa_unorm_to_unorm(g, 16, 8); + + + dst[2] = _mesa_unorm_to_unorm(b, 16, 8); + + dst[3] = 255; +} + +static inline void +unpack_ubyte_a8b8g8r8_snorm(const void *void_src, GLubyte dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + int8_t a = UNPACK(*src, 0, 8); + int8_t b = UNPACK(*src, 8, 8); + int8_t g = UNPACK(*src, 16, 8); + int8_t r = UNPACK(*src, 24, 8); + + + + dst[0] = _mesa_snorm_to_unorm(r, 8, 8); + + + dst[1] = _mesa_snorm_to_unorm(g, 8, 8); + + + dst[2] = _mesa_snorm_to_unorm(b, 8, 8); + + + dst[3] = _mesa_snorm_to_unorm(a, 8, 8); +} + +static inline void +unpack_ubyte_x8b8g8r8_snorm(const void *void_src, GLubyte dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + int8_t b = UNPACK(*src, 8, 8); + int8_t g = UNPACK(*src, 16, 8); + int8_t r = UNPACK(*src, 24, 8); + + + + dst[0] = _mesa_snorm_to_unorm(r, 8, 8); + + + dst[1] = _mesa_snorm_to_unorm(g, 8, 8); + + + dst[2] = _mesa_snorm_to_unorm(b, 8, 8); + + dst[3] = 255; +} + +static inline void +unpack_ubyte_r8g8b8a8_snorm(const void *void_src, GLubyte dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + int8_t r = UNPACK(*src, 0, 8); + int8_t g = UNPACK(*src, 8, 8); + int8_t b = UNPACK(*src, 16, 8); + int8_t a = UNPACK(*src, 24, 8); + + + + dst[0] = _mesa_snorm_to_unorm(r, 8, 8); + + + dst[1] = _mesa_snorm_to_unorm(g, 8, 8); + + + dst[2] = _mesa_snorm_to_unorm(b, 8, 8); + + + dst[3] = _mesa_snorm_to_unorm(a, 8, 8); +} + +static inline void +unpack_ubyte_r8g8b8x8_snorm(const void *void_src, GLubyte dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + int8_t r = UNPACK(*src, 0, 8); + int8_t g = UNPACK(*src, 8, 8); + int8_t b = UNPACK(*src, 16, 8); + + + + dst[0] = _mesa_snorm_to_unorm(r, 8, 8); + + + dst[1] = _mesa_snorm_to_unorm(g, 8, 8); + + + dst[2] = _mesa_snorm_to_unorm(b, 8, 8); + + dst[3] = 255; +} + +static inline void +unpack_ubyte_r16g16_snorm(const void *void_src, GLubyte dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + int16_t r = UNPACK(*src, 0, 16); + int16_t g = UNPACK(*src, 16, 16); + + + + dst[0] = _mesa_snorm_to_unorm(r, 16, 8); + + + dst[1] = _mesa_snorm_to_unorm(g, 16, 8); + + dst[2] = 0; + + dst[3] = 255; +} + +static inline void +unpack_ubyte_g16r16_snorm(const void *void_src, GLubyte dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + int16_t g = UNPACK(*src, 0, 16); + int16_t r = UNPACK(*src, 16, 16); + + + + dst[0] = _mesa_snorm_to_unorm(r, 16, 8); + + + dst[1] = _mesa_snorm_to_unorm(g, 16, 8); + + dst[2] = 0; + + dst[3] = 255; +} + +static inline void +unpack_ubyte_r8g8_snorm(const void *void_src, GLubyte dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + int8_t r = UNPACK(*src, 0, 8); + int8_t g = UNPACK(*src, 8, 8); + + + + dst[0] = _mesa_snorm_to_unorm(r, 8, 8); + + + dst[1] = _mesa_snorm_to_unorm(g, 8, 8); + + dst[2] = 0; + + dst[3] = 255; +} + +static inline void +unpack_ubyte_g8r8_snorm(const void *void_src, GLubyte dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + int8_t g = UNPACK(*src, 0, 8); + int8_t r = UNPACK(*src, 8, 8); + + + + dst[0] = _mesa_snorm_to_unorm(r, 8, 8); + + + dst[1] = _mesa_snorm_to_unorm(g, 8, 8); + + dst[2] = 0; + + dst[3] = 255; +} + +static inline void +unpack_ubyte_l8a8_snorm(const void *void_src, GLubyte dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + int8_t l = UNPACK(*src, 0, 8); + int8_t a = UNPACK(*src, 8, 8); + + + + dst[0] = _mesa_snorm_to_unorm(l, 8, 8); + + + dst[1] = _mesa_snorm_to_unorm(l, 8, 8); + + + dst[2] = _mesa_snorm_to_unorm(l, 8, 8); + + + dst[3] = _mesa_snorm_to_unorm(a, 8, 8); +} + +static inline void +unpack_ubyte_a8l8_snorm(const void *void_src, GLubyte dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + int8_t a = UNPACK(*src, 0, 8); + int8_t l = UNPACK(*src, 8, 8); + + + + dst[0] = _mesa_snorm_to_unorm(l, 8, 8); + + + dst[1] = _mesa_snorm_to_unorm(l, 8, 8); + + + dst[2] = _mesa_snorm_to_unorm(l, 8, 8); + + + dst[3] = _mesa_snorm_to_unorm(a, 8, 8); +} + +static inline void +unpack_ubyte_a_snorm8(const void *void_src, GLubyte dst[4]) +{ + int8_t *src = (int8_t *)void_src; + int8_t a = src[0]; + + + dst[0] = 0; + + dst[1] = 0; + + dst[2] = 0; + + + dst[3] = _mesa_snorm_to_unorm(a, 8, 8); +} + +static inline void +unpack_ubyte_a_snorm16(const void *void_src, GLubyte dst[4]) +{ + int16_t *src = (int16_t *)void_src; + int16_t a = src[0]; + + + dst[0] = 0; + + dst[1] = 0; + + dst[2] = 0; + + + dst[3] = _mesa_snorm_to_unorm(a, 16, 8); +} + +static inline void +unpack_ubyte_l_snorm8(const void *void_src, GLubyte dst[4]) +{ + int8_t *src = (int8_t *)void_src; + int8_t l = src[0]; + + + + dst[0] = _mesa_snorm_to_unorm(l, 8, 8); + + + dst[1] = _mesa_snorm_to_unorm(l, 8, 8); + + + dst[2] = _mesa_snorm_to_unorm(l, 8, 8); + + dst[3] = 255; +} + +static inline void +unpack_ubyte_l_snorm16(const void *void_src, GLubyte dst[4]) +{ + int16_t *src = (int16_t *)void_src; + int16_t l = src[0]; + + + + dst[0] = _mesa_snorm_to_unorm(l, 16, 8); + + + dst[1] = _mesa_snorm_to_unorm(l, 16, 8); + + + dst[2] = _mesa_snorm_to_unorm(l, 16, 8); + + dst[3] = 255; +} + +static inline void +unpack_ubyte_i_snorm8(const void *void_src, GLubyte dst[4]) +{ + int8_t *src = (int8_t *)void_src; + int8_t i = src[0]; + + + + dst[0] = _mesa_snorm_to_unorm(i, 8, 8); + + + dst[1] = _mesa_snorm_to_unorm(i, 8, 8); + + + dst[2] = _mesa_snorm_to_unorm(i, 8, 8); + + + dst[3] = _mesa_snorm_to_unorm(i, 8, 8); +} + +static inline void +unpack_ubyte_i_snorm16(const void *void_src, GLubyte dst[4]) +{ + int16_t *src = (int16_t *)void_src; + int16_t i = src[0]; + + + + dst[0] = _mesa_snorm_to_unorm(i, 16, 8); + + + dst[1] = _mesa_snorm_to_unorm(i, 16, 8); + + + dst[2] = _mesa_snorm_to_unorm(i, 16, 8); + + + dst[3] = _mesa_snorm_to_unorm(i, 16, 8); +} + +static inline void +unpack_ubyte_r_snorm8(const void *void_src, GLubyte dst[4]) +{ + int8_t *src = (int8_t *)void_src; + int8_t r = src[0]; + + + + dst[0] = _mesa_snorm_to_unorm(r, 8, 8); + + dst[1] = 0; + + dst[2] = 0; + + dst[3] = 255; +} + +static inline void +unpack_ubyte_r_snorm16(const void *void_src, GLubyte dst[4]) +{ + int16_t *src = (int16_t *)void_src; + int16_t r = src[0]; + + + + dst[0] = _mesa_snorm_to_unorm(r, 16, 8); + + dst[1] = 0; + + dst[2] = 0; + + dst[3] = 255; +} + +static inline void +unpack_ubyte_la_snorm16(const void *void_src, GLubyte dst[4]) +{ + int16_t *src = (int16_t *)void_src; + int16_t l = src[0]; + int16_t a = src[1]; + + + + dst[0] = _mesa_snorm_to_unorm(l, 16, 8); + + + dst[1] = _mesa_snorm_to_unorm(l, 16, 8); + + + dst[2] = _mesa_snorm_to_unorm(l, 16, 8); + + + dst[3] = _mesa_snorm_to_unorm(a, 16, 8); +} + +static inline void +unpack_ubyte_rgb_snorm16(const void *void_src, GLubyte dst[4]) +{ + int16_t *src = (int16_t *)void_src; + int16_t r = src[0]; + int16_t g = src[1]; + int16_t b = src[2]; + + + + dst[0] = _mesa_snorm_to_unorm(r, 16, 8); + + + dst[1] = _mesa_snorm_to_unorm(g, 16, 8); + + + dst[2] = _mesa_snorm_to_unorm(b, 16, 8); + + dst[3] = 255; +} + +static inline void +unpack_ubyte_rgba_snorm16(const void *void_src, GLubyte dst[4]) +{ + int16_t *src = (int16_t *)void_src; + int16_t r = src[0]; + int16_t g = src[1]; + int16_t b = src[2]; + int16_t a = src[3]; + + + + dst[0] = _mesa_snorm_to_unorm(r, 16, 8); + + + dst[1] = _mesa_snorm_to_unorm(g, 16, 8); + + + dst[2] = _mesa_snorm_to_unorm(b, 16, 8); + + + dst[3] = _mesa_snorm_to_unorm(a, 16, 8); +} + +static inline void +unpack_ubyte_rgbx_snorm16(const void *void_src, GLubyte dst[4]) +{ + int16_t *src = (int16_t *)void_src; + int16_t r = src[0]; + int16_t g = src[1]; + int16_t b = src[2]; + + + + dst[0] = _mesa_snorm_to_unorm(r, 16, 8); + + + dst[1] = _mesa_snorm_to_unorm(g, 16, 8); + + + dst[2] = _mesa_snorm_to_unorm(b, 16, 8); + + dst[3] = 255; +} + +static inline void +unpack_ubyte_a8b8g8r8_srgb(const void *void_src, GLubyte dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t a = UNPACK(*src, 0, 8); + uint8_t b = UNPACK(*src, 8, 8); + uint8_t g = UNPACK(*src, 16, 8); + uint8_t r = UNPACK(*src, 24, 8); + + + + + dst[0] = util_format_srgb_to_linear_8unorm(r); + + + + dst[1] = util_format_srgb_to_linear_8unorm(g); + + + + dst[2] = util_format_srgb_to_linear_8unorm(b); + + + dst[3] = _mesa_unorm_to_unorm(a, 8, 8); +} + +static inline void +unpack_ubyte_b8g8r8a8_srgb(const void *void_src, GLubyte dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t b = UNPACK(*src, 0, 8); + uint8_t g = UNPACK(*src, 8, 8); + uint8_t r = UNPACK(*src, 16, 8); + uint8_t a = UNPACK(*src, 24, 8); + + + + + dst[0] = util_format_srgb_to_linear_8unorm(r); + + + + dst[1] = util_format_srgb_to_linear_8unorm(g); + + + + dst[2] = util_format_srgb_to_linear_8unorm(b); + + + dst[3] = _mesa_unorm_to_unorm(a, 8, 8); +} + +static inline void +unpack_ubyte_a8r8g8b8_srgb(const void *void_src, GLubyte dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t a = UNPACK(*src, 0, 8); + uint8_t r = UNPACK(*src, 8, 8); + uint8_t g = UNPACK(*src, 16, 8); + uint8_t b = UNPACK(*src, 24, 8); + + + + + dst[0] = util_format_srgb_to_linear_8unorm(r); + + + + dst[1] = util_format_srgb_to_linear_8unorm(g); + + + + dst[2] = util_format_srgb_to_linear_8unorm(b); + + + dst[3] = _mesa_unorm_to_unorm(a, 8, 8); +} + +static inline void +unpack_ubyte_b8g8r8x8_srgb(const void *void_src, GLubyte dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t b = UNPACK(*src, 0, 8); + uint8_t g = UNPACK(*src, 8, 8); + uint8_t r = UNPACK(*src, 16, 8); + + + + + dst[0] = util_format_srgb_to_linear_8unorm(r); + + + + dst[1] = util_format_srgb_to_linear_8unorm(g); + + + + dst[2] = util_format_srgb_to_linear_8unorm(b); + + dst[3] = 255; +} + +static inline void +unpack_ubyte_x8r8g8b8_srgb(const void *void_src, GLubyte dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t r = UNPACK(*src, 8, 8); + uint8_t g = UNPACK(*src, 16, 8); + uint8_t b = UNPACK(*src, 24, 8); + + + + + dst[0] = util_format_srgb_to_linear_8unorm(r); + + + + dst[1] = util_format_srgb_to_linear_8unorm(g); + + + + dst[2] = util_format_srgb_to_linear_8unorm(b); + + dst[3] = 255; +} + +static inline void +unpack_ubyte_r8g8b8a8_srgb(const void *void_src, GLubyte dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t r = UNPACK(*src, 0, 8); + uint8_t g = UNPACK(*src, 8, 8); + uint8_t b = UNPACK(*src, 16, 8); + uint8_t a = UNPACK(*src, 24, 8); + + + + + dst[0] = util_format_srgb_to_linear_8unorm(r); + + + + dst[1] = util_format_srgb_to_linear_8unorm(g); + + + + dst[2] = util_format_srgb_to_linear_8unorm(b); + + + dst[3] = _mesa_unorm_to_unorm(a, 8, 8); +} + +static inline void +unpack_ubyte_r8g8b8x8_srgb(const void *void_src, GLubyte dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t r = UNPACK(*src, 0, 8); + uint8_t g = UNPACK(*src, 8, 8); + uint8_t b = UNPACK(*src, 16, 8); + + + + + dst[0] = util_format_srgb_to_linear_8unorm(r); + + + + dst[1] = util_format_srgb_to_linear_8unorm(g); + + + + dst[2] = util_format_srgb_to_linear_8unorm(b); + + dst[3] = 255; +} + +static inline void +unpack_ubyte_x8b8g8r8_srgb(const void *void_src, GLubyte dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t b = UNPACK(*src, 8, 8); + uint8_t g = UNPACK(*src, 16, 8); + uint8_t r = UNPACK(*src, 24, 8); + + + + + dst[0] = util_format_srgb_to_linear_8unorm(r); + + + + dst[1] = util_format_srgb_to_linear_8unorm(g); + + + + dst[2] = util_format_srgb_to_linear_8unorm(b); + + dst[3] = 255; +} + +static inline void +unpack_ubyte_l8a8_srgb(const void *void_src, GLubyte dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t l = UNPACK(*src, 0, 8); + uint8_t a = UNPACK(*src, 8, 8); + + + + dst[0] = _mesa_unorm_to_unorm(l, 8, 8); + + + dst[1] = _mesa_unorm_to_unorm(l, 8, 8); + + + dst[2] = _mesa_unorm_to_unorm(l, 8, 8); + + + dst[3] = _mesa_unorm_to_unorm(a, 8, 8); +} + +static inline void +unpack_ubyte_a8l8_srgb(const void *void_src, GLubyte dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t a = UNPACK(*src, 0, 8); + uint8_t l = UNPACK(*src, 8, 8); + + + + dst[0] = _mesa_unorm_to_unorm(l, 8, 8); + + + dst[1] = _mesa_unorm_to_unorm(l, 8, 8); + + + dst[2] = _mesa_unorm_to_unorm(l, 8, 8); + + + dst[3] = _mesa_unorm_to_unorm(a, 8, 8); +} + +static inline void +unpack_ubyte_r_srgb8(const void *void_src, GLubyte dst[4]) +{ + uint8_t *src = (uint8_t *)void_src; + uint8_t r = src[0]; + + + + + dst[0] = util_format_srgb_to_linear_8unorm(r); + + dst[1] = 0; + + dst[2] = 0; + + dst[3] = 255; +} + +static inline void +unpack_ubyte_l_srgb8(const void *void_src, GLubyte dst[4]) +{ + uint8_t *src = (uint8_t *)void_src; + uint8_t l = src[0]; + + + + dst[0] = _mesa_unorm_to_unorm(l, 8, 8); + + + dst[1] = _mesa_unorm_to_unorm(l, 8, 8); + + + dst[2] = _mesa_unorm_to_unorm(l, 8, 8); + + dst[3] = 255; +} + +static inline void +unpack_ubyte_bgr_srgb8(const void *void_src, GLubyte dst[4]) +{ + uint8_t *src = (uint8_t *)void_src; + uint8_t b = src[0]; + uint8_t g = src[1]; + uint8_t r = src[2]; + + + + + dst[0] = util_format_srgb_to_linear_8unorm(r); + + + + dst[1] = util_format_srgb_to_linear_8unorm(g); + + + + dst[2] = util_format_srgb_to_linear_8unorm(b); + + dst[3] = 255; +} + +/* integer packing functions */ + + +static inline void +unpack_int_a8b8g8r8_uint(const void *void_src, GLuint dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t a = UNPACK(*src, 0, 8); + uint8_t b = UNPACK(*src, 8, 8); + uint8_t g = UNPACK(*src, 16, 8); + uint8_t r = UNPACK(*src, 24, 8); + + + dst[0] = r; + + dst[1] = g; + + dst[2] = b; + + dst[3] = a; +} + +static inline void +unpack_int_a8r8g8b8_uint(const void *void_src, GLuint dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t a = UNPACK(*src, 0, 8); + uint8_t r = UNPACK(*src, 8, 8); + uint8_t g = UNPACK(*src, 16, 8); + uint8_t b = UNPACK(*src, 24, 8); + + + dst[0] = r; + + dst[1] = g; + + dst[2] = b; + + dst[3] = a; +} + +static inline void +unpack_int_r8g8b8a8_uint(const void *void_src, GLuint dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t r = UNPACK(*src, 0, 8); + uint8_t g = UNPACK(*src, 8, 8); + uint8_t b = UNPACK(*src, 16, 8); + uint8_t a = UNPACK(*src, 24, 8); + + + dst[0] = r; + + dst[1] = g; + + dst[2] = b; + + dst[3] = a; +} + +static inline void +unpack_int_b8g8r8a8_uint(const void *void_src, GLuint dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t b = UNPACK(*src, 0, 8); + uint8_t g = UNPACK(*src, 8, 8); + uint8_t r = UNPACK(*src, 16, 8); + uint8_t a = UNPACK(*src, 24, 8); + + + dst[0] = r; + + dst[1] = g; + + dst[2] = b; + + dst[3] = a; +} + +static inline void +unpack_int_b10g10r10a2_uint(const void *void_src, GLuint dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint16_t b = UNPACK(*src, 0, 10); + uint16_t g = UNPACK(*src, 10, 10); + uint16_t r = UNPACK(*src, 20, 10); + uint8_t a = UNPACK(*src, 30, 2); + + + dst[0] = r; + + dst[1] = g; + + dst[2] = b; + + dst[3] = a; +} + +static inline void +unpack_int_r10g10b10a2_uint(const void *void_src, GLuint dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint16_t r = UNPACK(*src, 0, 10); + uint16_t g = UNPACK(*src, 10, 10); + uint16_t b = UNPACK(*src, 20, 10); + uint8_t a = UNPACK(*src, 30, 2); + + + dst[0] = r; + + dst[1] = g; + + dst[2] = b; + + dst[3] = a; +} + +static inline void +unpack_int_a2b10g10r10_uint(const void *void_src, GLuint dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t a = UNPACK(*src, 0, 2); + uint16_t b = UNPACK(*src, 2, 10); + uint16_t g = UNPACK(*src, 12, 10); + uint16_t r = UNPACK(*src, 22, 10); + + + dst[0] = r; + + dst[1] = g; + + dst[2] = b; + + dst[3] = a; +} + +static inline void +unpack_int_a2r10g10b10_uint(const void *void_src, GLuint dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint8_t a = UNPACK(*src, 0, 2); + uint16_t r = UNPACK(*src, 2, 10); + uint16_t g = UNPACK(*src, 12, 10); + uint16_t b = UNPACK(*src, 22, 10); + + + dst[0] = r; + + dst[1] = g; + + dst[2] = b; + + dst[3] = a; +} + +static inline void +unpack_int_b5g6r5_uint(const void *void_src, GLuint dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t b = UNPACK(*src, 0, 5); + uint8_t g = UNPACK(*src, 5, 6); + uint8_t r = UNPACK(*src, 11, 5); + + + dst[0] = r; + + dst[1] = g; + + dst[2] = b; + + dst[3] = 1; +} + +static inline void +unpack_int_r5g6b5_uint(const void *void_src, GLuint dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t r = UNPACK(*src, 0, 5); + uint8_t g = UNPACK(*src, 5, 6); + uint8_t b = UNPACK(*src, 11, 5); + + + dst[0] = r; + + dst[1] = g; + + dst[2] = b; + + dst[3] = 1; +} + +static inline void +unpack_int_b2g3r3_uint(const void *void_src, GLuint dst[4]) +{ + uint8_t *src = (uint8_t *)void_src; + uint8_t b = UNPACK(*src, 0, 2); + uint8_t g = UNPACK(*src, 2, 3); + uint8_t r = UNPACK(*src, 5, 3); + + + dst[0] = r; + + dst[1] = g; + + dst[2] = b; + + dst[3] = 1; +} + +static inline void +unpack_int_r3g3b2_uint(const void *void_src, GLuint dst[4]) +{ + uint8_t *src = (uint8_t *)void_src; + uint8_t r = UNPACK(*src, 0, 3); + uint8_t g = UNPACK(*src, 3, 3); + uint8_t b = UNPACK(*src, 6, 2); + + + dst[0] = r; + + dst[1] = g; + + dst[2] = b; + + dst[3] = 1; +} + +static inline void +unpack_int_a4b4g4r4_uint(const void *void_src, GLuint dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t a = UNPACK(*src, 0, 4); + uint8_t b = UNPACK(*src, 4, 4); + uint8_t g = UNPACK(*src, 8, 4); + uint8_t r = UNPACK(*src, 12, 4); + + + dst[0] = r; + + dst[1] = g; + + dst[2] = b; + + dst[3] = a; +} + +static inline void +unpack_int_r4g4b4a4_uint(const void *void_src, GLuint dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t r = UNPACK(*src, 0, 4); + uint8_t g = UNPACK(*src, 4, 4); + uint8_t b = UNPACK(*src, 8, 4); + uint8_t a = UNPACK(*src, 12, 4); + + + dst[0] = r; + + dst[1] = g; + + dst[2] = b; + + dst[3] = a; +} + +static inline void +unpack_int_b4g4r4a4_uint(const void *void_src, GLuint dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t b = UNPACK(*src, 0, 4); + uint8_t g = UNPACK(*src, 4, 4); + uint8_t r = UNPACK(*src, 8, 4); + uint8_t a = UNPACK(*src, 12, 4); + + + dst[0] = r; + + dst[1] = g; + + dst[2] = b; + + dst[3] = a; +} + +static inline void +unpack_int_a4r4g4b4_uint(const void *void_src, GLuint dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t a = UNPACK(*src, 0, 4); + uint8_t r = UNPACK(*src, 4, 4); + uint8_t g = UNPACK(*src, 8, 4); + uint8_t b = UNPACK(*src, 12, 4); + + + dst[0] = r; + + dst[1] = g; + + dst[2] = b; + + dst[3] = a; +} + +static inline void +unpack_int_a1b5g5r5_uint(const void *void_src, GLuint dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t a = UNPACK(*src, 0, 1); + uint8_t b = UNPACK(*src, 1, 5); + uint8_t g = UNPACK(*src, 6, 5); + uint8_t r = UNPACK(*src, 11, 5); + + + dst[0] = r; + + dst[1] = g; + + dst[2] = b; + + dst[3] = a; +} + +static inline void +unpack_int_b5g5r5a1_uint(const void *void_src, GLuint dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t b = UNPACK(*src, 0, 5); + uint8_t g = UNPACK(*src, 5, 5); + uint8_t r = UNPACK(*src, 10, 5); + uint8_t a = UNPACK(*src, 15, 1); + + + dst[0] = r; + + dst[1] = g; + + dst[2] = b; + + dst[3] = a; +} + +static inline void +unpack_int_a1r5g5b5_uint(const void *void_src, GLuint dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t a = UNPACK(*src, 0, 1); + uint8_t r = UNPACK(*src, 1, 5); + uint8_t g = UNPACK(*src, 6, 5); + uint8_t b = UNPACK(*src, 11, 5); + + + dst[0] = r; + + dst[1] = g; + + dst[2] = b; + + dst[3] = a; +} + +static inline void +unpack_int_r5g5b5a1_uint(const void *void_src, GLuint dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint8_t r = UNPACK(*src, 0, 5); + uint8_t g = UNPACK(*src, 5, 5); + uint8_t b = UNPACK(*src, 10, 5); + uint8_t a = UNPACK(*src, 15, 1); + + + dst[0] = r; + + dst[1] = g; + + dst[2] = b; + + dst[3] = a; +} + +static inline void +unpack_int_a_uint8(const void *void_src, GLuint dst[4]) +{ + uint8_t *src = (uint8_t *)void_src; + uint8_t a = src[0]; + + + dst[0] = 0; + + dst[1] = 0; + + dst[2] = 0; + + dst[3] = a; +} + +static inline void +unpack_int_a_uint16(const void *void_src, GLuint dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint16_t a = src[0]; + + + dst[0] = 0; + + dst[1] = 0; + + dst[2] = 0; + + dst[3] = a; +} + +static inline void +unpack_int_a_uint32(const void *void_src, GLuint dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint32_t a = src[0]; + + + dst[0] = 0; + + dst[1] = 0; + + dst[2] = 0; + + dst[3] = a; +} + +static inline void +unpack_int_a_sint8(const void *void_src, GLuint dst[4]) +{ + int8_t *src = (int8_t *)void_src; + int8_t a = src[0]; + + + dst[0] = 0; + + dst[1] = 0; + + dst[2] = 0; + + dst[3] = a; +} + +static inline void +unpack_int_a_sint16(const void *void_src, GLuint dst[4]) +{ + int16_t *src = (int16_t *)void_src; + int16_t a = src[0]; + + + dst[0] = 0; + + dst[1] = 0; + + dst[2] = 0; + + dst[3] = a; +} + +static inline void +unpack_int_a_sint32(const void *void_src, GLuint dst[4]) +{ + int32_t *src = (int32_t *)void_src; + int32_t a = src[0]; + + + dst[0] = 0; + + dst[1] = 0; + + dst[2] = 0; + + dst[3] = a; +} + +static inline void +unpack_int_i_uint8(const void *void_src, GLuint dst[4]) +{ + uint8_t *src = (uint8_t *)void_src; + uint8_t i = src[0]; + + + dst[0] = i; + + dst[1] = i; + + dst[2] = i; + + dst[3] = i; +} + +static inline void +unpack_int_i_uint16(const void *void_src, GLuint dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint16_t i = src[0]; + + + dst[0] = i; + + dst[1] = i; + + dst[2] = i; + + dst[3] = i; +} + +static inline void +unpack_int_i_uint32(const void *void_src, GLuint dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint32_t i = src[0]; + + + dst[0] = i; + + dst[1] = i; + + dst[2] = i; + + dst[3] = i; +} + +static inline void +unpack_int_i_sint8(const void *void_src, GLuint dst[4]) +{ + int8_t *src = (int8_t *)void_src; + int8_t i = src[0]; + + + dst[0] = i; + + dst[1] = i; + + dst[2] = i; + + dst[3] = i; +} + +static inline void +unpack_int_i_sint16(const void *void_src, GLuint dst[4]) +{ + int16_t *src = (int16_t *)void_src; + int16_t i = src[0]; + + + dst[0] = i; + + dst[1] = i; + + dst[2] = i; + + dst[3] = i; +} + +static inline void +unpack_int_i_sint32(const void *void_src, GLuint dst[4]) +{ + int32_t *src = (int32_t *)void_src; + int32_t i = src[0]; + + + dst[0] = i; + + dst[1] = i; + + dst[2] = i; + + dst[3] = i; +} + +static inline void +unpack_int_l_uint8(const void *void_src, GLuint dst[4]) +{ + uint8_t *src = (uint8_t *)void_src; + uint8_t l = src[0]; + + + dst[0] = l; + + dst[1] = l; + + dst[2] = l; + + dst[3] = 1; +} + +static inline void +unpack_int_l_uint16(const void *void_src, GLuint dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint16_t l = src[0]; + + + dst[0] = l; + + dst[1] = l; + + dst[2] = l; + + dst[3] = 1; +} + +static inline void +unpack_int_l_uint32(const void *void_src, GLuint dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint32_t l = src[0]; + + + dst[0] = l; + + dst[1] = l; + + dst[2] = l; + + dst[3] = 1; +} + +static inline void +unpack_int_l_sint8(const void *void_src, GLuint dst[4]) +{ + int8_t *src = (int8_t *)void_src; + int8_t l = src[0]; + + + dst[0] = l; + + dst[1] = l; + + dst[2] = l; + + dst[3] = 1; +} + +static inline void +unpack_int_l_sint16(const void *void_src, GLuint dst[4]) +{ + int16_t *src = (int16_t *)void_src; + int16_t l = src[0]; + + + dst[0] = l; + + dst[1] = l; + + dst[2] = l; + + dst[3] = 1; +} + +static inline void +unpack_int_l_sint32(const void *void_src, GLuint dst[4]) +{ + int32_t *src = (int32_t *)void_src; + int32_t l = src[0]; + + + dst[0] = l; + + dst[1] = l; + + dst[2] = l; + + dst[3] = 1; +} + +static inline void +unpack_int_la_uint8(const void *void_src, GLuint dst[4]) +{ + uint8_t *src = (uint8_t *)void_src; + uint8_t l = src[0]; + uint8_t a = src[1]; + + + dst[0] = l; + + dst[1] = l; + + dst[2] = l; + + dst[3] = a; +} + +static inline void +unpack_int_la_uint16(const void *void_src, GLuint dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint16_t l = src[0]; + uint16_t a = src[1]; + + + dst[0] = l; + + dst[1] = l; + + dst[2] = l; + + dst[3] = a; +} + +static inline void +unpack_int_la_uint32(const void *void_src, GLuint dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint32_t l = src[0]; + uint32_t a = src[1]; + + + dst[0] = l; + + dst[1] = l; + + dst[2] = l; + + dst[3] = a; +} + +static inline void +unpack_int_la_sint8(const void *void_src, GLuint dst[4]) +{ + int8_t *src = (int8_t *)void_src; + int8_t l = src[0]; + int8_t a = src[1]; + + + dst[0] = l; + + dst[1] = l; + + dst[2] = l; + + dst[3] = a; +} + +static inline void +unpack_int_la_sint16(const void *void_src, GLuint dst[4]) +{ + int16_t *src = (int16_t *)void_src; + int16_t l = src[0]; + int16_t a = src[1]; + + + dst[0] = l; + + dst[1] = l; + + dst[2] = l; + + dst[3] = a; +} + +static inline void +unpack_int_la_sint32(const void *void_src, GLuint dst[4]) +{ + int32_t *src = (int32_t *)void_src; + int32_t l = src[0]; + int32_t a = src[1]; + + + dst[0] = l; + + dst[1] = l; + + dst[2] = l; + + dst[3] = a; +} + +static inline void +unpack_int_r_uint8(const void *void_src, GLuint dst[4]) +{ + uint8_t *src = (uint8_t *)void_src; + uint8_t r = src[0]; + + + dst[0] = r; + + dst[1] = 0; + + dst[2] = 0; + + dst[3] = 1; +} + +static inline void +unpack_int_r_uint16(const void *void_src, GLuint dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint16_t r = src[0]; + + + dst[0] = r; + + dst[1] = 0; + + dst[2] = 0; + + dst[3] = 1; +} + +static inline void +unpack_int_r_uint32(const void *void_src, GLuint dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint32_t r = src[0]; + + + dst[0] = r; + + dst[1] = 0; + + dst[2] = 0; + + dst[3] = 1; +} + +static inline void +unpack_int_r_sint8(const void *void_src, GLuint dst[4]) +{ + int8_t *src = (int8_t *)void_src; + int8_t r = src[0]; + + + dst[0] = r; + + dst[1] = 0; + + dst[2] = 0; + + dst[3] = 1; +} + +static inline void +unpack_int_r_sint16(const void *void_src, GLuint dst[4]) +{ + int16_t *src = (int16_t *)void_src; + int16_t r = src[0]; + + + dst[0] = r; + + dst[1] = 0; + + dst[2] = 0; + + dst[3] = 1; +} + +static inline void +unpack_int_r_sint32(const void *void_src, GLuint dst[4]) +{ + int32_t *src = (int32_t *)void_src; + int32_t r = src[0]; + + + dst[0] = r; + + dst[1] = 0; + + dst[2] = 0; + + dst[3] = 1; +} + +static inline void +unpack_int_rg_uint8(const void *void_src, GLuint dst[4]) +{ + uint8_t *src = (uint8_t *)void_src; + uint8_t r = src[0]; + uint8_t g = src[1]; + + + dst[0] = r; + + dst[1] = g; + + dst[2] = 0; + + dst[3] = 1; +} + +static inline void +unpack_int_rg_uint16(const void *void_src, GLuint dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint16_t r = src[0]; + uint16_t g = src[1]; + + + dst[0] = r; + + dst[1] = g; + + dst[2] = 0; + + dst[3] = 1; +} + +static inline void +unpack_int_rg_uint32(const void *void_src, GLuint dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint32_t r = src[0]; + uint32_t g = src[1]; + + + dst[0] = r; + + dst[1] = g; + + dst[2] = 0; + + dst[3] = 1; +} + +static inline void +unpack_int_rg_sint8(const void *void_src, GLuint dst[4]) +{ + int8_t *src = (int8_t *)void_src; + int8_t r = src[0]; + int8_t g = src[1]; + + + dst[0] = r; + + dst[1] = g; + + dst[2] = 0; + + dst[3] = 1; +} + +static inline void +unpack_int_rg_sint16(const void *void_src, GLuint dst[4]) +{ + int16_t *src = (int16_t *)void_src; + int16_t r = src[0]; + int16_t g = src[1]; + + + dst[0] = r; + + dst[1] = g; + + dst[2] = 0; + + dst[3] = 1; +} + +static inline void +unpack_int_rg_sint32(const void *void_src, GLuint dst[4]) +{ + int32_t *src = (int32_t *)void_src; + int32_t r = src[0]; + int32_t g = src[1]; + + + dst[0] = r; + + dst[1] = g; + + dst[2] = 0; + + dst[3] = 1; +} + +static inline void +unpack_int_rgb_uint8(const void *void_src, GLuint dst[4]) +{ + uint8_t *src = (uint8_t *)void_src; + uint8_t r = src[0]; + uint8_t g = src[1]; + uint8_t b = src[2]; + + + dst[0] = r; + + dst[1] = g; + + dst[2] = b; + + dst[3] = 1; +} + +static inline void +unpack_int_rgb_uint16(const void *void_src, GLuint dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint16_t r = src[0]; + uint16_t g = src[1]; + uint16_t b = src[2]; + + + dst[0] = r; + + dst[1] = g; + + dst[2] = b; + + dst[3] = 1; +} + +static inline void +unpack_int_rgb_uint32(const void *void_src, GLuint dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint32_t r = src[0]; + uint32_t g = src[1]; + uint32_t b = src[2]; + + + dst[0] = r; + + dst[1] = g; + + dst[2] = b; + + dst[3] = 1; +} + +static inline void +unpack_int_rgb_sint8(const void *void_src, GLuint dst[4]) +{ + int8_t *src = (int8_t *)void_src; + int8_t r = src[0]; + int8_t g = src[1]; + int8_t b = src[2]; + + + dst[0] = r; + + dst[1] = g; + + dst[2] = b; + + dst[3] = 1; +} + +static inline void +unpack_int_rgb_sint16(const void *void_src, GLuint dst[4]) +{ + int16_t *src = (int16_t *)void_src; + int16_t r = src[0]; + int16_t g = src[1]; + int16_t b = src[2]; + + + dst[0] = r; + + dst[1] = g; + + dst[2] = b; + + dst[3] = 1; +} + +static inline void +unpack_int_rgb_sint32(const void *void_src, GLuint dst[4]) +{ + int32_t *src = (int32_t *)void_src; + int32_t r = src[0]; + int32_t g = src[1]; + int32_t b = src[2]; + + + dst[0] = r; + + dst[1] = g; + + dst[2] = b; + + dst[3] = 1; +} + +static inline void +unpack_int_rgba_uint8(const void *void_src, GLuint dst[4]) +{ + uint8_t *src = (uint8_t *)void_src; + uint8_t r = src[0]; + uint8_t g = src[1]; + uint8_t b = src[2]; + uint8_t a = src[3]; + + + dst[0] = r; + + dst[1] = g; + + dst[2] = b; + + dst[3] = a; +} + +static inline void +unpack_int_rgba_uint16(const void *void_src, GLuint dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint16_t r = src[0]; + uint16_t g = src[1]; + uint16_t b = src[2]; + uint16_t a = src[3]; + + + dst[0] = r; + + dst[1] = g; + + dst[2] = b; + + dst[3] = a; +} + +static inline void +unpack_int_rgba_uint32(const void *void_src, GLuint dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint32_t r = src[0]; + uint32_t g = src[1]; + uint32_t b = src[2]; + uint32_t a = src[3]; + + + dst[0] = r; + + dst[1] = g; + + dst[2] = b; + + dst[3] = a; +} + +static inline void +unpack_int_rgba_sint8(const void *void_src, GLuint dst[4]) +{ + int8_t *src = (int8_t *)void_src; + int8_t r = src[0]; + int8_t g = src[1]; + int8_t b = src[2]; + int8_t a = src[3]; + + + dst[0] = r; + + dst[1] = g; + + dst[2] = b; + + dst[3] = a; +} + +static inline void +unpack_int_rgba_sint16(const void *void_src, GLuint dst[4]) +{ + int16_t *src = (int16_t *)void_src; + int16_t r = src[0]; + int16_t g = src[1]; + int16_t b = src[2]; + int16_t a = src[3]; + + + dst[0] = r; + + dst[1] = g; + + dst[2] = b; + + dst[3] = a; +} + +static inline void +unpack_int_rgba_sint32(const void *void_src, GLuint dst[4]) +{ + int32_t *src = (int32_t *)void_src; + int32_t r = src[0]; + int32_t g = src[1]; + int32_t b = src[2]; + int32_t a = src[3]; + + + dst[0] = r; + + dst[1] = g; + + dst[2] = b; + + dst[3] = a; +} + +static inline void +unpack_int_rgbx_uint8(const void *void_src, GLuint dst[4]) +{ + uint8_t *src = (uint8_t *)void_src; + uint8_t r = src[0]; + uint8_t g = src[1]; + uint8_t b = src[2]; + + + dst[0] = r; + + dst[1] = g; + + dst[2] = b; + + dst[3] = 1; +} + +static inline void +unpack_int_rgbx_uint16(const void *void_src, GLuint dst[4]) +{ + uint16_t *src = (uint16_t *)void_src; + uint16_t r = src[0]; + uint16_t g = src[1]; + uint16_t b = src[2]; + + + dst[0] = r; + + dst[1] = g; + + dst[2] = b; + + dst[3] = 1; +} + +static inline void +unpack_int_rgbx_uint32(const void *void_src, GLuint dst[4]) +{ + uint32_t *src = (uint32_t *)void_src; + uint32_t r = src[0]; + uint32_t g = src[1]; + uint32_t b = src[2]; + + + dst[0] = r; + + dst[1] = g; + + dst[2] = b; + + dst[3] = 1; +} + +static inline void +unpack_int_rgbx_sint8(const void *void_src, GLuint dst[4]) +{ + int8_t *src = (int8_t *)void_src; + int8_t r = src[0]; + int8_t g = src[1]; + int8_t b = src[2]; + + + dst[0] = r; + + dst[1] = g; + + dst[2] = b; + + dst[3] = 1; +} + +static inline void +unpack_int_rgbx_sint16(const void *void_src, GLuint dst[4]) +{ + int16_t *src = (int16_t *)void_src; + int16_t r = src[0]; + int16_t g = src[1]; + int16_t b = src[2]; + + + dst[0] = r; + + dst[1] = g; + + dst[2] = b; + + dst[3] = 1; +} + +static inline void +unpack_int_rgbx_sint32(const void *void_src, GLuint dst[4]) +{ + int32_t *src = (int32_t *)void_src; + int32_t r = src[0]; + int32_t g = src[1]; + int32_t b = src[2]; + + + dst[0] = r; + + dst[1] = g; + + dst[2] = b; + + dst[3] = 1; +} + + +void +_mesa_unpack_rgba_row(mesa_format format, GLuint n, + const void *src, GLfloat dst[][4]) +{ + GLubyte *s = (GLubyte *)src; + GLuint i; + + switch (format) { + case MESA_FORMAT_A8B8G8R8_UNORM: + for (i = 0; i < n; ++i) { + unpack_float_a8b8g8r8_unorm(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_X8B8G8R8_UNORM: + for (i = 0; i < n; ++i) { + unpack_float_x8b8g8r8_unorm(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_R8G8B8A8_UNORM: + for (i = 0; i < n; ++i) { + unpack_float_r8g8b8a8_unorm(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_R8G8B8X8_UNORM: + for (i = 0; i < n; ++i) { + unpack_float_r8g8b8x8_unorm(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_B8G8R8A8_UNORM: + for (i = 0; i < n; ++i) { + unpack_float_b8g8r8a8_unorm(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_B8G8R8X8_UNORM: + for (i = 0; i < n; ++i) { + unpack_float_b8g8r8x8_unorm(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_A8R8G8B8_UNORM: + for (i = 0; i < n; ++i) { + unpack_float_a8r8g8b8_unorm(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_X8R8G8B8_UNORM: + for (i = 0; i < n; ++i) { + unpack_float_x8r8g8b8_unorm(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_L16A16_UNORM: + for (i = 0; i < n; ++i) { + unpack_float_l16a16_unorm(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_A16L16_UNORM: + for (i = 0; i < n; ++i) { + unpack_float_a16l16_unorm(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_B5G6R5_UNORM: + for (i = 0; i < n; ++i) { + unpack_float_b5g6r5_unorm(s, dst[i]); + s += 2; + } + break; + case MESA_FORMAT_R5G6B5_UNORM: + for (i = 0; i < n; ++i) { + unpack_float_r5g6b5_unorm(s, dst[i]); + s += 2; + } + break; + case MESA_FORMAT_B4G4R4A4_UNORM: + for (i = 0; i < n; ++i) { + unpack_float_b4g4r4a4_unorm(s, dst[i]); + s += 2; + } + break; + case MESA_FORMAT_B4G4R4X4_UNORM: + for (i = 0; i < n; ++i) { + unpack_float_b4g4r4x4_unorm(s, dst[i]); + s += 2; + } + break; + case MESA_FORMAT_A4R4G4B4_UNORM: + for (i = 0; i < n; ++i) { + unpack_float_a4r4g4b4_unorm(s, dst[i]); + s += 2; + } + break; + case MESA_FORMAT_A1B5G5R5_UNORM: + for (i = 0; i < n; ++i) { + unpack_float_a1b5g5r5_unorm(s, dst[i]); + s += 2; + } + break; + case MESA_FORMAT_X1B5G5R5_UNORM: + for (i = 0; i < n; ++i) { + unpack_float_x1b5g5r5_unorm(s, dst[i]); + s += 2; + } + break; + case MESA_FORMAT_B5G5R5A1_UNORM: + for (i = 0; i < n; ++i) { + unpack_float_b5g5r5a1_unorm(s, dst[i]); + s += 2; + } + break; + case MESA_FORMAT_B5G5R5X1_UNORM: + for (i = 0; i < n; ++i) { + unpack_float_b5g5r5x1_unorm(s, dst[i]); + s += 2; + } + break; + case MESA_FORMAT_A1R5G5B5_UNORM: + for (i = 0; i < n; ++i) { + unpack_float_a1r5g5b5_unorm(s, dst[i]); + s += 2; + } + break; + case MESA_FORMAT_L8A8_UNORM: + for (i = 0; i < n; ++i) { + unpack_float_l8a8_unorm(s, dst[i]); + s += 2; + } + break; + case MESA_FORMAT_A8L8_UNORM: + for (i = 0; i < n; ++i) { + unpack_float_a8l8_unorm(s, dst[i]); + s += 2; + } + break; + case MESA_FORMAT_R8G8_UNORM: + for (i = 0; i < n; ++i) { + unpack_float_r8g8_unorm(s, dst[i]); + s += 2; + } + break; + case MESA_FORMAT_G8R8_UNORM: + for (i = 0; i < n; ++i) { + unpack_float_g8r8_unorm(s, dst[i]); + s += 2; + } + break; + case MESA_FORMAT_L4A4_UNORM: + for (i = 0; i < n; ++i) { + unpack_float_l4a4_unorm(s, dst[i]); + s += 1; + } + break; + case MESA_FORMAT_B2G3R3_UNORM: + for (i = 0; i < n; ++i) { + unpack_float_b2g3r3_unorm(s, dst[i]); + s += 1; + } + break; + case MESA_FORMAT_R16G16_UNORM: + for (i = 0; i < n; ++i) { + unpack_float_r16g16_unorm(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_G16R16_UNORM: + for (i = 0; i < n; ++i) { + unpack_float_g16r16_unorm(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_B10G10R10A2_UNORM: + for (i = 0; i < n; ++i) { + unpack_float_b10g10r10a2_unorm(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_B10G10R10X2_UNORM: + for (i = 0; i < n; ++i) { + unpack_float_b10g10r10x2_unorm(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_R10G10B10A2_UNORM: + for (i = 0; i < n; ++i) { + unpack_float_r10g10b10a2_unorm(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_R10G10B10X2_UNORM: + for (i = 0; i < n; ++i) { + unpack_float_r10g10b10x2_unorm(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_R3G3B2_UNORM: + for (i = 0; i < n; ++i) { + unpack_float_r3g3b2_unorm(s, dst[i]); + s += 1; + } + break; + case MESA_FORMAT_A4B4G4R4_UNORM: + for (i = 0; i < n; ++i) { + unpack_float_a4b4g4r4_unorm(s, dst[i]); + s += 2; + } + break; + case MESA_FORMAT_R4G4B4A4_UNORM: + for (i = 0; i < n; ++i) { + unpack_float_r4g4b4a4_unorm(s, dst[i]); + s += 2; + } + break; + case MESA_FORMAT_R5G5B5A1_UNORM: + for (i = 0; i < n; ++i) { + unpack_float_r5g5b5a1_unorm(s, dst[i]); + s += 2; + } + break; + case MESA_FORMAT_A2B10G10R10_UNORM: + for (i = 0; i < n; ++i) { + unpack_float_a2b10g10r10_unorm(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_A2R10G10B10_UNORM: + for (i = 0; i < n; ++i) { + unpack_float_a2r10g10b10_unorm(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_A_UNORM8: + for (i = 0; i < n; ++i) { + unpack_float_a_unorm8(s, dst[i]); + s += 1; + } + break; + case MESA_FORMAT_A_UNORM16: + for (i = 0; i < n; ++i) { + unpack_float_a_unorm16(s, dst[i]); + s += 2; + } + break; + case MESA_FORMAT_L_UNORM8: + for (i = 0; i < n; ++i) { + unpack_float_l_unorm8(s, dst[i]); + s += 1; + } + break; + case MESA_FORMAT_L_UNORM16: + for (i = 0; i < n; ++i) { + unpack_float_l_unorm16(s, dst[i]); + s += 2; + } + break; + case MESA_FORMAT_I_UNORM8: + for (i = 0; i < n; ++i) { + unpack_float_i_unorm8(s, dst[i]); + s += 1; + } + break; + case MESA_FORMAT_I_UNORM16: + for (i = 0; i < n; ++i) { + unpack_float_i_unorm16(s, dst[i]); + s += 2; + } + break; + case MESA_FORMAT_R_UNORM8: + for (i = 0; i < n; ++i) { + unpack_float_r_unorm8(s, dst[i]); + s += 1; + } + break; + case MESA_FORMAT_R_UNORM16: + for (i = 0; i < n; ++i) { + unpack_float_r_unorm16(s, dst[i]); + s += 2; + } + break; + case MESA_FORMAT_BGR_UNORM8: + for (i = 0; i < n; ++i) { + unpack_float_bgr_unorm8(s, dst[i]); + s += 3; + } + break; + case MESA_FORMAT_RGB_UNORM8: + for (i = 0; i < n; ++i) { + unpack_float_rgb_unorm8(s, dst[i]); + s += 3; + } + break; + case MESA_FORMAT_RGBA_UNORM16: + for (i = 0; i < n; ++i) { + unpack_float_rgba_unorm16(s, dst[i]); + s += 8; + } + break; + case MESA_FORMAT_RGBX_UNORM16: + for (i = 0; i < n; ++i) { + unpack_float_rgbx_unorm16(s, dst[i]); + s += 8; + } + break; + case MESA_FORMAT_A8B8G8R8_SNORM: + for (i = 0; i < n; ++i) { + unpack_float_a8b8g8r8_snorm(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_X8B8G8R8_SNORM: + for (i = 0; i < n; ++i) { + unpack_float_x8b8g8r8_snorm(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_R8G8B8A8_SNORM: + for (i = 0; i < n; ++i) { + unpack_float_r8g8b8a8_snorm(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_R8G8B8X8_SNORM: + for (i = 0; i < n; ++i) { + unpack_float_r8g8b8x8_snorm(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_R16G16_SNORM: + for (i = 0; i < n; ++i) { + unpack_float_r16g16_snorm(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_G16R16_SNORM: + for (i = 0; i < n; ++i) { + unpack_float_g16r16_snorm(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_R8G8_SNORM: + for (i = 0; i < n; ++i) { + unpack_float_r8g8_snorm(s, dst[i]); + s += 2; + } + break; + case MESA_FORMAT_G8R8_SNORM: + for (i = 0; i < n; ++i) { + unpack_float_g8r8_snorm(s, dst[i]); + s += 2; + } + break; + case MESA_FORMAT_L8A8_SNORM: + for (i = 0; i < n; ++i) { + unpack_float_l8a8_snorm(s, dst[i]); + s += 2; + } + break; + case MESA_FORMAT_A8L8_SNORM: + for (i = 0; i < n; ++i) { + unpack_float_a8l8_snorm(s, dst[i]); + s += 2; + } + break; + case MESA_FORMAT_A_SNORM8: + for (i = 0; i < n; ++i) { + unpack_float_a_snorm8(s, dst[i]); + s += 1; + } + break; + case MESA_FORMAT_A_SNORM16: + for (i = 0; i < n; ++i) { + unpack_float_a_snorm16(s, dst[i]); + s += 2; + } + break; + case MESA_FORMAT_L_SNORM8: + for (i = 0; i < n; ++i) { + unpack_float_l_snorm8(s, dst[i]); + s += 1; + } + break; + case MESA_FORMAT_L_SNORM16: + for (i = 0; i < n; ++i) { + unpack_float_l_snorm16(s, dst[i]); + s += 2; + } + break; + case MESA_FORMAT_I_SNORM8: + for (i = 0; i < n; ++i) { + unpack_float_i_snorm8(s, dst[i]); + s += 1; + } + break; + case MESA_FORMAT_I_SNORM16: + for (i = 0; i < n; ++i) { + unpack_float_i_snorm16(s, dst[i]); + s += 2; + } + break; + case MESA_FORMAT_R_SNORM8: + for (i = 0; i < n; ++i) { + unpack_float_r_snorm8(s, dst[i]); + s += 1; + } + break; + case MESA_FORMAT_R_SNORM16: + for (i = 0; i < n; ++i) { + unpack_float_r_snorm16(s, dst[i]); + s += 2; + } + break; + case MESA_FORMAT_LA_SNORM16: + for (i = 0; i < n; ++i) { + unpack_float_la_snorm16(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_RGB_SNORM16: + for (i = 0; i < n; ++i) { + unpack_float_rgb_snorm16(s, dst[i]); + s += 6; + } + break; + case MESA_FORMAT_RGBA_SNORM16: + for (i = 0; i < n; ++i) { + unpack_float_rgba_snorm16(s, dst[i]); + s += 8; + } + break; + case MESA_FORMAT_RGBX_SNORM16: + for (i = 0; i < n; ++i) { + unpack_float_rgbx_snorm16(s, dst[i]); + s += 8; + } + break; + case MESA_FORMAT_A8B8G8R8_SRGB: + for (i = 0; i < n; ++i) { + unpack_float_a8b8g8r8_srgb(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_B8G8R8A8_SRGB: + for (i = 0; i < n; ++i) { + unpack_float_b8g8r8a8_srgb(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_A8R8G8B8_SRGB: + for (i = 0; i < n; ++i) { + unpack_float_a8r8g8b8_srgb(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_B8G8R8X8_SRGB: + for (i = 0; i < n; ++i) { + unpack_float_b8g8r8x8_srgb(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_X8R8G8B8_SRGB: + for (i = 0; i < n; ++i) { + unpack_float_x8r8g8b8_srgb(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_R8G8B8A8_SRGB: + for (i = 0; i < n; ++i) { + unpack_float_r8g8b8a8_srgb(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_R8G8B8X8_SRGB: + for (i = 0; i < n; ++i) { + unpack_float_r8g8b8x8_srgb(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_X8B8G8R8_SRGB: + for (i = 0; i < n; ++i) { + unpack_float_x8b8g8r8_srgb(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_L8A8_SRGB: + for (i = 0; i < n; ++i) { + unpack_float_l8a8_srgb(s, dst[i]); + s += 2; + } + break; + case MESA_FORMAT_A8L8_SRGB: + for (i = 0; i < n; ++i) { + unpack_float_a8l8_srgb(s, dst[i]); + s += 2; + } + break; + case MESA_FORMAT_R_SRGB8: + for (i = 0; i < n; ++i) { + unpack_float_r_srgb8(s, dst[i]); + s += 1; + } + break; + case MESA_FORMAT_L_SRGB8: + for (i = 0; i < n; ++i) { + unpack_float_l_srgb8(s, dst[i]); + s += 1; + } + break; + case MESA_FORMAT_BGR_SRGB8: + for (i = 0; i < n; ++i) { + unpack_float_bgr_srgb8(s, dst[i]); + s += 3; + } + break; + case MESA_FORMAT_R9G9B9E5_FLOAT: + for (i = 0; i < n; ++i) { + unpack_float_r9g9b9e5_float(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_R11G11B10_FLOAT: + for (i = 0; i < n; ++i) { + unpack_float_r11g11b10_float(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_A_FLOAT16: + for (i = 0; i < n; ++i) { + unpack_float_a_float16(s, dst[i]); + s += 2; + } + break; + case MESA_FORMAT_A_FLOAT32: + for (i = 0; i < n; ++i) { + unpack_float_a_float32(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_L_FLOAT16: + for (i = 0; i < n; ++i) { + unpack_float_l_float16(s, dst[i]); + s += 2; + } + break; + case MESA_FORMAT_L_FLOAT32: + for (i = 0; i < n; ++i) { + unpack_float_l_float32(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_LA_FLOAT16: + for (i = 0; i < n; ++i) { + unpack_float_la_float16(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_LA_FLOAT32: + for (i = 0; i < n; ++i) { + unpack_float_la_float32(s, dst[i]); + s += 8; + } + break; + case MESA_FORMAT_I_FLOAT16: + for (i = 0; i < n; ++i) { + unpack_float_i_float16(s, dst[i]); + s += 2; + } + break; + case MESA_FORMAT_I_FLOAT32: + for (i = 0; i < n; ++i) { + unpack_float_i_float32(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_R_FLOAT16: + for (i = 0; i < n; ++i) { + unpack_float_r_float16(s, dst[i]); + s += 2; + } + break; + case MESA_FORMAT_R_FLOAT32: + for (i = 0; i < n; ++i) { + unpack_float_r_float32(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_RG_FLOAT16: + for (i = 0; i < n; ++i) { + unpack_float_rg_float16(s, dst[i]); + s += 4; + } + break; + case MESA_FORMAT_RG_FLOAT32: + for (i = 0; i < n; ++i) { + unpack_float_rg_float32(s, dst[i]); + s += 8; + } + break; + case MESA_FORMAT_RGB_FLOAT16: + for (i = 0; i < n; ++i) { + unpack_float_rgb_float16(s, dst[i]); + s += 6; + } + break; + case MESA_FORMAT_RGB_FLOAT32: + for (i = 0; i < n; ++i) { + unpack_float_rgb_float32(s, dst[i]); + s += 12; + } + break; + case MESA_FORMAT_RGBA_FLOAT16: + for (i = 0; i < n; ++i) { + unpack_float_rgba_float16(s, dst[i]); + s += 8; + } + break; + case MESA_FORMAT_RGBA_FLOAT32: + for (i = 0; i < n; ++i) { + unpack_float_rgba_float32(s, dst[i]); + s += 16; + } + break; + case MESA_FORMAT_RGBX_FLOAT16: + for (i = 0; i < n; ++i) { + unpack_float_rgbx_float16(s, dst[i]); + s += 8; + } + break; + case MESA_FORMAT_RGBX_FLOAT32: + for (i = 0; i < n; ++i) { + unpack_float_rgbx_float32(s, dst[i]); + s += 16; + } + break; + case MESA_FORMAT_YCBCR: + unpack_float_ycbcr(src, dst, n); + break; + case MESA_FORMAT_YCBCR_REV: + unpack_float_ycbcr_rev(src, dst, n); + break; + default: + _mesa_problem(NULL, "%s: bad format %s", __func__, + _mesa_get_format_name(format)); + return; + } +} + +void +_mesa_unpack_ubyte_rgba_row(mesa_format format, GLuint n, + const void *src, GLubyte dst[][4]) +{ + GLubyte *s = (GLubyte *)src; + GLuint i; + + switch (format) { + + case MESA_FORMAT_A8B8G8R8_UNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_a8b8g8r8_unorm(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_X8B8G8R8_UNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_x8b8g8r8_unorm(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_R8G8B8A8_UNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_r8g8b8a8_unorm(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_R8G8B8X8_UNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_r8g8b8x8_unorm(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_B8G8R8A8_UNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_b8g8r8a8_unorm(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_B8G8R8X8_UNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_b8g8r8x8_unorm(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_A8R8G8B8_UNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_a8r8g8b8_unorm(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_X8R8G8B8_UNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_x8r8g8b8_unorm(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_L16A16_UNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_l16a16_unorm(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_A16L16_UNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_a16l16_unorm(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_B5G6R5_UNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_b5g6r5_unorm(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_R5G6B5_UNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_r5g6b5_unorm(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_B4G4R4A4_UNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_b4g4r4a4_unorm(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_B4G4R4X4_UNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_b4g4r4x4_unorm(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_A4R4G4B4_UNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_a4r4g4b4_unorm(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_A1B5G5R5_UNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_a1b5g5r5_unorm(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_X1B5G5R5_UNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_x1b5g5r5_unorm(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_B5G5R5A1_UNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_b5g5r5a1_unorm(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_B5G5R5X1_UNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_b5g5r5x1_unorm(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_A1R5G5B5_UNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_a1r5g5b5_unorm(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_L8A8_UNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_l8a8_unorm(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_A8L8_UNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_a8l8_unorm(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_R8G8_UNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_r8g8_unorm(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_G8R8_UNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_g8r8_unorm(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_L4A4_UNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_l4a4_unorm(s, dst[i]); + s += 1; + } + break; + + case MESA_FORMAT_B2G3R3_UNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_b2g3r3_unorm(s, dst[i]); + s += 1; + } + break; + + case MESA_FORMAT_R16G16_UNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_r16g16_unorm(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_G16R16_UNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_g16r16_unorm(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_B10G10R10A2_UNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_b10g10r10a2_unorm(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_B10G10R10X2_UNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_b10g10r10x2_unorm(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_R10G10B10A2_UNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_r10g10b10a2_unorm(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_R10G10B10X2_UNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_r10g10b10x2_unorm(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_R3G3B2_UNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_r3g3b2_unorm(s, dst[i]); + s += 1; + } + break; + + case MESA_FORMAT_A4B4G4R4_UNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_a4b4g4r4_unorm(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_R4G4B4A4_UNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_r4g4b4a4_unorm(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_R5G5B5A1_UNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_r5g5b5a1_unorm(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_A2B10G10R10_UNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_a2b10g10r10_unorm(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_A2R10G10B10_UNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_a2r10g10b10_unorm(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_A_UNORM8: + for (i = 0; i < n; ++i) { + unpack_ubyte_a_unorm8(s, dst[i]); + s += 1; + } + break; + + case MESA_FORMAT_A_UNORM16: + for (i = 0; i < n; ++i) { + unpack_ubyte_a_unorm16(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_L_UNORM8: + for (i = 0; i < n; ++i) { + unpack_ubyte_l_unorm8(s, dst[i]); + s += 1; + } + break; + + case MESA_FORMAT_L_UNORM16: + for (i = 0; i < n; ++i) { + unpack_ubyte_l_unorm16(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_I_UNORM8: + for (i = 0; i < n; ++i) { + unpack_ubyte_i_unorm8(s, dst[i]); + s += 1; + } + break; + + case MESA_FORMAT_I_UNORM16: + for (i = 0; i < n; ++i) { + unpack_ubyte_i_unorm16(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_R_UNORM8: + for (i = 0; i < n; ++i) { + unpack_ubyte_r_unorm8(s, dst[i]); + s += 1; + } + break; + + case MESA_FORMAT_R_UNORM16: + for (i = 0; i < n; ++i) { + unpack_ubyte_r_unorm16(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_BGR_UNORM8: + for (i = 0; i < n; ++i) { + unpack_ubyte_bgr_unorm8(s, dst[i]); + s += 3; + } + break; + + case MESA_FORMAT_RGB_UNORM8: + for (i = 0; i < n; ++i) { + unpack_ubyte_rgb_unorm8(s, dst[i]); + s += 3; + } + break; + + case MESA_FORMAT_RGBA_UNORM16: + for (i = 0; i < n; ++i) { + unpack_ubyte_rgba_unorm16(s, dst[i]); + s += 8; + } + break; + + case MESA_FORMAT_RGBX_UNORM16: + for (i = 0; i < n; ++i) { + unpack_ubyte_rgbx_unorm16(s, dst[i]); + s += 8; + } + break; + + case MESA_FORMAT_A8B8G8R8_SNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_a8b8g8r8_snorm(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_X8B8G8R8_SNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_x8b8g8r8_snorm(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_R8G8B8A8_SNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_r8g8b8a8_snorm(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_R8G8B8X8_SNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_r8g8b8x8_snorm(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_R16G16_SNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_r16g16_snorm(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_G16R16_SNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_g16r16_snorm(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_R8G8_SNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_r8g8_snorm(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_G8R8_SNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_g8r8_snorm(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_L8A8_SNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_l8a8_snorm(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_A8L8_SNORM: + for (i = 0; i < n; ++i) { + unpack_ubyte_a8l8_snorm(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_A_SNORM8: + for (i = 0; i < n; ++i) { + unpack_ubyte_a_snorm8(s, dst[i]); + s += 1; + } + break; + + case MESA_FORMAT_A_SNORM16: + for (i = 0; i < n; ++i) { + unpack_ubyte_a_snorm16(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_L_SNORM8: + for (i = 0; i < n; ++i) { + unpack_ubyte_l_snorm8(s, dst[i]); + s += 1; + } + break; + + case MESA_FORMAT_L_SNORM16: + for (i = 0; i < n; ++i) { + unpack_ubyte_l_snorm16(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_I_SNORM8: + for (i = 0; i < n; ++i) { + unpack_ubyte_i_snorm8(s, dst[i]); + s += 1; + } + break; + + case MESA_FORMAT_I_SNORM16: + for (i = 0; i < n; ++i) { + unpack_ubyte_i_snorm16(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_R_SNORM8: + for (i = 0; i < n; ++i) { + unpack_ubyte_r_snorm8(s, dst[i]); + s += 1; + } + break; + + case MESA_FORMAT_R_SNORM16: + for (i = 0; i < n; ++i) { + unpack_ubyte_r_snorm16(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_LA_SNORM16: + for (i = 0; i < n; ++i) { + unpack_ubyte_la_snorm16(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_RGB_SNORM16: + for (i = 0; i < n; ++i) { + unpack_ubyte_rgb_snorm16(s, dst[i]); + s += 6; + } + break; + + case MESA_FORMAT_RGBA_SNORM16: + for (i = 0; i < n; ++i) { + unpack_ubyte_rgba_snorm16(s, dst[i]); + s += 8; + } + break; + + case MESA_FORMAT_RGBX_SNORM16: + for (i = 0; i < n; ++i) { + unpack_ubyte_rgbx_snorm16(s, dst[i]); + s += 8; + } + break; + + case MESA_FORMAT_A8B8G8R8_SRGB: + for (i = 0; i < n; ++i) { + unpack_ubyte_a8b8g8r8_srgb(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_B8G8R8A8_SRGB: + for (i = 0; i < n; ++i) { + unpack_ubyte_b8g8r8a8_srgb(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_A8R8G8B8_SRGB: + for (i = 0; i < n; ++i) { + unpack_ubyte_a8r8g8b8_srgb(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_B8G8R8X8_SRGB: + for (i = 0; i < n; ++i) { + unpack_ubyte_b8g8r8x8_srgb(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_X8R8G8B8_SRGB: + for (i = 0; i < n; ++i) { + unpack_ubyte_x8r8g8b8_srgb(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_R8G8B8A8_SRGB: + for (i = 0; i < n; ++i) { + unpack_ubyte_r8g8b8a8_srgb(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_R8G8B8X8_SRGB: + for (i = 0; i < n; ++i) { + unpack_ubyte_r8g8b8x8_srgb(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_X8B8G8R8_SRGB: + for (i = 0; i < n; ++i) { + unpack_ubyte_x8b8g8r8_srgb(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_L8A8_SRGB: + for (i = 0; i < n; ++i) { + unpack_ubyte_l8a8_srgb(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_A8L8_SRGB: + for (i = 0; i < n; ++i) { + unpack_ubyte_a8l8_srgb(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_R_SRGB8: + for (i = 0; i < n; ++i) { + unpack_ubyte_r_srgb8(s, dst[i]); + s += 1; + } + break; + + case MESA_FORMAT_L_SRGB8: + for (i = 0; i < n; ++i) { + unpack_ubyte_l_srgb8(s, dst[i]); + s += 1; + } + break; + + case MESA_FORMAT_BGR_SRGB8: + for (i = 0; i < n; ++i) { + unpack_ubyte_bgr_srgb8(s, dst[i]); + s += 3; + } + break; + default: + /* get float values, convert to ubyte */ + { + GLfloat *tmp = malloc(n * 4 * sizeof(GLfloat)); + if (tmp) { + GLuint i; + _mesa_unpack_rgba_row(format, n, src, (GLfloat (*)[4]) tmp); + for (i = 0; i < n; i++) { + dst[i][0] = _mesa_float_to_unorm(tmp[i*4+0], 8); + dst[i][1] = _mesa_float_to_unorm(tmp[i*4+1], 8); + dst[i][2] = _mesa_float_to_unorm(tmp[i*4+2], 8); + dst[i][3] = _mesa_float_to_unorm(tmp[i*4+3], 8); + } + free(tmp); + } + } + break; + } +} + +void +_mesa_unpack_uint_rgba_row(mesa_format format, GLuint n, + const void *src, GLuint dst[][4]) +{ + GLubyte *s = (GLubyte *)src; + GLuint i; + + switch (format) { + + case MESA_FORMAT_A8B8G8R8_UINT: + for (i = 0; i < n; ++i) { + unpack_int_a8b8g8r8_uint(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_A8R8G8B8_UINT: + for (i = 0; i < n; ++i) { + unpack_int_a8r8g8b8_uint(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_R8G8B8A8_UINT: + for (i = 0; i < n; ++i) { + unpack_int_r8g8b8a8_uint(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_B8G8R8A8_UINT: + for (i = 0; i < n; ++i) { + unpack_int_b8g8r8a8_uint(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_B10G10R10A2_UINT: + for (i = 0; i < n; ++i) { + unpack_int_b10g10r10a2_uint(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_R10G10B10A2_UINT: + for (i = 0; i < n; ++i) { + unpack_int_r10g10b10a2_uint(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_A2B10G10R10_UINT: + for (i = 0; i < n; ++i) { + unpack_int_a2b10g10r10_uint(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_A2R10G10B10_UINT: + for (i = 0; i < n; ++i) { + unpack_int_a2r10g10b10_uint(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_B5G6R5_UINT: + for (i = 0; i < n; ++i) { + unpack_int_b5g6r5_uint(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_R5G6B5_UINT: + for (i = 0; i < n; ++i) { + unpack_int_r5g6b5_uint(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_B2G3R3_UINT: + for (i = 0; i < n; ++i) { + unpack_int_b2g3r3_uint(s, dst[i]); + s += 1; + } + break; + + case MESA_FORMAT_R3G3B2_UINT: + for (i = 0; i < n; ++i) { + unpack_int_r3g3b2_uint(s, dst[i]); + s += 1; + } + break; + + case MESA_FORMAT_A4B4G4R4_UINT: + for (i = 0; i < n; ++i) { + unpack_int_a4b4g4r4_uint(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_R4G4B4A4_UINT: + for (i = 0; i < n; ++i) { + unpack_int_r4g4b4a4_uint(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_B4G4R4A4_UINT: + for (i = 0; i < n; ++i) { + unpack_int_b4g4r4a4_uint(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_A4R4G4B4_UINT: + for (i = 0; i < n; ++i) { + unpack_int_a4r4g4b4_uint(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_A1B5G5R5_UINT: + for (i = 0; i < n; ++i) { + unpack_int_a1b5g5r5_uint(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_B5G5R5A1_UINT: + for (i = 0; i < n; ++i) { + unpack_int_b5g5r5a1_uint(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_A1R5G5B5_UINT: + for (i = 0; i < n; ++i) { + unpack_int_a1r5g5b5_uint(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_R5G5B5A1_UINT: + for (i = 0; i < n; ++i) { + unpack_int_r5g5b5a1_uint(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_A_UINT8: + for (i = 0; i < n; ++i) { + unpack_int_a_uint8(s, dst[i]); + s += 1; + } + break; + + case MESA_FORMAT_A_UINT16: + for (i = 0; i < n; ++i) { + unpack_int_a_uint16(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_A_UINT32: + for (i = 0; i < n; ++i) { + unpack_int_a_uint32(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_A_SINT8: + for (i = 0; i < n; ++i) { + unpack_int_a_sint8(s, dst[i]); + s += 1; + } + break; + + case MESA_FORMAT_A_SINT16: + for (i = 0; i < n; ++i) { + unpack_int_a_sint16(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_A_SINT32: + for (i = 0; i < n; ++i) { + unpack_int_a_sint32(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_I_UINT8: + for (i = 0; i < n; ++i) { + unpack_int_i_uint8(s, dst[i]); + s += 1; + } + break; + + case MESA_FORMAT_I_UINT16: + for (i = 0; i < n; ++i) { + unpack_int_i_uint16(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_I_UINT32: + for (i = 0; i < n; ++i) { + unpack_int_i_uint32(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_I_SINT8: + for (i = 0; i < n; ++i) { + unpack_int_i_sint8(s, dst[i]); + s += 1; + } + break; + + case MESA_FORMAT_I_SINT16: + for (i = 0; i < n; ++i) { + unpack_int_i_sint16(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_I_SINT32: + for (i = 0; i < n; ++i) { + unpack_int_i_sint32(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_L_UINT8: + for (i = 0; i < n; ++i) { + unpack_int_l_uint8(s, dst[i]); + s += 1; + } + break; + + case MESA_FORMAT_L_UINT16: + for (i = 0; i < n; ++i) { + unpack_int_l_uint16(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_L_UINT32: + for (i = 0; i < n; ++i) { + unpack_int_l_uint32(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_L_SINT8: + for (i = 0; i < n; ++i) { + unpack_int_l_sint8(s, dst[i]); + s += 1; + } + break; + + case MESA_FORMAT_L_SINT16: + for (i = 0; i < n; ++i) { + unpack_int_l_sint16(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_L_SINT32: + for (i = 0; i < n; ++i) { + unpack_int_l_sint32(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_LA_UINT8: + for (i = 0; i < n; ++i) { + unpack_int_la_uint8(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_LA_UINT16: + for (i = 0; i < n; ++i) { + unpack_int_la_uint16(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_LA_UINT32: + for (i = 0; i < n; ++i) { + unpack_int_la_uint32(s, dst[i]); + s += 8; + } + break; + + case MESA_FORMAT_LA_SINT8: + for (i = 0; i < n; ++i) { + unpack_int_la_sint8(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_LA_SINT16: + for (i = 0; i < n; ++i) { + unpack_int_la_sint16(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_LA_SINT32: + for (i = 0; i < n; ++i) { + unpack_int_la_sint32(s, dst[i]); + s += 8; + } + break; + + case MESA_FORMAT_R_UINT8: + for (i = 0; i < n; ++i) { + unpack_int_r_uint8(s, dst[i]); + s += 1; + } + break; + + case MESA_FORMAT_R_UINT16: + for (i = 0; i < n; ++i) { + unpack_int_r_uint16(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_R_UINT32: + for (i = 0; i < n; ++i) { + unpack_int_r_uint32(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_R_SINT8: + for (i = 0; i < n; ++i) { + unpack_int_r_sint8(s, dst[i]); + s += 1; + } + break; + + case MESA_FORMAT_R_SINT16: + for (i = 0; i < n; ++i) { + unpack_int_r_sint16(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_R_SINT32: + for (i = 0; i < n; ++i) { + unpack_int_r_sint32(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_RG_UINT8: + for (i = 0; i < n; ++i) { + unpack_int_rg_uint8(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_RG_UINT16: + for (i = 0; i < n; ++i) { + unpack_int_rg_uint16(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_RG_UINT32: + for (i = 0; i < n; ++i) { + unpack_int_rg_uint32(s, dst[i]); + s += 8; + } + break; + + case MESA_FORMAT_RG_SINT8: + for (i = 0; i < n; ++i) { + unpack_int_rg_sint8(s, dst[i]); + s += 2; + } + break; + + case MESA_FORMAT_RG_SINT16: + for (i = 0; i < n; ++i) { + unpack_int_rg_sint16(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_RG_SINT32: + for (i = 0; i < n; ++i) { + unpack_int_rg_sint32(s, dst[i]); + s += 8; + } + break; + + case MESA_FORMAT_RGB_UINT8: + for (i = 0; i < n; ++i) { + unpack_int_rgb_uint8(s, dst[i]); + s += 3; + } + break; + + case MESA_FORMAT_RGB_UINT16: + for (i = 0; i < n; ++i) { + unpack_int_rgb_uint16(s, dst[i]); + s += 6; + } + break; + + case MESA_FORMAT_RGB_UINT32: + for (i = 0; i < n; ++i) { + unpack_int_rgb_uint32(s, dst[i]); + s += 12; + } + break; + + case MESA_FORMAT_RGB_SINT8: + for (i = 0; i < n; ++i) { + unpack_int_rgb_sint8(s, dst[i]); + s += 3; + } + break; + + case MESA_FORMAT_RGB_SINT16: + for (i = 0; i < n; ++i) { + unpack_int_rgb_sint16(s, dst[i]); + s += 6; + } + break; + + case MESA_FORMAT_RGB_SINT32: + for (i = 0; i < n; ++i) { + unpack_int_rgb_sint32(s, dst[i]); + s += 12; + } + break; + + case MESA_FORMAT_RGBA_UINT8: + for (i = 0; i < n; ++i) { + unpack_int_rgba_uint8(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_RGBA_UINT16: + for (i = 0; i < n; ++i) { + unpack_int_rgba_uint16(s, dst[i]); + s += 8; + } + break; + + case MESA_FORMAT_RGBA_UINT32: + for (i = 0; i < n; ++i) { + unpack_int_rgba_uint32(s, dst[i]); + s += 16; + } + break; + + case MESA_FORMAT_RGBA_SINT8: + for (i = 0; i < n; ++i) { + unpack_int_rgba_sint8(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_RGBA_SINT16: + for (i = 0; i < n; ++i) { + unpack_int_rgba_sint16(s, dst[i]); + s += 8; + } + break; + + case MESA_FORMAT_RGBA_SINT32: + for (i = 0; i < n; ++i) { + unpack_int_rgba_sint32(s, dst[i]); + s += 16; + } + break; + + case MESA_FORMAT_RGBX_UINT8: + for (i = 0; i < n; ++i) { + unpack_int_rgbx_uint8(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_RGBX_UINT16: + for (i = 0; i < n; ++i) { + unpack_int_rgbx_uint16(s, dst[i]); + s += 8; + } + break; + + case MESA_FORMAT_RGBX_UINT32: + for (i = 0; i < n; ++i) { + unpack_int_rgbx_uint32(s, dst[i]); + s += 16; + } + break; + + case MESA_FORMAT_RGBX_SINT8: + for (i = 0; i < n; ++i) { + unpack_int_rgbx_sint8(s, dst[i]); + s += 4; + } + break; + + case MESA_FORMAT_RGBX_SINT16: + for (i = 0; i < n; ++i) { + unpack_int_rgbx_sint16(s, dst[i]); + s += 8; + } + break; + + case MESA_FORMAT_RGBX_SINT32: + for (i = 0; i < n; ++i) { + unpack_int_rgbx_sint32(s, dst[i]); + s += 16; + } + break; + default: + _mesa_problem(NULL, "%s: bad format %s", __func__, + _mesa_get_format_name(format)); + return; + } +} + +/** + * Unpack a 2D rect of pixels returning float RGBA colors. + * \param format the source image format + * \param src start address of the source image + * \param srcRowStride source image row stride in bytes + * \param dst start address of the dest image + * \param dstRowStride dest image row stride in bytes + * \param x source image start X pos + * \param y source image start Y pos + * \param width width of rect region to convert + * \param height height of rect region to convert + */ +void +_mesa_unpack_rgba_block(mesa_format format, + const void *src, GLint srcRowStride, + GLfloat dst[][4], GLint dstRowStride, + GLuint x, GLuint y, GLuint width, GLuint height) +{ + const GLuint srcPixStride = _mesa_get_format_bytes(format); + const GLuint dstPixStride = 4 * sizeof(GLfloat); + const GLubyte *srcRow; + GLubyte *dstRow; + GLuint i; + + /* XXX needs to be fixed for compressed formats */ + + srcRow = ((const GLubyte *) src) + srcRowStride * y + srcPixStride * x; + dstRow = ((GLubyte *) dst) + dstRowStride * y + dstPixStride * x; + + for (i = 0; i < height; i++) { + _mesa_unpack_rgba_row(format, width, srcRow, (GLfloat (*)[4]) dstRow); + + dstRow += dstRowStride; + srcRow += srcRowStride; + } +} + +/** Helper struct for MESA_FORMAT_Z32_FLOAT_S8X24_UINT */ +struct z32f_x24s8 +{ + float z; + uint32_t x24s8; +}; + +typedef void (*unpack_float_z_func)(GLuint n, const void *src, GLfloat *dst); + +static void +unpack_float_z_X8_UINT_Z24_UNORM(GLuint n, const void *src, GLfloat *dst) +{ + /* only return Z, not stencil data */ + const GLuint *s = ((const GLuint *) src); + const GLdouble scale = 1.0 / (GLdouble) 0xffffff; + GLuint i; + for (i = 0; i < n; i++) { + dst[i] = (GLfloat) ((s[i] >> 8) * scale); + assert(dst[i] >= 0.0F); + assert(dst[i] <= 1.0F); + } +} + +static void +unpack_float_z_Z24_UNORM_X8_UINT(GLuint n, const void *src, GLfloat *dst) +{ + /* only return Z, not stencil data */ + const GLuint *s = ((const GLuint *) src); + const GLdouble scale = 1.0 / (GLdouble) 0xffffff; + GLuint i; + for (i = 0; i < n; i++) { + dst[i] = (GLfloat) ((s[i] & 0x00ffffff) * scale); + assert(dst[i] >= 0.0F); + assert(dst[i] <= 1.0F); + } +} + +static void +unpack_float_Z_UNORM16(GLuint n, const void *src, GLfloat *dst) +{ + const GLushort *s = ((const GLushort *) src); + GLuint i; + for (i = 0; i < n; i++) { + dst[i] = s[i] * (1.0F / 65535.0F); + } +} + +static void +unpack_float_Z_UNORM32(GLuint n, const void *src, GLfloat *dst) +{ + const GLuint *s = ((const GLuint *) src); + GLuint i; + for (i = 0; i < n; i++) { + dst[i] = s[i] * (1.0F / 0xffffffff); + } +} + +static void +unpack_float_Z_FLOAT32(GLuint n, const void *src, GLfloat *dst) +{ + memcpy(dst, src, n * sizeof(float)); +} + +static void +unpack_float_z_Z32X24S8(GLuint n, const void *src, GLfloat *dst) +{ + const struct z32f_x24s8 *s = (const struct z32f_x24s8 *) src; + GLuint i; + for (i = 0; i < n; i++) { + dst[i] = s[i].z; + } +} + + + +/** + * Unpack Z values. + * The returned values will always be in the range [0.0, 1.0]. + */ +void +_mesa_unpack_float_z_row(mesa_format format, GLuint n, + const void *src, GLfloat *dst) +{ + unpack_float_z_func unpack; + + switch (format) { + case MESA_FORMAT_S8_UINT_Z24_UNORM: + case MESA_FORMAT_X8_UINT_Z24_UNORM: + unpack = unpack_float_z_X8_UINT_Z24_UNORM; + break; + case MESA_FORMAT_Z24_UNORM_S8_UINT: + case MESA_FORMAT_Z24_UNORM_X8_UINT: + unpack = unpack_float_z_Z24_UNORM_X8_UINT; + break; + case MESA_FORMAT_Z_UNORM16: + unpack = unpack_float_Z_UNORM16; + break; + case MESA_FORMAT_Z_UNORM32: + unpack = unpack_float_Z_UNORM32; + break; + case MESA_FORMAT_Z_FLOAT32: + unpack = unpack_float_Z_FLOAT32; + break; + case MESA_FORMAT_Z32_FLOAT_S8X24_UINT: + unpack = unpack_float_z_Z32X24S8; + break; + default: + _mesa_problem(NULL, "bad format %s in _mesa_unpack_float_z_row", + _mesa_get_format_name(format)); + return; + } + + unpack(n, src, dst); +} + + + +typedef void (*unpack_uint_z_func)(const void *src, GLuint *dst, GLuint n); + +static void +unpack_uint_z_X8_UINT_Z24_UNORM(const void *src, GLuint *dst, GLuint n) +{ + /* only return Z, not stencil data */ + const GLuint *s = ((const GLuint *) src); + GLuint i; + for (i = 0; i < n; i++) { + dst[i] = (s[i] & 0xffffff00) | (s[i] >> 24); + } +} + +static void +unpack_uint_z_Z24_UNORM_X8_UINT(const void *src, GLuint *dst, GLuint n) +{ + /* only return Z, not stencil data */ + const GLuint *s = ((const GLuint *) src); + GLuint i; + for (i = 0; i < n; i++) { + dst[i] = (s[i] << 8) | ((s[i] >> 16) & 0xff); + } +} + +static void +unpack_uint_Z_UNORM16(const void *src, GLuint *dst, GLuint n) +{ + const GLushort *s = ((const GLushort *)src); + GLuint i; + for (i = 0; i < n; i++) { + dst[i] = (s[i] << 16) | s[i]; + } +} + +static void +unpack_uint_Z_UNORM32(const void *src, GLuint *dst, GLuint n) +{ + memcpy(dst, src, n * sizeof(GLuint)); +} + +static void +unpack_uint_Z_FLOAT32(const void *src, GLuint *dst, GLuint n) +{ + const float *s = (const float *)src; + GLuint i; + for (i = 0; i < n; i++) { + dst[i] = FLOAT_TO_UINT(CLAMP(s[i], 0.0F, 1.0F)); + } +} + +static void +unpack_uint_Z_FLOAT32_X24S8(const void *src, GLuint *dst, GLuint n) +{ + const struct z32f_x24s8 *s = (const struct z32f_x24s8 *) src; + GLuint i; + + for (i = 0; i < n; i++) { + dst[i] = FLOAT_TO_UINT(CLAMP(s[i].z, 0.0F, 1.0F)); + } +} + + +/** + * Unpack Z values. + * The returned values will always be in the range [0, 0xffffffff]. + */ +void +_mesa_unpack_uint_z_row(mesa_format format, GLuint n, + const void *src, GLuint *dst) +{ + unpack_uint_z_func unpack; + const GLubyte *srcPtr = (GLubyte *) src; + + switch (format) { + case MESA_FORMAT_S8_UINT_Z24_UNORM: + case MESA_FORMAT_X8_UINT_Z24_UNORM: + unpack = unpack_uint_z_X8_UINT_Z24_UNORM; + break; + case MESA_FORMAT_Z24_UNORM_S8_UINT: + case MESA_FORMAT_Z24_UNORM_X8_UINT: + unpack = unpack_uint_z_Z24_UNORM_X8_UINT; + break; + case MESA_FORMAT_Z_UNORM16: + unpack = unpack_uint_Z_UNORM16; + break; + case MESA_FORMAT_Z_UNORM32: + unpack = unpack_uint_Z_UNORM32; + break; + case MESA_FORMAT_Z_FLOAT32: + unpack = unpack_uint_Z_FLOAT32; + break; + case MESA_FORMAT_Z32_FLOAT_S8X24_UINT: + unpack = unpack_uint_Z_FLOAT32_X24S8; + break; + default: + _mesa_problem(NULL, "bad format %s in _mesa_unpack_uint_z_row", + _mesa_get_format_name(format)); + return; + } + + unpack(srcPtr, dst, n); +} + + +static void +unpack_ubyte_s_S_UINT8(const void *src, GLubyte *dst, GLuint n) +{ + memcpy(dst, src, n); +} + +static void +unpack_ubyte_s_S8_UINT_Z24_UNORM(const void *src, GLubyte *dst, GLuint n) +{ + GLuint i; + const GLuint *src32 = src; + + for (i = 0; i < n; i++) + dst[i] = src32[i] & 0xff; +} + +static void +unpack_ubyte_s_Z24_UNORM_S8_UINT(const void *src, GLubyte *dst, GLuint n) +{ + GLuint i; + const GLuint *src32 = src; + + for (i = 0; i < n; i++) + dst[i] = src32[i] >> 24; +} + +static void +unpack_ubyte_s_Z32_FLOAT_S8X24_UINT(const void *src, GLubyte *dst, GLuint n) +{ + GLuint i; + const struct z32f_x24s8 *s = (const struct z32f_x24s8 *) src; + + for (i = 0; i < n; i++) + dst[i] = s[i].x24s8 & 0xff; +} + +void +_mesa_unpack_ubyte_stencil_row(mesa_format format, GLuint n, + const void *src, GLubyte *dst) +{ + switch (format) { + case MESA_FORMAT_S_UINT8: + unpack_ubyte_s_S_UINT8(src, dst, n); + break; + case MESA_FORMAT_S8_UINT_Z24_UNORM: + unpack_ubyte_s_S8_UINT_Z24_UNORM(src, dst, n); + break; + case MESA_FORMAT_Z24_UNORM_S8_UINT: + unpack_ubyte_s_Z24_UNORM_S8_UINT(src, dst, n); + break; + case MESA_FORMAT_Z32_FLOAT_S8X24_UINT: + unpack_ubyte_s_Z32_FLOAT_S8X24_UINT(src, dst, n); + break; + default: + _mesa_problem(NULL, "bad format %s in _mesa_unpack_ubyte_s_row", + _mesa_get_format_name(format)); + return; + } +} + +static void +unpack_uint_24_8_depth_stencil_Z24_UNORM_S8_UINT(const GLuint *src, GLuint *dst, GLuint n) +{ + GLuint i; + + for (i = 0; i < n; i++) { + GLuint val = src[i]; + dst[i] = val >> 24 | val << 8; + } +} + +static void +unpack_uint_24_8_depth_stencil_Z32_S8X24(const GLuint *src, + GLuint *dst, GLuint n) +{ + GLuint i; + + for (i = 0; i < n; i++) { + /* 8 bytes per pixel (float + uint32) */ + GLfloat zf = ((GLfloat *) src)[i * 2 + 0]; + GLuint z24 = (GLuint) (zf * (GLfloat) 0xffffff); + GLuint s = src[i * 2 + 1] & 0xff; + dst[i] = (z24 << 8) | s; + } +} + +static void +unpack_uint_24_8_depth_stencil_S8_UINT_Z24_UNORM(const GLuint *src, GLuint *dst, GLuint n) +{ + memcpy(dst, src, n * 4); +} + +/** + * Unpack depth/stencil returning as GL_UNSIGNED_INT_24_8. + * \param format the source data format + */ +void +_mesa_unpack_uint_24_8_depth_stencil_row(mesa_format format, GLuint n, + const void *src, GLuint *dst) +{ + switch (format) { + case MESA_FORMAT_S8_UINT_Z24_UNORM: + unpack_uint_24_8_depth_stencil_S8_UINT_Z24_UNORM(src, dst, n); + break; + case MESA_FORMAT_Z24_UNORM_S8_UINT: + unpack_uint_24_8_depth_stencil_Z24_UNORM_S8_UINT(src, dst, n); + break; + case MESA_FORMAT_Z32_FLOAT_S8X24_UINT: + unpack_uint_24_8_depth_stencil_Z32_S8X24(src, dst, n); + break; + default: + _mesa_problem(NULL, + "bad format %s in _mesa_unpack_uint_24_8_depth_stencil_row", + _mesa_get_format_name(format)); + return; + } +} + +static void +unpack_float_32_uint_24_8_Z24_UNORM_S8_UINT(const GLuint *src, + GLuint *dst, GLuint n) +{ + GLuint i; + struct z32f_x24s8 *d = (struct z32f_x24s8 *) dst; + const GLdouble scale = 1.0 / (GLdouble) 0xffffff; + + for (i = 0; i < n; i++) { + const GLuint z24 = src[i] & 0xffffff; + d[i].z = z24 * scale; + d[i].x24s8 = src[i] >> 24; + assert(d[i].z >= 0.0f); + assert(d[i].z <= 1.0f); + } +} + +static void +unpack_float_32_uint_24_8_Z32_FLOAT_S8X24_UINT(const GLuint *src, + GLuint *dst, GLuint n) +{ + memcpy(dst, src, n * sizeof(struct z32f_x24s8)); +} + +static void +unpack_float_32_uint_24_8_S8_UINT_Z24_UNORM(const GLuint *src, + GLuint *dst, GLuint n) +{ + GLuint i; + struct z32f_x24s8 *d = (struct z32f_x24s8 *) dst; + const GLdouble scale = 1.0 / (GLdouble) 0xffffff; + + for (i = 0; i < n; i++) { + const GLuint z24 = src[i] >> 8; + d[i].z = z24 * scale; + d[i].x24s8 = src[i] & 0xff; + assert(d[i].z >= 0.0f); + assert(d[i].z <= 1.0f); + } +} + +/** + * Unpack depth/stencil returning as GL_FLOAT_32_UNSIGNED_INT_24_8_REV. + * \param format the source data format + * + * In GL_FLOAT_32_UNSIGNED_INT_24_8_REV lower 4 bytes contain float + * component and higher 4 bytes contain packed 24-bit and 8-bit + * components. + * + * 31 30 29 28 ... 4 3 2 1 0 31 30 29 ... 9 8 7 6 5 ... 2 1 0 + * +-------------------------+ +--------------------------------+ + * | Float Component | | Unused | 8 bit stencil | + * +-------------------------+ +--------------------------------+ + * lower 4 bytes higher 4 bytes + */ +void +_mesa_unpack_float_32_uint_24_8_depth_stencil_row(mesa_format format, GLuint n, + const void *src, GLuint *dst) +{ + switch (format) { + case MESA_FORMAT_S8_UINT_Z24_UNORM: + unpack_float_32_uint_24_8_S8_UINT_Z24_UNORM(src, dst, n); + break; + case MESA_FORMAT_Z24_UNORM_S8_UINT: + unpack_float_32_uint_24_8_Z24_UNORM_S8_UINT(src, dst, n); + break; + case MESA_FORMAT_Z32_FLOAT_S8X24_UINT: + unpack_float_32_uint_24_8_Z32_FLOAT_S8X24_UINT(src, dst, n); + break; + default: + _mesa_problem(NULL, + "bad format %s in _mesa_unpack_uint_24_8_depth_stencil_row", + _mesa_get_format_name(format)); + return; + } +} + +/** + * Unpack depth/stencil + * \param format the source data format + * \param type the destination data type + */ +void +_mesa_unpack_depth_stencil_row(mesa_format format, GLuint n, + const void *src, GLenum type, + GLuint *dst) +{ + assert(type == GL_UNSIGNED_INT_24_8 || + type == GL_FLOAT_32_UNSIGNED_INT_24_8_REV); + + switch (type) { + case GL_UNSIGNED_INT_24_8: + _mesa_unpack_uint_24_8_depth_stencil_row(format, n, src, dst); + break; + case GL_FLOAT_32_UNSIGNED_INT_24_8_REV: + _mesa_unpack_float_32_uint_24_8_depth_stencil_row(format, n, src, dst); + break; + default: + _mesa_problem(NULL, + "bad type 0x%x in _mesa_unpack_depth_stencil_row", + type); + return; + } +} + diff --git a/prebuilt-intermediates/nir/nir_builder_opcodes.h b/prebuilt-intermediates/nir/nir_builder_opcodes.h new file mode 100644 index 00000000000..31e4b01c5cb --- /dev/null +++ b/prebuilt-intermediates/nir/nir_builder_opcodes.h @@ -0,0 +1,1655 @@ +/* Copyright (C) 2015 Broadcom + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#ifndef _NIR_BUILDER_OPCODES_ +#define _NIR_BUILDER_OPCODES_ + + + +static inline nir_ssa_def * +nir_b2f16(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_b2f16, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_b2f32(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_b2f32, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_b2f64(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_b2f64, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_b2i1(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_b2i1, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_b2i16(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_b2i16, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_b2i32(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_b2i32, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_b2i64(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_b2i64, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_b2i8(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_b2i8, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_b32all_fequal2(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_b32all_fequal2, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_b32all_fequal3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_b32all_fequal3, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_b32all_fequal4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_b32all_fequal4, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_b32all_iequal2(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_b32all_iequal2, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_b32all_iequal3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_b32all_iequal3, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_b32all_iequal4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_b32all_iequal4, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_b32any_fnequal2(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_b32any_fnequal2, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_b32any_fnequal3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_b32any_fnequal3, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_b32any_fnequal4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_b32any_fnequal4, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_b32any_inequal2(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_b32any_inequal2, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_b32any_inequal3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_b32any_inequal3, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_b32any_inequal4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_b32any_inequal4, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_b32csel(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2) +{ + return nir_build_alu(build, nir_op_b32csel, src0, src1, src2, NULL); +} +static inline nir_ssa_def * +nir_ball_fequal2(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_ball_fequal2, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_ball_fequal3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_ball_fequal3, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_ball_fequal4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_ball_fequal4, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_ball_iequal2(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_ball_iequal2, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_ball_iequal3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_ball_iequal3, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_ball_iequal4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_ball_iequal4, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_bany_fnequal2(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_bany_fnequal2, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_bany_fnequal3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_bany_fnequal3, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_bany_fnequal4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_bany_fnequal4, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_bany_inequal2(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_bany_inequal2, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_bany_inequal3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_bany_inequal3, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_bany_inequal4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_bany_inequal4, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_bcsel(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2) +{ + return nir_build_alu(build, nir_op_bcsel, src0, src1, src2, NULL); +} +static inline nir_ssa_def * +nir_bfi(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2) +{ + return nir_build_alu(build, nir_op_bfi, src0, src1, src2, NULL); +} +static inline nir_ssa_def * +nir_bfm(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_bfm, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_bit_count(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_bit_count, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_bitfield_insert(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3) +{ + return nir_build_alu(build, nir_op_bitfield_insert, src0, src1, src2, src3); +} +static inline nir_ssa_def * +nir_bitfield_reverse(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_bitfield_reverse, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_cube_face_coord(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_cube_face_coord, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_cube_face_index(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_cube_face_index, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_extract_i16(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_extract_i16, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_extract_i8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_extract_i8, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_extract_u16(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_extract_u16, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_extract_u8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_extract_u8, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_f2b1(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_f2b1, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_f2b32(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_f2b32, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_f2f16(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_f2f16, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_f2f16_rtne(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_f2f16_rtne, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_f2f16_rtz(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_f2f16_rtz, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_f2f32(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_f2f32, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_f2f64(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_f2f64, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_f2i1(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_f2i1, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_f2i16(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_f2i16, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_f2i32(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_f2i32, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_f2i64(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_f2i64, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_f2i8(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_f2i8, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_f2u1(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_f2u1, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_f2u16(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_f2u16, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_f2u32(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_f2u32, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_f2u64(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_f2u64, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_f2u8(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_f2u8, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_fabs(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_fabs, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_fadd(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_fadd, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_fall_equal2(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_fall_equal2, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_fall_equal3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_fall_equal3, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_fall_equal4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_fall_equal4, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_fand(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_fand, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_fany_nequal2(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_fany_nequal2, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_fany_nequal3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_fany_nequal3, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_fany_nequal4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_fany_nequal4, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_fceil(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_fceil, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_fcos(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_fcos, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_fcsel(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2) +{ + return nir_build_alu(build, nir_op_fcsel, src0, src1, src2, NULL); +} +static inline nir_ssa_def * +nir_fddx(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_fddx, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_fddx_coarse(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_fddx_coarse, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_fddx_fine(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_fddx_fine, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_fddy(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_fddy, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_fddy_coarse(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_fddy_coarse, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_fddy_fine(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_fddy_fine, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_fdiv(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_fdiv, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_fdot2(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_fdot2, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_fdot3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_fdot3, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_fdot4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_fdot4, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_fdot_replicated2(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_fdot_replicated2, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_fdot_replicated3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_fdot_replicated3, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_fdot_replicated4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_fdot_replicated4, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_fdph(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_fdph, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_fdph_replicated(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_fdph_replicated, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_feq(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_feq, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_feq32(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_feq32, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_fexp2(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_fexp2, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_ffloor(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_ffloor, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_ffma(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2) +{ + return nir_build_alu(build, nir_op_ffma, src0, src1, src2, NULL); +} +static inline nir_ssa_def * +nir_ffract(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_ffract, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_fge(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_fge, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_fge32(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_fge32, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_find_lsb(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_find_lsb, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_flog2(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_flog2, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_flrp(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2) +{ + return nir_build_alu(build, nir_op_flrp, src0, src1, src2, NULL); +} +static inline nir_ssa_def * +nir_flt(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_flt, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_flt32(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_flt32, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_fmax(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_fmax, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_fmax3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2) +{ + return nir_build_alu(build, nir_op_fmax3, src0, src1, src2, NULL); +} +static inline nir_ssa_def * +nir_fmed3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2) +{ + return nir_build_alu(build, nir_op_fmed3, src0, src1, src2, NULL); +} +static inline nir_ssa_def * +nir_fmin(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_fmin, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_fmin3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2) +{ + return nir_build_alu(build, nir_op_fmin3, src0, src1, src2, NULL); +} +static inline nir_ssa_def * +nir_fmod(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_fmod, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_fmov(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_fmov, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_fmul(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_fmul, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_fne(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_fne, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_fne32(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_fne32, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_fneg(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_fneg, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_fnoise1_1(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_fnoise1_1, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_fnoise1_2(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_fnoise1_2, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_fnoise1_3(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_fnoise1_3, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_fnoise1_4(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_fnoise1_4, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_fnoise2_1(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_fnoise2_1, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_fnoise2_2(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_fnoise2_2, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_fnoise2_3(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_fnoise2_3, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_fnoise2_4(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_fnoise2_4, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_fnoise3_1(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_fnoise3_1, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_fnoise3_2(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_fnoise3_2, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_fnoise3_3(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_fnoise3_3, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_fnoise3_4(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_fnoise3_4, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_fnoise4_1(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_fnoise4_1, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_fnoise4_2(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_fnoise4_2, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_fnoise4_3(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_fnoise4_3, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_fnoise4_4(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_fnoise4_4, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_fnot(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_fnot, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_for(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_for, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_fpow(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_fpow, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_fquantize2f16(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_fquantize2f16, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_frcp(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_frcp, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_frem(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_frem, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_frexp_exp(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_frexp_exp, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_frexp_sig(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_frexp_sig, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_fround_even(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_fround_even, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_frsq(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_frsq, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_fsat(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_fsat, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_fsign(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_fsign, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_fsin(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_fsin, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_fsqrt(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_fsqrt, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_fsub(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_fsub, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_ftrunc(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_ftrunc, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_fxor(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_fxor, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_i2b1(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_i2b1, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_i2b32(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_i2b32, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_i2f16(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_i2f16, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_i2f32(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_i2f32, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_i2f64(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_i2f64, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_i2i1(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_i2i1, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_i2i16(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_i2i16, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_i2i32(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_i2i32, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_i2i64(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_i2i64, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_i2i8(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_i2i8, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_iabs(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_iabs, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_iadd(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_iadd, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_iand(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_iand, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_ibfe(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2) +{ + return nir_build_alu(build, nir_op_ibfe, src0, src1, src2, NULL); +} +static inline nir_ssa_def * +nir_ibitfield_extract(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2) +{ + return nir_build_alu(build, nir_op_ibitfield_extract, src0, src1, src2, NULL); +} +static inline nir_ssa_def * +nir_idiv(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_idiv, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_ieq(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_ieq, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_ieq32(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_ieq32, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_ifind_msb(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_ifind_msb, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_ige(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_ige, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_ige32(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_ige32, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_ilt(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_ilt, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_ilt32(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_ilt32, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_imax(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_imax, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_imax3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2) +{ + return nir_build_alu(build, nir_op_imax3, src0, src1, src2, NULL); +} +static inline nir_ssa_def * +nir_imed3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2) +{ + return nir_build_alu(build, nir_op_imed3, src0, src1, src2, NULL); +} +static inline nir_ssa_def * +nir_imin(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_imin, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_imin3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2) +{ + return nir_build_alu(build, nir_op_imin3, src0, src1, src2, NULL); +} +static inline nir_ssa_def * +nir_imod(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_imod, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_imov(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_imov, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_imul(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_imul, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_imul_high(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_imul_high, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_ine(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_ine, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_ine32(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_ine32, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_ineg(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_ineg, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_inot(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_inot, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_ior(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_ior, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_irem(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_irem, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_ishl(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_ishl, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_ishr(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_ishr, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_isign(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_isign, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_isub(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_isub, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_ixor(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_ixor, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_ldexp(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_ldexp, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_pack_32_2x16(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_pack_32_2x16, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_pack_32_2x16_split(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_pack_32_2x16_split, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_pack_64_2x32(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_pack_64_2x32, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_pack_64_2x32_split(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_pack_64_2x32_split, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_pack_64_4x16(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_pack_64_4x16, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_pack_half_2x16(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_pack_half_2x16, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_pack_half_2x16_split(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_pack_half_2x16_split, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_pack_snorm_2x16(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_pack_snorm_2x16, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_pack_snorm_4x8(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_pack_snorm_4x8, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_pack_unorm_2x16(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_pack_unorm_2x16, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_pack_unorm_4x8(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_pack_unorm_4x8, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_pack_uvec2_to_uint(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_pack_uvec2_to_uint, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_pack_uvec4_to_uint(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_pack_uvec4_to_uint, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_seq(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_seq, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_sge(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_sge, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_slt(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_slt, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_sne(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_sne, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_u2f16(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_u2f16, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_u2f32(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_u2f32, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_u2f64(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_u2f64, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_u2u1(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_u2u1, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_u2u16(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_u2u16, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_u2u32(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_u2u32, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_u2u64(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_u2u64, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_u2u8(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_u2u8, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_uadd_carry(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_uadd_carry, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_uadd_sat(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_uadd_sat, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_ubfe(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2) +{ + return nir_build_alu(build, nir_op_ubfe, src0, src1, src2, NULL); +} +static inline nir_ssa_def * +nir_ubitfield_extract(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2) +{ + return nir_build_alu(build, nir_op_ubitfield_extract, src0, src1, src2, NULL); +} +static inline nir_ssa_def * +nir_udiv(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_udiv, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_ufind_msb(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_ufind_msb, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_uge(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_uge, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_uge32(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_uge32, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_ult(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_ult, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_ult32(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_ult32, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_umax(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_umax, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_umax3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2) +{ + return nir_build_alu(build, nir_op_umax3, src0, src1, src2, NULL); +} +static inline nir_ssa_def * +nir_umax_4x8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_umax_4x8, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_umed3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2) +{ + return nir_build_alu(build, nir_op_umed3, src0, src1, src2, NULL); +} +static inline nir_ssa_def * +nir_umin(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_umin, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_umin3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2) +{ + return nir_build_alu(build, nir_op_umin3, src0, src1, src2, NULL); +} +static inline nir_ssa_def * +nir_umin_4x8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_umin_4x8, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_umod(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_umod, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_umul_high(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_umul_high, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_umul_unorm_4x8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_umul_unorm_4x8, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_unpack_32_2x16(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_unpack_32_2x16, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_unpack_32_2x16_split_x(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_unpack_32_2x16_split_x, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_unpack_32_2x16_split_y(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_unpack_32_2x16_split_y, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_unpack_64_2x32(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_unpack_64_2x32, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_unpack_64_2x32_split_x(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_unpack_64_2x32_split_x, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_unpack_64_2x32_split_y(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_unpack_64_2x32_split_y, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_unpack_64_4x16(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_unpack_64_4x16, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_unpack_half_2x16(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_unpack_half_2x16, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_unpack_half_2x16_split_x(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_unpack_half_2x16_split_x, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_unpack_half_2x16_split_y(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_unpack_half_2x16_split_y, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_unpack_snorm_2x16(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_unpack_snorm_2x16, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_unpack_snorm_4x8(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_unpack_snorm_4x8, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_unpack_unorm_2x16(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_unpack_unorm_2x16, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_unpack_unorm_4x8(nir_builder *build, nir_ssa_def *src0) +{ + return nir_build_alu(build, nir_op_unpack_unorm_4x8, src0, NULL, NULL, NULL); +} +static inline nir_ssa_def * +nir_usadd_4x8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_usadd_4x8, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_ushr(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_ushr, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_ussub_4x8(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_ussub_4x8, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_usub_borrow(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_usub_borrow, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_vec2(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1) +{ + return nir_build_alu(build, nir_op_vec2, src0, src1, NULL, NULL); +} +static inline nir_ssa_def * +nir_vec3(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2) +{ + return nir_build_alu(build, nir_op_vec3, src0, src1, src2, NULL); +} +static inline nir_ssa_def * +nir_vec4(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3) +{ + return nir_build_alu(build, nir_op_vec4, src0, src1, src2, src3); +} + +/* Generic builder for system values. */ +static inline nir_ssa_def * +nir_load_system_value(nir_builder *build, nir_intrinsic_op op, int index, + unsigned bit_size) +{ + nir_intrinsic_instr *load = nir_intrinsic_instr_create(build->shader, op); + load->num_components = nir_intrinsic_infos[op].dest_components; + load->const_index[0] = index; + nir_ssa_dest_init(&load->instr, &load->dest, + nir_intrinsic_infos[op].dest_components, bit_size, NULL); + nir_builder_instr_insert(build, &load->instr); + return &load->dest.ssa; +} + + + + +static inline nir_ssa_def * +nir_load_alpha_ref_float(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_alpha_ref_float, + 0, 32); +} + +static inline nir_ssa_def * +nir_load_base_instance(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_base_instance, + 0, 32); +} + +static inline nir_ssa_def * +nir_load_base_vertex(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_base_vertex, + 0, 32); +} + +static inline nir_ssa_def * +nir_load_blend_const_color_a_float(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_blend_const_color_a_float, + 0, 32); +} + +static inline nir_ssa_def * +nir_load_blend_const_color_aaaa8888_unorm(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_blend_const_color_aaaa8888_unorm, + 0, 32); +} + +static inline nir_ssa_def * +nir_load_blend_const_color_b_float(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_blend_const_color_b_float, + 0, 32); +} + +static inline nir_ssa_def * +nir_load_blend_const_color_g_float(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_blend_const_color_g_float, + 0, 32); +} + +static inline nir_ssa_def * +nir_load_blend_const_color_r_float(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_blend_const_color_r_float, + 0, 32); +} + +static inline nir_ssa_def * +nir_load_blend_const_color_rgba8888_unorm(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_blend_const_color_rgba8888_unorm, + 0, 32); +} + +static inline nir_ssa_def * +nir_load_draw_id(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_draw_id, + 0, 32); +} + +static inline nir_ssa_def * +nir_load_first_vertex(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_first_vertex, + 0, 32); +} + +static inline nir_ssa_def * +nir_load_frag_coord(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_frag_coord, + 0, 32); +} + +static inline nir_ssa_def * +nir_load_front_face(nir_builder *build, unsigned bit_size) +{ + return nir_load_system_value(build, nir_intrinsic_load_front_face, + 0, bit_size); +} + +static inline nir_ssa_def * +nir_load_global_invocation_id(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_global_invocation_id, + 0, 32); +} + +static inline nir_ssa_def * +nir_load_helper_invocation(nir_builder *build, unsigned bit_size) +{ + return nir_load_system_value(build, nir_intrinsic_load_helper_invocation, + 0, bit_size); +} + +static inline nir_ssa_def * +nir_load_instance_id(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_instance_id, + 0, 32); +} + +static inline nir_ssa_def * +nir_load_invocation_id(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_invocation_id, + 0, 32); +} + +static inline nir_ssa_def * +nir_load_is_indexed_draw(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_is_indexed_draw, + 0, 32); +} + +static inline nir_ssa_def * +nir_load_layer_id(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_layer_id, + 0, 32); +} + +static inline nir_ssa_def * +nir_load_local_group_size(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_local_group_size, + 0, 32); +} + +static inline nir_ssa_def * +nir_load_local_invocation_id(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_local_invocation_id, + 0, 32); +} + +static inline nir_ssa_def * +nir_load_local_invocation_index(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_local_invocation_index, + 0, 32); +} + +static inline nir_ssa_def * +nir_load_num_subgroups(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_num_subgroups, + 0, 32); +} + +static inline nir_ssa_def * +nir_load_num_work_groups(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_num_work_groups, + 0, 32); +} + +static inline nir_ssa_def * +nir_load_patch_vertices_in(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_patch_vertices_in, + 0, 32); +} + +static inline nir_ssa_def * +nir_load_primitive_id(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_primitive_id, + 0, 32); +} + +static inline nir_ssa_def * +nir_load_sample_id(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_sample_id, + 0, 32); +} + +static inline nir_ssa_def * +nir_load_sample_id_no_per_sample(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_sample_id_no_per_sample, + 0, 32); +} + +static inline nir_ssa_def * +nir_load_sample_mask_in(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_sample_mask_in, + 0, 32); +} + +static inline nir_ssa_def * +nir_load_sample_pos(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_sample_pos, + 0, 32); +} + +static inline nir_ssa_def * +nir_load_subgroup_eq_mask(nir_builder *build, unsigned bit_size) +{ + return nir_load_system_value(build, nir_intrinsic_load_subgroup_eq_mask, + 0, bit_size); +} + +static inline nir_ssa_def * +nir_load_subgroup_ge_mask(nir_builder *build, unsigned bit_size) +{ + return nir_load_system_value(build, nir_intrinsic_load_subgroup_ge_mask, + 0, bit_size); +} + +static inline nir_ssa_def * +nir_load_subgroup_gt_mask(nir_builder *build, unsigned bit_size) +{ + return nir_load_system_value(build, nir_intrinsic_load_subgroup_gt_mask, + 0, bit_size); +} + +static inline nir_ssa_def * +nir_load_subgroup_id(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_subgroup_id, + 0, 32); +} + +static inline nir_ssa_def * +nir_load_subgroup_invocation(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_subgroup_invocation, + 0, 32); +} + +static inline nir_ssa_def * +nir_load_subgroup_le_mask(nir_builder *build, unsigned bit_size) +{ + return nir_load_system_value(build, nir_intrinsic_load_subgroup_le_mask, + 0, bit_size); +} + +static inline nir_ssa_def * +nir_load_subgroup_lt_mask(nir_builder *build, unsigned bit_size) +{ + return nir_load_system_value(build, nir_intrinsic_load_subgroup_lt_mask, + 0, bit_size); +} + +static inline nir_ssa_def * +nir_load_subgroup_size(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_subgroup_size, + 0, 32); +} + +static inline nir_ssa_def * +nir_load_tess_coord(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_tess_coord, + 0, 32); +} + +static inline nir_ssa_def * +nir_load_tess_level_inner(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_tess_level_inner, + 0, 32); +} + +static inline nir_ssa_def * +nir_load_tess_level_outer(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_tess_level_outer, + 0, 32); +} + +static inline nir_ssa_def * +nir_load_user_clip_plane(nir_builder *build, unsigned nir_intrinsic_ucp_id) +{ + return nir_load_system_value(build, nir_intrinsic_load_user_clip_plane, + nir_intrinsic_ucp_id, 32); +} + +static inline nir_ssa_def * +nir_load_vertex_id(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_vertex_id, + 0, 32); +} + +static inline nir_ssa_def * +nir_load_vertex_id_zero_base(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_vertex_id_zero_base, + 0, 32); +} + +static inline nir_ssa_def * +nir_load_view_index(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_view_index, + 0, 32); +} + +static inline nir_ssa_def * +nir_load_work_dim(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_work_dim, + 0, 32); +} + +static inline nir_ssa_def * +nir_load_work_group_id(nir_builder *build) +{ + return nir_load_system_value(build, nir_intrinsic_load_work_group_id, + 0, 32); +} + +#endif /* _NIR_BUILDER_OPCODES_ */ diff --git a/prebuilt-intermediates/nir/nir_constant_expressions.c b/prebuilt-intermediates/nir/nir_constant_expressions.c new file mode 100644 index 00000000000..e4b9aade728 --- /dev/null +++ b/prebuilt-intermediates/nir/nir_constant_expressions.c @@ -0,0 +1,20610 @@ +/* + * Copyright (C) 2014 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Jason Ekstrand (jason@jlekstrand.net) + */ + +#include +#include "util/rounding.h" /* for _mesa_roundeven */ +#include "util/half_float.h" +#include "util/bigmath.h" +#include "nir_constant_expressions.h" + +/** + * Evaluate one component of packSnorm4x8. + */ +static uint8_t +pack_snorm_1x8(float x) +{ + /* From section 8.4 of the GLSL 4.30 spec: + * + * packSnorm4x8 + * ------------ + * The conversion for component c of v to fixed point is done as + * follows: + * + * packSnorm4x8: round(clamp(c, -1, +1) * 127.0) + * + * We must first cast the float to an int, because casting a negative + * float to a uint is undefined. + */ + return (uint8_t) (int) + _mesa_roundevenf(CLAMP(x, -1.0f, +1.0f) * 127.0f); +} + +/** + * Evaluate one component of packSnorm2x16. + */ +static uint16_t +pack_snorm_1x16(float x) +{ + /* From section 8.4 of the GLSL ES 3.00 spec: + * + * packSnorm2x16 + * ------------- + * The conversion for component c of v to fixed point is done as + * follows: + * + * packSnorm2x16: round(clamp(c, -1, +1) * 32767.0) + * + * We must first cast the float to an int, because casting a negative + * float to a uint is undefined. + */ + return (uint16_t) (int) + _mesa_roundevenf(CLAMP(x, -1.0f, +1.0f) * 32767.0f); +} + +/** + * Evaluate one component of unpackSnorm4x8. + */ +static float +unpack_snorm_1x8(uint8_t u) +{ + /* From section 8.4 of the GLSL 4.30 spec: + * + * unpackSnorm4x8 + * -------------- + * The conversion for unpacked fixed-point value f to floating point is + * done as follows: + * + * unpackSnorm4x8: clamp(f / 127.0, -1, +1) + */ + return CLAMP((int8_t) u / 127.0f, -1.0f, +1.0f); +} + +/** + * Evaluate one component of unpackSnorm2x16. + */ +static float +unpack_snorm_1x16(uint16_t u) +{ + /* From section 8.4 of the GLSL ES 3.00 spec: + * + * unpackSnorm2x16 + * --------------- + * The conversion for unpacked fixed-point value f to floating point is + * done as follows: + * + * unpackSnorm2x16: clamp(f / 32767.0, -1, +1) + */ + return CLAMP((int16_t) u / 32767.0f, -1.0f, +1.0f); +} + +/** + * Evaluate one component packUnorm4x8. + */ +static uint8_t +pack_unorm_1x8(float x) +{ + /* From section 8.4 of the GLSL 4.30 spec: + * + * packUnorm4x8 + * ------------ + * The conversion for component c of v to fixed point is done as + * follows: + * + * packUnorm4x8: round(clamp(c, 0, +1) * 255.0) + */ + return (uint8_t) (int) + _mesa_roundevenf(CLAMP(x, 0.0f, 1.0f) * 255.0f); +} + +/** + * Evaluate one component packUnorm2x16. + */ +static uint16_t +pack_unorm_1x16(float x) +{ + /* From section 8.4 of the GLSL ES 3.00 spec: + * + * packUnorm2x16 + * ------------- + * The conversion for component c of v to fixed point is done as + * follows: + * + * packUnorm2x16: round(clamp(c, 0, +1) * 65535.0) + */ + return (uint16_t) (int) + _mesa_roundevenf(CLAMP(x, 0.0f, 1.0f) * 65535.0f); +} + +/** + * Evaluate one component of unpackUnorm4x8. + */ +static float +unpack_unorm_1x8(uint8_t u) +{ + /* From section 8.4 of the GLSL 4.30 spec: + * + * unpackUnorm4x8 + * -------------- + * The conversion for unpacked fixed-point value f to floating point is + * done as follows: + * + * unpackUnorm4x8: f / 255.0 + */ + return (float) u / 255.0f; +} + +/** + * Evaluate one component of unpackUnorm2x16. + */ +static float +unpack_unorm_1x16(uint16_t u) +{ + /* From section 8.4 of the GLSL ES 3.00 spec: + * + * unpackUnorm2x16 + * --------------- + * The conversion for unpacked fixed-point value f to floating point is + * done as follows: + * + * unpackUnorm2x16: f / 65535.0 + */ + return (float) u / 65535.0f; +} + +/** + * Evaluate one component of packHalf2x16. + */ +static uint16_t +pack_half_1x16(float x) +{ + return _mesa_float_to_half(x); +} + +/** + * Evaluate one component of unpackHalf2x16. + */ +static float +unpack_half_1x16(uint16_t u) +{ + return _mesa_half_to_float(u); +} + +/* Some typed vector structures to make things like src0.y work */ +typedef int8_t int1_t; +typedef uint8_t uint1_t; +typedef float float16_t; +typedef float float32_t; +typedef double float64_t; +typedef bool bool1_t; +typedef bool bool8_t; +typedef bool bool16_t; +typedef bool bool32_t; +typedef bool bool64_t; +struct float16_vec { + float16_t x; + float16_t y; + float16_t z; + float16_t w; +}; +struct float32_vec { + float32_t x; + float32_t y; + float32_t z; + float32_t w; +}; +struct float64_vec { + float64_t x; + float64_t y; + float64_t z; + float64_t w; +}; +struct int1_vec { + int1_t x; + int1_t y; + int1_t z; + int1_t w; +}; +struct int8_vec { + int8_t x; + int8_t y; + int8_t z; + int8_t w; +}; +struct int16_vec { + int16_t x; + int16_t y; + int16_t z; + int16_t w; +}; +struct int32_vec { + int32_t x; + int32_t y; + int32_t z; + int32_t w; +}; +struct int64_vec { + int64_t x; + int64_t y; + int64_t z; + int64_t w; +}; +struct uint1_vec { + uint1_t x; + uint1_t y; + uint1_t z; + uint1_t w; +}; +struct uint8_vec { + uint8_t x; + uint8_t y; + uint8_t z; + uint8_t w; +}; +struct uint16_vec { + uint16_t x; + uint16_t y; + uint16_t z; + uint16_t w; +}; +struct uint32_vec { + uint32_t x; + uint32_t y; + uint32_t z; + uint32_t w; +}; +struct uint64_vec { + uint64_t x; + uint64_t y; + uint64_t z; + uint64_t w; +}; +struct bool1_vec { + bool1_t x; + bool1_t y; + bool1_t z; + bool1_t w; +}; +struct bool32_vec { + bool32_t x; + bool32_t y; + bool32_t z; + bool32_t w; +}; + + + +static nir_const_value +evaluate_b2f16(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const bool1_t src0 = + _src[0].b[_i]; + + float16_t dst = src0; + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const bool32_t src0 = + _src[0].i32[_i]; + + float16_t dst = src0; + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_b2f32(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const bool1_t src0 = + _src[0].b[_i]; + + float32_t dst = src0; + + _dst_val.f32[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const bool32_t src0 = + _src[0].i32[_i]; + + float32_t dst = src0; + + _dst_val.f32[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_b2f64(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const bool1_t src0 = + _src[0].b[_i]; + + float64_t dst = src0; + + _dst_val.f64[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const bool32_t src0 = + _src[0].i32[_i]; + + float64_t dst = src0; + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_b2i1(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const bool1_t src0 = + _src[0].b[_i]; + + int1_t dst = src0; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const bool32_t src0 = + _src[0].i32[_i]; + + int1_t dst = src0; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_b2i16(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const bool1_t src0 = + _src[0].b[_i]; + + int16_t dst = src0; + + _dst_val.i16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const bool32_t src0 = + _src[0].i32[_i]; + + int16_t dst = src0; + + _dst_val.i16[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_b2i32(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const bool1_t src0 = + _src[0].b[_i]; + + int32_t dst = src0; + + _dst_val.i32[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const bool32_t src0 = + _src[0].i32[_i]; + + int32_t dst = src0; + + _dst_val.i32[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_b2i64(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const bool1_t src0 = + _src[0].b[_i]; + + int64_t dst = src0; + + _dst_val.i64[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const bool32_t src0 = + _src[0].i32[_i]; + + int64_t dst = src0; + + _dst_val.i64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_b2i8(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const bool1_t src0 = + _src[0].b[_i]; + + int8_t dst = src0; + + _dst_val.i8[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const bool32_t src0 = + _src[0].i32[_i]; + + int8_t dst = src0; + + _dst_val.i8[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_b32all_fequal2(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + const struct float16_vec src0 = { + _mesa_half_to_float(_src[0].u16[0]), + _mesa_half_to_float(_src[0].u16[1]), + 0, + 0, + }; + + const struct float16_vec src1 = { + _mesa_half_to_float(_src[1].u16[0]), + _mesa_half_to_float(_src[1].u16[1]), + 0, + 0, + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + case 32: { + + + + + const struct float32_vec src0 = { + _src[0].f32[0], + _src[0].f32[1], + 0, + 0, + }; + + const struct float32_vec src1 = { + _src[1].f32[0], + _src[1].f32[1], + 0, + 0, + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + case 64: { + + + + + const struct float64_vec src0 = { + _src[0].f64[0], + _src[0].f64[1], + 0, + 0, + }; + + const struct float64_vec src1 = { + _src[1].f64[0], + _src[1].f64[1], + 0, + 0, + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_b32all_fequal3(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + const struct float16_vec src0 = { + _mesa_half_to_float(_src[0].u16[0]), + _mesa_half_to_float(_src[0].u16[1]), + _mesa_half_to_float(_src[0].u16[2]), + 0, + }; + + const struct float16_vec src1 = { + _mesa_half_to_float(_src[1].u16[0]), + _mesa_half_to_float(_src[1].u16[1]), + _mesa_half_to_float(_src[1].u16[2]), + 0, + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y) && (src0.z == src1.z)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + case 32: { + + + + + const struct float32_vec src0 = { + _src[0].f32[0], + _src[0].f32[1], + _src[0].f32[2], + 0, + }; + + const struct float32_vec src1 = { + _src[1].f32[0], + _src[1].f32[1], + _src[1].f32[2], + 0, + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y) && (src0.z == src1.z)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + case 64: { + + + + + const struct float64_vec src0 = { + _src[0].f64[0], + _src[0].f64[1], + _src[0].f64[2], + 0, + }; + + const struct float64_vec src1 = { + _src[1].f64[0], + _src[1].f64[1], + _src[1].f64[2], + 0, + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y) && (src0.z == src1.z)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_b32all_fequal4(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + const struct float16_vec src0 = { + _mesa_half_to_float(_src[0].u16[0]), + _mesa_half_to_float(_src[0].u16[1]), + _mesa_half_to_float(_src[0].u16[2]), + _mesa_half_to_float(_src[0].u16[3]), + }; + + const struct float16_vec src1 = { + _mesa_half_to_float(_src[1].u16[0]), + _mesa_half_to_float(_src[1].u16[1]), + _mesa_half_to_float(_src[1].u16[2]), + _mesa_half_to_float(_src[1].u16[3]), + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y) && (src0.z == src1.z) && (src0.w == src1.w)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + case 32: { + + + + + const struct float32_vec src0 = { + _src[0].f32[0], + _src[0].f32[1], + _src[0].f32[2], + _src[0].f32[3], + }; + + const struct float32_vec src1 = { + _src[1].f32[0], + _src[1].f32[1], + _src[1].f32[2], + _src[1].f32[3], + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y) && (src0.z == src1.z) && (src0.w == src1.w)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + case 64: { + + + + + const struct float64_vec src0 = { + _src[0].f64[0], + _src[0].f64[1], + _src[0].f64[2], + _src[0].f64[3], + }; + + const struct float64_vec src1 = { + _src[1].f64[0], + _src[1].f64[1], + _src[1].f64[2], + _src[1].f64[3], + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y) && (src0.z == src1.z) && (src0.w == src1.w)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_b32all_iequal2(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + const struct int1_vec src0 = { + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[0].b[0], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[0].b[1], + 0, + 0, + }; + + const struct int1_vec src1 = { + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[1].b[0], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[1].b[1], + 0, + 0, + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + case 8: { + + + + + const struct int8_vec src0 = { + _src[0].i8[0], + _src[0].i8[1], + 0, + 0, + }; + + const struct int8_vec src1 = { + _src[1].i8[0], + _src[1].i8[1], + 0, + 0, + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + case 16: { + + + + + const struct int16_vec src0 = { + _src[0].i16[0], + _src[0].i16[1], + 0, + 0, + }; + + const struct int16_vec src1 = { + _src[1].i16[0], + _src[1].i16[1], + 0, + 0, + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + case 32: { + + + + + const struct int32_vec src0 = { + _src[0].i32[0], + _src[0].i32[1], + 0, + 0, + }; + + const struct int32_vec src1 = { + _src[1].i32[0], + _src[1].i32[1], + 0, + 0, + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + case 64: { + + + + + const struct int64_vec src0 = { + _src[0].i64[0], + _src[0].i64[1], + 0, + 0, + }; + + const struct int64_vec src1 = { + _src[1].i64[0], + _src[1].i64[1], + 0, + 0, + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_b32all_iequal3(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + const struct int1_vec src0 = { + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[0].b[0], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[0].b[1], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[0].b[2], + 0, + }; + + const struct int1_vec src1 = { + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[1].b[0], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[1].b[1], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[1].b[2], + 0, + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y) && (src0.z == src1.z)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + case 8: { + + + + + const struct int8_vec src0 = { + _src[0].i8[0], + _src[0].i8[1], + _src[0].i8[2], + 0, + }; + + const struct int8_vec src1 = { + _src[1].i8[0], + _src[1].i8[1], + _src[1].i8[2], + 0, + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y) && (src0.z == src1.z)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + case 16: { + + + + + const struct int16_vec src0 = { + _src[0].i16[0], + _src[0].i16[1], + _src[0].i16[2], + 0, + }; + + const struct int16_vec src1 = { + _src[1].i16[0], + _src[1].i16[1], + _src[1].i16[2], + 0, + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y) && (src0.z == src1.z)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + case 32: { + + + + + const struct int32_vec src0 = { + _src[0].i32[0], + _src[0].i32[1], + _src[0].i32[2], + 0, + }; + + const struct int32_vec src1 = { + _src[1].i32[0], + _src[1].i32[1], + _src[1].i32[2], + 0, + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y) && (src0.z == src1.z)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + case 64: { + + + + + const struct int64_vec src0 = { + _src[0].i64[0], + _src[0].i64[1], + _src[0].i64[2], + 0, + }; + + const struct int64_vec src1 = { + _src[1].i64[0], + _src[1].i64[1], + _src[1].i64[2], + 0, + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y) && (src0.z == src1.z)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_b32all_iequal4(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + const struct int1_vec src0 = { + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[0].b[0], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[0].b[1], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[0].b[2], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[0].b[3], + }; + + const struct int1_vec src1 = { + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[1].b[0], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[1].b[1], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[1].b[2], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[1].b[3], + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y) && (src0.z == src1.z) && (src0.w == src1.w)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + case 8: { + + + + + const struct int8_vec src0 = { + _src[0].i8[0], + _src[0].i8[1], + _src[0].i8[2], + _src[0].i8[3], + }; + + const struct int8_vec src1 = { + _src[1].i8[0], + _src[1].i8[1], + _src[1].i8[2], + _src[1].i8[3], + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y) && (src0.z == src1.z) && (src0.w == src1.w)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + case 16: { + + + + + const struct int16_vec src0 = { + _src[0].i16[0], + _src[0].i16[1], + _src[0].i16[2], + _src[0].i16[3], + }; + + const struct int16_vec src1 = { + _src[1].i16[0], + _src[1].i16[1], + _src[1].i16[2], + _src[1].i16[3], + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y) && (src0.z == src1.z) && (src0.w == src1.w)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + case 32: { + + + + + const struct int32_vec src0 = { + _src[0].i32[0], + _src[0].i32[1], + _src[0].i32[2], + _src[0].i32[3], + }; + + const struct int32_vec src1 = { + _src[1].i32[0], + _src[1].i32[1], + _src[1].i32[2], + _src[1].i32[3], + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y) && (src0.z == src1.z) && (src0.w == src1.w)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + case 64: { + + + + + const struct int64_vec src0 = { + _src[0].i64[0], + _src[0].i64[1], + _src[0].i64[2], + _src[0].i64[3], + }; + + const struct int64_vec src1 = { + _src[1].i64[0], + _src[1].i64[1], + _src[1].i64[2], + _src[1].i64[3], + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y) && (src0.z == src1.z) && (src0.w == src1.w)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_b32any_fnequal2(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + const struct float16_vec src0 = { + _mesa_half_to_float(_src[0].u16[0]), + _mesa_half_to_float(_src[0].u16[1]), + 0, + 0, + }; + + const struct float16_vec src1 = { + _mesa_half_to_float(_src[1].u16[0]), + _mesa_half_to_float(_src[1].u16[1]), + 0, + 0, + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + case 32: { + + + + + const struct float32_vec src0 = { + _src[0].f32[0], + _src[0].f32[1], + 0, + 0, + }; + + const struct float32_vec src1 = { + _src[1].f32[0], + _src[1].f32[1], + 0, + 0, + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + case 64: { + + + + + const struct float64_vec src0 = { + _src[0].f64[0], + _src[0].f64[1], + 0, + 0, + }; + + const struct float64_vec src1 = { + _src[1].f64[0], + _src[1].f64[1], + 0, + 0, + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_b32any_fnequal3(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + const struct float16_vec src0 = { + _mesa_half_to_float(_src[0].u16[0]), + _mesa_half_to_float(_src[0].u16[1]), + _mesa_half_to_float(_src[0].u16[2]), + 0, + }; + + const struct float16_vec src1 = { + _mesa_half_to_float(_src[1].u16[0]), + _mesa_half_to_float(_src[1].u16[1]), + _mesa_half_to_float(_src[1].u16[2]), + 0, + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y) || (src0.z != src1.z)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + case 32: { + + + + + const struct float32_vec src0 = { + _src[0].f32[0], + _src[0].f32[1], + _src[0].f32[2], + 0, + }; + + const struct float32_vec src1 = { + _src[1].f32[0], + _src[1].f32[1], + _src[1].f32[2], + 0, + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y) || (src0.z != src1.z)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + case 64: { + + + + + const struct float64_vec src0 = { + _src[0].f64[0], + _src[0].f64[1], + _src[0].f64[2], + 0, + }; + + const struct float64_vec src1 = { + _src[1].f64[0], + _src[1].f64[1], + _src[1].f64[2], + 0, + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y) || (src0.z != src1.z)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_b32any_fnequal4(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + const struct float16_vec src0 = { + _mesa_half_to_float(_src[0].u16[0]), + _mesa_half_to_float(_src[0].u16[1]), + _mesa_half_to_float(_src[0].u16[2]), + _mesa_half_to_float(_src[0].u16[3]), + }; + + const struct float16_vec src1 = { + _mesa_half_to_float(_src[1].u16[0]), + _mesa_half_to_float(_src[1].u16[1]), + _mesa_half_to_float(_src[1].u16[2]), + _mesa_half_to_float(_src[1].u16[3]), + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y) || (src0.z != src1.z) || (src0.w != src1.w)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + case 32: { + + + + + const struct float32_vec src0 = { + _src[0].f32[0], + _src[0].f32[1], + _src[0].f32[2], + _src[0].f32[3], + }; + + const struct float32_vec src1 = { + _src[1].f32[0], + _src[1].f32[1], + _src[1].f32[2], + _src[1].f32[3], + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y) || (src0.z != src1.z) || (src0.w != src1.w)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + case 64: { + + + + + const struct float64_vec src0 = { + _src[0].f64[0], + _src[0].f64[1], + _src[0].f64[2], + _src[0].f64[3], + }; + + const struct float64_vec src1 = { + _src[1].f64[0], + _src[1].f64[1], + _src[1].f64[2], + _src[1].f64[3], + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y) || (src0.z != src1.z) || (src0.w != src1.w)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_b32any_inequal2(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + const struct int1_vec src0 = { + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[0].b[0], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[0].b[1], + 0, + 0, + }; + + const struct int1_vec src1 = { + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[1].b[0], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[1].b[1], + 0, + 0, + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + case 8: { + + + + + const struct int8_vec src0 = { + _src[0].i8[0], + _src[0].i8[1], + 0, + 0, + }; + + const struct int8_vec src1 = { + _src[1].i8[0], + _src[1].i8[1], + 0, + 0, + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + case 16: { + + + + + const struct int16_vec src0 = { + _src[0].i16[0], + _src[0].i16[1], + 0, + 0, + }; + + const struct int16_vec src1 = { + _src[1].i16[0], + _src[1].i16[1], + 0, + 0, + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + case 32: { + + + + + const struct int32_vec src0 = { + _src[0].i32[0], + _src[0].i32[1], + 0, + 0, + }; + + const struct int32_vec src1 = { + _src[1].i32[0], + _src[1].i32[1], + 0, + 0, + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + case 64: { + + + + + const struct int64_vec src0 = { + _src[0].i64[0], + _src[0].i64[1], + 0, + 0, + }; + + const struct int64_vec src1 = { + _src[1].i64[0], + _src[1].i64[1], + 0, + 0, + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_b32any_inequal3(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + const struct int1_vec src0 = { + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[0].b[0], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[0].b[1], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[0].b[2], + 0, + }; + + const struct int1_vec src1 = { + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[1].b[0], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[1].b[1], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[1].b[2], + 0, + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y) || (src0.z != src1.z)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + case 8: { + + + + + const struct int8_vec src0 = { + _src[0].i8[0], + _src[0].i8[1], + _src[0].i8[2], + 0, + }; + + const struct int8_vec src1 = { + _src[1].i8[0], + _src[1].i8[1], + _src[1].i8[2], + 0, + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y) || (src0.z != src1.z)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + case 16: { + + + + + const struct int16_vec src0 = { + _src[0].i16[0], + _src[0].i16[1], + _src[0].i16[2], + 0, + }; + + const struct int16_vec src1 = { + _src[1].i16[0], + _src[1].i16[1], + _src[1].i16[2], + 0, + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y) || (src0.z != src1.z)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + case 32: { + + + + + const struct int32_vec src0 = { + _src[0].i32[0], + _src[0].i32[1], + _src[0].i32[2], + 0, + }; + + const struct int32_vec src1 = { + _src[1].i32[0], + _src[1].i32[1], + _src[1].i32[2], + 0, + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y) || (src0.z != src1.z)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + case 64: { + + + + + const struct int64_vec src0 = { + _src[0].i64[0], + _src[0].i64[1], + _src[0].i64[2], + 0, + }; + + const struct int64_vec src1 = { + _src[1].i64[0], + _src[1].i64[1], + _src[1].i64[2], + 0, + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y) || (src0.z != src1.z)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_b32any_inequal4(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + const struct int1_vec src0 = { + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[0].b[0], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[0].b[1], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[0].b[2], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[0].b[3], + }; + + const struct int1_vec src1 = { + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[1].b[0], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[1].b[1], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[1].b[2], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[1].b[3], + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y) || (src0.z != src1.z) || (src0.w != src1.w)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + case 8: { + + + + + const struct int8_vec src0 = { + _src[0].i8[0], + _src[0].i8[1], + _src[0].i8[2], + _src[0].i8[3], + }; + + const struct int8_vec src1 = { + _src[1].i8[0], + _src[1].i8[1], + _src[1].i8[2], + _src[1].i8[3], + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y) || (src0.z != src1.z) || (src0.w != src1.w)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + case 16: { + + + + + const struct int16_vec src0 = { + _src[0].i16[0], + _src[0].i16[1], + _src[0].i16[2], + _src[0].i16[3], + }; + + const struct int16_vec src1 = { + _src[1].i16[0], + _src[1].i16[1], + _src[1].i16[2], + _src[1].i16[3], + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y) || (src0.z != src1.z) || (src0.w != src1.w)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + case 32: { + + + + + const struct int32_vec src0 = { + _src[0].i32[0], + _src[0].i32[1], + _src[0].i32[2], + _src[0].i32[3], + }; + + const struct int32_vec src1 = { + _src[1].i32[0], + _src[1].i32[1], + _src[1].i32[2], + _src[1].i32[3], + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y) || (src0.z != src1.z) || (src0.w != src1.w)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + case 64: { + + + + + const struct int64_vec src0 = { + _src[0].i64[0], + _src[0].i64[1], + _src[0].i64[2], + _src[0].i64[3], + }; + + const struct int64_vec src1 = { + _src[1].i64[0], + _src[1].i64[1], + _src[1].i64[2], + _src[1].i64[3], + }; + + struct bool32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y) || (src0.z != src1.z) || (src0.w != src1.w)); + + _dst_val.i32[0] = -(int)dst.x; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_b32csel(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const bool32_t src0 = + _src[0].i32[_i]; + const uint1_t src1 = + _src[1].b[_i]; + const uint1_t src2 = + _src[2].b[_i]; + + uint1_t dst = src0 ? src1 : src2; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const bool32_t src0 = + _src[0].i32[_i]; + const uint8_t src1 = + _src[1].u8[_i]; + const uint8_t src2 = + _src[2].u8[_i]; + + uint8_t dst = src0 ? src1 : src2; + + _dst_val.u8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const bool32_t src0 = + _src[0].i32[_i]; + const uint16_t src1 = + _src[1].u16[_i]; + const uint16_t src2 = + _src[2].u16[_i]; + + uint16_t dst = src0 ? src1 : src2; + + _dst_val.u16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const bool32_t src0 = + _src[0].i32[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + const uint32_t src2 = + _src[2].u32[_i]; + + uint32_t dst = src0 ? src1 : src2; + + _dst_val.u32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const bool32_t src0 = + _src[0].i32[_i]; + const uint64_t src1 = + _src[1].u64[_i]; + const uint64_t src2 = + _src[2].u64[_i]; + + uint64_t dst = src0 ? src1 : src2; + + _dst_val.u64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_ball_fequal2(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + const struct float16_vec src0 = { + _mesa_half_to_float(_src[0].u16[0]), + _mesa_half_to_float(_src[0].u16[1]), + 0, + 0, + }; + + const struct float16_vec src1 = { + _mesa_half_to_float(_src[1].u16[0]), + _mesa_half_to_float(_src[1].u16[1]), + 0, + 0, + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + case 32: { + + + + + const struct float32_vec src0 = { + _src[0].f32[0], + _src[0].f32[1], + 0, + 0, + }; + + const struct float32_vec src1 = { + _src[1].f32[0], + _src[1].f32[1], + 0, + 0, + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + case 64: { + + + + + const struct float64_vec src0 = { + _src[0].f64[0], + _src[0].f64[1], + 0, + 0, + }; + + const struct float64_vec src1 = { + _src[1].f64[0], + _src[1].f64[1], + 0, + 0, + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_ball_fequal3(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + const struct float16_vec src0 = { + _mesa_half_to_float(_src[0].u16[0]), + _mesa_half_to_float(_src[0].u16[1]), + _mesa_half_to_float(_src[0].u16[2]), + 0, + }; + + const struct float16_vec src1 = { + _mesa_half_to_float(_src[1].u16[0]), + _mesa_half_to_float(_src[1].u16[1]), + _mesa_half_to_float(_src[1].u16[2]), + 0, + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y) && (src0.z == src1.z)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + case 32: { + + + + + const struct float32_vec src0 = { + _src[0].f32[0], + _src[0].f32[1], + _src[0].f32[2], + 0, + }; + + const struct float32_vec src1 = { + _src[1].f32[0], + _src[1].f32[1], + _src[1].f32[2], + 0, + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y) && (src0.z == src1.z)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + case 64: { + + + + + const struct float64_vec src0 = { + _src[0].f64[0], + _src[0].f64[1], + _src[0].f64[2], + 0, + }; + + const struct float64_vec src1 = { + _src[1].f64[0], + _src[1].f64[1], + _src[1].f64[2], + 0, + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y) && (src0.z == src1.z)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_ball_fequal4(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + const struct float16_vec src0 = { + _mesa_half_to_float(_src[0].u16[0]), + _mesa_half_to_float(_src[0].u16[1]), + _mesa_half_to_float(_src[0].u16[2]), + _mesa_half_to_float(_src[0].u16[3]), + }; + + const struct float16_vec src1 = { + _mesa_half_to_float(_src[1].u16[0]), + _mesa_half_to_float(_src[1].u16[1]), + _mesa_half_to_float(_src[1].u16[2]), + _mesa_half_to_float(_src[1].u16[3]), + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y) && (src0.z == src1.z) && (src0.w == src1.w)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + case 32: { + + + + + const struct float32_vec src0 = { + _src[0].f32[0], + _src[0].f32[1], + _src[0].f32[2], + _src[0].f32[3], + }; + + const struct float32_vec src1 = { + _src[1].f32[0], + _src[1].f32[1], + _src[1].f32[2], + _src[1].f32[3], + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y) && (src0.z == src1.z) && (src0.w == src1.w)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + case 64: { + + + + + const struct float64_vec src0 = { + _src[0].f64[0], + _src[0].f64[1], + _src[0].f64[2], + _src[0].f64[3], + }; + + const struct float64_vec src1 = { + _src[1].f64[0], + _src[1].f64[1], + _src[1].f64[2], + _src[1].f64[3], + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y) && (src0.z == src1.z) && (src0.w == src1.w)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_ball_iequal2(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + const struct int1_vec src0 = { + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[0].b[0], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[0].b[1], + 0, + 0, + }; + + const struct int1_vec src1 = { + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[1].b[0], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[1].b[1], + 0, + 0, + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + case 8: { + + + + + const struct int8_vec src0 = { + _src[0].i8[0], + _src[0].i8[1], + 0, + 0, + }; + + const struct int8_vec src1 = { + _src[1].i8[0], + _src[1].i8[1], + 0, + 0, + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + case 16: { + + + + + const struct int16_vec src0 = { + _src[0].i16[0], + _src[0].i16[1], + 0, + 0, + }; + + const struct int16_vec src1 = { + _src[1].i16[0], + _src[1].i16[1], + 0, + 0, + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + case 32: { + + + + + const struct int32_vec src0 = { + _src[0].i32[0], + _src[0].i32[1], + 0, + 0, + }; + + const struct int32_vec src1 = { + _src[1].i32[0], + _src[1].i32[1], + 0, + 0, + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + case 64: { + + + + + const struct int64_vec src0 = { + _src[0].i64[0], + _src[0].i64[1], + 0, + 0, + }; + + const struct int64_vec src1 = { + _src[1].i64[0], + _src[1].i64[1], + 0, + 0, + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_ball_iequal3(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + const struct int1_vec src0 = { + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[0].b[0], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[0].b[1], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[0].b[2], + 0, + }; + + const struct int1_vec src1 = { + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[1].b[0], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[1].b[1], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[1].b[2], + 0, + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y) && (src0.z == src1.z)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + case 8: { + + + + + const struct int8_vec src0 = { + _src[0].i8[0], + _src[0].i8[1], + _src[0].i8[2], + 0, + }; + + const struct int8_vec src1 = { + _src[1].i8[0], + _src[1].i8[1], + _src[1].i8[2], + 0, + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y) && (src0.z == src1.z)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + case 16: { + + + + + const struct int16_vec src0 = { + _src[0].i16[0], + _src[0].i16[1], + _src[0].i16[2], + 0, + }; + + const struct int16_vec src1 = { + _src[1].i16[0], + _src[1].i16[1], + _src[1].i16[2], + 0, + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y) && (src0.z == src1.z)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + case 32: { + + + + + const struct int32_vec src0 = { + _src[0].i32[0], + _src[0].i32[1], + _src[0].i32[2], + 0, + }; + + const struct int32_vec src1 = { + _src[1].i32[0], + _src[1].i32[1], + _src[1].i32[2], + 0, + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y) && (src0.z == src1.z)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + case 64: { + + + + + const struct int64_vec src0 = { + _src[0].i64[0], + _src[0].i64[1], + _src[0].i64[2], + 0, + }; + + const struct int64_vec src1 = { + _src[1].i64[0], + _src[1].i64[1], + _src[1].i64[2], + 0, + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y) && (src0.z == src1.z)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_ball_iequal4(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + const struct int1_vec src0 = { + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[0].b[0], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[0].b[1], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[0].b[2], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[0].b[3], + }; + + const struct int1_vec src1 = { + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[1].b[0], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[1].b[1], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[1].b[2], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[1].b[3], + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y) && (src0.z == src1.z) && (src0.w == src1.w)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + case 8: { + + + + + const struct int8_vec src0 = { + _src[0].i8[0], + _src[0].i8[1], + _src[0].i8[2], + _src[0].i8[3], + }; + + const struct int8_vec src1 = { + _src[1].i8[0], + _src[1].i8[1], + _src[1].i8[2], + _src[1].i8[3], + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y) && (src0.z == src1.z) && (src0.w == src1.w)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + case 16: { + + + + + const struct int16_vec src0 = { + _src[0].i16[0], + _src[0].i16[1], + _src[0].i16[2], + _src[0].i16[3], + }; + + const struct int16_vec src1 = { + _src[1].i16[0], + _src[1].i16[1], + _src[1].i16[2], + _src[1].i16[3], + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y) && (src0.z == src1.z) && (src0.w == src1.w)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + case 32: { + + + + + const struct int32_vec src0 = { + _src[0].i32[0], + _src[0].i32[1], + _src[0].i32[2], + _src[0].i32[3], + }; + + const struct int32_vec src1 = { + _src[1].i32[0], + _src[1].i32[1], + _src[1].i32[2], + _src[1].i32[3], + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y) && (src0.z == src1.z) && (src0.w == src1.w)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + case 64: { + + + + + const struct int64_vec src0 = { + _src[0].i64[0], + _src[0].i64[1], + _src[0].i64[2], + _src[0].i64[3], + }; + + const struct int64_vec src1 = { + _src[1].i64[0], + _src[1].i64[1], + _src[1].i64[2], + _src[1].i64[3], + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y) && (src0.z == src1.z) && (src0.w == src1.w)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_bany_fnequal2(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + const struct float16_vec src0 = { + _mesa_half_to_float(_src[0].u16[0]), + _mesa_half_to_float(_src[0].u16[1]), + 0, + 0, + }; + + const struct float16_vec src1 = { + _mesa_half_to_float(_src[1].u16[0]), + _mesa_half_to_float(_src[1].u16[1]), + 0, + 0, + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + case 32: { + + + + + const struct float32_vec src0 = { + _src[0].f32[0], + _src[0].f32[1], + 0, + 0, + }; + + const struct float32_vec src1 = { + _src[1].f32[0], + _src[1].f32[1], + 0, + 0, + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + case 64: { + + + + + const struct float64_vec src0 = { + _src[0].f64[0], + _src[0].f64[1], + 0, + 0, + }; + + const struct float64_vec src1 = { + _src[1].f64[0], + _src[1].f64[1], + 0, + 0, + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_bany_fnequal3(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + const struct float16_vec src0 = { + _mesa_half_to_float(_src[0].u16[0]), + _mesa_half_to_float(_src[0].u16[1]), + _mesa_half_to_float(_src[0].u16[2]), + 0, + }; + + const struct float16_vec src1 = { + _mesa_half_to_float(_src[1].u16[0]), + _mesa_half_to_float(_src[1].u16[1]), + _mesa_half_to_float(_src[1].u16[2]), + 0, + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y) || (src0.z != src1.z)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + case 32: { + + + + + const struct float32_vec src0 = { + _src[0].f32[0], + _src[0].f32[1], + _src[0].f32[2], + 0, + }; + + const struct float32_vec src1 = { + _src[1].f32[0], + _src[1].f32[1], + _src[1].f32[2], + 0, + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y) || (src0.z != src1.z)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + case 64: { + + + + + const struct float64_vec src0 = { + _src[0].f64[0], + _src[0].f64[1], + _src[0].f64[2], + 0, + }; + + const struct float64_vec src1 = { + _src[1].f64[0], + _src[1].f64[1], + _src[1].f64[2], + 0, + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y) || (src0.z != src1.z)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_bany_fnequal4(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + const struct float16_vec src0 = { + _mesa_half_to_float(_src[0].u16[0]), + _mesa_half_to_float(_src[0].u16[1]), + _mesa_half_to_float(_src[0].u16[2]), + _mesa_half_to_float(_src[0].u16[3]), + }; + + const struct float16_vec src1 = { + _mesa_half_to_float(_src[1].u16[0]), + _mesa_half_to_float(_src[1].u16[1]), + _mesa_half_to_float(_src[1].u16[2]), + _mesa_half_to_float(_src[1].u16[3]), + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y) || (src0.z != src1.z) || (src0.w != src1.w)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + case 32: { + + + + + const struct float32_vec src0 = { + _src[0].f32[0], + _src[0].f32[1], + _src[0].f32[2], + _src[0].f32[3], + }; + + const struct float32_vec src1 = { + _src[1].f32[0], + _src[1].f32[1], + _src[1].f32[2], + _src[1].f32[3], + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y) || (src0.z != src1.z) || (src0.w != src1.w)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + case 64: { + + + + + const struct float64_vec src0 = { + _src[0].f64[0], + _src[0].f64[1], + _src[0].f64[2], + _src[0].f64[3], + }; + + const struct float64_vec src1 = { + _src[1].f64[0], + _src[1].f64[1], + _src[1].f64[2], + _src[1].f64[3], + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y) || (src0.z != src1.z) || (src0.w != src1.w)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_bany_inequal2(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + const struct int1_vec src0 = { + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[0].b[0], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[0].b[1], + 0, + 0, + }; + + const struct int1_vec src1 = { + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[1].b[0], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[1].b[1], + 0, + 0, + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + case 8: { + + + + + const struct int8_vec src0 = { + _src[0].i8[0], + _src[0].i8[1], + 0, + 0, + }; + + const struct int8_vec src1 = { + _src[1].i8[0], + _src[1].i8[1], + 0, + 0, + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + case 16: { + + + + + const struct int16_vec src0 = { + _src[0].i16[0], + _src[0].i16[1], + 0, + 0, + }; + + const struct int16_vec src1 = { + _src[1].i16[0], + _src[1].i16[1], + 0, + 0, + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + case 32: { + + + + + const struct int32_vec src0 = { + _src[0].i32[0], + _src[0].i32[1], + 0, + 0, + }; + + const struct int32_vec src1 = { + _src[1].i32[0], + _src[1].i32[1], + 0, + 0, + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + case 64: { + + + + + const struct int64_vec src0 = { + _src[0].i64[0], + _src[0].i64[1], + 0, + 0, + }; + + const struct int64_vec src1 = { + _src[1].i64[0], + _src[1].i64[1], + 0, + 0, + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_bany_inequal3(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + const struct int1_vec src0 = { + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[0].b[0], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[0].b[1], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[0].b[2], + 0, + }; + + const struct int1_vec src1 = { + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[1].b[0], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[1].b[1], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[1].b[2], + 0, + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y) || (src0.z != src1.z)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + case 8: { + + + + + const struct int8_vec src0 = { + _src[0].i8[0], + _src[0].i8[1], + _src[0].i8[2], + 0, + }; + + const struct int8_vec src1 = { + _src[1].i8[0], + _src[1].i8[1], + _src[1].i8[2], + 0, + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y) || (src0.z != src1.z)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + case 16: { + + + + + const struct int16_vec src0 = { + _src[0].i16[0], + _src[0].i16[1], + _src[0].i16[2], + 0, + }; + + const struct int16_vec src1 = { + _src[1].i16[0], + _src[1].i16[1], + _src[1].i16[2], + 0, + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y) || (src0.z != src1.z)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + case 32: { + + + + + const struct int32_vec src0 = { + _src[0].i32[0], + _src[0].i32[1], + _src[0].i32[2], + 0, + }; + + const struct int32_vec src1 = { + _src[1].i32[0], + _src[1].i32[1], + _src[1].i32[2], + 0, + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y) || (src0.z != src1.z)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + case 64: { + + + + + const struct int64_vec src0 = { + _src[0].i64[0], + _src[0].i64[1], + _src[0].i64[2], + 0, + }; + + const struct int64_vec src1 = { + _src[1].i64[0], + _src[1].i64[1], + _src[1].i64[2], + 0, + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y) || (src0.z != src1.z)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_bany_inequal4(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + const struct int1_vec src0 = { + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[0].b[0], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[0].b[1], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[0].b[2], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[0].b[3], + }; + + const struct int1_vec src1 = { + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[1].b[0], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[1].b[1], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[1].b[2], + /* 1-bit integers use a 0/-1 convention */ + -(int1_t)_src[1].b[3], + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y) || (src0.z != src1.z) || (src0.w != src1.w)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + case 8: { + + + + + const struct int8_vec src0 = { + _src[0].i8[0], + _src[0].i8[1], + _src[0].i8[2], + _src[0].i8[3], + }; + + const struct int8_vec src1 = { + _src[1].i8[0], + _src[1].i8[1], + _src[1].i8[2], + _src[1].i8[3], + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y) || (src0.z != src1.z) || (src0.w != src1.w)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + case 16: { + + + + + const struct int16_vec src0 = { + _src[0].i16[0], + _src[0].i16[1], + _src[0].i16[2], + _src[0].i16[3], + }; + + const struct int16_vec src1 = { + _src[1].i16[0], + _src[1].i16[1], + _src[1].i16[2], + _src[1].i16[3], + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y) || (src0.z != src1.z) || (src0.w != src1.w)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + case 32: { + + + + + const struct int32_vec src0 = { + _src[0].i32[0], + _src[0].i32[1], + _src[0].i32[2], + _src[0].i32[3], + }; + + const struct int32_vec src1 = { + _src[1].i32[0], + _src[1].i32[1], + _src[1].i32[2], + _src[1].i32[3], + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y) || (src0.z != src1.z) || (src0.w != src1.w)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + case 64: { + + + + + const struct int64_vec src0 = { + _src[0].i64[0], + _src[0].i64[1], + _src[0].i64[2], + _src[0].i64[3], + }; + + const struct int64_vec src1 = { + _src[1].i64[0], + _src[1].i64[1], + _src[1].i64[2], + _src[1].i64[3], + }; + + struct bool1_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y) || (src0.z != src1.z) || (src0.w != src1.w)); + + _dst_val.b[0] = -(int)dst.x; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_bcsel(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const bool1_t src0 = + _src[0].b[_i]; + const uint1_t src1 = + _src[1].b[_i]; + const uint1_t src2 = + _src[2].b[_i]; + + uint1_t dst = src0 ? src1 : src2; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const bool1_t src0 = + _src[0].b[_i]; + const uint8_t src1 = + _src[1].u8[_i]; + const uint8_t src2 = + _src[2].u8[_i]; + + uint8_t dst = src0 ? src1 : src2; + + _dst_val.u8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const bool1_t src0 = + _src[0].b[_i]; + const uint16_t src1 = + _src[1].u16[_i]; + const uint16_t src2 = + _src[2].u16[_i]; + + uint16_t dst = src0 ? src1 : src2; + + _dst_val.u16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const bool1_t src0 = + _src[0].b[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + const uint32_t src2 = + _src[2].u32[_i]; + + uint32_t dst = src0 ? src1 : src2; + + _dst_val.u32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const bool1_t src0 = + _src[0].b[_i]; + const uint64_t src1 = + _src[1].u64[_i]; + const uint64_t src2 = + _src[2].u64[_i]; + + uint64_t dst = src0 ? src1 : src2; + + _dst_val.u64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_bfi(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + const uint32_t src2 = + _src[2].u32[_i]; + + uint32_t dst; + + +unsigned mask = src0, insert = src1, base = src2; +if (mask == 0) { + dst = base; +} else { + unsigned tmp = mask; + while (!(tmp & 1)) { + tmp >>= 1; + insert <<= 1; + } + dst = (base & ~mask) | (insert & mask); +} + + + _dst_val.u32[_i] = dst; + } + + + return _dst_val; +} +static nir_const_value +evaluate_bfm(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + const int32_t src1 = + _src[1].i32[_i]; + + uint32_t dst; + + +int bits = src0, offset = src1; +if (offset < 0 || bits < 0 || offset > 31 || bits > 31 || offset + bits > 32) + dst = 0; /* undefined */ +else + dst = ((1u << bits) - 1) << offset; + + + _dst_val.u32[_i] = dst; + } + + + return _dst_val; +} +static nir_const_value +evaluate_bit_count(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint1_t src0 = + _src[0].b[_i]; + + uint32_t dst; + + +dst = 0; +for (unsigned bit = 0; bit < bit_size; bit++) { + if ((src0 >> bit) & 1) + dst++; +} + + + _dst_val.u32[_i] = dst; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint8_t src0 = + _src[0].u8[_i]; + + uint32_t dst; + + +dst = 0; +for (unsigned bit = 0; bit < bit_size; bit++) { + if ((src0 >> bit) & 1) + dst++; +} + + + _dst_val.u32[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint16_t src0 = + _src[0].u16[_i]; + + uint32_t dst; + + +dst = 0; +for (unsigned bit = 0; bit < bit_size; bit++) { + if ((src0 >> bit) & 1) + dst++; +} + + + _dst_val.u32[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + + uint32_t dst; + + +dst = 0; +for (unsigned bit = 0; bit < bit_size; bit++) { + if ((src0 >> bit) & 1) + dst++; +} + + + _dst_val.u32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint64_t src0 = + _src[0].u64[_i]; + + uint32_t dst; + + +dst = 0; +for (unsigned bit = 0; bit < bit_size; bit++) { + if ((src0 >> bit) & 1) + dst++; +} + + + _dst_val.u32[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_bitfield_insert(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + const int32_t src2 = + _src[2].i32[_i]; + const int32_t src3 = + _src[3].i32[_i]; + + uint32_t dst; + + +unsigned base = src0, insert = src1; +int offset = src2, bits = src3; +if (bits == 0) { + dst = base; +} else if (offset < 0 || bits < 0 || bits + offset > 32) { + dst = 0; +} else { + unsigned mask = ((1ull << bits) - 1) << offset; + dst = (base & ~mask) | ((insert << offset) & mask); +} + + + _dst_val.u32[_i] = dst; + } + + + return _dst_val; +} +static nir_const_value +evaluate_bitfield_reverse(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + + uint32_t dst; + + +/* we're not winning any awards for speed here, but that's ok */ +dst = 0; +for (unsigned bit = 0; bit < 32; bit++) + dst |= ((src0 >> bit) & 1) << (31 - bit); + + + _dst_val.u32[_i] = dst; + } + + + return _dst_val; +} +static nir_const_value +evaluate_cube_face_coord(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + const struct float32_vec src0 = { + _src[0].f32[0], + _src[0].f32[1], + _src[0].f32[2], + 0, + }; + + struct float32_vec dst; + + +dst.x = dst.y = 0.0; +float absX = fabs(src0.x); +float absY = fabs(src0.y); +float absZ = fabs(src0.z); + +float ma = 0.0; +if (absX >= absY && absX >= absZ) { ma = 2 * src0.x; } +if (absY >= absX && absY >= absZ) { ma = 2 * src0.y; } +if (absZ >= absX && absZ >= absY) { ma = 2 * src0.z; } + +if (src0.x >= 0 && absX >= absY && absX >= absZ) { dst.x = -src0.z; dst.y = -src0.y; } +if (src0.x < 0 && absX >= absY && absX >= absZ) { dst.x = src0.z; dst.y = -src0.y; } +if (src0.y >= 0 && absY >= absX && absY >= absZ) { dst.x = src0.x; dst.y = src0.z; } +if (src0.y < 0 && absY >= absX && absY >= absZ) { dst.x = src0.x; dst.y = -src0.z; } +if (src0.z >= 0 && absZ >= absX && absZ >= absY) { dst.x = src0.x; dst.y = -src0.y; } +if (src0.z < 0 && absZ >= absX && absZ >= absY) { dst.x = -src0.x; dst.y = -src0.y; } + +dst.x = dst.x / ma + 0.5; +dst.y = dst.y / ma + 0.5; + + + _dst_val.f32[0] = dst.x; + _dst_val.f32[1] = dst.y; + + + return _dst_val; +} +static nir_const_value +evaluate_cube_face_index(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + const struct float32_vec src0 = { + _src[0].f32[0], + _src[0].f32[1], + _src[0].f32[2], + 0, + }; + + struct float32_vec dst; + + +float absX = fabs(src0.x); +float absY = fabs(src0.y); +float absZ = fabs(src0.z); +if (src0.x >= 0 && absX >= absY && absX >= absZ) dst.x = 0; +if (src0.x < 0 && absX >= absY && absX >= absZ) dst.x = 1; +if (src0.y >= 0 && absY >= absX && absY >= absZ) dst.x = 2; +if (src0.y < 0 && absY >= absX && absY >= absZ) dst.x = 3; +if (src0.z >= 0 && absZ >= absX && absZ >= absY) dst.x = 4; +if (src0.z < 0 && absZ >= absX && absZ >= absY) dst.x = 5; + + + _dst_val.f32[0] = dst.x; + + + return _dst_val; +} +static nir_const_value +evaluate_extract_i16(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + /* 1-bit integers use a 0/-1 convention */ + const int1_t src1 = -(int1_t)_src[1].b[_i]; + + int1_t dst = (int16_t)(src0 >> (src1 * 16)); + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + const int8_t src1 = + _src[1].i8[_i]; + + int8_t dst = (int16_t)(src0 >> (src1 * 16)); + + _dst_val.i8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + const int16_t src1 = + _src[1].i16[_i]; + + int16_t dst = (int16_t)(src0 >> (src1 * 16)); + + _dst_val.i16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + const int32_t src1 = + _src[1].i32[_i]; + + int32_t dst = (int16_t)(src0 >> (src1 * 16)); + + _dst_val.i32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + const int64_t src1 = + _src[1].i64[_i]; + + int64_t dst = (int16_t)(src0 >> (src1 * 16)); + + _dst_val.i64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_extract_i8(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + /* 1-bit integers use a 0/-1 convention */ + const int1_t src1 = -(int1_t)_src[1].b[_i]; + + int1_t dst = (int8_t)(src0 >> (src1 * 8)); + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + const int8_t src1 = + _src[1].i8[_i]; + + int8_t dst = (int8_t)(src0 >> (src1 * 8)); + + _dst_val.i8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + const int16_t src1 = + _src[1].i16[_i]; + + int16_t dst = (int8_t)(src0 >> (src1 * 8)); + + _dst_val.i16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + const int32_t src1 = + _src[1].i32[_i]; + + int32_t dst = (int8_t)(src0 >> (src1 * 8)); + + _dst_val.i32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + const int64_t src1 = + _src[1].i64[_i]; + + int64_t dst = (int8_t)(src0 >> (src1 * 8)); + + _dst_val.i64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_extract_u16(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint1_t src0 = + _src[0].b[_i]; + const uint1_t src1 = + _src[1].b[_i]; + + uint1_t dst = (uint16_t)(src0 >> (src1 * 16)); + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint8_t src0 = + _src[0].u8[_i]; + const uint8_t src1 = + _src[1].u8[_i]; + + uint8_t dst = (uint16_t)(src0 >> (src1 * 16)); + + _dst_val.u8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint16_t src0 = + _src[0].u16[_i]; + const uint16_t src1 = + _src[1].u16[_i]; + + uint16_t dst = (uint16_t)(src0 >> (src1 * 16)); + + _dst_val.u16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + + uint32_t dst = (uint16_t)(src0 >> (src1 * 16)); + + _dst_val.u32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint64_t src0 = + _src[0].u64[_i]; + const uint64_t src1 = + _src[1].u64[_i]; + + uint64_t dst = (uint16_t)(src0 >> (src1 * 16)); + + _dst_val.u64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_extract_u8(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint1_t src0 = + _src[0].b[_i]; + const uint1_t src1 = + _src[1].b[_i]; + + uint1_t dst = (uint8_t)(src0 >> (src1 * 8)); + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint8_t src0 = + _src[0].u8[_i]; + const uint8_t src1 = + _src[1].u8[_i]; + + uint8_t dst = (uint8_t)(src0 >> (src1 * 8)); + + _dst_val.u8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint16_t src0 = + _src[0].u16[_i]; + const uint16_t src1 = + _src[1].u16[_i]; + + uint16_t dst = (uint8_t)(src0 >> (src1 * 8)); + + _dst_val.u16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + + uint32_t dst = (uint8_t)(src0 >> (src1 * 8)); + + _dst_val.u32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint64_t src0 = + _src[0].u64[_i]; + const uint64_t src1 = + _src[1].u64[_i]; + + uint64_t dst = (uint8_t)(src0 >> (src1 * 8)); + + _dst_val.u64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_f2b1(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + + bool1_t dst = src0 != 0; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + + bool1_t dst = src0 != 0; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + + bool1_t dst = src0 != 0; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_f2b32(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + + bool32_t dst = src0 != 0; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + + bool32_t dst = src0 != 0; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + + bool32_t dst = src0 != 0; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_f2f16(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + + float16_t dst = src0; + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + + float16_t dst = src0; + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + + float16_t dst = src0; + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_f2f16_rtne(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + + float16_t dst = src0; + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + + float16_t dst = src0; + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + + float16_t dst = src0; + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_f2f16_rtz(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + + float16_t dst = src0; + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + + float16_t dst = src0; + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + + float16_t dst = src0; + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_f2f32(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + + float32_t dst = src0; + + _dst_val.f32[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + + float32_t dst = src0; + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + + float32_t dst = src0; + + _dst_val.f32[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_f2f64(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + + float64_t dst = src0; + + _dst_val.f64[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + + float64_t dst = src0; + + _dst_val.f64[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + + float64_t dst = src0; + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_f2i1(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + + int1_t dst = src0; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + + int1_t dst = src0; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + + int1_t dst = src0; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_f2i16(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + + int16_t dst = src0; + + _dst_val.i16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + + int16_t dst = src0; + + _dst_val.i16[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + + int16_t dst = src0; + + _dst_val.i16[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_f2i32(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + + int32_t dst = src0; + + _dst_val.i32[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + + int32_t dst = src0; + + _dst_val.i32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + + int32_t dst = src0; + + _dst_val.i32[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_f2i64(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + + int64_t dst = src0; + + _dst_val.i64[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + + int64_t dst = src0; + + _dst_val.i64[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + + int64_t dst = src0; + + _dst_val.i64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_f2i8(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + + int8_t dst = src0; + + _dst_val.i8[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + + int8_t dst = src0; + + _dst_val.i8[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + + int8_t dst = src0; + + _dst_val.i8[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_f2u1(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + + uint1_t dst = src0; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + + uint1_t dst = src0; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + + uint1_t dst = src0; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_f2u16(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + + uint16_t dst = src0; + + _dst_val.u16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + + uint16_t dst = src0; + + _dst_val.u16[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + + uint16_t dst = src0; + + _dst_val.u16[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_f2u32(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + + uint32_t dst = src0; + + _dst_val.u32[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + + uint32_t dst = src0; + + _dst_val.u32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + + uint32_t dst = src0; + + _dst_val.u32[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_f2u64(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + + uint64_t dst = src0; + + _dst_val.u64[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + + uint64_t dst = src0; + + _dst_val.u64[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + + uint64_t dst = src0; + + _dst_val.u64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_f2u8(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + + uint8_t dst = src0; + + _dst_val.u8[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + + uint8_t dst = src0; + + _dst_val.u8[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + + uint8_t dst = src0; + + _dst_val.u8[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fabs(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + + float16_t dst = fabs(src0); + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + + float32_t dst = fabs(src0); + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + + float64_t dst = fabs(src0); + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fadd(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + const float src1 = + _mesa_half_to_float(_src[1].u16[_i]); + + float16_t dst = src0 + src1; + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + const float32_t src1 = + _src[1].f32[_i]; + + float32_t dst = src0 + src1; + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + const float64_t src1 = + _src[1].f64[_i]; + + float64_t dst = src0 + src1; + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fall_equal2(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + const struct float32_vec src0 = { + _src[0].f32[0], + _src[0].f32[1], + 0, + 0, + }; + + const struct float32_vec src1 = { + _src[1].f32[0], + _src[1].f32[1], + 0, + 0, + }; + + struct float32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y)) ? 1.0f : 0.0f; + + _dst_val.f32[0] = dst.x; + + + return _dst_val; +} +static nir_const_value +evaluate_fall_equal3(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + const struct float32_vec src0 = { + _src[0].f32[0], + _src[0].f32[1], + _src[0].f32[2], + 0, + }; + + const struct float32_vec src1 = { + _src[1].f32[0], + _src[1].f32[1], + _src[1].f32[2], + 0, + }; + + struct float32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y) && (src0.z == src1.z)) ? 1.0f : 0.0f; + + _dst_val.f32[0] = dst.x; + + + return _dst_val; +} +static nir_const_value +evaluate_fall_equal4(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + const struct float32_vec src0 = { + _src[0].f32[0], + _src[0].f32[1], + _src[0].f32[2], + _src[0].f32[3], + }; + + const struct float32_vec src1 = { + _src[1].f32[0], + _src[1].f32[1], + _src[1].f32[2], + _src[1].f32[3], + }; + + struct float32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x == src1.x) && (src0.y == src1.y) && (src0.z == src1.z) && (src0.w == src1.w)) ? 1.0f : 0.0f; + + _dst_val.f32[0] = dst.x; + + + return _dst_val; +} +static nir_const_value +evaluate_fand(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + const float32_t src1 = + _src[1].f32[_i]; + + float32_t dst = ((src0 != 0.0f) && (src1 != 0.0f)) ? 1.0f : 0.0f; + + _dst_val.f32[_i] = dst; + } + + + return _dst_val; +} +static nir_const_value +evaluate_fany_nequal2(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + const struct float32_vec src0 = { + _src[0].f32[0], + _src[0].f32[1], + 0, + 0, + }; + + const struct float32_vec src1 = { + _src[1].f32[0], + _src[1].f32[1], + 0, + 0, + }; + + struct float32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y)) ? 1.0f : 0.0f; + + _dst_val.f32[0] = dst.x; + + + return _dst_val; +} +static nir_const_value +evaluate_fany_nequal3(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + const struct float32_vec src0 = { + _src[0].f32[0], + _src[0].f32[1], + _src[0].f32[2], + 0, + }; + + const struct float32_vec src1 = { + _src[1].f32[0], + _src[1].f32[1], + _src[1].f32[2], + 0, + }; + + struct float32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y) || (src0.z != src1.z)) ? 1.0f : 0.0f; + + _dst_val.f32[0] = dst.x; + + + return _dst_val; +} +static nir_const_value +evaluate_fany_nequal4(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + const struct float32_vec src0 = { + _src[0].f32[0], + _src[0].f32[1], + _src[0].f32[2], + _src[0].f32[3], + }; + + const struct float32_vec src1 = { + _src[1].f32[0], + _src[1].f32[1], + _src[1].f32[2], + _src[1].f32[3], + }; + + struct float32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x != src1.x) || (src0.y != src1.y) || (src0.z != src1.z) || (src0.w != src1.w)) ? 1.0f : 0.0f; + + _dst_val.f32[0] = dst.x; + + + return _dst_val; +} +static nir_const_value +evaluate_fceil(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + + float16_t dst = bit_size == 64 ? ceil(src0) : ceilf(src0); + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + + float32_t dst = bit_size == 64 ? ceil(src0) : ceilf(src0); + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + + float64_t dst = bit_size == 64 ? ceil(src0) : ceilf(src0); + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fcos(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + + float16_t dst = bit_size == 64 ? cos(src0) : cosf(src0); + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + + float32_t dst = bit_size == 64 ? cos(src0) : cosf(src0); + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + + float64_t dst = bit_size == 64 ? cos(src0) : cosf(src0); + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fcsel(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + const float32_t src1 = + _src[1].f32[_i]; + const float32_t src2 = + _src[2].f32[_i]; + + float32_t dst = (src0 != 0.0f) ? src1 : src2; + + _dst_val.f32[_i] = dst; + } + + + return _dst_val; +} +static nir_const_value +evaluate_fddx(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + + float16_t dst = 0.0; + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + + float32_t dst = 0.0; + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + + float64_t dst = 0.0; + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fddx_coarse(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + + float16_t dst = 0.0; + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + + float32_t dst = 0.0; + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + + float64_t dst = 0.0; + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fddx_fine(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + + float16_t dst = 0.0; + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + + float32_t dst = 0.0; + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + + float64_t dst = 0.0; + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fddy(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + + float16_t dst = 0.0; + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + + float32_t dst = 0.0; + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + + float64_t dst = 0.0; + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fddy_coarse(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + + float16_t dst = 0.0; + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + + float32_t dst = 0.0; + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + + float64_t dst = 0.0; + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fddy_fine(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + + float16_t dst = 0.0; + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + + float32_t dst = 0.0; + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + + float64_t dst = 0.0; + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fdiv(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + const float src1 = + _mesa_half_to_float(_src[1].u16[_i]); + + float16_t dst = src0 / src1; + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + const float32_t src1 = + _src[1].f32[_i]; + + float32_t dst = src0 / src1; + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + const float64_t src1 = + _src[1].f64[_i]; + + float64_t dst = src0 / src1; + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fdot2(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + const struct float16_vec src0 = { + _mesa_half_to_float(_src[0].u16[0]), + _mesa_half_to_float(_src[0].u16[1]), + 0, + 0, + }; + + const struct float16_vec src1 = { + _mesa_half_to_float(_src[1].u16[0]), + _mesa_half_to_float(_src[1].u16[1]), + 0, + 0, + }; + + struct float16_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x * src1.x) + (src0.y * src1.y)); + + _dst_val.u16[0] = _mesa_float_to_half(dst.x); + + break; + } + case 32: { + + + + + const struct float32_vec src0 = { + _src[0].f32[0], + _src[0].f32[1], + 0, + 0, + }; + + const struct float32_vec src1 = { + _src[1].f32[0], + _src[1].f32[1], + 0, + 0, + }; + + struct float32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x * src1.x) + (src0.y * src1.y)); + + _dst_val.f32[0] = dst.x; + + break; + } + case 64: { + + + + + const struct float64_vec src0 = { + _src[0].f64[0], + _src[0].f64[1], + 0, + 0, + }; + + const struct float64_vec src1 = { + _src[1].f64[0], + _src[1].f64[1], + 0, + 0, + }; + + struct float64_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x * src1.x) + (src0.y * src1.y)); + + _dst_val.f64[0] = dst.x; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fdot3(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + const struct float16_vec src0 = { + _mesa_half_to_float(_src[0].u16[0]), + _mesa_half_to_float(_src[0].u16[1]), + _mesa_half_to_float(_src[0].u16[2]), + 0, + }; + + const struct float16_vec src1 = { + _mesa_half_to_float(_src[1].u16[0]), + _mesa_half_to_float(_src[1].u16[1]), + _mesa_half_to_float(_src[1].u16[2]), + 0, + }; + + struct float16_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x * src1.x) + (src0.y * src1.y) + (src0.z * src1.z)); + + _dst_val.u16[0] = _mesa_float_to_half(dst.x); + + break; + } + case 32: { + + + + + const struct float32_vec src0 = { + _src[0].f32[0], + _src[0].f32[1], + _src[0].f32[2], + 0, + }; + + const struct float32_vec src1 = { + _src[1].f32[0], + _src[1].f32[1], + _src[1].f32[2], + 0, + }; + + struct float32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x * src1.x) + (src0.y * src1.y) + (src0.z * src1.z)); + + _dst_val.f32[0] = dst.x; + + break; + } + case 64: { + + + + + const struct float64_vec src0 = { + _src[0].f64[0], + _src[0].f64[1], + _src[0].f64[2], + 0, + }; + + const struct float64_vec src1 = { + _src[1].f64[0], + _src[1].f64[1], + _src[1].f64[2], + 0, + }; + + struct float64_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x * src1.x) + (src0.y * src1.y) + (src0.z * src1.z)); + + _dst_val.f64[0] = dst.x; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fdot4(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + const struct float16_vec src0 = { + _mesa_half_to_float(_src[0].u16[0]), + _mesa_half_to_float(_src[0].u16[1]), + _mesa_half_to_float(_src[0].u16[2]), + _mesa_half_to_float(_src[0].u16[3]), + }; + + const struct float16_vec src1 = { + _mesa_half_to_float(_src[1].u16[0]), + _mesa_half_to_float(_src[1].u16[1]), + _mesa_half_to_float(_src[1].u16[2]), + _mesa_half_to_float(_src[1].u16[3]), + }; + + struct float16_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x * src1.x) + (src0.y * src1.y) + (src0.z * src1.z) + (src0.w * src1.w)); + + _dst_val.u16[0] = _mesa_float_to_half(dst.x); + + break; + } + case 32: { + + + + + const struct float32_vec src0 = { + _src[0].f32[0], + _src[0].f32[1], + _src[0].f32[2], + _src[0].f32[3], + }; + + const struct float32_vec src1 = { + _src[1].f32[0], + _src[1].f32[1], + _src[1].f32[2], + _src[1].f32[3], + }; + + struct float32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x * src1.x) + (src0.y * src1.y) + (src0.z * src1.z) + (src0.w * src1.w)); + + _dst_val.f32[0] = dst.x; + + break; + } + case 64: { + + + + + const struct float64_vec src0 = { + _src[0].f64[0], + _src[0].f64[1], + _src[0].f64[2], + _src[0].f64[3], + }; + + const struct float64_vec src1 = { + _src[1].f64[0], + _src[1].f64[1], + _src[1].f64[2], + _src[1].f64[3], + }; + + struct float64_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x * src1.x) + (src0.y * src1.y) + (src0.z * src1.z) + (src0.w * src1.w)); + + _dst_val.f64[0] = dst.x; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fdot_replicated2(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + const struct float16_vec src0 = { + _mesa_half_to_float(_src[0].u16[0]), + _mesa_half_to_float(_src[0].u16[1]), + 0, + 0, + }; + + const struct float16_vec src1 = { + _mesa_half_to_float(_src[1].u16[0]), + _mesa_half_to_float(_src[1].u16[1]), + 0, + 0, + }; + + struct float16_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x * src1.x) + (src0.y * src1.y)); + + _dst_val.u16[0] = _mesa_float_to_half(dst.x); + _dst_val.u16[1] = _mesa_float_to_half(dst.y); + _dst_val.u16[2] = _mesa_float_to_half(dst.z); + _dst_val.u16[3] = _mesa_float_to_half(dst.w); + + break; + } + case 32: { + + + + + const struct float32_vec src0 = { + _src[0].f32[0], + _src[0].f32[1], + 0, + 0, + }; + + const struct float32_vec src1 = { + _src[1].f32[0], + _src[1].f32[1], + 0, + 0, + }; + + struct float32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x * src1.x) + (src0.y * src1.y)); + + _dst_val.f32[0] = dst.x; + _dst_val.f32[1] = dst.y; + _dst_val.f32[2] = dst.z; + _dst_val.f32[3] = dst.w; + + break; + } + case 64: { + + + + + const struct float64_vec src0 = { + _src[0].f64[0], + _src[0].f64[1], + 0, + 0, + }; + + const struct float64_vec src1 = { + _src[1].f64[0], + _src[1].f64[1], + 0, + 0, + }; + + struct float64_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x * src1.x) + (src0.y * src1.y)); + + _dst_val.f64[0] = dst.x; + _dst_val.f64[1] = dst.y; + _dst_val.f64[2] = dst.z; + _dst_val.f64[3] = dst.w; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fdot_replicated3(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + const struct float16_vec src0 = { + _mesa_half_to_float(_src[0].u16[0]), + _mesa_half_to_float(_src[0].u16[1]), + _mesa_half_to_float(_src[0].u16[2]), + 0, + }; + + const struct float16_vec src1 = { + _mesa_half_to_float(_src[1].u16[0]), + _mesa_half_to_float(_src[1].u16[1]), + _mesa_half_to_float(_src[1].u16[2]), + 0, + }; + + struct float16_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x * src1.x) + (src0.y * src1.y) + (src0.z * src1.z)); + + _dst_val.u16[0] = _mesa_float_to_half(dst.x); + _dst_val.u16[1] = _mesa_float_to_half(dst.y); + _dst_val.u16[2] = _mesa_float_to_half(dst.z); + _dst_val.u16[3] = _mesa_float_to_half(dst.w); + + break; + } + case 32: { + + + + + const struct float32_vec src0 = { + _src[0].f32[0], + _src[0].f32[1], + _src[0].f32[2], + 0, + }; + + const struct float32_vec src1 = { + _src[1].f32[0], + _src[1].f32[1], + _src[1].f32[2], + 0, + }; + + struct float32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x * src1.x) + (src0.y * src1.y) + (src0.z * src1.z)); + + _dst_val.f32[0] = dst.x; + _dst_val.f32[1] = dst.y; + _dst_val.f32[2] = dst.z; + _dst_val.f32[3] = dst.w; + + break; + } + case 64: { + + + + + const struct float64_vec src0 = { + _src[0].f64[0], + _src[0].f64[1], + _src[0].f64[2], + 0, + }; + + const struct float64_vec src1 = { + _src[1].f64[0], + _src[1].f64[1], + _src[1].f64[2], + 0, + }; + + struct float64_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x * src1.x) + (src0.y * src1.y) + (src0.z * src1.z)); + + _dst_val.f64[0] = dst.x; + _dst_val.f64[1] = dst.y; + _dst_val.f64[2] = dst.z; + _dst_val.f64[3] = dst.w; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fdot_replicated4(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + const struct float16_vec src0 = { + _mesa_half_to_float(_src[0].u16[0]), + _mesa_half_to_float(_src[0].u16[1]), + _mesa_half_to_float(_src[0].u16[2]), + _mesa_half_to_float(_src[0].u16[3]), + }; + + const struct float16_vec src1 = { + _mesa_half_to_float(_src[1].u16[0]), + _mesa_half_to_float(_src[1].u16[1]), + _mesa_half_to_float(_src[1].u16[2]), + _mesa_half_to_float(_src[1].u16[3]), + }; + + struct float16_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x * src1.x) + (src0.y * src1.y) + (src0.z * src1.z) + (src0.w * src1.w)); + + _dst_val.u16[0] = _mesa_float_to_half(dst.x); + _dst_val.u16[1] = _mesa_float_to_half(dst.y); + _dst_val.u16[2] = _mesa_float_to_half(dst.z); + _dst_val.u16[3] = _mesa_float_to_half(dst.w); + + break; + } + case 32: { + + + + + const struct float32_vec src0 = { + _src[0].f32[0], + _src[0].f32[1], + _src[0].f32[2], + _src[0].f32[3], + }; + + const struct float32_vec src1 = { + _src[1].f32[0], + _src[1].f32[1], + _src[1].f32[2], + _src[1].f32[3], + }; + + struct float32_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x * src1.x) + (src0.y * src1.y) + (src0.z * src1.z) + (src0.w * src1.w)); + + _dst_val.f32[0] = dst.x; + _dst_val.f32[1] = dst.y; + _dst_val.f32[2] = dst.z; + _dst_val.f32[3] = dst.w; + + break; + } + case 64: { + + + + + const struct float64_vec src0 = { + _src[0].f64[0], + _src[0].f64[1], + _src[0].f64[2], + _src[0].f64[3], + }; + + const struct float64_vec src1 = { + _src[1].f64[0], + _src[1].f64[1], + _src[1].f64[2], + _src[1].f64[3], + }; + + struct float64_vec dst; + + dst.x = dst.y = dst.z = dst.w = ((src0.x * src1.x) + (src0.y * src1.y) + (src0.z * src1.z) + (src0.w * src1.w)); + + _dst_val.f64[0] = dst.x; + _dst_val.f64[1] = dst.y; + _dst_val.f64[2] = dst.z; + _dst_val.f64[3] = dst.w; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fdph(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + const struct float16_vec src0 = { + _mesa_half_to_float(_src[0].u16[0]), + _mesa_half_to_float(_src[0].u16[1]), + _mesa_half_to_float(_src[0].u16[2]), + 0, + }; + + const struct float16_vec src1 = { + _mesa_half_to_float(_src[1].u16[0]), + _mesa_half_to_float(_src[1].u16[1]), + _mesa_half_to_float(_src[1].u16[2]), + _mesa_half_to_float(_src[1].u16[3]), + }; + + struct float16_vec dst; + + dst.x = dst.y = dst.z = dst.w = src0.x * src1.x + src0.y * src1.y + src0.z * src1.z + src1.w; + + _dst_val.u16[0] = _mesa_float_to_half(dst.x); + + break; + } + case 32: { + + + + + const struct float32_vec src0 = { + _src[0].f32[0], + _src[0].f32[1], + _src[0].f32[2], + 0, + }; + + const struct float32_vec src1 = { + _src[1].f32[0], + _src[1].f32[1], + _src[1].f32[2], + _src[1].f32[3], + }; + + struct float32_vec dst; + + dst.x = dst.y = dst.z = dst.w = src0.x * src1.x + src0.y * src1.y + src0.z * src1.z + src1.w; + + _dst_val.f32[0] = dst.x; + + break; + } + case 64: { + + + + + const struct float64_vec src0 = { + _src[0].f64[0], + _src[0].f64[1], + _src[0].f64[2], + 0, + }; + + const struct float64_vec src1 = { + _src[1].f64[0], + _src[1].f64[1], + _src[1].f64[2], + _src[1].f64[3], + }; + + struct float64_vec dst; + + dst.x = dst.y = dst.z = dst.w = src0.x * src1.x + src0.y * src1.y + src0.z * src1.z + src1.w; + + _dst_val.f64[0] = dst.x; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fdph_replicated(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + const struct float16_vec src0 = { + _mesa_half_to_float(_src[0].u16[0]), + _mesa_half_to_float(_src[0].u16[1]), + _mesa_half_to_float(_src[0].u16[2]), + 0, + }; + + const struct float16_vec src1 = { + _mesa_half_to_float(_src[1].u16[0]), + _mesa_half_to_float(_src[1].u16[1]), + _mesa_half_to_float(_src[1].u16[2]), + _mesa_half_to_float(_src[1].u16[3]), + }; + + struct float16_vec dst; + + dst.x = dst.y = dst.z = dst.w = src0.x * src1.x + src0.y * src1.y + src0.z * src1.z + src1.w; + + _dst_val.u16[0] = _mesa_float_to_half(dst.x); + _dst_val.u16[1] = _mesa_float_to_half(dst.y); + _dst_val.u16[2] = _mesa_float_to_half(dst.z); + _dst_val.u16[3] = _mesa_float_to_half(dst.w); + + break; + } + case 32: { + + + + + const struct float32_vec src0 = { + _src[0].f32[0], + _src[0].f32[1], + _src[0].f32[2], + 0, + }; + + const struct float32_vec src1 = { + _src[1].f32[0], + _src[1].f32[1], + _src[1].f32[2], + _src[1].f32[3], + }; + + struct float32_vec dst; + + dst.x = dst.y = dst.z = dst.w = src0.x * src1.x + src0.y * src1.y + src0.z * src1.z + src1.w; + + _dst_val.f32[0] = dst.x; + _dst_val.f32[1] = dst.y; + _dst_val.f32[2] = dst.z; + _dst_val.f32[3] = dst.w; + + break; + } + case 64: { + + + + + const struct float64_vec src0 = { + _src[0].f64[0], + _src[0].f64[1], + _src[0].f64[2], + 0, + }; + + const struct float64_vec src1 = { + _src[1].f64[0], + _src[1].f64[1], + _src[1].f64[2], + _src[1].f64[3], + }; + + struct float64_vec dst; + + dst.x = dst.y = dst.z = dst.w = src0.x * src1.x + src0.y * src1.y + src0.z * src1.z + src1.w; + + _dst_val.f64[0] = dst.x; + _dst_val.f64[1] = dst.y; + _dst_val.f64[2] = dst.z; + _dst_val.f64[3] = dst.w; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_feq(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + const float src1 = + _mesa_half_to_float(_src[1].u16[_i]); + + bool1_t dst = src0 == src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + const float32_t src1 = + _src[1].f32[_i]; + + bool1_t dst = src0 == src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + const float64_t src1 = + _src[1].f64[_i]; + + bool1_t dst = src0 == src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_feq32(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + const float src1 = + _mesa_half_to_float(_src[1].u16[_i]); + + bool32_t dst = src0 == src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + const float32_t src1 = + _src[1].f32[_i]; + + bool32_t dst = src0 == src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + const float64_t src1 = + _src[1].f64[_i]; + + bool32_t dst = src0 == src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fexp2(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + + float16_t dst = exp2f(src0); + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + + float32_t dst = exp2f(src0); + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + + float64_t dst = exp2f(src0); + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_ffloor(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + + float16_t dst = bit_size == 64 ? floor(src0) : floorf(src0); + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + + float32_t dst = bit_size == 64 ? floor(src0) : floorf(src0); + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + + float64_t dst = bit_size == 64 ? floor(src0) : floorf(src0); + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_ffma(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + const float src1 = + _mesa_half_to_float(_src[1].u16[_i]); + const float src2 = + _mesa_half_to_float(_src[2].u16[_i]); + + float16_t dst = src0 * src1 + src2; + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + const float32_t src1 = + _src[1].f32[_i]; + const float32_t src2 = + _src[2].f32[_i]; + + float32_t dst = src0 * src1 + src2; + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + const float64_t src1 = + _src[1].f64[_i]; + const float64_t src2 = + _src[2].f64[_i]; + + float64_t dst = src0 * src1 + src2; + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_ffract(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + + float16_t dst = src0 - (bit_size == 64 ? floor(src0) : floorf(src0)); + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + + float32_t dst = src0 - (bit_size == 64 ? floor(src0) : floorf(src0)); + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + + float64_t dst = src0 - (bit_size == 64 ? floor(src0) : floorf(src0)); + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fge(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + const float src1 = + _mesa_half_to_float(_src[1].u16[_i]); + + bool1_t dst = src0 >= src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + const float32_t src1 = + _src[1].f32[_i]; + + bool1_t dst = src0 >= src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + const float64_t src1 = + _src[1].f64[_i]; + + bool1_t dst = src0 >= src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fge32(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + const float src1 = + _mesa_half_to_float(_src[1].u16[_i]); + + bool32_t dst = src0 >= src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + const float32_t src1 = + _src[1].f32[_i]; + + bool32_t dst = src0 >= src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + const float64_t src1 = + _src[1].f64[_i]; + + bool32_t dst = src0 >= src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_find_lsb(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + + int32_t dst; + + +dst = -1; +for (unsigned bit = 0; bit < bit_size; bit++) { + if ((src0 >> bit) & 1) { + dst = bit; + break; + } +} + + + _dst_val.i32[_i] = dst; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + + int32_t dst; + + +dst = -1; +for (unsigned bit = 0; bit < bit_size; bit++) { + if ((src0 >> bit) & 1) { + dst = bit; + break; + } +} + + + _dst_val.i32[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + + int32_t dst; + + +dst = -1; +for (unsigned bit = 0; bit < bit_size; bit++) { + if ((src0 >> bit) & 1) { + dst = bit; + break; + } +} + + + _dst_val.i32[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + + int32_t dst; + + +dst = -1; +for (unsigned bit = 0; bit < bit_size; bit++) { + if ((src0 >> bit) & 1) { + dst = bit; + break; + } +} + + + _dst_val.i32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + + int32_t dst; + + +dst = -1; +for (unsigned bit = 0; bit < bit_size; bit++) { + if ((src0 >> bit) & 1) { + dst = bit; + break; + } +} + + + _dst_val.i32[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_flog2(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + + float16_t dst = log2f(src0); + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + + float32_t dst = log2f(src0); + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + + float64_t dst = log2f(src0); + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_flrp(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + const float src1 = + _mesa_half_to_float(_src[1].u16[_i]); + const float src2 = + _mesa_half_to_float(_src[2].u16[_i]); + + float16_t dst = src0 * (1 - src2) + src1 * src2; + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + const float32_t src1 = + _src[1].f32[_i]; + const float32_t src2 = + _src[2].f32[_i]; + + float32_t dst = src0 * (1 - src2) + src1 * src2; + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + const float64_t src1 = + _src[1].f64[_i]; + const float64_t src2 = + _src[2].f64[_i]; + + float64_t dst = src0 * (1 - src2) + src1 * src2; + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_flt(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + const float src1 = + _mesa_half_to_float(_src[1].u16[_i]); + + bool1_t dst = src0 < src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + const float32_t src1 = + _src[1].f32[_i]; + + bool1_t dst = src0 < src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + const float64_t src1 = + _src[1].f64[_i]; + + bool1_t dst = src0 < src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_flt32(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + const float src1 = + _mesa_half_to_float(_src[1].u16[_i]); + + bool32_t dst = src0 < src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + const float32_t src1 = + _src[1].f32[_i]; + + bool32_t dst = src0 < src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + const float64_t src1 = + _src[1].f64[_i]; + + bool32_t dst = src0 < src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fmax(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + const float src1 = + _mesa_half_to_float(_src[1].u16[_i]); + + float16_t dst = fmaxf(src0, src1); + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + const float32_t src1 = + _src[1].f32[_i]; + + float32_t dst = fmaxf(src0, src1); + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + const float64_t src1 = + _src[1].f64[_i]; + + float64_t dst = fmaxf(src0, src1); + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fmax3(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + const float src1 = + _mesa_half_to_float(_src[1].u16[_i]); + const float src2 = + _mesa_half_to_float(_src[2].u16[_i]); + + float16_t dst = fmaxf(src0, fmaxf(src1, src2)); + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + const float32_t src1 = + _src[1].f32[_i]; + const float32_t src2 = + _src[2].f32[_i]; + + float32_t dst = fmaxf(src0, fmaxf(src1, src2)); + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + const float64_t src1 = + _src[1].f64[_i]; + const float64_t src2 = + _src[2].f64[_i]; + + float64_t dst = fmaxf(src0, fmaxf(src1, src2)); + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fmed3(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + const float src1 = + _mesa_half_to_float(_src[1].u16[_i]); + const float src2 = + _mesa_half_to_float(_src[2].u16[_i]); + + float16_t dst = fmaxf(fminf(fmaxf(src0, src1), src2), fminf(src0, src1)); + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + const float32_t src1 = + _src[1].f32[_i]; + const float32_t src2 = + _src[2].f32[_i]; + + float32_t dst = fmaxf(fminf(fmaxf(src0, src1), src2), fminf(src0, src1)); + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + const float64_t src1 = + _src[1].f64[_i]; + const float64_t src2 = + _src[2].f64[_i]; + + float64_t dst = fmaxf(fminf(fmaxf(src0, src1), src2), fminf(src0, src1)); + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fmin(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + const float src1 = + _mesa_half_to_float(_src[1].u16[_i]); + + float16_t dst = fminf(src0, src1); + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + const float32_t src1 = + _src[1].f32[_i]; + + float32_t dst = fminf(src0, src1); + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + const float64_t src1 = + _src[1].f64[_i]; + + float64_t dst = fminf(src0, src1); + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fmin3(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + const float src1 = + _mesa_half_to_float(_src[1].u16[_i]); + const float src2 = + _mesa_half_to_float(_src[2].u16[_i]); + + float16_t dst = fminf(src0, fminf(src1, src2)); + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + const float32_t src1 = + _src[1].f32[_i]; + const float32_t src2 = + _src[2].f32[_i]; + + float32_t dst = fminf(src0, fminf(src1, src2)); + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + const float64_t src1 = + _src[1].f64[_i]; + const float64_t src2 = + _src[2].f64[_i]; + + float64_t dst = fminf(src0, fminf(src1, src2)); + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fmod(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + const float src1 = + _mesa_half_to_float(_src[1].u16[_i]); + + float16_t dst = src0 - src1 * floorf(src0 / src1); + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + const float32_t src1 = + _src[1].f32[_i]; + + float32_t dst = src0 - src1 * floorf(src0 / src1); + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + const float64_t src1 = + _src[1].f64[_i]; + + float64_t dst = src0 - src1 * floorf(src0 / src1); + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fmov(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + + float16_t dst = src0; + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + + float32_t dst = src0; + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + + float64_t dst = src0; + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fmul(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + const float src1 = + _mesa_half_to_float(_src[1].u16[_i]); + + float16_t dst = src0 * src1; + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + const float32_t src1 = + _src[1].f32[_i]; + + float32_t dst = src0 * src1; + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + const float64_t src1 = + _src[1].f64[_i]; + + float64_t dst = src0 * src1; + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fne(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + const float src1 = + _mesa_half_to_float(_src[1].u16[_i]); + + bool1_t dst = src0 != src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + const float32_t src1 = + _src[1].f32[_i]; + + bool1_t dst = src0 != src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + const float64_t src1 = + _src[1].f64[_i]; + + bool1_t dst = src0 != src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fne32(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + const float src1 = + _mesa_half_to_float(_src[1].u16[_i]); + + bool32_t dst = src0 != src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + const float32_t src1 = + _src[1].f32[_i]; + + bool32_t dst = src0 != src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + const float64_t src1 = + _src[1].f64[_i]; + + bool32_t dst = src0 != src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fneg(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + + float16_t dst = -src0; + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + + float32_t dst = -src0; + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + + float64_t dst = -src0; + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fnoise1_1(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + struct float16_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.u16[0] = _mesa_float_to_half(dst.x); + + break; + } + case 32: { + + + + + struct float32_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.f32[0] = dst.x; + + break; + } + case 64: { + + + + + struct float64_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.f64[0] = dst.x; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fnoise1_2(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + struct float16_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.u16[0] = _mesa_float_to_half(dst.x); + + break; + } + case 32: { + + + + + struct float32_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.f32[0] = dst.x; + + break; + } + case 64: { + + + + + struct float64_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.f64[0] = dst.x; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fnoise1_3(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + struct float16_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.u16[0] = _mesa_float_to_half(dst.x); + + break; + } + case 32: { + + + + + struct float32_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.f32[0] = dst.x; + + break; + } + case 64: { + + + + + struct float64_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.f64[0] = dst.x; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fnoise1_4(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + struct float16_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.u16[0] = _mesa_float_to_half(dst.x); + + break; + } + case 32: { + + + + + struct float32_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.f32[0] = dst.x; + + break; + } + case 64: { + + + + + struct float64_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.f64[0] = dst.x; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fnoise2_1(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + struct float16_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.u16[0] = _mesa_float_to_half(dst.x); + _dst_val.u16[1] = _mesa_float_to_half(dst.y); + + break; + } + case 32: { + + + + + struct float32_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.f32[0] = dst.x; + _dst_val.f32[1] = dst.y; + + break; + } + case 64: { + + + + + struct float64_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.f64[0] = dst.x; + _dst_val.f64[1] = dst.y; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fnoise2_2(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + struct float16_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.u16[0] = _mesa_float_to_half(dst.x); + _dst_val.u16[1] = _mesa_float_to_half(dst.y); + + break; + } + case 32: { + + + + + struct float32_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.f32[0] = dst.x; + _dst_val.f32[1] = dst.y; + + break; + } + case 64: { + + + + + struct float64_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.f64[0] = dst.x; + _dst_val.f64[1] = dst.y; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fnoise2_3(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + struct float16_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.u16[0] = _mesa_float_to_half(dst.x); + _dst_val.u16[1] = _mesa_float_to_half(dst.y); + + break; + } + case 32: { + + + + + struct float32_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.f32[0] = dst.x; + _dst_val.f32[1] = dst.y; + + break; + } + case 64: { + + + + + struct float64_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.f64[0] = dst.x; + _dst_val.f64[1] = dst.y; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fnoise2_4(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + struct float16_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.u16[0] = _mesa_float_to_half(dst.x); + _dst_val.u16[1] = _mesa_float_to_half(dst.y); + + break; + } + case 32: { + + + + + struct float32_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.f32[0] = dst.x; + _dst_val.f32[1] = dst.y; + + break; + } + case 64: { + + + + + struct float64_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.f64[0] = dst.x; + _dst_val.f64[1] = dst.y; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fnoise3_1(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + struct float16_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.u16[0] = _mesa_float_to_half(dst.x); + _dst_val.u16[1] = _mesa_float_to_half(dst.y); + _dst_val.u16[2] = _mesa_float_to_half(dst.z); + + break; + } + case 32: { + + + + + struct float32_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.f32[0] = dst.x; + _dst_val.f32[1] = dst.y; + _dst_val.f32[2] = dst.z; + + break; + } + case 64: { + + + + + struct float64_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.f64[0] = dst.x; + _dst_val.f64[1] = dst.y; + _dst_val.f64[2] = dst.z; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fnoise3_2(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + struct float16_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.u16[0] = _mesa_float_to_half(dst.x); + _dst_val.u16[1] = _mesa_float_to_half(dst.y); + _dst_val.u16[2] = _mesa_float_to_half(dst.z); + + break; + } + case 32: { + + + + + struct float32_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.f32[0] = dst.x; + _dst_val.f32[1] = dst.y; + _dst_val.f32[2] = dst.z; + + break; + } + case 64: { + + + + + struct float64_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.f64[0] = dst.x; + _dst_val.f64[1] = dst.y; + _dst_val.f64[2] = dst.z; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fnoise3_3(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + struct float16_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.u16[0] = _mesa_float_to_half(dst.x); + _dst_val.u16[1] = _mesa_float_to_half(dst.y); + _dst_val.u16[2] = _mesa_float_to_half(dst.z); + + break; + } + case 32: { + + + + + struct float32_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.f32[0] = dst.x; + _dst_val.f32[1] = dst.y; + _dst_val.f32[2] = dst.z; + + break; + } + case 64: { + + + + + struct float64_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.f64[0] = dst.x; + _dst_val.f64[1] = dst.y; + _dst_val.f64[2] = dst.z; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fnoise3_4(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + struct float16_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.u16[0] = _mesa_float_to_half(dst.x); + _dst_val.u16[1] = _mesa_float_to_half(dst.y); + _dst_val.u16[2] = _mesa_float_to_half(dst.z); + + break; + } + case 32: { + + + + + struct float32_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.f32[0] = dst.x; + _dst_val.f32[1] = dst.y; + _dst_val.f32[2] = dst.z; + + break; + } + case 64: { + + + + + struct float64_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.f64[0] = dst.x; + _dst_val.f64[1] = dst.y; + _dst_val.f64[2] = dst.z; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fnoise4_1(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + struct float16_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.u16[0] = _mesa_float_to_half(dst.x); + _dst_val.u16[1] = _mesa_float_to_half(dst.y); + _dst_val.u16[2] = _mesa_float_to_half(dst.z); + _dst_val.u16[3] = _mesa_float_to_half(dst.w); + + break; + } + case 32: { + + + + + struct float32_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.f32[0] = dst.x; + _dst_val.f32[1] = dst.y; + _dst_val.f32[2] = dst.z; + _dst_val.f32[3] = dst.w; + + break; + } + case 64: { + + + + + struct float64_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.f64[0] = dst.x; + _dst_val.f64[1] = dst.y; + _dst_val.f64[2] = dst.z; + _dst_val.f64[3] = dst.w; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fnoise4_2(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + struct float16_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.u16[0] = _mesa_float_to_half(dst.x); + _dst_val.u16[1] = _mesa_float_to_half(dst.y); + _dst_val.u16[2] = _mesa_float_to_half(dst.z); + _dst_val.u16[3] = _mesa_float_to_half(dst.w); + + break; + } + case 32: { + + + + + struct float32_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.f32[0] = dst.x; + _dst_val.f32[1] = dst.y; + _dst_val.f32[2] = dst.z; + _dst_val.f32[3] = dst.w; + + break; + } + case 64: { + + + + + struct float64_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.f64[0] = dst.x; + _dst_val.f64[1] = dst.y; + _dst_val.f64[2] = dst.z; + _dst_val.f64[3] = dst.w; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fnoise4_3(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + struct float16_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.u16[0] = _mesa_float_to_half(dst.x); + _dst_val.u16[1] = _mesa_float_to_half(dst.y); + _dst_val.u16[2] = _mesa_float_to_half(dst.z); + _dst_val.u16[3] = _mesa_float_to_half(dst.w); + + break; + } + case 32: { + + + + + struct float32_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.f32[0] = dst.x; + _dst_val.f32[1] = dst.y; + _dst_val.f32[2] = dst.z; + _dst_val.f32[3] = dst.w; + + break; + } + case 64: { + + + + + struct float64_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.f64[0] = dst.x; + _dst_val.f64[1] = dst.y; + _dst_val.f64[2] = dst.z; + _dst_val.f64[3] = dst.w; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fnoise4_4(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + struct float16_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.u16[0] = _mesa_float_to_half(dst.x); + _dst_val.u16[1] = _mesa_float_to_half(dst.y); + _dst_val.u16[2] = _mesa_float_to_half(dst.z); + _dst_val.u16[3] = _mesa_float_to_half(dst.w); + + break; + } + case 32: { + + + + + struct float32_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.f32[0] = dst.x; + _dst_val.f32[1] = dst.y; + _dst_val.f32[2] = dst.z; + _dst_val.f32[3] = dst.w; + + break; + } + case 64: { + + + + + struct float64_vec dst; + + dst.x = dst.y = dst.z = dst.w = 0.0f; + + _dst_val.f64[0] = dst.x; + _dst_val.f64[1] = dst.y; + _dst_val.f64[2] = dst.z; + _dst_val.f64[3] = dst.w; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fnot(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + + float16_t dst = bit_size == 64 ? ((src0 == 0.0) ? 1.0 : 0.0f) : ((src0 == 0.0f) ? 1.0f : 0.0f); + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + + float32_t dst = bit_size == 64 ? ((src0 == 0.0) ? 1.0 : 0.0f) : ((src0 == 0.0f) ? 1.0f : 0.0f); + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + + float64_t dst = bit_size == 64 ? ((src0 == 0.0) ? 1.0 : 0.0f) : ((src0 == 0.0f) ? 1.0f : 0.0f); + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_for(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + const float32_t src1 = + _src[1].f32[_i]; + + float32_t dst = ((src0 != 0.0f) || (src1 != 0.0f)) ? 1.0f : 0.0f; + + _dst_val.f32[_i] = dst; + } + + + return _dst_val; +} +static nir_const_value +evaluate_fpow(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + const float src1 = + _mesa_half_to_float(_src[1].u16[_i]); + + float16_t dst = bit_size == 64 ? powf(src0, src1) : pow(src0, src1); + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + const float32_t src1 = + _src[1].f32[_i]; + + float32_t dst = bit_size == 64 ? powf(src0, src1) : pow(src0, src1); + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + const float64_t src1 = + _src[1].f64[_i]; + + float64_t dst = bit_size == 64 ? powf(src0, src1) : pow(src0, src1); + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fquantize2f16(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + + float16_t dst = (fabs(src0) < ldexpf(1.0, -14)) ? copysignf(0.0f, src0) : _mesa_half_to_float(_mesa_float_to_half(src0)); + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + + float32_t dst = (fabs(src0) < ldexpf(1.0, -14)) ? copysignf(0.0f, src0) : _mesa_half_to_float(_mesa_float_to_half(src0)); + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + + float64_t dst = (fabs(src0) < ldexpf(1.0, -14)) ? copysignf(0.0f, src0) : _mesa_half_to_float(_mesa_float_to_half(src0)); + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_frcp(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + + float16_t dst = bit_size == 64 ? 1.0 / src0 : 1.0f / src0; + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + + float32_t dst = bit_size == 64 ? 1.0 / src0 : 1.0f / src0; + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + + float64_t dst = bit_size == 64 ? 1.0 / src0 : 1.0f / src0; + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_frem(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + const float src1 = + _mesa_half_to_float(_src[1].u16[_i]); + + float16_t dst = src0 - src1 * truncf(src0 / src1); + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + const float32_t src1 = + _src[1].f32[_i]; + + float32_t dst = src0 - src1 * truncf(src0 / src1); + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + const float64_t src1 = + _src[1].f64[_i]; + + float64_t dst = src0 - src1 * truncf(src0 / src1); + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_frexp_exp(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + + int32_t dst; + + frexp(src0, &dst); + + _dst_val.i32[_i] = dst; + } + + + return _dst_val; +} +static nir_const_value +evaluate_frexp_sig(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + + float64_t dst; + + int n; dst = frexp(src0, &n); + + _dst_val.f64[_i] = dst; + } + + + return _dst_val; +} +static nir_const_value +evaluate_fround_even(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + + float16_t dst = bit_size == 64 ? _mesa_roundeven(src0) : _mesa_roundevenf(src0); + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + + float32_t dst = bit_size == 64 ? _mesa_roundeven(src0) : _mesa_roundevenf(src0); + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + + float64_t dst = bit_size == 64 ? _mesa_roundeven(src0) : _mesa_roundevenf(src0); + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_frsq(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + + float16_t dst = bit_size == 64 ? 1.0 / sqrt(src0) : 1.0f / sqrtf(src0); + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + + float32_t dst = bit_size == 64 ? 1.0 / sqrt(src0) : 1.0f / sqrtf(src0); + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + + float64_t dst = bit_size == 64 ? 1.0 / sqrt(src0) : 1.0f / sqrtf(src0); + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fsat(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + + float16_t dst = bit_size == 64 ? ((src0 > 1.0) ? 1.0 : ((src0 <= 0.0) ? 0.0 : src0)) : ((src0 > 1.0f) ? 1.0f : ((src0 <= 0.0f) ? 0.0f : src0)); + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + + float32_t dst = bit_size == 64 ? ((src0 > 1.0) ? 1.0 : ((src0 <= 0.0) ? 0.0 : src0)) : ((src0 > 1.0f) ? 1.0f : ((src0 <= 0.0f) ? 0.0f : src0)); + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + + float64_t dst = bit_size == 64 ? ((src0 > 1.0) ? 1.0 : ((src0 <= 0.0) ? 0.0 : src0)) : ((src0 > 1.0f) ? 1.0f : ((src0 <= 0.0f) ? 0.0f : src0)); + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fsign(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + + float16_t dst = bit_size == 64 ? ((src0 == 0.0) ? 0.0 : ((src0 > 0.0) ? 1.0 : -1.0)) : ((src0 == 0.0f) ? 0.0f : ((src0 > 0.0f) ? 1.0f : -1.0f)); + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + + float32_t dst = bit_size == 64 ? ((src0 == 0.0) ? 0.0 : ((src0 > 0.0) ? 1.0 : -1.0)) : ((src0 == 0.0f) ? 0.0f : ((src0 > 0.0f) ? 1.0f : -1.0f)); + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + + float64_t dst = bit_size == 64 ? ((src0 == 0.0) ? 0.0 : ((src0 > 0.0) ? 1.0 : -1.0)) : ((src0 == 0.0f) ? 0.0f : ((src0 > 0.0f) ? 1.0f : -1.0f)); + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fsin(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + + float16_t dst = bit_size == 64 ? sin(src0) : sinf(src0); + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + + float32_t dst = bit_size == 64 ? sin(src0) : sinf(src0); + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + + float64_t dst = bit_size == 64 ? sin(src0) : sinf(src0); + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fsqrt(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + + float16_t dst = bit_size == 64 ? sqrt(src0) : sqrtf(src0); + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + + float32_t dst = bit_size == 64 ? sqrt(src0) : sqrtf(src0); + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + + float64_t dst = bit_size == 64 ? sqrt(src0) : sqrtf(src0); + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fsub(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + const float src1 = + _mesa_half_to_float(_src[1].u16[_i]); + + float16_t dst = src0 - src1; + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + const float32_t src1 = + _src[1].f32[_i]; + + float32_t dst = src0 - src1; + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + const float64_t src1 = + _src[1].f64[_i]; + + float64_t dst = src0 - src1; + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_ftrunc(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + + float16_t dst = bit_size == 64 ? trunc(src0) : truncf(src0); + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + + float32_t dst = bit_size == 64 ? trunc(src0) : truncf(src0); + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + + float64_t dst = bit_size == 64 ? trunc(src0) : truncf(src0); + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_fxor(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + const float32_t src1 = + _src[1].f32[_i]; + + float32_t dst = (src0 != 0.0f && src1 == 0.0f) || (src0 == 0.0f && src1 != 0.0f) ? 1.0f : 0.0f; + + _dst_val.f32[_i] = dst; + } + + + return _dst_val; +} +static nir_const_value +evaluate_i2b1(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + + bool1_t dst = src0 != 0; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + + bool1_t dst = src0 != 0; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + + bool1_t dst = src0 != 0; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + + bool1_t dst = src0 != 0; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + + bool1_t dst = src0 != 0; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_i2b32(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + + bool32_t dst = src0 != 0; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + + bool32_t dst = src0 != 0; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + + bool32_t dst = src0 != 0; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + + bool32_t dst = src0 != 0; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + + bool32_t dst = src0 != 0; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_i2f16(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + + float16_t dst = src0; + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + + float16_t dst = src0; + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + + float16_t dst = src0; + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + + float16_t dst = src0; + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + + float16_t dst = src0; + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_i2f32(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + + float32_t dst = src0; + + _dst_val.f32[_i] = dst; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + + float32_t dst = src0; + + _dst_val.f32[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + + float32_t dst = src0; + + _dst_val.f32[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + + float32_t dst = src0; + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + + float32_t dst = src0; + + _dst_val.f32[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_i2f64(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + + float64_t dst = src0; + + _dst_val.f64[_i] = dst; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + + float64_t dst = src0; + + _dst_val.f64[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + + float64_t dst = src0; + + _dst_val.f64[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + + float64_t dst = src0; + + _dst_val.f64[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + + float64_t dst = src0; + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_i2i1(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + + int1_t dst = src0; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + + int1_t dst = src0; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + + int1_t dst = src0; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + + int1_t dst = src0; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + + int1_t dst = src0; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_i2i16(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + + int16_t dst = src0; + + _dst_val.i16[_i] = dst; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + + int16_t dst = src0; + + _dst_val.i16[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + + int16_t dst = src0; + + _dst_val.i16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + + int16_t dst = src0; + + _dst_val.i16[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + + int16_t dst = src0; + + _dst_val.i16[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_i2i32(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + + int32_t dst = src0; + + _dst_val.i32[_i] = dst; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + + int32_t dst = src0; + + _dst_val.i32[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + + int32_t dst = src0; + + _dst_val.i32[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + + int32_t dst = src0; + + _dst_val.i32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + + int32_t dst = src0; + + _dst_val.i32[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_i2i64(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + + int64_t dst = src0; + + _dst_val.i64[_i] = dst; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + + int64_t dst = src0; + + _dst_val.i64[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + + int64_t dst = src0; + + _dst_val.i64[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + + int64_t dst = src0; + + _dst_val.i64[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + + int64_t dst = src0; + + _dst_val.i64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_i2i8(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + + int8_t dst = src0; + + _dst_val.i8[_i] = dst; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + + int8_t dst = src0; + + _dst_val.i8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + + int8_t dst = src0; + + _dst_val.i8[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + + int8_t dst = src0; + + _dst_val.i8[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + + int8_t dst = src0; + + _dst_val.i8[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_iabs(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + + int1_t dst = (src0 < 0) ? -src0 : src0; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + + int8_t dst = (src0 < 0) ? -src0 : src0; + + _dst_val.i8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + + int16_t dst = (src0 < 0) ? -src0 : src0; + + _dst_val.i16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + + int32_t dst = (src0 < 0) ? -src0 : src0; + + _dst_val.i32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + + int64_t dst = (src0 < 0) ? -src0 : src0; + + _dst_val.i64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_iadd(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + /* 1-bit integers use a 0/-1 convention */ + const int1_t src1 = -(int1_t)_src[1].b[_i]; + + int1_t dst = src0 + src1; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + const int8_t src1 = + _src[1].i8[_i]; + + int8_t dst = src0 + src1; + + _dst_val.i8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + const int16_t src1 = + _src[1].i16[_i]; + + int16_t dst = src0 + src1; + + _dst_val.i16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + const int32_t src1 = + _src[1].i32[_i]; + + int32_t dst = src0 + src1; + + _dst_val.i32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + const int64_t src1 = + _src[1].i64[_i]; + + int64_t dst = src0 + src1; + + _dst_val.i64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_iand(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint1_t src0 = + _src[0].b[_i]; + const uint1_t src1 = + _src[1].b[_i]; + + uint1_t dst = src0 & src1; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint8_t src0 = + _src[0].u8[_i]; + const uint8_t src1 = + _src[1].u8[_i]; + + uint8_t dst = src0 & src1; + + _dst_val.u8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint16_t src0 = + _src[0].u16[_i]; + const uint16_t src1 = + _src[1].u16[_i]; + + uint16_t dst = src0 & src1; + + _dst_val.u16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + + uint32_t dst = src0 & src1; + + _dst_val.u32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint64_t src0 = + _src[0].u64[_i]; + const uint64_t src1 = + _src[1].u64[_i]; + + uint64_t dst = src0 & src1; + + _dst_val.u64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_ibfe(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + const int32_t src1 = + _src[1].i32[_i]; + const int32_t src2 = + _src[2].i32[_i]; + + int32_t dst; + + +int base = src0; +int offset = src1, bits = src2; +if (bits == 0) { + dst = 0; +} else if (bits < 0 || offset < 0) { + dst = 0; /* undefined */ +} else if (offset + bits < 32) { + dst = (base << (32 - bits - offset)) >> (32 - bits); +} else { + dst = base >> offset; +} + + + _dst_val.i32[_i] = dst; + } + + + return _dst_val; +} +static nir_const_value +evaluate_ibitfield_extract(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + const int32_t src1 = + _src[1].i32[_i]; + const int32_t src2 = + _src[2].i32[_i]; + + int32_t dst; + + +int base = src0; +int offset = src1, bits = src2; +if (bits == 0) { + dst = 0; +} else if (offset < 0 || bits < 0 || offset + bits > 32) { + dst = 0; +} else { + dst = (base << (32 - offset - bits)) >> offset; /* use sign-extending shift */ +} + + + _dst_val.i32[_i] = dst; + } + + + return _dst_val; +} +static nir_const_value +evaluate_idiv(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + /* 1-bit integers use a 0/-1 convention */ + const int1_t src1 = -(int1_t)_src[1].b[_i]; + + int1_t dst = src1 == 0 ? 0 : (src0 / src1); + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + const int8_t src1 = + _src[1].i8[_i]; + + int8_t dst = src1 == 0 ? 0 : (src0 / src1); + + _dst_val.i8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + const int16_t src1 = + _src[1].i16[_i]; + + int16_t dst = src1 == 0 ? 0 : (src0 / src1); + + _dst_val.i16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + const int32_t src1 = + _src[1].i32[_i]; + + int32_t dst = src1 == 0 ? 0 : (src0 / src1); + + _dst_val.i32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + const int64_t src1 = + _src[1].i64[_i]; + + int64_t dst = src1 == 0 ? 0 : (src0 / src1); + + _dst_val.i64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_ieq(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + /* 1-bit integers use a 0/-1 convention */ + const int1_t src1 = -(int1_t)_src[1].b[_i]; + + bool1_t dst = src0 == src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + const int8_t src1 = + _src[1].i8[_i]; + + bool1_t dst = src0 == src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + const int16_t src1 = + _src[1].i16[_i]; + + bool1_t dst = src0 == src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + const int32_t src1 = + _src[1].i32[_i]; + + bool1_t dst = src0 == src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + const int64_t src1 = + _src[1].i64[_i]; + + bool1_t dst = src0 == src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_ieq32(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + /* 1-bit integers use a 0/-1 convention */ + const int1_t src1 = -(int1_t)_src[1].b[_i]; + + bool32_t dst = src0 == src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + const int8_t src1 = + _src[1].i8[_i]; + + bool32_t dst = src0 == src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + const int16_t src1 = + _src[1].i16[_i]; + + bool32_t dst = src0 == src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + const int32_t src1 = + _src[1].i32[_i]; + + bool32_t dst = src0 == src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + const int64_t src1 = + _src[1].i64[_i]; + + bool32_t dst = src0 == src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_ifind_msb(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + + int32_t dst; + + +dst = -1; +for (int bit = 31; bit >= 0; bit--) { + /* If src0 < 0, we're looking for the first 0 bit. + * if src0 >= 0, we're looking for the first 1 bit. + */ + if ((((src0 >> bit) & 1) && (src0 >= 0)) || + (!((src0 >> bit) & 1) && (src0 < 0))) { + dst = bit; + break; + } +} + + + _dst_val.i32[_i] = dst; + } + + + return _dst_val; +} +static nir_const_value +evaluate_ige(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + /* 1-bit integers use a 0/-1 convention */ + const int1_t src1 = -(int1_t)_src[1].b[_i]; + + bool1_t dst = src0 >= src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + const int8_t src1 = + _src[1].i8[_i]; + + bool1_t dst = src0 >= src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + const int16_t src1 = + _src[1].i16[_i]; + + bool1_t dst = src0 >= src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + const int32_t src1 = + _src[1].i32[_i]; + + bool1_t dst = src0 >= src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + const int64_t src1 = + _src[1].i64[_i]; + + bool1_t dst = src0 >= src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_ige32(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + /* 1-bit integers use a 0/-1 convention */ + const int1_t src1 = -(int1_t)_src[1].b[_i]; + + bool32_t dst = src0 >= src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + const int8_t src1 = + _src[1].i8[_i]; + + bool32_t dst = src0 >= src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + const int16_t src1 = + _src[1].i16[_i]; + + bool32_t dst = src0 >= src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + const int32_t src1 = + _src[1].i32[_i]; + + bool32_t dst = src0 >= src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + const int64_t src1 = + _src[1].i64[_i]; + + bool32_t dst = src0 >= src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_ilt(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + /* 1-bit integers use a 0/-1 convention */ + const int1_t src1 = -(int1_t)_src[1].b[_i]; + + bool1_t dst = src0 < src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + const int8_t src1 = + _src[1].i8[_i]; + + bool1_t dst = src0 < src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + const int16_t src1 = + _src[1].i16[_i]; + + bool1_t dst = src0 < src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + const int32_t src1 = + _src[1].i32[_i]; + + bool1_t dst = src0 < src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + const int64_t src1 = + _src[1].i64[_i]; + + bool1_t dst = src0 < src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_ilt32(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + /* 1-bit integers use a 0/-1 convention */ + const int1_t src1 = -(int1_t)_src[1].b[_i]; + + bool32_t dst = src0 < src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + const int8_t src1 = + _src[1].i8[_i]; + + bool32_t dst = src0 < src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + const int16_t src1 = + _src[1].i16[_i]; + + bool32_t dst = src0 < src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + const int32_t src1 = + _src[1].i32[_i]; + + bool32_t dst = src0 < src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + const int64_t src1 = + _src[1].i64[_i]; + + bool32_t dst = src0 < src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_imax(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + /* 1-bit integers use a 0/-1 convention */ + const int1_t src1 = -(int1_t)_src[1].b[_i]; + + int1_t dst = src1 > src0 ? src1 : src0; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + const int8_t src1 = + _src[1].i8[_i]; + + int8_t dst = src1 > src0 ? src1 : src0; + + _dst_val.i8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + const int16_t src1 = + _src[1].i16[_i]; + + int16_t dst = src1 > src0 ? src1 : src0; + + _dst_val.i16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + const int32_t src1 = + _src[1].i32[_i]; + + int32_t dst = src1 > src0 ? src1 : src0; + + _dst_val.i32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + const int64_t src1 = + _src[1].i64[_i]; + + int64_t dst = src1 > src0 ? src1 : src0; + + _dst_val.i64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_imax3(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + /* 1-bit integers use a 0/-1 convention */ + const int1_t src1 = -(int1_t)_src[1].b[_i]; + /* 1-bit integers use a 0/-1 convention */ + const int1_t src2 = -(int1_t)_src[2].b[_i]; + + int1_t dst = MAX2(src0, MAX2(src1, src2)); + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + const int8_t src1 = + _src[1].i8[_i]; + const int8_t src2 = + _src[2].i8[_i]; + + int8_t dst = MAX2(src0, MAX2(src1, src2)); + + _dst_val.i8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + const int16_t src1 = + _src[1].i16[_i]; + const int16_t src2 = + _src[2].i16[_i]; + + int16_t dst = MAX2(src0, MAX2(src1, src2)); + + _dst_val.i16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + const int32_t src1 = + _src[1].i32[_i]; + const int32_t src2 = + _src[2].i32[_i]; + + int32_t dst = MAX2(src0, MAX2(src1, src2)); + + _dst_val.i32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + const int64_t src1 = + _src[1].i64[_i]; + const int64_t src2 = + _src[2].i64[_i]; + + int64_t dst = MAX2(src0, MAX2(src1, src2)); + + _dst_val.i64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_imed3(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + /* 1-bit integers use a 0/-1 convention */ + const int1_t src1 = -(int1_t)_src[1].b[_i]; + /* 1-bit integers use a 0/-1 convention */ + const int1_t src2 = -(int1_t)_src[2].b[_i]; + + int1_t dst = MAX2(MIN2(MAX2(src0, src1), src2), MIN2(src0, src1)); + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + const int8_t src1 = + _src[1].i8[_i]; + const int8_t src2 = + _src[2].i8[_i]; + + int8_t dst = MAX2(MIN2(MAX2(src0, src1), src2), MIN2(src0, src1)); + + _dst_val.i8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + const int16_t src1 = + _src[1].i16[_i]; + const int16_t src2 = + _src[2].i16[_i]; + + int16_t dst = MAX2(MIN2(MAX2(src0, src1), src2), MIN2(src0, src1)); + + _dst_val.i16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + const int32_t src1 = + _src[1].i32[_i]; + const int32_t src2 = + _src[2].i32[_i]; + + int32_t dst = MAX2(MIN2(MAX2(src0, src1), src2), MIN2(src0, src1)); + + _dst_val.i32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + const int64_t src1 = + _src[1].i64[_i]; + const int64_t src2 = + _src[2].i64[_i]; + + int64_t dst = MAX2(MIN2(MAX2(src0, src1), src2), MIN2(src0, src1)); + + _dst_val.i64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_imin(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + /* 1-bit integers use a 0/-1 convention */ + const int1_t src1 = -(int1_t)_src[1].b[_i]; + + int1_t dst = src1 > src0 ? src0 : src1; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + const int8_t src1 = + _src[1].i8[_i]; + + int8_t dst = src1 > src0 ? src0 : src1; + + _dst_val.i8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + const int16_t src1 = + _src[1].i16[_i]; + + int16_t dst = src1 > src0 ? src0 : src1; + + _dst_val.i16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + const int32_t src1 = + _src[1].i32[_i]; + + int32_t dst = src1 > src0 ? src0 : src1; + + _dst_val.i32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + const int64_t src1 = + _src[1].i64[_i]; + + int64_t dst = src1 > src0 ? src0 : src1; + + _dst_val.i64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_imin3(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + /* 1-bit integers use a 0/-1 convention */ + const int1_t src1 = -(int1_t)_src[1].b[_i]; + /* 1-bit integers use a 0/-1 convention */ + const int1_t src2 = -(int1_t)_src[2].b[_i]; + + int1_t dst = MIN2(src0, MIN2(src1, src2)); + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + const int8_t src1 = + _src[1].i8[_i]; + const int8_t src2 = + _src[2].i8[_i]; + + int8_t dst = MIN2(src0, MIN2(src1, src2)); + + _dst_val.i8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + const int16_t src1 = + _src[1].i16[_i]; + const int16_t src2 = + _src[2].i16[_i]; + + int16_t dst = MIN2(src0, MIN2(src1, src2)); + + _dst_val.i16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + const int32_t src1 = + _src[1].i32[_i]; + const int32_t src2 = + _src[2].i32[_i]; + + int32_t dst = MIN2(src0, MIN2(src1, src2)); + + _dst_val.i32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + const int64_t src1 = + _src[1].i64[_i]; + const int64_t src2 = + _src[2].i64[_i]; + + int64_t dst = MIN2(src0, MIN2(src1, src2)); + + _dst_val.i64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_imod(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + /* 1-bit integers use a 0/-1 convention */ + const int1_t src1 = -(int1_t)_src[1].b[_i]; + + int1_t dst = src1 == 0 ? 0 : ((src0 % src1 == 0 || (src0 >= 0) == (src1 >= 0)) ? src0 % src1 : src0 % src1 + src1); + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + const int8_t src1 = + _src[1].i8[_i]; + + int8_t dst = src1 == 0 ? 0 : ((src0 % src1 == 0 || (src0 >= 0) == (src1 >= 0)) ? src0 % src1 : src0 % src1 + src1); + + _dst_val.i8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + const int16_t src1 = + _src[1].i16[_i]; + + int16_t dst = src1 == 0 ? 0 : ((src0 % src1 == 0 || (src0 >= 0) == (src1 >= 0)) ? src0 % src1 : src0 % src1 + src1); + + _dst_val.i16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + const int32_t src1 = + _src[1].i32[_i]; + + int32_t dst = src1 == 0 ? 0 : ((src0 % src1 == 0 || (src0 >= 0) == (src1 >= 0)) ? src0 % src1 : src0 % src1 + src1); + + _dst_val.i32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + const int64_t src1 = + _src[1].i64[_i]; + + int64_t dst = src1 == 0 ? 0 : ((src0 % src1 == 0 || (src0 >= 0) == (src1 >= 0)) ? src0 % src1 : src0 % src1 + src1); + + _dst_val.i64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_imov(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + + int1_t dst = src0; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + + int8_t dst = src0; + + _dst_val.i8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + + int16_t dst = src0; + + _dst_val.i16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + + int32_t dst = src0; + + _dst_val.i32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + + int64_t dst = src0; + + _dst_val.i64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_imul(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + /* 1-bit integers use a 0/-1 convention */ + const int1_t src1 = -(int1_t)_src[1].b[_i]; + + int1_t dst = src0 * src1; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + const int8_t src1 = + _src[1].i8[_i]; + + int8_t dst = src0 * src1; + + _dst_val.i8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + const int16_t src1 = + _src[1].i16[_i]; + + int16_t dst = src0 * src1; + + _dst_val.i16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + const int32_t src1 = + _src[1].i32[_i]; + + int32_t dst = src0 * src1; + + _dst_val.i32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + const int64_t src1 = + _src[1].i64[_i]; + + int64_t dst = src0 * src1; + + _dst_val.i64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_imul_high(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + /* 1-bit integers use a 0/-1 convention */ + const int1_t src1 = -(int1_t)_src[1].b[_i]; + + int1_t dst; + + +if (bit_size == 64) { + /* We need to do a full 128-bit x 128-bit multiply in order for the sign + * extension to work properly. The casts are kind-of annoying but needed + * to prevent compiler warnings. + */ + uint32_t src0_u32[4] = { + src0, + (int64_t)src0 >> 32, + (int64_t)src0 >> 63, + (int64_t)src0 >> 63, + }; + uint32_t src1_u32[4] = { + src1, + (int64_t)src1 >> 32, + (int64_t)src1 >> 63, + (int64_t)src1 >> 63, + }; + uint32_t prod_u32[4]; + ubm_mul_u32arr(prod_u32, src0_u32, src1_u32); + dst = (uint64_t)prod_u32[2] | ((uint64_t)prod_u32[3] << 32); +} else { + dst = ((int64_t)src0 * (int64_t)src1) >> bit_size; +} + + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + const int8_t src1 = + _src[1].i8[_i]; + + int8_t dst; + + +if (bit_size == 64) { + /* We need to do a full 128-bit x 128-bit multiply in order for the sign + * extension to work properly. The casts are kind-of annoying but needed + * to prevent compiler warnings. + */ + uint32_t src0_u32[4] = { + src0, + (int64_t)src0 >> 32, + (int64_t)src0 >> 63, + (int64_t)src0 >> 63, + }; + uint32_t src1_u32[4] = { + src1, + (int64_t)src1 >> 32, + (int64_t)src1 >> 63, + (int64_t)src1 >> 63, + }; + uint32_t prod_u32[4]; + ubm_mul_u32arr(prod_u32, src0_u32, src1_u32); + dst = (uint64_t)prod_u32[2] | ((uint64_t)prod_u32[3] << 32); +} else { + dst = ((int64_t)src0 * (int64_t)src1) >> bit_size; +} + + + _dst_val.i8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + const int16_t src1 = + _src[1].i16[_i]; + + int16_t dst; + + +if (bit_size == 64) { + /* We need to do a full 128-bit x 128-bit multiply in order for the sign + * extension to work properly. The casts are kind-of annoying but needed + * to prevent compiler warnings. + */ + uint32_t src0_u32[4] = { + src0, + (int64_t)src0 >> 32, + (int64_t)src0 >> 63, + (int64_t)src0 >> 63, + }; + uint32_t src1_u32[4] = { + src1, + (int64_t)src1 >> 32, + (int64_t)src1 >> 63, + (int64_t)src1 >> 63, + }; + uint32_t prod_u32[4]; + ubm_mul_u32arr(prod_u32, src0_u32, src1_u32); + dst = (uint64_t)prod_u32[2] | ((uint64_t)prod_u32[3] << 32); +} else { + dst = ((int64_t)src0 * (int64_t)src1) >> bit_size; +} + + + _dst_val.i16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + const int32_t src1 = + _src[1].i32[_i]; + + int32_t dst; + + +if (bit_size == 64) { + /* We need to do a full 128-bit x 128-bit multiply in order for the sign + * extension to work properly. The casts are kind-of annoying but needed + * to prevent compiler warnings. + */ + uint32_t src0_u32[4] = { + src0, + (int64_t)src0 >> 32, + (int64_t)src0 >> 63, + (int64_t)src0 >> 63, + }; + uint32_t src1_u32[4] = { + src1, + (int64_t)src1 >> 32, + (int64_t)src1 >> 63, + (int64_t)src1 >> 63, + }; + uint32_t prod_u32[4]; + ubm_mul_u32arr(prod_u32, src0_u32, src1_u32); + dst = (uint64_t)prod_u32[2] | ((uint64_t)prod_u32[3] << 32); +} else { + dst = ((int64_t)src0 * (int64_t)src1) >> bit_size; +} + + + _dst_val.i32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + const int64_t src1 = + _src[1].i64[_i]; + + int64_t dst; + + +if (bit_size == 64) { + /* We need to do a full 128-bit x 128-bit multiply in order for the sign + * extension to work properly. The casts are kind-of annoying but needed + * to prevent compiler warnings. + */ + uint32_t src0_u32[4] = { + src0, + (int64_t)src0 >> 32, + (int64_t)src0 >> 63, + (int64_t)src0 >> 63, + }; + uint32_t src1_u32[4] = { + src1, + (int64_t)src1 >> 32, + (int64_t)src1 >> 63, + (int64_t)src1 >> 63, + }; + uint32_t prod_u32[4]; + ubm_mul_u32arr(prod_u32, src0_u32, src1_u32); + dst = (uint64_t)prod_u32[2] | ((uint64_t)prod_u32[3] << 32); +} else { + dst = ((int64_t)src0 * (int64_t)src1) >> bit_size; +} + + + _dst_val.i64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_ine(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + /* 1-bit integers use a 0/-1 convention */ + const int1_t src1 = -(int1_t)_src[1].b[_i]; + + bool1_t dst = src0 != src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + const int8_t src1 = + _src[1].i8[_i]; + + bool1_t dst = src0 != src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + const int16_t src1 = + _src[1].i16[_i]; + + bool1_t dst = src0 != src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + const int32_t src1 = + _src[1].i32[_i]; + + bool1_t dst = src0 != src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + const int64_t src1 = + _src[1].i64[_i]; + + bool1_t dst = src0 != src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_ine32(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + /* 1-bit integers use a 0/-1 convention */ + const int1_t src1 = -(int1_t)_src[1].b[_i]; + + bool32_t dst = src0 != src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + const int8_t src1 = + _src[1].i8[_i]; + + bool32_t dst = src0 != src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + const int16_t src1 = + _src[1].i16[_i]; + + bool32_t dst = src0 != src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + const int32_t src1 = + _src[1].i32[_i]; + + bool32_t dst = src0 != src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + const int64_t src1 = + _src[1].i64[_i]; + + bool32_t dst = src0 != src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_ineg(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + + int1_t dst = -src0; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + + int8_t dst = -src0; + + _dst_val.i8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + + int16_t dst = -src0; + + _dst_val.i16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + + int32_t dst = -src0; + + _dst_val.i32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + + int64_t dst = -src0; + + _dst_val.i64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_inot(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + + int1_t dst = ~src0; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + + int8_t dst = ~src0; + + _dst_val.i8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + + int16_t dst = ~src0; + + _dst_val.i16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + + int32_t dst = ~src0; + + _dst_val.i32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + + int64_t dst = ~src0; + + _dst_val.i64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_ior(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint1_t src0 = + _src[0].b[_i]; + const uint1_t src1 = + _src[1].b[_i]; + + uint1_t dst = src0 | src1; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint8_t src0 = + _src[0].u8[_i]; + const uint8_t src1 = + _src[1].u8[_i]; + + uint8_t dst = src0 | src1; + + _dst_val.u8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint16_t src0 = + _src[0].u16[_i]; + const uint16_t src1 = + _src[1].u16[_i]; + + uint16_t dst = src0 | src1; + + _dst_val.u16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + + uint32_t dst = src0 | src1; + + _dst_val.u32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint64_t src0 = + _src[0].u64[_i]; + const uint64_t src1 = + _src[1].u64[_i]; + + uint64_t dst = src0 | src1; + + _dst_val.u64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_irem(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + /* 1-bit integers use a 0/-1 convention */ + const int1_t src1 = -(int1_t)_src[1].b[_i]; + + int1_t dst = src1 == 0 ? 0 : src0 % src1; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + const int8_t src1 = + _src[1].i8[_i]; + + int8_t dst = src1 == 0 ? 0 : src0 % src1; + + _dst_val.i8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + const int16_t src1 = + _src[1].i16[_i]; + + int16_t dst = src1 == 0 ? 0 : src0 % src1; + + _dst_val.i16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + const int32_t src1 = + _src[1].i32[_i]; + + int32_t dst = src1 == 0 ? 0 : src0 % src1; + + _dst_val.i32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + const int64_t src1 = + _src[1].i64[_i]; + + int64_t dst = src1 == 0 ? 0 : src0 % src1; + + _dst_val.i64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_ishl(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + + int1_t dst = src0 << src1; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + + int8_t dst = src0 << src1; + + _dst_val.i8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + + int16_t dst = src0 << src1; + + _dst_val.i16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + + int32_t dst = src0 << src1; + + _dst_val.i32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + + int64_t dst = src0 << src1; + + _dst_val.i64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_ishr(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + + int1_t dst = src0 >> src1; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + + int8_t dst = src0 >> src1; + + _dst_val.i8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + + int16_t dst = src0 >> src1; + + _dst_val.i16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + + int32_t dst = src0 >> src1; + + _dst_val.i32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + + int64_t dst = src0 >> src1; + + _dst_val.i64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_isign(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + + int1_t dst = (src0 == 0) ? 0 : ((src0 > 0) ? 1 : -1); + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + + int8_t dst = (src0 == 0) ? 0 : ((src0 > 0) ? 1 : -1); + + _dst_val.i8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + + int16_t dst = (src0 == 0) ? 0 : ((src0 > 0) ? 1 : -1); + + _dst_val.i16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + + int32_t dst = (src0 == 0) ? 0 : ((src0 > 0) ? 1 : -1); + + _dst_val.i32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + + int64_t dst = (src0 == 0) ? 0 : ((src0 > 0) ? 1 : -1); + + _dst_val.i64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_isub(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + /* 1-bit integers use a 0/-1 convention */ + const int1_t src0 = -(int1_t)_src[0].b[_i]; + /* 1-bit integers use a 0/-1 convention */ + const int1_t src1 = -(int1_t)_src[1].b[_i]; + + int1_t dst = src0 - src1; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int8_t src0 = + _src[0].i8[_i]; + const int8_t src1 = + _src[1].i8[_i]; + + int8_t dst = src0 - src1; + + _dst_val.i8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int16_t src0 = + _src[0].i16[_i]; + const int16_t src1 = + _src[1].i16[_i]; + + int16_t dst = src0 - src1; + + _dst_val.i16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + const int32_t src1 = + _src[1].i32[_i]; + + int32_t dst = src0 - src1; + + _dst_val.i32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int64_t src0 = + _src[0].i64[_i]; + const int64_t src1 = + _src[1].i64[_i]; + + int64_t dst = src0 - src1; + + _dst_val.i64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_ixor(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint1_t src0 = + _src[0].b[_i]; + const uint1_t src1 = + _src[1].b[_i]; + + uint1_t dst = src0 ^ src1; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint8_t src0 = + _src[0].u8[_i]; + const uint8_t src1 = + _src[1].u8[_i]; + + uint8_t dst = src0 ^ src1; + + _dst_val.u8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint16_t src0 = + _src[0].u16[_i]; + const uint16_t src1 = + _src[1].u16[_i]; + + uint16_t dst = src0 ^ src1; + + _dst_val.u16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + + uint32_t dst = src0 ^ src1; + + _dst_val.u32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint64_t src0 = + _src[0].u64[_i]; + const uint64_t src1 = + _src[1].u64[_i]; + + uint64_t dst = src0 ^ src1; + + _dst_val.u64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_ldexp(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + const int32_t src1 = + _src[1].i32[_i]; + + float16_t dst; + + +dst = (bit_size == 64) ? ldexp(src0, src1) : ldexpf(src0, src1); +/* flush denormals to zero. */ +if (!isnormal(dst)) + dst = copysignf(0.0f, src0); + + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + const int32_t src1 = + _src[1].i32[_i]; + + float32_t dst; + + +dst = (bit_size == 64) ? ldexp(src0, src1) : ldexpf(src0, src1); +/* flush denormals to zero. */ +if (!isnormal(dst)) + dst = copysignf(0.0f, src0); + + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + const int32_t src1 = + _src[1].i32[_i]; + + float64_t dst; + + +dst = (bit_size == 64) ? ldexp(src0, src1) : ldexpf(src0, src1); +/* flush denormals to zero. */ +if (!isnormal(dst)) + dst = copysignf(0.0f, src0); + + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_pack_32_2x16(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + const struct uint16_vec src0 = { + _src[0].u16[0], + _src[0].u16[1], + 0, + 0, + }; + + struct uint32_vec dst; + + dst.x = src0.x | ((uint32_t)src0.y << 16); + + _dst_val.u32[0] = dst.x; + + + return _dst_val; +} +static nir_const_value +evaluate_pack_32_2x16_split(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint16_t src0 = + _src[0].u16[_i]; + const uint16_t src1 = + _src[1].u16[_i]; + + uint32_t dst = src0 | ((uint32_t)src1 << 16); + + _dst_val.u32[_i] = dst; + } + + + return _dst_val; +} +static nir_const_value +evaluate_pack_64_2x32(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + const struct uint32_vec src0 = { + _src[0].u32[0], + _src[0].u32[1], + 0, + 0, + }; + + struct uint64_vec dst; + + dst.x = src0.x | ((uint64_t)src0.y << 32); + + _dst_val.u64[0] = dst.x; + + + return _dst_val; +} +static nir_const_value +evaluate_pack_64_2x32_split(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + + uint64_t dst = src0 | ((uint64_t)src1 << 32); + + _dst_val.u64[_i] = dst; + } + + + return _dst_val; +} +static nir_const_value +evaluate_pack_64_4x16(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + const struct uint16_vec src0 = { + _src[0].u16[0], + _src[0].u16[1], + _src[0].u16[2], + _src[0].u16[3], + }; + + struct uint64_vec dst; + + dst.x = src0.x | ((uint64_t)src0.y << 16) | ((uint64_t)src0.z << 32) | ((uint64_t)src0.w << 48); + + _dst_val.u64[0] = dst.x; + + + return _dst_val; +} +static nir_const_value +evaluate_pack_half_2x16(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + const struct float32_vec src0 = { + _src[0].f32[0], + _src[0].f32[1], + 0, + 0, + }; + + struct uint32_vec dst; + + +dst.x = (uint32_t) pack_half_1x16(src0.x); +dst.x |= ((uint32_t) pack_half_1x16(src0.y)) << 16; + + + _dst_val.u32[0] = dst.x; + + + return _dst_val; +} +static nir_const_value +evaluate_pack_half_2x16_split(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + const struct float32_vec src0 = { + _src[0].f32[0], + 0, + 0, + 0, + }; + + const struct float32_vec src1 = { + _src[1].f32[0], + 0, + 0, + 0, + }; + + struct uint32_vec dst; + + dst.x = dst.y = dst.z = dst.w = pack_half_1x16(src0.x) | (pack_half_1x16(src1.x) << 16); + + _dst_val.u32[0] = dst.x; + + + return _dst_val; +} +static nir_const_value +evaluate_pack_snorm_2x16(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + const struct float32_vec src0 = { + _src[0].f32[0], + _src[0].f32[1], + 0, + 0, + }; + + struct uint32_vec dst; + + +dst.x = (uint32_t) pack_snorm_1x16(src0.x); +dst.x |= ((uint32_t) pack_snorm_1x16(src0.y)) << 16; + + + _dst_val.u32[0] = dst.x; + + + return _dst_val; +} +static nir_const_value +evaluate_pack_snorm_4x8(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + const struct float32_vec src0 = { + _src[0].f32[0], + _src[0].f32[1], + _src[0].f32[2], + _src[0].f32[3], + }; + + struct uint32_vec dst; + + +dst.x = (uint32_t) pack_snorm_1x8(src0.x); +dst.x |= ((uint32_t) pack_snorm_1x8(src0.y)) << 8; +dst.x |= ((uint32_t) pack_snorm_1x8(src0.z)) << 16; +dst.x |= ((uint32_t) pack_snorm_1x8(src0.w)) << 24; + + + _dst_val.u32[0] = dst.x; + + + return _dst_val; +} +static nir_const_value +evaluate_pack_unorm_2x16(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + const struct float32_vec src0 = { + _src[0].f32[0], + _src[0].f32[1], + 0, + 0, + }; + + struct uint32_vec dst; + + +dst.x = (uint32_t) pack_unorm_1x16(src0.x); +dst.x |= ((uint32_t) pack_unorm_1x16(src0.y)) << 16; + + + _dst_val.u32[0] = dst.x; + + + return _dst_val; +} +static nir_const_value +evaluate_pack_unorm_4x8(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + const struct float32_vec src0 = { + _src[0].f32[0], + _src[0].f32[1], + _src[0].f32[2], + _src[0].f32[3], + }; + + struct uint32_vec dst; + + +dst.x = (uint32_t) pack_unorm_1x8(src0.x); +dst.x |= ((uint32_t) pack_unorm_1x8(src0.y)) << 8; +dst.x |= ((uint32_t) pack_unorm_1x8(src0.z)) << 16; +dst.x |= ((uint32_t) pack_unorm_1x8(src0.w)) << 24; + + + _dst_val.u32[0] = dst.x; + + + return _dst_val; +} +static nir_const_value +evaluate_pack_uvec2_to_uint(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + const struct uint32_vec src0 = { + _src[0].u32[0], + _src[0].u32[1], + 0, + 0, + }; + + struct uint32_vec dst; + + +dst.x = (src0.x & 0xffff) | (src0.y << 16); + + + _dst_val.u32[0] = dst.x; + + + return _dst_val; +} +static nir_const_value +evaluate_pack_uvec4_to_uint(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + const struct uint32_vec src0 = { + _src[0].u32[0], + _src[0].u32[1], + _src[0].u32[2], + _src[0].u32[3], + }; + + struct uint32_vec dst; + + +dst.x = (src0.x << 0) | + (src0.y << 8) | + (src0.z << 16) | + (src0.w << 24); + + + _dst_val.u32[0] = dst.x; + + + return _dst_val; +} +static nir_const_value +evaluate_seq(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + const float32_t src1 = + _src[1].f32[_i]; + + float32_t dst = (src0 == src1) ? 1.0f : 0.0f; + + _dst_val.f32[_i] = dst; + } + + + return _dst_val; +} +static nir_const_value +evaluate_sge(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float src0 = + _mesa_half_to_float(_src[0].u16[_i]); + const float src1 = + _mesa_half_to_float(_src[1].u16[_i]); + + float16_t dst = (src0 >= src1) ? 1.0f : 0.0f; + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + const float32_t src1 = + _src[1].f32[_i]; + + float32_t dst = (src0 >= src1) ? 1.0f : 0.0f; + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float64_t src0 = + _src[0].f64[_i]; + const float64_t src1 = + _src[1].f64[_i]; + + float64_t dst = (src0 >= src1) ? 1.0f : 0.0f; + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_slt(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + const float32_t src1 = + _src[1].f32[_i]; + + float32_t dst = (src0 < src1) ? 1.0f : 0.0f; + + _dst_val.f32[_i] = dst; + } + + + return _dst_val; +} +static nir_const_value +evaluate_sne(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const float32_t src0 = + _src[0].f32[_i]; + const float32_t src1 = + _src[1].f32[_i]; + + float32_t dst = (src0 != src1) ? 1.0f : 0.0f; + + _dst_val.f32[_i] = dst; + } + + + return _dst_val; +} +static nir_const_value +evaluate_u2f16(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint1_t src0 = + _src[0].b[_i]; + + float16_t dst = src0; + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint8_t src0 = + _src[0].u8[_i]; + + float16_t dst = src0; + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint16_t src0 = + _src[0].u16[_i]; + + float16_t dst = src0; + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + + float16_t dst = src0; + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint64_t src0 = + _src[0].u64[_i]; + + float16_t dst = src0; + + _dst_val.u16[_i] = _mesa_float_to_half(dst); + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_u2f32(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint1_t src0 = + _src[0].b[_i]; + + float32_t dst = src0; + + _dst_val.f32[_i] = dst; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint8_t src0 = + _src[0].u8[_i]; + + float32_t dst = src0; + + _dst_val.f32[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint16_t src0 = + _src[0].u16[_i]; + + float32_t dst = src0; + + _dst_val.f32[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + + float32_t dst = src0; + + _dst_val.f32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint64_t src0 = + _src[0].u64[_i]; + + float32_t dst = src0; + + _dst_val.f32[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_u2f64(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint1_t src0 = + _src[0].b[_i]; + + float64_t dst = src0; + + _dst_val.f64[_i] = dst; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint8_t src0 = + _src[0].u8[_i]; + + float64_t dst = src0; + + _dst_val.f64[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint16_t src0 = + _src[0].u16[_i]; + + float64_t dst = src0; + + _dst_val.f64[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + + float64_t dst = src0; + + _dst_val.f64[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint64_t src0 = + _src[0].u64[_i]; + + float64_t dst = src0; + + _dst_val.f64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_u2u1(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint1_t src0 = + _src[0].b[_i]; + + uint1_t dst = src0; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint8_t src0 = + _src[0].u8[_i]; + + uint1_t dst = src0; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint16_t src0 = + _src[0].u16[_i]; + + uint1_t dst = src0; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + + uint1_t dst = src0; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint64_t src0 = + _src[0].u64[_i]; + + uint1_t dst = src0; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_u2u16(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint1_t src0 = + _src[0].b[_i]; + + uint16_t dst = src0; + + _dst_val.u16[_i] = dst; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint8_t src0 = + _src[0].u8[_i]; + + uint16_t dst = src0; + + _dst_val.u16[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint16_t src0 = + _src[0].u16[_i]; + + uint16_t dst = src0; + + _dst_val.u16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + + uint16_t dst = src0; + + _dst_val.u16[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint64_t src0 = + _src[0].u64[_i]; + + uint16_t dst = src0; + + _dst_val.u16[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_u2u32(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint1_t src0 = + _src[0].b[_i]; + + uint32_t dst = src0; + + _dst_val.u32[_i] = dst; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint8_t src0 = + _src[0].u8[_i]; + + uint32_t dst = src0; + + _dst_val.u32[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint16_t src0 = + _src[0].u16[_i]; + + uint32_t dst = src0; + + _dst_val.u32[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + + uint32_t dst = src0; + + _dst_val.u32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint64_t src0 = + _src[0].u64[_i]; + + uint32_t dst = src0; + + _dst_val.u32[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_u2u64(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint1_t src0 = + _src[0].b[_i]; + + uint64_t dst = src0; + + _dst_val.u64[_i] = dst; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint8_t src0 = + _src[0].u8[_i]; + + uint64_t dst = src0; + + _dst_val.u64[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint16_t src0 = + _src[0].u16[_i]; + + uint64_t dst = src0; + + _dst_val.u64[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + + uint64_t dst = src0; + + _dst_val.u64[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint64_t src0 = + _src[0].u64[_i]; + + uint64_t dst = src0; + + _dst_val.u64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_u2u8(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint1_t src0 = + _src[0].b[_i]; + + uint8_t dst = src0; + + _dst_val.u8[_i] = dst; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint8_t src0 = + _src[0].u8[_i]; + + uint8_t dst = src0; + + _dst_val.u8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint16_t src0 = + _src[0].u16[_i]; + + uint8_t dst = src0; + + _dst_val.u8[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + + uint8_t dst = src0; + + _dst_val.u8[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint64_t src0 = + _src[0].u64[_i]; + + uint8_t dst = src0; + + _dst_val.u8[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_uadd_carry(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint1_t src0 = + _src[0].b[_i]; + const uint1_t src1 = + _src[1].b[_i]; + + uint1_t dst = src0 + src1 < src0; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint8_t src0 = + _src[0].u8[_i]; + const uint8_t src1 = + _src[1].u8[_i]; + + uint8_t dst = src0 + src1 < src0; + + _dst_val.u8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint16_t src0 = + _src[0].u16[_i]; + const uint16_t src1 = + _src[1].u16[_i]; + + uint16_t dst = src0 + src1 < src0; + + _dst_val.u16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + + uint32_t dst = src0 + src1 < src0; + + _dst_val.u32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint64_t src0 = + _src[0].u64[_i]; + const uint64_t src1 = + _src[1].u64[_i]; + + uint64_t dst = src0 + src1 < src0; + + _dst_val.u64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_uadd_sat(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint1_t src0 = + _src[0].b[_i]; + const uint1_t src1 = + _src[1].b[_i]; + + uint1_t dst = (src0 + src1) < src0 ? UINT64_MAX : (src0 + src1); + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint8_t src0 = + _src[0].u8[_i]; + const uint8_t src1 = + _src[1].u8[_i]; + + uint8_t dst = (src0 + src1) < src0 ? UINT64_MAX : (src0 + src1); + + _dst_val.u8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint16_t src0 = + _src[0].u16[_i]; + const uint16_t src1 = + _src[1].u16[_i]; + + uint16_t dst = (src0 + src1) < src0 ? UINT64_MAX : (src0 + src1); + + _dst_val.u16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + + uint32_t dst = (src0 + src1) < src0 ? UINT64_MAX : (src0 + src1); + + _dst_val.u32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint64_t src0 = + _src[0].u64[_i]; + const uint64_t src1 = + _src[1].u64[_i]; + + uint64_t dst = (src0 + src1) < src0 ? UINT64_MAX : (src0 + src1); + + _dst_val.u64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_ubfe(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + const int32_t src1 = + _src[1].i32[_i]; + const int32_t src2 = + _src[2].i32[_i]; + + uint32_t dst; + + +unsigned base = src0; +int offset = src1, bits = src2; +if (bits == 0) { + dst = 0; +} else if (bits < 0 || offset < 0) { + dst = 0; /* undefined */ +} else if (offset + bits < 32) { + dst = (base << (32 - bits - offset)) >> (32 - bits); +} else { + dst = base >> offset; +} + + + _dst_val.u32[_i] = dst; + } + + + return _dst_val; +} +static nir_const_value +evaluate_ubitfield_extract(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + const int32_t src1 = + _src[1].i32[_i]; + const int32_t src2 = + _src[2].i32[_i]; + + uint32_t dst; + + +unsigned base = src0; +int offset = src1, bits = src2; +if (bits == 0) { + dst = 0; +} else if (bits < 0 || offset < 0 || offset + bits > 32) { + dst = 0; /* undefined per the spec */ +} else { + dst = (base >> offset) & ((1ull << bits) - 1); +} + + + _dst_val.u32[_i] = dst; + } + + + return _dst_val; +} +static nir_const_value +evaluate_udiv(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint1_t src0 = + _src[0].b[_i]; + const uint1_t src1 = + _src[1].b[_i]; + + uint1_t dst = src1 == 0 ? 0 : (src0 / src1); + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint8_t src0 = + _src[0].u8[_i]; + const uint8_t src1 = + _src[1].u8[_i]; + + uint8_t dst = src1 == 0 ? 0 : (src0 / src1); + + _dst_val.u8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint16_t src0 = + _src[0].u16[_i]; + const uint16_t src1 = + _src[1].u16[_i]; + + uint16_t dst = src1 == 0 ? 0 : (src0 / src1); + + _dst_val.u16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + + uint32_t dst = src1 == 0 ? 0 : (src0 / src1); + + _dst_val.u32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint64_t src0 = + _src[0].u64[_i]; + const uint64_t src1 = + _src[1].u64[_i]; + + uint64_t dst = src1 == 0 ? 0 : (src0 / src1); + + _dst_val.u64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_ufind_msb(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint1_t src0 = + _src[0].b[_i]; + + int32_t dst; + + +dst = -1; +for (int bit = bit_size - 1; bit >= 0; bit--) { + if ((src0 >> bit) & 1) { + dst = bit; + break; + } +} + + + _dst_val.i32[_i] = dst; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint8_t src0 = + _src[0].u8[_i]; + + int32_t dst; + + +dst = -1; +for (int bit = bit_size - 1; bit >= 0; bit--) { + if ((src0 >> bit) & 1) { + dst = bit; + break; + } +} + + + _dst_val.i32[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint16_t src0 = + _src[0].u16[_i]; + + int32_t dst; + + +dst = -1; +for (int bit = bit_size - 1; bit >= 0; bit--) { + if ((src0 >> bit) & 1) { + dst = bit; + break; + } +} + + + _dst_val.i32[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + + int32_t dst; + + +dst = -1; +for (int bit = bit_size - 1; bit >= 0; bit--) { + if ((src0 >> bit) & 1) { + dst = bit; + break; + } +} + + + _dst_val.i32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint64_t src0 = + _src[0].u64[_i]; + + int32_t dst; + + +dst = -1; +for (int bit = bit_size - 1; bit >= 0; bit--) { + if ((src0 >> bit) & 1) { + dst = bit; + break; + } +} + + + _dst_val.i32[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_uge(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint1_t src0 = + _src[0].b[_i]; + const uint1_t src1 = + _src[1].b[_i]; + + bool1_t dst = src0 >= src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint8_t src0 = + _src[0].u8[_i]; + const uint8_t src1 = + _src[1].u8[_i]; + + bool1_t dst = src0 >= src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint16_t src0 = + _src[0].u16[_i]; + const uint16_t src1 = + _src[1].u16[_i]; + + bool1_t dst = src0 >= src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + + bool1_t dst = src0 >= src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint64_t src0 = + _src[0].u64[_i]; + const uint64_t src1 = + _src[1].u64[_i]; + + bool1_t dst = src0 >= src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_uge32(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint1_t src0 = + _src[0].b[_i]; + const uint1_t src1 = + _src[1].b[_i]; + + bool32_t dst = src0 >= src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint8_t src0 = + _src[0].u8[_i]; + const uint8_t src1 = + _src[1].u8[_i]; + + bool32_t dst = src0 >= src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint16_t src0 = + _src[0].u16[_i]; + const uint16_t src1 = + _src[1].u16[_i]; + + bool32_t dst = src0 >= src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + + bool32_t dst = src0 >= src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint64_t src0 = + _src[0].u64[_i]; + const uint64_t src1 = + _src[1].u64[_i]; + + bool32_t dst = src0 >= src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_ult(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint1_t src0 = + _src[0].b[_i]; + const uint1_t src1 = + _src[1].b[_i]; + + bool1_t dst = src0 < src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint8_t src0 = + _src[0].u8[_i]; + const uint8_t src1 = + _src[1].u8[_i]; + + bool1_t dst = src0 < src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint16_t src0 = + _src[0].u16[_i]; + const uint16_t src1 = + _src[1].u16[_i]; + + bool1_t dst = src0 < src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + + bool1_t dst = src0 < src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint64_t src0 = + _src[0].u64[_i]; + const uint64_t src1 = + _src[1].u64[_i]; + + bool1_t dst = src0 < src1; + + _dst_val.b[_i] = -(int)dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_ult32(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint1_t src0 = + _src[0].b[_i]; + const uint1_t src1 = + _src[1].b[_i]; + + bool32_t dst = src0 < src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint8_t src0 = + _src[0].u8[_i]; + const uint8_t src1 = + _src[1].u8[_i]; + + bool32_t dst = src0 < src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint16_t src0 = + _src[0].u16[_i]; + const uint16_t src1 = + _src[1].u16[_i]; + + bool32_t dst = src0 < src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + + bool32_t dst = src0 < src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint64_t src0 = + _src[0].u64[_i]; + const uint64_t src1 = + _src[1].u64[_i]; + + bool32_t dst = src0 < src1; + + _dst_val.i32[_i] = -(int)dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_umax(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint1_t src0 = + _src[0].b[_i]; + const uint1_t src1 = + _src[1].b[_i]; + + uint1_t dst = src1 > src0 ? src1 : src0; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint8_t src0 = + _src[0].u8[_i]; + const uint8_t src1 = + _src[1].u8[_i]; + + uint8_t dst = src1 > src0 ? src1 : src0; + + _dst_val.u8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint16_t src0 = + _src[0].u16[_i]; + const uint16_t src1 = + _src[1].u16[_i]; + + uint16_t dst = src1 > src0 ? src1 : src0; + + _dst_val.u16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + + uint32_t dst = src1 > src0 ? src1 : src0; + + _dst_val.u32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint64_t src0 = + _src[0].u64[_i]; + const uint64_t src1 = + _src[1].u64[_i]; + + uint64_t dst = src1 > src0 ? src1 : src0; + + _dst_val.u64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_umax3(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint1_t src0 = + _src[0].b[_i]; + const uint1_t src1 = + _src[1].b[_i]; + const uint1_t src2 = + _src[2].b[_i]; + + uint1_t dst = MAX2(src0, MAX2(src1, src2)); + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint8_t src0 = + _src[0].u8[_i]; + const uint8_t src1 = + _src[1].u8[_i]; + const uint8_t src2 = + _src[2].u8[_i]; + + uint8_t dst = MAX2(src0, MAX2(src1, src2)); + + _dst_val.u8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint16_t src0 = + _src[0].u16[_i]; + const uint16_t src1 = + _src[1].u16[_i]; + const uint16_t src2 = + _src[2].u16[_i]; + + uint16_t dst = MAX2(src0, MAX2(src1, src2)); + + _dst_val.u16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + const uint32_t src2 = + _src[2].u32[_i]; + + uint32_t dst = MAX2(src0, MAX2(src1, src2)); + + _dst_val.u32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint64_t src0 = + _src[0].u64[_i]; + const uint64_t src1 = + _src[1].u64[_i]; + const uint64_t src2 = + _src[2].u64[_i]; + + uint64_t dst = MAX2(src0, MAX2(src1, src2)); + + _dst_val.u64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_umax_4x8(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + const int32_t src1 = + _src[1].i32[_i]; + + int32_t dst; + + +dst = 0; +for (int i = 0; i < 32; i += 8) { + dst |= MAX2((src0 >> i) & 0xff, (src1 >> i) & 0xff) << i; +} + + + _dst_val.i32[_i] = dst; + } + + + return _dst_val; +} +static nir_const_value +evaluate_umed3(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint1_t src0 = + _src[0].b[_i]; + const uint1_t src1 = + _src[1].b[_i]; + const uint1_t src2 = + _src[2].b[_i]; + + uint1_t dst = MAX2(MIN2(MAX2(src0, src1), src2), MIN2(src0, src1)); + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint8_t src0 = + _src[0].u8[_i]; + const uint8_t src1 = + _src[1].u8[_i]; + const uint8_t src2 = + _src[2].u8[_i]; + + uint8_t dst = MAX2(MIN2(MAX2(src0, src1), src2), MIN2(src0, src1)); + + _dst_val.u8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint16_t src0 = + _src[0].u16[_i]; + const uint16_t src1 = + _src[1].u16[_i]; + const uint16_t src2 = + _src[2].u16[_i]; + + uint16_t dst = MAX2(MIN2(MAX2(src0, src1), src2), MIN2(src0, src1)); + + _dst_val.u16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + const uint32_t src2 = + _src[2].u32[_i]; + + uint32_t dst = MAX2(MIN2(MAX2(src0, src1), src2), MIN2(src0, src1)); + + _dst_val.u32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint64_t src0 = + _src[0].u64[_i]; + const uint64_t src1 = + _src[1].u64[_i]; + const uint64_t src2 = + _src[2].u64[_i]; + + uint64_t dst = MAX2(MIN2(MAX2(src0, src1), src2), MIN2(src0, src1)); + + _dst_val.u64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_umin(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint1_t src0 = + _src[0].b[_i]; + const uint1_t src1 = + _src[1].b[_i]; + + uint1_t dst = src1 > src0 ? src0 : src1; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint8_t src0 = + _src[0].u8[_i]; + const uint8_t src1 = + _src[1].u8[_i]; + + uint8_t dst = src1 > src0 ? src0 : src1; + + _dst_val.u8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint16_t src0 = + _src[0].u16[_i]; + const uint16_t src1 = + _src[1].u16[_i]; + + uint16_t dst = src1 > src0 ? src0 : src1; + + _dst_val.u16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + + uint32_t dst = src1 > src0 ? src0 : src1; + + _dst_val.u32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint64_t src0 = + _src[0].u64[_i]; + const uint64_t src1 = + _src[1].u64[_i]; + + uint64_t dst = src1 > src0 ? src0 : src1; + + _dst_val.u64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_umin3(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint1_t src0 = + _src[0].b[_i]; + const uint1_t src1 = + _src[1].b[_i]; + const uint1_t src2 = + _src[2].b[_i]; + + uint1_t dst = MIN2(src0, MIN2(src1, src2)); + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint8_t src0 = + _src[0].u8[_i]; + const uint8_t src1 = + _src[1].u8[_i]; + const uint8_t src2 = + _src[2].u8[_i]; + + uint8_t dst = MIN2(src0, MIN2(src1, src2)); + + _dst_val.u8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint16_t src0 = + _src[0].u16[_i]; + const uint16_t src1 = + _src[1].u16[_i]; + const uint16_t src2 = + _src[2].u16[_i]; + + uint16_t dst = MIN2(src0, MIN2(src1, src2)); + + _dst_val.u16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + const uint32_t src2 = + _src[2].u32[_i]; + + uint32_t dst = MIN2(src0, MIN2(src1, src2)); + + _dst_val.u32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint64_t src0 = + _src[0].u64[_i]; + const uint64_t src1 = + _src[1].u64[_i]; + const uint64_t src2 = + _src[2].u64[_i]; + + uint64_t dst = MIN2(src0, MIN2(src1, src2)); + + _dst_val.u64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_umin_4x8(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + const int32_t src1 = + _src[1].i32[_i]; + + int32_t dst; + + +dst = 0; +for (int i = 0; i < 32; i += 8) { + dst |= MIN2((src0 >> i) & 0xff, (src1 >> i) & 0xff) << i; +} + + + _dst_val.i32[_i] = dst; + } + + + return _dst_val; +} +static nir_const_value +evaluate_umod(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint1_t src0 = + _src[0].b[_i]; + const uint1_t src1 = + _src[1].b[_i]; + + uint1_t dst = src1 == 0 ? 0 : src0 % src1; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint8_t src0 = + _src[0].u8[_i]; + const uint8_t src1 = + _src[1].u8[_i]; + + uint8_t dst = src1 == 0 ? 0 : src0 % src1; + + _dst_val.u8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint16_t src0 = + _src[0].u16[_i]; + const uint16_t src1 = + _src[1].u16[_i]; + + uint16_t dst = src1 == 0 ? 0 : src0 % src1; + + _dst_val.u16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + + uint32_t dst = src1 == 0 ? 0 : src0 % src1; + + _dst_val.u32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint64_t src0 = + _src[0].u64[_i]; + const uint64_t src1 = + _src[1].u64[_i]; + + uint64_t dst = src1 == 0 ? 0 : src0 % src1; + + _dst_val.u64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_umul_high(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint1_t src0 = + _src[0].b[_i]; + const uint1_t src1 = + _src[1].b[_i]; + + uint1_t dst; + + +if (bit_size == 64) { + /* The casts are kind-of annoying but needed to prevent compiler warnings. */ + uint32_t src0_u32[2] = { src0, (uint64_t)src0 >> 32 }; + uint32_t src1_u32[2] = { src1, (uint64_t)src1 >> 32 }; + uint32_t prod_u32[4]; + ubm_mul_u32arr(prod_u32, src0_u32, src1_u32); + dst = (uint64_t)prod_u32[2] | ((uint64_t)prod_u32[3] << 32); +} else { + dst = ((uint64_t)src0 * (uint64_t)src1) >> bit_size; +} + + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint8_t src0 = + _src[0].u8[_i]; + const uint8_t src1 = + _src[1].u8[_i]; + + uint8_t dst; + + +if (bit_size == 64) { + /* The casts are kind-of annoying but needed to prevent compiler warnings. */ + uint32_t src0_u32[2] = { src0, (uint64_t)src0 >> 32 }; + uint32_t src1_u32[2] = { src1, (uint64_t)src1 >> 32 }; + uint32_t prod_u32[4]; + ubm_mul_u32arr(prod_u32, src0_u32, src1_u32); + dst = (uint64_t)prod_u32[2] | ((uint64_t)prod_u32[3] << 32); +} else { + dst = ((uint64_t)src0 * (uint64_t)src1) >> bit_size; +} + + + _dst_val.u8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint16_t src0 = + _src[0].u16[_i]; + const uint16_t src1 = + _src[1].u16[_i]; + + uint16_t dst; + + +if (bit_size == 64) { + /* The casts are kind-of annoying but needed to prevent compiler warnings. */ + uint32_t src0_u32[2] = { src0, (uint64_t)src0 >> 32 }; + uint32_t src1_u32[2] = { src1, (uint64_t)src1 >> 32 }; + uint32_t prod_u32[4]; + ubm_mul_u32arr(prod_u32, src0_u32, src1_u32); + dst = (uint64_t)prod_u32[2] | ((uint64_t)prod_u32[3] << 32); +} else { + dst = ((uint64_t)src0 * (uint64_t)src1) >> bit_size; +} + + + _dst_val.u16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + + uint32_t dst; + + +if (bit_size == 64) { + /* The casts are kind-of annoying but needed to prevent compiler warnings. */ + uint32_t src0_u32[2] = { src0, (uint64_t)src0 >> 32 }; + uint32_t src1_u32[2] = { src1, (uint64_t)src1 >> 32 }; + uint32_t prod_u32[4]; + ubm_mul_u32arr(prod_u32, src0_u32, src1_u32); + dst = (uint64_t)prod_u32[2] | ((uint64_t)prod_u32[3] << 32); +} else { + dst = ((uint64_t)src0 * (uint64_t)src1) >> bit_size; +} + + + _dst_val.u32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint64_t src0 = + _src[0].u64[_i]; + const uint64_t src1 = + _src[1].u64[_i]; + + uint64_t dst; + + +if (bit_size == 64) { + /* The casts are kind-of annoying but needed to prevent compiler warnings. */ + uint32_t src0_u32[2] = { src0, (uint64_t)src0 >> 32 }; + uint32_t src1_u32[2] = { src1, (uint64_t)src1 >> 32 }; + uint32_t prod_u32[4]; + ubm_mul_u32arr(prod_u32, src0_u32, src1_u32); + dst = (uint64_t)prod_u32[2] | ((uint64_t)prod_u32[3] << 32); +} else { + dst = ((uint64_t)src0 * (uint64_t)src1) >> bit_size; +} + + + _dst_val.u64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_umul_unorm_4x8(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + const int32_t src1 = + _src[1].i32[_i]; + + int32_t dst; + + +dst = 0; +for (int i = 0; i < 32; i += 8) { + int src0_chan = (src0 >> i) & 0xff; + int src1_chan = (src1 >> i) & 0xff; + dst |= ((src0_chan * src1_chan) / 255) << i; +} + + + _dst_val.i32[_i] = dst; + } + + + return _dst_val; +} +static nir_const_value +evaluate_unpack_32_2x16(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + const struct uint32_vec src0 = { + _src[0].u32[0], + 0, + 0, + 0, + }; + + struct uint16_vec dst; + + dst.x = src0.x; dst.y = src0.x >> 16; + + _dst_val.u16[0] = dst.x; + _dst_val.u16[1] = dst.y; + + + return _dst_val; +} +static nir_const_value +evaluate_unpack_32_2x16_split_x(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + + uint16_t dst = src0; + + _dst_val.u16[_i] = dst; + } + + + return _dst_val; +} +static nir_const_value +evaluate_unpack_32_2x16_split_y(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + + uint16_t dst = src0 >> 16; + + _dst_val.u16[_i] = dst; + } + + + return _dst_val; +} +static nir_const_value +evaluate_unpack_64_2x32(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + const struct uint64_vec src0 = { + _src[0].u64[0], + 0, + 0, + 0, + }; + + struct uint32_vec dst; + + dst.x = src0.x; dst.y = src0.x >> 32; + + _dst_val.u32[0] = dst.x; + _dst_val.u32[1] = dst.y; + + + return _dst_val; +} +static nir_const_value +evaluate_unpack_64_2x32_split_x(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint64_t src0 = + _src[0].u64[_i]; + + uint32_t dst = src0; + + _dst_val.u32[_i] = dst; + } + + + return _dst_val; +} +static nir_const_value +evaluate_unpack_64_2x32_split_y(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint64_t src0 = + _src[0].u64[_i]; + + uint32_t dst = src0 >> 32; + + _dst_val.u32[_i] = dst; + } + + + return _dst_val; +} +static nir_const_value +evaluate_unpack_64_4x16(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + const struct uint64_vec src0 = { + _src[0].u64[0], + 0, + 0, + 0, + }; + + struct uint16_vec dst; + + dst.x = src0.x; dst.y = src0.x >> 16; dst.z = src0.x >> 32; dst.w = src0.w >> 48; + + _dst_val.u16[0] = dst.x; + _dst_val.u16[1] = dst.y; + _dst_val.u16[2] = dst.z; + _dst_val.u16[3] = dst.w; + + + return _dst_val; +} +static nir_const_value +evaluate_unpack_half_2x16(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + const struct uint32_vec src0 = { + _src[0].u32[0], + 0, + 0, + 0, + }; + + struct float32_vec dst; + + +dst.x = unpack_half_1x16((uint16_t)(src0.x & 0xffff)); +dst.y = unpack_half_1x16((uint16_t)(src0.x << 16)); + + + _dst_val.f32[0] = dst.x; + _dst_val.f32[1] = dst.y; + + + return _dst_val; +} +static nir_const_value +evaluate_unpack_half_2x16_split_x(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + + float32_t dst = unpack_half_1x16((uint16_t)(src0 & 0xffff)); + + _dst_val.f32[_i] = dst; + } + + + return _dst_val; +} +static nir_const_value +evaluate_unpack_half_2x16_split_y(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + + float32_t dst = unpack_half_1x16((uint16_t)(src0 >> 16)); + + _dst_val.f32[_i] = dst; + } + + + return _dst_val; +} +static nir_const_value +evaluate_unpack_snorm_2x16(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + const struct uint32_vec src0 = { + _src[0].u32[0], + 0, + 0, + 0, + }; + + struct float32_vec dst; + + +dst.x = unpack_snorm_1x16((uint16_t)(src0.x & 0xffff)); +dst.y = unpack_snorm_1x16((uint16_t)(src0.x << 16)); + + + _dst_val.f32[0] = dst.x; + _dst_val.f32[1] = dst.y; + + + return _dst_val; +} +static nir_const_value +evaluate_unpack_snorm_4x8(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + const struct uint32_vec src0 = { + _src[0].u32[0], + 0, + 0, + 0, + }; + + struct float32_vec dst; + + +dst.x = unpack_snorm_1x8((uint8_t)(src0.x & 0xff)); +dst.y = unpack_snorm_1x8((uint8_t)((src0.x >> 8) & 0xff)); +dst.z = unpack_snorm_1x8((uint8_t)((src0.x >> 16) & 0xff)); +dst.w = unpack_snorm_1x8((uint8_t)(src0.x >> 24)); + + + _dst_val.f32[0] = dst.x; + _dst_val.f32[1] = dst.y; + _dst_val.f32[2] = dst.z; + _dst_val.f32[3] = dst.w; + + + return _dst_val; +} +static nir_const_value +evaluate_unpack_unorm_2x16(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + const struct uint32_vec src0 = { + _src[0].u32[0], + 0, + 0, + 0, + }; + + struct float32_vec dst; + + +dst.x = unpack_unorm_1x16((uint16_t)(src0.x & 0xffff)); +dst.y = unpack_unorm_1x16((uint16_t)(src0.x << 16)); + + + _dst_val.f32[0] = dst.x; + _dst_val.f32[1] = dst.y; + + + return _dst_val; +} +static nir_const_value +evaluate_unpack_unorm_4x8(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + const struct uint32_vec src0 = { + _src[0].u32[0], + 0, + 0, + 0, + }; + + struct float32_vec dst; + + +dst.x = unpack_unorm_1x8((uint8_t)(src0.x & 0xff)); +dst.y = unpack_unorm_1x8((uint8_t)((src0.x >> 8) & 0xff)); +dst.z = unpack_unorm_1x8((uint8_t)((src0.x >> 16) & 0xff)); +dst.w = unpack_unorm_1x8((uint8_t)(src0.x >> 24)); + + + _dst_val.f32[0] = dst.x; + _dst_val.f32[1] = dst.y; + _dst_val.f32[2] = dst.z; + _dst_val.f32[3] = dst.w; + + + return _dst_val; +} +static nir_const_value +evaluate_usadd_4x8(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + const int32_t src1 = + _src[1].i32[_i]; + + int32_t dst; + + +dst = 0; +for (int i = 0; i < 32; i += 8) { + dst |= MIN2(((src0 >> i) & 0xff) + ((src1 >> i) & 0xff), 0xff) << i; +} + + + _dst_val.i32[_i] = dst; + } + + + return _dst_val; +} +static nir_const_value +evaluate_ushr(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint1_t src0 = + _src[0].b[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + + uint1_t dst = src0 >> src1; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint8_t src0 = + _src[0].u8[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + + uint8_t dst = src0 >> src1; + + _dst_val.u8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint16_t src0 = + _src[0].u16[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + + uint16_t dst = src0 >> src1; + + _dst_val.u16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + + uint32_t dst = src0 >> src1; + + _dst_val.u32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint64_t src0 = + _src[0].u64[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + + uint64_t dst = src0 >> src1; + + _dst_val.u64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_ussub_4x8(MAYBE_UNUSED unsigned num_components, + UNUSED unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const int32_t src0 = + _src[0].i32[_i]; + const int32_t src1 = + _src[1].i32[_i]; + + int32_t dst; + + +dst = 0; +for (int i = 0; i < 32; i += 8) { + int src0_chan = (src0 >> i) & 0xff; + int src1_chan = (src1 >> i) & 0xff; + if (src0_chan > src1_chan) + dst |= (src0_chan - src1_chan) << i; +} + + + _dst_val.i32[_i] = dst; + } + + + return _dst_val; +} +static nir_const_value +evaluate_usub_borrow(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint1_t src0 = + _src[0].b[_i]; + const uint1_t src1 = + _src[1].b[_i]; + + uint1_t dst = src0 < src1; + + /* 1-bit integers get truncated */ + _dst_val.b[_i] = dst & 1; + } + + break; + } + case 8: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint8_t src0 = + _src[0].u8[_i]; + const uint8_t src1 = + _src[1].u8[_i]; + + uint8_t dst = src0 < src1; + + _dst_val.u8[_i] = dst; + } + + break; + } + case 16: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint16_t src0 = + _src[0].u16[_i]; + const uint16_t src1 = + _src[1].u16[_i]; + + uint16_t dst = src0 < src1; + + _dst_val.u16[_i] = dst; + } + + break; + } + case 32: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint32_t src0 = + _src[0].u32[_i]; + const uint32_t src1 = + _src[1].u32[_i]; + + uint32_t dst = src0 < src1; + + _dst_val.u32[_i] = dst; + } + + break; + } + case 64: { + + + + + for (unsigned _i = 0; _i < num_components; _i++) { + const uint64_t src0 = + _src[0].u64[_i]; + const uint64_t src1 = + _src[1].u64[_i]; + + uint64_t dst = src0 < src1; + + _dst_val.u64[_i] = dst; + } + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_vec2(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + const struct uint1_vec src0 = { + _src[0].b[0], + 0, + 0, + 0, + }; + + const struct uint1_vec src1 = { + _src[1].b[0], + 0, + 0, + 0, + }; + + struct uint1_vec dst; + + +dst.x = src0.x; +dst.y = src1.x; + + + /* 1-bit integers get truncated */ + _dst_val.b[0] = dst.x & 1; + /* 1-bit integers get truncated */ + _dst_val.b[1] = dst.y & 1; + + break; + } + case 8: { + + + + + const struct uint8_vec src0 = { + _src[0].u8[0], + 0, + 0, + 0, + }; + + const struct uint8_vec src1 = { + _src[1].u8[0], + 0, + 0, + 0, + }; + + struct uint8_vec dst; + + +dst.x = src0.x; +dst.y = src1.x; + + + _dst_val.u8[0] = dst.x; + _dst_val.u8[1] = dst.y; + + break; + } + case 16: { + + + + + const struct uint16_vec src0 = { + _src[0].u16[0], + 0, + 0, + 0, + }; + + const struct uint16_vec src1 = { + _src[1].u16[0], + 0, + 0, + 0, + }; + + struct uint16_vec dst; + + +dst.x = src0.x; +dst.y = src1.x; + + + _dst_val.u16[0] = dst.x; + _dst_val.u16[1] = dst.y; + + break; + } + case 32: { + + + + + const struct uint32_vec src0 = { + _src[0].u32[0], + 0, + 0, + 0, + }; + + const struct uint32_vec src1 = { + _src[1].u32[0], + 0, + 0, + 0, + }; + + struct uint32_vec dst; + + +dst.x = src0.x; +dst.y = src1.x; + + + _dst_val.u32[0] = dst.x; + _dst_val.u32[1] = dst.y; + + break; + } + case 64: { + + + + + const struct uint64_vec src0 = { + _src[0].u64[0], + 0, + 0, + 0, + }; + + const struct uint64_vec src1 = { + _src[1].u64[0], + 0, + 0, + 0, + }; + + struct uint64_vec dst; + + +dst.x = src0.x; +dst.y = src1.x; + + + _dst_val.u64[0] = dst.x; + _dst_val.u64[1] = dst.y; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_vec3(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + const struct uint1_vec src0 = { + _src[0].b[0], + 0, + 0, + 0, + }; + + const struct uint1_vec src1 = { + _src[1].b[0], + 0, + 0, + 0, + }; + + const struct uint1_vec src2 = { + _src[2].b[0], + 0, + 0, + 0, + }; + + struct uint1_vec dst; + + +dst.x = src0.x; +dst.y = src1.x; +dst.z = src2.x; + + + /* 1-bit integers get truncated */ + _dst_val.b[0] = dst.x & 1; + /* 1-bit integers get truncated */ + _dst_val.b[1] = dst.y & 1; + /* 1-bit integers get truncated */ + _dst_val.b[2] = dst.z & 1; + + break; + } + case 8: { + + + + + const struct uint8_vec src0 = { + _src[0].u8[0], + 0, + 0, + 0, + }; + + const struct uint8_vec src1 = { + _src[1].u8[0], + 0, + 0, + 0, + }; + + const struct uint8_vec src2 = { + _src[2].u8[0], + 0, + 0, + 0, + }; + + struct uint8_vec dst; + + +dst.x = src0.x; +dst.y = src1.x; +dst.z = src2.x; + + + _dst_val.u8[0] = dst.x; + _dst_val.u8[1] = dst.y; + _dst_val.u8[2] = dst.z; + + break; + } + case 16: { + + + + + const struct uint16_vec src0 = { + _src[0].u16[0], + 0, + 0, + 0, + }; + + const struct uint16_vec src1 = { + _src[1].u16[0], + 0, + 0, + 0, + }; + + const struct uint16_vec src2 = { + _src[2].u16[0], + 0, + 0, + 0, + }; + + struct uint16_vec dst; + + +dst.x = src0.x; +dst.y = src1.x; +dst.z = src2.x; + + + _dst_val.u16[0] = dst.x; + _dst_val.u16[1] = dst.y; + _dst_val.u16[2] = dst.z; + + break; + } + case 32: { + + + + + const struct uint32_vec src0 = { + _src[0].u32[0], + 0, + 0, + 0, + }; + + const struct uint32_vec src1 = { + _src[1].u32[0], + 0, + 0, + 0, + }; + + const struct uint32_vec src2 = { + _src[2].u32[0], + 0, + 0, + 0, + }; + + struct uint32_vec dst; + + +dst.x = src0.x; +dst.y = src1.x; +dst.z = src2.x; + + + _dst_val.u32[0] = dst.x; + _dst_val.u32[1] = dst.y; + _dst_val.u32[2] = dst.z; + + break; + } + case 64: { + + + + + const struct uint64_vec src0 = { + _src[0].u64[0], + 0, + 0, + 0, + }; + + const struct uint64_vec src1 = { + _src[1].u64[0], + 0, + 0, + 0, + }; + + const struct uint64_vec src2 = { + _src[2].u64[0], + 0, + 0, + 0, + }; + + struct uint64_vec dst; + + +dst.x = src0.x; +dst.y = src1.x; +dst.z = src2.x; + + + _dst_val.u64[0] = dst.x; + _dst_val.u64[1] = dst.y; + _dst_val.u64[2] = dst.z; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} +static nir_const_value +evaluate_vec4(MAYBE_UNUSED unsigned num_components, + unsigned bit_size, + MAYBE_UNUSED nir_const_value *_src) +{ + nir_const_value _dst_val = { {0, } }; + + switch (bit_size) { + case 1: { + + + + + const struct uint1_vec src0 = { + _src[0].b[0], + 0, + 0, + 0, + }; + + const struct uint1_vec src1 = { + _src[1].b[0], + 0, + 0, + 0, + }; + + const struct uint1_vec src2 = { + _src[2].b[0], + 0, + 0, + 0, + }; + + const struct uint1_vec src3 = { + _src[3].b[0], + 0, + 0, + 0, + }; + + struct uint1_vec dst; + + +dst.x = src0.x; +dst.y = src1.x; +dst.z = src2.x; +dst.w = src3.x; + + + /* 1-bit integers get truncated */ + _dst_val.b[0] = dst.x & 1; + /* 1-bit integers get truncated */ + _dst_val.b[1] = dst.y & 1; + /* 1-bit integers get truncated */ + _dst_val.b[2] = dst.z & 1; + /* 1-bit integers get truncated */ + _dst_val.b[3] = dst.w & 1; + + break; + } + case 8: { + + + + + const struct uint8_vec src0 = { + _src[0].u8[0], + 0, + 0, + 0, + }; + + const struct uint8_vec src1 = { + _src[1].u8[0], + 0, + 0, + 0, + }; + + const struct uint8_vec src2 = { + _src[2].u8[0], + 0, + 0, + 0, + }; + + const struct uint8_vec src3 = { + _src[3].u8[0], + 0, + 0, + 0, + }; + + struct uint8_vec dst; + + +dst.x = src0.x; +dst.y = src1.x; +dst.z = src2.x; +dst.w = src3.x; + + + _dst_val.u8[0] = dst.x; + _dst_val.u8[1] = dst.y; + _dst_val.u8[2] = dst.z; + _dst_val.u8[3] = dst.w; + + break; + } + case 16: { + + + + + const struct uint16_vec src0 = { + _src[0].u16[0], + 0, + 0, + 0, + }; + + const struct uint16_vec src1 = { + _src[1].u16[0], + 0, + 0, + 0, + }; + + const struct uint16_vec src2 = { + _src[2].u16[0], + 0, + 0, + 0, + }; + + const struct uint16_vec src3 = { + _src[3].u16[0], + 0, + 0, + 0, + }; + + struct uint16_vec dst; + + +dst.x = src0.x; +dst.y = src1.x; +dst.z = src2.x; +dst.w = src3.x; + + + _dst_val.u16[0] = dst.x; + _dst_val.u16[1] = dst.y; + _dst_val.u16[2] = dst.z; + _dst_val.u16[3] = dst.w; + + break; + } + case 32: { + + + + + const struct uint32_vec src0 = { + _src[0].u32[0], + 0, + 0, + 0, + }; + + const struct uint32_vec src1 = { + _src[1].u32[0], + 0, + 0, + 0, + }; + + const struct uint32_vec src2 = { + _src[2].u32[0], + 0, + 0, + 0, + }; + + const struct uint32_vec src3 = { + _src[3].u32[0], + 0, + 0, + 0, + }; + + struct uint32_vec dst; + + +dst.x = src0.x; +dst.y = src1.x; +dst.z = src2.x; +dst.w = src3.x; + + + _dst_val.u32[0] = dst.x; + _dst_val.u32[1] = dst.y; + _dst_val.u32[2] = dst.z; + _dst_val.u32[3] = dst.w; + + break; + } + case 64: { + + + + + const struct uint64_vec src0 = { + _src[0].u64[0], + 0, + 0, + 0, + }; + + const struct uint64_vec src1 = { + _src[1].u64[0], + 0, + 0, + 0, + }; + + const struct uint64_vec src2 = { + _src[2].u64[0], + 0, + 0, + 0, + }; + + const struct uint64_vec src3 = { + _src[3].u64[0], + 0, + 0, + 0, + }; + + struct uint64_vec dst; + + +dst.x = src0.x; +dst.y = src1.x; +dst.z = src2.x; +dst.w = src3.x; + + + _dst_val.u64[0] = dst.x; + _dst_val.u64[1] = dst.y; + _dst_val.u64[2] = dst.z; + _dst_val.u64[3] = dst.w; + + break; + } + + default: + unreachable("unknown bit width"); + } + + return _dst_val; +} + +nir_const_value +nir_eval_const_opcode(nir_op op, unsigned num_components, + unsigned bit_width, nir_const_value *src) +{ + switch (op) { + case nir_op_b2f16: + return evaluate_b2f16(num_components, bit_width, src); + case nir_op_b2f32: + return evaluate_b2f32(num_components, bit_width, src); + case nir_op_b2f64: + return evaluate_b2f64(num_components, bit_width, src); + case nir_op_b2i1: + return evaluate_b2i1(num_components, bit_width, src); + case nir_op_b2i16: + return evaluate_b2i16(num_components, bit_width, src); + case nir_op_b2i32: + return evaluate_b2i32(num_components, bit_width, src); + case nir_op_b2i64: + return evaluate_b2i64(num_components, bit_width, src); + case nir_op_b2i8: + return evaluate_b2i8(num_components, bit_width, src); + case nir_op_b32all_fequal2: + return evaluate_b32all_fequal2(num_components, bit_width, src); + case nir_op_b32all_fequal3: + return evaluate_b32all_fequal3(num_components, bit_width, src); + case nir_op_b32all_fequal4: + return evaluate_b32all_fequal4(num_components, bit_width, src); + case nir_op_b32all_iequal2: + return evaluate_b32all_iequal2(num_components, bit_width, src); + case nir_op_b32all_iequal3: + return evaluate_b32all_iequal3(num_components, bit_width, src); + case nir_op_b32all_iequal4: + return evaluate_b32all_iequal4(num_components, bit_width, src); + case nir_op_b32any_fnequal2: + return evaluate_b32any_fnequal2(num_components, bit_width, src); + case nir_op_b32any_fnequal3: + return evaluate_b32any_fnequal3(num_components, bit_width, src); + case nir_op_b32any_fnequal4: + return evaluate_b32any_fnequal4(num_components, bit_width, src); + case nir_op_b32any_inequal2: + return evaluate_b32any_inequal2(num_components, bit_width, src); + case nir_op_b32any_inequal3: + return evaluate_b32any_inequal3(num_components, bit_width, src); + case nir_op_b32any_inequal4: + return evaluate_b32any_inequal4(num_components, bit_width, src); + case nir_op_b32csel: + return evaluate_b32csel(num_components, bit_width, src); + case nir_op_ball_fequal2: + return evaluate_ball_fequal2(num_components, bit_width, src); + case nir_op_ball_fequal3: + return evaluate_ball_fequal3(num_components, bit_width, src); + case nir_op_ball_fequal4: + return evaluate_ball_fequal4(num_components, bit_width, src); + case nir_op_ball_iequal2: + return evaluate_ball_iequal2(num_components, bit_width, src); + case nir_op_ball_iequal3: + return evaluate_ball_iequal3(num_components, bit_width, src); + case nir_op_ball_iequal4: + return evaluate_ball_iequal4(num_components, bit_width, src); + case nir_op_bany_fnequal2: + return evaluate_bany_fnequal2(num_components, bit_width, src); + case nir_op_bany_fnequal3: + return evaluate_bany_fnequal3(num_components, bit_width, src); + case nir_op_bany_fnequal4: + return evaluate_bany_fnequal4(num_components, bit_width, src); + case nir_op_bany_inequal2: + return evaluate_bany_inequal2(num_components, bit_width, src); + case nir_op_bany_inequal3: + return evaluate_bany_inequal3(num_components, bit_width, src); + case nir_op_bany_inequal4: + return evaluate_bany_inequal4(num_components, bit_width, src); + case nir_op_bcsel: + return evaluate_bcsel(num_components, bit_width, src); + case nir_op_bfi: + return evaluate_bfi(num_components, bit_width, src); + case nir_op_bfm: + return evaluate_bfm(num_components, bit_width, src); + case nir_op_bit_count: + return evaluate_bit_count(num_components, bit_width, src); + case nir_op_bitfield_insert: + return evaluate_bitfield_insert(num_components, bit_width, src); + case nir_op_bitfield_reverse: + return evaluate_bitfield_reverse(num_components, bit_width, src); + case nir_op_cube_face_coord: + return evaluate_cube_face_coord(num_components, bit_width, src); + case nir_op_cube_face_index: + return evaluate_cube_face_index(num_components, bit_width, src); + case nir_op_extract_i16: + return evaluate_extract_i16(num_components, bit_width, src); + case nir_op_extract_i8: + return evaluate_extract_i8(num_components, bit_width, src); + case nir_op_extract_u16: + return evaluate_extract_u16(num_components, bit_width, src); + case nir_op_extract_u8: + return evaluate_extract_u8(num_components, bit_width, src); + case nir_op_f2b1: + return evaluate_f2b1(num_components, bit_width, src); + case nir_op_f2b32: + return evaluate_f2b32(num_components, bit_width, src); + case nir_op_f2f16: + return evaluate_f2f16(num_components, bit_width, src); + case nir_op_f2f16_rtne: + return evaluate_f2f16_rtne(num_components, bit_width, src); + case nir_op_f2f16_rtz: + return evaluate_f2f16_rtz(num_components, bit_width, src); + case nir_op_f2f32: + return evaluate_f2f32(num_components, bit_width, src); + case nir_op_f2f64: + return evaluate_f2f64(num_components, bit_width, src); + case nir_op_f2i1: + return evaluate_f2i1(num_components, bit_width, src); + case nir_op_f2i16: + return evaluate_f2i16(num_components, bit_width, src); + case nir_op_f2i32: + return evaluate_f2i32(num_components, bit_width, src); + case nir_op_f2i64: + return evaluate_f2i64(num_components, bit_width, src); + case nir_op_f2i8: + return evaluate_f2i8(num_components, bit_width, src); + case nir_op_f2u1: + return evaluate_f2u1(num_components, bit_width, src); + case nir_op_f2u16: + return evaluate_f2u16(num_components, bit_width, src); + case nir_op_f2u32: + return evaluate_f2u32(num_components, bit_width, src); + case nir_op_f2u64: + return evaluate_f2u64(num_components, bit_width, src); + case nir_op_f2u8: + return evaluate_f2u8(num_components, bit_width, src); + case nir_op_fabs: + return evaluate_fabs(num_components, bit_width, src); + case nir_op_fadd: + return evaluate_fadd(num_components, bit_width, src); + case nir_op_fall_equal2: + return evaluate_fall_equal2(num_components, bit_width, src); + case nir_op_fall_equal3: + return evaluate_fall_equal3(num_components, bit_width, src); + case nir_op_fall_equal4: + return evaluate_fall_equal4(num_components, bit_width, src); + case nir_op_fand: + return evaluate_fand(num_components, bit_width, src); + case nir_op_fany_nequal2: + return evaluate_fany_nequal2(num_components, bit_width, src); + case nir_op_fany_nequal3: + return evaluate_fany_nequal3(num_components, bit_width, src); + case nir_op_fany_nequal4: + return evaluate_fany_nequal4(num_components, bit_width, src); + case nir_op_fceil: + return evaluate_fceil(num_components, bit_width, src); + case nir_op_fcos: + return evaluate_fcos(num_components, bit_width, src); + case nir_op_fcsel: + return evaluate_fcsel(num_components, bit_width, src); + case nir_op_fddx: + return evaluate_fddx(num_components, bit_width, src); + case nir_op_fddx_coarse: + return evaluate_fddx_coarse(num_components, bit_width, src); + case nir_op_fddx_fine: + return evaluate_fddx_fine(num_components, bit_width, src); + case nir_op_fddy: + return evaluate_fddy(num_components, bit_width, src); + case nir_op_fddy_coarse: + return evaluate_fddy_coarse(num_components, bit_width, src); + case nir_op_fddy_fine: + return evaluate_fddy_fine(num_components, bit_width, src); + case nir_op_fdiv: + return evaluate_fdiv(num_components, bit_width, src); + case nir_op_fdot2: + return evaluate_fdot2(num_components, bit_width, src); + case nir_op_fdot3: + return evaluate_fdot3(num_components, bit_width, src); + case nir_op_fdot4: + return evaluate_fdot4(num_components, bit_width, src); + case nir_op_fdot_replicated2: + return evaluate_fdot_replicated2(num_components, bit_width, src); + case nir_op_fdot_replicated3: + return evaluate_fdot_replicated3(num_components, bit_width, src); + case nir_op_fdot_replicated4: + return evaluate_fdot_replicated4(num_components, bit_width, src); + case nir_op_fdph: + return evaluate_fdph(num_components, bit_width, src); + case nir_op_fdph_replicated: + return evaluate_fdph_replicated(num_components, bit_width, src); + case nir_op_feq: + return evaluate_feq(num_components, bit_width, src); + case nir_op_feq32: + return evaluate_feq32(num_components, bit_width, src); + case nir_op_fexp2: + return evaluate_fexp2(num_components, bit_width, src); + case nir_op_ffloor: + return evaluate_ffloor(num_components, bit_width, src); + case nir_op_ffma: + return evaluate_ffma(num_components, bit_width, src); + case nir_op_ffract: + return evaluate_ffract(num_components, bit_width, src); + case nir_op_fge: + return evaluate_fge(num_components, bit_width, src); + case nir_op_fge32: + return evaluate_fge32(num_components, bit_width, src); + case nir_op_find_lsb: + return evaluate_find_lsb(num_components, bit_width, src); + case nir_op_flog2: + return evaluate_flog2(num_components, bit_width, src); + case nir_op_flrp: + return evaluate_flrp(num_components, bit_width, src); + case nir_op_flt: + return evaluate_flt(num_components, bit_width, src); + case nir_op_flt32: + return evaluate_flt32(num_components, bit_width, src); + case nir_op_fmax: + return evaluate_fmax(num_components, bit_width, src); + case nir_op_fmax3: + return evaluate_fmax3(num_components, bit_width, src); + case nir_op_fmed3: + return evaluate_fmed3(num_components, bit_width, src); + case nir_op_fmin: + return evaluate_fmin(num_components, bit_width, src); + case nir_op_fmin3: + return evaluate_fmin3(num_components, bit_width, src); + case nir_op_fmod: + return evaluate_fmod(num_components, bit_width, src); + case nir_op_fmov: + return evaluate_fmov(num_components, bit_width, src); + case nir_op_fmul: + return evaluate_fmul(num_components, bit_width, src); + case nir_op_fne: + return evaluate_fne(num_components, bit_width, src); + case nir_op_fne32: + return evaluate_fne32(num_components, bit_width, src); + case nir_op_fneg: + return evaluate_fneg(num_components, bit_width, src); + case nir_op_fnoise1_1: + return evaluate_fnoise1_1(num_components, bit_width, src); + case nir_op_fnoise1_2: + return evaluate_fnoise1_2(num_components, bit_width, src); + case nir_op_fnoise1_3: + return evaluate_fnoise1_3(num_components, bit_width, src); + case nir_op_fnoise1_4: + return evaluate_fnoise1_4(num_components, bit_width, src); + case nir_op_fnoise2_1: + return evaluate_fnoise2_1(num_components, bit_width, src); + case nir_op_fnoise2_2: + return evaluate_fnoise2_2(num_components, bit_width, src); + case nir_op_fnoise2_3: + return evaluate_fnoise2_3(num_components, bit_width, src); + case nir_op_fnoise2_4: + return evaluate_fnoise2_4(num_components, bit_width, src); + case nir_op_fnoise3_1: + return evaluate_fnoise3_1(num_components, bit_width, src); + case nir_op_fnoise3_2: + return evaluate_fnoise3_2(num_components, bit_width, src); + case nir_op_fnoise3_3: + return evaluate_fnoise3_3(num_components, bit_width, src); + case nir_op_fnoise3_4: + return evaluate_fnoise3_4(num_components, bit_width, src); + case nir_op_fnoise4_1: + return evaluate_fnoise4_1(num_components, bit_width, src); + case nir_op_fnoise4_2: + return evaluate_fnoise4_2(num_components, bit_width, src); + case nir_op_fnoise4_3: + return evaluate_fnoise4_3(num_components, bit_width, src); + case nir_op_fnoise4_4: + return evaluate_fnoise4_4(num_components, bit_width, src); + case nir_op_fnot: + return evaluate_fnot(num_components, bit_width, src); + case nir_op_for: + return evaluate_for(num_components, bit_width, src); + case nir_op_fpow: + return evaluate_fpow(num_components, bit_width, src); + case nir_op_fquantize2f16: + return evaluate_fquantize2f16(num_components, bit_width, src); + case nir_op_frcp: + return evaluate_frcp(num_components, bit_width, src); + case nir_op_frem: + return evaluate_frem(num_components, bit_width, src); + case nir_op_frexp_exp: + return evaluate_frexp_exp(num_components, bit_width, src); + case nir_op_frexp_sig: + return evaluate_frexp_sig(num_components, bit_width, src); + case nir_op_fround_even: + return evaluate_fround_even(num_components, bit_width, src); + case nir_op_frsq: + return evaluate_frsq(num_components, bit_width, src); + case nir_op_fsat: + return evaluate_fsat(num_components, bit_width, src); + case nir_op_fsign: + return evaluate_fsign(num_components, bit_width, src); + case nir_op_fsin: + return evaluate_fsin(num_components, bit_width, src); + case nir_op_fsqrt: + return evaluate_fsqrt(num_components, bit_width, src); + case nir_op_fsub: + return evaluate_fsub(num_components, bit_width, src); + case nir_op_ftrunc: + return evaluate_ftrunc(num_components, bit_width, src); + case nir_op_fxor: + return evaluate_fxor(num_components, bit_width, src); + case nir_op_i2b1: + return evaluate_i2b1(num_components, bit_width, src); + case nir_op_i2b32: + return evaluate_i2b32(num_components, bit_width, src); + case nir_op_i2f16: + return evaluate_i2f16(num_components, bit_width, src); + case nir_op_i2f32: + return evaluate_i2f32(num_components, bit_width, src); + case nir_op_i2f64: + return evaluate_i2f64(num_components, bit_width, src); + case nir_op_i2i1: + return evaluate_i2i1(num_components, bit_width, src); + case nir_op_i2i16: + return evaluate_i2i16(num_components, bit_width, src); + case nir_op_i2i32: + return evaluate_i2i32(num_components, bit_width, src); + case nir_op_i2i64: + return evaluate_i2i64(num_components, bit_width, src); + case nir_op_i2i8: + return evaluate_i2i8(num_components, bit_width, src); + case nir_op_iabs: + return evaluate_iabs(num_components, bit_width, src); + case nir_op_iadd: + return evaluate_iadd(num_components, bit_width, src); + case nir_op_iand: + return evaluate_iand(num_components, bit_width, src); + case nir_op_ibfe: + return evaluate_ibfe(num_components, bit_width, src); + case nir_op_ibitfield_extract: + return evaluate_ibitfield_extract(num_components, bit_width, src); + case nir_op_idiv: + return evaluate_idiv(num_components, bit_width, src); + case nir_op_ieq: + return evaluate_ieq(num_components, bit_width, src); + case nir_op_ieq32: + return evaluate_ieq32(num_components, bit_width, src); + case nir_op_ifind_msb: + return evaluate_ifind_msb(num_components, bit_width, src); + case nir_op_ige: + return evaluate_ige(num_components, bit_width, src); + case nir_op_ige32: + return evaluate_ige32(num_components, bit_width, src); + case nir_op_ilt: + return evaluate_ilt(num_components, bit_width, src); + case nir_op_ilt32: + return evaluate_ilt32(num_components, bit_width, src); + case nir_op_imax: + return evaluate_imax(num_components, bit_width, src); + case nir_op_imax3: + return evaluate_imax3(num_components, bit_width, src); + case nir_op_imed3: + return evaluate_imed3(num_components, bit_width, src); + case nir_op_imin: + return evaluate_imin(num_components, bit_width, src); + case nir_op_imin3: + return evaluate_imin3(num_components, bit_width, src); + case nir_op_imod: + return evaluate_imod(num_components, bit_width, src); + case nir_op_imov: + return evaluate_imov(num_components, bit_width, src); + case nir_op_imul: + return evaluate_imul(num_components, bit_width, src); + case nir_op_imul_high: + return evaluate_imul_high(num_components, bit_width, src); + case nir_op_ine: + return evaluate_ine(num_components, bit_width, src); + case nir_op_ine32: + return evaluate_ine32(num_components, bit_width, src); + case nir_op_ineg: + return evaluate_ineg(num_components, bit_width, src); + case nir_op_inot: + return evaluate_inot(num_components, bit_width, src); + case nir_op_ior: + return evaluate_ior(num_components, bit_width, src); + case nir_op_irem: + return evaluate_irem(num_components, bit_width, src); + case nir_op_ishl: + return evaluate_ishl(num_components, bit_width, src); + case nir_op_ishr: + return evaluate_ishr(num_components, bit_width, src); + case nir_op_isign: + return evaluate_isign(num_components, bit_width, src); + case nir_op_isub: + return evaluate_isub(num_components, bit_width, src); + case nir_op_ixor: + return evaluate_ixor(num_components, bit_width, src); + case nir_op_ldexp: + return evaluate_ldexp(num_components, bit_width, src); + case nir_op_pack_32_2x16: + return evaluate_pack_32_2x16(num_components, bit_width, src); + case nir_op_pack_32_2x16_split: + return evaluate_pack_32_2x16_split(num_components, bit_width, src); + case nir_op_pack_64_2x32: + return evaluate_pack_64_2x32(num_components, bit_width, src); + case nir_op_pack_64_2x32_split: + return evaluate_pack_64_2x32_split(num_components, bit_width, src); + case nir_op_pack_64_4x16: + return evaluate_pack_64_4x16(num_components, bit_width, src); + case nir_op_pack_half_2x16: + return evaluate_pack_half_2x16(num_components, bit_width, src); + case nir_op_pack_half_2x16_split: + return evaluate_pack_half_2x16_split(num_components, bit_width, src); + case nir_op_pack_snorm_2x16: + return evaluate_pack_snorm_2x16(num_components, bit_width, src); + case nir_op_pack_snorm_4x8: + return evaluate_pack_snorm_4x8(num_components, bit_width, src); + case nir_op_pack_unorm_2x16: + return evaluate_pack_unorm_2x16(num_components, bit_width, src); + case nir_op_pack_unorm_4x8: + return evaluate_pack_unorm_4x8(num_components, bit_width, src); + case nir_op_pack_uvec2_to_uint: + return evaluate_pack_uvec2_to_uint(num_components, bit_width, src); + case nir_op_pack_uvec4_to_uint: + return evaluate_pack_uvec4_to_uint(num_components, bit_width, src); + case nir_op_seq: + return evaluate_seq(num_components, bit_width, src); + case nir_op_sge: + return evaluate_sge(num_components, bit_width, src); + case nir_op_slt: + return evaluate_slt(num_components, bit_width, src); + case nir_op_sne: + return evaluate_sne(num_components, bit_width, src); + case nir_op_u2f16: + return evaluate_u2f16(num_components, bit_width, src); + case nir_op_u2f32: + return evaluate_u2f32(num_components, bit_width, src); + case nir_op_u2f64: + return evaluate_u2f64(num_components, bit_width, src); + case nir_op_u2u1: + return evaluate_u2u1(num_components, bit_width, src); + case nir_op_u2u16: + return evaluate_u2u16(num_components, bit_width, src); + case nir_op_u2u32: + return evaluate_u2u32(num_components, bit_width, src); + case nir_op_u2u64: + return evaluate_u2u64(num_components, bit_width, src); + case nir_op_u2u8: + return evaluate_u2u8(num_components, bit_width, src); + case nir_op_uadd_carry: + return evaluate_uadd_carry(num_components, bit_width, src); + case nir_op_uadd_sat: + return evaluate_uadd_sat(num_components, bit_width, src); + case nir_op_ubfe: + return evaluate_ubfe(num_components, bit_width, src); + case nir_op_ubitfield_extract: + return evaluate_ubitfield_extract(num_components, bit_width, src); + case nir_op_udiv: + return evaluate_udiv(num_components, bit_width, src); + case nir_op_ufind_msb: + return evaluate_ufind_msb(num_components, bit_width, src); + case nir_op_uge: + return evaluate_uge(num_components, bit_width, src); + case nir_op_uge32: + return evaluate_uge32(num_components, bit_width, src); + case nir_op_ult: + return evaluate_ult(num_components, bit_width, src); + case nir_op_ult32: + return evaluate_ult32(num_components, bit_width, src); + case nir_op_umax: + return evaluate_umax(num_components, bit_width, src); + case nir_op_umax3: + return evaluate_umax3(num_components, bit_width, src); + case nir_op_umax_4x8: + return evaluate_umax_4x8(num_components, bit_width, src); + case nir_op_umed3: + return evaluate_umed3(num_components, bit_width, src); + case nir_op_umin: + return evaluate_umin(num_components, bit_width, src); + case nir_op_umin3: + return evaluate_umin3(num_components, bit_width, src); + case nir_op_umin_4x8: + return evaluate_umin_4x8(num_components, bit_width, src); + case nir_op_umod: + return evaluate_umod(num_components, bit_width, src); + case nir_op_umul_high: + return evaluate_umul_high(num_components, bit_width, src); + case nir_op_umul_unorm_4x8: + return evaluate_umul_unorm_4x8(num_components, bit_width, src); + case nir_op_unpack_32_2x16: + return evaluate_unpack_32_2x16(num_components, bit_width, src); + case nir_op_unpack_32_2x16_split_x: + return evaluate_unpack_32_2x16_split_x(num_components, bit_width, src); + case nir_op_unpack_32_2x16_split_y: + return evaluate_unpack_32_2x16_split_y(num_components, bit_width, src); + case nir_op_unpack_64_2x32: + return evaluate_unpack_64_2x32(num_components, bit_width, src); + case nir_op_unpack_64_2x32_split_x: + return evaluate_unpack_64_2x32_split_x(num_components, bit_width, src); + case nir_op_unpack_64_2x32_split_y: + return evaluate_unpack_64_2x32_split_y(num_components, bit_width, src); + case nir_op_unpack_64_4x16: + return evaluate_unpack_64_4x16(num_components, bit_width, src); + case nir_op_unpack_half_2x16: + return evaluate_unpack_half_2x16(num_components, bit_width, src); + case nir_op_unpack_half_2x16_split_x: + return evaluate_unpack_half_2x16_split_x(num_components, bit_width, src); + case nir_op_unpack_half_2x16_split_y: + return evaluate_unpack_half_2x16_split_y(num_components, bit_width, src); + case nir_op_unpack_snorm_2x16: + return evaluate_unpack_snorm_2x16(num_components, bit_width, src); + case nir_op_unpack_snorm_4x8: + return evaluate_unpack_snorm_4x8(num_components, bit_width, src); + case nir_op_unpack_unorm_2x16: + return evaluate_unpack_unorm_2x16(num_components, bit_width, src); + case nir_op_unpack_unorm_4x8: + return evaluate_unpack_unorm_4x8(num_components, bit_width, src); + case nir_op_usadd_4x8: + return evaluate_usadd_4x8(num_components, bit_width, src); + case nir_op_ushr: + return evaluate_ushr(num_components, bit_width, src); + case nir_op_ussub_4x8: + return evaluate_ussub_4x8(num_components, bit_width, src); + case nir_op_usub_borrow: + return evaluate_usub_borrow(num_components, bit_width, src); + case nir_op_vec2: + return evaluate_vec2(num_components, bit_width, src); + case nir_op_vec3: + return evaluate_vec3(num_components, bit_width, src); + case nir_op_vec4: + return evaluate_vec4(num_components, bit_width, src); + default: + unreachable("shouldn't get here"); + } +} diff --git a/prebuilt-intermediates/nir/nir_intrinsics.c b/prebuilt-intermediates/nir/nir_intrinsics.c new file mode 100644 index 00000000000..6464c071b6d --- /dev/null +++ b/prebuilt-intermediates/nir/nir_intrinsics.c @@ -0,0 +1,2998 @@ +/* Copyright (C) 2018 Red Hat + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#include "nir.h" + +const nir_intrinsic_info nir_intrinsic_infos[nir_num_intrinsics] = { +{ + .name = "atomic_counter_add", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "atomic_counter_add_deref", + .num_srcs = 2, + .src_components = { + -1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "atomic_counter_and", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "atomic_counter_and_deref", + .num_srcs = 2, + .src_components = { + -1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "atomic_counter_comp_swap", + .num_srcs = 3, + .src_components = { + 1, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "atomic_counter_comp_swap_deref", + .num_srcs = 3, + .src_components = { + -1, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "atomic_counter_exchange", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "atomic_counter_exchange_deref", + .num_srcs = 2, + .src_components = { + -1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "atomic_counter_inc", + .num_srcs = 1, + .src_components = { + 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "atomic_counter_inc_deref", + .num_srcs = 1, + .src_components = { + -1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "atomic_counter_max", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "atomic_counter_max_deref", + .num_srcs = 2, + .src_components = { + -1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "atomic_counter_min", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "atomic_counter_min_deref", + .num_srcs = 2, + .src_components = { + -1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "atomic_counter_or", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "atomic_counter_or_deref", + .num_srcs = 2, + .src_components = { + -1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "atomic_counter_post_dec", + .num_srcs = 1, + .src_components = { + 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "atomic_counter_post_dec_deref", + .num_srcs = 1, + .src_components = { + -1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "atomic_counter_pre_dec", + .num_srcs = 1, + .src_components = { + 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "atomic_counter_pre_dec_deref", + .num_srcs = 1, + .src_components = { + -1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "atomic_counter_read", + .num_srcs = 1, + .src_components = { + 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "atomic_counter_read_deref", + .num_srcs = 1, + .src_components = { + -1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "atomic_counter_xor", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "atomic_counter_xor_deref", + .num_srcs = 2, + .src_components = { + -1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "ballot", + .num_srcs = 1, + .src_components = { + 1 + }, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "ballot_bit_count_exclusive", + .num_srcs = 1, + .src_components = { + 4 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "ballot_bit_count_inclusive", + .num_srcs = 1, + .src_components = { + 4 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "ballot_bit_count_reduce", + .num_srcs = 1, + .src_components = { + 4 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "ballot_bitfield_extract", + .num_srcs = 2, + .src_components = { + 4, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "ballot_find_lsb", + .num_srcs = 1, + .src_components = { + 4 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "ballot_find_msb", + .num_srcs = 1, + .src_components = { + 4 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "barrier", + .num_srcs = 0, + .has_dest = false, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "begin_invocation_interlock", + .num_srcs = 0, + .has_dest = false, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "copy_deref", + .num_srcs = 2, + .src_components = { + -1, -1 + }, + .has_dest = false, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "deref_atomic_add", + .num_srcs = 2, + .src_components = { + -1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "deref_atomic_and", + .num_srcs = 2, + .src_components = { + -1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "deref_atomic_comp_swap", + .num_srcs = 3, + .src_components = { + -1, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "deref_atomic_exchange", + .num_srcs = 2, + .src_components = { + -1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "deref_atomic_fadd", + .num_srcs = 2, + .src_components = { + -1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "deref_atomic_fcomp_swap", + .num_srcs = 3, + .src_components = { + -1, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "deref_atomic_fmax", + .num_srcs = 2, + .src_components = { + -1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "deref_atomic_fmin", + .num_srcs = 2, + .src_components = { + -1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "deref_atomic_imax", + .num_srcs = 2, + .src_components = { + -1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "deref_atomic_imin", + .num_srcs = 2, + .src_components = { + -1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "deref_atomic_or", + .num_srcs = 2, + .src_components = { + -1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "deref_atomic_umax", + .num_srcs = 2, + .src_components = { + -1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "deref_atomic_umin", + .num_srcs = 2, + .src_components = { + -1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "deref_atomic_xor", + .num_srcs = 2, + .src_components = { + -1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "discard", + .num_srcs = 0, + .has_dest = false, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "discard_if", + .num_srcs = 1, + .src_components = { + 1 + }, + .has_dest = false, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "elect", + .num_srcs = 0, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "emit_vertex", + .num_srcs = 0, + .has_dest = false, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_STREAM_ID] = 1, + }, + .flags = 0, +}, +{ + .name = "emit_vertex_with_counter", + .num_srcs = 1, + .src_components = { + 1 + }, + .has_dest = false, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_STREAM_ID] = 1, + }, + .flags = 0, +}, +{ + .name = "end_invocation_interlock", + .num_srcs = 0, + .has_dest = false, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "end_primitive", + .num_srcs = 0, + .has_dest = false, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_STREAM_ID] = 1, + }, + .flags = 0, +}, +{ + .name = "end_primitive_with_counter", + .num_srcs = 1, + .src_components = { + 1 + }, + .has_dest = false, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_STREAM_ID] = 1, + }, + .flags = 0, +}, +{ + .name = "exclusive_scan", + .num_srcs = 1, + .src_components = { + 0 + }, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_REDUCTION_OP] = 1, + }, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "first_invocation", + .num_srcs = 0, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "get_buffer_size", + .num_srcs = 1, + .src_components = { + 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "global_atomic_add", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "global_atomic_and", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "global_atomic_comp_swap", + .num_srcs = 3, + .src_components = { + 1, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "global_atomic_exchange", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "global_atomic_fadd", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "global_atomic_fcomp_swap", + .num_srcs = 3, + .src_components = { + 1, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "global_atomic_fmax", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "global_atomic_fmin", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "global_atomic_imax", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "global_atomic_imin", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "global_atomic_or", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "global_atomic_umax", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "global_atomic_umin", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "global_atomic_xor", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "group_memory_barrier", + .num_srcs = 0, + .has_dest = false, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "image_atomic_add", + .num_srcs = 4, + .src_components = { + 1, 4, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 4, + .index_map = { + [NIR_INTRINSIC_IMAGE_DIM] = 1, + [NIR_INTRINSIC_IMAGE_ARRAY] = 2, + [NIR_INTRINSIC_FORMAT] = 3, + [NIR_INTRINSIC_ACCESS] = 4, + }, + .flags = 0, +}, +{ + .name = "image_atomic_and", + .num_srcs = 4, + .src_components = { + 1, 4, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 4, + .index_map = { + [NIR_INTRINSIC_IMAGE_DIM] = 1, + [NIR_INTRINSIC_IMAGE_ARRAY] = 2, + [NIR_INTRINSIC_FORMAT] = 3, + [NIR_INTRINSIC_ACCESS] = 4, + }, + .flags = 0, +}, +{ + .name = "image_atomic_comp_swap", + .num_srcs = 5, + .src_components = { + 1, 4, 1, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 4, + .index_map = { + [NIR_INTRINSIC_IMAGE_DIM] = 1, + [NIR_INTRINSIC_IMAGE_ARRAY] = 2, + [NIR_INTRINSIC_FORMAT] = 3, + [NIR_INTRINSIC_ACCESS] = 4, + }, + .flags = 0, +}, +{ + .name = "image_atomic_exchange", + .num_srcs = 4, + .src_components = { + 1, 4, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 4, + .index_map = { + [NIR_INTRINSIC_IMAGE_DIM] = 1, + [NIR_INTRINSIC_IMAGE_ARRAY] = 2, + [NIR_INTRINSIC_FORMAT] = 3, + [NIR_INTRINSIC_ACCESS] = 4, + }, + .flags = 0, +}, +{ + .name = "image_atomic_fadd", + .num_srcs = 5, + .src_components = { + 1, 1, 4, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 4, + .index_map = { + [NIR_INTRINSIC_IMAGE_DIM] = 1, + [NIR_INTRINSIC_IMAGE_ARRAY] = 2, + [NIR_INTRINSIC_FORMAT] = 3, + [NIR_INTRINSIC_ACCESS] = 4, + }, + .flags = 0, +}, +{ + .name = "image_atomic_max", + .num_srcs = 4, + .src_components = { + 1, 4, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 4, + .index_map = { + [NIR_INTRINSIC_IMAGE_DIM] = 1, + [NIR_INTRINSIC_IMAGE_ARRAY] = 2, + [NIR_INTRINSIC_FORMAT] = 3, + [NIR_INTRINSIC_ACCESS] = 4, + }, + .flags = 0, +}, +{ + .name = "image_atomic_min", + .num_srcs = 4, + .src_components = { + 1, 4, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 4, + .index_map = { + [NIR_INTRINSIC_IMAGE_DIM] = 1, + [NIR_INTRINSIC_IMAGE_ARRAY] = 2, + [NIR_INTRINSIC_FORMAT] = 3, + [NIR_INTRINSIC_ACCESS] = 4, + }, + .flags = 0, +}, +{ + .name = "image_atomic_or", + .num_srcs = 4, + .src_components = { + 1, 4, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 4, + .index_map = { + [NIR_INTRINSIC_IMAGE_DIM] = 1, + [NIR_INTRINSIC_IMAGE_ARRAY] = 2, + [NIR_INTRINSIC_FORMAT] = 3, + [NIR_INTRINSIC_ACCESS] = 4, + }, + .flags = 0, +}, +{ + .name = "image_atomic_xor", + .num_srcs = 4, + .src_components = { + 1, 4, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 4, + .index_map = { + [NIR_INTRINSIC_IMAGE_DIM] = 1, + [NIR_INTRINSIC_IMAGE_ARRAY] = 2, + [NIR_INTRINSIC_FORMAT] = 3, + [NIR_INTRINSIC_ACCESS] = 4, + }, + .flags = 0, +}, +{ + .name = "image_deref_atomic_add", + .num_srcs = 4, + .src_components = { + 1, 4, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "image_deref_atomic_and", + .num_srcs = 4, + .src_components = { + 1, 4, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "image_deref_atomic_comp_swap", + .num_srcs = 5, + .src_components = { + 1, 4, 1, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "image_deref_atomic_exchange", + .num_srcs = 4, + .src_components = { + 1, 4, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "image_deref_atomic_fadd", + .num_srcs = 5, + .src_components = { + 1, 1, 4, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "image_deref_atomic_max", + .num_srcs = 4, + .src_components = { + 1, 4, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "image_deref_atomic_min", + .num_srcs = 4, + .src_components = { + 1, 4, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "image_deref_atomic_or", + .num_srcs = 4, + .src_components = { + 1, 4, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "image_deref_atomic_xor", + .num_srcs = 4, + .src_components = { + 1, 4, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "image_deref_load", + .num_srcs = 3, + .src_components = { + 1, 4, 1 + }, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "image_deref_load_param_intel", + .num_srcs = 1, + .src_components = { + 1 + }, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "image_deref_load_raw_intel", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "image_deref_samples", + .num_srcs = 1, + .src_components = { + 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "image_deref_size", + .num_srcs = 1, + .src_components = { + 1 + }, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "image_deref_store", + .num_srcs = 4, + .src_components = { + 1, 4, 1, 0 + }, + .has_dest = false, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "image_deref_store_raw_intel", + .num_srcs = 3, + .src_components = { + 1, 1, 0 + }, + .has_dest = false, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "image_load", + .num_srcs = 3, + .src_components = { + 1, 4, 1 + }, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 4, + .index_map = { + [NIR_INTRINSIC_IMAGE_DIM] = 1, + [NIR_INTRINSIC_IMAGE_ARRAY] = 2, + [NIR_INTRINSIC_FORMAT] = 3, + [NIR_INTRINSIC_ACCESS] = 4, + }, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "image_load_raw_intel", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 4, + .index_map = { + [NIR_INTRINSIC_IMAGE_DIM] = 1, + [NIR_INTRINSIC_IMAGE_ARRAY] = 2, + [NIR_INTRINSIC_FORMAT] = 3, + [NIR_INTRINSIC_ACCESS] = 4, + }, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "image_samples", + .num_srcs = 1, + .src_components = { + 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 4, + .index_map = { + [NIR_INTRINSIC_IMAGE_DIM] = 1, + [NIR_INTRINSIC_IMAGE_ARRAY] = 2, + [NIR_INTRINSIC_FORMAT] = 3, + [NIR_INTRINSIC_ACCESS] = 4, + }, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "image_size", + .num_srcs = 1, + .src_components = { + 1 + }, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 4, + .index_map = { + [NIR_INTRINSIC_IMAGE_DIM] = 1, + [NIR_INTRINSIC_IMAGE_ARRAY] = 2, + [NIR_INTRINSIC_FORMAT] = 3, + [NIR_INTRINSIC_ACCESS] = 4, + }, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "image_store", + .num_srcs = 4, + .src_components = { + 1, 4, 1, 0 + }, + .has_dest = false, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 4, + .index_map = { + [NIR_INTRINSIC_IMAGE_DIM] = 1, + [NIR_INTRINSIC_IMAGE_ARRAY] = 2, + [NIR_INTRINSIC_FORMAT] = 3, + [NIR_INTRINSIC_ACCESS] = 4, + }, + .flags = 0, +}, +{ + .name = "image_store_raw_intel", + .num_srcs = 3, + .src_components = { + 1, 1, 0 + }, + .has_dest = false, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 4, + .index_map = { + [NIR_INTRINSIC_IMAGE_DIM] = 1, + [NIR_INTRINSIC_IMAGE_ARRAY] = 2, + [NIR_INTRINSIC_FORMAT] = 3, + [NIR_INTRINSIC_ACCESS] = 4, + }, + .flags = 0, +}, +{ + .name = "inclusive_scan", + .num_srcs = 1, + .src_components = { + 0 + }, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_REDUCTION_OP] = 1, + }, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "interp_deref_at_centroid", + .num_srcs = 1, + .src_components = { + 1 + }, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "interp_deref_at_offset", + .num_srcs = 2, + .src_components = { + 1, 2 + }, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "interp_deref_at_sample", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_alpha_ref_float", + .num_srcs = 0, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_barycentric_at_offset", + .num_srcs = 1, + .src_components = { + 2 + }, + .has_dest = true, + .dest_components = 2, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_INTERP_MODE] = 1, + }, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_barycentric_at_sample", + .num_srcs = 1, + .src_components = { + 1 + }, + .has_dest = true, + .dest_components = 2, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_INTERP_MODE] = 1, + }, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_barycentric_centroid", + .num_srcs = 0, + .has_dest = true, + .dest_components = 2, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_INTERP_MODE] = 1, + }, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_barycentric_pixel", + .num_srcs = 0, + .has_dest = true, + .dest_components = 2, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_INTERP_MODE] = 1, + }, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_barycentric_sample", + .num_srcs = 0, + .has_dest = true, + .dest_components = 2, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_INTERP_MODE] = 1, + }, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_base_instance", + .num_srcs = 0, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_base_vertex", + .num_srcs = 0, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_blend_const_color_a_float", + .num_srcs = 0, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_blend_const_color_aaaa8888_unorm", + .num_srcs = 0, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_blend_const_color_b_float", + .num_srcs = 0, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_blend_const_color_g_float", + .num_srcs = 0, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_blend_const_color_r_float", + .num_srcs = 0, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_blend_const_color_rgba8888_unorm", + .num_srcs = 0, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_constant", + .num_srcs = 1, + .src_components = { + 1 + }, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 2, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + [NIR_INTRINSIC_RANGE] = 2, + }, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_deref", + .num_srcs = 1, + .src_components = { + -1 + }, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_ACCESS] = 1, + }, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "load_draw_id", + .num_srcs = 0, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_first_vertex", + .num_srcs = 0, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_frag_coord", + .num_srcs = 0, + .has_dest = true, + .dest_components = 4, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_front_face", + .num_srcs = 0, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x21, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_global", + .num_srcs = 1, + .src_components = { + 1 + }, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 3, + .index_map = { + [NIR_INTRINSIC_ACCESS] = 1, + [NIR_INTRINSIC_ALIGN_MUL] = 2, + [NIR_INTRINSIC_ALIGN_OFFSET] = 3, + }, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "load_global_invocation_id", + .num_srcs = 0, + .has_dest = true, + .dest_components = 3, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_helper_invocation", + .num_srcs = 0, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x21, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_input", + .num_srcs = 1, + .src_components = { + 1 + }, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 2, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + [NIR_INTRINSIC_COMPONENT] = 2, + }, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_instance_id", + .num_srcs = 0, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_interpolated_input", + .num_srcs = 2, + .src_components = { + 2, 1 + }, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 2, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + [NIR_INTRINSIC_COMPONENT] = 2, + }, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_invocation_id", + .num_srcs = 0, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_is_indexed_draw", + .num_srcs = 0, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_layer_id", + .num_srcs = 0, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_local_group_size", + .num_srcs = 0, + .has_dest = true, + .dest_components = 3, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_local_invocation_id", + .num_srcs = 0, + .has_dest = true, + .dest_components = 3, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_local_invocation_index", + .num_srcs = 0, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_num_subgroups", + .num_srcs = 0, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_num_work_groups", + .num_srcs = 0, + .has_dest = true, + .dest_components = 3, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_output", + .num_srcs = 1, + .src_components = { + 1 + }, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 2, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + [NIR_INTRINSIC_COMPONENT] = 2, + }, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "load_param", + .num_srcs = 0, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_PARAM_IDX] = 1, + }, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "load_patch_vertices_in", + .num_srcs = 0, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_per_vertex_input", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 2, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + [NIR_INTRINSIC_COMPONENT] = 2, + }, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_per_vertex_output", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 2, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + [NIR_INTRINSIC_COMPONENT] = 2, + }, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "load_primitive_id", + .num_srcs = 0, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_push_constant", + .num_srcs = 1, + .src_components = { + 1 + }, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 2, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + [NIR_INTRINSIC_RANGE] = 2, + }, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_sample_id", + .num_srcs = 0, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_sample_id_no_per_sample", + .num_srcs = 0, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_sample_mask_in", + .num_srcs = 0, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_sample_pos", + .num_srcs = 0, + .has_dest = true, + .dest_components = 2, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_shared", + .num_srcs = 1, + .src_components = { + 1 + }, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 3, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + [NIR_INTRINSIC_ALIGN_MUL] = 2, + [NIR_INTRINSIC_ALIGN_OFFSET] = 3, + }, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "load_ssbo", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 3, + .index_map = { + [NIR_INTRINSIC_ACCESS] = 1, + [NIR_INTRINSIC_ALIGN_MUL] = 2, + [NIR_INTRINSIC_ALIGN_OFFSET] = 3, + }, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "load_subgroup_eq_mask", + .num_srcs = 0, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x60, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_subgroup_ge_mask", + .num_srcs = 0, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x60, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_subgroup_gt_mask", + .num_srcs = 0, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x60, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_subgroup_id", + .num_srcs = 0, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_subgroup_invocation", + .num_srcs = 0, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_subgroup_le_mask", + .num_srcs = 0, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x60, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_subgroup_lt_mask", + .num_srcs = 0, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x60, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_subgroup_size", + .num_srcs = 0, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_tess_coord", + .num_srcs = 0, + .has_dest = true, + .dest_components = 3, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_tess_level_inner", + .num_srcs = 0, + .has_dest = true, + .dest_components = 2, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_tess_level_outer", + .num_srcs = 0, + .has_dest = true, + .dest_components = 4, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_ubo", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 2, + .index_map = { + [NIR_INTRINSIC_ALIGN_MUL] = 1, + [NIR_INTRINSIC_ALIGN_OFFSET] = 2, + }, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_uniform", + .num_srcs = 1, + .src_components = { + 1 + }, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 2, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + [NIR_INTRINSIC_RANGE] = 2, + }, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_user_clip_plane", + .num_srcs = 0, + .has_dest = true, + .dest_components = 4, + .dest_bit_sizes = 0x20, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_UCP_ID] = 1, + }, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_vertex_id", + .num_srcs = 0, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_vertex_id_zero_base", + .num_srcs = 0, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_view_index", + .num_srcs = 0, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_vulkan_descriptor", + .num_srcs = 1, + .src_components = { + 1 + }, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_DESC_TYPE] = 1, + }, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_work_dim", + .num_srcs = 0, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "load_work_group_id", + .num_srcs = 0, + .has_dest = true, + .dest_components = 3, + .dest_bit_sizes = 0x20, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "memory_barrier", + .num_srcs = 0, + .has_dest = false, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "memory_barrier_atomic_counter", + .num_srcs = 0, + .has_dest = false, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "memory_barrier_buffer", + .num_srcs = 0, + .has_dest = false, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "memory_barrier_image", + .num_srcs = 0, + .has_dest = false, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "memory_barrier_shared", + .num_srcs = 0, + .has_dest = false, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "nop", + .num_srcs = 0, + .has_dest = false, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "quad_broadcast", + .num_srcs = 2, + .src_components = { + 0, 1 + }, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "quad_swap_diagonal", + .num_srcs = 1, + .src_components = { + 0 + }, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "quad_swap_horizontal", + .num_srcs = 1, + .src_components = { + 0 + }, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "quad_swap_vertical", + .num_srcs = 1, + .src_components = { + 0 + }, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "read_first_invocation", + .num_srcs = 1, + .src_components = { + 0 + }, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "read_invocation", + .num_srcs = 2, + .src_components = { + 0, 1 + }, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "reduce", + .num_srcs = 1, + .src_components = { + 0 + }, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 2, + .index_map = { + [NIR_INTRINSIC_REDUCTION_OP] = 1, + [NIR_INTRINSIC_CLUSTER_SIZE] = 2, + }, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "set_vertex_count", + .num_srcs = 1, + .src_components = { + 1 + }, + .has_dest = false, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "shader_clock", + .num_srcs = 0, + .has_dest = true, + .dest_components = 2, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "shared_atomic_add", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "shared_atomic_and", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "shared_atomic_comp_swap", + .num_srcs = 3, + .src_components = { + 1, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "shared_atomic_exchange", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "shared_atomic_fadd", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "shared_atomic_fcomp_swap", + .num_srcs = 3, + .src_components = { + 1, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "shared_atomic_fmax", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "shared_atomic_fmin", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "shared_atomic_imax", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "shared_atomic_imin", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "shared_atomic_or", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "shared_atomic_umax", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "shared_atomic_umin", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "shared_atomic_xor", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + }, + .flags = 0, +}, +{ + .name = "shuffle", + .num_srcs = 2, + .src_components = { + 0, 1 + }, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "shuffle_down", + .num_srcs = 2, + .src_components = { + 0, 1 + }, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "shuffle_up", + .num_srcs = 2, + .src_components = { + 0, 1 + }, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "shuffle_xor", + .num_srcs = 2, + .src_components = { + 0, 1 + }, + .has_dest = true, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "ssbo_atomic_add", + .num_srcs = 3, + .src_components = { + 1, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "ssbo_atomic_and", + .num_srcs = 3, + .src_components = { + 1, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "ssbo_atomic_comp_swap", + .num_srcs = 4, + .src_components = { + 1, 1, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "ssbo_atomic_exchange", + .num_srcs = 3, + .src_components = { + 1, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "ssbo_atomic_fadd", + .num_srcs = 3, + .src_components = { + 1, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "ssbo_atomic_fcomp_swap", + .num_srcs = 4, + .src_components = { + 1, 1, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "ssbo_atomic_fmax", + .num_srcs = 3, + .src_components = { + 1, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "ssbo_atomic_fmin", + .num_srcs = 3, + .src_components = { + 1, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "ssbo_atomic_imax", + .num_srcs = 3, + .src_components = { + 1, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "ssbo_atomic_imin", + .num_srcs = 3, + .src_components = { + 1, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "ssbo_atomic_or", + .num_srcs = 3, + .src_components = { + 1, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "ssbo_atomic_umax", + .num_srcs = 3, + .src_components = { + 1, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "ssbo_atomic_umin", + .num_srcs = 3, + .src_components = { + 1, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "ssbo_atomic_xor", + .num_srcs = 3, + .src_components = { + 1, 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = 0, +}, +{ + .name = "store_deref", + .num_srcs = 2, + .src_components = { + -1, 0 + }, + .has_dest = false, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 2, + .index_map = { + [NIR_INTRINSIC_WRMASK] = 1, + [NIR_INTRINSIC_ACCESS] = 2, + }, + .flags = 0, +}, +{ + .name = "store_global", + .num_srcs = 2, + .src_components = { + 0, 1 + }, + .has_dest = false, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 4, + .index_map = { + [NIR_INTRINSIC_WRMASK] = 1, + [NIR_INTRINSIC_ACCESS] = 2, + [NIR_INTRINSIC_ALIGN_MUL] = 3, + [NIR_INTRINSIC_ALIGN_OFFSET] = 4, + }, + .flags = 0, +}, +{ + .name = "store_output", + .num_srcs = 2, + .src_components = { + 0, 1 + }, + .has_dest = false, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 3, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + [NIR_INTRINSIC_WRMASK] = 2, + [NIR_INTRINSIC_COMPONENT] = 3, + }, + .flags = 0, +}, +{ + .name = "store_per_vertex_output", + .num_srcs = 3, + .src_components = { + 0, 1, 1 + }, + .has_dest = false, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 3, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + [NIR_INTRINSIC_WRMASK] = 2, + [NIR_INTRINSIC_COMPONENT] = 3, + }, + .flags = 0, +}, +{ + .name = "store_shared", + .num_srcs = 2, + .src_components = { + 0, 1 + }, + .has_dest = false, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 4, + .index_map = { + [NIR_INTRINSIC_BASE] = 1, + [NIR_INTRINSIC_WRMASK] = 2, + [NIR_INTRINSIC_ALIGN_MUL] = 3, + [NIR_INTRINSIC_ALIGN_OFFSET] = 4, + }, + .flags = 0, +}, +{ + .name = "store_ssbo", + .num_srcs = 3, + .src_components = { + 0, 1, 1 + }, + .has_dest = false, + .dest_components = 0, + .dest_bit_sizes = 0x0, + .num_indices = 4, + .index_map = { + [NIR_INTRINSIC_WRMASK] = 1, + [NIR_INTRINSIC_ACCESS] = 2, + [NIR_INTRINSIC_ALIGN_MUL] = 3, + [NIR_INTRINSIC_ALIGN_OFFSET] = 4, + }, + .flags = 0, +}, +{ + .name = "vote_all", + .num_srcs = 1, + .src_components = { + 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "vote_any", + .num_srcs = 1, + .src_components = { + 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "vote_feq", + .num_srcs = 1, + .src_components = { + 0 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "vote_ieq", + .num_srcs = 1, + .src_components = { + 0 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 0, + .flags = NIR_INTRINSIC_CAN_ELIMINATE, +}, +{ + .name = "vulkan_resource_index", + .num_srcs = 1, + .src_components = { + 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 3, + .index_map = { + [NIR_INTRINSIC_DESC_SET] = 1, + [NIR_INTRINSIC_BINDING] = 2, + [NIR_INTRINSIC_DESC_TYPE] = 3, + }, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +{ + .name = "vulkan_resource_reindex", + .num_srcs = 2, + .src_components = { + 1, 1 + }, + .has_dest = true, + .dest_components = 1, + .dest_bit_sizes = 0x0, + .num_indices = 1, + .index_map = { + [NIR_INTRINSIC_DESC_TYPE] = 1, + }, + .flags = NIR_INTRINSIC_CAN_ELIMINATE | NIR_INTRINSIC_CAN_REORDER, +}, +}; diff --git a/prebuilt-intermediates/nir/nir_intrinsics.h b/prebuilt-intermediates/nir/nir_intrinsics.h new file mode 100644 index 00000000000..48e67cd97a9 --- /dev/null +++ b/prebuilt-intermediates/nir/nir_intrinsics.h @@ -0,0 +1,269 @@ +/* Copyright (C) 2018 Red Hat + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#ifndef _NIR_INTRINSICS_ +#define _NIR_INTRINSICS_ + + + +typedef enum { + nir_intrinsic_atomic_counter_add, + nir_intrinsic_atomic_counter_add_deref, + nir_intrinsic_atomic_counter_and, + nir_intrinsic_atomic_counter_and_deref, + nir_intrinsic_atomic_counter_comp_swap, + nir_intrinsic_atomic_counter_comp_swap_deref, + nir_intrinsic_atomic_counter_exchange, + nir_intrinsic_atomic_counter_exchange_deref, + nir_intrinsic_atomic_counter_inc, + nir_intrinsic_atomic_counter_inc_deref, + nir_intrinsic_atomic_counter_max, + nir_intrinsic_atomic_counter_max_deref, + nir_intrinsic_atomic_counter_min, + nir_intrinsic_atomic_counter_min_deref, + nir_intrinsic_atomic_counter_or, + nir_intrinsic_atomic_counter_or_deref, + nir_intrinsic_atomic_counter_post_dec, + nir_intrinsic_atomic_counter_post_dec_deref, + nir_intrinsic_atomic_counter_pre_dec, + nir_intrinsic_atomic_counter_pre_dec_deref, + nir_intrinsic_atomic_counter_read, + nir_intrinsic_atomic_counter_read_deref, + nir_intrinsic_atomic_counter_xor, + nir_intrinsic_atomic_counter_xor_deref, + nir_intrinsic_ballot, + nir_intrinsic_ballot_bit_count_exclusive, + nir_intrinsic_ballot_bit_count_inclusive, + nir_intrinsic_ballot_bit_count_reduce, + nir_intrinsic_ballot_bitfield_extract, + nir_intrinsic_ballot_find_lsb, + nir_intrinsic_ballot_find_msb, + nir_intrinsic_barrier, + nir_intrinsic_begin_invocation_interlock, + nir_intrinsic_copy_deref, + nir_intrinsic_deref_atomic_add, + nir_intrinsic_deref_atomic_and, + nir_intrinsic_deref_atomic_comp_swap, + nir_intrinsic_deref_atomic_exchange, + nir_intrinsic_deref_atomic_fadd, + nir_intrinsic_deref_atomic_fcomp_swap, + nir_intrinsic_deref_atomic_fmax, + nir_intrinsic_deref_atomic_fmin, + nir_intrinsic_deref_atomic_imax, + nir_intrinsic_deref_atomic_imin, + nir_intrinsic_deref_atomic_or, + nir_intrinsic_deref_atomic_umax, + nir_intrinsic_deref_atomic_umin, + nir_intrinsic_deref_atomic_xor, + nir_intrinsic_discard, + nir_intrinsic_discard_if, + nir_intrinsic_elect, + nir_intrinsic_emit_vertex, + nir_intrinsic_emit_vertex_with_counter, + nir_intrinsic_end_invocation_interlock, + nir_intrinsic_end_primitive, + nir_intrinsic_end_primitive_with_counter, + nir_intrinsic_exclusive_scan, + nir_intrinsic_first_invocation, + nir_intrinsic_get_buffer_size, + nir_intrinsic_global_atomic_add, + nir_intrinsic_global_atomic_and, + nir_intrinsic_global_atomic_comp_swap, + nir_intrinsic_global_atomic_exchange, + nir_intrinsic_global_atomic_fadd, + nir_intrinsic_global_atomic_fcomp_swap, + nir_intrinsic_global_atomic_fmax, + nir_intrinsic_global_atomic_fmin, + nir_intrinsic_global_atomic_imax, + nir_intrinsic_global_atomic_imin, + nir_intrinsic_global_atomic_or, + nir_intrinsic_global_atomic_umax, + nir_intrinsic_global_atomic_umin, + nir_intrinsic_global_atomic_xor, + nir_intrinsic_group_memory_barrier, + nir_intrinsic_image_atomic_add, + nir_intrinsic_image_atomic_and, + nir_intrinsic_image_atomic_comp_swap, + nir_intrinsic_image_atomic_exchange, + nir_intrinsic_image_atomic_fadd, + nir_intrinsic_image_atomic_max, + nir_intrinsic_image_atomic_min, + nir_intrinsic_image_atomic_or, + nir_intrinsic_image_atomic_xor, + nir_intrinsic_image_deref_atomic_add, + nir_intrinsic_image_deref_atomic_and, + nir_intrinsic_image_deref_atomic_comp_swap, + nir_intrinsic_image_deref_atomic_exchange, + nir_intrinsic_image_deref_atomic_fadd, + nir_intrinsic_image_deref_atomic_max, + nir_intrinsic_image_deref_atomic_min, + nir_intrinsic_image_deref_atomic_or, + nir_intrinsic_image_deref_atomic_xor, + nir_intrinsic_image_deref_load, + nir_intrinsic_image_deref_load_param_intel, + nir_intrinsic_image_deref_load_raw_intel, + nir_intrinsic_image_deref_samples, + nir_intrinsic_image_deref_size, + nir_intrinsic_image_deref_store, + nir_intrinsic_image_deref_store_raw_intel, + nir_intrinsic_image_load, + nir_intrinsic_image_load_raw_intel, + nir_intrinsic_image_samples, + nir_intrinsic_image_size, + nir_intrinsic_image_store, + nir_intrinsic_image_store_raw_intel, + nir_intrinsic_inclusive_scan, + nir_intrinsic_interp_deref_at_centroid, + nir_intrinsic_interp_deref_at_offset, + nir_intrinsic_interp_deref_at_sample, + nir_intrinsic_load_alpha_ref_float, + nir_intrinsic_load_barycentric_at_offset, + nir_intrinsic_load_barycentric_at_sample, + nir_intrinsic_load_barycentric_centroid, + nir_intrinsic_load_barycentric_pixel, + nir_intrinsic_load_barycentric_sample, + nir_intrinsic_load_base_instance, + nir_intrinsic_load_base_vertex, + nir_intrinsic_load_blend_const_color_a_float, + nir_intrinsic_load_blend_const_color_aaaa8888_unorm, + nir_intrinsic_load_blend_const_color_b_float, + nir_intrinsic_load_blend_const_color_g_float, + nir_intrinsic_load_blend_const_color_r_float, + nir_intrinsic_load_blend_const_color_rgba8888_unorm, + nir_intrinsic_load_constant, + nir_intrinsic_load_deref, + nir_intrinsic_load_draw_id, + nir_intrinsic_load_first_vertex, + nir_intrinsic_load_frag_coord, + nir_intrinsic_load_front_face, + nir_intrinsic_load_global, + nir_intrinsic_load_global_invocation_id, + nir_intrinsic_load_helper_invocation, + nir_intrinsic_load_input, + nir_intrinsic_load_instance_id, + nir_intrinsic_load_interpolated_input, + nir_intrinsic_load_invocation_id, + nir_intrinsic_load_is_indexed_draw, + nir_intrinsic_load_layer_id, + nir_intrinsic_load_local_group_size, + nir_intrinsic_load_local_invocation_id, + nir_intrinsic_load_local_invocation_index, + nir_intrinsic_load_num_subgroups, + nir_intrinsic_load_num_work_groups, + nir_intrinsic_load_output, + nir_intrinsic_load_param, + nir_intrinsic_load_patch_vertices_in, + nir_intrinsic_load_per_vertex_input, + nir_intrinsic_load_per_vertex_output, + nir_intrinsic_load_primitive_id, + nir_intrinsic_load_push_constant, + nir_intrinsic_load_sample_id, + nir_intrinsic_load_sample_id_no_per_sample, + nir_intrinsic_load_sample_mask_in, + nir_intrinsic_load_sample_pos, + nir_intrinsic_load_shared, + nir_intrinsic_load_ssbo, + nir_intrinsic_load_subgroup_eq_mask, + nir_intrinsic_load_subgroup_ge_mask, + nir_intrinsic_load_subgroup_gt_mask, + nir_intrinsic_load_subgroup_id, + nir_intrinsic_load_subgroup_invocation, + nir_intrinsic_load_subgroup_le_mask, + nir_intrinsic_load_subgroup_lt_mask, + nir_intrinsic_load_subgroup_size, + nir_intrinsic_load_tess_coord, + nir_intrinsic_load_tess_level_inner, + nir_intrinsic_load_tess_level_outer, + nir_intrinsic_load_ubo, + nir_intrinsic_load_uniform, + nir_intrinsic_load_user_clip_plane, + nir_intrinsic_load_vertex_id, + nir_intrinsic_load_vertex_id_zero_base, + nir_intrinsic_load_view_index, + nir_intrinsic_load_vulkan_descriptor, + nir_intrinsic_load_work_dim, + nir_intrinsic_load_work_group_id, + nir_intrinsic_memory_barrier, + nir_intrinsic_memory_barrier_atomic_counter, + nir_intrinsic_memory_barrier_buffer, + nir_intrinsic_memory_barrier_image, + nir_intrinsic_memory_barrier_shared, + nir_intrinsic_nop, + nir_intrinsic_quad_broadcast, + nir_intrinsic_quad_swap_diagonal, + nir_intrinsic_quad_swap_horizontal, + nir_intrinsic_quad_swap_vertical, + nir_intrinsic_read_first_invocation, + nir_intrinsic_read_invocation, + nir_intrinsic_reduce, + nir_intrinsic_set_vertex_count, + nir_intrinsic_shader_clock, + nir_intrinsic_shared_atomic_add, + nir_intrinsic_shared_atomic_and, + nir_intrinsic_shared_atomic_comp_swap, + nir_intrinsic_shared_atomic_exchange, + nir_intrinsic_shared_atomic_fadd, + nir_intrinsic_shared_atomic_fcomp_swap, + nir_intrinsic_shared_atomic_fmax, + nir_intrinsic_shared_atomic_fmin, + nir_intrinsic_shared_atomic_imax, + nir_intrinsic_shared_atomic_imin, + nir_intrinsic_shared_atomic_or, + nir_intrinsic_shared_atomic_umax, + nir_intrinsic_shared_atomic_umin, + nir_intrinsic_shared_atomic_xor, + nir_intrinsic_shuffle, + nir_intrinsic_shuffle_down, + nir_intrinsic_shuffle_up, + nir_intrinsic_shuffle_xor, + nir_intrinsic_ssbo_atomic_add, + nir_intrinsic_ssbo_atomic_and, + nir_intrinsic_ssbo_atomic_comp_swap, + nir_intrinsic_ssbo_atomic_exchange, + nir_intrinsic_ssbo_atomic_fadd, + nir_intrinsic_ssbo_atomic_fcomp_swap, + nir_intrinsic_ssbo_atomic_fmax, + nir_intrinsic_ssbo_atomic_fmin, + nir_intrinsic_ssbo_atomic_imax, + nir_intrinsic_ssbo_atomic_imin, + nir_intrinsic_ssbo_atomic_or, + nir_intrinsic_ssbo_atomic_umax, + nir_intrinsic_ssbo_atomic_umin, + nir_intrinsic_ssbo_atomic_xor, + nir_intrinsic_store_deref, + nir_intrinsic_store_global, + nir_intrinsic_store_output, + nir_intrinsic_store_per_vertex_output, + nir_intrinsic_store_shared, + nir_intrinsic_store_ssbo, + nir_intrinsic_vote_all, + nir_intrinsic_vote_any, + nir_intrinsic_vote_feq, + nir_intrinsic_vote_ieq, + nir_intrinsic_vulkan_resource_index, + nir_intrinsic_vulkan_resource_reindex, + + nir_last_intrinsic = nir_intrinsic_vulkan_resource_reindex, + nir_num_intrinsics = nir_last_intrinsic + 1 +} nir_intrinsic_op; + +#endif /* _NIR_INTRINSICS_ */ \ No newline at end of file diff --git a/prebuilt-intermediates/nir/nir_opcodes.c b/prebuilt-intermediates/nir/nir_opcodes.c new file mode 100644 index 00000000000..b79faa46aa3 --- /dev/null +++ b/prebuilt-intermediates/nir/nir_opcodes.c @@ -0,0 +1,3862 @@ + +#include "nir.h" + +nir_op +nir_type_conversion_op(nir_alu_type src, nir_alu_type dst, nir_rounding_mode rnd) +{ + nir_alu_type src_base = (nir_alu_type) nir_alu_type_get_base_type(src); + nir_alu_type dst_base = (nir_alu_type) nir_alu_type_get_base_type(dst); + unsigned src_bit_size = nir_alu_type_get_type_size(src); + unsigned dst_bit_size = nir_alu_type_get_type_size(dst); + + if (src == dst && src_base == nir_type_float) { + return nir_op_fmov; + } else if (src == dst && src_base == nir_type_bool) { + return nir_op_imov; + } else if ((src_base == nir_type_int || src_base == nir_type_uint) && + (dst_base == nir_type_int || dst_base == nir_type_uint) && + src_bit_size == dst_bit_size) { + /* Integer <-> integer conversions with the same bit-size on both + * ends are just no-op moves. + */ + return nir_op_imov; + } + + switch (src_base) { + case nir_type_int: + switch (dst_base) { + case nir_type_int: + case nir_type_uint: + + switch (dst_bit_size) { + case 1: + assert(rnd == nir_rounding_mode_undef); + return nir_op_i2i1; + case 8: + assert(rnd == nir_rounding_mode_undef); + return nir_op_i2i8; + case 16: + assert(rnd == nir_rounding_mode_undef); + return nir_op_i2i16; + case 32: + assert(rnd == nir_rounding_mode_undef); + return nir_op_i2i32; + case 64: + assert(rnd == nir_rounding_mode_undef); + return nir_op_i2i64; + default: + unreachable("Invalid nir alu bit size"); + } + case nir_type_float: + switch (dst_bit_size) { + case 16: + assert(rnd == nir_rounding_mode_undef); + return nir_op_i2f16; + case 32: + assert(rnd == nir_rounding_mode_undef); + return nir_op_i2f32; + case 64: + assert(rnd == nir_rounding_mode_undef); + return nir_op_i2f64; + default: + unreachable("Invalid nir alu bit size"); + } + case nir_type_bool: + switch (dst_bit_size) { + case 1: + assert(rnd == nir_rounding_mode_undef); + return nir_op_i2b1; + case 32: + assert(rnd == nir_rounding_mode_undef); + return nir_op_i2b32; + default: + unreachable("Invalid nir alu bit size"); + } + default: + unreachable("Invalid nir alu base type"); + } + case nir_type_uint: + switch (dst_base) { + case nir_type_int: + case nir_type_uint: + + switch (dst_bit_size) { + case 1: + assert(rnd == nir_rounding_mode_undef); + return nir_op_u2u1; + case 8: + assert(rnd == nir_rounding_mode_undef); + return nir_op_u2u8; + case 16: + assert(rnd == nir_rounding_mode_undef); + return nir_op_u2u16; + case 32: + assert(rnd == nir_rounding_mode_undef); + return nir_op_u2u32; + case 64: + assert(rnd == nir_rounding_mode_undef); + return nir_op_u2u64; + default: + unreachable("Invalid nir alu bit size"); + } + case nir_type_float: + switch (dst_bit_size) { + case 16: + assert(rnd == nir_rounding_mode_undef); + return nir_op_u2f16; + case 32: + assert(rnd == nir_rounding_mode_undef); + return nir_op_u2f32; + case 64: + assert(rnd == nir_rounding_mode_undef); + return nir_op_u2f64; + default: + unreachable("Invalid nir alu bit size"); + } + case nir_type_bool: + + switch (dst_bit_size) { + case 1: + assert(rnd == nir_rounding_mode_undef); + return nir_op_i2b1; + case 32: + assert(rnd == nir_rounding_mode_undef); + return nir_op_i2b32; + default: + unreachable("Invalid nir alu bit size"); + } + default: + unreachable("Invalid nir alu base type"); + } + case nir_type_float: + switch (dst_base) { + case nir_type_int: + switch (dst_bit_size) { + case 1: + assert(rnd == nir_rounding_mode_undef); + return nir_op_f2i1; + case 8: + assert(rnd == nir_rounding_mode_undef); + return nir_op_f2i8; + case 16: + assert(rnd == nir_rounding_mode_undef); + return nir_op_f2i16; + case 32: + assert(rnd == nir_rounding_mode_undef); + return nir_op_f2i32; + case 64: + assert(rnd == nir_rounding_mode_undef); + return nir_op_f2i64; + default: + unreachable("Invalid nir alu bit size"); + } + case nir_type_uint: + switch (dst_bit_size) { + case 1: + assert(rnd == nir_rounding_mode_undef); + return nir_op_f2u1; + case 8: + assert(rnd == nir_rounding_mode_undef); + return nir_op_f2u8; + case 16: + assert(rnd == nir_rounding_mode_undef); + return nir_op_f2u16; + case 32: + assert(rnd == nir_rounding_mode_undef); + return nir_op_f2u32; + case 64: + assert(rnd == nir_rounding_mode_undef); + return nir_op_f2u64; + default: + unreachable("Invalid nir alu bit size"); + } + case nir_type_float: + switch (dst_bit_size) { + case 16: + switch(rnd) { + case nir_rounding_mode_rtne: + return nir_op_f2f16_rtne; + case nir_rounding_mode_rtz: + return nir_op_f2f16_rtz; + case nir_rounding_mode_undef: + return nir_op_f2f16; + default: + unreachable("Invalid 16-bit nir rounding mode"); + } + case 32: + assert(rnd == nir_rounding_mode_undef); + return nir_op_f2f32; + case 64: + assert(rnd == nir_rounding_mode_undef); + return nir_op_f2f64; + default: + unreachable("Invalid nir alu bit size"); + } + case nir_type_bool: + switch (dst_bit_size) { + case 1: + assert(rnd == nir_rounding_mode_undef); + return nir_op_f2b1; + case 32: + assert(rnd == nir_rounding_mode_undef); + return nir_op_f2b32; + default: + unreachable("Invalid nir alu bit size"); + } + default: + unreachable("Invalid nir alu base type"); + } + case nir_type_bool: + switch (dst_base) { + case nir_type_int: + case nir_type_uint: + + switch (dst_bit_size) { + case 1: + assert(rnd == nir_rounding_mode_undef); + return nir_op_b2i1; + case 8: + assert(rnd == nir_rounding_mode_undef); + return nir_op_b2i8; + case 16: + assert(rnd == nir_rounding_mode_undef); + return nir_op_b2i16; + case 32: + assert(rnd == nir_rounding_mode_undef); + return nir_op_b2i32; + case 64: + assert(rnd == nir_rounding_mode_undef); + return nir_op_b2i64; + default: + unreachable("Invalid nir alu bit size"); + } + case nir_type_float: + switch (dst_bit_size) { + case 16: + assert(rnd == nir_rounding_mode_undef); + return nir_op_b2f16; + case 32: + assert(rnd == nir_rounding_mode_undef); + return nir_op_b2f32; + case 64: + assert(rnd == nir_rounding_mode_undef); + return nir_op_b2f64; + default: + unreachable("Invalid nir alu bit size"); + } + case nir_type_bool: + + switch (dst_bit_size) { + case 1: + assert(rnd == nir_rounding_mode_undef); + return nir_op_b2i1; + case 8: + assert(rnd == nir_rounding_mode_undef); + return nir_op_b2i8; + case 16: + assert(rnd == nir_rounding_mode_undef); + return nir_op_b2i16; + case 32: + assert(rnd == nir_rounding_mode_undef); + return nir_op_b2i32; + case 64: + assert(rnd == nir_rounding_mode_undef); + return nir_op_b2i64; + default: + unreachable("Invalid nir alu bit size"); + } + default: + unreachable("Invalid nir alu base type"); + } + default: + unreachable("Invalid nir alu base type"); + } +} + +const nir_op_info nir_op_infos[nir_num_opcodes] = { +{ + .name = "b2f16", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float16, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_bool + }, + .algebraic_properties = + 0 +}, +{ + .name = "b2f32", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float32, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_bool + }, + .algebraic_properties = + 0 +}, +{ + .name = "b2f64", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float64, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_bool + }, + .algebraic_properties = + 0 +}, +{ + .name = "b2i1", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_int1, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_bool + }, + .algebraic_properties = + 0 +}, +{ + .name = "b2i16", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_int16, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_bool + }, + .algebraic_properties = + 0 +}, +{ + .name = "b2i32", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_int32, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_bool + }, + .algebraic_properties = + 0 +}, +{ + .name = "b2i64", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_int64, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_bool + }, + .algebraic_properties = + 0 +}, +{ + .name = "b2i8", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_int8, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_bool + }, + .algebraic_properties = + 0 +}, +{ + .name = "b32all_fequal2", + .num_inputs = 2, + .output_size = 1, + .output_type = nir_type_bool32, + .input_sizes = { + 2, 2 + }, + .input_types = { + nir_type_float, nir_type_float + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "b32all_fequal3", + .num_inputs = 2, + .output_size = 1, + .output_type = nir_type_bool32, + .input_sizes = { + 3, 3 + }, + .input_types = { + nir_type_float, nir_type_float + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "b32all_fequal4", + .num_inputs = 2, + .output_size = 1, + .output_type = nir_type_bool32, + .input_sizes = { + 4, 4 + }, + .input_types = { + nir_type_float, nir_type_float + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "b32all_iequal2", + .num_inputs = 2, + .output_size = 1, + .output_type = nir_type_bool32, + .input_sizes = { + 2, 2 + }, + .input_types = { + nir_type_int, nir_type_int + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "b32all_iequal3", + .num_inputs = 2, + .output_size = 1, + .output_type = nir_type_bool32, + .input_sizes = { + 3, 3 + }, + .input_types = { + nir_type_int, nir_type_int + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "b32all_iequal4", + .num_inputs = 2, + .output_size = 1, + .output_type = nir_type_bool32, + .input_sizes = { + 4, 4 + }, + .input_types = { + nir_type_int, nir_type_int + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "b32any_fnequal2", + .num_inputs = 2, + .output_size = 1, + .output_type = nir_type_bool32, + .input_sizes = { + 2, 2 + }, + .input_types = { + nir_type_float, nir_type_float + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "b32any_fnequal3", + .num_inputs = 2, + .output_size = 1, + .output_type = nir_type_bool32, + .input_sizes = { + 3, 3 + }, + .input_types = { + nir_type_float, nir_type_float + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "b32any_fnequal4", + .num_inputs = 2, + .output_size = 1, + .output_type = nir_type_bool32, + .input_sizes = { + 4, 4 + }, + .input_types = { + nir_type_float, nir_type_float + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "b32any_inequal2", + .num_inputs = 2, + .output_size = 1, + .output_type = nir_type_bool32, + .input_sizes = { + 2, 2 + }, + .input_types = { + nir_type_int, nir_type_int + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "b32any_inequal3", + .num_inputs = 2, + .output_size = 1, + .output_type = nir_type_bool32, + .input_sizes = { + 3, 3 + }, + .input_types = { + nir_type_int, nir_type_int + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "b32any_inequal4", + .num_inputs = 2, + .output_size = 1, + .output_type = nir_type_bool32, + .input_sizes = { + 4, 4 + }, + .input_types = { + nir_type_int, nir_type_int + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "b32csel", + .num_inputs = 3, + .output_size = 0, + .output_type = nir_type_uint, + .input_sizes = { + 0, 0, 0 + }, + .input_types = { + nir_type_bool32, nir_type_uint, nir_type_uint + }, + .algebraic_properties = + 0 +}, +{ + .name = "ball_fequal2", + .num_inputs = 2, + .output_size = 1, + .output_type = nir_type_bool1, + .input_sizes = { + 2, 2 + }, + .input_types = { + nir_type_float, nir_type_float + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "ball_fequal3", + .num_inputs = 2, + .output_size = 1, + .output_type = nir_type_bool1, + .input_sizes = { + 3, 3 + }, + .input_types = { + nir_type_float, nir_type_float + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "ball_fequal4", + .num_inputs = 2, + .output_size = 1, + .output_type = nir_type_bool1, + .input_sizes = { + 4, 4 + }, + .input_types = { + nir_type_float, nir_type_float + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "ball_iequal2", + .num_inputs = 2, + .output_size = 1, + .output_type = nir_type_bool1, + .input_sizes = { + 2, 2 + }, + .input_types = { + nir_type_int, nir_type_int + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "ball_iequal3", + .num_inputs = 2, + .output_size = 1, + .output_type = nir_type_bool1, + .input_sizes = { + 3, 3 + }, + .input_types = { + nir_type_int, nir_type_int + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "ball_iequal4", + .num_inputs = 2, + .output_size = 1, + .output_type = nir_type_bool1, + .input_sizes = { + 4, 4 + }, + .input_types = { + nir_type_int, nir_type_int + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "bany_fnequal2", + .num_inputs = 2, + .output_size = 1, + .output_type = nir_type_bool1, + .input_sizes = { + 2, 2 + }, + .input_types = { + nir_type_float, nir_type_float + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "bany_fnequal3", + .num_inputs = 2, + .output_size = 1, + .output_type = nir_type_bool1, + .input_sizes = { + 3, 3 + }, + .input_types = { + nir_type_float, nir_type_float + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "bany_fnequal4", + .num_inputs = 2, + .output_size = 1, + .output_type = nir_type_bool1, + .input_sizes = { + 4, 4 + }, + .input_types = { + nir_type_float, nir_type_float + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "bany_inequal2", + .num_inputs = 2, + .output_size = 1, + .output_type = nir_type_bool1, + .input_sizes = { + 2, 2 + }, + .input_types = { + nir_type_int, nir_type_int + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "bany_inequal3", + .num_inputs = 2, + .output_size = 1, + .output_type = nir_type_bool1, + .input_sizes = { + 3, 3 + }, + .input_types = { + nir_type_int, nir_type_int + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "bany_inequal4", + .num_inputs = 2, + .output_size = 1, + .output_type = nir_type_bool1, + .input_sizes = { + 4, 4 + }, + .input_types = { + nir_type_int, nir_type_int + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "bcsel", + .num_inputs = 3, + .output_size = 0, + .output_type = nir_type_uint, + .input_sizes = { + 0, 0, 0 + }, + .input_types = { + nir_type_bool1, nir_type_uint, nir_type_uint + }, + .algebraic_properties = + 0 +}, +{ + .name = "bfi", + .num_inputs = 3, + .output_size = 0, + .output_type = nir_type_uint32, + .input_sizes = { + 0, 0, 0 + }, + .input_types = { + nir_type_uint32, nir_type_uint32, nir_type_uint32 + }, + .algebraic_properties = + 0 +}, +{ + .name = "bfm", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_uint32, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_int32, nir_type_int32 + }, + .algebraic_properties = + 0 +}, +{ + .name = "bit_count", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_uint32, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_uint + }, + .algebraic_properties = + 0 +}, +{ + .name = "bitfield_insert", + .num_inputs = 4, + .output_size = 0, + .output_type = nir_type_uint32, + .input_sizes = { + 0, 0, 0, 0 + }, + .input_types = { + nir_type_uint32, nir_type_uint32, nir_type_int32, nir_type_int32 + }, + .algebraic_properties = + 0 +}, +{ + .name = "bitfield_reverse", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_uint32, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_uint32 + }, + .algebraic_properties = + 0 +}, +{ + .name = "cube_face_coord", + .num_inputs = 1, + .output_size = 2, + .output_type = nir_type_float32, + .input_sizes = { + 3 + }, + .input_types = { + nir_type_float32 + }, + .algebraic_properties = + 0 +}, +{ + .name = "cube_face_index", + .num_inputs = 1, + .output_size = 1, + .output_type = nir_type_float32, + .input_sizes = { + 3 + }, + .input_types = { + nir_type_float32 + }, + .algebraic_properties = + 0 +}, +{ + .name = "extract_i16", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_int, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_int, nir_type_int + }, + .algebraic_properties = + 0 +}, +{ + .name = "extract_i8", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_int, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_int, nir_type_int + }, + .algebraic_properties = + 0 +}, +{ + .name = "extract_u16", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_uint, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_uint, nir_type_uint + }, + .algebraic_properties = + 0 +}, +{ + .name = "extract_u8", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_uint, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_uint, nir_type_uint + }, + .algebraic_properties = + 0 +}, +{ + .name = "f2b1", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_bool1, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "f2b32", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_bool32, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "f2f16", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float16, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "f2f16_rtne", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float16, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "f2f16_rtz", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float16, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "f2f32", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float32, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "f2f64", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float64, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "f2i1", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_int1, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "f2i16", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_int16, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "f2i32", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_int32, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "f2i64", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_int64, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "f2i8", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_int8, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "f2u1", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_uint1, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "f2u16", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_uint16, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "f2u32", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_uint32, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "f2u64", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_uint64, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "f2u8", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_uint8, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fabs", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fadd", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_float, nir_type_float + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE | NIR_OP_IS_ASSOCIATIVE +}, +{ + .name = "fall_equal2", + .num_inputs = 2, + .output_size = 1, + .output_type = nir_type_float32, + .input_sizes = { + 2, 2 + }, + .input_types = { + nir_type_float32, nir_type_float32 + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "fall_equal3", + .num_inputs = 2, + .output_size = 1, + .output_type = nir_type_float32, + .input_sizes = { + 3, 3 + }, + .input_types = { + nir_type_float32, nir_type_float32 + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "fall_equal4", + .num_inputs = 2, + .output_size = 1, + .output_type = nir_type_float32, + .input_sizes = { + 4, 4 + }, + .input_types = { + nir_type_float32, nir_type_float32 + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "fand", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_float32, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_float32, nir_type_float32 + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "fany_nequal2", + .num_inputs = 2, + .output_size = 1, + .output_type = nir_type_float32, + .input_sizes = { + 2, 2 + }, + .input_types = { + nir_type_float32, nir_type_float32 + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "fany_nequal3", + .num_inputs = 2, + .output_size = 1, + .output_type = nir_type_float32, + .input_sizes = { + 3, 3 + }, + .input_types = { + nir_type_float32, nir_type_float32 + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "fany_nequal4", + .num_inputs = 2, + .output_size = 1, + .output_type = nir_type_float32, + .input_sizes = { + 4, 4 + }, + .input_types = { + nir_type_float32, nir_type_float32 + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "fceil", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fcos", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fcsel", + .num_inputs = 3, + .output_size = 0, + .output_type = nir_type_float32, + .input_sizes = { + 0, 0, 0 + }, + .input_types = { + nir_type_float32, nir_type_float32, nir_type_float32 + }, + .algebraic_properties = + 0 +}, +{ + .name = "fddx", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fddx_coarse", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fddx_fine", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fddy", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fddy_coarse", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fddy_fine", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fdiv", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_float, nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fdot2", + .num_inputs = 2, + .output_size = 1, + .output_type = nir_type_float, + .input_sizes = { + 2, 2 + }, + .input_types = { + nir_type_float, nir_type_float + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "fdot3", + .num_inputs = 2, + .output_size = 1, + .output_type = nir_type_float, + .input_sizes = { + 3, 3 + }, + .input_types = { + nir_type_float, nir_type_float + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "fdot4", + .num_inputs = 2, + .output_size = 1, + .output_type = nir_type_float, + .input_sizes = { + 4, 4 + }, + .input_types = { + nir_type_float, nir_type_float + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "fdot_replicated2", + .num_inputs = 2, + .output_size = 4, + .output_type = nir_type_float, + .input_sizes = { + 2, 2 + }, + .input_types = { + nir_type_float, nir_type_float + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "fdot_replicated3", + .num_inputs = 2, + .output_size = 4, + .output_type = nir_type_float, + .input_sizes = { + 3, 3 + }, + .input_types = { + nir_type_float, nir_type_float + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "fdot_replicated4", + .num_inputs = 2, + .output_size = 4, + .output_type = nir_type_float, + .input_sizes = { + 4, 4 + }, + .input_types = { + nir_type_float, nir_type_float + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "fdph", + .num_inputs = 2, + .output_size = 1, + .output_type = nir_type_float, + .input_sizes = { + 3, 4 + }, + .input_types = { + nir_type_float, nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fdph_replicated", + .num_inputs = 2, + .output_size = 4, + .output_type = nir_type_float, + .input_sizes = { + 3, 4 + }, + .input_types = { + nir_type_float, nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "feq", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_bool1, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_float, nir_type_float + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "feq32", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_bool32, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_float, nir_type_float + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "fexp2", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "ffloor", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "ffma", + .num_inputs = 3, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0, 0, 0 + }, + .input_types = { + nir_type_float, nir_type_float, nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "ffract", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fge", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_bool1, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_float, nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fge32", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_bool32, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_float, nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "find_lsb", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_int32, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_int + }, + .algebraic_properties = + 0 +}, +{ + .name = "flog2", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "flrp", + .num_inputs = 3, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0, 0, 0 + }, + .input_types = { + nir_type_float, nir_type_float, nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "flt", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_bool1, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_float, nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "flt32", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_bool32, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_float, nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fmax", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_float, nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fmax3", + .num_inputs = 3, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0, 0, 0 + }, + .input_types = { + nir_type_float, nir_type_float, nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fmed3", + .num_inputs = 3, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0, 0, 0 + }, + .input_types = { + nir_type_float, nir_type_float, nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fmin", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_float, nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fmin3", + .num_inputs = 3, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0, 0, 0 + }, + .input_types = { + nir_type_float, nir_type_float, nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fmod", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_float, nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fmov", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fmul", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_float, nir_type_float + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE | NIR_OP_IS_ASSOCIATIVE +}, +{ + .name = "fne", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_bool1, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_float, nir_type_float + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "fne32", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_bool32, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_float, nir_type_float + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "fneg", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fnoise1_1", + .num_inputs = 1, + .output_size = 1, + .output_type = nir_type_float, + .input_sizes = { + 1 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fnoise1_2", + .num_inputs = 1, + .output_size = 1, + .output_type = nir_type_float, + .input_sizes = { + 2 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fnoise1_3", + .num_inputs = 1, + .output_size = 1, + .output_type = nir_type_float, + .input_sizes = { + 3 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fnoise1_4", + .num_inputs = 1, + .output_size = 1, + .output_type = nir_type_float, + .input_sizes = { + 4 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fnoise2_1", + .num_inputs = 1, + .output_size = 2, + .output_type = nir_type_float, + .input_sizes = { + 1 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fnoise2_2", + .num_inputs = 1, + .output_size = 2, + .output_type = nir_type_float, + .input_sizes = { + 2 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fnoise2_3", + .num_inputs = 1, + .output_size = 2, + .output_type = nir_type_float, + .input_sizes = { + 3 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fnoise2_4", + .num_inputs = 1, + .output_size = 2, + .output_type = nir_type_float, + .input_sizes = { + 4 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fnoise3_1", + .num_inputs = 1, + .output_size = 3, + .output_type = nir_type_float, + .input_sizes = { + 1 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fnoise3_2", + .num_inputs = 1, + .output_size = 3, + .output_type = nir_type_float, + .input_sizes = { + 2 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fnoise3_3", + .num_inputs = 1, + .output_size = 3, + .output_type = nir_type_float, + .input_sizes = { + 3 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fnoise3_4", + .num_inputs = 1, + .output_size = 3, + .output_type = nir_type_float, + .input_sizes = { + 4 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fnoise4_1", + .num_inputs = 1, + .output_size = 4, + .output_type = nir_type_float, + .input_sizes = { + 1 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fnoise4_2", + .num_inputs = 1, + .output_size = 4, + .output_type = nir_type_float, + .input_sizes = { + 2 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fnoise4_3", + .num_inputs = 1, + .output_size = 4, + .output_type = nir_type_float, + .input_sizes = { + 3 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fnoise4_4", + .num_inputs = 1, + .output_size = 4, + .output_type = nir_type_float, + .input_sizes = { + 4 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fnot", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "for", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_float32, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_float32, nir_type_float32 + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "fpow", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_float, nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fquantize2f16", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "frcp", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "frem", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_float, nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "frexp_exp", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_int32, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float64 + }, + .algebraic_properties = + 0 +}, +{ + .name = "frexp_sig", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float64, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float64 + }, + .algebraic_properties = + 0 +}, +{ + .name = "fround_even", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "frsq", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fsat", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fsign", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fsin", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fsqrt", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fsub", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_float, nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "ftrunc", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "fxor", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_float32, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_float32, nir_type_float32 + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "i2b1", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_bool1, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_int + }, + .algebraic_properties = + 0 +}, +{ + .name = "i2b32", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_bool32, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_int + }, + .algebraic_properties = + 0 +}, +{ + .name = "i2f16", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float16, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_int + }, + .algebraic_properties = + 0 +}, +{ + .name = "i2f32", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float32, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_int + }, + .algebraic_properties = + 0 +}, +{ + .name = "i2f64", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float64, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_int + }, + .algebraic_properties = + 0 +}, +{ + .name = "i2i1", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_int1, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_int + }, + .algebraic_properties = + 0 +}, +{ + .name = "i2i16", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_int16, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_int + }, + .algebraic_properties = + 0 +}, +{ + .name = "i2i32", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_int32, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_int + }, + .algebraic_properties = + 0 +}, +{ + .name = "i2i64", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_int64, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_int + }, + .algebraic_properties = + 0 +}, +{ + .name = "i2i8", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_int8, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_int + }, + .algebraic_properties = + 0 +}, +{ + .name = "iabs", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_int, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_int + }, + .algebraic_properties = + 0 +}, +{ + .name = "iadd", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_int, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_int, nir_type_int + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE | NIR_OP_IS_ASSOCIATIVE +}, +{ + .name = "iand", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_uint, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_uint, nir_type_uint + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE | NIR_OP_IS_ASSOCIATIVE +}, +{ + .name = "ibfe", + .num_inputs = 3, + .output_size = 0, + .output_type = nir_type_int32, + .input_sizes = { + 0, 0, 0 + }, + .input_types = { + nir_type_int32, nir_type_int32, nir_type_int32 + }, + .algebraic_properties = + 0 +}, +{ + .name = "ibitfield_extract", + .num_inputs = 3, + .output_size = 0, + .output_type = nir_type_int32, + .input_sizes = { + 0, 0, 0 + }, + .input_types = { + nir_type_int32, nir_type_int32, nir_type_int32 + }, + .algebraic_properties = + 0 +}, +{ + .name = "idiv", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_int, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_int, nir_type_int + }, + .algebraic_properties = + 0 +}, +{ + .name = "ieq", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_bool1, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_int, nir_type_int + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "ieq32", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_bool32, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_int, nir_type_int + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "ifind_msb", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_int32, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_int32 + }, + .algebraic_properties = + 0 +}, +{ + .name = "ige", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_bool1, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_int, nir_type_int + }, + .algebraic_properties = + 0 +}, +{ + .name = "ige32", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_bool32, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_int, nir_type_int + }, + .algebraic_properties = + 0 +}, +{ + .name = "ilt", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_bool1, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_int, nir_type_int + }, + .algebraic_properties = + 0 +}, +{ + .name = "ilt32", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_bool32, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_int, nir_type_int + }, + .algebraic_properties = + 0 +}, +{ + .name = "imax", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_int, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_int, nir_type_int + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE | NIR_OP_IS_ASSOCIATIVE +}, +{ + .name = "imax3", + .num_inputs = 3, + .output_size = 0, + .output_type = nir_type_int, + .input_sizes = { + 0, 0, 0 + }, + .input_types = { + nir_type_int, nir_type_int, nir_type_int + }, + .algebraic_properties = + 0 +}, +{ + .name = "imed3", + .num_inputs = 3, + .output_size = 0, + .output_type = nir_type_int, + .input_sizes = { + 0, 0, 0 + }, + .input_types = { + nir_type_int, nir_type_int, nir_type_int + }, + .algebraic_properties = + 0 +}, +{ + .name = "imin", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_int, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_int, nir_type_int + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE | NIR_OP_IS_ASSOCIATIVE +}, +{ + .name = "imin3", + .num_inputs = 3, + .output_size = 0, + .output_type = nir_type_int, + .input_sizes = { + 0, 0, 0 + }, + .input_types = { + nir_type_int, nir_type_int, nir_type_int + }, + .algebraic_properties = + 0 +}, +{ + .name = "imod", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_int, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_int, nir_type_int + }, + .algebraic_properties = + 0 +}, +{ + .name = "imov", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_int, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_int + }, + .algebraic_properties = + 0 +}, +{ + .name = "imul", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_int, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_int, nir_type_int + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE | NIR_OP_IS_ASSOCIATIVE +}, +{ + .name = "imul_high", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_int, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_int, nir_type_int + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "ine", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_bool1, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_int, nir_type_int + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "ine32", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_bool32, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_int, nir_type_int + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "ineg", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_int, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_int + }, + .algebraic_properties = + 0 +}, +{ + .name = "inot", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_int, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_int + }, + .algebraic_properties = + 0 +}, +{ + .name = "ior", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_uint, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_uint, nir_type_uint + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE | NIR_OP_IS_ASSOCIATIVE +}, +{ + .name = "irem", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_int, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_int, nir_type_int + }, + .algebraic_properties = + 0 +}, +{ + .name = "ishl", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_int, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_int, nir_type_uint32 + }, + .algebraic_properties = + 0 +}, +{ + .name = "ishr", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_int, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_int, nir_type_uint32 + }, + .algebraic_properties = + 0 +}, +{ + .name = "isign", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_int, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_int + }, + .algebraic_properties = + 0 +}, +{ + .name = "isub", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_int, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_int, nir_type_int + }, + .algebraic_properties = + 0 +}, +{ + .name = "ixor", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_uint, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_uint, nir_type_uint + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE | NIR_OP_IS_ASSOCIATIVE +}, +{ + .name = "ldexp", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_float, nir_type_int32 + }, + .algebraic_properties = + 0 +}, +{ + .name = "pack_32_2x16", + .num_inputs = 1, + .output_size = 1, + .output_type = nir_type_uint32, + .input_sizes = { + 2 + }, + .input_types = { + nir_type_uint16 + }, + .algebraic_properties = + 0 +}, +{ + .name = "pack_32_2x16_split", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_uint32, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_uint16, nir_type_uint16 + }, + .algebraic_properties = + 0 +}, +{ + .name = "pack_64_2x32", + .num_inputs = 1, + .output_size = 1, + .output_type = nir_type_uint64, + .input_sizes = { + 2 + }, + .input_types = { + nir_type_uint32 + }, + .algebraic_properties = + 0 +}, +{ + .name = "pack_64_2x32_split", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_uint64, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_uint32, nir_type_uint32 + }, + .algebraic_properties = + 0 +}, +{ + .name = "pack_64_4x16", + .num_inputs = 1, + .output_size = 1, + .output_type = nir_type_uint64, + .input_sizes = { + 4 + }, + .input_types = { + nir_type_uint16 + }, + .algebraic_properties = + 0 +}, +{ + .name = "pack_half_2x16", + .num_inputs = 1, + .output_size = 1, + .output_type = nir_type_uint32, + .input_sizes = { + 2 + }, + .input_types = { + nir_type_float32 + }, + .algebraic_properties = + 0 +}, +{ + .name = "pack_half_2x16_split", + .num_inputs = 2, + .output_size = 1, + .output_type = nir_type_uint32, + .input_sizes = { + 1, 1 + }, + .input_types = { + nir_type_float32, nir_type_float32 + }, + .algebraic_properties = + 0 +}, +{ + .name = "pack_snorm_2x16", + .num_inputs = 1, + .output_size = 1, + .output_type = nir_type_uint32, + .input_sizes = { + 2 + }, + .input_types = { + nir_type_float32 + }, + .algebraic_properties = + 0 +}, +{ + .name = "pack_snorm_4x8", + .num_inputs = 1, + .output_size = 1, + .output_type = nir_type_uint32, + .input_sizes = { + 4 + }, + .input_types = { + nir_type_float32 + }, + .algebraic_properties = + 0 +}, +{ + .name = "pack_unorm_2x16", + .num_inputs = 1, + .output_size = 1, + .output_type = nir_type_uint32, + .input_sizes = { + 2 + }, + .input_types = { + nir_type_float32 + }, + .algebraic_properties = + 0 +}, +{ + .name = "pack_unorm_4x8", + .num_inputs = 1, + .output_size = 1, + .output_type = nir_type_uint32, + .input_sizes = { + 4 + }, + .input_types = { + nir_type_float32 + }, + .algebraic_properties = + 0 +}, +{ + .name = "pack_uvec2_to_uint", + .num_inputs = 1, + .output_size = 1, + .output_type = nir_type_uint32, + .input_sizes = { + 2 + }, + .input_types = { + nir_type_uint32 + }, + .algebraic_properties = + 0 +}, +{ + .name = "pack_uvec4_to_uint", + .num_inputs = 1, + .output_size = 1, + .output_type = nir_type_uint32, + .input_sizes = { + 4 + }, + .input_types = { + nir_type_uint32 + }, + .algebraic_properties = + 0 +}, +{ + .name = "seq", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_float32, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_float32, nir_type_float32 + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "sge", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_float, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_float, nir_type_float + }, + .algebraic_properties = + 0 +}, +{ + .name = "slt", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_float32, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_float32, nir_type_float32 + }, + .algebraic_properties = + 0 +}, +{ + .name = "sne", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_float32, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_float32, nir_type_float32 + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "u2f16", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float16, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_uint + }, + .algebraic_properties = + 0 +}, +{ + .name = "u2f32", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float32, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_uint + }, + .algebraic_properties = + 0 +}, +{ + .name = "u2f64", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float64, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_uint + }, + .algebraic_properties = + 0 +}, +{ + .name = "u2u1", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_uint1, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_uint + }, + .algebraic_properties = + 0 +}, +{ + .name = "u2u16", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_uint16, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_uint + }, + .algebraic_properties = + 0 +}, +{ + .name = "u2u32", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_uint32, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_uint + }, + .algebraic_properties = + 0 +}, +{ + .name = "u2u64", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_uint64, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_uint + }, + .algebraic_properties = + 0 +}, +{ + .name = "u2u8", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_uint8, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_uint + }, + .algebraic_properties = + 0 +}, +{ + .name = "uadd_carry", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_uint, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_uint, nir_type_uint + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "uadd_sat", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_uint, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_uint, nir_type_uint + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "ubfe", + .num_inputs = 3, + .output_size = 0, + .output_type = nir_type_uint32, + .input_sizes = { + 0, 0, 0 + }, + .input_types = { + nir_type_uint32, nir_type_int32, nir_type_int32 + }, + .algebraic_properties = + 0 +}, +{ + .name = "ubitfield_extract", + .num_inputs = 3, + .output_size = 0, + .output_type = nir_type_uint32, + .input_sizes = { + 0, 0, 0 + }, + .input_types = { + nir_type_uint32, nir_type_int32, nir_type_int32 + }, + .algebraic_properties = + 0 +}, +{ + .name = "udiv", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_uint, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_uint, nir_type_uint + }, + .algebraic_properties = + 0 +}, +{ + .name = "ufind_msb", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_int32, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_uint + }, + .algebraic_properties = + 0 +}, +{ + .name = "uge", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_bool1, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_uint, nir_type_uint + }, + .algebraic_properties = + 0 +}, +{ + .name = "uge32", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_bool32, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_uint, nir_type_uint + }, + .algebraic_properties = + 0 +}, +{ + .name = "ult", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_bool1, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_uint, nir_type_uint + }, + .algebraic_properties = + 0 +}, +{ + .name = "ult32", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_bool32, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_uint, nir_type_uint + }, + .algebraic_properties = + 0 +}, +{ + .name = "umax", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_uint, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_uint, nir_type_uint + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE | NIR_OP_IS_ASSOCIATIVE +}, +{ + .name = "umax3", + .num_inputs = 3, + .output_size = 0, + .output_type = nir_type_uint, + .input_sizes = { + 0, 0, 0 + }, + .input_types = { + nir_type_uint, nir_type_uint, nir_type_uint + }, + .algebraic_properties = + 0 +}, +{ + .name = "umax_4x8", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_int32, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_int32, nir_type_int32 + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE | NIR_OP_IS_ASSOCIATIVE +}, +{ + .name = "umed3", + .num_inputs = 3, + .output_size = 0, + .output_type = nir_type_uint, + .input_sizes = { + 0, 0, 0 + }, + .input_types = { + nir_type_uint, nir_type_uint, nir_type_uint + }, + .algebraic_properties = + 0 +}, +{ + .name = "umin", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_uint, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_uint, nir_type_uint + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE | NIR_OP_IS_ASSOCIATIVE +}, +{ + .name = "umin3", + .num_inputs = 3, + .output_size = 0, + .output_type = nir_type_uint, + .input_sizes = { + 0, 0, 0 + }, + .input_types = { + nir_type_uint, nir_type_uint, nir_type_uint + }, + .algebraic_properties = + 0 +}, +{ + .name = "umin_4x8", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_int32, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_int32, nir_type_int32 + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE | NIR_OP_IS_ASSOCIATIVE +}, +{ + .name = "umod", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_uint, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_uint, nir_type_uint + }, + .algebraic_properties = + 0 +}, +{ + .name = "umul_high", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_uint, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_uint, nir_type_uint + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE +}, +{ + .name = "umul_unorm_4x8", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_int32, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_int32, nir_type_int32 + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE | NIR_OP_IS_ASSOCIATIVE +}, +{ + .name = "unpack_32_2x16", + .num_inputs = 1, + .output_size = 2, + .output_type = nir_type_uint16, + .input_sizes = { + 1 + }, + .input_types = { + nir_type_uint32 + }, + .algebraic_properties = + 0 +}, +{ + .name = "unpack_32_2x16_split_x", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_uint16, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_uint32 + }, + .algebraic_properties = + 0 +}, +{ + .name = "unpack_32_2x16_split_y", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_uint16, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_uint32 + }, + .algebraic_properties = + 0 +}, +{ + .name = "unpack_64_2x32", + .num_inputs = 1, + .output_size = 2, + .output_type = nir_type_uint32, + .input_sizes = { + 1 + }, + .input_types = { + nir_type_uint64 + }, + .algebraic_properties = + 0 +}, +{ + .name = "unpack_64_2x32_split_x", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_uint32, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_uint64 + }, + .algebraic_properties = + 0 +}, +{ + .name = "unpack_64_2x32_split_y", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_uint32, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_uint64 + }, + .algebraic_properties = + 0 +}, +{ + .name = "unpack_64_4x16", + .num_inputs = 1, + .output_size = 4, + .output_type = nir_type_uint16, + .input_sizes = { + 1 + }, + .input_types = { + nir_type_uint64 + }, + .algebraic_properties = + 0 +}, +{ + .name = "unpack_half_2x16", + .num_inputs = 1, + .output_size = 2, + .output_type = nir_type_float32, + .input_sizes = { + 1 + }, + .input_types = { + nir_type_uint32 + }, + .algebraic_properties = + 0 +}, +{ + .name = "unpack_half_2x16_split_x", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float32, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_uint32 + }, + .algebraic_properties = + 0 +}, +{ + .name = "unpack_half_2x16_split_y", + .num_inputs = 1, + .output_size = 0, + .output_type = nir_type_float32, + .input_sizes = { + 0 + }, + .input_types = { + nir_type_uint32 + }, + .algebraic_properties = + 0 +}, +{ + .name = "unpack_snorm_2x16", + .num_inputs = 1, + .output_size = 2, + .output_type = nir_type_float32, + .input_sizes = { + 1 + }, + .input_types = { + nir_type_uint32 + }, + .algebraic_properties = + 0 +}, +{ + .name = "unpack_snorm_4x8", + .num_inputs = 1, + .output_size = 4, + .output_type = nir_type_float32, + .input_sizes = { + 1 + }, + .input_types = { + nir_type_uint32 + }, + .algebraic_properties = + 0 +}, +{ + .name = "unpack_unorm_2x16", + .num_inputs = 1, + .output_size = 2, + .output_type = nir_type_float32, + .input_sizes = { + 1 + }, + .input_types = { + nir_type_uint32 + }, + .algebraic_properties = + 0 +}, +{ + .name = "unpack_unorm_4x8", + .num_inputs = 1, + .output_size = 4, + .output_type = nir_type_float32, + .input_sizes = { + 1 + }, + .input_types = { + nir_type_uint32 + }, + .algebraic_properties = + 0 +}, +{ + .name = "usadd_4x8", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_int32, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_int32, nir_type_int32 + }, + .algebraic_properties = + NIR_OP_IS_COMMUTATIVE | NIR_OP_IS_ASSOCIATIVE +}, +{ + .name = "ushr", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_uint, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_uint, nir_type_uint32 + }, + .algebraic_properties = + 0 +}, +{ + .name = "ussub_4x8", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_int32, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_int32, nir_type_int32 + }, + .algebraic_properties = + 0 +}, +{ + .name = "usub_borrow", + .num_inputs = 2, + .output_size = 0, + .output_type = nir_type_uint, + .input_sizes = { + 0, 0 + }, + .input_types = { + nir_type_uint, nir_type_uint + }, + .algebraic_properties = + 0 +}, +{ + .name = "vec2", + .num_inputs = 2, + .output_size = 2, + .output_type = nir_type_uint, + .input_sizes = { + 1, 1 + }, + .input_types = { + nir_type_uint, nir_type_uint + }, + .algebraic_properties = + 0 +}, +{ + .name = "vec3", + .num_inputs = 3, + .output_size = 3, + .output_type = nir_type_uint, + .input_sizes = { + 1, 1, 1 + }, + .input_types = { + nir_type_uint, nir_type_uint, nir_type_uint + }, + .algebraic_properties = + 0 +}, +{ + .name = "vec4", + .num_inputs = 4, + .output_size = 4, + .output_type = nir_type_uint, + .input_sizes = { + 1, 1, 1, 1 + }, + .input_types = { + nir_type_uint, nir_type_uint, nir_type_uint, nir_type_uint + }, + .algebraic_properties = + 0 +}, +}; + diff --git a/prebuilt-intermediates/nir/nir_opcodes.h b/prebuilt-intermediates/nir/nir_opcodes.h new file mode 100644 index 00000000000..75ec01037b9 --- /dev/null +++ b/prebuilt-intermediates/nir/nir_opcodes.h @@ -0,0 +1,292 @@ +/* Copyright (C) 2014 Connor Abbott + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + * Authors: + * Connor Abbott (cwabbott0@gmail.com) + */ + +#ifndef _NIR_OPCODES_ +#define _NIR_OPCODES_ + + + +typedef enum { + nir_op_b2f16, + nir_op_b2f32, + nir_op_b2f64, + nir_op_b2i1, + nir_op_b2i16, + nir_op_b2i32, + nir_op_b2i64, + nir_op_b2i8, + nir_op_b32all_fequal2, + nir_op_b32all_fequal3, + nir_op_b32all_fequal4, + nir_op_b32all_iequal2, + nir_op_b32all_iequal3, + nir_op_b32all_iequal4, + nir_op_b32any_fnequal2, + nir_op_b32any_fnequal3, + nir_op_b32any_fnequal4, + nir_op_b32any_inequal2, + nir_op_b32any_inequal3, + nir_op_b32any_inequal4, + nir_op_b32csel, + nir_op_ball_fequal2, + nir_op_ball_fequal3, + nir_op_ball_fequal4, + nir_op_ball_iequal2, + nir_op_ball_iequal3, + nir_op_ball_iequal4, + nir_op_bany_fnequal2, + nir_op_bany_fnequal3, + nir_op_bany_fnequal4, + nir_op_bany_inequal2, + nir_op_bany_inequal3, + nir_op_bany_inequal4, + nir_op_bcsel, + nir_op_bfi, + nir_op_bfm, + nir_op_bit_count, + nir_op_bitfield_insert, + nir_op_bitfield_reverse, + nir_op_cube_face_coord, + nir_op_cube_face_index, + nir_op_extract_i16, + nir_op_extract_i8, + nir_op_extract_u16, + nir_op_extract_u8, + nir_op_f2b1, + nir_op_f2b32, + nir_op_f2f16, + nir_op_f2f16_rtne, + nir_op_f2f16_rtz, + nir_op_f2f32, + nir_op_f2f64, + nir_op_f2i1, + nir_op_f2i16, + nir_op_f2i32, + nir_op_f2i64, + nir_op_f2i8, + nir_op_f2u1, + nir_op_f2u16, + nir_op_f2u32, + nir_op_f2u64, + nir_op_f2u8, + nir_op_fabs, + nir_op_fadd, + nir_op_fall_equal2, + nir_op_fall_equal3, + nir_op_fall_equal4, + nir_op_fand, + nir_op_fany_nequal2, + nir_op_fany_nequal3, + nir_op_fany_nequal4, + nir_op_fceil, + nir_op_fcos, + nir_op_fcsel, + nir_op_fddx, + nir_op_fddx_coarse, + nir_op_fddx_fine, + nir_op_fddy, + nir_op_fddy_coarse, + nir_op_fddy_fine, + nir_op_fdiv, + nir_op_fdot2, + nir_op_fdot3, + nir_op_fdot4, + nir_op_fdot_replicated2, + nir_op_fdot_replicated3, + nir_op_fdot_replicated4, + nir_op_fdph, + nir_op_fdph_replicated, + nir_op_feq, + nir_op_feq32, + nir_op_fexp2, + nir_op_ffloor, + nir_op_ffma, + nir_op_ffract, + nir_op_fge, + nir_op_fge32, + nir_op_find_lsb, + nir_op_flog2, + nir_op_flrp, + nir_op_flt, + nir_op_flt32, + nir_op_fmax, + nir_op_fmax3, + nir_op_fmed3, + nir_op_fmin, + nir_op_fmin3, + nir_op_fmod, + nir_op_fmov, + nir_op_fmul, + nir_op_fne, + nir_op_fne32, + nir_op_fneg, + nir_op_fnoise1_1, + nir_op_fnoise1_2, + nir_op_fnoise1_3, + nir_op_fnoise1_4, + nir_op_fnoise2_1, + nir_op_fnoise2_2, + nir_op_fnoise2_3, + nir_op_fnoise2_4, + nir_op_fnoise3_1, + nir_op_fnoise3_2, + nir_op_fnoise3_3, + nir_op_fnoise3_4, + nir_op_fnoise4_1, + nir_op_fnoise4_2, + nir_op_fnoise4_3, + nir_op_fnoise4_4, + nir_op_fnot, + nir_op_for, + nir_op_fpow, + nir_op_fquantize2f16, + nir_op_frcp, + nir_op_frem, + nir_op_frexp_exp, + nir_op_frexp_sig, + nir_op_fround_even, + nir_op_frsq, + nir_op_fsat, + nir_op_fsign, + nir_op_fsin, + nir_op_fsqrt, + nir_op_fsub, + nir_op_ftrunc, + nir_op_fxor, + nir_op_i2b1, + nir_op_i2b32, + nir_op_i2f16, + nir_op_i2f32, + nir_op_i2f64, + nir_op_i2i1, + nir_op_i2i16, + nir_op_i2i32, + nir_op_i2i64, + nir_op_i2i8, + nir_op_iabs, + nir_op_iadd, + nir_op_iand, + nir_op_ibfe, + nir_op_ibitfield_extract, + nir_op_idiv, + nir_op_ieq, + nir_op_ieq32, + nir_op_ifind_msb, + nir_op_ige, + nir_op_ige32, + nir_op_ilt, + nir_op_ilt32, + nir_op_imax, + nir_op_imax3, + nir_op_imed3, + nir_op_imin, + nir_op_imin3, + nir_op_imod, + nir_op_imov, + nir_op_imul, + nir_op_imul_high, + nir_op_ine, + nir_op_ine32, + nir_op_ineg, + nir_op_inot, + nir_op_ior, + nir_op_irem, + nir_op_ishl, + nir_op_ishr, + nir_op_isign, + nir_op_isub, + nir_op_ixor, + nir_op_ldexp, + nir_op_pack_32_2x16, + nir_op_pack_32_2x16_split, + nir_op_pack_64_2x32, + nir_op_pack_64_2x32_split, + nir_op_pack_64_4x16, + nir_op_pack_half_2x16, + nir_op_pack_half_2x16_split, + nir_op_pack_snorm_2x16, + nir_op_pack_snorm_4x8, + nir_op_pack_unorm_2x16, + nir_op_pack_unorm_4x8, + nir_op_pack_uvec2_to_uint, + nir_op_pack_uvec4_to_uint, + nir_op_seq, + nir_op_sge, + nir_op_slt, + nir_op_sne, + nir_op_u2f16, + nir_op_u2f32, + nir_op_u2f64, + nir_op_u2u1, + nir_op_u2u16, + nir_op_u2u32, + nir_op_u2u64, + nir_op_u2u8, + nir_op_uadd_carry, + nir_op_uadd_sat, + nir_op_ubfe, + nir_op_ubitfield_extract, + nir_op_udiv, + nir_op_ufind_msb, + nir_op_uge, + nir_op_uge32, + nir_op_ult, + nir_op_ult32, + nir_op_umax, + nir_op_umax3, + nir_op_umax_4x8, + nir_op_umed3, + nir_op_umin, + nir_op_umin3, + nir_op_umin_4x8, + nir_op_umod, + nir_op_umul_high, + nir_op_umul_unorm_4x8, + nir_op_unpack_32_2x16, + nir_op_unpack_32_2x16_split_x, + nir_op_unpack_32_2x16_split_y, + nir_op_unpack_64_2x32, + nir_op_unpack_64_2x32_split_x, + nir_op_unpack_64_2x32_split_y, + nir_op_unpack_64_4x16, + nir_op_unpack_half_2x16, + nir_op_unpack_half_2x16_split_x, + nir_op_unpack_half_2x16_split_y, + nir_op_unpack_snorm_2x16, + nir_op_unpack_snorm_4x8, + nir_op_unpack_unorm_2x16, + nir_op_unpack_unorm_4x8, + nir_op_usadd_4x8, + nir_op_ushr, + nir_op_ussub_4x8, + nir_op_usub_borrow, + nir_op_vec2, + nir_op_vec3, + nir_op_vec4, + nir_last_opcode = nir_op_vec4, + nir_num_opcodes = nir_last_opcode + 1 +} nir_op; + +#endif /* _NIR_OPCODES_ */ diff --git a/prebuilt-intermediates/nir/nir_opt_algebraic.c b/prebuilt-intermediates/nir/nir_opt_algebraic.c new file mode 100644 index 00000000000..bbfb5021569 --- /dev/null +++ b/prebuilt-intermediates/nir/nir_opt_algebraic.c @@ -0,0 +1,39316 @@ + +#include "nir.h" +#include "nir_builder.h" +#include "nir_search.h" +#include "nir_search_helpers.h" + +#ifndef NIR_OPT_ALGEBRAIC_STRUCT_DEFS +#define NIR_OPT_ALGEBRAIC_STRUCT_DEFS + +struct transform { + const nir_search_expression *search; + const nir_search_value *replace; + unsigned condition_offset; +}; + +#endif + + +static const nir_search_variable search0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search0_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + true, + nir_type_invalid, + (is_pos_power_of_two), +}; +static const nir_search_expression search0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_imul, + { &search0_0.value, &search0_1.value }, + NULL, +}; + +static const nir_search_variable replace0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace0_1_0 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_find_lsb, + { &replace0_1_0.value }, + NULL, +}; +static const nir_search_expression replace0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &replace0_0.value, &replace0_1.value }, + NULL, +}; + +static const nir_search_variable search1_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search1_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + true, + nir_type_invalid, + (is_neg_power_of_two), +}; +static const nir_search_expression search1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_imul, + { &search1_0.value, &search1_1.value }, + NULL, +}; + +static const nir_search_variable replace1_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace1_0_1_0_0 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace1_0_1_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iabs, + { &replace1_0_1_0_0.value }, + NULL, +}; +static const nir_search_expression replace1_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_find_lsb, + { &replace1_0_1_0.value }, + NULL, +}; +static const nir_search_expression replace1_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &replace1_0_0.value, &replace1_0_1.value }, + NULL, +}; +static const nir_search_expression replace1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ineg, + { &replace1_0.value }, + NULL, +}; + +static const nir_search_variable search2_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search2_1 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0x1 /* 1 */ }, +}; +static const nir_search_expression search2 = { + { nir_search_value_expression, -1 }, + false, + nir_op_udiv, + { &search2_0.value, &search2_1.value }, + NULL, +}; + +static const nir_search_variable replace2 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search3_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search3_1 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0x1 /* 1 */ }, +}; +static const nir_search_expression search3 = { + { nir_search_value_expression, -1 }, + false, + nir_op_idiv, + { &search3_0.value, &search3_1.value }, + NULL, +}; + +static const nir_search_variable replace3 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search4_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search4_1 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0x1 /* 1 */ }, +}; +static const nir_search_expression search4 = { + { nir_search_value_expression, -1 }, + false, + nir_op_umod, + { &search4_0.value, &search4_1.value }, + NULL, +}; + +static const nir_search_constant replace4 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0x0 /* 0 */ }, +}; + +static const nir_search_variable search5_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search5_1 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0x1 /* 1 */ }, +}; +static const nir_search_expression search5 = { + { nir_search_value_expression, -1 }, + false, + nir_op_imod, + { &search5_0.value, &search5_1.value }, + NULL, +}; + +static const nir_search_constant replace5 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0x0 /* 0 */ }, +}; + +static const nir_search_variable search6_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search6_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + true, + nir_type_invalid, + (is_pos_power_of_two), +}; +static const nir_search_expression search6 = { + { nir_search_value_expression, 32 }, + false, + nir_op_udiv, + { &search6_0.value, &search6_1.value }, + NULL, +}; + +static const nir_search_variable replace6_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace6_1_0 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace6_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_find_lsb, + { &replace6_1_0.value }, + NULL, +}; +static const nir_search_expression replace6 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &replace6_0.value, &replace6_1.value }, + NULL, +}; + +static const nir_search_variable search7_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search7_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + true, + nir_type_invalid, + (is_pos_power_of_two), +}; +static const nir_search_expression search7 = { + { nir_search_value_expression, 32 }, + false, + nir_op_idiv, + { &search7_0.value, &search7_1.value }, + NULL, +}; + +static const nir_search_variable replace7_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace7_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_isign, + { &replace7_0_0.value }, + NULL, +}; + +static const nir_search_variable replace7_1_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace7_1_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iabs, + { &replace7_1_0_0.value }, + NULL, +}; + +static const nir_search_variable replace7_1_1_0 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace7_1_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_find_lsb, + { &replace7_1_1_0.value }, + NULL, +}; +static const nir_search_expression replace7_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &replace7_1_0.value, &replace7_1_1.value }, + NULL, +}; +static const nir_search_expression replace7 = { + { nir_search_value_expression, 32 }, + false, + nir_op_imul, + { &replace7_0.value, &replace7_1.value }, + NULL, +}; + +static const nir_search_variable search8_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search8_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + true, + nir_type_invalid, + (is_neg_power_of_two), +}; +static const nir_search_expression search8 = { + { nir_search_value_expression, 32 }, + false, + nir_op_idiv, + { &search8_0.value, &search8_1.value }, + NULL, +}; + +static const nir_search_variable replace8_0_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace8_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_isign, + { &replace8_0_0_0.value }, + NULL, +}; + +static const nir_search_variable replace8_0_1_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace8_0_1_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iabs, + { &replace8_0_1_0_0.value }, + NULL, +}; + +static const nir_search_variable replace8_0_1_1_0_0 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace8_0_1_1_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iabs, + { &replace8_0_1_1_0_0.value }, + NULL, +}; +static const nir_search_expression replace8_0_1_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_find_lsb, + { &replace8_0_1_1_0.value }, + NULL, +}; +static const nir_search_expression replace8_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &replace8_0_1_0.value, &replace8_0_1_1.value }, + NULL, +}; +static const nir_search_expression replace8_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_imul, + { &replace8_0_0.value, &replace8_0_1.value }, + NULL, +}; +static const nir_search_expression replace8 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ineg, + { &replace8_0.value }, + NULL, +}; + +static const nir_search_variable search9_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search9_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + true, + nir_type_invalid, + (is_pos_power_of_two), +}; +static const nir_search_expression search9 = { + { nir_search_value_expression, -2 }, + false, + nir_op_umod, + { &search9_0.value, &search9_1.value }, + NULL, +}; + +static const nir_search_variable replace9_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace9_1_0 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace9_1_1 = { + { nir_search_value_constant, -2 }, + nir_type_int, { 0x1 /* 1 */ }, +}; +static const nir_search_expression replace9_1 = { + { nir_search_value_expression, -2 }, + false, + nir_op_isub, + { &replace9_1_0.value, &replace9_1_1.value }, + NULL, +}; +static const nir_search_expression replace9 = { + { nir_search_value_expression, -2 }, + false, + nir_op_iand, + { &replace9_0.value, &replace9_1.value }, + NULL, +}; + +static const nir_search_variable search10_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search10_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fneg, + { &search10_0_0.value }, + NULL, +}; +static const nir_search_expression search10 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fneg, + { &search10_0.value }, + NULL, +}; + +static const nir_search_variable replace10 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search11_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search11_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_ineg, + { &search11_0_0.value }, + NULL, +}; +static const nir_search_expression search11 = { + { nir_search_value_expression, -1 }, + false, + nir_op_ineg, + { &search11_0.value }, + NULL, +}; + +static const nir_search_variable replace11 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search12_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search12_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fabs, + { &search12_0_0.value }, + NULL, +}; +static const nir_search_expression search12 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fabs, + { &search12_0.value }, + NULL, +}; + +static const nir_search_variable replace12_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace12 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fabs, + { &replace12_0.value }, + NULL, +}; + +static const nir_search_variable search13_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search13_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fneg, + { &search13_0_0.value }, + NULL, +}; +static const nir_search_expression search13 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fabs, + { &search13_0.value }, + NULL, +}; + +static const nir_search_variable replace13_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace13 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fabs, + { &replace13_0.value }, + NULL, +}; + +static const nir_search_variable search14_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search14_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_u2f, + { &search14_0_0.value }, + NULL, +}; +static const nir_search_expression search14 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fabs, + { &search14_0.value }, + NULL, +}; + +static const nir_search_variable replace14_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace14 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_u2f, + { &replace14_0.value }, + NULL, +}; + +static const nir_search_variable search15_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search15_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_iabs, + { &search15_0_0.value }, + NULL, +}; +static const nir_search_expression search15 = { + { nir_search_value_expression, -1 }, + false, + nir_op_iabs, + { &search15_0.value }, + NULL, +}; + +static const nir_search_variable replace15_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace15 = { + { nir_search_value_expression, -1 }, + false, + nir_op_iabs, + { &replace15_0.value }, + NULL, +}; + +static const nir_search_variable search16_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search16_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_ineg, + { &search16_0_0.value }, + NULL, +}; +static const nir_search_expression search16 = { + { nir_search_value_expression, -1 }, + false, + nir_op_iabs, + { &search16_0.value }, + NULL, +}; + +static const nir_search_variable replace16_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace16 = { + { nir_search_value_expression, -1 }, + false, + nir_op_iabs, + { &replace16_0.value }, + NULL, +}; + +static const nir_search_variable search17_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search17_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fneg, + { &search17_0_0.value }, + NULL, +}; +static const nir_search_expression search17 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_f2b, + { &search17_0.value }, + NULL, +}; + +static const nir_search_variable replace17_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace17 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_f2b, + { &replace17_0.value }, + NULL, +}; + +static const nir_search_variable search18_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search18_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_ineg, + { &search18_0_0.value }, + NULL, +}; +static const nir_search_expression search18 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_i2b, + { &search18_0.value }, + NULL, +}; + +static const nir_search_variable replace18_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace18 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_i2b, + { &replace18_0.value }, + NULL, +}; + +static const nir_search_variable search19_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search19_1 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search19 = { + { nir_search_value_expression, -1 }, + true, + nir_op_fadd, + { &search19_0.value, &search19_1.value }, + NULL, +}; + +static const nir_search_variable replace19 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search20_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search20_1 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression search20 = { + { nir_search_value_expression, -1 }, + false, + nir_op_iadd, + { &search20_0.value, &search20_1.value }, + NULL, +}; + +static const nir_search_variable replace20 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search21_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search21_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression search21 = { + { nir_search_value_expression, 32 }, + false, + nir_op_usadd_4x8, + { &search21_0.value, &search21_1.value }, + NULL, +}; + +static const nir_search_variable replace21 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search22_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search22_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { -0x1 /* -1 */ }, +}; +static const nir_search_expression search22 = { + { nir_search_value_expression, 32 }, + false, + nir_op_usadd_4x8, + { &search22_0.value, &search22_1.value }, + NULL, +}; + +static const nir_search_constant replace22 = { + { nir_search_value_constant, 32 }, + nir_type_int, { -0x1 /* -1 */ }, +}; + +static const nir_search_variable search23_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search23_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search23_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fmul, + { &search23_0_0.value, &search23_0_1.value }, + NULL, +}; + +static const nir_search_variable search23_1_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search23_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search23_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fmul, + { &search23_1_0.value, &search23_1_1.value }, + NULL, +}; +static const nir_search_expression search23 = { + { nir_search_value_expression, -3 }, + true, + nir_op_fadd, + { &search23_0.value, &search23_1.value }, + NULL, +}; + +static const nir_search_variable replace23_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace23_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace23_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace23_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fadd, + { &replace23_1_0.value, &replace23_1_1.value }, + NULL, +}; +static const nir_search_expression replace23 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fmul, + { &replace23_0.value, &replace23_1.value }, + NULL, +}; + +static const nir_search_variable search24_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search24_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search24_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_imul, + { &search24_0_0.value, &search24_0_1.value }, + NULL, +}; + +static const nir_search_variable search24_1_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search24_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search24_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_imul, + { &search24_1_0.value, &search24_1_1.value }, + NULL, +}; +static const nir_search_expression search24 = { + { nir_search_value_expression, -3 }, + false, + nir_op_iadd, + { &search24_0.value, &search24_1.value }, + NULL, +}; + +static const nir_search_variable replace24_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace24_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace24_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace24_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_iadd, + { &replace24_1_0.value, &replace24_1_1.value }, + NULL, +}; +static const nir_search_expression replace24 = { + { nir_search_value_expression, -3 }, + false, + nir_op_imul, + { &replace24_0.value, &replace24_1.value }, + NULL, +}; + +static const nir_search_variable search25_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search25_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fneg, + { &search25_0_0.value }, + NULL, +}; + +static const nir_search_variable search25_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search25 = { + { nir_search_value_expression, -1 }, + true, + nir_op_fadd, + { &search25_0.value, &search25_1.value }, + NULL, +}; + +static const nir_search_constant replace25 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; + +static const nir_search_variable search26_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search26_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_ineg, + { &search26_0_0.value }, + NULL, +}; + +static const nir_search_variable search26_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search26 = { + { nir_search_value_expression, -1 }, + false, + nir_op_iadd, + { &search26_0.value, &search26_1.value }, + NULL, +}; + +static const nir_search_constant replace26 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0x0 /* 0 */ }, +}; + +static const nir_search_variable search27_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search27_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_ineg, + { &search27_0_0.value }, + NULL, +}; + +static const nir_search_variable search27_1_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search27_1_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search27_1 = { + { nir_search_value_expression, -2 }, + false, + nir_op_iadd, + { &search27_1_0.value, &search27_1_1.value }, + NULL, +}; +static const nir_search_expression search27 = { + { nir_search_value_expression, -2 }, + false, + nir_op_iadd, + { &search27_0.value, &search27_1.value }, + NULL, +}; + +static const nir_search_variable replace27 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search28_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search28_1_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search28_1_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_ineg, + { &search28_1_0_0.value }, + NULL, +}; + +static const nir_search_variable search28_1_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search28_1 = { + { nir_search_value_expression, -2 }, + false, + nir_op_iadd, + { &search28_1_0.value, &search28_1_1.value }, + NULL, +}; +static const nir_search_expression search28 = { + { nir_search_value_expression, -2 }, + false, + nir_op_iadd, + { &search28_0.value, &search28_1.value }, + NULL, +}; + +static const nir_search_variable replace28 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search29_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search29_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fneg, + { &search29_0_0.value }, + NULL, +}; + +static const nir_search_variable search29_1_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search29_1_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search29_1 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fadd, + { &search29_1_0.value, &search29_1_1.value }, + NULL, +}; +static const nir_search_expression search29 = { + { nir_search_value_expression, -2 }, + true, + nir_op_fadd, + { &search29_0.value, &search29_1.value }, + NULL, +}; + +static const nir_search_variable replace29 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search30_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search30_1_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search30_1_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fneg, + { &search30_1_0_0.value }, + NULL, +}; + +static const nir_search_variable search30_1_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search30_1 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fadd, + { &search30_1_0.value, &search30_1_1.value }, + NULL, +}; +static const nir_search_expression search30 = { + { nir_search_value_expression, -2 }, + true, + nir_op_fadd, + { &search30_0.value, &search30_1.value }, + NULL, +}; + +static const nir_search_variable replace30 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search31_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search31_1 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search31 = { + { nir_search_value_expression, -1 }, + true, + nir_op_fmul, + { &search31_0.value, &search31_1.value }, + NULL, +}; + +static const nir_search_constant replace31 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; + +static const nir_search_variable search32_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search32_1 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression search32 = { + { nir_search_value_expression, -1 }, + false, + nir_op_imul, + { &search32_0.value, &search32_1.value }, + NULL, +}; + +static const nir_search_constant replace32 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0x0 /* 0 */ }, +}; + +static const nir_search_variable search33_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search33_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression search33 = { + { nir_search_value_expression, 32 }, + false, + nir_op_umul_unorm_4x8, + { &search33_0.value, &search33_1.value }, + NULL, +}; + +static const nir_search_constant replace33 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x0 /* 0 */ }, +}; + +static const nir_search_variable search34_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search34_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { -0x1 /* -1 */ }, +}; +static const nir_search_expression search34 = { + { nir_search_value_expression, 32 }, + false, + nir_op_umul_unorm_4x8, + { &search34_0.value, &search34_1.value }, + NULL, +}; + +static const nir_search_variable replace34 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search35_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search35_1 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x3ff0000000000000 /* 1.0 */ }, +}; +static const nir_search_expression search35 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmul, + { &search35_0.value, &search35_1.value }, + NULL, +}; + +static const nir_search_variable replace35 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search36_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search36_1 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0x1 /* 1 */ }, +}; +static const nir_search_expression search36 = { + { nir_search_value_expression, -1 }, + false, + nir_op_imul, + { &search36_0.value, &search36_1.value }, + NULL, +}; + +static const nir_search_variable replace36 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search37_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search37_1 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0xbff0000000000000L /* -1.0 */ }, +}; +static const nir_search_expression search37 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmul, + { &search37_0.value, &search37_1.value }, + NULL, +}; + +static const nir_search_variable replace37_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace37 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fneg, + { &replace37_0.value }, + NULL, +}; + +static const nir_search_variable search38_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search38_1 = { + { nir_search_value_constant, -1 }, + nir_type_int, { -0x1 /* -1 */ }, +}; +static const nir_search_expression search38 = { + { nir_search_value_expression, -1 }, + false, + nir_op_imul, + { &search38_0.value, &search38_1.value }, + NULL, +}; + +static const nir_search_variable replace38_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace38 = { + { nir_search_value_expression, -1 }, + false, + nir_op_ineg, + { &replace38_0.value }, + NULL, +}; + +static const nir_search_variable search39_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search39_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fsign, + { &search39_0_0.value }, + NULL, +}; + +static const nir_search_variable search39_1_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search39_1_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search39_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmul, + { &search39_1_0.value, &search39_1_1.value }, + NULL, +}; +static const nir_search_expression search39 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmul, + { &search39_0.value, &search39_1.value }, + NULL, +}; + +static const nir_search_variable replace39_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace39_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fabs, + { &replace39_0_0.value }, + NULL, +}; + +static const nir_search_variable replace39_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace39 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmul, + { &replace39_0.value, &replace39_1.value }, + NULL, +}; + +static const nir_search_variable search40_0_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search40_0_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fsign, + { &search40_0_0_0.value }, + NULL, +}; + +static const nir_search_variable search40_0_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search40_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmul, + { &search40_0_0.value, &search40_0_1.value }, + NULL, +}; + +static const nir_search_variable search40_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search40 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmul, + { &search40_0.value, &search40_1.value }, + NULL, +}; + +static const nir_search_variable replace40_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace40_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fabs, + { &replace40_0_0.value }, + NULL, +}; + +static const nir_search_variable replace40_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace40 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmul, + { &replace40_0.value, &replace40_1.value }, + NULL, +}; + +static const nir_search_constant search41_0 = { + { nir_search_value_constant, -2 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; + +static const nir_search_variable search41_1 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search41_2 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search41 = { + { nir_search_value_expression, -2 }, + true, + nir_op_ffma, + { &search41_0.value, &search41_1.value, &search41_2.value }, + NULL, +}; + +static const nir_search_variable replace41 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search42_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search42_1 = { + { nir_search_value_constant, -2 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; + +static const nir_search_variable search42_2 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search42 = { + { nir_search_value_expression, -2 }, + true, + nir_op_ffma, + { &search42_0.value, &search42_1.value, &search42_2.value }, + NULL, +}; + +static const nir_search_variable replace42 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search43_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search43_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search43_2 = { + { nir_search_value_constant, -2 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search43 = { + { nir_search_value_expression, -2 }, + true, + nir_op_ffma, + { &search43_0.value, &search43_1.value, &search43_2.value }, + NULL, +}; + +static const nir_search_variable replace43_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace43_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace43 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fmul, + { &replace43_0.value, &replace43_1.value }, + NULL, +}; + +static const nir_search_variable search44_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search44_1 = { + { nir_search_value_constant, -2 }, + nir_type_float, { 0x3ff0000000000000 /* 1.0 */ }, +}; + +static const nir_search_variable search44_2 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search44 = { + { nir_search_value_expression, -2 }, + false, + nir_op_ffma, + { &search44_0.value, &search44_1.value, &search44_2.value }, + NULL, +}; + +static const nir_search_variable replace44_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace44_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace44 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fadd, + { &replace44_0.value, &replace44_1.value }, + NULL, +}; + +static const nir_search_constant search45_0 = { + { nir_search_value_constant, -2 }, + nir_type_float, { 0x3ff0000000000000 /* 1.0 */ }, +}; + +static const nir_search_variable search45_1 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search45_2 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search45 = { + { nir_search_value_expression, -2 }, + false, + nir_op_ffma, + { &search45_0.value, &search45_1.value, &search45_2.value }, + NULL, +}; + +static const nir_search_variable replace45_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace45_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace45 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fadd, + { &replace45_0.value, &replace45_1.value }, + NULL, +}; + +static const nir_search_variable search46_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search46_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search46_2 = { + { nir_search_value_constant, -2 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search46 = { + { nir_search_value_expression, -2 }, + true, + nir_op_flrp, + { &search46_0.value, &search46_1.value, &search46_2.value }, + NULL, +}; + +static const nir_search_variable replace46 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search47_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search47_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search47_2 = { + { nir_search_value_constant, -2 }, + nir_type_float, { 0x3ff0000000000000 /* 1.0 */ }, +}; +static const nir_search_expression search47 = { + { nir_search_value_expression, -2 }, + true, + nir_op_flrp, + { &search47_0.value, &search47_1.value, &search47_2.value }, + NULL, +}; + +static const nir_search_variable replace47 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search48_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search48_1 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search48_2 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search48 = { + { nir_search_value_expression, -2 }, + true, + nir_op_flrp, + { &search48_0.value, &search48_1.value, &search48_2.value }, + NULL, +}; + +static const nir_search_variable replace48 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search49_0 = { + { nir_search_value_constant, -2 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; + +static const nir_search_variable search49_1 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search49_2 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search49 = { + { nir_search_value_expression, -2 }, + true, + nir_op_flrp, + { &search49_0.value, &search49_1.value, &search49_2.value }, + NULL, +}; + +static const nir_search_variable replace49_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace49_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace49 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fmul, + { &replace49_0.value, &replace49_1.value }, + NULL, +}; + +static const nir_search_variable search50_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search50_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search50_2_0 = { + { nir_search_value_variable, 1 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search50_2 = { + { nir_search_value_expression, -2 }, + false, + nir_search_op_b2f, + { &search50_2_0.value }, + NULL, +}; +static const nir_search_expression search50 = { + { nir_search_value_expression, -2 }, + true, + nir_op_flrp, + { &search50_0.value, &search50_1.value, &search50_2.value }, + NULL, +}; + +static const nir_search_variable replace50_0 = { + { nir_search_value_variable, 1 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace50_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace50_2 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace50 = { + { nir_search_value_expression, -2 }, + false, + nir_op_bcsel, + { &replace50_0.value, &replace50_1.value, &replace50_2.value }, + NULL, +}; + +static const nir_search_variable search51_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search51_1 = { + { nir_search_value_constant, -2 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; + +static const nir_search_variable search51_2 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search51 = { + { nir_search_value_expression, -2 }, + true, + nir_op_flrp, + { &search51_0.value, &search51_1.value, &search51_2.value }, + NULL, +}; + +static const nir_search_variable replace51_0_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace51_0_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fneg, + { &replace51_0_0_0.value }, + NULL, +}; + +static const nir_search_variable replace51_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace51_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fmul, + { &replace51_0_0.value, &replace51_0_1.value }, + NULL, +}; + +static const nir_search_variable replace51_1 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace51 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fadd, + { &replace51_0.value, &replace51_1.value }, + NULL, +}; + +static const nir_search_variable search52_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search52_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search52_2 = { + { nir_search_value_variable, 32 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search52 = { + { nir_search_value_expression, 32 }, + false, + nir_op_flrp, + { &search52_0.value, &search52_1.value, &search52_2.value }, + NULL, +}; + +static const nir_search_variable replace52_0_0 = { + { nir_search_value_variable, 32 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace52_0_1_0 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace52_0_1_1 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace52_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fsub, + { &replace52_0_1_0.value, &replace52_0_1_1.value }, + NULL, +}; +static const nir_search_expression replace52_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fmul, + { &replace52_0_0.value, &replace52_0_1.value }, + NULL, +}; + +static const nir_search_variable replace52_1 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace52 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fadd, + { &replace52_0.value, &replace52_1.value }, + NULL, +}; + +static const nir_search_variable search53_0 = { + { nir_search_value_variable, 64 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search53_1 = { + { nir_search_value_variable, 64 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search53_2 = { + { nir_search_value_variable, 64 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search53 = { + { nir_search_value_expression, 64 }, + false, + nir_op_flrp, + { &search53_0.value, &search53_1.value, &search53_2.value }, + NULL, +}; + +static const nir_search_variable replace53_0_0 = { + { nir_search_value_variable, 64 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace53_0_1_0 = { + { nir_search_value_variable, 64 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace53_0_1_1 = { + { nir_search_value_variable, 64 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace53_0_1 = { + { nir_search_value_expression, 64 }, + false, + nir_op_fsub, + { &replace53_0_1_0.value, &replace53_0_1_1.value }, + NULL, +}; +static const nir_search_expression replace53_0 = { + { nir_search_value_expression, 64 }, + false, + nir_op_fmul, + { &replace53_0_0.value, &replace53_0_1.value }, + NULL, +}; + +static const nir_search_variable replace53_1 = { + { nir_search_value_variable, 64 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace53 = { + { nir_search_value_expression, 64 }, + false, + nir_op_fadd, + { &replace53_0.value, &replace53_1.value }, + NULL, +}; + +static const nir_search_variable search54_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search54 = { + { nir_search_value_expression, -1 }, + false, + nir_op_ffloor, + { &search54_0.value }, + NULL, +}; + +static const nir_search_variable replace54_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace54_1_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace54_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_ffract, + { &replace54_1_0.value }, + NULL, +}; +static const nir_search_expression replace54 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fsub, + { &replace54_0.value, &replace54_1.value }, + NULL, +}; + +static const nir_search_variable search55_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search55 = { + { nir_search_value_expression, -1 }, + false, + nir_op_ffract, + { &search55_0.value }, + NULL, +}; + +static const nir_search_variable replace55_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace55_1_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace55_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_ffloor, + { &replace55_1_0.value }, + NULL, +}; +static const nir_search_expression replace55 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fsub, + { &replace55_0.value, &replace55_1.value }, + NULL, +}; + +static const nir_search_variable search56_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search56 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fceil, + { &search56_0.value }, + NULL, +}; + +static const nir_search_variable replace56_0_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace56_0_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fneg, + { &replace56_0_0_0.value }, + NULL, +}; +static const nir_search_expression replace56_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_ffloor, + { &replace56_0_0.value }, + NULL, +}; +static const nir_search_expression replace56 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fneg, + { &replace56_0.value }, + NULL, +}; + +static const nir_search_variable search57_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search57_0_1_0 = { + { nir_search_value_constant, -3 }, + nir_type_float, { 0x3ff0000000000000 /* 1.0 */ }, +}; + +static const nir_search_variable search57_0_1_1_0_0 = { + { nir_search_value_variable, 1 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search57_0_1_1_0 = { + { nir_search_value_expression, -3 }, + false, + nir_search_op_b2f, + { &search57_0_1_1_0_0.value }, + NULL, +}; +static const nir_search_expression search57_0_1_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fneg, + { &search57_0_1_1_0.value }, + NULL, +}; +static const nir_search_expression search57_0_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fadd, + { &search57_0_1_0.value, &search57_0_1_1.value }, + NULL, +}; +static const nir_search_expression search57_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fmul, + { &search57_0_0.value, &search57_0_1.value }, + NULL, +}; + +static const nir_search_variable search57_1_0 = { + { nir_search_value_variable, -3 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search57_1_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search57_1_1 = { + { nir_search_value_expression, -3 }, + false, + nir_search_op_b2f, + { &search57_1_1_0.value }, + NULL, +}; +static const nir_search_expression search57_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fmul, + { &search57_1_0.value, &search57_1_1.value }, + NULL, +}; +static const nir_search_expression search57 = { + { nir_search_value_expression, -3 }, + true, + nir_op_fadd, + { &search57_0.value, &search57_1.value }, + NULL, +}; + +static const nir_search_variable replace57_0 = { + { nir_search_value_variable, 1 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace57_1 = { + { nir_search_value_variable, -3 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace57_2 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace57 = { + { nir_search_value_expression, -3 }, + false, + nir_op_bcsel, + { &replace57_0.value, &replace57_1.value, &replace57_2.value }, + NULL, +}; + +static const nir_search_variable search58_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search58_0_1_0 = { + { nir_search_value_constant, 32 }, + nir_type_float, { 0x3ff0000000000000 /* 1.0 */ }, +}; + +static const nir_search_variable search58_0_1_1_0 = { + { nir_search_value_variable, 32 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search58_0_1_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fneg, + { &search58_0_1_1_0.value }, + NULL, +}; +static const nir_search_expression search58_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fadd, + { &search58_0_1_0.value, &search58_0_1_1.value }, + NULL, +}; +static const nir_search_expression search58_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fmul, + { &search58_0_0.value, &search58_0_1.value }, + NULL, +}; + +static const nir_search_variable search58_1_0 = { + { nir_search_value_variable, 32 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search58_1_1 = { + { nir_search_value_variable, 32 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search58_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fmul, + { &search58_1_0.value, &search58_1_1.value }, + NULL, +}; +static const nir_search_expression search58 = { + { nir_search_value_expression, 32 }, + true, + nir_op_fadd, + { &search58_0.value, &search58_1.value }, + NULL, +}; + +static const nir_search_variable replace58_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace58_1 = { + { nir_search_value_variable, 32 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace58_2 = { + { nir_search_value_variable, 32 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace58 = { + { nir_search_value_expression, 32 }, + false, + nir_op_flrp, + { &replace58_0.value, &replace58_1.value, &replace58_2.value }, + NULL, +}; + +static const nir_search_variable search59_0_0 = { + { nir_search_value_variable, 64 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search59_0_1_0 = { + { nir_search_value_constant, 64 }, + nir_type_float, { 0x3ff0000000000000 /* 1.0 */ }, +}; + +static const nir_search_variable search59_0_1_1_0 = { + { nir_search_value_variable, 64 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search59_0_1_1 = { + { nir_search_value_expression, 64 }, + false, + nir_op_fneg, + { &search59_0_1_1_0.value }, + NULL, +}; +static const nir_search_expression search59_0_1 = { + { nir_search_value_expression, 64 }, + false, + nir_op_fadd, + { &search59_0_1_0.value, &search59_0_1_1.value }, + NULL, +}; +static const nir_search_expression search59_0 = { + { nir_search_value_expression, 64 }, + false, + nir_op_fmul, + { &search59_0_0.value, &search59_0_1.value }, + NULL, +}; + +static const nir_search_variable search59_1_0 = { + { nir_search_value_variable, 64 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search59_1_1 = { + { nir_search_value_variable, 64 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search59_1 = { + { nir_search_value_expression, 64 }, + false, + nir_op_fmul, + { &search59_1_0.value, &search59_1_1.value }, + NULL, +}; +static const nir_search_expression search59 = { + { nir_search_value_expression, 64 }, + true, + nir_op_fadd, + { &search59_0.value, &search59_1.value }, + NULL, +}; + +static const nir_search_variable replace59_0 = { + { nir_search_value_variable, 64 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace59_1 = { + { nir_search_value_variable, 64 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace59_2 = { + { nir_search_value_variable, 64 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace59 = { + { nir_search_value_expression, 64 }, + false, + nir_op_flrp, + { &replace59_0.value, &replace59_1.value, &replace59_2.value }, + NULL, +}; + +static const nir_search_variable search60_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search60_1_0_0 = { + { nir_search_value_variable, 1 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search60_1_0 = { + { nir_search_value_expression, -1 }, + false, + nir_search_op_b2f, + { &search60_1_0_0.value }, + NULL, +}; + +static const nir_search_variable search60_1_1_0 = { + { nir_search_value_variable, -1 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search60_1_1_1_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search60_1_1_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fneg, + { &search60_1_1_1_0.value }, + NULL, +}; +static const nir_search_expression search60_1_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fadd, + { &search60_1_1_0.value, &search60_1_1_1.value }, + NULL, +}; +static const nir_search_expression search60_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmul, + { &search60_1_0.value, &search60_1_1.value }, + NULL, +}; +static const nir_search_expression search60 = { + { nir_search_value_expression, -1 }, + true, + nir_op_fadd, + { &search60_0.value, &search60_1.value }, + NULL, +}; + +static const nir_search_variable replace60_0 = { + { nir_search_value_variable, 1 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace60_1 = { + { nir_search_value_variable, -1 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace60_2 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace60 = { + { nir_search_value_expression, -1 }, + false, + nir_op_bcsel, + { &replace60_0.value, &replace60_1.value, &replace60_2.value }, + NULL, +}; + +static const nir_search_variable search61_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search61_1_0 = { + { nir_search_value_variable, 32 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search61_1_1_0 = { + { nir_search_value_variable, 32 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search61_1_1_1_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search61_1_1_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fneg, + { &search61_1_1_1_0.value }, + NULL, +}; +static const nir_search_expression search61_1_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fadd, + { &search61_1_1_0.value, &search61_1_1_1.value }, + NULL, +}; +static const nir_search_expression search61_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fmul, + { &search61_1_0.value, &search61_1_1.value }, + NULL, +}; +static const nir_search_expression search61 = { + { nir_search_value_expression, 32 }, + true, + nir_op_fadd, + { &search61_0.value, &search61_1.value }, + NULL, +}; + +static const nir_search_variable replace61_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace61_1 = { + { nir_search_value_variable, 32 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace61_2 = { + { nir_search_value_variable, 32 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace61 = { + { nir_search_value_expression, 32 }, + false, + nir_op_flrp, + { &replace61_0.value, &replace61_1.value, &replace61_2.value }, + NULL, +}; + +static const nir_search_variable search62_0 = { + { nir_search_value_variable, 64 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search62_1_0 = { + { nir_search_value_variable, 64 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search62_1_1_0 = { + { nir_search_value_variable, 64 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search62_1_1_1_0 = { + { nir_search_value_variable, 64 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search62_1_1_1 = { + { nir_search_value_expression, 64 }, + false, + nir_op_fneg, + { &search62_1_1_1_0.value }, + NULL, +}; +static const nir_search_expression search62_1_1 = { + { nir_search_value_expression, 64 }, + false, + nir_op_fadd, + { &search62_1_1_0.value, &search62_1_1_1.value }, + NULL, +}; +static const nir_search_expression search62_1 = { + { nir_search_value_expression, 64 }, + false, + nir_op_fmul, + { &search62_1_0.value, &search62_1_1.value }, + NULL, +}; +static const nir_search_expression search62 = { + { nir_search_value_expression, 64 }, + true, + nir_op_fadd, + { &search62_0.value, &search62_1.value }, + NULL, +}; + +static const nir_search_variable replace62_0 = { + { nir_search_value_variable, 64 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace62_1 = { + { nir_search_value_variable, 64 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace62_2 = { + { nir_search_value_variable, 64 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace62 = { + { nir_search_value_expression, 64 }, + false, + nir_op_flrp, + { &replace62_0.value, &replace62_1.value, &replace62_2.value }, + NULL, +}; + +static const nir_search_variable search63_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search63_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search63_2 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search63 = { + { nir_search_value_expression, -3 }, + false, + nir_op_ffma, + { &search63_0.value, &search63_1.value, &search63_2.value }, + NULL, +}; + +static const nir_search_variable replace63_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace63_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace63_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fmul, + { &replace63_0_0.value, &replace63_0_1.value }, + NULL, +}; + +static const nir_search_variable replace63_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace63 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fadd, + { &replace63_0.value, &replace63_1.value }, + NULL, +}; + +static const nir_search_variable search64_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search64_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search64_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fmul, + { &search64_0_0.value, &search64_0_1.value }, + NULL, +}; + +static const nir_search_variable search64_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search64 = { + { nir_search_value_expression, -3 }, + true, + nir_op_fadd, + { &search64_0.value, &search64_1.value }, + NULL, +}; + +static const nir_search_variable replace64_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace64_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace64_2 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace64 = { + { nir_search_value_expression, -3 }, + false, + nir_op_ffma, + { &replace64_0.value, &replace64_1.value, &replace64_2.value }, + NULL, +}; + +static const nir_search_variable search65_0_0 = { + { nir_search_value_variable, -4 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search65_0_1 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search65_0_2 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search65_0_3 = { + { nir_search_value_constant, -4 }, + nir_type_float, { 0x3ff0000000000000 /* 1.0 */ }, +}; +static const nir_search_expression search65_0 = { + { nir_search_value_expression, -4 }, + false, + nir_op_vec4, + { &search65_0_0.value, &search65_0_1.value, &search65_0_2.value, &search65_0_3.value }, + NULL, +}; + +static const nir_search_variable search65_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search65 = { + { nir_search_value_expression, -4 }, + false, + nir_op_fdot4, + { &search65_0.value, &search65_1.value }, + NULL, +}; + +static const nir_search_variable replace65_0_0 = { + { nir_search_value_variable, -4 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace65_0_1 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace65_0_2 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace65_0 = { + { nir_search_value_expression, -4 }, + false, + nir_op_vec3, + { &replace65_0_0.value, &replace65_0_1.value, &replace65_0_2.value }, + NULL, +}; + +static const nir_search_variable replace65_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace65 = { + { nir_search_value_expression, -4 }, + false, + nir_op_fdph, + { &replace65_0.value, &replace65_1.value }, + NULL, +}; + +static const nir_search_variable search66_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search66_0_1 = { + { nir_search_value_constant, -2 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; + +static const nir_search_constant search66_0_2 = { + { nir_search_value_constant, -2 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; + +static const nir_search_constant search66_0_3 = { + { nir_search_value_constant, -2 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search66_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_vec4, + { &search66_0_0.value, &search66_0_1.value, &search66_0_2.value, &search66_0_3.value }, + NULL, +}; + +static const nir_search_variable search66_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search66 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fdot4, + { &search66_0.value, &search66_1.value }, + NULL, +}; + +static const nir_search_variable replace66_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace66_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace66 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fmul, + { &replace66_0.value, &replace66_1.value }, + NULL, +}; + +static const nir_search_variable search67_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search67_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search67_0_2 = { + { nir_search_value_constant, -3 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; + +static const nir_search_constant search67_0_3 = { + { nir_search_value_constant, -3 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search67_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_vec4, + { &search67_0_0.value, &search67_0_1.value, &search67_0_2.value, &search67_0_3.value }, + NULL, +}; + +static const nir_search_variable search67_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search67 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fdot4, + { &search67_0.value, &search67_1.value }, + NULL, +}; + +static const nir_search_variable replace67_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace67_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace67_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_vec2, + { &replace67_0_0.value, &replace67_0_1.value }, + NULL, +}; + +static const nir_search_variable replace67_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace67 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fdot2, + { &replace67_0.value, &replace67_1.value }, + NULL, +}; + +static const nir_search_variable search68_0_0 = { + { nir_search_value_variable, -4 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search68_0_1 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search68_0_2 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search68_0_3 = { + { nir_search_value_constant, -4 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search68_0 = { + { nir_search_value_expression, -4 }, + false, + nir_op_vec4, + { &search68_0_0.value, &search68_0_1.value, &search68_0_2.value, &search68_0_3.value }, + NULL, +}; + +static const nir_search_variable search68_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search68 = { + { nir_search_value_expression, -4 }, + false, + nir_op_fdot4, + { &search68_0.value, &search68_1.value }, + NULL, +}; + +static const nir_search_variable replace68_0_0 = { + { nir_search_value_variable, -4 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace68_0_1 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace68_0_2 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace68_0 = { + { nir_search_value_expression, -4 }, + false, + nir_op_vec3, + { &replace68_0_0.value, &replace68_0_1.value, &replace68_0_2.value }, + NULL, +}; + +static const nir_search_variable replace68_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace68 = { + { nir_search_value_expression, -4 }, + false, + nir_op_fdot3, + { &replace68_0.value, &replace68_1.value }, + NULL, +}; + +static const nir_search_variable search69_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search69_0_1 = { + { nir_search_value_constant, -2 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; + +static const nir_search_constant search69_0_2 = { + { nir_search_value_constant, -2 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search69_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_vec3, + { &search69_0_0.value, &search69_0_1.value, &search69_0_2.value }, + NULL, +}; + +static const nir_search_variable search69_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search69 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fdot3, + { &search69_0.value, &search69_1.value }, + NULL, +}; + +static const nir_search_variable replace69_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace69_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace69 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fmul, + { &replace69_0.value, &replace69_1.value }, + NULL, +}; + +static const nir_search_variable search70_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search70_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search70_0_2 = { + { nir_search_value_constant, -3 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search70_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_vec3, + { &search70_0_0.value, &search70_0_1.value, &search70_0_2.value }, + NULL, +}; + +static const nir_search_variable search70_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search70 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fdot3, + { &search70_0.value, &search70_1.value }, + NULL, +}; + +static const nir_search_variable replace70_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace70_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace70_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_vec2, + { &replace70_0_0.value, &replace70_0_1.value }, + NULL, +}; + +static const nir_search_variable replace70_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace70 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fdot2, + { &replace70_0.value, &replace70_1.value }, + NULL, +}; + +static const nir_search_variable search71_0_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search71_0_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search71_0_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_imul, + { &search71_0_0_0.value, &search71_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search71_0_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search71_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_iadd, + { &search71_0_0.value, &search71_0_1.value }, + NULL, +}; + +static const nir_search_variable search71_1 = { + { nir_search_value_variable, 32 }, + 3, /* d */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search71 = { + { nir_search_value_expression, -3 }, + false, + nir_op_ishl, + { &search71_0.value, &search71_1.value }, + NULL, +}; + +static const nir_search_variable replace71_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace71_0_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace71_0_1_1 = { + { nir_search_value_variable, 32 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace71_0_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_ishl, + { &replace71_0_1_0.value, &replace71_0_1_1.value }, + NULL, +}; +static const nir_search_expression replace71_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_imul, + { &replace71_0_0.value, &replace71_0_1.value }, + NULL, +}; + +static const nir_search_variable replace71_1_0 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace71_1_1 = { + { nir_search_value_variable, 32 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace71_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_ishl, + { &replace71_1_0.value, &replace71_1_1.value }, + NULL, +}; +static const nir_search_expression replace71 = { + { nir_search_value_expression, -3 }, + false, + nir_op_iadd, + { &replace71_0.value, &replace71_1.value }, + NULL, +}; + +static const nir_search_variable search72_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search72_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search72_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_imul, + { &search72_0_0.value, &search72_0_1.value }, + NULL, +}; + +static const nir_search_variable search72_1 = { + { nir_search_value_variable, 32 }, + 2, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search72 = { + { nir_search_value_expression, -2 }, + false, + nir_op_ishl, + { &search72_0.value, &search72_1.value }, + NULL, +}; + +static const nir_search_variable replace72_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace72_1_0 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace72_1_1 = { + { nir_search_value_variable, 32 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace72_1 = { + { nir_search_value_expression, -2 }, + false, + nir_op_ishl, + { &replace72_1_0.value, &replace72_1_1.value }, + NULL, +}; +static const nir_search_expression replace72 = { + { nir_search_value_expression, -2 }, + false, + nir_op_imul, + { &replace72_0.value, &replace72_1.value }, + NULL, +}; + +static const nir_search_variable search73_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search73_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search73_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search73_0_0.value, &search73_0_1.value }, + NULL, +}; +static const nir_search_expression search73 = { + { nir_search_value_expression, 1 }, + true, + nir_op_inot, + { &search73_0.value }, + NULL, +}; + +static const nir_search_variable replace73_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace73_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace73 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &replace73_0.value, &replace73_1.value }, + NULL, +}; + +static const nir_search_variable search74_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search74_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search74_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search74_0_0.value, &search74_0_1.value }, + NULL, +}; +static const nir_search_expression search74 = { + { nir_search_value_expression, 1 }, + true, + nir_op_inot, + { &search74_0.value }, + NULL, +}; + +static const nir_search_variable replace74_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace74_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace74 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &replace74_0.value, &replace74_1.value }, + NULL, +}; + +static const nir_search_variable search75_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search75_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search75_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &search75_0_0.value, &search75_0_1.value }, + NULL, +}; +static const nir_search_expression search75 = { + { nir_search_value_expression, 1 }, + true, + nir_op_inot, + { &search75_0.value }, + NULL, +}; + +static const nir_search_variable replace75_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace75_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace75 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &replace75_0.value, &replace75_1.value }, + NULL, +}; + +static const nir_search_variable search76_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search76_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search76_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &search76_0_0.value, &search76_0_1.value }, + NULL, +}; +static const nir_search_expression search76 = { + { nir_search_value_expression, 1 }, + true, + nir_op_inot, + { &search76_0.value }, + NULL, +}; + +static const nir_search_variable replace76_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace76_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace76 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &replace76_0.value, &replace76_1.value }, + NULL, +}; + +static const nir_search_variable search77_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search77_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search77_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &search77_0_0.value, &search77_0_1.value }, + NULL, +}; +static const nir_search_expression search77 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &search77_0.value }, + NULL, +}; + +static const nir_search_variable replace77_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace77_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace77 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &replace77_0.value, &replace77_1.value }, + NULL, +}; + +static const nir_search_variable search78_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search78_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search78_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &search78_0_0.value, &search78_0_1.value }, + NULL, +}; +static const nir_search_expression search78 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &search78_0.value }, + NULL, +}; + +static const nir_search_variable replace78_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace78_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace78 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &replace78_0.value, &replace78_1.value }, + NULL, +}; + +static const nir_search_variable search79_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search79_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search79_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &search79_0_0.value, &search79_0_1.value }, + NULL, +}; +static const nir_search_expression search79 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &search79_0.value }, + NULL, +}; + +static const nir_search_variable replace79_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace79_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace79 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &replace79_0.value, &replace79_1.value }, + NULL, +}; + +static const nir_search_variable search80_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search80_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search80_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &search80_0_0.value, &search80_0_1.value }, + NULL, +}; +static const nir_search_expression search80 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &search80_0.value }, + NULL, +}; + +static const nir_search_variable replace80_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace80_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace80 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &replace80_0.value, &replace80_1.value }, + NULL, +}; + +static const nir_search_variable search81_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search81_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search81_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ieq, + { &search81_0_0.value, &search81_0_1.value }, + NULL, +}; +static const nir_search_expression search81 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &search81_0.value }, + NULL, +}; + +static const nir_search_variable replace81_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace81_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace81 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ine, + { &replace81_0.value, &replace81_1.value }, + NULL, +}; + +static const nir_search_variable search82_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search82_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search82_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ine, + { &search82_0_0.value, &search82_0_1.value }, + NULL, +}; +static const nir_search_expression search82 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &search82_0.value }, + NULL, +}; + +static const nir_search_variable replace82_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace82_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace82 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ieq, + { &replace82_0.value, &replace82_1.value }, + NULL, +}; + +static const nir_search_constant search83_0 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; + +static const nir_search_variable search83_1_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search83_1 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search83_1_0.value }, + NULL, +}; +static const nir_search_expression search83 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search83_0.value, &search83_1.value }, + NULL, +}; + +static const nir_search_variable replace83_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace83 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &replace83_0.value }, + NULL, +}; + +static const nir_search_variable search84_0_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search84_0_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search84_0_0_0.value }, + NULL, +}; +static const nir_search_expression search84_0 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fneg, + { &search84_0_0.value }, + NULL, +}; + +static const nir_search_constant search84_1 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search84 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search84_0.value, &search84_1.value }, + NULL, +}; + +static const nir_search_variable replace84_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace84 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &replace84_0.value }, + NULL, +}; + +static const nir_search_variable search85_0_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search85_0_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search85_0_0_0.value }, + NULL, +}; + +static const nir_search_variable search85_0_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search85_0_1 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search85_0_1_0.value }, + NULL, +}; +static const nir_search_expression search85_0 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fadd, + { &search85_0_0.value, &search85_0_1.value }, + NULL, +}; + +static const nir_search_constant search85_1 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search85 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &search85_0.value, &search85_1.value }, + NULL, +}; + +static const nir_search_variable replace85_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace85_1 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace85 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &replace85_0.value, &replace85_1.value }, + NULL, +}; + +static const nir_search_variable search86_0_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search86_0_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search86_0_0_0.value }, + NULL, +}; + +static const nir_search_variable search86_0_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search86_0_1 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search86_0_1_0.value }, + NULL, +}; +static const nir_search_expression search86_0 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fmax, + { &search86_0_0.value, &search86_0_1.value }, + NULL, +}; + +static const nir_search_constant search86_1 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search86 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &search86_0.value, &search86_1.value }, + NULL, +}; + +static const nir_search_variable replace86_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace86_1 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace86 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &replace86_0.value, &replace86_1.value }, + NULL, +}; + +static const nir_search_variable search87_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search87_0_1 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x3ff0000000000000 /* 1.0 */ }, +}; + +static const nir_search_variable search87_0_2_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search87_0_2 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search87_0_2_0.value }, + NULL, +}; +static const nir_search_expression search87_0 = { + { nir_search_value_expression, 0 }, + false, + nir_op_bcsel, + { &search87_0_0.value, &search87_0_1.value, &search87_0_2.value }, + NULL, +}; + +static const nir_search_constant search87_1 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search87 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &search87_0.value, &search87_1.value }, + NULL, +}; + +static const nir_search_variable replace87_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace87_1 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace87 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &replace87_0.value, &replace87_1.value }, + NULL, +}; + +static const nir_search_variable search88_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search88_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search88_0_0.value }, + NULL, +}; + +static const nir_search_variable search88_1_0_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search88_1_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search88_1_0_0.value }, + NULL, +}; +static const nir_search_expression search88_1 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fneg, + { &search88_1_0.value }, + NULL, +}; +static const nir_search_expression search88 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &search88_0.value, &search88_1.value }, + NULL, +}; + +static const nir_search_variable replace88_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace88_1 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace88 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &replace88_0.value, &replace88_1.value }, + NULL, +}; + +static const nir_search_variable search89_0_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search89_0_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search89_0_0_0.value }, + NULL, +}; + +static const nir_search_variable search89_0_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search89_0_1 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search89_0_1_0.value }, + NULL, +}; +static const nir_search_expression search89_0 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fmul, + { &search89_0_0.value, &search89_0_1.value }, + NULL, +}; + +static const nir_search_constant search89_1 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search89 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &search89_0.value, &search89_1.value }, + NULL, +}; + +static const nir_search_variable replace89_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace89_1 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace89 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &replace89_0.value, &replace89_1.value }, + NULL, +}; + +static const nir_search_variable search90_0_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search90_0_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search90_0_0_0.value }, + NULL, +}; + +static const nir_search_variable search90_0_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search90_0_1 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search90_0_1_0.value }, + NULL, +}; +static const nir_search_expression search90_0 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fmin, + { &search90_0_0.value, &search90_0_1.value }, + NULL, +}; + +static const nir_search_constant search90_1 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search90 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &search90_0.value, &search90_1.value }, + NULL, +}; + +static const nir_search_variable replace90_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace90_1 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace90 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &replace90_0.value, &replace90_1.value }, + NULL, +}; + +static const nir_search_variable search91_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search91_0_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search91_0_1 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search91_0_1_0.value }, + NULL, +}; + +static const nir_search_constant search91_0_2 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search91_0 = { + { nir_search_value_expression, 0 }, + false, + nir_op_bcsel, + { &search91_0_0.value, &search91_0_1.value, &search91_0_2.value }, + NULL, +}; + +static const nir_search_constant search91_1 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search91 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &search91_0.value, &search91_1.value }, + NULL, +}; + +static const nir_search_variable replace91_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace91_1 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace91 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &replace91_0.value, &replace91_1.value }, + NULL, +}; + +static const nir_search_variable search92_0_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search92_0_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search92_0_0_0.value }, + NULL, +}; + +static const nir_search_variable search92_0_1_0_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search92_0_1_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search92_0_1_0_0.value }, + NULL, +}; +static const nir_search_expression search92_0_1 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fneg, + { &search92_0_1_0.value }, + NULL, +}; +static const nir_search_expression search92_0 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fadd, + { &search92_0_0.value, &search92_0_1.value }, + NULL, +}; + +static const nir_search_constant search92_1 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search92 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &search92_0.value, &search92_1.value }, + NULL, +}; + +static const nir_search_variable replace92_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace92_1 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace92 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ixor, + { &replace92_0.value, &replace92_1.value }, + NULL, +}; + +static const nir_search_variable search93_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search93_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search93_0_0.value }, + NULL, +}; + +static const nir_search_variable search93_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search93_1 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search93_1_0.value }, + NULL, +}; +static const nir_search_expression search93 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &search93_0.value, &search93_1.value }, + NULL, +}; + +static const nir_search_variable replace93_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace93_1 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace93 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ixor, + { &replace93_0.value, &replace93_1.value }, + NULL, +}; + +static const nir_search_variable search94_0_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search94_0_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search94_0_0_0.value }, + NULL, +}; +static const nir_search_expression search94_0 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fneg, + { &search94_0_0.value }, + NULL, +}; + +static const nir_search_variable search94_1_0_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search94_1_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search94_1_0_0.value }, + NULL, +}; +static const nir_search_expression search94_1 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fneg, + { &search94_1_0.value }, + NULL, +}; +static const nir_search_expression search94 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &search94_0.value, &search94_1.value }, + NULL, +}; + +static const nir_search_variable replace94_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace94_1 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace94 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ixor, + { &replace94_0.value, &replace94_1.value }, + NULL, +}; + +static const nir_search_variable search95_0_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search95_0_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search95_0_0_0.value }, + NULL, +}; + +static const nir_search_variable search95_0_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search95_0_1 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search95_0_1_0.value }, + NULL, +}; +static const nir_search_expression search95_0 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fadd, + { &search95_0_0.value, &search95_0_1.value }, + NULL, +}; + +static const nir_search_constant search95_1 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search95 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &search95_0.value, &search95_1.value }, + NULL, +}; + +static const nir_search_variable replace95_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace95_0_1 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace95_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &replace95_0_0.value, &replace95_0_1.value }, + NULL, +}; +static const nir_search_expression replace95 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &replace95_0.value }, + NULL, +}; + +static const nir_search_variable search96_0_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search96_0_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search96_0_0_0.value }, + NULL, +}; + +static const nir_search_variable search96_0_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search96_0_1 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search96_0_1_0.value }, + NULL, +}; +static const nir_search_expression search96_0 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fmax, + { &search96_0_0.value, &search96_0_1.value }, + NULL, +}; + +static const nir_search_constant search96_1 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search96 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &search96_0.value, &search96_1.value }, + NULL, +}; + +static const nir_search_variable replace96_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace96_0_1 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace96_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &replace96_0_0.value, &replace96_0_1.value }, + NULL, +}; +static const nir_search_expression replace96 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &replace96_0.value }, + NULL, +}; + +static const nir_search_variable search97_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search97_0_1 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x3ff0000000000000 /* 1.0 */ }, +}; + +static const nir_search_variable search97_0_2_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search97_0_2 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search97_0_2_0.value }, + NULL, +}; +static const nir_search_expression search97_0 = { + { nir_search_value_expression, 0 }, + false, + nir_op_bcsel, + { &search97_0_0.value, &search97_0_1.value, &search97_0_2.value }, + NULL, +}; + +static const nir_search_constant search97_1 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search97 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &search97_0.value, &search97_1.value }, + NULL, +}; + +static const nir_search_variable replace97_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace97_0_1 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace97_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &replace97_0_0.value, &replace97_0_1.value }, + NULL, +}; +static const nir_search_expression replace97 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &replace97_0.value }, + NULL, +}; + +static const nir_search_variable search98_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search98_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search98_0_0.value }, + NULL, +}; + +static const nir_search_variable search98_1_0_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search98_1_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search98_1_0_0.value }, + NULL, +}; +static const nir_search_expression search98_1 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fneg, + { &search98_1_0.value }, + NULL, +}; +static const nir_search_expression search98 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &search98_0.value, &search98_1.value }, + NULL, +}; + +static const nir_search_variable replace98_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace98_0_1 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace98_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &replace98_0_0.value, &replace98_0_1.value }, + NULL, +}; +static const nir_search_expression replace98 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &replace98_0.value }, + NULL, +}; + +static const nir_search_variable search99_0_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search99_0_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search99_0_0_0.value }, + NULL, +}; + +static const nir_search_variable search99_0_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search99_0_1 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search99_0_1_0.value }, + NULL, +}; +static const nir_search_expression search99_0 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fmul, + { &search99_0_0.value, &search99_0_1.value }, + NULL, +}; + +static const nir_search_constant search99_1 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search99 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &search99_0.value, &search99_1.value }, + NULL, +}; + +static const nir_search_variable replace99_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace99_0_1 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace99_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &replace99_0_0.value, &replace99_0_1.value }, + NULL, +}; +static const nir_search_expression replace99 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &replace99_0.value }, + NULL, +}; + +static const nir_search_variable search100_0_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search100_0_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search100_0_0_0.value }, + NULL, +}; + +static const nir_search_variable search100_0_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search100_0_1 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search100_0_1_0.value }, + NULL, +}; +static const nir_search_expression search100_0 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fmin, + { &search100_0_0.value, &search100_0_1.value }, + NULL, +}; + +static const nir_search_constant search100_1 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search100 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &search100_0.value, &search100_1.value }, + NULL, +}; + +static const nir_search_variable replace100_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace100_0_1 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace100_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &replace100_0_0.value, &replace100_0_1.value }, + NULL, +}; +static const nir_search_expression replace100 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &replace100_0.value }, + NULL, +}; + +static const nir_search_variable search101_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search101_0_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search101_0_1 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search101_0_1_0.value }, + NULL, +}; + +static const nir_search_constant search101_0_2 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search101_0 = { + { nir_search_value_expression, 0 }, + false, + nir_op_bcsel, + { &search101_0_0.value, &search101_0_1.value, &search101_0_2.value }, + NULL, +}; + +static const nir_search_constant search101_1 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search101 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &search101_0.value, &search101_1.value }, + NULL, +}; + +static const nir_search_variable replace101_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace101_0_1 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace101_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &replace101_0_0.value, &replace101_0_1.value }, + NULL, +}; +static const nir_search_expression replace101 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &replace101_0.value }, + NULL, +}; + +static const nir_search_variable search102_0_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search102_0_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search102_0_0_0.value }, + NULL, +}; + +static const nir_search_variable search102_0_1_0_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search102_0_1_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search102_0_1_0_0.value }, + NULL, +}; +static const nir_search_expression search102_0_1 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fneg, + { &search102_0_1_0.value }, + NULL, +}; +static const nir_search_expression search102_0 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fadd, + { &search102_0_0.value, &search102_0_1.value }, + NULL, +}; + +static const nir_search_constant search102_1 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search102 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &search102_0.value, &search102_1.value }, + NULL, +}; + +static const nir_search_variable replace102_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace102_1 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace102 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ieq, + { &replace102_0.value, &replace102_1.value }, + NULL, +}; + +static const nir_search_variable search103_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search103_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search103_0_0.value }, + NULL, +}; + +static const nir_search_variable search103_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search103_1 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search103_1_0.value }, + NULL, +}; +static const nir_search_expression search103 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &search103_0.value, &search103_1.value }, + NULL, +}; + +static const nir_search_variable replace103_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace103_1 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace103 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ieq, + { &replace103_0.value, &replace103_1.value }, + NULL, +}; + +static const nir_search_variable search104_0_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search104_0_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search104_0_0_0.value }, + NULL, +}; +static const nir_search_expression search104_0 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fneg, + { &search104_0_0.value }, + NULL, +}; + +static const nir_search_variable search104_1_0_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search104_1_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search104_1_0_0.value }, + NULL, +}; +static const nir_search_expression search104_1 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fneg, + { &search104_1_0.value }, + NULL, +}; +static const nir_search_expression search104 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &search104_0.value, &search104_1.value }, + NULL, +}; + +static const nir_search_variable replace104_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace104_1 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace104 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ieq, + { &replace104_0.value, &replace104_1.value }, + NULL, +}; + +static const nir_search_variable search105_0_0_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search105_0_0_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search105_0_0_0_0.value }, + NULL, +}; + +static const nir_search_variable search105_0_0_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search105_0_0_1 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search105_0_0_1_0.value }, + NULL, +}; +static const nir_search_expression search105_0_0 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fadd, + { &search105_0_0_0.value, &search105_0_0_1.value }, + NULL, +}; +static const nir_search_expression search105_0 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fneg, + { &search105_0_0.value }, + NULL, +}; + +static const nir_search_constant search105_1 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search105 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search105_0.value, &search105_1.value }, + NULL, +}; + +static const nir_search_variable replace105_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace105_1 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace105 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &replace105_0.value, &replace105_1.value }, + NULL, +}; + +static const nir_search_constant search106_0 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; + +static const nir_search_variable search106_1_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search106_1_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search106_1_0_0.value }, + NULL, +}; + +static const nir_search_variable search106_1_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search106_1_1 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search106_1_1_0.value }, + NULL, +}; +static const nir_search_expression search106_1 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fadd, + { &search106_1_0.value, &search106_1_1.value }, + NULL, +}; +static const nir_search_expression search106 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search106_0.value, &search106_1.value }, + NULL, +}; + +static const nir_search_variable replace106_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace106_1 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace106 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &replace106_0.value, &replace106_1.value }, + NULL, +}; + +static const nir_search_variable search107_0_0_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search107_0_0_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search107_0_0_0_0.value }, + NULL, +}; + +static const nir_search_variable search107_0_0_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search107_0_0_1 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search107_0_0_1_0.value }, + NULL, +}; +static const nir_search_expression search107_0_0 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fadd, + { &search107_0_0_0.value, &search107_0_0_1.value }, + NULL, +}; +static const nir_search_expression search107_0 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fneg, + { &search107_0_0.value }, + NULL, +}; + +static const nir_search_constant search107_1 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search107 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search107_0.value, &search107_1.value }, + NULL, +}; + +static const nir_search_variable replace107_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace107_0_1 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace107_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &replace107_0_0.value, &replace107_0_1.value }, + NULL, +}; +static const nir_search_expression replace107 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &replace107_0.value }, + NULL, +}; + +static const nir_search_constant search108_0 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; + +static const nir_search_variable search108_1_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search108_1_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search108_1_0_0.value }, + NULL, +}; + +static const nir_search_variable search108_1_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search108_1_1 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search108_1_1_0.value }, + NULL, +}; +static const nir_search_expression search108_1 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fadd, + { &search108_1_0.value, &search108_1_1.value }, + NULL, +}; +static const nir_search_expression search108 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search108_0.value, &search108_1.value }, + NULL, +}; + +static const nir_search_variable replace108_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace108_0_1 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace108_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &replace108_0_0.value, &replace108_0_1.value }, + NULL, +}; +static const nir_search_expression replace108 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &replace108_0.value }, + NULL, +}; + +static const nir_search_variable search109_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search109_0_1_0_0_0 = { + { nir_search_value_variable, 1 }, + 1, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search109_0_1_0_0 = { + { nir_search_value_expression, -1 }, + false, + nir_search_op_b2f, + { &search109_0_1_0_0_0.value }, + NULL, +}; + +static const nir_search_variable search109_0_1_0_1_0 = { + { nir_search_value_variable, 1 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search109_0_1_0_1 = { + { nir_search_value_expression, -1 }, + false, + nir_search_op_b2f, + { &search109_0_1_0_1_0.value }, + NULL, +}; +static const nir_search_expression search109_0_1_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fadd, + { &search109_0_1_0_0.value, &search109_0_1_0_1.value }, + NULL, +}; +static const nir_search_expression search109_0_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fneg, + { &search109_0_1_0.value }, + NULL, +}; +static const nir_search_expression search109_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmin, + { &search109_0_0.value, &search109_0_1.value }, + NULL, +}; + +static const nir_search_constant search109_1 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search109 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search109_0.value, &search109_1.value }, + NULL, +}; + +static const nir_search_variable replace109_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace109_0_1 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression replace109_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &replace109_0_0.value, &replace109_0_1.value }, + NULL, +}; + +static const nir_search_variable replace109_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace109_1_1 = { + { nir_search_value_variable, 1 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace109_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &replace109_1_0.value, &replace109_1_1.value }, + NULL, +}; +static const nir_search_expression replace109 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &replace109_0.value, &replace109_1.value }, + NULL, +}; + +static const nir_search_variable search110_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search110_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search110_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fadd, + { &search110_0_0.value, &search110_0_1.value }, + NULL, +}; + +static const nir_search_variable search110_1 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search110 = { + { nir_search_value_expression, 1 }, + true, + nir_op_flt, + { &search110_0.value, &search110_1.value }, + NULL, +}; + +static const nir_search_variable replace110_0 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace110_1 = { + { nir_search_value_constant, -2 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression replace110 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &replace110_0.value, &replace110_1.value }, + NULL, +}; + +static const nir_search_variable search111_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search111_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search111_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fadd, + { &search111_0_0.value, &search111_0_1.value }, + NULL, +}; + +static const nir_search_variable search111_1 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search111 = { + { nir_search_value_expression, 1 }, + true, + nir_op_fge, + { &search111_0.value, &search111_1.value }, + NULL, +}; + +static const nir_search_variable replace111_0 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace111_1 = { + { nir_search_value_constant, -2 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression replace111 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &replace111_0.value, &replace111_1.value }, + NULL, +}; + +static const nir_search_variable search112_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search112_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search112_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fadd, + { &search112_0_0.value, &search112_0_1.value }, + NULL, +}; + +static const nir_search_variable search112_1 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search112 = { + { nir_search_value_expression, 1 }, + true, + nir_op_feq, + { &search112_0.value, &search112_1.value }, + NULL, +}; + +static const nir_search_variable replace112_0 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace112_1 = { + { nir_search_value_constant, -2 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression replace112 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &replace112_0.value, &replace112_1.value }, + NULL, +}; + +static const nir_search_variable search113_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search113_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search113_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fadd, + { &search113_0_0.value, &search113_0_1.value }, + NULL, +}; + +static const nir_search_variable search113_1 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search113 = { + { nir_search_value_expression, 1 }, + true, + nir_op_fne, + { &search113_0.value, &search113_1.value }, + NULL, +}; + +static const nir_search_variable replace113_0 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace113_1 = { + { nir_search_value_constant, -2 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression replace113 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &replace113_0.value, &replace113_1.value }, + NULL, +}; + +static const nir_search_variable search114_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search114_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search114_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_iadd, + { &search114_0_0.value, &search114_0_1.value }, + NULL, +}; + +static const nir_search_variable search114_1 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search114 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ieq, + { &search114_0.value, &search114_1.value }, + NULL, +}; + +static const nir_search_variable replace114_0 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace114_1 = { + { nir_search_value_constant, -2 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression replace114 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ieq, + { &replace114_0.value, &replace114_1.value }, + NULL, +}; + +static const nir_search_variable search115_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search115_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search115_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_iadd, + { &search115_0_0.value, &search115_0_1.value }, + NULL, +}; + +static const nir_search_variable search115_1 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search115 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ine, + { &search115_0.value, &search115_1.value }, + NULL, +}; + +static const nir_search_variable replace115_0 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace115_1 = { + { nir_search_value_constant, -2 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression replace115 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ine, + { &replace115_0.value, &replace115_1.value }, + NULL, +}; + +static const nir_search_variable search116_0_0_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search116_0_0_0 = { + { nir_search_value_expression, 1 }, + false, + nir_search_op_b2f, + { &search116_0_0_0_0.value }, + NULL, +}; +static const nir_search_expression search116_0_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fneg, + { &search116_0_0_0.value }, + NULL, +}; + +static const nir_search_variable search116_0_1 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search116_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fmin, + { &search116_0_0.value, &search116_0_1.value }, + NULL, +}; + +static const nir_search_constant search116_1 = { + { nir_search_value_constant, 1 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search116 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search116_0.value, &search116_1.value }, + NULL, +}; + +static const nir_search_variable replace116_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace116_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &replace116_0_0.value }, + NULL, +}; + +static const nir_search_variable replace116_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace116_1_1 = { + { nir_search_value_constant, 1 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression replace116_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &replace116_1_0.value, &replace116_1_1.value }, + NULL, +}; +static const nir_search_expression replace116 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &replace116_0.value, &replace116_1.value }, + NULL, +}; + +static const nir_search_variable search117_0_0_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search117_0_0_0 = { + { nir_search_value_expression, 1 }, + false, + nir_search_op_b2f, + { &search117_0_0_0_0.value }, + NULL, +}; +static const nir_search_expression search117_0_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fneg, + { &search117_0_0_0.value }, + NULL, +}; + +static const nir_search_variable search117_0_1 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search117_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fmin, + { &search117_0_0.value, &search117_0_1.value }, + NULL, +}; + +static const nir_search_constant search117_1 = { + { nir_search_value_constant, 1 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search117 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &search117_0.value, &search117_1.value }, + NULL, +}; + +static const nir_search_variable replace117_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace117_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &replace117_0_0.value }, + NULL, +}; + +static const nir_search_variable replace117_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace117_1_1 = { + { nir_search_value_constant, 1 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression replace117_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &replace117_1_0.value, &replace117_1_1.value }, + NULL, +}; +static const nir_search_expression replace117 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &replace117_0.value, &replace117_1.value }, + NULL, +}; + +static const nir_search_variable search118_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search118_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search118_0_0.value }, + NULL, +}; + +static const nir_search_constant search118_1 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search118 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &search118_0.value, &search118_1.value }, + NULL, +}; + +static const nir_search_variable replace118_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace118 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &replace118_0.value }, + NULL, +}; + +static const nir_search_variable search119_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search119_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search119_0_0.value }, + NULL, +}; + +static const nir_search_constant search119_1 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search119 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &search119_0.value, &search119_1.value }, + NULL, +}; + +static const nir_search_variable replace119 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search120_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search120_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2i, + { &search120_0_0.value }, + NULL, +}; + +static const nir_search_constant search120_1 = { + { nir_search_value_constant, 0 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression search120 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ieq, + { &search120_0.value, &search120_1.value }, + NULL, +}; + +static const nir_search_variable replace120_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace120 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &replace120_0.value }, + NULL, +}; + +static const nir_search_variable search121_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search121_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2i, + { &search121_0_0.value }, + NULL, +}; + +static const nir_search_constant search121_1 = { + { nir_search_value_constant, 0 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression search121 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ine, + { &search121_0.value, &search121_1.value }, + NULL, +}; + +static const nir_search_variable replace121 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search122_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search122_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_u2f, + { &search122_0_0.value }, + NULL, +}; + +static const nir_search_constant search122_1 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search122 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &search122_0.value, &search122_1.value }, + NULL, +}; + +static const nir_search_variable replace122_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace122_1 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression replace122 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ine, + { &replace122_0.value, &replace122_1.value }, + NULL, +}; + +static const nir_search_variable search123_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search123_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_u2f, + { &search123_0_0.value }, + NULL, +}; + +static const nir_search_constant search123_1 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search123 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &search123_0.value, &search123_1.value }, + NULL, +}; + +static const nir_search_variable replace123_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace123_1 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression replace123 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ieq, + { &replace123_0.value, &replace123_1.value }, + NULL, +}; + +static const nir_search_variable search124_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search124_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_u2f, + { &search124_0_0.value }, + NULL, +}; + +static const nir_search_constant search124_1 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search124 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search124_0.value, &search124_1.value }, + NULL, +}; + +static const nir_search_constant replace124 = { + { nir_search_value_constant, 1 }, + nir_type_bool, { NIR_TRUE /* True */ }, +}; + +static const nir_search_constant search125_0 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; + +static const nir_search_variable search125_1_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search125_1 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_u2f, + { &search125_1_0.value }, + NULL, +}; +static const nir_search_expression search125 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search125_0.value, &search125_1.value }, + NULL, +}; + +static const nir_search_constant replace125_0 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0x0 /* 0 */ }, +}; + +static const nir_search_variable replace125_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace125 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &replace125_0.value, &replace125_1.value }, + NULL, +}; + +static const nir_search_variable search126_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search126_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_u2f, + { &search126_0_0.value }, + NULL, +}; + +static const nir_search_constant search126_1 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search126 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search126_0.value, &search126_1.value }, + NULL, +}; + +static const nir_search_constant replace126 = { + { nir_search_value_constant, 1 }, + nir_type_bool, { NIR_FALSE /* False */ }, +}; + +static const nir_search_constant search127_0 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; + +static const nir_search_variable search127_1_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search127_1 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_u2f, + { &search127_1_0.value }, + NULL, +}; +static const nir_search_expression search127 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search127_0.value, &search127_1.value }, + NULL, +}; + +static const nir_search_constant replace127_0 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0x0 /* 0 */ }, +}; + +static const nir_search_variable replace127_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace127 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &replace127_0.value, &replace127_1.value }, + NULL, +}; + +static const nir_search_variable search128_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search128_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_i2f, + { &search128_0_0.value }, + NULL, +}; + +static const nir_search_constant search128_1 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search128 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &search128_0.value, &search128_1.value }, + NULL, +}; + +static const nir_search_variable replace128_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace128_1 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression replace128 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ine, + { &replace128_0.value, &replace128_1.value }, + NULL, +}; + +static const nir_search_variable search129_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search129_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_i2f, + { &search129_0_0.value }, + NULL, +}; + +static const nir_search_constant search129_1 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search129 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &search129_0.value, &search129_1.value }, + NULL, +}; + +static const nir_search_variable replace129_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace129_1 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression replace129 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ieq, + { &replace129_0.value, &replace129_1.value }, + NULL, +}; + +static const nir_search_variable search130_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search130_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_i2f, + { &search130_0_0.value }, + NULL, +}; + +static const nir_search_constant search130_1 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search130 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search130_0.value, &search130_1.value }, + NULL, +}; + +static const nir_search_variable replace130_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace130_1 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression replace130 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &replace130_0.value, &replace130_1.value }, + NULL, +}; + +static const nir_search_constant search131_0 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; + +static const nir_search_variable search131_1_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search131_1 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_i2f, + { &search131_1_0.value }, + NULL, +}; +static const nir_search_expression search131 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search131_0.value, &search131_1.value }, + NULL, +}; + +static const nir_search_constant replace131_0 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0x0 /* 0 */ }, +}; + +static const nir_search_variable replace131_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace131 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &replace131_0.value, &replace131_1.value }, + NULL, +}; + +static const nir_search_variable search132_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search132_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_i2f, + { &search132_0_0.value }, + NULL, +}; + +static const nir_search_constant search132_1 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search132 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search132_0.value, &search132_1.value }, + NULL, +}; + +static const nir_search_variable replace132_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace132_1 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression replace132 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &replace132_0.value, &replace132_1.value }, + NULL, +}; + +static const nir_search_constant search133_0 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; + +static const nir_search_variable search133_1_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search133_1 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_i2f, + { &search133_1_0.value }, + NULL, +}; +static const nir_search_expression search133 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search133_0.value, &search133_1.value }, + NULL, +}; + +static const nir_search_constant replace133_0 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0x0 /* 0 */ }, +}; + +static const nir_search_variable replace133_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace133 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &replace133_0.value, &replace133_1.value }, + NULL, +}; + +static const nir_search_constant search134_0 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; + +static const nir_search_variable search134_1_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search134_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fabs, + { &search134_1_0.value }, + NULL, +}; +static const nir_search_expression search134 = { + { nir_search_value_expression, 1 }, + true, + nir_op_flt, + { &search134_0.value, &search134_1.value }, + NULL, +}; + +static const nir_search_variable replace134_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace134_1 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression replace134 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &replace134_0.value, &replace134_1.value }, + NULL, +}; + +static const nir_search_variable search135_0_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search135_0_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fabs, + { &search135_0_0_0.value }, + NULL, +}; +static const nir_search_expression search135_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fneg, + { &search135_0_0.value }, + NULL, +}; + +static const nir_search_constant search135_1 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search135 = { + { nir_search_value_expression, 1 }, + true, + nir_op_flt, + { &search135_0.value, &search135_1.value }, + NULL, +}; + +static const nir_search_variable replace135_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace135_1 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression replace135 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &replace135_0.value, &replace135_1.value }, + NULL, +}; + +static const nir_search_constant search136_0 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; + +static const nir_search_variable search136_1_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search136_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fabs, + { &search136_1_0.value }, + NULL, +}; +static const nir_search_expression search136 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search136_0.value, &search136_1.value }, + NULL, +}; + +static const nir_search_variable replace136_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace136_1 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression replace136 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &replace136_0.value, &replace136_1.value }, + NULL, +}; + +static const nir_search_variable search137_0_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search137_0_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fabs, + { &search137_0_0_0.value }, + NULL, +}; +static const nir_search_expression search137_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fneg, + { &search137_0_0.value }, + NULL, +}; + +static const nir_search_constant search137_1 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search137 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search137_0.value, &search137_1.value }, + NULL, +}; + +static const nir_search_variable replace137_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace137_1 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression replace137 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &replace137_0.value, &replace137_1.value }, + NULL, +}; + +static const nir_search_variable search138_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search138_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search138_0_0.value }, + (is_used_once), +}; + +static const nir_search_variable search138_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search138_1 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search138_1_0.value }, + NULL, +}; +static const nir_search_expression search138 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fmax, + { &search138_0.value, &search138_1.value }, + NULL, +}; + +static const nir_search_variable replace138_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace138_0_1 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace138_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &replace138_0_0.value, &replace138_0_1.value }, + NULL, +}; +static const nir_search_expression replace138 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &replace138_0.value }, + NULL, +}; + +static const nir_search_variable search139_0_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search139_0_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search139_0_0_0.value }, + (is_used_once), +}; +static const nir_search_expression search139_0 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fneg, + { &search139_0_0.value }, + (is_used_once), +}; + +static const nir_search_variable search139_1_0_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search139_1_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search139_1_0_0.value }, + NULL, +}; +static const nir_search_expression search139_1 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fneg, + { &search139_1_0.value }, + NULL, +}; +static const nir_search_expression search139 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fmax, + { &search139_0.value, &search139_1.value }, + NULL, +}; + +static const nir_search_variable replace139_0_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace139_0_0_1 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace139_0_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &replace139_0_0_0.value, &replace139_0_0_1.value }, + NULL, +}; +static const nir_search_expression replace139_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &replace139_0_0.value }, + NULL, +}; +static const nir_search_expression replace139 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fneg, + { &replace139_0.value }, + NULL, +}; + +static const nir_search_variable search140_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search140_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search140_0_0.value }, + (is_used_once), +}; + +static const nir_search_variable search140_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search140_1 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search140_1_0.value }, + NULL, +}; +static const nir_search_expression search140 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fmin, + { &search140_0.value, &search140_1.value }, + NULL, +}; + +static const nir_search_variable replace140_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace140_0_1 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace140_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &replace140_0_0.value, &replace140_0_1.value }, + NULL, +}; +static const nir_search_expression replace140 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &replace140_0.value }, + NULL, +}; + +static const nir_search_variable search141_0_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search141_0_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search141_0_0_0.value }, + (is_used_once), +}; +static const nir_search_expression search141_0 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fneg, + { &search141_0_0.value }, + (is_used_once), +}; + +static const nir_search_variable search141_1_0_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search141_1_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search141_1_0_0.value }, + NULL, +}; +static const nir_search_expression search141_1 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fneg, + { &search141_1_0.value }, + NULL, +}; +static const nir_search_expression search141 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fmin, + { &search141_0.value, &search141_1.value }, + NULL, +}; + +static const nir_search_variable replace141_0_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace141_0_0_1 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace141_0_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &replace141_0_0_0.value, &replace141_0_0_1.value }, + NULL, +}; +static const nir_search_expression replace141_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &replace141_0_0.value }, + NULL, +}; +static const nir_search_expression replace141 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fneg, + { &replace141_0.value }, + NULL, +}; + +static const nir_search_variable search142_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search142_0 = { + { nir_search_value_expression, -2 }, + false, + nir_search_op_b2f, + { &search142_0_0.value }, + NULL, +}; + +static const nir_search_variable search142_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search142 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fmin, + { &search142_0.value, &search142_1.value }, + NULL, +}; + +static const nir_search_variable replace142_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace142_1_0 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace142_1_1 = { + { nir_search_value_constant, -2 }, + nir_type_float, { 0x3ff0000000000000 /* 1.0 */ }, +}; +static const nir_search_expression replace142_1 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fmin, + { &replace142_1_0.value, &replace142_1_1.value }, + NULL, +}; + +static const nir_search_variable replace142_2_0 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace142_2_1 = { + { nir_search_value_constant, -2 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression replace142_2 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fmin, + { &replace142_2_0.value, &replace142_2_1.value }, + NULL, +}; +static const nir_search_expression replace142 = { + { nir_search_value_expression, -2 }, + false, + nir_op_bcsel, + { &replace142_0.value, &replace142_1.value, &replace142_2.value }, + NULL, +}; + +static const nir_search_variable search143_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search143_0_1_0 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search143_0_1 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fneg, + { &search143_0_1_0.value }, + NULL, +}; +static const nir_search_expression search143_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fadd, + { &search143_0_0.value, &search143_0_1.value }, + (is_used_once), +}; + +static const nir_search_constant search143_1 = { + { nir_search_value_constant, -2 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search143 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search143_0.value, &search143_1.value }, + NULL, +}; + +static const nir_search_variable replace143_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace143_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace143 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &replace143_0.value, &replace143_1.value }, + NULL, +}; + +static const nir_search_variable search144_0_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search144_0_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fabs, + { &search144_0_0_0.value }, + NULL, +}; +static const nir_search_expression search144_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fneg, + { &search144_0_0.value }, + NULL, +}; + +static const nir_search_constant search144_1 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search144 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search144_0.value, &search144_1.value }, + NULL, +}; + +static const nir_search_variable replace144_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace144_1 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression replace144 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &replace144_0.value, &replace144_1.value }, + NULL, +}; + +static const nir_search_variable search145_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search145_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search145_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search145_0_0.value, &search145_0_1.value }, + NULL, +}; + +static const nir_search_variable search145_1 = { + { nir_search_value_variable, -2 }, + 0, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search145_2 = { + { nir_search_value_variable, -2 }, + 1, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search145 = { + { nir_search_value_expression, -2 }, + true, + nir_op_bcsel, + { &search145_0.value, &search145_1.value, &search145_2.value }, + NULL, +}; + +static const nir_search_variable replace145_0 = { + { nir_search_value_variable, -2 }, + 1, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace145_1 = { + { nir_search_value_variable, -2 }, + 0, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace145 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fmin, + { &replace145_0.value, &replace145_1.value }, + NULL, +}; + +static const nir_search_variable search146_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search146_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search146_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search146_0_0.value, &search146_0_1.value }, + NULL, +}; + +static const nir_search_variable search146_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search146_2 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search146 = { + { nir_search_value_expression, -2 }, + true, + nir_op_bcsel, + { &search146_0.value, &search146_1.value, &search146_2.value }, + NULL, +}; + +static const nir_search_variable replace146_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace146_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace146 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fmax, + { &replace146_0.value, &replace146_1.value }, + NULL, +}; + +static const nir_search_variable search147_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search147_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search147_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search147_0_0.value, &search147_0_1.value }, + NULL, +}; + +static const nir_search_variable search147_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search147_2 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search147 = { + { nir_search_value_expression, -2 }, + true, + nir_op_bcsel, + { &search147_0.value, &search147_1.value, &search147_2.value }, + NULL, +}; + +static const nir_search_variable replace147_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace147_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace147 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fmin, + { &replace147_0.value, &replace147_1.value }, + NULL, +}; + +static const nir_search_variable search148_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search148_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search148_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search148_0_0.value, &search148_0_1.value }, + NULL, +}; + +static const nir_search_variable search148_1 = { + { nir_search_value_variable, -2 }, + 0, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search148_2 = { + { nir_search_value_variable, -2 }, + 1, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search148 = { + { nir_search_value_expression, -2 }, + true, + nir_op_bcsel, + { &search148_0.value, &search148_1.value, &search148_2.value }, + NULL, +}; + +static const nir_search_variable replace148_0 = { + { nir_search_value_variable, -2 }, + 1, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace148_1 = { + { nir_search_value_variable, -2 }, + 0, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace148 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fmax, + { &replace148_0.value, &replace148_1.value }, + NULL, +}; + +static const nir_search_variable search149_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search149_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &search149_0_0.value }, + NULL, +}; + +static const nir_search_variable search149_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search149_2 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search149 = { + { nir_search_value_expression, -3 }, + false, + nir_op_bcsel, + { &search149_0.value, &search149_1.value, &search149_2.value }, + NULL, +}; + +static const nir_search_variable replace149_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace149_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace149_2 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace149 = { + { nir_search_value_expression, -3 }, + false, + nir_op_bcsel, + { &replace149_0.value, &replace149_1.value, &replace149_2.value }, + NULL, +}; + +static const nir_search_variable search150_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search150_1_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search150_1_1 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search150_1_2 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search150_1 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &search150_1_0.value, &search150_1_1.value, &search150_1_2.value }, + NULL, +}; + +static const nir_search_variable search150_2 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search150 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &search150_0.value, &search150_1.value, &search150_2.value }, + NULL, +}; + +static const nir_search_variable replace150_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace150_1 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace150_2 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace150 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &replace150_0.value, &replace150_1.value, &replace150_2.value }, + NULL, +}; + +static const nir_search_variable search151_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search151_1 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search151_2_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search151_2_1 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search151_2_2 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search151_2 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &search151_2_0.value, &search151_2_1.value, &search151_2_2.value }, + NULL, +}; +static const nir_search_expression search151 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &search151_0.value, &search151_1.value, &search151_2.value }, + NULL, +}; + +static const nir_search_variable replace151_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace151_1 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace151_2 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace151 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &replace151_0.value, &replace151_1.value, &replace151_2.value }, + NULL, +}; + +static const nir_search_variable search152_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search152_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search152_1_1 = { + { nir_search_value_variable, -5 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search152_1_2 = { + { nir_search_value_variable, -5 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search152_1 = { + { nir_search_value_expression, -5 }, + false, + nir_op_bcsel, + { &search152_1_0.value, &search152_1_1.value, &search152_1_2.value }, + NULL, +}; + +static const nir_search_variable search152_2_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search152_2_1 = { + { nir_search_value_variable, -5 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search152_2_2 = { + { nir_search_value_variable, -5 }, + 4, /* e */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search152_2 = { + { nir_search_value_expression, -5 }, + false, + nir_op_bcsel, + { &search152_2_0.value, &search152_2_1.value, &search152_2_2.value }, + (is_used_once), +}; +static const nir_search_expression search152 = { + { nir_search_value_expression, -5 }, + false, + nir_op_bcsel, + { &search152_0.value, &search152_1.value, &search152_2.value }, + NULL, +}; + +static const nir_search_variable replace152_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace152_1 = { + { nir_search_value_variable, -5 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace152_2_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace152_2_1 = { + { nir_search_value_variable, -5 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace152_2_2 = { + { nir_search_value_variable, -5 }, + 4, /* e */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace152_2 = { + { nir_search_value_expression, -5 }, + false, + nir_op_bcsel, + { &replace152_2_0.value, &replace152_2_1.value, &replace152_2_2.value }, + NULL, +}; +static const nir_search_expression replace152 = { + { nir_search_value_expression, -5 }, + false, + nir_op_bcsel, + { &replace152_0.value, &replace152_1.value, &replace152_2.value }, + NULL, +}; + +static const nir_search_variable search153_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search153_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search153_1_1 = { + { nir_search_value_variable, -5 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search153_1_2 = { + { nir_search_value_variable, -5 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search153_1 = { + { nir_search_value_expression, -5 }, + false, + nir_op_bcsel, + { &search153_1_0.value, &search153_1_1.value, &search153_1_2.value }, + (is_used_once), +}; + +static const nir_search_variable search153_2_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search153_2_1 = { + { nir_search_value_variable, -5 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search153_2_2 = { + { nir_search_value_variable, -5 }, + 4, /* e */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search153_2 = { + { nir_search_value_expression, -5 }, + false, + nir_op_bcsel, + { &search153_2_0.value, &search153_2_1.value, &search153_2_2.value }, + NULL, +}; +static const nir_search_expression search153 = { + { nir_search_value_expression, -5 }, + false, + nir_op_bcsel, + { &search153_0.value, &search153_1.value, &search153_2.value }, + NULL, +}; + +static const nir_search_variable replace153_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace153_1 = { + { nir_search_value_variable, -5 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace153_2_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace153_2_1 = { + { nir_search_value_variable, -5 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace153_2_2 = { + { nir_search_value_variable, -5 }, + 4, /* e */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace153_2 = { + { nir_search_value_expression, -5 }, + false, + nir_op_bcsel, + { &replace153_2_0.value, &replace153_2_1.value, &replace153_2_2.value }, + NULL, +}; +static const nir_search_expression replace153 = { + { nir_search_value_expression, -5 }, + false, + nir_op_bcsel, + { &replace153_0.value, &replace153_1.value, &replace153_2.value }, + NULL, +}; + +static const nir_search_variable search154_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search154_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search154_1_1 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search154_1_2 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search154_1 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &search154_1_0.value, &search154_1_1.value, &search154_1_2.value }, + NULL, +}; + +static const nir_search_variable search154_2_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search154_2_1 = { + { nir_search_value_variable, -4 }, + 4, /* e */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search154_2_2 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search154_2 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &search154_2_0.value, &search154_2_1.value, &search154_2_2.value }, + (is_used_once), +}; +static const nir_search_expression search154 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &search154_0.value, &search154_1.value, &search154_2.value }, + NULL, +}; + +static const nir_search_variable replace154_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace154_1_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace154_1_1 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace154_1_2 = { + { nir_search_value_variable, -4 }, + 4, /* e */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace154_1 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &replace154_1_0.value, &replace154_1_1.value, &replace154_1_2.value }, + NULL, +}; + +static const nir_search_variable replace154_2 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace154 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &replace154_0.value, &replace154_1.value, &replace154_2.value }, + NULL, +}; + +static const nir_search_variable search155_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search155_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search155_1_1 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search155_1_2 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search155_1 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &search155_1_0.value, &search155_1_1.value, &search155_1_2.value }, + (is_used_once), +}; + +static const nir_search_variable search155_2_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search155_2_1 = { + { nir_search_value_variable, -4 }, + 4, /* e */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search155_2_2 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search155_2 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &search155_2_0.value, &search155_2_1.value, &search155_2_2.value }, + NULL, +}; +static const nir_search_expression search155 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &search155_0.value, &search155_1.value, &search155_2.value }, + NULL, +}; + +static const nir_search_variable replace155_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace155_1_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace155_1_1 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace155_1_2 = { + { nir_search_value_variable, -4 }, + 4, /* e */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace155_1 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &replace155_1_0.value, &replace155_1_1.value, &replace155_1_2.value }, + NULL, +}; + +static const nir_search_variable replace155_2 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace155 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &replace155_0.value, &replace155_1.value, &replace155_2.value }, + NULL, +}; + +static const nir_search_variable search156_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search156_1 = { + { nir_search_value_constant, 1 }, + nir_type_bool, { NIR_TRUE /* True */ }, +}; + +static const nir_search_variable search156_2 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_bool, + NULL, +}; +static const nir_search_expression search156 = { + { nir_search_value_expression, 1 }, + false, + nir_op_bcsel, + { &search156_0.value, &search156_1.value, &search156_2.value }, + NULL, +}; + +static const nir_search_variable replace156_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace156_1 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace156 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &replace156_0.value, &replace156_1.value }, + NULL, +}; + +static const nir_search_variable search157_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search157_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search157 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmin, + { &search157_0.value, &search157_1.value }, + NULL, +}; + +static const nir_search_variable replace157 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search158_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search158_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search158 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmax, + { &search158_0.value, &search158_1.value }, + NULL, +}; + +static const nir_search_variable replace158 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search159_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search159_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search159 = { + { nir_search_value_expression, -1 }, + false, + nir_op_imin, + { &search159_0.value, &search159_1.value }, + NULL, +}; + +static const nir_search_variable replace159 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search160_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search160_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search160 = { + { nir_search_value_expression, -1 }, + false, + nir_op_imax, + { &search160_0.value, &search160_1.value }, + NULL, +}; + +static const nir_search_variable replace160 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search161_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search161_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search161 = { + { nir_search_value_expression, -1 }, + false, + nir_op_umin, + { &search161_0.value, &search161_1.value }, + NULL, +}; + +static const nir_search_variable replace161 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search162_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search162_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search162 = { + { nir_search_value_expression, -1 }, + false, + nir_op_umax, + { &search162_0.value, &search162_1.value }, + NULL, +}; + +static const nir_search_variable replace162 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search163_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search163_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search163_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fmax, + { &search163_0_0.value, &search163_0_1.value }, + NULL, +}; + +static const nir_search_variable search163_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search163 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fmax, + { &search163_0.value, &search163_1.value }, + NULL, +}; + +static const nir_search_variable replace163_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace163_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace163 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fmax, + { &replace163_0.value, &replace163_1.value }, + NULL, +}; + +static const nir_search_variable search164_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search164_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search164_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_umax, + { &search164_0_0.value, &search164_0_1.value }, + NULL, +}; + +static const nir_search_variable search164_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search164 = { + { nir_search_value_expression, -2 }, + false, + nir_op_umax, + { &search164_0.value, &search164_1.value }, + NULL, +}; + +static const nir_search_variable replace164_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace164_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace164 = { + { nir_search_value_expression, -2 }, + false, + nir_op_umax, + { &replace164_0.value, &replace164_1.value }, + NULL, +}; + +static const nir_search_variable search165_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search165_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search165_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_imax, + { &search165_0_0.value, &search165_0_1.value }, + NULL, +}; + +static const nir_search_variable search165_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search165 = { + { nir_search_value_expression, -2 }, + false, + nir_op_imax, + { &search165_0.value, &search165_1.value }, + NULL, +}; + +static const nir_search_variable replace165_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace165_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace165 = { + { nir_search_value_expression, -2 }, + false, + nir_op_imax, + { &replace165_0.value, &replace165_1.value }, + NULL, +}; + +static const nir_search_variable search166_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search166_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search166_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fmin, + { &search166_0_0.value, &search166_0_1.value }, + NULL, +}; + +static const nir_search_variable search166_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search166 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fmin, + { &search166_0.value, &search166_1.value }, + NULL, +}; + +static const nir_search_variable replace166_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace166_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace166 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fmin, + { &replace166_0.value, &replace166_1.value }, + NULL, +}; + +static const nir_search_variable search167_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search167_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search167_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_umin, + { &search167_0_0.value, &search167_0_1.value }, + NULL, +}; + +static const nir_search_variable search167_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search167 = { + { nir_search_value_expression, -2 }, + false, + nir_op_umin, + { &search167_0.value, &search167_1.value }, + NULL, +}; + +static const nir_search_variable replace167_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace167_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace167 = { + { nir_search_value_expression, -2 }, + false, + nir_op_umin, + { &replace167_0.value, &replace167_1.value }, + NULL, +}; + +static const nir_search_variable search168_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search168_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search168_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_imin, + { &search168_0_0.value, &search168_0_1.value }, + NULL, +}; + +static const nir_search_variable search168_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search168 = { + { nir_search_value_expression, -2 }, + false, + nir_op_imin, + { &search168_0.value, &search168_1.value }, + NULL, +}; + +static const nir_search_variable replace168_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace168_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace168 = { + { nir_search_value_expression, -2 }, + false, + nir_op_imin, + { &replace168_0.value, &replace168_1.value }, + NULL, +}; + +static const nir_search_variable search169_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search169_1_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search169_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fneg, + { &search169_1_0.value }, + NULL, +}; +static const nir_search_expression search169 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmax, + { &search169_0.value, &search169_1.value }, + NULL, +}; + +static const nir_search_variable replace169_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace169 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fabs, + { &replace169_0.value }, + NULL, +}; + +static const nir_search_variable search170_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search170_1_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search170_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_ineg, + { &search170_1_0.value }, + NULL, +}; +static const nir_search_expression search170 = { + { nir_search_value_expression, -1 }, + false, + nir_op_imax, + { &search170_0.value, &search170_1.value }, + NULL, +}; + +static const nir_search_variable replace170_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace170 = { + { nir_search_value_expression, -1 }, + false, + nir_op_iabs, + { &replace170_0.value }, + NULL, +}; + +static const nir_search_variable search171_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search171_1_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search171_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fneg, + { &search171_1_0.value }, + NULL, +}; +static const nir_search_expression search171 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmin, + { &search171_0.value, &search171_1.value }, + NULL, +}; + +static const nir_search_variable replace171_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace171_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fabs, + { &replace171_0_0.value }, + NULL, +}; +static const nir_search_expression replace171 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fneg, + { &replace171_0.value }, + NULL, +}; + +static const nir_search_variable search172_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search172_1_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search172_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_ineg, + { &search172_1_0.value }, + NULL, +}; +static const nir_search_expression search172 = { + { nir_search_value_expression, -1 }, + false, + nir_op_imin, + { &search172_0.value, &search172_1.value }, + NULL, +}; + +static const nir_search_variable replace172_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace172_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_iabs, + { &replace172_0_0.value }, + NULL, +}; +static const nir_search_expression replace172 = { + { nir_search_value_expression, -1 }, + false, + nir_op_ineg, + { &replace172_0.value }, + NULL, +}; + +static const nir_search_variable search173_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search173_1_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search173_1_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fabs, + { &search173_1_0_0.value }, + NULL, +}; +static const nir_search_expression search173_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fneg, + { &search173_1_0.value }, + NULL, +}; +static const nir_search_expression search173 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmin, + { &search173_0.value, &search173_1.value }, + NULL, +}; + +static const nir_search_variable replace173_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace173_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fabs, + { &replace173_0_0.value }, + NULL, +}; +static const nir_search_expression replace173 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fneg, + { &replace173_0.value }, + NULL, +}; + +static const nir_search_variable search174_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search174_1_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search174_1_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_iabs, + { &search174_1_0_0.value }, + NULL, +}; +static const nir_search_expression search174_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_ineg, + { &search174_1_0.value }, + NULL, +}; +static const nir_search_expression search174 = { + { nir_search_value_expression, -1 }, + false, + nir_op_imin, + { &search174_0.value, &search174_1.value }, + NULL, +}; + +static const nir_search_variable replace174_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace174_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_iabs, + { &replace174_0_0.value }, + NULL, +}; +static const nir_search_expression replace174 = { + { nir_search_value_expression, -1 }, + false, + nir_op_ineg, + { &replace174_0.value }, + NULL, +}; + +static const nir_search_variable search175_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search175_1_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search175_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fabs, + { &search175_1_0.value }, + NULL, +}; +static const nir_search_expression search175 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmin, + { &search175_0.value, &search175_1.value }, + NULL, +}; + +static const nir_search_variable replace175 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search176_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search176_1_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search176_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_iabs, + { &search176_1_0.value }, + NULL, +}; +static const nir_search_expression search176 = { + { nir_search_value_expression, -1 }, + false, + nir_op_imin, + { &search176_0.value, &search176_1.value }, + NULL, +}; + +static const nir_search_variable replace176 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search177_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search177_1_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search177_1_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fabs, + { &search177_1_0_0.value }, + NULL, +}; +static const nir_search_expression search177_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fneg, + { &search177_1_0.value }, + NULL, +}; +static const nir_search_expression search177 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmax, + { &search177_0.value, &search177_1.value }, + NULL, +}; + +static const nir_search_variable replace177 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search178_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search178_1_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search178_1_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_iabs, + { &search178_1_0_0.value }, + NULL, +}; +static const nir_search_expression search178_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_ineg, + { &search178_1_0.value }, + NULL, +}; +static const nir_search_expression search178 = { + { nir_search_value_expression, -1 }, + false, + nir_op_imax, + { &search178_0.value, &search178_1.value }, + NULL, +}; + +static const nir_search_variable replace178 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search179_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search179_1_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search179_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fabs, + { &search179_1_0.value }, + NULL, +}; +static const nir_search_expression search179 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmax, + { &search179_0.value, &search179_1.value }, + NULL, +}; + +static const nir_search_variable replace179_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace179 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fabs, + { &replace179_0.value }, + NULL, +}; + +static const nir_search_variable search180_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search180_1_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search180_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_iabs, + { &search180_1_0.value }, + NULL, +}; +static const nir_search_expression search180 = { + { nir_search_value_expression, -1 }, + false, + nir_op_imax, + { &search180_0.value, &search180_1.value }, + NULL, +}; + +static const nir_search_variable replace180_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace180 = { + { nir_search_value_expression, -1 }, + false, + nir_op_iabs, + { &replace180_0.value }, + NULL, +}; + +static const nir_search_variable search181_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search181_1_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search181_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fneg, + { &search181_1_0.value }, + NULL, +}; +static const nir_search_expression search181 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmax, + { &search181_0.value, &search181_1.value }, + NULL, +}; + +static const nir_search_variable replace181_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace181 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fabs, + { &replace181_0.value }, + NULL, +}; + +static const nir_search_variable search182_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search182_1_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search182_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_ineg, + { &search182_1_0.value }, + NULL, +}; +static const nir_search_expression search182 = { + { nir_search_value_expression, -1 }, + false, + nir_op_imax, + { &search182_0.value, &search182_1.value }, + NULL, +}; + +static const nir_search_variable replace182_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace182 = { + { nir_search_value_expression, -1 }, + false, + nir_op_iabs, + { &replace182_0.value }, + NULL, +}; + +static const nir_search_variable search183_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search183_0_1 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search183_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmax, + { &search183_0_0.value, &search183_0_1.value }, + NULL, +}; + +static const nir_search_constant search183_1 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x3ff0000000000000 /* 1.0 */ }, +}; +static const nir_search_expression search183 = { + { nir_search_value_expression, -1 }, + true, + nir_op_fmin, + { &search183_0.value, &search183_1.value }, + NULL, +}; + +static const nir_search_variable replace183_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace183 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fsat, + { &replace183_0.value }, + NULL, +}; + +static const nir_search_variable search184_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search184_0_1 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x3ff0000000000000 /* 1.0 */ }, +}; +static const nir_search_expression search184_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmin, + { &search184_0_0.value, &search184_0_1.value }, + NULL, +}; + +static const nir_search_constant search184_1 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search184 = { + { nir_search_value_expression, -1 }, + true, + nir_op_fmax, + { &search184_0.value, &search184_1.value }, + NULL, +}; + +static const nir_search_variable replace184_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace184 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fsat, + { &replace184_0.value }, + NULL, +}; + +static const nir_search_variable search185_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search185_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fsign, + { &search185_0_0.value }, + NULL, +}; +static const nir_search_expression search185 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fsat, + { &search185_0.value }, + NULL, +}; + +static const nir_search_constant replace185_0_0 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; + +static const nir_search_variable replace185_0_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace185_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &replace185_0_0.value, &replace185_0_1.value }, + NULL, +}; +static const nir_search_expression replace185 = { + { nir_search_value_expression, -1 }, + false, + nir_search_op_b2f, + { &replace185_0.value }, + NULL, +}; + +static const nir_search_variable search186_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search186 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fsat, + { &search186_0.value }, + NULL, +}; + +static const nir_search_variable replace186_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace186_0_1 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression replace186_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmax, + { &replace186_0_0.value, &replace186_0_1.value }, + NULL, +}; + +static const nir_search_constant replace186_1 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x3ff0000000000000 /* 1.0 */ }, +}; +static const nir_search_expression replace186 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmin, + { &replace186_0.value, &replace186_1.value }, + NULL, +}; + +static const nir_search_variable search187_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search187_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fsat, + { &search187_0_0.value }, + NULL, +}; +static const nir_search_expression search187 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fsat, + { &search187_0.value }, + NULL, +}; + +static const nir_search_variable replace187_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace187 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fsat, + { &replace187_0.value }, + NULL, +}; + +static const nir_search_variable search188_0_0_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search188_0_0_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search188_0_0_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fmax, + { &search188_0_0_0_0.value, &search188_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search188_0_0_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search188_0_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fmin, + { &search188_0_0_0.value, &search188_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search188_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search188_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fmax, + { &search188_0_0.value, &search188_0_1.value }, + NULL, +}; + +static const nir_search_variable search188_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search188 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fmin, + { &search188_0.value, &search188_1.value }, + NULL, +}; + +static const nir_search_variable replace188_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace188_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace188_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fmax, + { &replace188_0_0.value, &replace188_0_1.value }, + NULL, +}; + +static const nir_search_variable replace188_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace188 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fmin, + { &replace188_0.value, &replace188_1.value }, + NULL, +}; + +static const nir_search_variable search189_0_0_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search189_0_0_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search189_0_0_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_imax, + { &search189_0_0_0_0.value, &search189_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search189_0_0_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search189_0_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_imin, + { &search189_0_0_0.value, &search189_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search189_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search189_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_imax, + { &search189_0_0.value, &search189_0_1.value }, + NULL, +}; + +static const nir_search_variable search189_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search189 = { + { nir_search_value_expression, -3 }, + false, + nir_op_imin, + { &search189_0.value, &search189_1.value }, + NULL, +}; + +static const nir_search_variable replace189_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace189_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace189_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_imax, + { &replace189_0_0.value, &replace189_0_1.value }, + NULL, +}; + +static const nir_search_variable replace189_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace189 = { + { nir_search_value_expression, -3 }, + false, + nir_op_imin, + { &replace189_0.value, &replace189_1.value }, + NULL, +}; + +static const nir_search_variable search190_0_0_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search190_0_0_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search190_0_0_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_umax, + { &search190_0_0_0_0.value, &search190_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search190_0_0_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search190_0_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_umin, + { &search190_0_0_0.value, &search190_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search190_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search190_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_umax, + { &search190_0_0.value, &search190_0_1.value }, + NULL, +}; + +static const nir_search_variable search190_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search190 = { + { nir_search_value_expression, -3 }, + false, + nir_op_umin, + { &search190_0.value, &search190_1.value }, + NULL, +}; + +static const nir_search_variable replace190_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace190_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace190_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_umax, + { &replace190_0_0.value, &replace190_0_1.value }, + NULL, +}; + +static const nir_search_variable replace190_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace190 = { + { nir_search_value_expression, -3 }, + false, + nir_op_umin, + { &replace190_0.value, &replace190_1.value }, + NULL, +}; + +static const nir_search_variable search191_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search191_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fsat, + { &search191_0_0.value }, + NULL, +}; + +static const nir_search_variable search191_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + true, + nir_type_invalid, + (is_zero_to_one), +}; +static const nir_search_expression search191 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fmax, + { &search191_0.value, &search191_1.value }, + NULL, +}; + +static const nir_search_variable replace191_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace191_0_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace191_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fmax, + { &replace191_0_0.value, &replace191_0_1.value }, + NULL, +}; +static const nir_search_expression replace191 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fsat, + { &replace191_0.value }, + NULL, +}; + +static const nir_search_variable search192_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search192_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fsat, + { &search192_0_0.value }, + NULL, +}; + +static const nir_search_variable search192_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + true, + nir_type_invalid, + (is_zero_to_one), +}; +static const nir_search_expression search192 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fmin, + { &search192_0.value, &search192_1.value }, + NULL, +}; + +static const nir_search_variable replace192_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace192_0_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace192_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fmin, + { &replace192_0_0.value, &replace192_0_1.value }, + NULL, +}; +static const nir_search_expression replace192 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fsat, + { &replace192_0.value }, + NULL, +}; + +static const nir_search_variable search193_0_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search193_0_0_1 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression search193_0_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_imax, + { &search193_0_0_0.value, &search193_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search193_0_1 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0xff /* 255 */ }, +}; +static const nir_search_expression search193_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_imin, + { &search193_0_0.value, &search193_0_1.value }, + NULL, +}; + +static const nir_search_constant search193_1 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression search193 = { + { nir_search_value_expression, -1 }, + false, + nir_op_extract_u8, + { &search193_0.value, &search193_1.value }, + NULL, +}; + +static const nir_search_variable replace193_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace193_0_1 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression replace193_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_imax, + { &replace193_0_0.value, &replace193_0_1.value }, + NULL, +}; + +static const nir_search_constant replace193_1 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0xff /* 255 */ }, +}; +static const nir_search_expression replace193 = { + { nir_search_value_expression, -1 }, + false, + nir_op_imin, + { &replace193_0.value, &replace193_1.value }, + NULL, +}; + +static const nir_search_variable search194_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search194_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search194_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search194_0_0.value, &search194_0_1.value }, + (is_used_once), +}; + +static const nir_search_variable search194_1_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search194_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search194_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search194_1_0.value, &search194_1_1.value }, + NULL, +}; +static const nir_search_expression search194 = { + { nir_search_value_expression, 1 }, + true, + nir_op_ior, + { &search194_0.value, &search194_1.value }, + NULL, +}; + +static const nir_search_variable replace194_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace194_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace194_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace194_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fmax, + { &replace194_1_0.value, &replace194_1_1.value }, + NULL, +}; +static const nir_search_expression replace194 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &replace194_0.value, &replace194_1.value }, + NULL, +}; + +static const nir_search_variable search195_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search195_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search195_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search195_0_0.value, &search195_0_1.value }, + (is_used_once), +}; + +static const nir_search_variable search195_1_0 = { + { nir_search_value_variable, -2 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search195_1_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search195_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search195_1_0.value, &search195_1_1.value }, + NULL, +}; +static const nir_search_expression search195 = { + { nir_search_value_expression, 1 }, + true, + nir_op_ior, + { &search195_0.value, &search195_1.value }, + NULL, +}; + +static const nir_search_variable replace195_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace195_0_1 = { + { nir_search_value_variable, -2 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace195_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fmin, + { &replace195_0_0.value, &replace195_0_1.value }, + NULL, +}; + +static const nir_search_variable replace195_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace195 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &replace195_0.value, &replace195_1.value }, + NULL, +}; + +static const nir_search_variable search196_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search196_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search196_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search196_0_0.value, &search196_0_1.value }, + (is_used_once), +}; + +static const nir_search_variable search196_1_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search196_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search196_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search196_1_0.value, &search196_1_1.value }, + NULL, +}; +static const nir_search_expression search196 = { + { nir_search_value_expression, 1 }, + true, + nir_op_ior, + { &search196_0.value, &search196_1.value }, + NULL, +}; + +static const nir_search_variable replace196_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace196_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace196_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace196_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fmin, + { &replace196_1_0.value, &replace196_1_1.value }, + NULL, +}; +static const nir_search_expression replace196 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &replace196_0.value, &replace196_1.value }, + NULL, +}; + +static const nir_search_variable search197_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search197_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search197_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search197_0_0.value, &search197_0_1.value }, + (is_used_once), +}; + +static const nir_search_variable search197_1_0 = { + { nir_search_value_variable, -2 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search197_1_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search197_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search197_1_0.value, &search197_1_1.value }, + NULL, +}; +static const nir_search_expression search197 = { + { nir_search_value_expression, 1 }, + true, + nir_op_ior, + { &search197_0.value, &search197_1.value }, + NULL, +}; + +static const nir_search_variable replace197_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace197_0_1 = { + { nir_search_value_variable, -2 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace197_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fmax, + { &replace197_0_0.value, &replace197_0_1.value }, + NULL, +}; + +static const nir_search_variable replace197_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace197 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &replace197_0.value, &replace197_1.value }, + NULL, +}; + +static const nir_search_variable search198_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search198_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search198_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search198_0_0.value, &search198_0_1.value }, + NULL, +}; + +static const nir_search_variable search198_1_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search198_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search198_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search198_1_0.value, &search198_1_1.value }, + NULL, +}; +static const nir_search_expression search198 = { + { nir_search_value_expression, 1 }, + true, + nir_op_ior, + { &search198_0.value, &search198_1.value }, + NULL, +}; + +static const nir_search_variable replace198_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace198_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace198_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace198_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fmax, + { &replace198_1_0.value, &replace198_1_1.value }, + NULL, +}; +static const nir_search_expression replace198 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &replace198_0.value, &replace198_1.value }, + NULL, +}; + +static const nir_search_variable search199_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search199_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search199_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search199_0_0.value, &search199_0_1.value }, + NULL, +}; + +static const nir_search_variable search199_1_0 = { + { nir_search_value_variable, -2 }, + 2, /* b */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search199_1_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search199_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search199_1_0.value, &search199_1_1.value }, + NULL, +}; +static const nir_search_expression search199 = { + { nir_search_value_expression, 1 }, + true, + nir_op_ior, + { &search199_0.value, &search199_1.value }, + NULL, +}; + +static const nir_search_variable replace199_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace199_0_1 = { + { nir_search_value_variable, -2 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace199_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fmin, + { &replace199_0_0.value, &replace199_0_1.value }, + NULL, +}; + +static const nir_search_variable replace199_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace199 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &replace199_0.value, &replace199_1.value }, + NULL, +}; + +static const nir_search_variable search200_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search200_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search200_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search200_0_0.value, &search200_0_1.value }, + NULL, +}; + +static const nir_search_variable search200_1_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search200_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search200_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search200_1_0.value, &search200_1_1.value }, + NULL, +}; +static const nir_search_expression search200 = { + { nir_search_value_expression, 1 }, + true, + nir_op_ior, + { &search200_0.value, &search200_1.value }, + NULL, +}; + +static const nir_search_variable replace200_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace200_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace200_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace200_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fmin, + { &replace200_1_0.value, &replace200_1_1.value }, + NULL, +}; +static const nir_search_expression replace200 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &replace200_0.value, &replace200_1.value }, + NULL, +}; + +static const nir_search_variable search201_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search201_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search201_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search201_0_0.value, &search201_0_1.value }, + NULL, +}; + +static const nir_search_variable search201_1_0 = { + { nir_search_value_variable, -2 }, + 2, /* b */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search201_1_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search201_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search201_1_0.value, &search201_1_1.value }, + NULL, +}; +static const nir_search_expression search201 = { + { nir_search_value_expression, 1 }, + true, + nir_op_ior, + { &search201_0.value, &search201_1.value }, + NULL, +}; + +static const nir_search_variable replace201_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace201_0_1 = { + { nir_search_value_variable, -2 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace201_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fmax, + { &replace201_0_0.value, &replace201_0_1.value }, + NULL, +}; + +static const nir_search_variable replace201_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace201 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &replace201_0.value, &replace201_1.value }, + NULL, +}; + +static const nir_search_variable search202_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search202_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search202_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search202_0_0.value, &search202_0_1.value }, + (is_used_once), +}; + +static const nir_search_variable search202_1_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search202_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search202_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search202_1_0.value, &search202_1_1.value }, + NULL, +}; +static const nir_search_expression search202 = { + { nir_search_value_expression, 1 }, + true, + nir_op_iand, + { &search202_0.value, &search202_1.value }, + NULL, +}; + +static const nir_search_variable replace202_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace202_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace202_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace202_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fmin, + { &replace202_1_0.value, &replace202_1_1.value }, + NULL, +}; +static const nir_search_expression replace202 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &replace202_0.value, &replace202_1.value }, + NULL, +}; + +static const nir_search_variable search203_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search203_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search203_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search203_0_0.value, &search203_0_1.value }, + (is_used_once), +}; + +static const nir_search_variable search203_1_0 = { + { nir_search_value_variable, -2 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search203_1_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search203_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search203_1_0.value, &search203_1_1.value }, + NULL, +}; +static const nir_search_expression search203 = { + { nir_search_value_expression, 1 }, + true, + nir_op_iand, + { &search203_0.value, &search203_1.value }, + NULL, +}; + +static const nir_search_variable replace203_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace203_0_1 = { + { nir_search_value_variable, -2 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace203_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fmax, + { &replace203_0_0.value, &replace203_0_1.value }, + NULL, +}; + +static const nir_search_variable replace203_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace203 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &replace203_0.value, &replace203_1.value }, + NULL, +}; + +static const nir_search_variable search204_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search204_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search204_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search204_0_0.value, &search204_0_1.value }, + (is_used_once), +}; + +static const nir_search_variable search204_1_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search204_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search204_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search204_1_0.value, &search204_1_1.value }, + NULL, +}; +static const nir_search_expression search204 = { + { nir_search_value_expression, 1 }, + true, + nir_op_iand, + { &search204_0.value, &search204_1.value }, + NULL, +}; + +static const nir_search_variable replace204_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace204_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace204_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace204_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fmax, + { &replace204_1_0.value, &replace204_1_1.value }, + NULL, +}; +static const nir_search_expression replace204 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &replace204_0.value, &replace204_1.value }, + NULL, +}; + +static const nir_search_variable search205_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search205_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search205_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search205_0_0.value, &search205_0_1.value }, + (is_used_once), +}; + +static const nir_search_variable search205_1_0 = { + { nir_search_value_variable, -2 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search205_1_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search205_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search205_1_0.value, &search205_1_1.value }, + NULL, +}; +static const nir_search_expression search205 = { + { nir_search_value_expression, 1 }, + true, + nir_op_iand, + { &search205_0.value, &search205_1.value }, + NULL, +}; + +static const nir_search_variable replace205_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace205_0_1 = { + { nir_search_value_variable, -2 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace205_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fmin, + { &replace205_0_0.value, &replace205_0_1.value }, + NULL, +}; + +static const nir_search_variable replace205_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace205 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &replace205_0.value, &replace205_1.value }, + NULL, +}; + +static const nir_search_variable search206_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search206_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search206_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search206_0_0.value, &search206_0_1.value }, + NULL, +}; + +static const nir_search_variable search206_1_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search206_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search206_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search206_1_0.value, &search206_1_1.value }, + NULL, +}; +static const nir_search_expression search206 = { + { nir_search_value_expression, 1 }, + true, + nir_op_iand, + { &search206_0.value, &search206_1.value }, + NULL, +}; + +static const nir_search_variable replace206_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace206_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace206_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace206_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fmin, + { &replace206_1_0.value, &replace206_1_1.value }, + NULL, +}; +static const nir_search_expression replace206 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &replace206_0.value, &replace206_1.value }, + NULL, +}; + +static const nir_search_variable search207_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search207_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search207_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search207_0_0.value, &search207_0_1.value }, + NULL, +}; + +static const nir_search_variable search207_1_0 = { + { nir_search_value_variable, -2 }, + 2, /* b */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search207_1_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search207_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search207_1_0.value, &search207_1_1.value }, + NULL, +}; +static const nir_search_expression search207 = { + { nir_search_value_expression, 1 }, + true, + nir_op_iand, + { &search207_0.value, &search207_1.value }, + NULL, +}; + +static const nir_search_variable replace207_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace207_0_1 = { + { nir_search_value_variable, -2 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace207_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fmax, + { &replace207_0_0.value, &replace207_0_1.value }, + NULL, +}; + +static const nir_search_variable replace207_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace207 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &replace207_0.value, &replace207_1.value }, + NULL, +}; + +static const nir_search_variable search208_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search208_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search208_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search208_0_0.value, &search208_0_1.value }, + NULL, +}; + +static const nir_search_variable search208_1_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search208_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search208_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search208_1_0.value, &search208_1_1.value }, + NULL, +}; +static const nir_search_expression search208 = { + { nir_search_value_expression, 1 }, + true, + nir_op_iand, + { &search208_0.value, &search208_1.value }, + NULL, +}; + +static const nir_search_variable replace208_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace208_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace208_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace208_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fmax, + { &replace208_1_0.value, &replace208_1_1.value }, + NULL, +}; +static const nir_search_expression replace208 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &replace208_0.value, &replace208_1.value }, + NULL, +}; + +static const nir_search_variable search209_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search209_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search209_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search209_0_0.value, &search209_0_1.value }, + NULL, +}; + +static const nir_search_variable search209_1_0 = { + { nir_search_value_variable, -2 }, + 2, /* b */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search209_1_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search209_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search209_1_0.value, &search209_1_1.value }, + NULL, +}; +static const nir_search_expression search209 = { + { nir_search_value_expression, 1 }, + true, + nir_op_iand, + { &search209_0.value, &search209_1.value }, + NULL, +}; + +static const nir_search_variable replace209_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace209_0_1 = { + { nir_search_value_variable, -2 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace209_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fmin, + { &replace209_0_0.value, &replace209_0_1.value }, + NULL, +}; + +static const nir_search_variable replace209_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace209 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &replace209_0.value, &replace209_1.value }, + NULL, +}; + +static const nir_search_variable search210_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search210_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search210_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &search210_0_0.value, &search210_0_1.value }, + (is_used_once), +}; + +static const nir_search_variable search210_1_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search210_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search210_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &search210_1_0.value, &search210_1_1.value }, + NULL, +}; +static const nir_search_expression search210 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &search210_0.value, &search210_1.value }, + NULL, +}; + +static const nir_search_variable replace210_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace210_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace210_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace210_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_imax, + { &replace210_1_0.value, &replace210_1_1.value }, + NULL, +}; +static const nir_search_expression replace210 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &replace210_0.value, &replace210_1.value }, + NULL, +}; + +static const nir_search_variable search211_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search211_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search211_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &search211_0_0.value, &search211_0_1.value }, + (is_used_once), +}; + +static const nir_search_variable search211_1_0 = { + { nir_search_value_variable, -2 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search211_1_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search211_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &search211_1_0.value, &search211_1_1.value }, + NULL, +}; +static const nir_search_expression search211 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &search211_0.value, &search211_1.value }, + NULL, +}; + +static const nir_search_variable replace211_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace211_0_1 = { + { nir_search_value_variable, -2 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace211_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_imin, + { &replace211_0_0.value, &replace211_0_1.value }, + NULL, +}; + +static const nir_search_variable replace211_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace211 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &replace211_0.value, &replace211_1.value }, + NULL, +}; + +static const nir_search_variable search212_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search212_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search212_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &search212_0_0.value, &search212_0_1.value }, + (is_used_once), +}; + +static const nir_search_variable search212_1_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search212_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search212_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &search212_1_0.value, &search212_1_1.value }, + NULL, +}; +static const nir_search_expression search212 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &search212_0.value, &search212_1.value }, + NULL, +}; + +static const nir_search_variable replace212_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace212_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace212_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace212_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_imin, + { &replace212_1_0.value, &replace212_1_1.value }, + NULL, +}; +static const nir_search_expression replace212 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &replace212_0.value, &replace212_1.value }, + NULL, +}; + +static const nir_search_variable search213_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search213_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search213_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &search213_0_0.value, &search213_0_1.value }, + (is_used_once), +}; + +static const nir_search_variable search213_1_0 = { + { nir_search_value_variable, -2 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search213_1_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search213_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &search213_1_0.value, &search213_1_1.value }, + NULL, +}; +static const nir_search_expression search213 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &search213_0.value, &search213_1.value }, + NULL, +}; + +static const nir_search_variable replace213_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace213_0_1 = { + { nir_search_value_variable, -2 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace213_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_imax, + { &replace213_0_0.value, &replace213_0_1.value }, + NULL, +}; + +static const nir_search_variable replace213_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace213 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &replace213_0.value, &replace213_1.value }, + NULL, +}; + +static const nir_search_variable search214_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search214_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search214_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &search214_0_0.value, &search214_0_1.value }, + (is_used_once), +}; + +static const nir_search_variable search214_1_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search214_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search214_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &search214_1_0.value, &search214_1_1.value }, + NULL, +}; +static const nir_search_expression search214 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &search214_0.value, &search214_1.value }, + NULL, +}; + +static const nir_search_variable replace214_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace214_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace214_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace214_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_umax, + { &replace214_1_0.value, &replace214_1_1.value }, + NULL, +}; +static const nir_search_expression replace214 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &replace214_0.value, &replace214_1.value }, + NULL, +}; + +static const nir_search_variable search215_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search215_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search215_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &search215_0_0.value, &search215_0_1.value }, + (is_used_once), +}; + +static const nir_search_variable search215_1_0 = { + { nir_search_value_variable, -2 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search215_1_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search215_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &search215_1_0.value, &search215_1_1.value }, + NULL, +}; +static const nir_search_expression search215 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &search215_0.value, &search215_1.value }, + NULL, +}; + +static const nir_search_variable replace215_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace215_0_1 = { + { nir_search_value_variable, -2 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace215_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_umin, + { &replace215_0_0.value, &replace215_0_1.value }, + NULL, +}; + +static const nir_search_variable replace215_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace215 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &replace215_0.value, &replace215_1.value }, + NULL, +}; + +static const nir_search_variable search216_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search216_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search216_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &search216_0_0.value, &search216_0_1.value }, + (is_used_once), +}; + +static const nir_search_variable search216_1_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search216_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search216_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &search216_1_0.value, &search216_1_1.value }, + NULL, +}; +static const nir_search_expression search216 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &search216_0.value, &search216_1.value }, + NULL, +}; + +static const nir_search_variable replace216_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace216_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace216_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace216_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_umin, + { &replace216_1_0.value, &replace216_1_1.value }, + NULL, +}; +static const nir_search_expression replace216 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &replace216_0.value, &replace216_1.value }, + NULL, +}; + +static const nir_search_variable search217_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search217_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search217_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &search217_0_0.value, &search217_0_1.value }, + (is_used_once), +}; + +static const nir_search_variable search217_1_0 = { + { nir_search_value_variable, -2 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search217_1_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search217_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &search217_1_0.value, &search217_1_1.value }, + NULL, +}; +static const nir_search_expression search217 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &search217_0.value, &search217_1.value }, + NULL, +}; + +static const nir_search_variable replace217_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace217_0_1 = { + { nir_search_value_variable, -2 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace217_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_umax, + { &replace217_0_0.value, &replace217_0_1.value }, + NULL, +}; + +static const nir_search_variable replace217_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace217 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &replace217_0.value, &replace217_1.value }, + NULL, +}; + +static const nir_search_variable search218_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search218_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search218_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &search218_0_0.value, &search218_0_1.value }, + (is_used_once), +}; + +static const nir_search_variable search218_1_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search218_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search218_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &search218_1_0.value, &search218_1_1.value }, + NULL, +}; +static const nir_search_expression search218 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &search218_0.value, &search218_1.value }, + NULL, +}; + +static const nir_search_variable replace218_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace218_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace218_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace218_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_imin, + { &replace218_1_0.value, &replace218_1_1.value }, + NULL, +}; +static const nir_search_expression replace218 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &replace218_0.value, &replace218_1.value }, + NULL, +}; + +static const nir_search_variable search219_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search219_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search219_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &search219_0_0.value, &search219_0_1.value }, + (is_used_once), +}; + +static const nir_search_variable search219_1_0 = { + { nir_search_value_variable, -2 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search219_1_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search219_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &search219_1_0.value, &search219_1_1.value }, + NULL, +}; +static const nir_search_expression search219 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &search219_0.value, &search219_1.value }, + NULL, +}; + +static const nir_search_variable replace219_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace219_0_1 = { + { nir_search_value_variable, -2 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace219_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_imax, + { &replace219_0_0.value, &replace219_0_1.value }, + NULL, +}; + +static const nir_search_variable replace219_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace219 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &replace219_0.value, &replace219_1.value }, + NULL, +}; + +static const nir_search_variable search220_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search220_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search220_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &search220_0_0.value, &search220_0_1.value }, + (is_used_once), +}; + +static const nir_search_variable search220_1_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search220_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search220_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &search220_1_0.value, &search220_1_1.value }, + NULL, +}; +static const nir_search_expression search220 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &search220_0.value, &search220_1.value }, + NULL, +}; + +static const nir_search_variable replace220_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace220_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace220_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace220_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_imax, + { &replace220_1_0.value, &replace220_1_1.value }, + NULL, +}; +static const nir_search_expression replace220 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &replace220_0.value, &replace220_1.value }, + NULL, +}; + +static const nir_search_variable search221_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search221_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search221_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &search221_0_0.value, &search221_0_1.value }, + (is_used_once), +}; + +static const nir_search_variable search221_1_0 = { + { nir_search_value_variable, -2 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search221_1_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search221_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &search221_1_0.value, &search221_1_1.value }, + NULL, +}; +static const nir_search_expression search221 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &search221_0.value, &search221_1.value }, + NULL, +}; + +static const nir_search_variable replace221_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace221_0_1 = { + { nir_search_value_variable, -2 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace221_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_imin, + { &replace221_0_0.value, &replace221_0_1.value }, + NULL, +}; + +static const nir_search_variable replace221_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace221 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &replace221_0.value, &replace221_1.value }, + NULL, +}; + +static const nir_search_variable search222_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search222_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search222_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &search222_0_0.value, &search222_0_1.value }, + (is_used_once), +}; + +static const nir_search_variable search222_1_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search222_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search222_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &search222_1_0.value, &search222_1_1.value }, + NULL, +}; +static const nir_search_expression search222 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &search222_0.value, &search222_1.value }, + NULL, +}; + +static const nir_search_variable replace222_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace222_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace222_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace222_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_umin, + { &replace222_1_0.value, &replace222_1_1.value }, + NULL, +}; +static const nir_search_expression replace222 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &replace222_0.value, &replace222_1.value }, + NULL, +}; + +static const nir_search_variable search223_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search223_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search223_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &search223_0_0.value, &search223_0_1.value }, + (is_used_once), +}; + +static const nir_search_variable search223_1_0 = { + { nir_search_value_variable, -2 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search223_1_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search223_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &search223_1_0.value, &search223_1_1.value }, + NULL, +}; +static const nir_search_expression search223 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &search223_0.value, &search223_1.value }, + NULL, +}; + +static const nir_search_variable replace223_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace223_0_1 = { + { nir_search_value_variable, -2 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace223_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_umax, + { &replace223_0_0.value, &replace223_0_1.value }, + NULL, +}; + +static const nir_search_variable replace223_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace223 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &replace223_0.value, &replace223_1.value }, + NULL, +}; + +static const nir_search_variable search224_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search224_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search224_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &search224_0_0.value, &search224_0_1.value }, + (is_used_once), +}; + +static const nir_search_variable search224_1_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search224_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search224_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &search224_1_0.value, &search224_1_1.value }, + NULL, +}; +static const nir_search_expression search224 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &search224_0.value, &search224_1.value }, + NULL, +}; + +static const nir_search_variable replace224_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace224_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace224_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace224_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_umax, + { &replace224_1_0.value, &replace224_1_1.value }, + NULL, +}; +static const nir_search_expression replace224 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &replace224_0.value, &replace224_1.value }, + NULL, +}; + +static const nir_search_variable search225_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search225_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search225_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &search225_0_0.value, &search225_0_1.value }, + (is_used_once), +}; + +static const nir_search_variable search225_1_0 = { + { nir_search_value_variable, -2 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search225_1_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search225_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &search225_1_0.value, &search225_1_1.value }, + NULL, +}; +static const nir_search_expression search225 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &search225_0.value, &search225_1.value }, + NULL, +}; + +static const nir_search_variable replace225_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace225_0_1 = { + { nir_search_value_variable, -2 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace225_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_umin, + { &replace225_0_0.value, &replace225_0_1.value }, + NULL, +}; + +static const nir_search_variable replace225_1 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace225 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &replace225_0.value, &replace225_1.value }, + NULL, +}; + +static const nir_search_variable search226_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_bool, + NULL, +}; + +static const nir_search_variable search226_1_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search226_1_1 = { + { nir_search_value_constant, 1 }, + nir_type_bool, { NIR_FALSE /* False */ }, +}; +static const nir_search_expression search226_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ieq, + { &search226_1_0.value, &search226_1_1.value }, + NULL, +}; +static const nir_search_expression search226 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &search226_0.value, &search226_1.value }, + NULL, +}; + +static const nir_search_constant replace226 = { + { nir_search_value_constant, 1 }, + nir_type_bool, { NIR_TRUE /* True */ }, +}; + +static const nir_search_variable search227_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search227_1_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search227_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_inot, + { &search227_1_0.value }, + NULL, +}; +static const nir_search_expression search227 = { + { nir_search_value_expression, -1 }, + false, + nir_op_ior, + { &search227_0.value, &search227_1.value }, + NULL, +}; + +static const nir_search_constant replace227 = { + { nir_search_value_constant, -1 }, + nir_type_int, { -0x1 /* -1 */ }, +}; + +static const nir_search_variable search228_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search228_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression search228_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ieq, + { &search228_0_0.value, &search228_0_1.value }, + NULL, +}; + +static const nir_search_variable search228_1_0 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search228_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression search228_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ieq, + { &search228_1_0.value, &search228_1_1.value }, + NULL, +}; +static const nir_search_expression search228 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &search228_0.value, &search228_1.value }, + NULL, +}; + +static const nir_search_variable replace228_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace228_0_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace228_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ior, + { &replace228_0_0.value, &replace228_0_1.value }, + NULL, +}; + +static const nir_search_constant replace228_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression replace228 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ieq, + { &replace228_0.value, &replace228_1.value }, + NULL, +}; + +static const nir_search_variable search229_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search229_1_0 = { + { nir_search_value_variable, -1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search229_1_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search229_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmax, + { &search229_1_0.value, &search229_1_1.value }, + NULL, +}; +static const nir_search_expression search229 = { + { nir_search_value_expression, 1 }, + true, + nir_op_flt, + { &search229_0.value, &search229_1.value }, + NULL, +}; + +static const nir_search_variable replace229_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace229_1 = { + { nir_search_value_variable, -1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace229 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &replace229_0.value, &replace229_1.value }, + NULL, +}; + +static const nir_search_variable search230_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search230_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search230_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fmin, + { &search230_0_0.value, &search230_0_1.value }, + NULL, +}; + +static const nir_search_variable search230_1 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search230 = { + { nir_search_value_expression, 1 }, + true, + nir_op_flt, + { &search230_0.value, &search230_1.value }, + NULL, +}; + +static const nir_search_variable replace230_0 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace230_1 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace230 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &replace230_0.value, &replace230_1.value }, + NULL, +}; + +static const nir_search_variable search231_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search231_1_0 = { + { nir_search_value_variable, -1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search231_1_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search231_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmin, + { &search231_1_0.value, &search231_1_1.value }, + NULL, +}; +static const nir_search_expression search231 = { + { nir_search_value_expression, 1 }, + true, + nir_op_fge, + { &search231_0.value, &search231_1.value }, + NULL, +}; + +static const nir_search_constant replace231 = { + { nir_search_value_constant, 1 }, + nir_type_bool, { NIR_TRUE /* True */ }, +}; + +static const nir_search_variable search232_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search232_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search232_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fmax, + { &search232_0_0.value, &search232_0_1.value }, + NULL, +}; + +static const nir_search_variable search232_1 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search232 = { + { nir_search_value_expression, 1 }, + true, + nir_op_fge, + { &search232_0.value, &search232_1.value }, + NULL, +}; + +static const nir_search_constant replace232 = { + { nir_search_value_constant, 1 }, + nir_type_bool, { NIR_TRUE /* True */ }, +}; + +static const nir_search_variable search233_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search233_1_0 = { + { nir_search_value_variable, -1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search233_1_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search233_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmin, + { &search233_1_0.value, &search233_1_1.value }, + NULL, +}; +static const nir_search_expression search233 = { + { nir_search_value_expression, 1 }, + true, + nir_op_flt, + { &search233_0.value, &search233_1.value }, + NULL, +}; + +static const nir_search_constant replace233 = { + { nir_search_value_constant, 1 }, + nir_type_bool, { NIR_FALSE /* False */ }, +}; + +static const nir_search_variable search234_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search234_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search234_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fmax, + { &search234_0_0.value, &search234_0_1.value }, + NULL, +}; + +static const nir_search_variable search234_1 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search234 = { + { nir_search_value_expression, 1 }, + true, + nir_op_flt, + { &search234_0.value, &search234_1.value }, + NULL, +}; + +static const nir_search_constant replace234 = { + { nir_search_value_constant, 1 }, + nir_type_bool, { NIR_FALSE /* False */ }, +}; + +static const nir_search_variable search235_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search235_1_0 = { + { nir_search_value_variable, -1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search235_1_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search235_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmax, + { &search235_1_0.value, &search235_1_1.value }, + NULL, +}; +static const nir_search_expression search235 = { + { nir_search_value_expression, 1 }, + true, + nir_op_fge, + { &search235_0.value, &search235_1.value }, + NULL, +}; + +static const nir_search_variable replace235_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace235_1 = { + { nir_search_value_variable, -1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace235 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &replace235_0.value, &replace235_1.value }, + NULL, +}; + +static const nir_search_variable search236_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search236_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search236_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fmin, + { &search236_0_0.value, &search236_0_1.value }, + NULL, +}; + +static const nir_search_variable search236_1 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search236 = { + { nir_search_value_expression, 1 }, + true, + nir_op_fge, + { &search236_0.value, &search236_1.value }, + NULL, +}; + +static const nir_search_variable replace236_0 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace236_1 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace236 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &replace236_0.value, &replace236_1.value }, + NULL, +}; + +static const nir_search_variable search237_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search237_1_0 = { + { nir_search_value_variable, -1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search237_1_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search237_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_imax, + { &search237_1_0.value, &search237_1_1.value }, + NULL, +}; +static const nir_search_expression search237 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &search237_0.value, &search237_1.value }, + NULL, +}; + +static const nir_search_variable replace237_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace237_1 = { + { nir_search_value_variable, -1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace237 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &replace237_0.value, &replace237_1.value }, + NULL, +}; + +static const nir_search_variable search238_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search238_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search238_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_imin, + { &search238_0_0.value, &search238_0_1.value }, + NULL, +}; + +static const nir_search_variable search238_1 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search238 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &search238_0.value, &search238_1.value }, + NULL, +}; + +static const nir_search_variable replace238_0 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace238_1 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace238 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &replace238_0.value, &replace238_1.value }, + NULL, +}; + +static const nir_search_variable search239_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search239_1_0 = { + { nir_search_value_variable, -1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search239_1_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search239_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_imin, + { &search239_1_0.value, &search239_1_1.value }, + NULL, +}; +static const nir_search_expression search239 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &search239_0.value, &search239_1.value }, + NULL, +}; + +static const nir_search_constant replace239 = { + { nir_search_value_constant, 1 }, + nir_type_bool, { NIR_TRUE /* True */ }, +}; + +static const nir_search_variable search240_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search240_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search240_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_imax, + { &search240_0_0.value, &search240_0_1.value }, + NULL, +}; + +static const nir_search_variable search240_1 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search240 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &search240_0.value, &search240_1.value }, + NULL, +}; + +static const nir_search_constant replace240 = { + { nir_search_value_constant, 1 }, + nir_type_bool, { NIR_TRUE /* True */ }, +}; + +static const nir_search_variable search241_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search241_1_0 = { + { nir_search_value_variable, -1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search241_1_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search241_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_umax, + { &search241_1_0.value, &search241_1_1.value }, + NULL, +}; +static const nir_search_expression search241 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &search241_0.value, &search241_1.value }, + NULL, +}; + +static const nir_search_variable replace241_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace241_1 = { + { nir_search_value_variable, -1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace241 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &replace241_0.value, &replace241_1.value }, + NULL, +}; + +static const nir_search_variable search242_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search242_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search242_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_umin, + { &search242_0_0.value, &search242_0_1.value }, + NULL, +}; + +static const nir_search_variable search242_1 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search242 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &search242_0.value, &search242_1.value }, + NULL, +}; + +static const nir_search_variable replace242_0 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace242_1 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace242 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &replace242_0.value, &replace242_1.value }, + NULL, +}; + +static const nir_search_variable search243_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search243_1_0 = { + { nir_search_value_variable, -1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search243_1_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search243_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_umin, + { &search243_1_0.value, &search243_1_1.value }, + NULL, +}; +static const nir_search_expression search243 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &search243_0.value, &search243_1.value }, + NULL, +}; + +static const nir_search_constant replace243 = { + { nir_search_value_constant, 1 }, + nir_type_bool, { NIR_TRUE /* True */ }, +}; + +static const nir_search_variable search244_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search244_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search244_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_umax, + { &search244_0_0.value, &search244_0_1.value }, + NULL, +}; + +static const nir_search_variable search244_1 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search244 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &search244_0.value, &search244_1.value }, + NULL, +}; + +static const nir_search_constant replace244 = { + { nir_search_value_constant, 1 }, + nir_type_bool, { NIR_TRUE /* True */ }, +}; + +static const nir_search_variable search245_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search245_1_0 = { + { nir_search_value_variable, -1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search245_1_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search245_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_imin, + { &search245_1_0.value, &search245_1_1.value }, + NULL, +}; +static const nir_search_expression search245 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &search245_0.value, &search245_1.value }, + NULL, +}; + +static const nir_search_constant replace245 = { + { nir_search_value_constant, 1 }, + nir_type_bool, { NIR_FALSE /* False */ }, +}; + +static const nir_search_variable search246_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search246_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search246_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_imax, + { &search246_0_0.value, &search246_0_1.value }, + NULL, +}; + +static const nir_search_variable search246_1 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search246 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &search246_0.value, &search246_1.value }, + NULL, +}; + +static const nir_search_constant replace246 = { + { nir_search_value_constant, 1 }, + nir_type_bool, { NIR_FALSE /* False */ }, +}; + +static const nir_search_variable search247_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search247_1_0 = { + { nir_search_value_variable, -1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search247_1_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search247_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_imax, + { &search247_1_0.value, &search247_1_1.value }, + NULL, +}; +static const nir_search_expression search247 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &search247_0.value, &search247_1.value }, + NULL, +}; + +static const nir_search_variable replace247_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace247_1 = { + { nir_search_value_variable, -1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace247 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &replace247_0.value, &replace247_1.value }, + NULL, +}; + +static const nir_search_variable search248_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search248_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search248_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_imin, + { &search248_0_0.value, &search248_0_1.value }, + NULL, +}; + +static const nir_search_variable search248_1 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search248 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &search248_0.value, &search248_1.value }, + NULL, +}; + +static const nir_search_variable replace248_0 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace248_1 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace248 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &replace248_0.value, &replace248_1.value }, + NULL, +}; + +static const nir_search_variable search249_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search249_1_0 = { + { nir_search_value_variable, -1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search249_1_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search249_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_umin, + { &search249_1_0.value, &search249_1_1.value }, + NULL, +}; +static const nir_search_expression search249 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &search249_0.value, &search249_1.value }, + NULL, +}; + +static const nir_search_constant replace249 = { + { nir_search_value_constant, 1 }, + nir_type_bool, { NIR_FALSE /* False */ }, +}; + +static const nir_search_variable search250_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search250_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search250_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_umax, + { &search250_0_0.value, &search250_0_1.value }, + NULL, +}; + +static const nir_search_variable search250_1 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search250 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &search250_0.value, &search250_1.value }, + NULL, +}; + +static const nir_search_constant replace250 = { + { nir_search_value_constant, 1 }, + nir_type_bool, { NIR_FALSE /* False */ }, +}; + +static const nir_search_variable search251_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search251_1_0 = { + { nir_search_value_variable, -1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search251_1_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search251_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_umax, + { &search251_1_0.value, &search251_1_1.value }, + NULL, +}; +static const nir_search_expression search251 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &search251_0.value, &search251_1.value }, + NULL, +}; + +static const nir_search_variable replace251_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace251_1 = { + { nir_search_value_variable, -1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace251 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &replace251_0.value, &replace251_1.value }, + NULL, +}; + +static const nir_search_variable search252_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search252_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search252_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_umin, + { &search252_0_0.value, &search252_0_1.value }, + NULL, +}; + +static const nir_search_variable search252_1 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search252 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &search252_0.value, &search252_1.value }, + NULL, +}; + +static const nir_search_variable replace252_0 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace252_1 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace252 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &replace252_0.value, &replace252_1.value }, + NULL, +}; + +static const nir_search_variable search253_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search253_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search253_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search253_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_imax, + { &search253_1_0.value, &search253_1_1.value }, + NULL, +}; +static const nir_search_expression search253 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &search253_0.value, &search253_1.value }, + NULL, +}; + +static const nir_search_variable replace253_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace253_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace253_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &replace253_0_0.value, &replace253_0_1.value }, + NULL, +}; + +static const nir_search_variable replace253_1_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace253_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace253_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &replace253_1_0.value, &replace253_1_1.value }, + NULL, +}; +static const nir_search_expression replace253 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &replace253_0.value, &replace253_1.value }, + NULL, +}; + +static const nir_search_variable search254_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search254_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search254_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_imin, + { &search254_0_0.value, &search254_0_1.value }, + NULL, +}; + +static const nir_search_variable search254_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search254 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &search254_0.value, &search254_1.value }, + NULL, +}; + +static const nir_search_variable replace254_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace254_0_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace254_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &replace254_0_0.value, &replace254_0_1.value }, + NULL, +}; + +static const nir_search_variable replace254_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace254_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace254_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &replace254_1_0.value, &replace254_1_1.value }, + NULL, +}; +static const nir_search_expression replace254 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &replace254_0.value, &replace254_1.value }, + NULL, +}; + +static const nir_search_variable search255_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search255_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search255_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search255_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_imin, + { &search255_1_0.value, &search255_1_1.value }, + NULL, +}; +static const nir_search_expression search255 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &search255_0.value, &search255_1.value }, + NULL, +}; + +static const nir_search_variable replace255_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace255_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace255_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &replace255_0_0.value, &replace255_0_1.value }, + NULL, +}; + +static const nir_search_variable replace255_1_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace255_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace255_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &replace255_1_0.value, &replace255_1_1.value }, + NULL, +}; +static const nir_search_expression replace255 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &replace255_0.value, &replace255_1.value }, + NULL, +}; + +static const nir_search_variable search256_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search256_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search256_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_imax, + { &search256_0_0.value, &search256_0_1.value }, + NULL, +}; + +static const nir_search_variable search256_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search256 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &search256_0.value, &search256_1.value }, + NULL, +}; + +static const nir_search_variable replace256_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace256_0_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace256_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &replace256_0_0.value, &replace256_0_1.value }, + NULL, +}; + +static const nir_search_variable replace256_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace256_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace256_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &replace256_1_0.value, &replace256_1_1.value }, + NULL, +}; +static const nir_search_expression replace256 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &replace256_0.value, &replace256_1.value }, + NULL, +}; + +static const nir_search_variable search257_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search257_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search257_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search257_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_umax, + { &search257_1_0.value, &search257_1_1.value }, + NULL, +}; +static const nir_search_expression search257 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &search257_0.value, &search257_1.value }, + NULL, +}; + +static const nir_search_variable replace257_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace257_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace257_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &replace257_0_0.value, &replace257_0_1.value }, + NULL, +}; + +static const nir_search_variable replace257_1_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace257_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace257_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &replace257_1_0.value, &replace257_1_1.value }, + NULL, +}; +static const nir_search_expression replace257 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &replace257_0.value, &replace257_1.value }, + NULL, +}; + +static const nir_search_variable search258_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search258_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search258_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_umin, + { &search258_0_0.value, &search258_0_1.value }, + NULL, +}; + +static const nir_search_variable search258_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search258 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &search258_0.value, &search258_1.value }, + NULL, +}; + +static const nir_search_variable replace258_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace258_0_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace258_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &replace258_0_0.value, &replace258_0_1.value }, + NULL, +}; + +static const nir_search_variable replace258_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace258_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace258_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &replace258_1_0.value, &replace258_1_1.value }, + NULL, +}; +static const nir_search_expression replace258 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &replace258_0.value, &replace258_1.value }, + NULL, +}; + +static const nir_search_variable search259_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search259_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search259_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search259_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_umin, + { &search259_1_0.value, &search259_1_1.value }, + NULL, +}; +static const nir_search_expression search259 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &search259_0.value, &search259_1.value }, + NULL, +}; + +static const nir_search_variable replace259_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace259_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace259_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &replace259_0_0.value, &replace259_0_1.value }, + NULL, +}; + +static const nir_search_variable replace259_1_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace259_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace259_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &replace259_1_0.value, &replace259_1_1.value }, + NULL, +}; +static const nir_search_expression replace259 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &replace259_0.value, &replace259_1.value }, + NULL, +}; + +static const nir_search_variable search260_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search260_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search260_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_umax, + { &search260_0_0.value, &search260_0_1.value }, + NULL, +}; + +static const nir_search_variable search260_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search260 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &search260_0.value, &search260_1.value }, + NULL, +}; + +static const nir_search_variable replace260_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace260_0_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace260_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &replace260_0_0.value, &replace260_0_1.value }, + NULL, +}; + +static const nir_search_variable replace260_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace260_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace260_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &replace260_1_0.value, &replace260_1_1.value }, + NULL, +}; +static const nir_search_expression replace260 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &replace260_0.value, &replace260_1.value }, + NULL, +}; + +static const nir_search_variable search261_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search261_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search261_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search261_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_imin, + { &search261_1_0.value, &search261_1_1.value }, + NULL, +}; +static const nir_search_expression search261 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &search261_0.value, &search261_1.value }, + NULL, +}; + +static const nir_search_variable replace261_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace261_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace261_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &replace261_0_0.value, &replace261_0_1.value }, + NULL, +}; + +static const nir_search_variable replace261_1_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace261_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace261_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &replace261_1_0.value, &replace261_1_1.value }, + NULL, +}; +static const nir_search_expression replace261 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &replace261_0.value, &replace261_1.value }, + NULL, +}; + +static const nir_search_variable search262_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search262_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search262_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_imax, + { &search262_0_0.value, &search262_0_1.value }, + NULL, +}; + +static const nir_search_variable search262_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search262 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &search262_0.value, &search262_1.value }, + NULL, +}; + +static const nir_search_variable replace262_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace262_0_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace262_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &replace262_0_0.value, &replace262_0_1.value }, + NULL, +}; + +static const nir_search_variable replace262_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace262_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace262_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &replace262_1_0.value, &replace262_1_1.value }, + NULL, +}; +static const nir_search_expression replace262 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &replace262_0.value, &replace262_1.value }, + NULL, +}; + +static const nir_search_variable search263_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search263_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search263_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search263_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_imax, + { &search263_1_0.value, &search263_1_1.value }, + NULL, +}; +static const nir_search_expression search263 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &search263_0.value, &search263_1.value }, + NULL, +}; + +static const nir_search_variable replace263_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace263_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace263_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &replace263_0_0.value, &replace263_0_1.value }, + NULL, +}; + +static const nir_search_variable replace263_1_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace263_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace263_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &replace263_1_0.value, &replace263_1_1.value }, + NULL, +}; +static const nir_search_expression replace263 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &replace263_0.value, &replace263_1.value }, + NULL, +}; + +static const nir_search_variable search264_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search264_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search264_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_imin, + { &search264_0_0.value, &search264_0_1.value }, + NULL, +}; + +static const nir_search_variable search264_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search264 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &search264_0.value, &search264_1.value }, + NULL, +}; + +static const nir_search_variable replace264_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace264_0_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace264_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &replace264_0_0.value, &replace264_0_1.value }, + NULL, +}; + +static const nir_search_variable replace264_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace264_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace264_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &replace264_1_0.value, &replace264_1_1.value }, + NULL, +}; +static const nir_search_expression replace264 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &replace264_0.value, &replace264_1.value }, + NULL, +}; + +static const nir_search_variable search265_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search265_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search265_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search265_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_umin, + { &search265_1_0.value, &search265_1_1.value }, + NULL, +}; +static const nir_search_expression search265 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &search265_0.value, &search265_1.value }, + NULL, +}; + +static const nir_search_variable replace265_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace265_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace265_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &replace265_0_0.value, &replace265_0_1.value }, + NULL, +}; + +static const nir_search_variable replace265_1_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace265_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace265_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &replace265_1_0.value, &replace265_1_1.value }, + NULL, +}; +static const nir_search_expression replace265 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &replace265_0.value, &replace265_1.value }, + NULL, +}; + +static const nir_search_variable search266_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search266_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search266_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_umax, + { &search266_0_0.value, &search266_0_1.value }, + NULL, +}; + +static const nir_search_variable search266_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search266 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &search266_0.value, &search266_1.value }, + NULL, +}; + +static const nir_search_variable replace266_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace266_0_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace266_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &replace266_0_0.value, &replace266_0_1.value }, + NULL, +}; + +static const nir_search_variable replace266_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace266_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace266_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &replace266_1_0.value, &replace266_1_1.value }, + NULL, +}; +static const nir_search_expression replace266 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &replace266_0.value, &replace266_1.value }, + NULL, +}; + +static const nir_search_variable search267_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search267_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search267_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search267_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_umax, + { &search267_1_0.value, &search267_1_1.value }, + NULL, +}; +static const nir_search_expression search267 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &search267_0.value, &search267_1.value }, + NULL, +}; + +static const nir_search_variable replace267_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace267_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace267_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &replace267_0_0.value, &replace267_0_1.value }, + NULL, +}; + +static const nir_search_variable replace267_1_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace267_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace267_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &replace267_1_0.value, &replace267_1_1.value }, + NULL, +}; +static const nir_search_expression replace267 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &replace267_0.value, &replace267_1.value }, + NULL, +}; + +static const nir_search_variable search268_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search268_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search268_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_umin, + { &search268_0_0.value, &search268_0_1.value }, + NULL, +}; + +static const nir_search_variable search268_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search268 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &search268_0.value, &search268_1.value }, + NULL, +}; + +static const nir_search_variable replace268_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace268_0_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace268_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &replace268_0_0.value, &replace268_0_1.value }, + NULL, +}; + +static const nir_search_variable replace268_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace268_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace268_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &replace268_1_0.value, &replace268_1_1.value }, + NULL, +}; +static const nir_search_expression replace268 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &replace268_0.value, &replace268_1.value }, + NULL, +}; + +static const nir_search_variable search269_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search269_0_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search269_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_slt, + { &search269_0_0.value, &search269_0_1.value }, + NULL, +}; +static const nir_search_expression search269 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fabs, + { &search269_0.value }, + NULL, +}; + +static const nir_search_variable replace269_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace269_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace269 = { + { nir_search_value_expression, 32 }, + false, + nir_op_slt, + { &replace269_0.value, &replace269_1.value }, + NULL, +}; + +static const nir_search_variable search270_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search270_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search270_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_sge, + { &search270_0_0.value, &search270_0_1.value }, + NULL, +}; +static const nir_search_expression search270 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fabs, + { &search270_0.value }, + NULL, +}; + +static const nir_search_variable replace270_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace270_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace270 = { + { nir_search_value_expression, -2 }, + false, + nir_op_sge, + { &replace270_0.value, &replace270_1.value }, + NULL, +}; + +static const nir_search_variable search271_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search271_0_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search271_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_seq, + { &search271_0_0.value, &search271_0_1.value }, + NULL, +}; +static const nir_search_expression search271 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fabs, + { &search271_0.value }, + NULL, +}; + +static const nir_search_variable replace271_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace271_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace271 = { + { nir_search_value_expression, 32 }, + false, + nir_op_seq, + { &replace271_0.value, &replace271_1.value }, + NULL, +}; + +static const nir_search_variable search272_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search272_0_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search272_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_sne, + { &search272_0_0.value, &search272_0_1.value }, + NULL, +}; +static const nir_search_expression search272 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fabs, + { &search272_0.value }, + NULL, +}; + +static const nir_search_variable replace272_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace272_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace272 = { + { nir_search_value_expression, 32 }, + false, + nir_op_sne, + { &replace272_0.value, &replace272_1.value }, + NULL, +}; + +static const nir_search_variable search273_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search273_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search273 = { + { nir_search_value_expression, 32 }, + false, + nir_op_slt, + { &search273_0.value, &search273_1.value }, + NULL, +}; + +static const nir_search_variable replace273_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace273_0_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace273_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &replace273_0_0.value, &replace273_0_1.value }, + NULL, +}; +static const nir_search_expression replace273 = { + { nir_search_value_expression, 32 }, + false, + nir_search_op_b2f, + { &replace273_0.value }, + NULL, +}; + +static const nir_search_variable search274_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search274_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search274 = { + { nir_search_value_expression, -2 }, + false, + nir_op_sge, + { &search274_0.value, &search274_1.value }, + NULL, +}; + +static const nir_search_variable replace274_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace274_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace274_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &replace274_0_0.value, &replace274_0_1.value }, + NULL, +}; +static const nir_search_expression replace274 = { + { nir_search_value_expression, -2 }, + false, + nir_search_op_b2f, + { &replace274_0.value }, + NULL, +}; + +static const nir_search_variable search275_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search275_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search275 = { + { nir_search_value_expression, 32 }, + false, + nir_op_seq, + { &search275_0.value, &search275_1.value }, + NULL, +}; + +static const nir_search_variable replace275_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace275_0_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace275_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &replace275_0_0.value, &replace275_0_1.value }, + NULL, +}; +static const nir_search_expression replace275 = { + { nir_search_value_expression, 32 }, + false, + nir_search_op_b2f, + { &replace275_0.value }, + NULL, +}; + +static const nir_search_variable search276_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search276_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search276 = { + { nir_search_value_expression, 32 }, + false, + nir_op_sne, + { &search276_0.value, &search276_1.value }, + NULL, +}; + +static const nir_search_variable replace276_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace276_0_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace276_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &replace276_0_0.value, &replace276_0_1.value }, + NULL, +}; +static const nir_search_expression replace276 = { + { nir_search_value_expression, 32 }, + false, + nir_search_op_b2f, + { &replace276_0.value }, + NULL, +}; + +static const nir_search_variable search277_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search277_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fneg, + { &search277_0_0.value }, + NULL, +}; + +static const nir_search_variable search277_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search277 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &search277_0.value, &search277_1.value }, + NULL, +}; + +static const nir_search_variable replace277_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace277_1 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression replace277 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &replace277_0.value, &replace277_1.value }, + NULL, +}; + +static const nir_search_variable search278_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search278_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fneg, + { &search278_0_0.value }, + NULL, +}; + +static const nir_search_variable search278_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search278 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &search278_0.value, &search278_1.value }, + NULL, +}; + +static const nir_search_variable replace278_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace278_1 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression replace278 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &replace278_0.value, &replace278_1.value }, + NULL, +}; + +static const nir_search_variable search279_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search279_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2i, + { &search279_0_0.value }, + NULL, +}; + +static const nir_search_variable search279_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search279_1 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2i, + { &search279_1_0.value }, + NULL, +}; +static const nir_search_expression search279 = { + { nir_search_value_expression, 0 }, + false, + nir_op_imul, + { &search279_0.value, &search279_1.value }, + NULL, +}; + +static const nir_search_variable replace279_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace279_0_1 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace279_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &replace279_0_0.value, &replace279_0_1.value }, + NULL, +}; +static const nir_search_expression replace279 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2i, + { &replace279_0.value }, + NULL, +}; + +static const nir_search_variable search280_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search280_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search280_0_0.value }, + NULL, +}; + +static const nir_search_variable search280_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search280_1 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search280_1_0.value }, + NULL, +}; +static const nir_search_expression search280 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fmul, + { &search280_0.value, &search280_1.value }, + NULL, +}; + +static const nir_search_variable replace280_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace280_0_1 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace280_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &replace280_0_0.value, &replace280_0_1.value }, + NULL, +}; +static const nir_search_expression replace280 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &replace280_0.value }, + NULL, +}; + +static const nir_search_variable search281_0_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search281_0_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search281_0_0_0.value }, + NULL, +}; + +static const nir_search_variable search281_0_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search281_0_1 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search281_0_1_0.value }, + NULL, +}; +static const nir_search_expression search281_0 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fadd, + { &search281_0_0.value, &search281_0_1.value }, + NULL, +}; +static const nir_search_expression search281 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fsat, + { &search281_0.value }, + NULL, +}; + +static const nir_search_variable replace281_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace281_0_1 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace281_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &replace281_0_0.value, &replace281_0_1.value }, + NULL, +}; +static const nir_search_expression replace281 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &replace281_0.value }, + NULL, +}; + +static const nir_search_variable search282_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_bool, + NULL, +}; + +static const nir_search_constant search282_1 = { + { nir_search_value_constant, 32 }, + nir_type_float, { 0x3ff0000000000000 /* 1.0 */ }, +}; +static const nir_search_expression search282 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iand, + { &search282_0.value, &search282_1.value }, + NULL, +}; + +static const nir_search_variable replace282_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace282 = { + { nir_search_value_expression, 32 }, + false, + nir_search_op_b2f, + { &replace282_0.value }, + NULL, +}; + +static const nir_search_variable search283_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search283_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_b2i32, + { &search283_0_0.value }, + NULL, +}; +static const nir_search_expression search283 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ineg, + { &search283_0.value }, + NULL, +}; + +static const nir_search_variable replace283 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search284_0_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search284_0_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search284_0_0_0.value }, + NULL, +}; +static const nir_search_expression search284_0 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fneg, + { &search284_0_0.value }, + NULL, +}; + +static const nir_search_constant search284_1 = { + { nir_search_value_constant, 0 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression search284 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search284_0.value, &search284_1.value }, + NULL, +}; + +static const nir_search_variable replace284 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search285_0_0 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; + +static const nir_search_variable search285_0_1_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search285_0_1 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search285_0_1_0.value }, + NULL, +}; +static const nir_search_expression search285_0 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fsub, + { &search285_0_0.value, &search285_0_1.value }, + NULL, +}; + +static const nir_search_constant search285_1 = { + { nir_search_value_constant, 0 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression search285 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search285_0.value, &search285_1.value }, + NULL, +}; + +static const nir_search_variable replace285 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search286_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search286_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search286 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &search286_0.value, &search286_1.value }, + NULL, +}; + +static const nir_search_constant replace286 = { + { nir_search_value_constant, 1 }, + nir_type_bool, { NIR_FALSE /* False */ }, +}; + +static const nir_search_variable search287_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search287_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search287 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &search287_0.value, &search287_1.value }, + NULL, +}; + +static const nir_search_constant replace287 = { + { nir_search_value_constant, 1 }, + nir_type_bool, { NIR_TRUE /* True */ }, +}; + +static const nir_search_variable search288_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search288_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search288 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ieq, + { &search288_0.value, &search288_1.value }, + NULL, +}; + +static const nir_search_constant replace288 = { + { nir_search_value_constant, 1 }, + nir_type_bool, { NIR_TRUE /* True */ }, +}; + +static const nir_search_variable search289_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search289_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search289 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ine, + { &search289_0.value, &search289_1.value }, + NULL, +}; + +static const nir_search_constant replace289 = { + { nir_search_value_constant, 1 }, + nir_type_bool, { NIR_FALSE /* False */ }, +}; + +static const nir_search_variable search290_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search290_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search290 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &search290_0.value, &search290_1.value }, + NULL, +}; + +static const nir_search_constant replace290 = { + { nir_search_value_constant, 1 }, + nir_type_bool, { NIR_FALSE /* False */ }, +}; + +static const nir_search_variable search291_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search291_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search291 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &search291_0.value, &search291_1.value }, + NULL, +}; + +static const nir_search_constant replace291 = { + { nir_search_value_constant, 1 }, + nir_type_bool, { NIR_TRUE /* True */ }, +}; + +static const nir_search_variable search292_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search292_1 = { + { nir_search_value_constant, 32 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search292 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fand, + { &search292_0.value, &search292_1.value }, + NULL, +}; + +static const nir_search_constant replace292 = { + { nir_search_value_constant, 32 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; + +static const nir_search_variable search293_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search293_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search293 = { + { nir_search_value_expression, -1 }, + false, + nir_op_iand, + { &search293_0.value, &search293_1.value }, + NULL, +}; + +static const nir_search_variable replace293 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search294_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search294_1 = { + { nir_search_value_constant, -1 }, + nir_type_int, { -0x1 /* -1 */ }, +}; +static const nir_search_expression search294 = { + { nir_search_value_expression, -1 }, + false, + nir_op_iand, + { &search294_0.value, &search294_1.value }, + NULL, +}; + +static const nir_search_variable replace294 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search295_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search295_1 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression search295 = { + { nir_search_value_expression, -1 }, + false, + nir_op_iand, + { &search295_0.value, &search295_1.value }, + NULL, +}; + +static const nir_search_constant replace295 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0x0 /* 0 */ }, +}; + +static const nir_search_variable search296_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search296_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search296 = { + { nir_search_value_expression, -1 }, + false, + nir_op_ior, + { &search296_0.value, &search296_1.value }, + NULL, +}; + +static const nir_search_variable replace296 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search297_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search297_1 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression search297 = { + { nir_search_value_expression, -1 }, + false, + nir_op_ior, + { &search297_0.value, &search297_1.value }, + NULL, +}; + +static const nir_search_variable replace297 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search298_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search298_1 = { + { nir_search_value_constant, 1 }, + nir_type_bool, { NIR_TRUE /* True */ }, +}; +static const nir_search_expression search298 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &search298_0.value, &search298_1.value }, + NULL, +}; + +static const nir_search_constant replace298 = { + { nir_search_value_constant, 1 }, + nir_type_bool, { NIR_TRUE /* True */ }, +}; + +static const nir_search_variable search299_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search299_1 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search299 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fxor, + { &search299_0.value, &search299_1.value }, + NULL, +}; + +static const nir_search_constant replace299 = { + { nir_search_value_constant, 32 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; + +static const nir_search_variable search300_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search300_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search300 = { + { nir_search_value_expression, -1 }, + false, + nir_op_ixor, + { &search300_0.value, &search300_1.value }, + NULL, +}; + +static const nir_search_constant replace300 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0x0 /* 0 */ }, +}; + +static const nir_search_variable search301_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search301_1 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression search301 = { + { nir_search_value_expression, -1 }, + false, + nir_op_ixor, + { &search301_0.value, &search301_1.value }, + NULL, +}; + +static const nir_search_variable replace301 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search302_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search302_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_inot, + { &search302_0_0.value }, + NULL, +}; +static const nir_search_expression search302 = { + { nir_search_value_expression, -1 }, + false, + nir_op_inot, + { &search302_0.value }, + NULL, +}; + +static const nir_search_variable replace302 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search303_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search303_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search303_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_iand, + { &search303_0_0.value, &search303_0_1.value }, + NULL, +}; + +static const nir_search_variable search303_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search303 = { + { nir_search_value_expression, -2 }, + false, + nir_op_ior, + { &search303_0.value, &search303_1.value }, + NULL, +}; + +static const nir_search_variable replace303 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search304_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search304_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search304_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_ior, + { &search304_0_0.value, &search304_0_1.value }, + NULL, +}; + +static const nir_search_variable search304_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search304 = { + { nir_search_value_expression, -2 }, + false, + nir_op_ior, + { &search304_0.value, &search304_1.value }, + NULL, +}; + +static const nir_search_variable replace304_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace304_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace304 = { + { nir_search_value_expression, -2 }, + false, + nir_op_ior, + { &replace304_0.value, &replace304_1.value }, + NULL, +}; + +static const nir_search_variable search305_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search305_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search305_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_ior, + { &search305_0_0.value, &search305_0_1.value }, + NULL, +}; + +static const nir_search_variable search305_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search305 = { + { nir_search_value_expression, -2 }, + false, + nir_op_iand, + { &search305_0.value, &search305_1.value }, + NULL, +}; + +static const nir_search_variable replace305 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search306_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search306_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search306_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_iand, + { &search306_0_0.value, &search306_0_1.value }, + NULL, +}; + +static const nir_search_variable search306_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search306 = { + { nir_search_value_expression, -2 }, + false, + nir_op_iand, + { &search306_0.value, &search306_1.value }, + NULL, +}; + +static const nir_search_variable replace306_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace306_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace306 = { + { nir_search_value_expression, -2 }, + false, + nir_op_iand, + { &replace306_0.value, &replace306_1.value }, + NULL, +}; + +static const nir_search_variable search307_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search307_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_inot, + { &search307_0_0.value }, + NULL, +}; + +static const nir_search_variable search307_1_0 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search307_1 = { + { nir_search_value_expression, -2 }, + false, + nir_op_inot, + { &search307_1_0.value }, + NULL, +}; +static const nir_search_expression search307 = { + { nir_search_value_expression, -2 }, + false, + nir_op_iand, + { &search307_0.value, &search307_1.value }, + NULL, +}; + +static const nir_search_variable replace307_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace307_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace307_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_ior, + { &replace307_0_0.value, &replace307_0_1.value }, + NULL, +}; +static const nir_search_expression replace307 = { + { nir_search_value_expression, -2 }, + false, + nir_op_inot, + { &replace307_0.value }, + NULL, +}; + +static const nir_search_variable search308_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search308_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_inot, + { &search308_0_0.value }, + NULL, +}; + +static const nir_search_variable search308_1_0 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search308_1 = { + { nir_search_value_expression, -2 }, + false, + nir_op_inot, + { &search308_1_0.value }, + NULL, +}; +static const nir_search_expression search308 = { + { nir_search_value_expression, -2 }, + false, + nir_op_ior, + { &search308_0.value, &search308_1.value }, + NULL, +}; + +static const nir_search_variable replace308_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace308_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace308_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_iand, + { &replace308_0_0.value, &replace308_0_1.value }, + NULL, +}; +static const nir_search_expression replace308 = { + { nir_search_value_expression, -2 }, + false, + nir_op_inot, + { &replace308_0.value }, + NULL, +}; + +static const nir_search_constant search309_0 = { + { nir_search_value_constant, 0 }, + nir_type_int, { 0x0 /* 0 */ }, +}; + +static const nir_search_variable search309_1 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search309 = { + { nir_search_value_expression, 0 }, + false, + nir_op_ishl, + { &search309_0.value, &search309_1.value }, + NULL, +}; + +static const nir_search_constant replace309 = { + { nir_search_value_constant, 0 }, + nir_type_int, { 0x0 /* 0 */ }, +}; + +static const nir_search_variable search310_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search310_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression search310 = { + { nir_search_value_expression, -1 }, + false, + nir_op_ishl, + { &search310_0.value, &search310_1.value }, + NULL, +}; + +static const nir_search_variable replace310 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search311_0 = { + { nir_search_value_constant, 0 }, + nir_type_int, { 0x0 /* 0 */ }, +}; + +static const nir_search_variable search311_1 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search311 = { + { nir_search_value_expression, 0 }, + false, + nir_op_ishr, + { &search311_0.value, &search311_1.value }, + NULL, +}; + +static const nir_search_constant replace311 = { + { nir_search_value_constant, 0 }, + nir_type_int, { 0x0 /* 0 */ }, +}; + +static const nir_search_variable search312_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search312_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression search312 = { + { nir_search_value_expression, -1 }, + false, + nir_op_ishr, + { &search312_0.value, &search312_1.value }, + NULL, +}; + +static const nir_search_variable replace312 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search313_0 = { + { nir_search_value_constant, 0 }, + nir_type_int, { 0x0 /* 0 */ }, +}; + +static const nir_search_variable search313_1 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search313 = { + { nir_search_value_expression, 0 }, + false, + nir_op_ushr, + { &search313_0.value, &search313_1.value }, + NULL, +}; + +static const nir_search_constant replace313 = { + { nir_search_value_constant, 0 }, + nir_type_int, { 0x0 /* 0 */ }, +}; + +static const nir_search_variable search314_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search314_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression search314 = { + { nir_search_value_expression, -1 }, + false, + nir_op_ushr, + { &search314_0.value, &search314_1.value }, + NULL, +}; + +static const nir_search_variable replace314 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search315_0 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0xff /* 255 */ }, +}; + +static const nir_search_variable search315_1_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search315_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x18 /* 24 */ }, +}; +static const nir_search_expression search315_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search315_1_0.value, &search315_1_1.value }, + NULL, +}; +static const nir_search_expression search315 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iand, + { &search315_0.value, &search315_1.value }, + NULL, +}; + +static const nir_search_variable replace315_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace315_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x18 /* 24 */ }, +}; +static const nir_search_expression replace315 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &replace315_0.value, &replace315_1.value }, + NULL, +}; + +static const nir_search_constant search316_0 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0xffff /* 65535 */ }, +}; + +static const nir_search_variable search316_1_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search316_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search316_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search316_1_0.value, &search316_1_1.value }, + NULL, +}; +static const nir_search_expression search316 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iand, + { &search316_0.value, &search316_1.value }, + NULL, +}; + +static const nir_search_variable replace316_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace316_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression replace316 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &replace316_0.value, &replace316_1.value }, + NULL, +}; + +static const nir_search_variable search317_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search317_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_flog2, + { &search317_0_0.value }, + NULL, +}; +static const nir_search_expression search317 = { + { nir_search_value_expression, -1 }, + true, + nir_op_fexp2, + { &search317_0.value }, + NULL, +}; + +static const nir_search_variable replace317 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search318_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search318_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fexp2, + { &search318_0_0.value }, + NULL, +}; +static const nir_search_expression search318 = { + { nir_search_value_expression, -1 }, + true, + nir_op_flog2, + { &search318_0.value }, + NULL, +}; + +static const nir_search_variable replace318 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search319_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search319_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search319 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fpow, + { &search319_0.value, &search319_1.value }, + NULL, +}; + +static const nir_search_variable replace319_0_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace319_0_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_flog2, + { &replace319_0_0_0.value }, + NULL, +}; + +static const nir_search_variable replace319_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace319_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fmul, + { &replace319_0_0.value, &replace319_0_1.value }, + NULL, +}; +static const nir_search_expression replace319 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fexp2, + { &replace319_0.value }, + NULL, +}; + +static const nir_search_variable search320_0_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search320_0_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_flog2, + { &search320_0_0_0.value }, + NULL, +}; + +static const nir_search_variable search320_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search320_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fmul, + { &search320_0_0.value, &search320_0_1.value }, + NULL, +}; +static const nir_search_expression search320 = { + { nir_search_value_expression, -2 }, + true, + nir_op_fexp2, + { &search320_0.value }, + NULL, +}; + +static const nir_search_variable replace320_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace320_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace320 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fpow, + { &replace320_0.value, &replace320_1.value }, + NULL, +}; + +static const nir_search_variable search321_0_0_0_0 = { + { nir_search_value_variable, -4 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search321_0_0_0 = { + { nir_search_value_expression, -4 }, + false, + nir_op_flog2, + { &search321_0_0_0_0.value }, + NULL, +}; + +static const nir_search_variable search321_0_0_1 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search321_0_0 = { + { nir_search_value_expression, -4 }, + false, + nir_op_fmul, + { &search321_0_0_0.value, &search321_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search321_0_1_0_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search321_0_1_0 = { + { nir_search_value_expression, -4 }, + false, + nir_op_flog2, + { &search321_0_1_0_0.value }, + NULL, +}; + +static const nir_search_variable search321_0_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search321_0_1 = { + { nir_search_value_expression, -4 }, + false, + nir_op_fmul, + { &search321_0_1_0.value, &search321_0_1_1.value }, + NULL, +}; +static const nir_search_expression search321_0 = { + { nir_search_value_expression, -4 }, + false, + nir_op_fadd, + { &search321_0_0.value, &search321_0_1.value }, + NULL, +}; +static const nir_search_expression search321 = { + { nir_search_value_expression, -4 }, + true, + nir_op_fexp2, + { &search321_0.value }, + NULL, +}; + +static const nir_search_variable replace321_0_0 = { + { nir_search_value_variable, -4 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace321_0_1 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace321_0 = { + { nir_search_value_expression, -4 }, + false, + nir_op_fpow, + { &replace321_0_0.value, &replace321_0_1.value }, + NULL, +}; + +static const nir_search_variable replace321_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace321_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace321_1 = { + { nir_search_value_expression, -4 }, + false, + nir_op_fpow, + { &replace321_1_0.value, &replace321_1_1.value }, + NULL, +}; +static const nir_search_expression replace321 = { + { nir_search_value_expression, -4 }, + true, + nir_op_fmul, + { &replace321_0.value, &replace321_1.value }, + NULL, +}; + +static const nir_search_variable search322_0_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search322_0_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_flog2, + { &search322_0_0_0.value }, + NULL, +}; + +static const nir_search_constant search322_0_1 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x4000000000000000 /* 2.0 */ }, +}; +static const nir_search_expression search322_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmul, + { &search322_0_0.value, &search322_0_1.value }, + NULL, +}; +static const nir_search_expression search322 = { + { nir_search_value_expression, -1 }, + true, + nir_op_fexp2, + { &search322_0.value }, + NULL, +}; + +static const nir_search_variable replace322_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace322_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace322 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmul, + { &replace322_0.value, &replace322_1.value }, + NULL, +}; + +static const nir_search_variable search323_0_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search323_0_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_flog2, + { &search323_0_0_0.value }, + NULL, +}; + +static const nir_search_constant search323_0_1 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x4010000000000000 /* 4.0 */ }, +}; +static const nir_search_expression search323_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmul, + { &search323_0_0.value, &search323_0_1.value }, + NULL, +}; +static const nir_search_expression search323 = { + { nir_search_value_expression, -1 }, + true, + nir_op_fexp2, + { &search323_0.value }, + NULL, +}; + +static const nir_search_variable replace323_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace323_0_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace323_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmul, + { &replace323_0_0.value, &replace323_0_1.value }, + NULL, +}; + +static const nir_search_variable replace323_1_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace323_1_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace323_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmul, + { &replace323_1_0.value, &replace323_1_1.value }, + NULL, +}; +static const nir_search_expression replace323 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmul, + { &replace323_0.value, &replace323_1.value }, + NULL, +}; + +static const nir_search_variable search324_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search324_1 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x3ff0000000000000 /* 1.0 */ }, +}; +static const nir_search_expression search324 = { + { nir_search_value_expression, -1 }, + true, + nir_op_fpow, + { &search324_0.value, &search324_1.value }, + NULL, +}; + +static const nir_search_variable replace324 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search325_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search325_1 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x4000000000000000 /* 2.0 */ }, +}; +static const nir_search_expression search325 = { + { nir_search_value_expression, -1 }, + true, + nir_op_fpow, + { &search325_0.value, &search325_1.value }, + NULL, +}; + +static const nir_search_variable replace325_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace325_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace325 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmul, + { &replace325_0.value, &replace325_1.value }, + NULL, +}; + +static const nir_search_variable search326_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search326_1 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x4010000000000000 /* 4.0 */ }, +}; +static const nir_search_expression search326 = { + { nir_search_value_expression, -1 }, + true, + nir_op_fpow, + { &search326_0.value, &search326_1.value }, + NULL, +}; + +static const nir_search_variable replace326_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace326_0_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace326_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmul, + { &replace326_0_0.value, &replace326_0_1.value }, + NULL, +}; + +static const nir_search_variable replace326_1_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace326_1_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace326_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmul, + { &replace326_1_0.value, &replace326_1_1.value }, + NULL, +}; +static const nir_search_expression replace326 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmul, + { &replace326_0.value, &replace326_1.value }, + NULL, +}; + +static const nir_search_constant search327_0 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x4000000000000000 /* 2.0 */ }, +}; + +static const nir_search_variable search327_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search327 = { + { nir_search_value_expression, -1 }, + true, + nir_op_fpow, + { &search327_0.value, &search327_1.value }, + NULL, +}; + +static const nir_search_variable replace327_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace327 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fexp2, + { &replace327_0.value }, + NULL, +}; + +static const nir_search_variable search328_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search328_0_1 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x400199999999999a /* 2.2 */ }, +}; +static const nir_search_expression search328_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fpow, + { &search328_0_0.value, &search328_0_1.value }, + NULL, +}; + +static const nir_search_constant search328_1 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x3fdd1743e963dc48 /* 0.454545 */ }, +}; +static const nir_search_expression search328 = { + { nir_search_value_expression, -1 }, + true, + nir_op_fpow, + { &search328_0.value, &search328_1.value }, + NULL, +}; + +static const nir_search_variable replace328 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search329_0_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search329_0_0_1 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x400199999999999a /* 2.2 */ }, +}; +static const nir_search_expression search329_0_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fpow, + { &search329_0_0_0.value, &search329_0_0_1.value }, + NULL, +}; +static const nir_search_expression search329_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fabs, + { &search329_0_0.value }, + NULL, +}; + +static const nir_search_constant search329_1 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x3fdd1743e963dc48 /* 0.454545 */ }, +}; +static const nir_search_expression search329 = { + { nir_search_value_expression, -1 }, + true, + nir_op_fpow, + { &search329_0.value, &search329_1.value }, + NULL, +}; + +static const nir_search_variable replace329_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace329 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fabs, + { &replace329_0.value }, + NULL, +}; + +static const nir_search_variable search330_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search330_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fexp2, + { &search330_0_0.value }, + NULL, +}; +static const nir_search_expression search330 = { + { nir_search_value_expression, -1 }, + true, + nir_op_fsqrt, + { &search330_0.value }, + NULL, +}; + +static const nir_search_constant replace330_0_0 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x3fe0000000000000 /* 0.5 */ }, +}; + +static const nir_search_variable replace330_0_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace330_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmul, + { &replace330_0_0.value, &replace330_0_1.value }, + NULL, +}; +static const nir_search_expression replace330 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fexp2, + { &replace330_0.value }, + NULL, +}; + +static const nir_search_variable search331_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search331_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fexp2, + { &search331_0_0.value }, + NULL, +}; +static const nir_search_expression search331 = { + { nir_search_value_expression, -1 }, + true, + nir_op_frcp, + { &search331_0.value }, + NULL, +}; + +static const nir_search_variable replace331_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace331_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fneg, + { &replace331_0_0.value }, + NULL, +}; +static const nir_search_expression replace331 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fexp2, + { &replace331_0.value }, + NULL, +}; + +static const nir_search_variable search332_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search332_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fexp2, + { &search332_0_0.value }, + NULL, +}; +static const nir_search_expression search332 = { + { nir_search_value_expression, -1 }, + true, + nir_op_frsq, + { &search332_0.value }, + NULL, +}; + +static const nir_search_constant replace332_0_0 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0xbfe0000000000000L /* -0.5 */ }, +}; + +static const nir_search_variable replace332_0_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace332_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmul, + { &replace332_0_0.value, &replace332_0_1.value }, + NULL, +}; +static const nir_search_expression replace332 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fexp2, + { &replace332_0.value }, + NULL, +}; + +static const nir_search_variable search333_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search333_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fsqrt, + { &search333_0_0.value }, + NULL, +}; +static const nir_search_expression search333 = { + { nir_search_value_expression, -1 }, + true, + nir_op_flog2, + { &search333_0.value }, + NULL, +}; + +static const nir_search_constant replace333_0 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x3fe0000000000000 /* 0.5 */ }, +}; + +static const nir_search_variable replace333_1_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace333_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_flog2, + { &replace333_1_0.value }, + NULL, +}; +static const nir_search_expression replace333 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmul, + { &replace333_0.value, &replace333_1.value }, + NULL, +}; + +static const nir_search_variable search334_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search334_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_frcp, + { &search334_0_0.value }, + NULL, +}; +static const nir_search_expression search334 = { + { nir_search_value_expression, -1 }, + true, + nir_op_flog2, + { &search334_0.value }, + NULL, +}; + +static const nir_search_variable replace334_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace334_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_flog2, + { &replace334_0_0.value }, + NULL, +}; +static const nir_search_expression replace334 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fneg, + { &replace334_0.value }, + NULL, +}; + +static const nir_search_variable search335_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search335_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_frsq, + { &search335_0_0.value }, + NULL, +}; +static const nir_search_expression search335 = { + { nir_search_value_expression, -1 }, + true, + nir_op_flog2, + { &search335_0.value }, + NULL, +}; + +static const nir_search_constant replace335_0 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0xbfe0000000000000L /* -0.5 */ }, +}; + +static const nir_search_variable replace335_1_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace335_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_flog2, + { &replace335_1_0.value }, + NULL, +}; +static const nir_search_expression replace335 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fmul, + { &replace335_0.value, &replace335_1.value }, + NULL, +}; + +static const nir_search_variable search336_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search336_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search336_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fpow, + { &search336_0_0.value, &search336_0_1.value }, + NULL, +}; +static const nir_search_expression search336 = { + { nir_search_value_expression, -2 }, + true, + nir_op_flog2, + { &search336_0.value }, + NULL, +}; + +static const nir_search_variable replace336_0 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace336_1_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace336_1 = { + { nir_search_value_expression, -2 }, + false, + nir_op_flog2, + { &replace336_1_0.value }, + NULL, +}; +static const nir_search_expression replace336 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fmul, + { &replace336_0.value, &replace336_1.value }, + NULL, +}; + +static const nir_search_variable search337_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search337_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fexp2, + { &search337_0_0.value }, + (is_used_once), +}; + +static const nir_search_variable search337_1_0 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search337_1 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fexp2, + { &search337_1_0.value }, + (is_used_once), +}; +static const nir_search_expression search337 = { + { nir_search_value_expression, -2 }, + true, + nir_op_fmul, + { &search337_0.value, &search337_1.value }, + NULL, +}; + +static const nir_search_variable replace337_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace337_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace337_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fadd, + { &replace337_0_0.value, &replace337_0_1.value }, + NULL, +}; +static const nir_search_expression replace337 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fexp2, + { &replace337_0.value }, + NULL, +}; + +static const nir_search_constant search338_0 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x3ff0000000000000 /* 1.0 */ }, +}; + +static const nir_search_variable search338_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search338 = { + { nir_search_value_expression, -1 }, + true, + nir_op_fdiv, + { &search338_0.value, &search338_1.value }, + NULL, +}; + +static const nir_search_variable replace338_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace338 = { + { nir_search_value_expression, -1 }, + false, + nir_op_frcp, + { &replace338_0.value }, + NULL, +}; + +static const nir_search_variable search339_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search339_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search339 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fdiv, + { &search339_0.value, &search339_1.value }, + NULL, +}; + +static const nir_search_variable replace339_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace339_1_0 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace339_1 = { + { nir_search_value_expression, -2 }, + false, + nir_op_frcp, + { &replace339_1_0.value }, + NULL, +}; +static const nir_search_expression replace339 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fmul, + { &replace339_0.value, &replace339_1.value }, + NULL, +}; + +static const nir_search_variable search340_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search340_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_frcp, + { &search340_0_0.value }, + NULL, +}; +static const nir_search_expression search340 = { + { nir_search_value_expression, -1 }, + true, + nir_op_frcp, + { &search340_0.value }, + NULL, +}; + +static const nir_search_variable replace340 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search341_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search341_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fsqrt, + { &search341_0_0.value }, + NULL, +}; +static const nir_search_expression search341 = { + { nir_search_value_expression, -1 }, + true, + nir_op_frcp, + { &search341_0.value }, + NULL, +}; + +static const nir_search_variable replace341_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace341 = { + { nir_search_value_expression, -1 }, + false, + nir_op_frsq, + { &replace341_0.value }, + NULL, +}; + +static const nir_search_variable search342_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search342 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fsqrt, + { &search342_0.value }, + NULL, +}; + +static const nir_search_variable replace342_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace342_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_frsq, + { &replace342_0_0.value }, + NULL, +}; +static const nir_search_expression replace342 = { + { nir_search_value_expression, -1 }, + false, + nir_op_frcp, + { &replace342_0.value }, + NULL, +}; + +static const nir_search_variable search343_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search343_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_frsq, + { &search343_0_0.value }, + NULL, +}; +static const nir_search_expression search343 = { + { nir_search_value_expression, -1 }, + true, + nir_op_frcp, + { &search343_0.value }, + NULL, +}; + +static const nir_search_variable replace343_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace343 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fsqrt, + { &replace343_0.value }, + NULL, +}; + +static const nir_search_variable search344_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_bool, + NULL, +}; + +static const nir_search_constant search344_1 = { + { nir_search_value_constant, 1 }, + nir_type_bool, { NIR_TRUE /* True */ }, +}; +static const nir_search_expression search344 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ieq, + { &search344_0.value, &search344_1.value }, + NULL, +}; + +static const nir_search_variable replace344 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search345_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_bool, + NULL, +}; + +static const nir_search_constant search345_1 = { + { nir_search_value_constant, 1 }, + nir_type_bool, { NIR_TRUE /* True */ }, +}; +static const nir_search_expression search345 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ine, + { &search345_0.value, &search345_1.value }, + (is_not_used_by_if), +}; + +static const nir_search_variable replace345_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace345 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &replace345_0.value }, + NULL, +}; + +static const nir_search_variable search346_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_bool, + NULL, +}; + +static const nir_search_constant search346_1 = { + { nir_search_value_constant, 1 }, + nir_type_bool, { NIR_FALSE /* False */ }, +}; +static const nir_search_expression search346 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ine, + { &search346_0.value, &search346_1.value }, + NULL, +}; + +static const nir_search_variable replace346 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search347_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_bool, + NULL, +}; + +static const nir_search_constant search347_1 = { + { nir_search_value_constant, 1 }, + nir_type_bool, { NIR_FALSE /* False */ }, +}; +static const nir_search_expression search347 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ieq, + { &search347_0.value, &search347_1.value }, + (is_not_used_by_if), +}; + +static const nir_search_variable replace347_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace347 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &replace347_0.value }, + NULL, +}; + +static const nir_search_variable search348_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search348_1 = { + { nir_search_value_constant, 1 }, + nir_type_bool, { NIR_TRUE /* True */ }, +}; + +static const nir_search_constant search348_2 = { + { nir_search_value_constant, 1 }, + nir_type_bool, { NIR_FALSE /* False */ }, +}; +static const nir_search_expression search348 = { + { nir_search_value_expression, 1 }, + false, + nir_op_bcsel, + { &search348_0.value, &search348_1.value, &search348_2.value }, + NULL, +}; + +static const nir_search_variable replace348 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search349_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search349_1 = { + { nir_search_value_constant, 1 }, + nir_type_bool, { NIR_FALSE /* False */ }, +}; + +static const nir_search_constant search349_2 = { + { nir_search_value_constant, 1 }, + nir_type_bool, { NIR_TRUE /* True */ }, +}; +static const nir_search_expression search349 = { + { nir_search_value_expression, 1 }, + false, + nir_op_bcsel, + { &search349_0.value, &search349_1.value, &search349_2.value }, + NULL, +}; + +static const nir_search_variable replace349_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace349 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &replace349_0.value }, + NULL, +}; + +static const nir_search_variable search350_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search350_1 = { + { nir_search_value_constant, 32 }, + nir_type_float, { 0x3ff0000000000000 /* 1.0 */ }, +}; + +static const nir_search_constant search350_2 = { + { nir_search_value_constant, 32 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search350 = { + { nir_search_value_expression, 32 }, + false, + nir_op_bcsel, + { &search350_0.value, &search350_1.value, &search350_2.value }, + NULL, +}; + +static const nir_search_variable replace350_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace350 = { + { nir_search_value_expression, 32 }, + false, + nir_search_op_b2f, + { &replace350_0.value }, + NULL, +}; + +static const nir_search_variable search351_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search351_1 = { + { nir_search_value_constant, 32 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; + +static const nir_search_constant search351_2 = { + { nir_search_value_constant, 32 }, + nir_type_float, { 0x3ff0000000000000 /* 1.0 */ }, +}; +static const nir_search_expression search351 = { + { nir_search_value_expression, 32 }, + false, + nir_op_bcsel, + { &search351_0.value, &search351_1.value, &search351_2.value }, + NULL, +}; + +static const nir_search_variable replace351_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace351_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &replace351_0_0.value }, + NULL, +}; +static const nir_search_expression replace351 = { + { nir_search_value_expression, 32 }, + false, + nir_search_op_b2f, + { &replace351_0.value }, + NULL, +}; + +static const nir_search_variable search352_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search352_1 = { + { nir_search_value_constant, 32 }, + nir_type_float, { 0xbff0000000000000L /* -1.0 */ }, +}; + +static const nir_search_constant search352_2 = { + { nir_search_value_constant, 32 }, + nir_type_float, { 0x8000000000000000L /* -0.0 */ }, +}; +static const nir_search_expression search352 = { + { nir_search_value_expression, 32 }, + false, + nir_op_bcsel, + { &search352_0.value, &search352_1.value, &search352_2.value }, + NULL, +}; + +static const nir_search_variable replace352_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace352_0 = { + { nir_search_value_expression, 32 }, + false, + nir_search_op_b2f, + { &replace352_0_0.value }, + NULL, +}; +static const nir_search_expression replace352 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fneg, + { &replace352_0.value }, + NULL, +}; + +static const nir_search_variable search353_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search353_1 = { + { nir_search_value_constant, 32 }, + nir_type_float, { 0x8000000000000000L /* -0.0 */ }, +}; + +static const nir_search_constant search353_2 = { + { nir_search_value_constant, 32 }, + nir_type_float, { 0xbff0000000000000L /* -1.0 */ }, +}; +static const nir_search_expression search353 = { + { nir_search_value_expression, 32 }, + false, + nir_op_bcsel, + { &search353_0.value, &search353_1.value, &search353_2.value }, + NULL, +}; + +static const nir_search_variable replace353_0_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace353_0_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &replace353_0_0_0.value }, + NULL, +}; +static const nir_search_expression replace353_0 = { + { nir_search_value_expression, 32 }, + false, + nir_search_op_b2f, + { &replace353_0_0.value }, + NULL, +}; +static const nir_search_expression replace353 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fneg, + { &replace353_0.value }, + NULL, +}; + +static const nir_search_constant search354_0 = { + { nir_search_value_constant, 1 }, + nir_type_bool, { NIR_TRUE /* True */ }, +}; + +static const nir_search_variable search354_1 = { + { nir_search_value_variable, -2 }, + 0, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search354_2 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search354 = { + { nir_search_value_expression, -2 }, + false, + nir_op_bcsel, + { &search354_0.value, &search354_1.value, &search354_2.value }, + NULL, +}; + +static const nir_search_variable replace354 = { + { nir_search_value_variable, -2 }, + 0, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search355_0 = { + { nir_search_value_constant, 1 }, + nir_type_bool, { NIR_FALSE /* False */ }, +}; + +static const nir_search_variable search355_1 = { + { nir_search_value_variable, -2 }, + 0, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search355_2 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search355 = { + { nir_search_value_expression, -2 }, + false, + nir_op_bcsel, + { &search355_0.value, &search355_1.value, &search355_2.value }, + NULL, +}; + +static const nir_search_variable replace355 = { + { nir_search_value_variable, -2 }, + 1, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search356_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search356_1_0 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search356_1 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search356_1_0.value }, + (is_used_once), +}; + +static const nir_search_variable search356_2_0 = { + { nir_search_value_variable, 32 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search356_2 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search356_2_0.value }, + NULL, +}; +static const nir_search_expression search356 = { + { nir_search_value_expression, 0 }, + false, + nir_op_bcsel, + { &search356_0.value, &search356_1.value, &search356_2.value }, + NULL, +}; + +static const nir_search_variable replace356_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace356_0_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace356_0_2 = { + { nir_search_value_variable, 32 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace356_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_bcsel, + { &replace356_0_0.value, &replace356_0_1.value, &replace356_0_2.value }, + NULL, +}; +static const nir_search_expression replace356 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &replace356_0.value }, + NULL, +}; + +static const nir_search_variable search357_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search357_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search357_2 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search357 = { + { nir_search_value_expression, -3 }, + false, + nir_op_bcsel, + { &search357_0.value, &search357_1.value, &search357_2.value }, + NULL, +}; + +static const nir_search_variable replace357_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace357_0_1 = { + { nir_search_value_constant, 1 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression replace357_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ine, + { &replace357_0_0.value, &replace357_0_1.value }, + NULL, +}; + +static const nir_search_variable replace357_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace357_2 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace357 = { + { nir_search_value_expression, -3 }, + false, + nir_op_bcsel, + { &replace357_0.value, &replace357_1.value, &replace357_2.value }, + NULL, +}; + +static const nir_search_variable search358_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search358_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search358_2 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search358 = { + { nir_search_value_expression, -2 }, + false, + nir_op_bcsel, + { &search358_0.value, &search358_1.value, &search358_2.value }, + NULL, +}; + +static const nir_search_variable replace358 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search359_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search359_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search359_2 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search359 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fcsel, + { &search359_0.value, &search359_1.value, &search359_2.value }, + NULL, +}; + +static const nir_search_variable replace359 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search360_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search360_1 = { + { nir_search_value_constant, 0 }, + nir_type_int, { -0x1 /* -1 */ }, +}; + +static const nir_search_constant search360_2 = { + { nir_search_value_constant, 0 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression search360 = { + { nir_search_value_expression, 0 }, + false, + nir_op_bcsel, + { &search360_0.value, &search360_1.value, &search360_2.value }, + NULL, +}; + +static const nir_search_variable replace360_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace360_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2i, + { &replace360_0_0.value }, + NULL, +}; +static const nir_search_expression replace360 = { + { nir_search_value_expression, 0 }, + false, + nir_op_ineg, + { &replace360_0.value }, + NULL, +}; + +static const nir_search_variable search361_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search361_1 = { + { nir_search_value_constant, 0 }, + nir_type_int, { 0x0 /* 0 */ }, +}; + +static const nir_search_constant search361_2 = { + { nir_search_value_constant, 0 }, + nir_type_int, { -0x1 /* -1 */ }, +}; +static const nir_search_expression search361 = { + { nir_search_value_expression, 0 }, + false, + nir_op_bcsel, + { &search361_0.value, &search361_1.value, &search361_2.value }, + NULL, +}; + +static const nir_search_variable replace361_0_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace361_0_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &replace361_0_0_0.value }, + NULL, +}; +static const nir_search_expression replace361_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2i, + { &replace361_0_0.value }, + NULL, +}; +static const nir_search_expression replace361 = { + { nir_search_value_expression, 0 }, + false, + nir_op_ineg, + { &replace361_0.value }, + NULL, +}; + +static const nir_search_variable search362_0_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search362_0_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2i, + { &search362_0_0_0.value }, + NULL, +}; +static const nir_search_expression search362_0 = { + { nir_search_value_expression, 0 }, + false, + nir_op_ineg, + { &search362_0_0.value }, + NULL, +}; + +static const nir_search_variable search362_1_0_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search362_1_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2i, + { &search362_1_0_0.value }, + NULL, +}; +static const nir_search_expression search362_1 = { + { nir_search_value_expression, 0 }, + false, + nir_op_ineg, + { &search362_1_0.value }, + NULL, +}; +static const nir_search_expression search362 = { + { nir_search_value_expression, 0 }, + false, + nir_op_iand, + { &search362_0.value, &search362_1.value }, + NULL, +}; + +static const nir_search_variable replace362_0_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace362_0_0_1 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace362_0_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &replace362_0_0_0.value, &replace362_0_0_1.value }, + NULL, +}; +static const nir_search_expression replace362_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2i, + { &replace362_0_0.value }, + NULL, +}; +static const nir_search_expression replace362 = { + { nir_search_value_expression, 0 }, + false, + nir_op_ineg, + { &replace362_0.value }, + NULL, +}; + +static const nir_search_variable search363_0_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search363_0_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2i, + { &search363_0_0_0.value }, + NULL, +}; +static const nir_search_expression search363_0 = { + { nir_search_value_expression, 0 }, + false, + nir_op_ineg, + { &search363_0_0.value }, + NULL, +}; + +static const nir_search_variable search363_1_0_0 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search363_1_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2i, + { &search363_1_0_0.value }, + NULL, +}; +static const nir_search_expression search363_1 = { + { nir_search_value_expression, 0 }, + false, + nir_op_ineg, + { &search363_1_0.value }, + NULL, +}; +static const nir_search_expression search363 = { + { nir_search_value_expression, 0 }, + false, + nir_op_ior, + { &search363_0.value, &search363_1.value }, + NULL, +}; + +static const nir_search_variable replace363_0_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace363_0_0_1 = { + { nir_search_value_variable, 1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace363_0_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &replace363_0_0_0.value, &replace363_0_0_1.value }, + NULL, +}; +static const nir_search_expression replace363_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2i, + { &replace363_0_0.value }, + NULL, +}; +static const nir_search_expression replace363 = { + { nir_search_value_expression, 0 }, + false, + nir_op_ineg, + { &replace363_0.value }, + NULL, +}; + +static const nir_search_variable search364_0_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search364_0_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2i, + { &search364_0_0_0.value }, + NULL, +}; +static const nir_search_expression search364_0 = { + { nir_search_value_expression, 0 }, + false, + nir_op_ineg, + { &search364_0_0.value }, + NULL, +}; + +static const nir_search_constant search364_1 = { + { nir_search_value_constant, 0 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression search364 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ieq, + { &search364_0.value, &search364_1.value }, + NULL, +}; + +static const nir_search_variable replace364_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace364 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &replace364_0.value }, + NULL, +}; + +static const nir_search_variable search365_0_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search365_0_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2i, + { &search365_0_0_0.value }, + NULL, +}; +static const nir_search_expression search365_0 = { + { nir_search_value_expression, 0 }, + false, + nir_op_ineg, + { &search365_0_0.value }, + NULL, +}; + +static const nir_search_constant search365_1 = { + { nir_search_value_constant, 0 }, + nir_type_int, { -0x1 /* -1 */ }, +}; +static const nir_search_expression search365 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ieq, + { &search365_0.value, &search365_1.value }, + NULL, +}; + +static const nir_search_variable replace365 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search366_0_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search366_0_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2i, + { &search366_0_0_0.value }, + NULL, +}; +static const nir_search_expression search366_0 = { + { nir_search_value_expression, 0 }, + false, + nir_op_ineg, + { &search366_0_0.value }, + NULL, +}; + +static const nir_search_constant search366_1 = { + { nir_search_value_constant, 0 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression search366 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ine, + { &search366_0.value, &search366_1.value }, + NULL, +}; + +static const nir_search_variable replace366 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search367_0_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search367_0_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2i, + { &search367_0_0_0.value }, + NULL, +}; +static const nir_search_expression search367_0 = { + { nir_search_value_expression, 0 }, + false, + nir_op_ineg, + { &search367_0_0.value }, + NULL, +}; + +static const nir_search_constant search367_1 = { + { nir_search_value_constant, 0 }, + nir_type_int, { -0x1 /* -1 */ }, +}; +static const nir_search_expression search367 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ine, + { &search367_0.value, &search367_1.value }, + NULL, +}; + +static const nir_search_variable replace367_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace367 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &replace367_0.value }, + NULL, +}; + +static const nir_search_variable search368_0_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search368_0_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2i, + { &search368_0_0_0.value }, + NULL, +}; +static const nir_search_expression search368_0 = { + { nir_search_value_expression, 0 }, + false, + nir_op_ineg, + { &search368_0_0.value }, + NULL, +}; + +static const nir_search_constant search368_1 = { + { nir_search_value_constant, 0 }, + nir_type_float, { 0x3ff0000000000000 /* 1.0 */ }, +}; +static const nir_search_expression search368 = { + { nir_search_value_expression, 0 }, + false, + nir_op_iand, + { &search368_0.value, &search368_1.value }, + NULL, +}; + +static const nir_search_variable replace368_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace368 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &replace368_0.value }, + NULL, +}; + +static const nir_search_variable search369_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search369_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2i, + { &search369_0_0.value }, + NULL, +}; +static const nir_search_expression search369 = { + { nir_search_value_expression, 32 }, + false, + nir_op_i2b32, + { &search369_0.value }, + NULL, +}; + +static const nir_search_variable replace369 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search370_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search370_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_ftrunc, + { &search370_0_0.value }, + NULL, +}; +static const nir_search_expression search370 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_f2i, + { &search370_0.value }, + NULL, +}; + +static const nir_search_variable replace370_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace370 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_f2i, + { &replace370_0.value }, + NULL, +}; + +static const nir_search_variable search371_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search371_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_ftrunc, + { &search371_0_0.value }, + NULL, +}; +static const nir_search_expression search371 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_f2u, + { &search371_0.value }, + NULL, +}; + +static const nir_search_variable replace371_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace371 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_f2u, + { &replace371_0.value }, + NULL, +}; + +static const nir_search_variable search372_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search372_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_ineg, + { &search372_0_0.value }, + NULL, +}; +static const nir_search_expression search372 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_i2b, + { &search372_0.value }, + NULL, +}; + +static const nir_search_variable replace372_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace372 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_i2b, + { &replace372_0.value }, + NULL, +}; + +static const nir_search_variable search373_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search373_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_iabs, + { &search373_0_0.value }, + NULL, +}; +static const nir_search_expression search373 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_i2b, + { &search373_0.value }, + NULL, +}; + +static const nir_search_variable replace373_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace373 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_i2b, + { &replace373_0.value }, + NULL, +}; + +static const nir_search_variable search374_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search374_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search374_0_0.value }, + NULL, +}; +static const nir_search_expression search374 = { + { nir_search_value_expression, 0 }, + false, + nir_op_fabs, + { &search374_0.value }, + NULL, +}; + +static const nir_search_variable replace374_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace374 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &replace374_0.value }, + NULL, +}; + +static const nir_search_variable search375_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search375_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2i, + { &search375_0_0.value }, + NULL, +}; +static const nir_search_expression search375 = { + { nir_search_value_expression, 0 }, + false, + nir_op_iabs, + { &search375_0.value }, + NULL, +}; + +static const nir_search_variable replace375_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace375 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2i, + { &replace375_0.value }, + NULL, +}; + +static const nir_search_variable search376_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search376_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_f2b1, + { &search376_0_0.value }, + NULL, +}; +static const nir_search_expression search376 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &search376_0.value }, + NULL, +}; + +static const nir_search_variable replace376_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace376_1 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression replace376 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &replace376_0.value, &replace376_1.value }, + NULL, +}; + +static const nir_search_variable search377_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search377_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_i2f, + { &search377_0_0.value }, + NULL, +}; +static const nir_search_expression search377 = { + { nir_search_value_expression, 32 }, + true, + nir_op_f2i32, + { &search377_0.value }, + NULL, +}; + +static const nir_search_variable replace377 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search378_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search378_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_u2f, + { &search378_0_0.value }, + NULL, +}; +static const nir_search_expression search378 = { + { nir_search_value_expression, 32 }, + true, + nir_op_f2i32, + { &search378_0.value }, + NULL, +}; + +static const nir_search_variable replace378 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search379_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search379_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_i2f, + { &search379_0_0.value }, + NULL, +}; +static const nir_search_expression search379 = { + { nir_search_value_expression, 32 }, + true, + nir_op_f2u32, + { &search379_0.value }, + NULL, +}; + +static const nir_search_variable replace379 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search380_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search380_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_u2f, + { &search380_0_0.value }, + NULL, +}; +static const nir_search_expression search380 = { + { nir_search_value_expression, 32 }, + true, + nir_op_f2u32, + { &search380_0.value }, + NULL, +}; + +static const nir_search_variable replace380 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search381_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search381_0_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search381_0 = { + { nir_search_value_expression, 64 }, + false, + nir_op_pack_64_2x32_split, + { &search381_0_0.value, &search381_0_1.value }, + NULL, +}; +static const nir_search_expression search381 = { + { nir_search_value_expression, 32 }, + false, + nir_op_unpack_64_2x32_split_x, + { &search381_0.value }, + NULL, +}; + +static const nir_search_variable replace381 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search382_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search382_0_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search382_0 = { + { nir_search_value_expression, 64 }, + false, + nir_op_pack_64_2x32_split, + { &search382_0_0.value, &search382_0_1.value }, + NULL, +}; +static const nir_search_expression search382 = { + { nir_search_value_expression, 32 }, + false, + nir_op_unpack_64_2x32_split_y, + { &search382_0.value }, + NULL, +}; + +static const nir_search_variable replace382 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search383_0_0 = { + { nir_search_value_variable, 64 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search383_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_unpack_64_2x32_split_x, + { &search383_0_0.value }, + NULL, +}; + +static const nir_search_variable search383_1_0 = { + { nir_search_value_variable, 64 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search383_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_unpack_64_2x32_split_y, + { &search383_1_0.value }, + NULL, +}; +static const nir_search_expression search383 = { + { nir_search_value_expression, 64 }, + false, + nir_op_pack_64_2x32_split, + { &search383_0.value, &search383_1.value }, + NULL, +}; + +static const nir_search_variable replace383 = { + { nir_search_value_variable, 64 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search384_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search384_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x18 /* 24 */ }, +}; +static const nir_search_expression search384_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search384_0_0.value, &search384_0_1.value }, + NULL, +}; + +static const nir_search_constant search384_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x18 /* 24 */ }, +}; +static const nir_search_expression search384 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search384_0.value, &search384_1.value }, + NULL, +}; + +static const nir_search_variable replace384_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace384_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression replace384 = { + { nir_search_value_expression, 32 }, + false, + nir_op_extract_u8, + { &replace384_0.value, &replace384_1.value }, + NULL, +}; + +static const nir_search_variable search385_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search385_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search385_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search385_0_0.value, &search385_0_1.value }, + NULL, +}; + +static const nir_search_constant search385_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x18 /* 24 */ }, +}; +static const nir_search_expression search385 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search385_0.value, &search385_1.value }, + NULL, +}; + +static const nir_search_variable replace385_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace385_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x1 /* 1 */ }, +}; +static const nir_search_expression replace385 = { + { nir_search_value_expression, 32 }, + false, + nir_op_extract_u8, + { &replace385_0.value, &replace385_1.value }, + NULL, +}; + +static const nir_search_variable search386_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search386_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x8 /* 8 */ }, +}; +static const nir_search_expression search386_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search386_0_0.value, &search386_0_1.value }, + NULL, +}; + +static const nir_search_constant search386_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x18 /* 24 */ }, +}; +static const nir_search_expression search386 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search386_0.value, &search386_1.value }, + NULL, +}; + +static const nir_search_variable replace386_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace386_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x2 /* 2 */ }, +}; +static const nir_search_expression replace386 = { + { nir_search_value_expression, 32 }, + false, + nir_op_extract_u8, + { &replace386_0.value, &replace386_1.value }, + NULL, +}; + +static const nir_search_variable search387_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search387_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x18 /* 24 */ }, +}; +static const nir_search_expression search387 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search387_0.value, &search387_1.value }, + NULL, +}; + +static const nir_search_variable replace387_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace387_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x3 /* 3 */ }, +}; +static const nir_search_expression replace387 = { + { nir_search_value_expression, 32 }, + false, + nir_op_extract_u8, + { &replace387_0.value, &replace387_1.value }, + NULL, +}; + +static const nir_search_variable search388_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search388_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x18 /* 24 */ }, +}; +static const nir_search_expression search388_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search388_0_0.value, &search388_0_1.value }, + NULL, +}; + +static const nir_search_constant search388_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x18 /* 24 */ }, +}; +static const nir_search_expression search388 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishr, + { &search388_0.value, &search388_1.value }, + NULL, +}; + +static const nir_search_variable replace388_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace388_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression replace388 = { + { nir_search_value_expression, 32 }, + false, + nir_op_extract_i8, + { &replace388_0.value, &replace388_1.value }, + NULL, +}; + +static const nir_search_variable search389_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search389_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search389_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search389_0_0.value, &search389_0_1.value }, + NULL, +}; + +static const nir_search_constant search389_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x18 /* 24 */ }, +}; +static const nir_search_expression search389 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishr, + { &search389_0.value, &search389_1.value }, + NULL, +}; + +static const nir_search_variable replace389_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace389_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x1 /* 1 */ }, +}; +static const nir_search_expression replace389 = { + { nir_search_value_expression, 32 }, + false, + nir_op_extract_i8, + { &replace389_0.value, &replace389_1.value }, + NULL, +}; + +static const nir_search_variable search390_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search390_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x8 /* 8 */ }, +}; +static const nir_search_expression search390_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search390_0_0.value, &search390_0_1.value }, + NULL, +}; + +static const nir_search_constant search390_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x18 /* 24 */ }, +}; +static const nir_search_expression search390 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishr, + { &search390_0.value, &search390_1.value }, + NULL, +}; + +static const nir_search_variable replace390_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace390_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x2 /* 2 */ }, +}; +static const nir_search_expression replace390 = { + { nir_search_value_expression, 32 }, + false, + nir_op_extract_i8, + { &replace390_0.value, &replace390_1.value }, + NULL, +}; + +static const nir_search_variable search391_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search391_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x18 /* 24 */ }, +}; +static const nir_search_expression search391 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishr, + { &search391_0.value, &search391_1.value }, + NULL, +}; + +static const nir_search_variable replace391_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace391_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x3 /* 3 */ }, +}; +static const nir_search_expression replace391 = { + { nir_search_value_expression, 32 }, + false, + nir_op_extract_i8, + { &replace391_0.value, &replace391_1.value }, + NULL, +}; + +static const nir_search_constant search392_0 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0xff /* 255 */ }, +}; + +static const nir_search_variable search392_1_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search392_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search392_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_ushr, + { &search392_1_0.value, &search392_1_1.value }, + NULL, +}; +static const nir_search_expression search392 = { + { nir_search_value_expression, -1 }, + false, + nir_op_iand, + { &search392_0.value, &search392_1.value }, + NULL, +}; + +static const nir_search_variable replace392_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace392_1 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0x2 /* 2 */ }, +}; +static const nir_search_expression replace392 = { + { nir_search_value_expression, -1 }, + false, + nir_op_extract_u8, + { &replace392_0.value, &replace392_1.value }, + NULL, +}; + +static const nir_search_constant search393_0 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0xff /* 255 */ }, +}; + +static const nir_search_variable search393_1_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search393_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x8 /* 8 */ }, +}; +static const nir_search_expression search393_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_ushr, + { &search393_1_0.value, &search393_1_1.value }, + NULL, +}; +static const nir_search_expression search393 = { + { nir_search_value_expression, -1 }, + false, + nir_op_iand, + { &search393_0.value, &search393_1.value }, + NULL, +}; + +static const nir_search_variable replace393_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace393_1 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0x1 /* 1 */ }, +}; +static const nir_search_expression replace393 = { + { nir_search_value_expression, -1 }, + false, + nir_op_extract_u8, + { &replace393_0.value, &replace393_1.value }, + NULL, +}; + +static const nir_search_constant search394_0 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0xff /* 255 */ }, +}; + +static const nir_search_variable search394_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search394 = { + { nir_search_value_expression, -1 }, + false, + nir_op_iand, + { &search394_0.value, &search394_1.value }, + NULL, +}; + +static const nir_search_variable replace394_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace394_1 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression replace394 = { + { nir_search_value_expression, -1 }, + false, + nir_op_extract_u8, + { &replace394_0.value, &replace394_1.value }, + NULL, +}; + +static const nir_search_variable search395_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search395_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search395_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search395_0_0.value, &search395_0_1.value }, + NULL, +}; + +static const nir_search_constant search395_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search395 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search395_0.value, &search395_1.value }, + NULL, +}; + +static const nir_search_variable replace395_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace395_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression replace395 = { + { nir_search_value_expression, 32 }, + false, + nir_op_extract_u16, + { &replace395_0.value, &replace395_1.value }, + NULL, +}; + +static const nir_search_variable search396_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search396_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search396 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search396_0.value, &search396_1.value }, + NULL, +}; + +static const nir_search_variable replace396_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace396_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x1 /* 1 */ }, +}; +static const nir_search_expression replace396 = { + { nir_search_value_expression, 32 }, + false, + nir_op_extract_u16, + { &replace396_0.value, &replace396_1.value }, + NULL, +}; + +static const nir_search_variable search397_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search397_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search397_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search397_0_0.value, &search397_0_1.value }, + NULL, +}; + +static const nir_search_constant search397_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search397 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishr, + { &search397_0.value, &search397_1.value }, + NULL, +}; + +static const nir_search_variable replace397_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace397_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression replace397 = { + { nir_search_value_expression, 32 }, + false, + nir_op_extract_i16, + { &replace397_0.value, &replace397_1.value }, + NULL, +}; + +static const nir_search_variable search398_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search398_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search398 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishr, + { &search398_0.value, &search398_1.value }, + NULL, +}; + +static const nir_search_variable replace398_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace398_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x1 /* 1 */ }, +}; +static const nir_search_expression replace398 = { + { nir_search_value_expression, 32 }, + false, + nir_op_extract_i16, + { &replace398_0.value, &replace398_1.value }, + NULL, +}; + +static const nir_search_constant search399_0 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0xffff /* 65535 */ }, +}; + +static const nir_search_variable search399_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search399 = { + { nir_search_value_expression, -1 }, + false, + nir_op_iand, + { &search399_0.value, &search399_1.value }, + NULL, +}; + +static const nir_search_variable replace399_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace399_1 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression replace399 = { + { nir_search_value_expression, -1 }, + false, + nir_op_extract_u16, + { &replace399_0.value, &replace399_1.value }, + NULL, +}; + +static const nir_search_variable search400_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search400_1_0 = { + { nir_search_value_constant, -2 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; + +static const nir_search_variable search400_1_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search400_1 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fsub, + { &search400_1_0.value, &search400_1_1.value }, + NULL, +}; +static const nir_search_expression search400 = { + { nir_search_value_expression, -2 }, + true, + nir_op_fsub, + { &search400_0.value, &search400_1.value }, + NULL, +}; + +static const nir_search_variable replace400_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace400_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace400 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fadd, + { &replace400_0.value, &replace400_1.value }, + NULL, +}; + +static const nir_search_variable search401_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search401_1_0 = { + { nir_search_value_constant, -2 }, + nir_type_int, { 0x0 /* 0 */ }, +}; + +static const nir_search_variable search401_1_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search401_1 = { + { nir_search_value_expression, -2 }, + false, + nir_op_isub, + { &search401_1_0.value, &search401_1_1.value }, + NULL, +}; +static const nir_search_expression search401 = { + { nir_search_value_expression, -2 }, + false, + nir_op_isub, + { &search401_0.value, &search401_1.value }, + NULL, +}; + +static const nir_search_variable replace401_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace401_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace401 = { + { nir_search_value_expression, -2 }, + false, + nir_op_iadd, + { &replace401_0.value, &replace401_1.value }, + NULL, +}; + +static const nir_search_variable search402_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search402_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression search402 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ussub_4x8, + { &search402_0.value, &search402_1.value }, + NULL, +}; + +static const nir_search_variable replace402 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search403_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search403_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { -0x1 /* -1 */ }, +}; +static const nir_search_expression search403 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ussub_4x8, + { &search403_0.value, &search403_1.value }, + NULL, +}; + +static const nir_search_constant replace403 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x0 /* 0 */ }, +}; + +static const nir_search_variable search404_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search404_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search404 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fsub, + { &search404_0.value, &search404_1.value }, + NULL, +}; + +static const nir_search_variable replace404_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace404_1_0 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace404_1 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fneg, + { &replace404_1_0.value }, + NULL, +}; +static const nir_search_expression replace404 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fadd, + { &replace404_0.value, &replace404_1.value }, + NULL, +}; + +static const nir_search_variable search405_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search405_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search405 = { + { nir_search_value_expression, -2 }, + false, + nir_op_isub, + { &search405_0.value, &search405_1.value }, + NULL, +}; + +static const nir_search_variable replace405_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace405_1_0 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace405_1 = { + { nir_search_value_expression, -2 }, + false, + nir_op_ineg, + { &replace405_1_0.value }, + NULL, +}; +static const nir_search_expression replace405 = { + { nir_search_value_expression, -2 }, + false, + nir_op_iadd, + { &replace405_0.value, &replace405_1.value }, + NULL, +}; + +static const nir_search_variable search406_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search406 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fneg, + { &search406_0.value }, + NULL, +}; + +static const nir_search_constant replace406_0 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; + +static const nir_search_variable replace406_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace406 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fsub, + { &replace406_0.value, &replace406_1.value }, + NULL, +}; + +static const nir_search_variable search407_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search407 = { + { nir_search_value_expression, -1 }, + false, + nir_op_ineg, + { &search407_0.value }, + NULL, +}; + +static const nir_search_constant replace407_0 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0x0 /* 0 */ }, +}; + +static const nir_search_variable replace407_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace407 = { + { nir_search_value_expression, -1 }, + false, + nir_op_isub, + { &replace407_0.value, &replace407_1.value }, + NULL, +}; + +static const nir_search_variable search408_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search408_1_0 = { + { nir_search_value_constant, -2 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; + +static const nir_search_variable search408_1_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search408_1 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fsub, + { &search408_1_0.value, &search408_1_1.value }, + NULL, +}; +static const nir_search_expression search408 = { + { nir_search_value_expression, -2 }, + true, + nir_op_fadd, + { &search408_0.value, &search408_1.value }, + NULL, +}; + +static const nir_search_variable replace408_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace408_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace408 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fsub, + { &replace408_0.value, &replace408_1.value }, + NULL, +}; + +static const nir_search_variable search409_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search409_1_0 = { + { nir_search_value_constant, -2 }, + nir_type_int, { 0x0 /* 0 */ }, +}; + +static const nir_search_variable search409_1_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search409_1 = { + { nir_search_value_expression, -2 }, + false, + nir_op_isub, + { &search409_1_0.value, &search409_1_1.value }, + NULL, +}; +static const nir_search_expression search409 = { + { nir_search_value_expression, -2 }, + false, + nir_op_iadd, + { &search409_0.value, &search409_1.value }, + NULL, +}; + +static const nir_search_variable replace409_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace409_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace409 = { + { nir_search_value_expression, -2 }, + false, + nir_op_isub, + { &replace409_0.value, &replace409_1.value }, + NULL, +}; + +static const nir_search_constant search410_0_0 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; + +static const nir_search_variable search410_0_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search410_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fsub, + { &search410_0_0.value, &search410_0_1.value }, + NULL, +}; +static const nir_search_expression search410 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fabs, + { &search410_0.value }, + NULL, +}; + +static const nir_search_variable replace410_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace410 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fabs, + { &replace410_0.value }, + NULL, +}; + +static const nir_search_constant search411_0_0 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0x0 /* 0 */ }, +}; + +static const nir_search_variable search411_0_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search411_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_isub, + { &search411_0_0.value, &search411_0_1.value }, + NULL, +}; +static const nir_search_expression search411 = { + { nir_search_value_expression, -1 }, + false, + nir_op_iabs, + { &search411_0.value }, + NULL, +}; + +static const nir_search_variable replace411_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace411 = { + { nir_search_value_expression, -1 }, + false, + nir_op_iabs, + { &replace411_0.value }, + NULL, +}; + +static const nir_search_variable search412_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search412_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fneg, + { &search412_0_0.value }, + NULL, +}; + +static const nir_search_variable search412_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search412 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fmul, + { &search412_0.value, &search412_1.value }, + NULL, +}; + +static const nir_search_variable replace412_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace412_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace412_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fmul, + { &replace412_0_0.value, &replace412_0_1.value }, + NULL, +}; +static const nir_search_expression replace412 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fneg, + { &replace412_0.value }, + NULL, +}; + +static const nir_search_variable search413_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search413_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_ineg, + { &search413_0_0.value }, + NULL, +}; + +static const nir_search_variable search413_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search413 = { + { nir_search_value_expression, -2 }, + false, + nir_op_imul, + { &search413_0.value, &search413_1.value }, + NULL, +}; + +static const nir_search_variable replace413_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace413_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace413_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_imul, + { &replace413_0_0.value, &replace413_0_1.value }, + NULL, +}; +static const nir_search_expression replace413 = { + { nir_search_value_expression, -2 }, + false, + nir_op_ineg, + { &replace413_0.value }, + NULL, +}; + +static const nir_search_variable search414_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + (is_not_const), +}; + +static const nir_search_variable search414_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + (is_not_const), +}; +static const nir_search_expression search414_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fmul, + { &search414_0_0.value, &search414_0_1.value }, + (is_used_once), +}; + +static const nir_search_variable search414_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search414 = { + { nir_search_value_expression, -3 }, + true, + nir_op_fmul, + { &search414_0.value, &search414_1.value }, + (is_used_once), +}; + +static const nir_search_variable replace414_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace414_0_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace414_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fmul, + { &replace414_0_0.value, &replace414_0_1.value }, + NULL, +}; + +static const nir_search_variable replace414_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace414 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fmul, + { &replace414_0.value, &replace414_1.value }, + NULL, +}; + +static const nir_search_variable search415_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + (is_not_const), +}; + +static const nir_search_variable search415_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + (is_not_const), +}; +static const nir_search_expression search415_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_imul, + { &search415_0_0.value, &search415_0_1.value }, + (is_used_once), +}; + +static const nir_search_variable search415_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search415 = { + { nir_search_value_expression, -3 }, + false, + nir_op_imul, + { &search415_0.value, &search415_1.value }, + (is_used_once), +}; + +static const nir_search_variable replace415_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace415_0_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace415_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_imul, + { &replace415_0_0.value, &replace415_0_1.value }, + NULL, +}; + +static const nir_search_variable replace415_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace415 = { + { nir_search_value_expression, -3 }, + false, + nir_op_imul, + { &replace415_0.value, &replace415_1.value }, + NULL, +}; + +static const nir_search_variable search416_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + (is_not_const), +}; + +static const nir_search_variable search416_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + (is_not_const), +}; +static const nir_search_expression search416_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fadd, + { &search416_0_0.value, &search416_0_1.value }, + (is_used_once), +}; + +static const nir_search_variable search416_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search416 = { + { nir_search_value_expression, -3 }, + true, + nir_op_fadd, + { &search416_0.value, &search416_1.value }, + (is_used_once), +}; + +static const nir_search_variable replace416_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace416_0_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace416_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fadd, + { &replace416_0_0.value, &replace416_0_1.value }, + NULL, +}; + +static const nir_search_variable replace416_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace416 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fadd, + { &replace416_0.value, &replace416_1.value }, + NULL, +}; + +static const nir_search_variable search417_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + (is_not_const), +}; + +static const nir_search_variable search417_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + (is_not_const), +}; +static const nir_search_expression search417_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_iadd, + { &search417_0_0.value, &search417_0_1.value }, + (is_used_once), +}; + +static const nir_search_variable search417_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search417 = { + { nir_search_value_expression, -3 }, + false, + nir_op_iadd, + { &search417_0.value, &search417_1.value }, + (is_used_once), +}; + +static const nir_search_variable replace417_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace417_0_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace417_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_iadd, + { &replace417_0_0.value, &replace417_0_1.value }, + NULL, +}; + +static const nir_search_variable replace417_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace417 = { + { nir_search_value_expression, -3 }, + false, + nir_op_iadd, + { &replace417_0.value, &replace417_1.value }, + NULL, +}; + +static const nir_search_variable search418_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search418_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + (is_not_const), +}; + +static const nir_search_variable search418_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search418_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fmul, + { &search418_1_0.value, &search418_1_1.value }, + NULL, +}; +static const nir_search_expression search418 = { + { nir_search_value_expression, -3 }, + true, + nir_op_fmul, + { &search418_0.value, &search418_1.value }, + NULL, +}; + +static const nir_search_variable replace418_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace418_0_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace418_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fmul, + { &replace418_0_0.value, &replace418_0_1.value }, + NULL, +}; + +static const nir_search_variable replace418_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace418 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fmul, + { &replace418_0.value, &replace418_1.value }, + NULL, +}; + +static const nir_search_variable search419_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search419_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + (is_not_const), +}; + +static const nir_search_variable search419_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search419_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_imul, + { &search419_1_0.value, &search419_1_1.value }, + NULL, +}; +static const nir_search_expression search419 = { + { nir_search_value_expression, -3 }, + false, + nir_op_imul, + { &search419_0.value, &search419_1.value }, + NULL, +}; + +static const nir_search_variable replace419_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace419_0_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace419_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_imul, + { &replace419_0_0.value, &replace419_0_1.value }, + NULL, +}; + +static const nir_search_variable replace419_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace419 = { + { nir_search_value_expression, -3 }, + false, + nir_op_imul, + { &replace419_0.value, &replace419_1.value }, + NULL, +}; + +static const nir_search_variable search420_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search420_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + (is_not_const), +}; + +static const nir_search_variable search420_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search420_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fadd, + { &search420_1_0.value, &search420_1_1.value }, + NULL, +}; +static const nir_search_expression search420 = { + { nir_search_value_expression, -3 }, + true, + nir_op_fadd, + { &search420_0.value, &search420_1.value }, + NULL, +}; + +static const nir_search_variable replace420_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace420_0_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace420_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fadd, + { &replace420_0_0.value, &replace420_0_1.value }, + NULL, +}; + +static const nir_search_variable replace420_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace420 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fadd, + { &replace420_0.value, &replace420_1.value }, + NULL, +}; + +static const nir_search_variable search421_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search421_1_0_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + (is_not_const), +}; + +static const nir_search_variable search421_1_0_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search421_1_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fadd, + { &search421_1_0_0.value, &search421_1_0_1.value }, + NULL, +}; +static const nir_search_expression search421_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fneg, + { &search421_1_0.value }, + NULL, +}; +static const nir_search_expression search421 = { + { nir_search_value_expression, -3 }, + true, + nir_op_fadd, + { &search421_0.value, &search421_1.value }, + NULL, +}; + +static const nir_search_variable replace421_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace421_0_1_0 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace421_0_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fneg, + { &replace421_0_1_0.value }, + NULL, +}; +static const nir_search_expression replace421_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fadd, + { &replace421_0_0.value, &replace421_0_1.value }, + NULL, +}; + +static const nir_search_variable replace421_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace421_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fneg, + { &replace421_1_0.value }, + NULL, +}; +static const nir_search_expression replace421 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fadd, + { &replace421_0.value, &replace421_1.value }, + NULL, +}; + +static const nir_search_variable search422_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search422_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + (is_not_const), +}; + +static const nir_search_variable search422_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search422_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_iadd, + { &search422_1_0.value, &search422_1_1.value }, + NULL, +}; +static const nir_search_expression search422 = { + { nir_search_value_expression, -3 }, + false, + nir_op_iadd, + { &search422_0.value, &search422_1.value }, + NULL, +}; + +static const nir_search_variable replace422_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace422_0_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace422_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_iadd, + { &replace422_0_0.value, &replace422_0_1.value }, + NULL, +}; + +static const nir_search_variable replace422_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace422 = { + { nir_search_value_expression, -3 }, + false, + nir_op_iadd, + { &replace422_0.value, &replace422_1.value }, + NULL, +}; + +static const nir_search_variable search423_0_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search423_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_find_lsb, + { &search423_0_0_0.value }, + NULL, +}; + +static const nir_search_constant search423_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression search423_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &search423_0_0.value, &search423_0_1.value }, + NULL, +}; + +static const nir_search_variable search423_1_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search423_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_find_lsb, + { &search423_1_0.value }, + NULL, +}; + +static const nir_search_constant search423_2 = { + { nir_search_value_constant, 32 }, + nir_type_int, { -0x1 /* -1 */ }, +}; +static const nir_search_expression search423 = { + { nir_search_value_expression, 32 }, + false, + nir_op_bcsel, + { &search423_0.value, &search423_1.value, &search423_2.value }, + NULL, +}; + +static const nir_search_variable replace423_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace423 = { + { nir_search_value_expression, 32 }, + false, + nir_op_find_lsb, + { &replace423_0.value }, + NULL, +}; + +static const nir_search_variable search424_0_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search424_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ifind_msb, + { &search424_0_0_0.value }, + NULL, +}; + +static const nir_search_constant search424_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression search424_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &search424_0_0.value, &search424_0_1.value }, + NULL, +}; + +static const nir_search_variable search424_1_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search424_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ifind_msb, + { &search424_1_0.value }, + NULL, +}; + +static const nir_search_constant search424_2 = { + { nir_search_value_constant, 32 }, + nir_type_int, { -0x1 /* -1 */ }, +}; +static const nir_search_expression search424 = { + { nir_search_value_expression, 32 }, + false, + nir_op_bcsel, + { &search424_0.value, &search424_1.value, &search424_2.value }, + NULL, +}; + +static const nir_search_variable replace424_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace424 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ifind_msb, + { &replace424_0.value }, + NULL, +}; + +static const nir_search_variable search425_0_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search425_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ufind_msb, + { &search425_0_0_0.value }, + NULL, +}; + +static const nir_search_constant search425_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression search425_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &search425_0_0.value, &search425_0_1.value }, + NULL, +}; + +static const nir_search_variable search425_1_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search425_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ufind_msb, + { &search425_1_0.value }, + NULL, +}; + +static const nir_search_constant search425_2 = { + { nir_search_value_constant, 32 }, + nir_type_int, { -0x1 /* -1 */ }, +}; +static const nir_search_expression search425 = { + { nir_search_value_expression, 32 }, + false, + nir_op_bcsel, + { &search425_0.value, &search425_1.value, &search425_2.value }, + NULL, +}; + +static const nir_search_variable replace425_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace425 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ufind_msb, + { &replace425_0.value }, + NULL, +}; + +static const nir_search_variable search426_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search426_0_1 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression search426_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ine, + { &search426_0_0.value, &search426_0_1.value }, + NULL, +}; + +static const nir_search_variable search426_1_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search426_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_find_lsb, + { &search426_1_0.value }, + NULL, +}; + +static const nir_search_constant search426_2 = { + { nir_search_value_constant, 32 }, + nir_type_int, { -0x1 /* -1 */ }, +}; +static const nir_search_expression search426 = { + { nir_search_value_expression, 32 }, + false, + nir_op_bcsel, + { &search426_0.value, &search426_1.value, &search426_2.value }, + NULL, +}; + +static const nir_search_variable replace426_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace426 = { + { nir_search_value_expression, 32 }, + false, + nir_op_find_lsb, + { &replace426_0.value }, + NULL, +}; + +static const nir_search_variable search427_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search427_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression search427_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ine, + { &search427_0_0.value, &search427_0_1.value }, + NULL, +}; + +static const nir_search_variable search427_1_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search427_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ifind_msb, + { &search427_1_0.value }, + NULL, +}; + +static const nir_search_constant search427_2 = { + { nir_search_value_constant, 32 }, + nir_type_int, { -0x1 /* -1 */ }, +}; +static const nir_search_expression search427 = { + { nir_search_value_expression, 32 }, + false, + nir_op_bcsel, + { &search427_0.value, &search427_1.value, &search427_2.value }, + NULL, +}; + +static const nir_search_variable replace427_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace427 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ifind_msb, + { &replace427_0.value }, + NULL, +}; + +static const nir_search_variable search428_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search428_0_1 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression search428_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ine, + { &search428_0_0.value, &search428_0_1.value }, + NULL, +}; + +static const nir_search_variable search428_1_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search428_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ufind_msb, + { &search428_1_0.value }, + NULL, +}; + +static const nir_search_constant search428_2 = { + { nir_search_value_constant, 32 }, + nir_type_int, { -0x1 /* -1 */ }, +}; +static const nir_search_expression search428 = { + { nir_search_value_expression, 32 }, + false, + nir_op_bcsel, + { &search428_0.value, &search428_1.value, &search428_2.value }, + NULL, +}; + +static const nir_search_variable replace428_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace428 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ufind_msb, + { &replace428_0.value }, + NULL, +}; + +static const nir_search_variable search429_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search429_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { -0x1 /* -1 */ }, +}; +static const nir_search_expression search429_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ine, + { &search429_0_0.value, &search429_0_1.value }, + NULL, +}; + +static const nir_search_variable search429_1_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search429_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ifind_msb, + { &search429_1_0.value }, + NULL, +}; + +static const nir_search_constant search429_2 = { + { nir_search_value_constant, 32 }, + nir_type_int, { -0x1 /* -1 */ }, +}; +static const nir_search_expression search429 = { + { nir_search_value_expression, 32 }, + false, + nir_op_bcsel, + { &search429_0.value, &search429_1.value, &search429_2.value }, + NULL, +}; + +static const nir_search_variable replace429_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace429 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ifind_msb, + { &replace429_0.value }, + NULL, +}; + +static const nir_search_variable search430_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search430_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search430 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fmod, + { &search430_0.value, &search430_1.value }, + NULL, +}; + +static const nir_search_variable replace430_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace430_1_0 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace430_1_1_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace430_1_1_0_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace430_1_1_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fdiv, + { &replace430_1_1_0_0.value, &replace430_1_1_0_1.value }, + NULL, +}; +static const nir_search_expression replace430_1_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ffloor, + { &replace430_1_1_0.value }, + NULL, +}; +static const nir_search_expression replace430_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fmul, + { &replace430_1_0.value, &replace430_1_1.value }, + NULL, +}; +static const nir_search_expression replace430 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fsub, + { &replace430_0.value, &replace430_1.value }, + NULL, +}; + +static const nir_search_variable search431_0 = { + { nir_search_value_variable, 64 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search431_1 = { + { nir_search_value_variable, 64 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search431 = { + { nir_search_value_expression, 64 }, + false, + nir_op_fmod, + { &search431_0.value, &search431_1.value }, + NULL, +}; + +static const nir_search_variable replace431_0 = { + { nir_search_value_variable, 64 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace431_1_0 = { + { nir_search_value_variable, 64 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace431_1_1_0_0 = { + { nir_search_value_variable, 64 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace431_1_1_0_1 = { + { nir_search_value_variable, 64 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace431_1_1_0 = { + { nir_search_value_expression, 64 }, + false, + nir_op_fdiv, + { &replace431_1_1_0_0.value, &replace431_1_1_0_1.value }, + NULL, +}; +static const nir_search_expression replace431_1_1 = { + { nir_search_value_expression, 64 }, + false, + nir_op_ffloor, + { &replace431_1_1_0.value }, + NULL, +}; +static const nir_search_expression replace431_1 = { + { nir_search_value_expression, 64 }, + false, + nir_op_fmul, + { &replace431_1_0.value, &replace431_1_1.value }, + NULL, +}; +static const nir_search_expression replace431 = { + { nir_search_value_expression, 64 }, + false, + nir_op_fsub, + { &replace431_0.value, &replace431_1.value }, + NULL, +}; + +static const nir_search_variable search432_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search432_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search432 = { + { nir_search_value_expression, -2 }, + false, + nir_op_frem, + { &search432_0.value, &search432_1.value }, + NULL, +}; + +static const nir_search_variable replace432_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace432_1_0 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace432_1_1_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace432_1_1_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace432_1_1_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fdiv, + { &replace432_1_1_0_0.value, &replace432_1_1_0_1.value }, + NULL, +}; +static const nir_search_expression replace432_1_1 = { + { nir_search_value_expression, -2 }, + false, + nir_op_ftrunc, + { &replace432_1_1_0.value }, + NULL, +}; +static const nir_search_expression replace432_1 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fmul, + { &replace432_1_0.value, &replace432_1_1.value }, + NULL, +}; +static const nir_search_expression replace432 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fsub, + { &replace432_0.value, &replace432_1.value }, + NULL, +}; + +static const nir_search_variable search433_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search433_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search433 = { + { nir_search_value_expression, 32 }, + false, + nir_op_uadd_carry, + { &search433_0.value, &search433_1.value }, + NULL, +}; + +static const nir_search_variable replace433_0_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace433_0_0_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace433_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iadd, + { &replace433_0_0_0.value, &replace433_0_0_1.value }, + NULL, +}; + +static const nir_search_variable replace433_0_1 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace433_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &replace433_0_0.value, &replace433_0_1.value }, + NULL, +}; +static const nir_search_expression replace433 = { + { nir_search_value_expression, 32 }, + false, + nir_search_op_b2i, + { &replace433_0.value }, + NULL, +}; + +static const nir_search_variable search434_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search434_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search434 = { + { nir_search_value_expression, 32 }, + false, + nir_op_usub_borrow, + { &search434_0.value, &search434_1.value }, + NULL, +}; + +static const nir_search_variable replace434_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace434_0_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace434_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &replace434_0_0.value, &replace434_0_1.value }, + NULL, +}; +static const nir_search_expression replace434 = { + { nir_search_value_expression, 32 }, + false, + nir_search_op_b2i, + { &replace434_0.value }, + NULL, +}; + +static const nir_search_variable search435_0 = { + { nir_search_value_variable, 32 }, + 0, /* base */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search435_1 = { + { nir_search_value_variable, 32 }, + 1, /* insert */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search435_2 = { + { nir_search_value_variable, 32 }, + 2, /* offset */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search435_3 = { + { nir_search_value_variable, 32 }, + 3, /* bits */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search435 = { + { nir_search_value_expression, 32 }, + false, + nir_op_bitfield_insert, + { &search435_0.value, &search435_1.value, &search435_2.value, &search435_3.value }, + NULL, +}; + +static const nir_search_constant replace435_0_0 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x1f /* 31 */ }, +}; + +static const nir_search_variable replace435_0_1 = { + { nir_search_value_variable, 32 }, + 3, /* bits */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace435_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &replace435_0_0.value, &replace435_0_1.value }, + NULL, +}; + +static const nir_search_variable replace435_1 = { + { nir_search_value_variable, 32 }, + 1, /* insert */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace435_2_0_0 = { + { nir_search_value_variable, 32 }, + 3, /* bits */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace435_2_0_1 = { + { nir_search_value_variable, 32 }, + 2, /* offset */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace435_2_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_bfm, + { &replace435_2_0_0.value, &replace435_2_0_1.value }, + NULL, +}; + +static const nir_search_variable replace435_2_1 = { + { nir_search_value_variable, 32 }, + 1, /* insert */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace435_2_2 = { + { nir_search_value_variable, 32 }, + 0, /* base */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace435_2 = { + { nir_search_value_expression, 32 }, + false, + nir_op_bfi, + { &replace435_2_0.value, &replace435_2_1.value, &replace435_2_2.value }, + NULL, +}; +static const nir_search_expression replace435 = { + { nir_search_value_expression, 32 }, + false, + nir_op_bcsel, + { &replace435_0.value, &replace435_1.value, &replace435_2.value }, + NULL, +}; + +static const nir_search_variable search436_0 = { + { nir_search_value_variable, 32 }, + 0, /* base */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search436_1 = { + { nir_search_value_variable, 32 }, + 1, /* insert */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search436_2 = { + { nir_search_value_variable, 32 }, + 2, /* offset */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search436_3 = { + { nir_search_value_variable, 32 }, + 3, /* bits */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search436 = { + { nir_search_value_expression, 32 }, + false, + nir_op_bitfield_insert, + { &search436_0.value, &search436_1.value, &search436_2.value, &search436_3.value }, + NULL, +}; + +static const nir_search_constant replace436_0_0 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x1f /* 31 */ }, +}; + +static const nir_search_variable replace436_0_1 = { + { nir_search_value_variable, 32 }, + 3, /* bits */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace436_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &replace436_0_0.value, &replace436_0_1.value }, + NULL, +}; + +static const nir_search_variable replace436_1 = { + { nir_search_value_variable, 32 }, + 1, /* insert */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace436_2_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* base */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace436_2_0_1_0_0 = { + { nir_search_value_variable, 32 }, + 3, /* bits */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace436_2_0_1_0_1 = { + { nir_search_value_variable, 32 }, + 2, /* offset */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace436_2_0_1_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_bfm, + { &replace436_2_0_1_0_0.value, &replace436_2_0_1_0_1.value }, + NULL, +}; +static const nir_search_expression replace436_2_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_inot, + { &replace436_2_0_1_0.value }, + NULL, +}; +static const nir_search_expression replace436_2_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iand, + { &replace436_2_0_0.value, &replace436_2_0_1.value }, + NULL, +}; + +static const nir_search_variable replace436_2_1_0_0 = { + { nir_search_value_variable, 32 }, + 1, /* insert */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace436_2_1_0_1 = { + { nir_search_value_variable, 32 }, + 2, /* offset */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace436_2_1_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &replace436_2_1_0_0.value, &replace436_2_1_0_1.value }, + NULL, +}; + +static const nir_search_variable replace436_2_1_1_0 = { + { nir_search_value_variable, 32 }, + 3, /* bits */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace436_2_1_1_1 = { + { nir_search_value_variable, 32 }, + 2, /* offset */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace436_2_1_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_bfm, + { &replace436_2_1_1_0.value, &replace436_2_1_1_1.value }, + NULL, +}; +static const nir_search_expression replace436_2_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iand, + { &replace436_2_1_0.value, &replace436_2_1_1.value }, + NULL, +}; +static const nir_search_expression replace436_2 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ior, + { &replace436_2_0.value, &replace436_2_1.value }, + NULL, +}; +static const nir_search_expression replace436 = { + { nir_search_value_expression, 32 }, + false, + nir_op_bcsel, + { &replace436_0.value, &replace436_1.value, &replace436_2.value }, + NULL, +}; + +static const nir_search_variable search437_0 = { + { nir_search_value_variable, 32 }, + 0, /* bits */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search437_1 = { + { nir_search_value_variable, 32 }, + 1, /* offset */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search437 = { + { nir_search_value_expression, 32 }, + false, + nir_op_bfm, + { &search437_0.value, &search437_1.value }, + NULL, +}; + +static const nir_search_constant replace437_0_0_0 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x1 /* 1 */ }, +}; + +static const nir_search_variable replace437_0_0_1 = { + { nir_search_value_variable, 32 }, + 0, /* bits */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace437_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &replace437_0_0_0.value, &replace437_0_0_1.value }, + NULL, +}; + +static const nir_search_constant replace437_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x1 /* 1 */ }, +}; +static const nir_search_expression replace437_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_isub, + { &replace437_0_0.value, &replace437_0_1.value }, + NULL, +}; + +static const nir_search_variable replace437_1 = { + { nir_search_value_variable, 32 }, + 1, /* offset */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace437 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &replace437_0.value, &replace437_1.value }, + NULL, +}; + +static const nir_search_variable search438_0 = { + { nir_search_value_variable, 32 }, + 0, /* value */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search438_1 = { + { nir_search_value_variable, 32 }, + 1, /* offset */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search438_2 = { + { nir_search_value_variable, 32 }, + 2, /* bits */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search438 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ibitfield_extract, + { &search438_0.value, &search438_1.value, &search438_2.value }, + NULL, +}; + +static const nir_search_constant replace438_0_0 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x1f /* 31 */ }, +}; + +static const nir_search_variable replace438_0_1 = { + { nir_search_value_variable, 32 }, + 2, /* bits */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace438_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &replace438_0_0.value, &replace438_0_1.value }, + NULL, +}; + +static const nir_search_variable replace438_1 = { + { nir_search_value_variable, 32 }, + 0, /* value */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace438_2_0 = { + { nir_search_value_variable, 32 }, + 0, /* value */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace438_2_1 = { + { nir_search_value_variable, 32 }, + 1, /* offset */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace438_2_2 = { + { nir_search_value_variable, 32 }, + 2, /* bits */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace438_2 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ibfe, + { &replace438_2_0.value, &replace438_2_1.value, &replace438_2_2.value }, + NULL, +}; +static const nir_search_expression replace438 = { + { nir_search_value_expression, 32 }, + false, + nir_op_bcsel, + { &replace438_0.value, &replace438_1.value, &replace438_2.value }, + NULL, +}; + +static const nir_search_variable search439_0 = { + { nir_search_value_variable, 32 }, + 0, /* value */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search439_1 = { + { nir_search_value_variable, 32 }, + 1, /* offset */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search439_2 = { + { nir_search_value_variable, 32 }, + 2, /* bits */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search439 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ubitfield_extract, + { &search439_0.value, &search439_1.value, &search439_2.value }, + NULL, +}; + +static const nir_search_constant replace439_0_0 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x1f /* 31 */ }, +}; + +static const nir_search_variable replace439_0_1 = { + { nir_search_value_variable, 32 }, + 2, /* bits */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace439_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &replace439_0_0.value, &replace439_0_1.value }, + NULL, +}; + +static const nir_search_variable replace439_1 = { + { nir_search_value_variable, 32 }, + 0, /* value */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace439_2_0 = { + { nir_search_value_variable, 32 }, + 0, /* value */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace439_2_1 = { + { nir_search_value_variable, 32 }, + 1, /* offset */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace439_2_2 = { + { nir_search_value_variable, 32 }, + 2, /* bits */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace439_2 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ubfe, + { &replace439_2_0.value, &replace439_2_1.value, &replace439_2_2.value }, + NULL, +}; +static const nir_search_expression replace439 = { + { nir_search_value_expression, 32 }, + false, + nir_op_bcsel, + { &replace439_0.value, &replace439_1.value, &replace439_2.value }, + NULL, +}; + +static const nir_search_variable search440_0 = { + { nir_search_value_variable, 32 }, + 0, /* value */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search440_1 = { + { nir_search_value_variable, 32 }, + 1, /* offset */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search440_2 = { + { nir_search_value_variable, 32 }, + 2, /* bits */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search440 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ibitfield_extract, + { &search440_0.value, &search440_1.value, &search440_2.value }, + NULL, +}; + +static const nir_search_constant replace440_0_0 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x0 /* 0 */ }, +}; + +static const nir_search_variable replace440_0_1 = { + { nir_search_value_variable, 32 }, + 2, /* bits */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace440_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ieq, + { &replace440_0_0.value, &replace440_0_1.value }, + NULL, +}; + +static const nir_search_constant replace440_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x0 /* 0 */ }, +}; + +static const nir_search_variable replace440_2_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* value */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace440_2_0_1_0_0 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x20 /* 32 */ }, +}; + +static const nir_search_variable replace440_2_0_1_0_1 = { + { nir_search_value_variable, 32 }, + 2, /* bits */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace440_2_0_1_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_isub, + { &replace440_2_0_1_0_0.value, &replace440_2_0_1_0_1.value }, + NULL, +}; + +static const nir_search_variable replace440_2_0_1_1 = { + { nir_search_value_variable, 32 }, + 1, /* offset */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace440_2_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_isub, + { &replace440_2_0_1_0.value, &replace440_2_0_1_1.value }, + NULL, +}; +static const nir_search_expression replace440_2_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &replace440_2_0_0.value, &replace440_2_0_1.value }, + NULL, +}; + +static const nir_search_constant replace440_2_1_0 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x20 /* 32 */ }, +}; + +static const nir_search_variable replace440_2_1_1 = { + { nir_search_value_variable, 32 }, + 2, /* bits */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace440_2_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_isub, + { &replace440_2_1_0.value, &replace440_2_1_1.value }, + NULL, +}; +static const nir_search_expression replace440_2 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishr, + { &replace440_2_0.value, &replace440_2_1.value }, + NULL, +}; +static const nir_search_expression replace440 = { + { nir_search_value_expression, 32 }, + false, + nir_op_bcsel, + { &replace440_0.value, &replace440_1.value, &replace440_2.value }, + NULL, +}; + +static const nir_search_variable search441_0 = { + { nir_search_value_variable, 32 }, + 0, /* value */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search441_1 = { + { nir_search_value_variable, 32 }, + 1, /* offset */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search441_2 = { + { nir_search_value_variable, 32 }, + 2, /* bits */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search441 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ubitfield_extract, + { &search441_0.value, &search441_1.value, &search441_2.value }, + NULL, +}; + +static const nir_search_variable replace441_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* value */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace441_0_1 = { + { nir_search_value_variable, 32 }, + 1, /* offset */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace441_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &replace441_0_0.value, &replace441_0_1.value }, + NULL, +}; + +static const nir_search_variable replace441_1_0_0 = { + { nir_search_value_variable, 32 }, + 2, /* bits */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace441_1_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x20 /* 32 */ }, +}; +static const nir_search_expression replace441_1_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ieq, + { &replace441_1_0_0.value, &replace441_1_0_1.value }, + NULL, +}; + +static const nir_search_constant replace441_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0xffffffff /* 4294967295 */ }, +}; + +static const nir_search_variable replace441_1_2_0 = { + { nir_search_value_variable, 32 }, + 2, /* bits */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace441_1_2_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression replace441_1_2 = { + { nir_search_value_expression, 32 }, + false, + nir_op_bfm, + { &replace441_1_2_0.value, &replace441_1_2_1.value }, + NULL, +}; +static const nir_search_expression replace441_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_bcsel, + { &replace441_1_0.value, &replace441_1_1.value, &replace441_1_2.value }, + NULL, +}; +static const nir_search_expression replace441 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iand, + { &replace441_0.value, &replace441_1.value }, + NULL, +}; + +static const nir_search_variable search442_0 = { + { nir_search_value_variable, 32 }, + 0, /* value */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search442 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ifind_msb, + { &search442_0.value }, + NULL, +}; + +static const nir_search_variable replace442_0_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* value */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace442_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression replace442_0_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &replace442_0_0_0.value, &replace442_0_0_1.value }, + NULL, +}; + +static const nir_search_variable replace442_0_1_0 = { + { nir_search_value_variable, 32 }, + 0, /* value */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace442_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_inot, + { &replace442_0_1_0.value }, + NULL, +}; + +static const nir_search_variable replace442_0_2 = { + { nir_search_value_variable, 32 }, + 0, /* value */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace442_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_bcsel, + { &replace442_0_0.value, &replace442_0_1.value, &replace442_0_2.value }, + NULL, +}; +static const nir_search_expression replace442 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ufind_msb, + { &replace442_0.value }, + NULL, +}; + +static const nir_search_variable search443_0 = { + { nir_search_value_variable, -1 }, + 0, /* value */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search443 = { + { nir_search_value_expression, 32 }, + false, + nir_op_find_lsb, + { &search443_0.value }, + NULL, +}; + +static const nir_search_variable replace443_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* value */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace443_0_1_0 = { + { nir_search_value_variable, -1 }, + 0, /* value */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace443_0_1 = { + { nir_search_value_expression, -1 }, + false, + nir_op_ineg, + { &replace443_0_1_0.value }, + NULL, +}; +static const nir_search_expression replace443_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_iand, + { &replace443_0_0.value, &replace443_0_1.value }, + NULL, +}; +static const nir_search_expression replace443 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ufind_msb, + { &replace443_0.value }, + NULL, +}; + +static const nir_search_variable search444_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search444_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search444 = { + { nir_search_value_expression, 32 }, + false, + nir_op_extract_i8, + { &search444_0.value, &search444_1.value }, + NULL, +}; + +static const nir_search_variable replace444_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace444_0_1_0_0 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x3 /* 3 */ }, +}; + +static const nir_search_variable replace444_0_1_0_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace444_0_1_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_isub, + { &replace444_0_1_0_0.value, &replace444_0_1_0_1.value }, + NULL, +}; + +static const nir_search_constant replace444_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x8 /* 8 */ }, +}; +static const nir_search_expression replace444_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_imul, + { &replace444_0_1_0.value, &replace444_0_1_1.value }, + NULL, +}; +static const nir_search_expression replace444_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &replace444_0_0.value, &replace444_0_1.value }, + NULL, +}; + +static const nir_search_constant replace444_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x18 /* 24 */ }, +}; +static const nir_search_expression replace444 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishr, + { &replace444_0.value, &replace444_1.value }, + NULL, +}; + +static const nir_search_variable search445_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search445_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search445 = { + { nir_search_value_expression, 32 }, + false, + nir_op_extract_u8, + { &search445_0.value, &search445_1.value }, + NULL, +}; + +static const nir_search_variable replace445_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace445_0_1_0 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace445_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x8 /* 8 */ }, +}; +static const nir_search_expression replace445_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_imul, + { &replace445_0_1_0.value, &replace445_0_1_1.value }, + NULL, +}; +static const nir_search_expression replace445_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &replace445_0_0.value, &replace445_0_1.value }, + NULL, +}; + +static const nir_search_constant replace445_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0xff /* 255 */ }, +}; +static const nir_search_expression replace445 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iand, + { &replace445_0.value, &replace445_1.value }, + NULL, +}; + +static const nir_search_variable search446_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search446_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search446 = { + { nir_search_value_expression, 32 }, + false, + nir_op_extract_i16, + { &search446_0.value, &search446_1.value }, + NULL, +}; + +static const nir_search_variable replace446_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace446_0_1_0_0 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x1 /* 1 */ }, +}; + +static const nir_search_variable replace446_0_1_0_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace446_0_1_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_isub, + { &replace446_0_1_0_0.value, &replace446_0_1_0_1.value }, + NULL, +}; + +static const nir_search_constant replace446_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression replace446_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_imul, + { &replace446_0_1_0.value, &replace446_0_1_1.value }, + NULL, +}; +static const nir_search_expression replace446_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &replace446_0_0.value, &replace446_0_1.value }, + NULL, +}; + +static const nir_search_constant replace446_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression replace446 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishr, + { &replace446_0.value, &replace446_1.value }, + NULL, +}; + +static const nir_search_variable search447_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search447_1 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search447 = { + { nir_search_value_expression, 32 }, + false, + nir_op_extract_u16, + { &search447_0.value, &search447_1.value }, + NULL, +}; + +static const nir_search_variable replace447_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace447_0_1_0 = { + { nir_search_value_variable, 32 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace447_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression replace447_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_imul, + { &replace447_0_1_0.value, &replace447_0_1_1.value }, + NULL, +}; +static const nir_search_expression replace447_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &replace447_0_0.value, &replace447_0_1.value }, + NULL, +}; + +static const nir_search_constant replace447_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0xffff /* 65535 */ }, +}; +static const nir_search_expression replace447 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iand, + { &replace447_0.value, &replace447_1.value }, + NULL, +}; + +static const nir_search_variable search448_0 = { + { nir_search_value_variable, 32 }, + 0, /* v */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search448 = { + { nir_search_value_expression, 32 }, + false, + nir_op_pack_unorm_2x16, + { &search448_0.value }, + NULL, +}; + +static const nir_search_variable replace448_0_0_0_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* v */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace448_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fsat, + { &replace448_0_0_0_0_0.value }, + NULL, +}; + +static const nir_search_constant replace448_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_float, { 0x40efffe000000000 /* 65535.0 */ }, +}; +static const nir_search_expression replace448_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fmul, + { &replace448_0_0_0_0.value, &replace448_0_0_0_1.value }, + NULL, +}; +static const nir_search_expression replace448_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fround_even, + { &replace448_0_0_0.value }, + NULL, +}; +static const nir_search_expression replace448_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_f2u32, + { &replace448_0_0.value }, + NULL, +}; +static const nir_search_expression replace448 = { + { nir_search_value_expression, 32 }, + false, + nir_op_pack_uvec2_to_uint, + { &replace448_0.value }, + NULL, +}; + +static const nir_search_variable search449_0 = { + { nir_search_value_variable, 32 }, + 0, /* v */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search449 = { + { nir_search_value_expression, 32 }, + false, + nir_op_pack_unorm_4x8, + { &search449_0.value }, + NULL, +}; + +static const nir_search_variable replace449_0_0_0_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* v */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace449_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fsat, + { &replace449_0_0_0_0_0.value }, + NULL, +}; + +static const nir_search_constant replace449_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_float, { 0x406fe00000000000 /* 255.0 */ }, +}; +static const nir_search_expression replace449_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fmul, + { &replace449_0_0_0_0.value, &replace449_0_0_0_1.value }, + NULL, +}; +static const nir_search_expression replace449_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fround_even, + { &replace449_0_0_0.value }, + NULL, +}; +static const nir_search_expression replace449_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_f2u32, + { &replace449_0_0.value }, + NULL, +}; +static const nir_search_expression replace449 = { + { nir_search_value_expression, 32 }, + false, + nir_op_pack_uvec4_to_uint, + { &replace449_0.value }, + NULL, +}; + +static const nir_search_variable search450_0 = { + { nir_search_value_variable, 32 }, + 0, /* v */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search450 = { + { nir_search_value_expression, 32 }, + false, + nir_op_pack_snorm_2x16, + { &search450_0.value }, + NULL, +}; + +static const nir_search_constant replace450_0_0_0_0_0 = { + { nir_search_value_constant, 32 }, + nir_type_float, { 0x3ff0000000000000 /* 1.0 */ }, +}; + +static const nir_search_constant replace450_0_0_0_0_1_0 = { + { nir_search_value_constant, 32 }, + nir_type_float, { 0xbff0000000000000L /* -1.0 */ }, +}; + +static const nir_search_variable replace450_0_0_0_0_1_1 = { + { nir_search_value_variable, 32 }, + 0, /* v */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace450_0_0_0_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fmax, + { &replace450_0_0_0_0_1_0.value, &replace450_0_0_0_0_1_1.value }, + NULL, +}; +static const nir_search_expression replace450_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fmin, + { &replace450_0_0_0_0_0.value, &replace450_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_constant replace450_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_float, { 0x40dfffc000000000 /* 32767.0 */ }, +}; +static const nir_search_expression replace450_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fmul, + { &replace450_0_0_0_0.value, &replace450_0_0_0_1.value }, + NULL, +}; +static const nir_search_expression replace450_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fround_even, + { &replace450_0_0_0.value }, + NULL, +}; +static const nir_search_expression replace450_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_f2i32, + { &replace450_0_0.value }, + NULL, +}; +static const nir_search_expression replace450 = { + { nir_search_value_expression, 32 }, + false, + nir_op_pack_uvec2_to_uint, + { &replace450_0.value }, + NULL, +}; + +static const nir_search_variable search451_0 = { + { nir_search_value_variable, 32 }, + 0, /* v */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search451 = { + { nir_search_value_expression, 32 }, + false, + nir_op_pack_snorm_4x8, + { &search451_0.value }, + NULL, +}; + +static const nir_search_constant replace451_0_0_0_0_0 = { + { nir_search_value_constant, 32 }, + nir_type_float, { 0x3ff0000000000000 /* 1.0 */ }, +}; + +static const nir_search_constant replace451_0_0_0_0_1_0 = { + { nir_search_value_constant, 32 }, + nir_type_float, { 0xbff0000000000000L /* -1.0 */ }, +}; + +static const nir_search_variable replace451_0_0_0_0_1_1 = { + { nir_search_value_variable, 32 }, + 0, /* v */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace451_0_0_0_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fmax, + { &replace451_0_0_0_0_1_0.value, &replace451_0_0_0_0_1_1.value }, + NULL, +}; +static const nir_search_expression replace451_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fmin, + { &replace451_0_0_0_0_0.value, &replace451_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_constant replace451_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_float, { 0x405fc00000000000 /* 127.0 */ }, +}; +static const nir_search_expression replace451_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fmul, + { &replace451_0_0_0_0.value, &replace451_0_0_0_1.value }, + NULL, +}; +static const nir_search_expression replace451_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fround_even, + { &replace451_0_0_0.value }, + NULL, +}; +static const nir_search_expression replace451_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_f2i32, + { &replace451_0_0.value }, + NULL, +}; +static const nir_search_expression replace451 = { + { nir_search_value_expression, 32 }, + false, + nir_op_pack_uvec4_to_uint, + { &replace451_0.value }, + NULL, +}; + +static const nir_search_variable search452_0 = { + { nir_search_value_variable, 32 }, + 0, /* v */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search452 = { + { nir_search_value_expression, 32 }, + false, + nir_op_unpack_unorm_2x16, + { &search452_0.value }, + NULL, +}; + +static const nir_search_variable replace452_0_0_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* v */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace452_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression replace452_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_extract_u16, + { &replace452_0_0_0_0.value, &replace452_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable replace452_0_0_1_0 = { + { nir_search_value_variable, 32 }, + 0, /* v */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace452_0_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x1 /* 1 */ }, +}; +static const nir_search_expression replace452_0_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_extract_u16, + { &replace452_0_0_1_0.value, &replace452_0_0_1_1.value }, + NULL, +}; +static const nir_search_expression replace452_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_vec2, + { &replace452_0_0_0.value, &replace452_0_0_1.value }, + NULL, +}; +static const nir_search_expression replace452_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_u2f32, + { &replace452_0_0.value }, + NULL, +}; + +static const nir_search_constant replace452_1 = { + { nir_search_value_constant, 32 }, + nir_type_float, { 0x40efffe000000000 /* 65535.0 */ }, +}; +static const nir_search_expression replace452 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fdiv, + { &replace452_0.value, &replace452_1.value }, + NULL, +}; + +static const nir_search_variable search453_0 = { + { nir_search_value_variable, 32 }, + 0, /* v */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search453 = { + { nir_search_value_expression, 32 }, + false, + nir_op_unpack_unorm_4x8, + { &search453_0.value }, + NULL, +}; + +static const nir_search_variable replace453_0_0_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* v */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace453_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression replace453_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_extract_u8, + { &replace453_0_0_0_0.value, &replace453_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable replace453_0_0_1_0 = { + { nir_search_value_variable, 32 }, + 0, /* v */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace453_0_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x1 /* 1 */ }, +}; +static const nir_search_expression replace453_0_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_extract_u8, + { &replace453_0_0_1_0.value, &replace453_0_0_1_1.value }, + NULL, +}; + +static const nir_search_variable replace453_0_0_2_0 = { + { nir_search_value_variable, 32 }, + 0, /* v */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace453_0_0_2_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x2 /* 2 */ }, +}; +static const nir_search_expression replace453_0_0_2 = { + { nir_search_value_expression, 32 }, + false, + nir_op_extract_u8, + { &replace453_0_0_2_0.value, &replace453_0_0_2_1.value }, + NULL, +}; + +static const nir_search_variable replace453_0_0_3_0 = { + { nir_search_value_variable, 32 }, + 0, /* v */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace453_0_0_3_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x3 /* 3 */ }, +}; +static const nir_search_expression replace453_0_0_3 = { + { nir_search_value_expression, 32 }, + false, + nir_op_extract_u8, + { &replace453_0_0_3_0.value, &replace453_0_0_3_1.value }, + NULL, +}; +static const nir_search_expression replace453_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_vec4, + { &replace453_0_0_0.value, &replace453_0_0_1.value, &replace453_0_0_2.value, &replace453_0_0_3.value }, + NULL, +}; +static const nir_search_expression replace453_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_u2f32, + { &replace453_0_0.value }, + NULL, +}; + +static const nir_search_constant replace453_1 = { + { nir_search_value_constant, 32 }, + nir_type_float, { 0x406fe00000000000 /* 255.0 */ }, +}; +static const nir_search_expression replace453 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fdiv, + { &replace453_0.value, &replace453_1.value }, + NULL, +}; + +static const nir_search_variable search454_0 = { + { nir_search_value_variable, 32 }, + 0, /* v */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search454 = { + { nir_search_value_expression, 32 }, + false, + nir_op_unpack_snorm_2x16, + { &search454_0.value }, + NULL, +}; + +static const nir_search_constant replace454_0 = { + { nir_search_value_constant, 32 }, + nir_type_float, { 0x3ff0000000000000 /* 1.0 */ }, +}; + +static const nir_search_constant replace454_1_0 = { + { nir_search_value_constant, 32 }, + nir_type_float, { 0xbff0000000000000L /* -1.0 */ }, +}; + +static const nir_search_variable replace454_1_1_0_0_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* v */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace454_1_1_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression replace454_1_1_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_extract_i16, + { &replace454_1_1_0_0_0_0.value, &replace454_1_1_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable replace454_1_1_0_0_1_0 = { + { nir_search_value_variable, 32 }, + 0, /* v */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace454_1_1_0_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x1 /* 1 */ }, +}; +static const nir_search_expression replace454_1_1_0_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_extract_i16, + { &replace454_1_1_0_0_1_0.value, &replace454_1_1_0_0_1_1.value }, + NULL, +}; +static const nir_search_expression replace454_1_1_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_vec2, + { &replace454_1_1_0_0_0.value, &replace454_1_1_0_0_1.value }, + NULL, +}; +static const nir_search_expression replace454_1_1_0 = { + { nir_search_value_expression, 32 }, + false, + nir_search_op_i2f, + { &replace454_1_1_0_0.value }, + NULL, +}; + +static const nir_search_constant replace454_1_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_float, { 0x40dfffc000000000 /* 32767.0 */ }, +}; +static const nir_search_expression replace454_1_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fdiv, + { &replace454_1_1_0.value, &replace454_1_1_1.value }, + NULL, +}; +static const nir_search_expression replace454_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fmax, + { &replace454_1_0.value, &replace454_1_1.value }, + NULL, +}; +static const nir_search_expression replace454 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fmin, + { &replace454_0.value, &replace454_1.value }, + NULL, +}; + +static const nir_search_variable search455_0 = { + { nir_search_value_variable, 32 }, + 0, /* v */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search455 = { + { nir_search_value_expression, 32 }, + false, + nir_op_unpack_snorm_4x8, + { &search455_0.value }, + NULL, +}; + +static const nir_search_constant replace455_0 = { + { nir_search_value_constant, 32 }, + nir_type_float, { 0x3ff0000000000000 /* 1.0 */ }, +}; + +static const nir_search_constant replace455_1_0 = { + { nir_search_value_constant, 32 }, + nir_type_float, { 0xbff0000000000000L /* -1.0 */ }, +}; + +static const nir_search_variable replace455_1_1_0_0_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* v */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace455_1_1_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x0 /* 0 */ }, +}; +static const nir_search_expression replace455_1_1_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_extract_i8, + { &replace455_1_1_0_0_0_0.value, &replace455_1_1_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable replace455_1_1_0_0_1_0 = { + { nir_search_value_variable, 32 }, + 0, /* v */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace455_1_1_0_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x1 /* 1 */ }, +}; +static const nir_search_expression replace455_1_1_0_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_extract_i8, + { &replace455_1_1_0_0_1_0.value, &replace455_1_1_0_0_1_1.value }, + NULL, +}; + +static const nir_search_variable replace455_1_1_0_0_2_0 = { + { nir_search_value_variable, 32 }, + 0, /* v */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace455_1_1_0_0_2_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x2 /* 2 */ }, +}; +static const nir_search_expression replace455_1_1_0_0_2 = { + { nir_search_value_expression, 32 }, + false, + nir_op_extract_i8, + { &replace455_1_1_0_0_2_0.value, &replace455_1_1_0_0_2_1.value }, + NULL, +}; + +static const nir_search_variable replace455_1_1_0_0_3_0 = { + { nir_search_value_variable, 32 }, + 0, /* v */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace455_1_1_0_0_3_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x3 /* 3 */ }, +}; +static const nir_search_expression replace455_1_1_0_0_3 = { + { nir_search_value_expression, 32 }, + false, + nir_op_extract_i8, + { &replace455_1_1_0_0_3_0.value, &replace455_1_1_0_0_3_1.value }, + NULL, +}; +static const nir_search_expression replace455_1_1_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_vec4, + { &replace455_1_1_0_0_0.value, &replace455_1_1_0_0_1.value, &replace455_1_1_0_0_2.value, &replace455_1_1_0_0_3.value }, + NULL, +}; +static const nir_search_expression replace455_1_1_0 = { + { nir_search_value_expression, 32 }, + false, + nir_search_op_i2f, + { &replace455_1_1_0_0.value }, + NULL, +}; + +static const nir_search_constant replace455_1_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_float, { 0x405fc00000000000 /* 127.0 */ }, +}; +static const nir_search_expression replace455_1_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fdiv, + { &replace455_1_1_0.value, &replace455_1_1_1.value }, + NULL, +}; +static const nir_search_expression replace455_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fmax, + { &replace455_1_0.value, &replace455_1_1.value }, + NULL, +}; +static const nir_search_expression replace455 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fmin, + { &replace455_0.value, &replace455_1.value }, + NULL, +}; + +static const nir_search_variable search456_0_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search456_0_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search456_0_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &search456_0_0_0.value, &search456_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search456_0_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search456_0_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search456_0_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &search456_0_1_0.value, &search456_0_1_1.value }, + NULL, +}; +static const nir_search_expression search456_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &search456_0_0.value, &search456_0_1.value }, + (is_used_once), +}; +static const nir_search_expression search456 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &search456_0.value }, + NULL, +}; + +static const nir_search_variable replace456_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace456_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace456_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &replace456_0_0.value, &replace456_0_1.value }, + NULL, +}; + +static const nir_search_variable replace456_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace456_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace456_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &replace456_1_0.value, &replace456_1_1.value }, + NULL, +}; +static const nir_search_expression replace456 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &replace456_0.value, &replace456_1.value }, + NULL, +}; + +static const nir_search_variable search457_0_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search457_0_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search457_0_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &search457_0_0_0.value, &search457_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search457_0_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search457_0_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search457_0_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &search457_0_1_0.value, &search457_0_1_1.value }, + NULL, +}; +static const nir_search_expression search457_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &search457_0_0.value, &search457_0_1.value }, + (is_used_once), +}; +static const nir_search_expression search457 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &search457_0.value }, + NULL, +}; + +static const nir_search_variable replace457_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace457_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace457_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &replace457_0_0.value, &replace457_0_1.value }, + NULL, +}; + +static const nir_search_variable replace457_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace457_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace457_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &replace457_1_0.value, &replace457_1_1.value }, + NULL, +}; +static const nir_search_expression replace457 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &replace457_0.value, &replace457_1.value }, + NULL, +}; + +static const nir_search_variable search458_0_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search458_0_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search458_0_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &search458_0_0_0.value, &search458_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search458_0_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search458_0_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search458_0_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &search458_0_1_0.value, &search458_0_1_1.value }, + NULL, +}; +static const nir_search_expression search458_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &search458_0_0.value, &search458_0_1.value }, + (is_used_once), +}; +static const nir_search_expression search458 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &search458_0.value }, + NULL, +}; + +static const nir_search_variable replace458_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace458_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace458_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &replace458_0_0.value, &replace458_0_1.value }, + NULL, +}; + +static const nir_search_variable replace458_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace458_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace458_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &replace458_1_0.value, &replace458_1_1.value }, + NULL, +}; +static const nir_search_expression replace458 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &replace458_0.value, &replace458_1.value }, + NULL, +}; + +static const nir_search_variable search459_0_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search459_0_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search459_0_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &search459_0_0_0.value, &search459_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search459_0_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search459_0_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search459_0_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &search459_0_1_0.value, &search459_0_1_1.value }, + NULL, +}; +static const nir_search_expression search459_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &search459_0_0.value, &search459_0_1.value }, + (is_used_once), +}; +static const nir_search_expression search459 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &search459_0.value }, + NULL, +}; + +static const nir_search_variable replace459_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace459_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace459_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &replace459_0_0.value, &replace459_0_1.value }, + NULL, +}; + +static const nir_search_variable replace459_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace459_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace459_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &replace459_1_0.value, &replace459_1_1.value }, + NULL, +}; +static const nir_search_expression replace459 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &replace459_0.value, &replace459_1.value }, + NULL, +}; + +static const nir_search_variable search460_0_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search460_0_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search460_0_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &search460_0_0_0.value, &search460_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search460_0_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search460_0_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search460_0_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search460_0_1_0.value, &search460_0_1_1.value }, + NULL, +}; +static const nir_search_expression search460_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &search460_0_0.value, &search460_0_1.value }, + (is_used_once), +}; +static const nir_search_expression search460 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &search460_0.value }, + NULL, +}; + +static const nir_search_variable replace460_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace460_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace460_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &replace460_0_0.value, &replace460_0_1.value }, + NULL, +}; + +static const nir_search_variable replace460_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace460_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace460_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &replace460_1_0.value, &replace460_1_1.value }, + NULL, +}; +static const nir_search_expression replace460 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &replace460_0.value, &replace460_1.value }, + NULL, +}; + +static const nir_search_variable search461_0_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search461_0_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search461_0_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &search461_0_0_0.value, &search461_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search461_0_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search461_0_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search461_0_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search461_0_1_0.value, &search461_0_1_1.value }, + NULL, +}; +static const nir_search_expression search461_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &search461_0_0.value, &search461_0_1.value }, + (is_used_once), +}; +static const nir_search_expression search461 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &search461_0.value }, + NULL, +}; + +static const nir_search_variable replace461_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace461_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace461_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &replace461_0_0.value, &replace461_0_1.value }, + NULL, +}; + +static const nir_search_variable replace461_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace461_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace461_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &replace461_1_0.value, &replace461_1_1.value }, + NULL, +}; +static const nir_search_expression replace461 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &replace461_0.value, &replace461_1.value }, + NULL, +}; + +static const nir_search_variable search462_0_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search462_0_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search462_0_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &search462_0_0_0.value, &search462_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search462_0_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search462_0_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search462_0_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search462_0_1_0.value, &search462_0_1_1.value }, + NULL, +}; +static const nir_search_expression search462_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &search462_0_0.value, &search462_0_1.value }, + (is_used_once), +}; +static const nir_search_expression search462 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &search462_0.value }, + NULL, +}; + +static const nir_search_variable replace462_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace462_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace462_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &replace462_0_0.value, &replace462_0_1.value }, + NULL, +}; + +static const nir_search_variable replace462_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace462_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace462_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &replace462_1_0.value, &replace462_1_1.value }, + NULL, +}; +static const nir_search_expression replace462 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &replace462_0.value, &replace462_1.value }, + NULL, +}; + +static const nir_search_variable search463_0_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search463_0_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search463_0_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &search463_0_0_0.value, &search463_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search463_0_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search463_0_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search463_0_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search463_0_1_0.value, &search463_0_1_1.value }, + NULL, +}; +static const nir_search_expression search463_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &search463_0_0.value, &search463_0_1.value }, + (is_used_once), +}; +static const nir_search_expression search463 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &search463_0.value }, + NULL, +}; + +static const nir_search_variable replace463_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace463_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace463_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &replace463_0_0.value, &replace463_0_1.value }, + NULL, +}; + +static const nir_search_variable replace463_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace463_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace463_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &replace463_1_0.value, &replace463_1_1.value }, + NULL, +}; +static const nir_search_expression replace463 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &replace463_0.value, &replace463_1.value }, + NULL, +}; + +static const nir_search_variable search464_0_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search464_0_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search464_0_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &search464_0_0_0.value, &search464_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search464_0_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search464_0_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search464_0_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &search464_0_1_0.value, &search464_0_1_1.value }, + NULL, +}; +static const nir_search_expression search464_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &search464_0_0.value, &search464_0_1.value }, + (is_used_once), +}; +static const nir_search_expression search464 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &search464_0.value }, + NULL, +}; + +static const nir_search_variable replace464_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace464_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace464_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &replace464_0_0.value, &replace464_0_1.value }, + NULL, +}; + +static const nir_search_variable replace464_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace464_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace464_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &replace464_1_0.value, &replace464_1_1.value }, + NULL, +}; +static const nir_search_expression replace464 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &replace464_0.value, &replace464_1.value }, + NULL, +}; + +static const nir_search_variable search465_0_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search465_0_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search465_0_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &search465_0_0_0.value, &search465_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search465_0_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search465_0_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search465_0_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &search465_0_1_0.value, &search465_0_1_1.value }, + NULL, +}; +static const nir_search_expression search465_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &search465_0_0.value, &search465_0_1.value }, + (is_used_once), +}; +static const nir_search_expression search465 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &search465_0.value }, + NULL, +}; + +static const nir_search_variable replace465_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace465_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace465_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &replace465_0_0.value, &replace465_0_1.value }, + NULL, +}; + +static const nir_search_variable replace465_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace465_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace465_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &replace465_1_0.value, &replace465_1_1.value }, + NULL, +}; +static const nir_search_expression replace465 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &replace465_0.value, &replace465_1.value }, + NULL, +}; + +static const nir_search_variable search466_0_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search466_0_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search466_0_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &search466_0_0_0.value, &search466_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search466_0_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search466_0_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search466_0_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search466_0_1_0.value, &search466_0_1_1.value }, + NULL, +}; +static const nir_search_expression search466_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &search466_0_0.value, &search466_0_1.value }, + (is_used_once), +}; +static const nir_search_expression search466 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &search466_0.value }, + NULL, +}; + +static const nir_search_variable replace466_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace466_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace466_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &replace466_0_0.value, &replace466_0_1.value }, + NULL, +}; + +static const nir_search_variable replace466_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace466_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace466_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &replace466_1_0.value, &replace466_1_1.value }, + NULL, +}; +static const nir_search_expression replace466 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &replace466_0.value, &replace466_1.value }, + NULL, +}; + +static const nir_search_variable search467_0_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search467_0_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search467_0_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &search467_0_0_0.value, &search467_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search467_0_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search467_0_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search467_0_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search467_0_1_0.value, &search467_0_1_1.value }, + NULL, +}; +static const nir_search_expression search467_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &search467_0_0.value, &search467_0_1.value }, + (is_used_once), +}; +static const nir_search_expression search467 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &search467_0.value }, + NULL, +}; + +static const nir_search_variable replace467_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace467_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace467_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &replace467_0_0.value, &replace467_0_1.value }, + NULL, +}; + +static const nir_search_variable replace467_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace467_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace467_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &replace467_1_0.value, &replace467_1_1.value }, + NULL, +}; +static const nir_search_expression replace467 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &replace467_0.value, &replace467_1.value }, + NULL, +}; + +static const nir_search_variable search468_0_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search468_0_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search468_0_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &search468_0_0_0.value, &search468_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search468_0_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search468_0_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search468_0_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search468_0_1_0.value, &search468_0_1_1.value }, + NULL, +}; +static const nir_search_expression search468_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &search468_0_0.value, &search468_0_1.value }, + (is_used_once), +}; +static const nir_search_expression search468 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &search468_0.value }, + NULL, +}; + +static const nir_search_variable replace468_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace468_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace468_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &replace468_0_0.value, &replace468_0_1.value }, + NULL, +}; + +static const nir_search_variable replace468_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace468_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace468_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &replace468_1_0.value, &replace468_1_1.value }, + NULL, +}; +static const nir_search_expression replace468 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &replace468_0.value, &replace468_1.value }, + NULL, +}; + +static const nir_search_variable search469_0_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search469_0_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search469_0_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &search469_0_0_0.value, &search469_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search469_0_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search469_0_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search469_0_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search469_0_1_0.value, &search469_0_1_1.value }, + NULL, +}; +static const nir_search_expression search469_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &search469_0_0.value, &search469_0_1.value }, + (is_used_once), +}; +static const nir_search_expression search469 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &search469_0.value }, + NULL, +}; + +static const nir_search_variable replace469_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace469_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace469_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &replace469_0_0.value, &replace469_0_1.value }, + NULL, +}; + +static const nir_search_variable replace469_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace469_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace469_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &replace469_1_0.value, &replace469_1_1.value }, + NULL, +}; +static const nir_search_expression replace469 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &replace469_0.value, &replace469_1.value }, + NULL, +}; + +static const nir_search_variable search470_0_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search470_0_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search470_0_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search470_0_0_0.value, &search470_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search470_0_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search470_0_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search470_0_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search470_0_1_0.value, &search470_0_1_1.value }, + NULL, +}; +static const nir_search_expression search470_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &search470_0_0.value, &search470_0_1.value }, + (is_used_once), +}; +static const nir_search_expression search470 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &search470_0.value }, + NULL, +}; + +static const nir_search_variable replace470_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace470_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace470_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &replace470_0_0.value, &replace470_0_1.value }, + NULL, +}; + +static const nir_search_variable replace470_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace470_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace470_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &replace470_1_0.value, &replace470_1_1.value }, + NULL, +}; +static const nir_search_expression replace470 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &replace470_0.value, &replace470_1.value }, + NULL, +}; + +static const nir_search_variable search471_0_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search471_0_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search471_0_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search471_0_0_0.value, &search471_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search471_0_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search471_0_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search471_0_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search471_0_1_0.value, &search471_0_1_1.value }, + NULL, +}; +static const nir_search_expression search471_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &search471_0_0.value, &search471_0_1.value }, + (is_used_once), +}; +static const nir_search_expression search471 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &search471_0.value }, + NULL, +}; + +static const nir_search_variable replace471_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace471_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace471_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &replace471_0_0.value, &replace471_0_1.value }, + NULL, +}; + +static const nir_search_variable replace471_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace471_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace471_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &replace471_1_0.value, &replace471_1_1.value }, + NULL, +}; +static const nir_search_expression replace471 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &replace471_0.value, &replace471_1.value }, + NULL, +}; + +static const nir_search_variable search472_0_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search472_0_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search472_0_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search472_0_0_0.value, &search472_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search472_0_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search472_0_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search472_0_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search472_0_1_0.value, &search472_0_1_1.value }, + NULL, +}; +static const nir_search_expression search472_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &search472_0_0.value, &search472_0_1.value }, + (is_used_once), +}; +static const nir_search_expression search472 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &search472_0.value }, + NULL, +}; + +static const nir_search_variable replace472_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace472_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace472_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &replace472_0_0.value, &replace472_0_1.value }, + NULL, +}; + +static const nir_search_variable replace472_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace472_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace472_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &replace472_1_0.value, &replace472_1_1.value }, + NULL, +}; +static const nir_search_expression replace472 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &replace472_0.value, &replace472_1.value }, + NULL, +}; + +static const nir_search_variable search473_0_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search473_0_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search473_0_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search473_0_0_0.value, &search473_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search473_0_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search473_0_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search473_0_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search473_0_1_0.value, &search473_0_1_1.value }, + NULL, +}; +static const nir_search_expression search473_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &search473_0_0.value, &search473_0_1.value }, + (is_used_once), +}; +static const nir_search_expression search473 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &search473_0.value }, + NULL, +}; + +static const nir_search_variable replace473_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace473_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace473_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &replace473_0_0.value, &replace473_0_1.value }, + NULL, +}; + +static const nir_search_variable replace473_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace473_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace473_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &replace473_1_0.value, &replace473_1_1.value }, + NULL, +}; +static const nir_search_expression replace473 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &replace473_0.value, &replace473_1.value }, + NULL, +}; + +static const nir_search_variable search474_0_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search474_0_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search474_0_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search474_0_0_0.value, &search474_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search474_0_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search474_0_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search474_0_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search474_0_1_0.value, &search474_0_1_1.value }, + NULL, +}; +static const nir_search_expression search474_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &search474_0_0.value, &search474_0_1.value }, + (is_used_once), +}; +static const nir_search_expression search474 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &search474_0.value }, + NULL, +}; + +static const nir_search_variable replace474_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace474_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace474_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &replace474_0_0.value, &replace474_0_1.value }, + NULL, +}; + +static const nir_search_variable replace474_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace474_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace474_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &replace474_1_0.value, &replace474_1_1.value }, + NULL, +}; +static const nir_search_expression replace474 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &replace474_0.value, &replace474_1.value }, + NULL, +}; + +static const nir_search_variable search475_0_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search475_0_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search475_0_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search475_0_0_0.value, &search475_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search475_0_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search475_0_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search475_0_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search475_0_1_0.value, &search475_0_1_1.value }, + NULL, +}; +static const nir_search_expression search475_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &search475_0_0.value, &search475_0_1.value }, + (is_used_once), +}; +static const nir_search_expression search475 = { + { nir_search_value_expression, 1 }, + false, + nir_op_inot, + { &search475_0.value }, + NULL, +}; + +static const nir_search_variable replace475_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace475_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace475_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &replace475_0_0.value, &replace475_0_1.value }, + NULL, +}; + +static const nir_search_variable replace475_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace475_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace475_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &replace475_1_0.value, &replace475_1_1.value }, + NULL, +}; +static const nir_search_expression replace475 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ior, + { &replace475_0.value, &replace475_1.value }, + NULL, +}; + +static const nir_search_variable search476_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search476_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search476_0_0.value }, + NULL, +}; +static const nir_search_expression search476 = { + { nir_search_value_expression, 1 }, + false, + nir_op_f2b1, + { &search476_0.value }, + NULL, +}; + +static const nir_search_variable replace476 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search477_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search477_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2i, + { &search477_0_0.value }, + NULL, +}; +static const nir_search_expression search477 = { + { nir_search_value_expression, 1 }, + false, + nir_op_i2b1, + { &search477_0.value }, + NULL, +}; + +static const nir_search_variable replace477 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search478_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search478_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search478_0_0.value }, + NULL, +}; +static const nir_search_expression search478 = { + { nir_search_value_expression, 32 }, + false, + nir_op_f2b32, + { &search478_0.value }, + NULL, +}; + +static const nir_search_variable replace478 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search479_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search479_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2i, + { &search479_0_0.value }, + NULL, +}; +static const nir_search_expression search479 = { + { nir_search_value_expression, 32 }, + false, + nir_op_i2b32, + { &search479_0.value }, + NULL, +}; + +static const nir_search_variable replace479 = { + { nir_search_value_variable, 32 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search480_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search480_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search480_0_0.value }, + NULL, +}; +static const nir_search_expression search480 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_f2f, + { &search480_0.value }, + NULL, +}; + +static const nir_search_variable replace480_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace480 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &replace480_0.value }, + NULL, +}; + +static const nir_search_variable search481_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search481_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search481_0_0.value }, + NULL, +}; +static const nir_search_expression search481 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_f2u, + { &search481_0.value }, + NULL, +}; + +static const nir_search_variable replace481_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace481 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2i, + { &replace481_0.value }, + NULL, +}; + +static const nir_search_variable search482_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search482_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &search482_0_0.value }, + NULL, +}; +static const nir_search_expression search482 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_f2i, + { &search482_0.value }, + NULL, +}; + +static const nir_search_variable replace482_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace482 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2i, + { &replace482_0.value }, + NULL, +}; + +static const nir_search_variable search483_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search483_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2i, + { &search483_0_0.value }, + NULL, +}; +static const nir_search_expression search483 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_u2f, + { &search483_0.value }, + NULL, +}; + +static const nir_search_variable replace483_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace483 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &replace483_0.value }, + NULL, +}; + +static const nir_search_variable search484_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search484_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2i, + { &search484_0_0.value }, + NULL, +}; +static const nir_search_expression search484 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_u2u, + { &search484_0.value }, + NULL, +}; + +static const nir_search_variable replace484_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace484 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2i, + { &replace484_0.value }, + NULL, +}; + +static const nir_search_variable search485_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search485_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2i, + { &search485_0_0.value }, + NULL, +}; +static const nir_search_expression search485 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_i2f, + { &search485_0.value }, + NULL, +}; + +static const nir_search_variable replace485_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace485 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2f, + { &replace485_0.value }, + NULL, +}; + +static const nir_search_variable search486_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search486_0 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2i, + { &search486_0_0.value }, + NULL, +}; +static const nir_search_expression search486 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_i2i, + { &search486_0.value }, + NULL, +}; + +static const nir_search_variable replace486_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace486 = { + { nir_search_value_expression, 0 }, + false, + nir_search_op_b2i, + { &replace486_0.value }, + NULL, +}; + +static const nir_search_variable search487_0 = { + { nir_search_value_variable, 32 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search487_1 = { + { nir_search_value_variable, 32 }, + 1, /* exp */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search487 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ldexp, + { &search487_0.value, &search487_1.value }, + NULL, +}; + +static const nir_search_variable replace487_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace487_0_1_0_0_0_0_0 = { + { nir_search_value_variable, 32 }, + 1, /* exp */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace487_0_1_0_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { -0xfc /* -252 */ }, +}; +static const nir_search_expression replace487_0_1_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_imax, + { &replace487_0_1_0_0_0_0_0.value, &replace487_0_1_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_constant replace487_0_1_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0xfe /* 254 */ }, +}; +static const nir_search_expression replace487_0_1_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_imin, + { &replace487_0_1_0_0_0_0.value, &replace487_0_1_0_0_0_1.value }, + NULL, +}; + +static const nir_search_constant replace487_0_1_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x1 /* 1 */ }, +}; +static const nir_search_expression replace487_0_1_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishr, + { &replace487_0_1_0_0_0.value, &replace487_0_1_0_0_1.value }, + NULL, +}; + +static const nir_search_constant replace487_0_1_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x7f /* 127 */ }, +}; +static const nir_search_expression replace487_0_1_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iadd, + { &replace487_0_1_0_0.value, &replace487_0_1_0_1.value }, + NULL, +}; + +static const nir_search_constant replace487_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x17 /* 23 */ }, +}; +static const nir_search_expression replace487_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &replace487_0_1_0.value, &replace487_0_1_1.value }, + NULL, +}; +static const nir_search_expression replace487_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fmul, + { &replace487_0_0.value, &replace487_0_1.value }, + NULL, +}; + +static const nir_search_variable replace487_1_0_0_0_0_0 = { + { nir_search_value_variable, 32 }, + 1, /* exp */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace487_1_0_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { -0xfc /* -252 */ }, +}; +static const nir_search_expression replace487_1_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_imax, + { &replace487_1_0_0_0_0_0.value, &replace487_1_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_constant replace487_1_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0xfe /* 254 */ }, +}; +static const nir_search_expression replace487_1_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_imin, + { &replace487_1_0_0_0_0.value, &replace487_1_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable replace487_1_0_0_1_0_0_0 = { + { nir_search_value_variable, 32 }, + 1, /* exp */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace487_1_0_0_1_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { -0xfc /* -252 */ }, +}; +static const nir_search_expression replace487_1_0_0_1_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_imax, + { &replace487_1_0_0_1_0_0_0.value, &replace487_1_0_0_1_0_0_1.value }, + NULL, +}; + +static const nir_search_constant replace487_1_0_0_1_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0xfe /* 254 */ }, +}; +static const nir_search_expression replace487_1_0_0_1_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_imin, + { &replace487_1_0_0_1_0_0.value, &replace487_1_0_0_1_0_1.value }, + NULL, +}; + +static const nir_search_constant replace487_1_0_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x1 /* 1 */ }, +}; +static const nir_search_expression replace487_1_0_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishr, + { &replace487_1_0_0_1_0.value, &replace487_1_0_0_1_1.value }, + NULL, +}; +static const nir_search_expression replace487_1_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_isub, + { &replace487_1_0_0_0.value, &replace487_1_0_0_1.value }, + NULL, +}; + +static const nir_search_constant replace487_1_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x7f /* 127 */ }, +}; +static const nir_search_expression replace487_1_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iadd, + { &replace487_1_0_0.value, &replace487_1_0_1.value }, + NULL, +}; + +static const nir_search_constant replace487_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x17 /* 23 */ }, +}; +static const nir_search_expression replace487_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &replace487_1_0.value, &replace487_1_1.value }, + NULL, +}; +static const nir_search_expression replace487 = { + { nir_search_value_expression, 32 }, + false, + nir_op_fmul, + { &replace487_0.value, &replace487_1.value }, + NULL, +}; + +static const nir_search_variable search488_0 = { + { nir_search_value_variable, 64 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search488_1 = { + { nir_search_value_variable, 32 }, + 1, /* exp */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search488 = { + { nir_search_value_expression, 64 }, + false, + nir_op_ldexp, + { &search488_0.value, &search488_1.value }, + NULL, +}; + +static const nir_search_variable replace488_0_0 = { + { nir_search_value_variable, 64 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace488_0_1_0 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x0 /* 0 */ }, +}; + +static const nir_search_variable replace488_0_1_1_0_0_0_0_0 = { + { nir_search_value_variable, 32 }, + 1, /* exp */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace488_0_1_1_0_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { -0x7fc /* -2044 */ }, +}; +static const nir_search_expression replace488_0_1_1_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_imax, + { &replace488_0_1_1_0_0_0_0_0.value, &replace488_0_1_1_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_constant replace488_0_1_1_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x7fe /* 2046 */ }, +}; +static const nir_search_expression replace488_0_1_1_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_imin, + { &replace488_0_1_1_0_0_0_0.value, &replace488_0_1_1_0_0_0_1.value }, + NULL, +}; + +static const nir_search_constant replace488_0_1_1_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x1 /* 1 */ }, +}; +static const nir_search_expression replace488_0_1_1_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishr, + { &replace488_0_1_1_0_0_0.value, &replace488_0_1_1_0_0_1.value }, + NULL, +}; + +static const nir_search_constant replace488_0_1_1_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x3ff /* 1023 */ }, +}; +static const nir_search_expression replace488_0_1_1_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iadd, + { &replace488_0_1_1_0_0.value, &replace488_0_1_1_0_1.value }, + NULL, +}; + +static const nir_search_constant replace488_0_1_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x14 /* 20 */ }, +}; +static const nir_search_expression replace488_0_1_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &replace488_0_1_1_0.value, &replace488_0_1_1_1.value }, + NULL, +}; +static const nir_search_expression replace488_0_1 = { + { nir_search_value_expression, 64 }, + false, + nir_op_pack_64_2x32_split, + { &replace488_0_1_0.value, &replace488_0_1_1.value }, + NULL, +}; +static const nir_search_expression replace488_0 = { + { nir_search_value_expression, 64 }, + false, + nir_op_fmul, + { &replace488_0_0.value, &replace488_0_1.value }, + NULL, +}; + +static const nir_search_constant replace488_1_0 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x0 /* 0 */ }, +}; + +static const nir_search_variable replace488_1_1_0_0_0_0_0 = { + { nir_search_value_variable, 32 }, + 1, /* exp */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace488_1_1_0_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { -0x7fc /* -2044 */ }, +}; +static const nir_search_expression replace488_1_1_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_imax, + { &replace488_1_1_0_0_0_0_0.value, &replace488_1_1_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_constant replace488_1_1_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x7fe /* 2046 */ }, +}; +static const nir_search_expression replace488_1_1_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_imin, + { &replace488_1_1_0_0_0_0.value, &replace488_1_1_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable replace488_1_1_0_0_1_0_0_0 = { + { nir_search_value_variable, 32 }, + 1, /* exp */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant replace488_1_1_0_0_1_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { -0x7fc /* -2044 */ }, +}; +static const nir_search_expression replace488_1_1_0_0_1_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_imax, + { &replace488_1_1_0_0_1_0_0_0.value, &replace488_1_1_0_0_1_0_0_1.value }, + NULL, +}; + +static const nir_search_constant replace488_1_1_0_0_1_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x7fe /* 2046 */ }, +}; +static const nir_search_expression replace488_1_1_0_0_1_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_imin, + { &replace488_1_1_0_0_1_0_0.value, &replace488_1_1_0_0_1_0_1.value }, + NULL, +}; + +static const nir_search_constant replace488_1_1_0_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x1 /* 1 */ }, +}; +static const nir_search_expression replace488_1_1_0_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishr, + { &replace488_1_1_0_0_1_0.value, &replace488_1_1_0_0_1_1.value }, + NULL, +}; +static const nir_search_expression replace488_1_1_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_isub, + { &replace488_1_1_0_0_0.value, &replace488_1_1_0_0_1.value }, + NULL, +}; + +static const nir_search_constant replace488_1_1_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x3ff /* 1023 */ }, +}; +static const nir_search_expression replace488_1_1_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iadd, + { &replace488_1_1_0_0.value, &replace488_1_1_0_1.value }, + NULL, +}; + +static const nir_search_constant replace488_1_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x14 /* 20 */ }, +}; +static const nir_search_expression replace488_1_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &replace488_1_1_0.value, &replace488_1_1_1.value }, + NULL, +}; +static const nir_search_expression replace488_1 = { + { nir_search_value_expression, 64 }, + false, + nir_op_pack_64_2x32_split, + { &replace488_1_0.value, &replace488_1_1.value }, + NULL, +}; +static const nir_search_expression replace488 = { + { nir_search_value_expression, 64 }, + false, + nir_op_fmul, + { &replace488_0.value, &replace488_1.value }, + NULL, +}; + +static const nir_search_variable search489_0_0_0_0_0_0_0_0_0_0_0_0_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search489_0_0_0_0_0_0_0_0_0_0_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search489_0_0_0_0_0_0_0_0_0_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search489_0_0_0_0_0_0_0_0_0_0_0_0_0_0.value, &search489_0_0_0_0_0_0_0_0_0_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search489_0_0_0_0_0_0_0_0_0_0_0_0_1_0 = { + { nir_search_value_variable, 32 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search489_0_0_0_0_0_0_0_0_0_0_0_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search489_0_0_0_0_0_0_0_0_0_0_0_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search489_0_0_0_0_0_0_0_0_0_0_0_0_1_0.value, &search489_0_0_0_0_0_0_0_0_0_0_0_0_1_1.value }, + NULL, +}; +static const nir_search_expression search489_0_0_0_0_0_0_0_0_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ior, + { &search489_0_0_0_0_0_0_0_0_0_0_0_0_0.value, &search489_0_0_0_0_0_0_0_0_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_0_0_0_0_0_0_0_0_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0xff00ff /* 16711935 */ }, +}; +static const nir_search_expression search489_0_0_0_0_0_0_0_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iand, + { &search489_0_0_0_0_0_0_0_0_0_0_0_0.value, &search489_0_0_0_0_0_0_0_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_0_0_0_0_0_0_0_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x8 /* 8 */ }, +}; +static const nir_search_expression search489_0_0_0_0_0_0_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search489_0_0_0_0_0_0_0_0_0_0_0.value, &search489_0_0_0_0_0_0_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search489_0_0_0_0_0_0_0_0_0_1_0_0_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search489_0_0_0_0_0_0_0_0_0_1_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search489_0_0_0_0_0_0_0_0_0_1_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search489_0_0_0_0_0_0_0_0_0_1_0_0_0_0.value, &search489_0_0_0_0_0_0_0_0_0_1_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search489_0_0_0_0_0_0_0_0_0_1_0_0_1_0 = { + { nir_search_value_variable, 32 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search489_0_0_0_0_0_0_0_0_0_1_0_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search489_0_0_0_0_0_0_0_0_0_1_0_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search489_0_0_0_0_0_0_0_0_0_1_0_0_1_0.value, &search489_0_0_0_0_0_0_0_0_0_1_0_0_1_1.value }, + NULL, +}; +static const nir_search_expression search489_0_0_0_0_0_0_0_0_0_1_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ior, + { &search489_0_0_0_0_0_0_0_0_0_1_0_0_0.value, &search489_0_0_0_0_0_0_0_0_0_1_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_0_0_0_0_0_0_0_0_0_1_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0xff00ff00 /* 4278255360 */ }, +}; +static const nir_search_expression search489_0_0_0_0_0_0_0_0_0_1_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iand, + { &search489_0_0_0_0_0_0_0_0_0_1_0_0.value, &search489_0_0_0_0_0_0_0_0_0_1_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_0_0_0_0_0_0_0_0_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x8 /* 8 */ }, +}; +static const nir_search_expression search489_0_0_0_0_0_0_0_0_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search489_0_0_0_0_0_0_0_0_0_1_0.value, &search489_0_0_0_0_0_0_0_0_0_1_1.value }, + NULL, +}; +static const nir_search_expression search489_0_0_0_0_0_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ior, + { &search489_0_0_0_0_0_0_0_0_0_0.value, &search489_0_0_0_0_0_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_0_0_0_0_0_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0xf0f0f0f /* 252645135 */ }, +}; +static const nir_search_expression search489_0_0_0_0_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iand, + { &search489_0_0_0_0_0_0_0_0_0.value, &search489_0_0_0_0_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_0_0_0_0_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x4 /* 4 */ }, +}; +static const nir_search_expression search489_0_0_0_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search489_0_0_0_0_0_0_0_0.value, &search489_0_0_0_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search489_0_0_0_0_0_0_1_0_0_0_0_0_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search489_0_0_0_0_0_0_1_0_0_0_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search489_0_0_0_0_0_0_1_0_0_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search489_0_0_0_0_0_0_1_0_0_0_0_0_0_0.value, &search489_0_0_0_0_0_0_1_0_0_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search489_0_0_0_0_0_0_1_0_0_0_0_0_1_0 = { + { nir_search_value_variable, 32 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search489_0_0_0_0_0_0_1_0_0_0_0_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search489_0_0_0_0_0_0_1_0_0_0_0_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search489_0_0_0_0_0_0_1_0_0_0_0_0_1_0.value, &search489_0_0_0_0_0_0_1_0_0_0_0_0_1_1.value }, + NULL, +}; +static const nir_search_expression search489_0_0_0_0_0_0_1_0_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ior, + { &search489_0_0_0_0_0_0_1_0_0_0_0_0_0.value, &search489_0_0_0_0_0_0_1_0_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_0_0_0_0_0_0_1_0_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0xff00ff /* 16711935 */ }, +}; +static const nir_search_expression search489_0_0_0_0_0_0_1_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iand, + { &search489_0_0_0_0_0_0_1_0_0_0_0_0.value, &search489_0_0_0_0_0_0_1_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_0_0_0_0_0_0_1_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x8 /* 8 */ }, +}; +static const nir_search_expression search489_0_0_0_0_0_0_1_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search489_0_0_0_0_0_0_1_0_0_0_0.value, &search489_0_0_0_0_0_0_1_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search489_0_0_0_0_0_0_1_0_0_1_0_0_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search489_0_0_0_0_0_0_1_0_0_1_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search489_0_0_0_0_0_0_1_0_0_1_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search489_0_0_0_0_0_0_1_0_0_1_0_0_0_0.value, &search489_0_0_0_0_0_0_1_0_0_1_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search489_0_0_0_0_0_0_1_0_0_1_0_0_1_0 = { + { nir_search_value_variable, 32 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search489_0_0_0_0_0_0_1_0_0_1_0_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search489_0_0_0_0_0_0_1_0_0_1_0_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search489_0_0_0_0_0_0_1_0_0_1_0_0_1_0.value, &search489_0_0_0_0_0_0_1_0_0_1_0_0_1_1.value }, + NULL, +}; +static const nir_search_expression search489_0_0_0_0_0_0_1_0_0_1_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ior, + { &search489_0_0_0_0_0_0_1_0_0_1_0_0_0.value, &search489_0_0_0_0_0_0_1_0_0_1_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_0_0_0_0_0_0_1_0_0_1_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0xff00ff00 /* 4278255360 */ }, +}; +static const nir_search_expression search489_0_0_0_0_0_0_1_0_0_1_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iand, + { &search489_0_0_0_0_0_0_1_0_0_1_0_0.value, &search489_0_0_0_0_0_0_1_0_0_1_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_0_0_0_0_0_0_1_0_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x8 /* 8 */ }, +}; +static const nir_search_expression search489_0_0_0_0_0_0_1_0_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search489_0_0_0_0_0_0_1_0_0_1_0.value, &search489_0_0_0_0_0_0_1_0_0_1_1.value }, + NULL, +}; +static const nir_search_expression search489_0_0_0_0_0_0_1_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ior, + { &search489_0_0_0_0_0_0_1_0_0_0.value, &search489_0_0_0_0_0_0_1_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_0_0_0_0_0_0_1_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0xf0f0f0f0 /* 4042322160 */ }, +}; +static const nir_search_expression search489_0_0_0_0_0_0_1_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iand, + { &search489_0_0_0_0_0_0_1_0_0.value, &search489_0_0_0_0_0_0_1_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_0_0_0_0_0_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x4 /* 4 */ }, +}; +static const nir_search_expression search489_0_0_0_0_0_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search489_0_0_0_0_0_0_1_0.value, &search489_0_0_0_0_0_0_1_1.value }, + NULL, +}; +static const nir_search_expression search489_0_0_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ior, + { &search489_0_0_0_0_0_0_0.value, &search489_0_0_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_0_0_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x33333333 /* 858993459 */ }, +}; +static const nir_search_expression search489_0_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iand, + { &search489_0_0_0_0_0_0.value, &search489_0_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_0_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x2 /* 2 */ }, +}; +static const nir_search_expression search489_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search489_0_0_0_0_0.value, &search489_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search489_0_0_0_1_0_0_0_0_0_0_0_0_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search489_0_0_0_1_0_0_0_0_0_0_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search489_0_0_0_1_0_0_0_0_0_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search489_0_0_0_1_0_0_0_0_0_0_0_0_0_0.value, &search489_0_0_0_1_0_0_0_0_0_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search489_0_0_0_1_0_0_0_0_0_0_0_0_1_0 = { + { nir_search_value_variable, 32 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search489_0_0_0_1_0_0_0_0_0_0_0_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search489_0_0_0_1_0_0_0_0_0_0_0_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search489_0_0_0_1_0_0_0_0_0_0_0_0_1_0.value, &search489_0_0_0_1_0_0_0_0_0_0_0_0_1_1.value }, + NULL, +}; +static const nir_search_expression search489_0_0_0_1_0_0_0_0_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ior, + { &search489_0_0_0_1_0_0_0_0_0_0_0_0_0.value, &search489_0_0_0_1_0_0_0_0_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_0_0_0_1_0_0_0_0_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0xff00ff /* 16711935 */ }, +}; +static const nir_search_expression search489_0_0_0_1_0_0_0_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iand, + { &search489_0_0_0_1_0_0_0_0_0_0_0_0.value, &search489_0_0_0_1_0_0_0_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_0_0_0_1_0_0_0_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x8 /* 8 */ }, +}; +static const nir_search_expression search489_0_0_0_1_0_0_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search489_0_0_0_1_0_0_0_0_0_0_0.value, &search489_0_0_0_1_0_0_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search489_0_0_0_1_0_0_0_0_0_1_0_0_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search489_0_0_0_1_0_0_0_0_0_1_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search489_0_0_0_1_0_0_0_0_0_1_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search489_0_0_0_1_0_0_0_0_0_1_0_0_0_0.value, &search489_0_0_0_1_0_0_0_0_0_1_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search489_0_0_0_1_0_0_0_0_0_1_0_0_1_0 = { + { nir_search_value_variable, 32 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search489_0_0_0_1_0_0_0_0_0_1_0_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search489_0_0_0_1_0_0_0_0_0_1_0_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search489_0_0_0_1_0_0_0_0_0_1_0_0_1_0.value, &search489_0_0_0_1_0_0_0_0_0_1_0_0_1_1.value }, + NULL, +}; +static const nir_search_expression search489_0_0_0_1_0_0_0_0_0_1_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ior, + { &search489_0_0_0_1_0_0_0_0_0_1_0_0_0.value, &search489_0_0_0_1_0_0_0_0_0_1_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_0_0_0_1_0_0_0_0_0_1_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0xff00ff00 /* 4278255360 */ }, +}; +static const nir_search_expression search489_0_0_0_1_0_0_0_0_0_1_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iand, + { &search489_0_0_0_1_0_0_0_0_0_1_0_0.value, &search489_0_0_0_1_0_0_0_0_0_1_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_0_0_0_1_0_0_0_0_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x8 /* 8 */ }, +}; +static const nir_search_expression search489_0_0_0_1_0_0_0_0_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search489_0_0_0_1_0_0_0_0_0_1_0.value, &search489_0_0_0_1_0_0_0_0_0_1_1.value }, + NULL, +}; +static const nir_search_expression search489_0_0_0_1_0_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ior, + { &search489_0_0_0_1_0_0_0_0_0_0.value, &search489_0_0_0_1_0_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_0_0_0_1_0_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0xf0f0f0f /* 252645135 */ }, +}; +static const nir_search_expression search489_0_0_0_1_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iand, + { &search489_0_0_0_1_0_0_0_0_0.value, &search489_0_0_0_1_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_0_0_0_1_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x4 /* 4 */ }, +}; +static const nir_search_expression search489_0_0_0_1_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search489_0_0_0_1_0_0_0_0.value, &search489_0_0_0_1_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search489_0_0_0_1_0_0_1_0_0_0_0_0_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search489_0_0_0_1_0_0_1_0_0_0_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search489_0_0_0_1_0_0_1_0_0_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search489_0_0_0_1_0_0_1_0_0_0_0_0_0_0.value, &search489_0_0_0_1_0_0_1_0_0_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search489_0_0_0_1_0_0_1_0_0_0_0_0_1_0 = { + { nir_search_value_variable, 32 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search489_0_0_0_1_0_0_1_0_0_0_0_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search489_0_0_0_1_0_0_1_0_0_0_0_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search489_0_0_0_1_0_0_1_0_0_0_0_0_1_0.value, &search489_0_0_0_1_0_0_1_0_0_0_0_0_1_1.value }, + NULL, +}; +static const nir_search_expression search489_0_0_0_1_0_0_1_0_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ior, + { &search489_0_0_0_1_0_0_1_0_0_0_0_0_0.value, &search489_0_0_0_1_0_0_1_0_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_0_0_0_1_0_0_1_0_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0xff00ff /* 16711935 */ }, +}; +static const nir_search_expression search489_0_0_0_1_0_0_1_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iand, + { &search489_0_0_0_1_0_0_1_0_0_0_0_0.value, &search489_0_0_0_1_0_0_1_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_0_0_0_1_0_0_1_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x8 /* 8 */ }, +}; +static const nir_search_expression search489_0_0_0_1_0_0_1_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search489_0_0_0_1_0_0_1_0_0_0_0.value, &search489_0_0_0_1_0_0_1_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search489_0_0_0_1_0_0_1_0_0_1_0_0_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search489_0_0_0_1_0_0_1_0_0_1_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search489_0_0_0_1_0_0_1_0_0_1_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search489_0_0_0_1_0_0_1_0_0_1_0_0_0_0.value, &search489_0_0_0_1_0_0_1_0_0_1_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search489_0_0_0_1_0_0_1_0_0_1_0_0_1_0 = { + { nir_search_value_variable, 32 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search489_0_0_0_1_0_0_1_0_0_1_0_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search489_0_0_0_1_0_0_1_0_0_1_0_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search489_0_0_0_1_0_0_1_0_0_1_0_0_1_0.value, &search489_0_0_0_1_0_0_1_0_0_1_0_0_1_1.value }, + NULL, +}; +static const nir_search_expression search489_0_0_0_1_0_0_1_0_0_1_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ior, + { &search489_0_0_0_1_0_0_1_0_0_1_0_0_0.value, &search489_0_0_0_1_0_0_1_0_0_1_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_0_0_0_1_0_0_1_0_0_1_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0xff00ff00 /* 4278255360 */ }, +}; +static const nir_search_expression search489_0_0_0_1_0_0_1_0_0_1_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iand, + { &search489_0_0_0_1_0_0_1_0_0_1_0_0.value, &search489_0_0_0_1_0_0_1_0_0_1_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_0_0_0_1_0_0_1_0_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x8 /* 8 */ }, +}; +static const nir_search_expression search489_0_0_0_1_0_0_1_0_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search489_0_0_0_1_0_0_1_0_0_1_0.value, &search489_0_0_0_1_0_0_1_0_0_1_1.value }, + NULL, +}; +static const nir_search_expression search489_0_0_0_1_0_0_1_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ior, + { &search489_0_0_0_1_0_0_1_0_0_0.value, &search489_0_0_0_1_0_0_1_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_0_0_0_1_0_0_1_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0xf0f0f0f0 /* 4042322160 */ }, +}; +static const nir_search_expression search489_0_0_0_1_0_0_1_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iand, + { &search489_0_0_0_1_0_0_1_0_0.value, &search489_0_0_0_1_0_0_1_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_0_0_0_1_0_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x4 /* 4 */ }, +}; +static const nir_search_expression search489_0_0_0_1_0_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search489_0_0_0_1_0_0_1_0.value, &search489_0_0_0_1_0_0_1_1.value }, + NULL, +}; +static const nir_search_expression search489_0_0_0_1_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ior, + { &search489_0_0_0_1_0_0_0.value, &search489_0_0_0_1_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_0_0_0_1_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0xcccccccc /* 3435973836 */ }, +}; +static const nir_search_expression search489_0_0_0_1_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iand, + { &search489_0_0_0_1_0_0.value, &search489_0_0_0_1_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_0_0_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x2 /* 2 */ }, +}; +static const nir_search_expression search489_0_0_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search489_0_0_0_1_0.value, &search489_0_0_0_1_1.value }, + NULL, +}; +static const nir_search_expression search489_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ior, + { &search489_0_0_0_0.value, &search489_0_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x55555555 /* 1431655765 */ }, +}; +static const nir_search_expression search489_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iand, + { &search489_0_0_0.value, &search489_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x1 /* 1 */ }, +}; +static const nir_search_expression search489_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search489_0_0.value, &search489_0_1.value }, + NULL, +}; + +static const nir_search_variable search489_1_0_0_0_0_0_0_0_0_0_0_0_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search489_1_0_0_0_0_0_0_0_0_0_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search489_1_0_0_0_0_0_0_0_0_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search489_1_0_0_0_0_0_0_0_0_0_0_0_0_0.value, &search489_1_0_0_0_0_0_0_0_0_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search489_1_0_0_0_0_0_0_0_0_0_0_0_1_0 = { + { nir_search_value_variable, 32 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search489_1_0_0_0_0_0_0_0_0_0_0_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search489_1_0_0_0_0_0_0_0_0_0_0_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search489_1_0_0_0_0_0_0_0_0_0_0_0_1_0.value, &search489_1_0_0_0_0_0_0_0_0_0_0_0_1_1.value }, + NULL, +}; +static const nir_search_expression search489_1_0_0_0_0_0_0_0_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ior, + { &search489_1_0_0_0_0_0_0_0_0_0_0_0_0.value, &search489_1_0_0_0_0_0_0_0_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_1_0_0_0_0_0_0_0_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0xff00ff /* 16711935 */ }, +}; +static const nir_search_expression search489_1_0_0_0_0_0_0_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iand, + { &search489_1_0_0_0_0_0_0_0_0_0_0_0.value, &search489_1_0_0_0_0_0_0_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_1_0_0_0_0_0_0_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x8 /* 8 */ }, +}; +static const nir_search_expression search489_1_0_0_0_0_0_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search489_1_0_0_0_0_0_0_0_0_0_0.value, &search489_1_0_0_0_0_0_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search489_1_0_0_0_0_0_0_0_0_1_0_0_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search489_1_0_0_0_0_0_0_0_0_1_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search489_1_0_0_0_0_0_0_0_0_1_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search489_1_0_0_0_0_0_0_0_0_1_0_0_0_0.value, &search489_1_0_0_0_0_0_0_0_0_1_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search489_1_0_0_0_0_0_0_0_0_1_0_0_1_0 = { + { nir_search_value_variable, 32 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search489_1_0_0_0_0_0_0_0_0_1_0_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search489_1_0_0_0_0_0_0_0_0_1_0_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search489_1_0_0_0_0_0_0_0_0_1_0_0_1_0.value, &search489_1_0_0_0_0_0_0_0_0_1_0_0_1_1.value }, + NULL, +}; +static const nir_search_expression search489_1_0_0_0_0_0_0_0_0_1_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ior, + { &search489_1_0_0_0_0_0_0_0_0_1_0_0_0.value, &search489_1_0_0_0_0_0_0_0_0_1_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_1_0_0_0_0_0_0_0_0_1_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0xff00ff00 /* 4278255360 */ }, +}; +static const nir_search_expression search489_1_0_0_0_0_0_0_0_0_1_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iand, + { &search489_1_0_0_0_0_0_0_0_0_1_0_0.value, &search489_1_0_0_0_0_0_0_0_0_1_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_1_0_0_0_0_0_0_0_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x8 /* 8 */ }, +}; +static const nir_search_expression search489_1_0_0_0_0_0_0_0_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search489_1_0_0_0_0_0_0_0_0_1_0.value, &search489_1_0_0_0_0_0_0_0_0_1_1.value }, + NULL, +}; +static const nir_search_expression search489_1_0_0_0_0_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ior, + { &search489_1_0_0_0_0_0_0_0_0_0.value, &search489_1_0_0_0_0_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_1_0_0_0_0_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0xf0f0f0f /* 252645135 */ }, +}; +static const nir_search_expression search489_1_0_0_0_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iand, + { &search489_1_0_0_0_0_0_0_0_0.value, &search489_1_0_0_0_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_1_0_0_0_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x4 /* 4 */ }, +}; +static const nir_search_expression search489_1_0_0_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search489_1_0_0_0_0_0_0_0.value, &search489_1_0_0_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search489_1_0_0_0_0_0_1_0_0_0_0_0_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search489_1_0_0_0_0_0_1_0_0_0_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search489_1_0_0_0_0_0_1_0_0_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search489_1_0_0_0_0_0_1_0_0_0_0_0_0_0.value, &search489_1_0_0_0_0_0_1_0_0_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search489_1_0_0_0_0_0_1_0_0_0_0_0_1_0 = { + { nir_search_value_variable, 32 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search489_1_0_0_0_0_0_1_0_0_0_0_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search489_1_0_0_0_0_0_1_0_0_0_0_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search489_1_0_0_0_0_0_1_0_0_0_0_0_1_0.value, &search489_1_0_0_0_0_0_1_0_0_0_0_0_1_1.value }, + NULL, +}; +static const nir_search_expression search489_1_0_0_0_0_0_1_0_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ior, + { &search489_1_0_0_0_0_0_1_0_0_0_0_0_0.value, &search489_1_0_0_0_0_0_1_0_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_1_0_0_0_0_0_1_0_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0xff00ff /* 16711935 */ }, +}; +static const nir_search_expression search489_1_0_0_0_0_0_1_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iand, + { &search489_1_0_0_0_0_0_1_0_0_0_0_0.value, &search489_1_0_0_0_0_0_1_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_1_0_0_0_0_0_1_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x8 /* 8 */ }, +}; +static const nir_search_expression search489_1_0_0_0_0_0_1_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search489_1_0_0_0_0_0_1_0_0_0_0.value, &search489_1_0_0_0_0_0_1_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search489_1_0_0_0_0_0_1_0_0_1_0_0_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search489_1_0_0_0_0_0_1_0_0_1_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search489_1_0_0_0_0_0_1_0_0_1_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search489_1_0_0_0_0_0_1_0_0_1_0_0_0_0.value, &search489_1_0_0_0_0_0_1_0_0_1_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search489_1_0_0_0_0_0_1_0_0_1_0_0_1_0 = { + { nir_search_value_variable, 32 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search489_1_0_0_0_0_0_1_0_0_1_0_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search489_1_0_0_0_0_0_1_0_0_1_0_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search489_1_0_0_0_0_0_1_0_0_1_0_0_1_0.value, &search489_1_0_0_0_0_0_1_0_0_1_0_0_1_1.value }, + NULL, +}; +static const nir_search_expression search489_1_0_0_0_0_0_1_0_0_1_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ior, + { &search489_1_0_0_0_0_0_1_0_0_1_0_0_0.value, &search489_1_0_0_0_0_0_1_0_0_1_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_1_0_0_0_0_0_1_0_0_1_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0xff00ff00 /* 4278255360 */ }, +}; +static const nir_search_expression search489_1_0_0_0_0_0_1_0_0_1_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iand, + { &search489_1_0_0_0_0_0_1_0_0_1_0_0.value, &search489_1_0_0_0_0_0_1_0_0_1_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_1_0_0_0_0_0_1_0_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x8 /* 8 */ }, +}; +static const nir_search_expression search489_1_0_0_0_0_0_1_0_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search489_1_0_0_0_0_0_1_0_0_1_0.value, &search489_1_0_0_0_0_0_1_0_0_1_1.value }, + NULL, +}; +static const nir_search_expression search489_1_0_0_0_0_0_1_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ior, + { &search489_1_0_0_0_0_0_1_0_0_0.value, &search489_1_0_0_0_0_0_1_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_1_0_0_0_0_0_1_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0xf0f0f0f0 /* 4042322160 */ }, +}; +static const nir_search_expression search489_1_0_0_0_0_0_1_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iand, + { &search489_1_0_0_0_0_0_1_0_0.value, &search489_1_0_0_0_0_0_1_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_1_0_0_0_0_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x4 /* 4 */ }, +}; +static const nir_search_expression search489_1_0_0_0_0_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search489_1_0_0_0_0_0_1_0.value, &search489_1_0_0_0_0_0_1_1.value }, + NULL, +}; +static const nir_search_expression search489_1_0_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ior, + { &search489_1_0_0_0_0_0_0.value, &search489_1_0_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_1_0_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x33333333 /* 858993459 */ }, +}; +static const nir_search_expression search489_1_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iand, + { &search489_1_0_0_0_0_0.value, &search489_1_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_1_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x2 /* 2 */ }, +}; +static const nir_search_expression search489_1_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search489_1_0_0_0_0.value, &search489_1_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search489_1_0_0_1_0_0_0_0_0_0_0_0_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search489_1_0_0_1_0_0_0_0_0_0_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search489_1_0_0_1_0_0_0_0_0_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search489_1_0_0_1_0_0_0_0_0_0_0_0_0_0.value, &search489_1_0_0_1_0_0_0_0_0_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search489_1_0_0_1_0_0_0_0_0_0_0_0_1_0 = { + { nir_search_value_variable, 32 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search489_1_0_0_1_0_0_0_0_0_0_0_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search489_1_0_0_1_0_0_0_0_0_0_0_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search489_1_0_0_1_0_0_0_0_0_0_0_0_1_0.value, &search489_1_0_0_1_0_0_0_0_0_0_0_0_1_1.value }, + NULL, +}; +static const nir_search_expression search489_1_0_0_1_0_0_0_0_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ior, + { &search489_1_0_0_1_0_0_0_0_0_0_0_0_0.value, &search489_1_0_0_1_0_0_0_0_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_1_0_0_1_0_0_0_0_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0xff00ff /* 16711935 */ }, +}; +static const nir_search_expression search489_1_0_0_1_0_0_0_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iand, + { &search489_1_0_0_1_0_0_0_0_0_0_0_0.value, &search489_1_0_0_1_0_0_0_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_1_0_0_1_0_0_0_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x8 /* 8 */ }, +}; +static const nir_search_expression search489_1_0_0_1_0_0_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search489_1_0_0_1_0_0_0_0_0_0_0.value, &search489_1_0_0_1_0_0_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search489_1_0_0_1_0_0_0_0_0_1_0_0_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search489_1_0_0_1_0_0_0_0_0_1_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search489_1_0_0_1_0_0_0_0_0_1_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search489_1_0_0_1_0_0_0_0_0_1_0_0_0_0.value, &search489_1_0_0_1_0_0_0_0_0_1_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search489_1_0_0_1_0_0_0_0_0_1_0_0_1_0 = { + { nir_search_value_variable, 32 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search489_1_0_0_1_0_0_0_0_0_1_0_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search489_1_0_0_1_0_0_0_0_0_1_0_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search489_1_0_0_1_0_0_0_0_0_1_0_0_1_0.value, &search489_1_0_0_1_0_0_0_0_0_1_0_0_1_1.value }, + NULL, +}; +static const nir_search_expression search489_1_0_0_1_0_0_0_0_0_1_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ior, + { &search489_1_0_0_1_0_0_0_0_0_1_0_0_0.value, &search489_1_0_0_1_0_0_0_0_0_1_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_1_0_0_1_0_0_0_0_0_1_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0xff00ff00 /* 4278255360 */ }, +}; +static const nir_search_expression search489_1_0_0_1_0_0_0_0_0_1_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iand, + { &search489_1_0_0_1_0_0_0_0_0_1_0_0.value, &search489_1_0_0_1_0_0_0_0_0_1_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_1_0_0_1_0_0_0_0_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x8 /* 8 */ }, +}; +static const nir_search_expression search489_1_0_0_1_0_0_0_0_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search489_1_0_0_1_0_0_0_0_0_1_0.value, &search489_1_0_0_1_0_0_0_0_0_1_1.value }, + NULL, +}; +static const nir_search_expression search489_1_0_0_1_0_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ior, + { &search489_1_0_0_1_0_0_0_0_0_0.value, &search489_1_0_0_1_0_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_1_0_0_1_0_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0xf0f0f0f /* 252645135 */ }, +}; +static const nir_search_expression search489_1_0_0_1_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iand, + { &search489_1_0_0_1_0_0_0_0_0.value, &search489_1_0_0_1_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_1_0_0_1_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x4 /* 4 */ }, +}; +static const nir_search_expression search489_1_0_0_1_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search489_1_0_0_1_0_0_0_0.value, &search489_1_0_0_1_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search489_1_0_0_1_0_0_1_0_0_0_0_0_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search489_1_0_0_1_0_0_1_0_0_0_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search489_1_0_0_1_0_0_1_0_0_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search489_1_0_0_1_0_0_1_0_0_0_0_0_0_0.value, &search489_1_0_0_1_0_0_1_0_0_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search489_1_0_0_1_0_0_1_0_0_0_0_0_1_0 = { + { nir_search_value_variable, 32 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search489_1_0_0_1_0_0_1_0_0_0_0_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search489_1_0_0_1_0_0_1_0_0_0_0_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search489_1_0_0_1_0_0_1_0_0_0_0_0_1_0.value, &search489_1_0_0_1_0_0_1_0_0_0_0_0_1_1.value }, + NULL, +}; +static const nir_search_expression search489_1_0_0_1_0_0_1_0_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ior, + { &search489_1_0_0_1_0_0_1_0_0_0_0_0_0.value, &search489_1_0_0_1_0_0_1_0_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_1_0_0_1_0_0_1_0_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0xff00ff /* 16711935 */ }, +}; +static const nir_search_expression search489_1_0_0_1_0_0_1_0_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iand, + { &search489_1_0_0_1_0_0_1_0_0_0_0_0.value, &search489_1_0_0_1_0_0_1_0_0_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_1_0_0_1_0_0_1_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x8 /* 8 */ }, +}; +static const nir_search_expression search489_1_0_0_1_0_0_1_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search489_1_0_0_1_0_0_1_0_0_0_0.value, &search489_1_0_0_1_0_0_1_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search489_1_0_0_1_0_0_1_0_0_1_0_0_0_0 = { + { nir_search_value_variable, 32 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search489_1_0_0_1_0_0_1_0_0_1_0_0_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search489_1_0_0_1_0_0_1_0_0_1_0_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ishl, + { &search489_1_0_0_1_0_0_1_0_0_1_0_0_0_0.value, &search489_1_0_0_1_0_0_1_0_0_1_0_0_0_1.value }, + NULL, +}; + +static const nir_search_variable search489_1_0_0_1_0_0_1_0_0_1_0_0_1_0 = { + { nir_search_value_variable, 32 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_constant search489_1_0_0_1_0_0_1_0_0_1_0_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x10 /* 16 */ }, +}; +static const nir_search_expression search489_1_0_0_1_0_0_1_0_0_1_0_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search489_1_0_0_1_0_0_1_0_0_1_0_0_1_0.value, &search489_1_0_0_1_0_0_1_0_0_1_0_0_1_1.value }, + NULL, +}; +static const nir_search_expression search489_1_0_0_1_0_0_1_0_0_1_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ior, + { &search489_1_0_0_1_0_0_1_0_0_1_0_0_0.value, &search489_1_0_0_1_0_0_1_0_0_1_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_1_0_0_1_0_0_1_0_0_1_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0xff00ff00 /* 4278255360 */ }, +}; +static const nir_search_expression search489_1_0_0_1_0_0_1_0_0_1_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iand, + { &search489_1_0_0_1_0_0_1_0_0_1_0_0.value, &search489_1_0_0_1_0_0_1_0_0_1_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_1_0_0_1_0_0_1_0_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x8 /* 8 */ }, +}; +static const nir_search_expression search489_1_0_0_1_0_0_1_0_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search489_1_0_0_1_0_0_1_0_0_1_0.value, &search489_1_0_0_1_0_0_1_0_0_1_1.value }, + NULL, +}; +static const nir_search_expression search489_1_0_0_1_0_0_1_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ior, + { &search489_1_0_0_1_0_0_1_0_0_0.value, &search489_1_0_0_1_0_0_1_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_1_0_0_1_0_0_1_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0xf0f0f0f0 /* 4042322160 */ }, +}; +static const nir_search_expression search489_1_0_0_1_0_0_1_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iand, + { &search489_1_0_0_1_0_0_1_0_0.value, &search489_1_0_0_1_0_0_1_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_1_0_0_1_0_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x4 /* 4 */ }, +}; +static const nir_search_expression search489_1_0_0_1_0_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search489_1_0_0_1_0_0_1_0.value, &search489_1_0_0_1_0_0_1_1.value }, + NULL, +}; +static const nir_search_expression search489_1_0_0_1_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ior, + { &search489_1_0_0_1_0_0_0.value, &search489_1_0_0_1_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_1_0_0_1_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0xcccccccc /* 3435973836 */ }, +}; +static const nir_search_expression search489_1_0_0_1_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iand, + { &search489_1_0_0_1_0_0.value, &search489_1_0_0_1_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_1_0_0_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x2 /* 2 */ }, +}; +static const nir_search_expression search489_1_0_0_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search489_1_0_0_1_0.value, &search489_1_0_0_1_1.value }, + NULL, +}; +static const nir_search_expression search489_1_0_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ior, + { &search489_1_0_0_0.value, &search489_1_0_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_1_0_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0xaaaaaaaa /* 2863311530 */ }, +}; +static const nir_search_expression search489_1_0 = { + { nir_search_value_expression, 32 }, + false, + nir_op_iand, + { &search489_1_0_0.value, &search489_1_0_1.value }, + NULL, +}; + +static const nir_search_constant search489_1_1 = { + { nir_search_value_constant, 32 }, + nir_type_int, { 0x1 /* 1 */ }, +}; +static const nir_search_expression search489_1 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ushr, + { &search489_1_0.value, &search489_1_1.value }, + NULL, +}; +static const nir_search_expression search489 = { + { nir_search_value_expression, 32 }, + false, + nir_op_ior, + { &search489_0.value, &search489_1.value }, + NULL, +}; + +static const nir_search_variable replace489_0 = { + { nir_search_value_variable, 32 }, + 0, /* x */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace489 = { + { nir_search_value_expression, 32 }, + false, + nir_op_bitfield_reverse, + { &replace489_0.value }, + NULL, +}; + +static const nir_search_variable search490_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search490_0_1 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search490_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &search490_0_0.value, &search490_0_1.value }, + NULL, +}; + +static const nir_search_variable search490_1_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search490_1_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search490_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search490_1_0.value, &search490_1_1.value }, + NULL, +}; +static const nir_search_expression search490 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &search490_0.value, &search490_1.value }, + NULL, +}; + +static const nir_search_variable replace490_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace490_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace490 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &replace490_0.value, &replace490_1.value }, + NULL, +}; + +static const nir_search_variable search491_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search491_0_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search491_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &search491_0_0.value, &search491_0_1.value }, + NULL, +}; + +static const nir_search_variable search491_1_0 = { + { nir_search_value_variable, -1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search491_1_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search491_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search491_1_0.value, &search491_1_1.value }, + NULL, +}; +static const nir_search_expression search491 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &search491_0.value, &search491_1.value }, + NULL, +}; + +static const nir_search_variable replace491_0 = { + { nir_search_value_variable, -1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace491_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace491 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &replace491_0.value, &replace491_1.value }, + NULL, +}; + +static const nir_search_variable search492_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search492_0_1 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search492_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &search492_0_0.value, &search492_0_1.value }, + NULL, +}; + +static const nir_search_variable search492_1_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search492_1_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search492_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search492_1_0.value, &search492_1_1.value }, + NULL, +}; +static const nir_search_expression search492 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &search492_0.value, &search492_1.value }, + NULL, +}; + +static const nir_search_variable replace492_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace492_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace492 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &replace492_0.value, &replace492_1.value }, + NULL, +}; + +static const nir_search_variable search493_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search493_0_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search493_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &search493_0_0.value, &search493_0_1.value }, + NULL, +}; + +static const nir_search_variable search493_1_0 = { + { nir_search_value_variable, -1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search493_1_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search493_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search493_1_0.value, &search493_1_1.value }, + NULL, +}; +static const nir_search_expression search493 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &search493_0.value, &search493_1.value }, + NULL, +}; + +static const nir_search_variable replace493_0 = { + { nir_search_value_variable, -1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace493_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace493 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &replace493_0.value, &replace493_1.value }, + NULL, +}; + +static const nir_search_variable search494_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search494_0_1 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search494_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &search494_0_0.value, &search494_0_1.value }, + NULL, +}; + +static const nir_search_variable search494_1_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search494_1_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search494_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &search494_1_0.value, &search494_1_1.value }, + NULL, +}; +static const nir_search_expression search494 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &search494_0.value, &search494_1.value }, + NULL, +}; + +static const nir_search_variable replace494_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace494_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace494 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &replace494_0.value, &replace494_1.value }, + NULL, +}; + +static const nir_search_variable search495_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search495_0_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search495_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &search495_0_0.value, &search495_0_1.value }, + NULL, +}; + +static const nir_search_variable search495_1_0 = { + { nir_search_value_variable, -1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search495_1_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search495_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &search495_1_0.value, &search495_1_1.value }, + NULL, +}; +static const nir_search_expression search495 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &search495_0.value, &search495_1.value }, + NULL, +}; + +static const nir_search_variable replace495_0 = { + { nir_search_value_variable, -1 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace495_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace495 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &replace495_0.value, &replace495_1.value }, + NULL, +}; + +static const nir_search_variable search496_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search496_0_1 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search496_0_2 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search496_0 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &search496_0_0.value, &search496_0_1.value, &search496_0_2.value }, + NULL, +}; + +static const nir_search_variable search496_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search496 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search496_0.value, &search496_1.value }, + NULL, +}; + +static const nir_search_variable replace496_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace496_1_0 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace496_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace496_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &replace496_1_0.value, &replace496_1_1.value }, + NULL, +}; + +static const nir_search_variable replace496_2_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace496_2_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace496_2 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &replace496_2_0.value, &replace496_2_1.value }, + NULL, +}; +static const nir_search_expression replace496 = { + { nir_search_value_expression, 1 }, + false, + nir_op_bcsel, + { &replace496_0.value, &replace496_1.value, &replace496_2.value }, + NULL, +}; + +static const nir_search_variable search497_0 = { + { nir_search_value_variable, -4 }, + 0, /* d */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search497_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search497_1_1 = { + { nir_search_value_variable, -4 }, + 2, /* b */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search497_1_2 = { + { nir_search_value_variable, -4 }, + 3, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search497_1 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &search497_1_0.value, &search497_1_1.value, &search497_1_2.value }, + NULL, +}; +static const nir_search_expression search497 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search497_0.value, &search497_1.value }, + NULL, +}; + +static const nir_search_variable replace497_0 = { + { nir_search_value_variable, 1 }, + 1, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace497_1_0 = { + { nir_search_value_variable, -4 }, + 0, /* d */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace497_1_1 = { + { nir_search_value_variable, -4 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace497_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &replace497_1_0.value, &replace497_1_1.value }, + NULL, +}; + +static const nir_search_variable replace497_2_0 = { + { nir_search_value_variable, -4 }, + 0, /* d */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace497_2_1 = { + { nir_search_value_variable, -4 }, + 3, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace497_2 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &replace497_2_0.value, &replace497_2_1.value }, + NULL, +}; +static const nir_search_expression replace497 = { + { nir_search_value_expression, 1 }, + false, + nir_op_bcsel, + { &replace497_0.value, &replace497_1.value, &replace497_2.value }, + NULL, +}; + +static const nir_search_variable search498_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search498_0_1 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search498_0_2 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search498_0 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &search498_0_0.value, &search498_0_1.value, &search498_0_2.value }, + NULL, +}; + +static const nir_search_variable search498_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search498 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search498_0.value, &search498_1.value }, + NULL, +}; + +static const nir_search_variable replace498_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace498_1_0 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace498_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace498_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &replace498_1_0.value, &replace498_1_1.value }, + NULL, +}; + +static const nir_search_variable replace498_2_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace498_2_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace498_2 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &replace498_2_0.value, &replace498_2_1.value }, + NULL, +}; +static const nir_search_expression replace498 = { + { nir_search_value_expression, 1 }, + false, + nir_op_bcsel, + { &replace498_0.value, &replace498_1.value, &replace498_2.value }, + NULL, +}; + +static const nir_search_variable search499_0 = { + { nir_search_value_variable, -4 }, + 0, /* d */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search499_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search499_1_1 = { + { nir_search_value_variable, -4 }, + 2, /* b */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search499_1_2 = { + { nir_search_value_variable, -4 }, + 3, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search499_1 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &search499_1_0.value, &search499_1_1.value, &search499_1_2.value }, + NULL, +}; +static const nir_search_expression search499 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &search499_0.value, &search499_1.value }, + NULL, +}; + +static const nir_search_variable replace499_0 = { + { nir_search_value_variable, 1 }, + 1, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace499_1_0 = { + { nir_search_value_variable, -4 }, + 0, /* d */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace499_1_1 = { + { nir_search_value_variable, -4 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace499_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &replace499_1_0.value, &replace499_1_1.value }, + NULL, +}; + +static const nir_search_variable replace499_2_0 = { + { nir_search_value_variable, -4 }, + 0, /* d */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace499_2_1 = { + { nir_search_value_variable, -4 }, + 3, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace499_2 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &replace499_2_0.value, &replace499_2_1.value }, + NULL, +}; +static const nir_search_expression replace499 = { + { nir_search_value_expression, 1 }, + false, + nir_op_bcsel, + { &replace499_0.value, &replace499_1.value, &replace499_2.value }, + NULL, +}; + +static const nir_search_variable search500_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search500_0_1 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search500_0_2 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search500_0 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &search500_0_0.value, &search500_0_1.value, &search500_0_2.value }, + NULL, +}; + +static const nir_search_variable search500_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search500 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &search500_0.value, &search500_1.value }, + NULL, +}; + +static const nir_search_variable replace500_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace500_1_0 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace500_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace500_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &replace500_1_0.value, &replace500_1_1.value }, + NULL, +}; + +static const nir_search_variable replace500_2_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace500_2_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace500_2 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &replace500_2_0.value, &replace500_2_1.value }, + NULL, +}; +static const nir_search_expression replace500 = { + { nir_search_value_expression, 1 }, + false, + nir_op_bcsel, + { &replace500_0.value, &replace500_1.value, &replace500_2.value }, + NULL, +}; + +static const nir_search_variable search501_0 = { + { nir_search_value_variable, -4 }, + 0, /* d */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search501_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search501_1_1 = { + { nir_search_value_variable, -4 }, + 2, /* b */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search501_1_2 = { + { nir_search_value_variable, -4 }, + 3, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search501_1 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &search501_1_0.value, &search501_1_1.value, &search501_1_2.value }, + NULL, +}; +static const nir_search_expression search501 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &search501_0.value, &search501_1.value }, + NULL, +}; + +static const nir_search_variable replace501_0 = { + { nir_search_value_variable, 1 }, + 1, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace501_1_0 = { + { nir_search_value_variable, -4 }, + 0, /* d */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace501_1_1 = { + { nir_search_value_variable, -4 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace501_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &replace501_1_0.value, &replace501_1_1.value }, + NULL, +}; + +static const nir_search_variable replace501_2_0 = { + { nir_search_value_variable, -4 }, + 0, /* d */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace501_2_1 = { + { nir_search_value_variable, -4 }, + 3, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace501_2 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &replace501_2_0.value, &replace501_2_1.value }, + NULL, +}; +static const nir_search_expression replace501 = { + { nir_search_value_expression, 1 }, + false, + nir_op_bcsel, + { &replace501_0.value, &replace501_1.value, &replace501_2.value }, + NULL, +}; + +static const nir_search_variable search502_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search502_0_1 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search502_0_2 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search502_0 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &search502_0_0.value, &search502_0_1.value, &search502_0_2.value }, + NULL, +}; + +static const nir_search_variable search502_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search502 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &search502_0.value, &search502_1.value }, + NULL, +}; + +static const nir_search_variable replace502_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace502_1_0 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace502_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace502_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &replace502_1_0.value, &replace502_1_1.value }, + NULL, +}; + +static const nir_search_variable replace502_2_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace502_2_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace502_2 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &replace502_2_0.value, &replace502_2_1.value }, + NULL, +}; +static const nir_search_expression replace502 = { + { nir_search_value_expression, 1 }, + false, + nir_op_bcsel, + { &replace502_0.value, &replace502_1.value, &replace502_2.value }, + NULL, +}; + +static const nir_search_variable search503_0 = { + { nir_search_value_variable, -4 }, + 0, /* d */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search503_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search503_1_1 = { + { nir_search_value_variable, -4 }, + 2, /* b */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search503_1_2 = { + { nir_search_value_variable, -4 }, + 3, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search503_1 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &search503_1_0.value, &search503_1_1.value, &search503_1_2.value }, + NULL, +}; +static const nir_search_expression search503 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &search503_0.value, &search503_1.value }, + NULL, +}; + +static const nir_search_variable replace503_0 = { + { nir_search_value_variable, 1 }, + 1, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace503_1_0 = { + { nir_search_value_variable, -4 }, + 0, /* d */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace503_1_1 = { + { nir_search_value_variable, -4 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace503_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &replace503_1_0.value, &replace503_1_1.value }, + NULL, +}; + +static const nir_search_variable replace503_2_0 = { + { nir_search_value_variable, -4 }, + 0, /* d */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace503_2_1 = { + { nir_search_value_variable, -4 }, + 3, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace503_2 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &replace503_2_0.value, &replace503_2_1.value }, + NULL, +}; +static const nir_search_expression replace503 = { + { nir_search_value_expression, 1 }, + false, + nir_op_bcsel, + { &replace503_0.value, &replace503_1.value, &replace503_2.value }, + NULL, +}; + +static const nir_search_variable search504_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search504_0_1 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search504_0_2 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search504_0 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &search504_0_0.value, &search504_0_1.value, &search504_0_2.value }, + NULL, +}; + +static const nir_search_variable search504_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search504 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &search504_0.value, &search504_1.value }, + NULL, +}; + +static const nir_search_variable replace504_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace504_1_0 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace504_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace504_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &replace504_1_0.value, &replace504_1_1.value }, + NULL, +}; + +static const nir_search_variable replace504_2_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace504_2_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace504_2 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &replace504_2_0.value, &replace504_2_1.value }, + NULL, +}; +static const nir_search_expression replace504 = { + { nir_search_value_expression, 1 }, + false, + nir_op_bcsel, + { &replace504_0.value, &replace504_1.value, &replace504_2.value }, + NULL, +}; + +static const nir_search_variable search505_0 = { + { nir_search_value_variable, -4 }, + 0, /* d */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search505_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search505_1_1 = { + { nir_search_value_variable, -4 }, + 2, /* b */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search505_1_2 = { + { nir_search_value_variable, -4 }, + 3, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search505_1 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &search505_1_0.value, &search505_1_1.value, &search505_1_2.value }, + NULL, +}; +static const nir_search_expression search505 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &search505_0.value, &search505_1.value }, + NULL, +}; + +static const nir_search_variable replace505_0 = { + { nir_search_value_variable, 1 }, + 1, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace505_1_0 = { + { nir_search_value_variable, -4 }, + 0, /* d */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace505_1_1 = { + { nir_search_value_variable, -4 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace505_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &replace505_1_0.value, &replace505_1_1.value }, + NULL, +}; + +static const nir_search_variable replace505_2_0 = { + { nir_search_value_variable, -4 }, + 0, /* d */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace505_2_1 = { + { nir_search_value_variable, -4 }, + 3, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace505_2 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ilt, + { &replace505_2_0.value, &replace505_2_1.value }, + NULL, +}; +static const nir_search_expression replace505 = { + { nir_search_value_expression, 1 }, + false, + nir_op_bcsel, + { &replace505_0.value, &replace505_1.value, &replace505_2.value }, + NULL, +}; + +static const nir_search_variable search506_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search506_0_1 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search506_0_2 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search506_0 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &search506_0_0.value, &search506_0_1.value, &search506_0_2.value }, + NULL, +}; + +static const nir_search_variable search506_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search506 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &search506_0.value, &search506_1.value }, + NULL, +}; + +static const nir_search_variable replace506_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace506_1_0 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace506_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace506_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &replace506_1_0.value, &replace506_1_1.value }, + NULL, +}; + +static const nir_search_variable replace506_2_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace506_2_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace506_2 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &replace506_2_0.value, &replace506_2_1.value }, + NULL, +}; +static const nir_search_expression replace506 = { + { nir_search_value_expression, 1 }, + false, + nir_op_bcsel, + { &replace506_0.value, &replace506_1.value, &replace506_2.value }, + NULL, +}; + +static const nir_search_variable search507_0 = { + { nir_search_value_variable, -4 }, + 0, /* d */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search507_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search507_1_1 = { + { nir_search_value_variable, -4 }, + 2, /* b */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search507_1_2 = { + { nir_search_value_variable, -4 }, + 3, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search507_1 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &search507_1_0.value, &search507_1_1.value, &search507_1_2.value }, + NULL, +}; +static const nir_search_expression search507 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &search507_0.value, &search507_1.value }, + NULL, +}; + +static const nir_search_variable replace507_0 = { + { nir_search_value_variable, 1 }, + 1, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace507_1_0 = { + { nir_search_value_variable, -4 }, + 0, /* d */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace507_1_1 = { + { nir_search_value_variable, -4 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace507_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &replace507_1_0.value, &replace507_1_1.value }, + NULL, +}; + +static const nir_search_variable replace507_2_0 = { + { nir_search_value_variable, -4 }, + 0, /* d */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace507_2_1 = { + { nir_search_value_variable, -4 }, + 3, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace507_2 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ige, + { &replace507_2_0.value, &replace507_2_1.value }, + NULL, +}; +static const nir_search_expression replace507 = { + { nir_search_value_expression, 1 }, + false, + nir_op_bcsel, + { &replace507_0.value, &replace507_1.value, &replace507_2.value }, + NULL, +}; + +static const nir_search_variable search508_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search508_0_1 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search508_0_2 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search508_0 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &search508_0_0.value, &search508_0_1.value, &search508_0_2.value }, + NULL, +}; + +static const nir_search_variable search508_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search508 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ieq, + { &search508_0.value, &search508_1.value }, + NULL, +}; + +static const nir_search_variable replace508_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace508_1_0 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace508_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace508_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ieq, + { &replace508_1_0.value, &replace508_1_1.value }, + NULL, +}; + +static const nir_search_variable replace508_2_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace508_2_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace508_2 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ieq, + { &replace508_2_0.value, &replace508_2_1.value }, + NULL, +}; +static const nir_search_expression replace508 = { + { nir_search_value_expression, 1 }, + false, + nir_op_bcsel, + { &replace508_0.value, &replace508_1.value, &replace508_2.value }, + NULL, +}; + +static const nir_search_variable search509_0 = { + { nir_search_value_variable, -4 }, + 0, /* d */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search509_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search509_1_1 = { + { nir_search_value_variable, -4 }, + 2, /* b */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search509_1_2 = { + { nir_search_value_variable, -4 }, + 3, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search509_1 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &search509_1_0.value, &search509_1_1.value, &search509_1_2.value }, + NULL, +}; +static const nir_search_expression search509 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ieq, + { &search509_0.value, &search509_1.value }, + NULL, +}; + +static const nir_search_variable replace509_0 = { + { nir_search_value_variable, 1 }, + 1, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace509_1_0 = { + { nir_search_value_variable, -4 }, + 0, /* d */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace509_1_1 = { + { nir_search_value_variable, -4 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace509_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ieq, + { &replace509_1_0.value, &replace509_1_1.value }, + NULL, +}; + +static const nir_search_variable replace509_2_0 = { + { nir_search_value_variable, -4 }, + 0, /* d */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace509_2_1 = { + { nir_search_value_variable, -4 }, + 3, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace509_2 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ieq, + { &replace509_2_0.value, &replace509_2_1.value }, + NULL, +}; +static const nir_search_expression replace509 = { + { nir_search_value_expression, 1 }, + false, + nir_op_bcsel, + { &replace509_0.value, &replace509_1.value, &replace509_2.value }, + NULL, +}; + +static const nir_search_variable search510_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search510_0_1 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search510_0_2 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search510_0 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &search510_0_0.value, &search510_0_1.value, &search510_0_2.value }, + NULL, +}; + +static const nir_search_variable search510_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search510 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ine, + { &search510_0.value, &search510_1.value }, + NULL, +}; + +static const nir_search_variable replace510_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace510_1_0 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace510_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace510_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ine, + { &replace510_1_0.value, &replace510_1_1.value }, + NULL, +}; + +static const nir_search_variable replace510_2_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace510_2_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace510_2 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ine, + { &replace510_2_0.value, &replace510_2_1.value }, + NULL, +}; +static const nir_search_expression replace510 = { + { nir_search_value_expression, 1 }, + false, + nir_op_bcsel, + { &replace510_0.value, &replace510_1.value, &replace510_2.value }, + NULL, +}; + +static const nir_search_variable search511_0 = { + { nir_search_value_variable, -4 }, + 0, /* d */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search511_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search511_1_1 = { + { nir_search_value_variable, -4 }, + 2, /* b */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search511_1_2 = { + { nir_search_value_variable, -4 }, + 3, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search511_1 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &search511_1_0.value, &search511_1_1.value, &search511_1_2.value }, + NULL, +}; +static const nir_search_expression search511 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ine, + { &search511_0.value, &search511_1.value }, + NULL, +}; + +static const nir_search_variable replace511_0 = { + { nir_search_value_variable, 1 }, + 1, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace511_1_0 = { + { nir_search_value_variable, -4 }, + 0, /* d */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace511_1_1 = { + { nir_search_value_variable, -4 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace511_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ine, + { &replace511_1_0.value, &replace511_1_1.value }, + NULL, +}; + +static const nir_search_variable replace511_2_0 = { + { nir_search_value_variable, -4 }, + 0, /* d */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace511_2_1 = { + { nir_search_value_variable, -4 }, + 3, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace511_2 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ine, + { &replace511_2_0.value, &replace511_2_1.value }, + NULL, +}; +static const nir_search_expression replace511 = { + { nir_search_value_expression, 1 }, + false, + nir_op_bcsel, + { &replace511_0.value, &replace511_1.value, &replace511_2.value }, + NULL, +}; + +static const nir_search_variable search512_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search512_0_1 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search512_0_2 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search512_0 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &search512_0_0.value, &search512_0_1.value, &search512_0_2.value }, + NULL, +}; + +static const nir_search_variable search512_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search512 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &search512_0.value, &search512_1.value }, + NULL, +}; + +static const nir_search_variable replace512_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace512_1_0 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace512_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace512_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &replace512_1_0.value, &replace512_1_1.value }, + NULL, +}; + +static const nir_search_variable replace512_2_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace512_2_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace512_2 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &replace512_2_0.value, &replace512_2_1.value }, + NULL, +}; +static const nir_search_expression replace512 = { + { nir_search_value_expression, 1 }, + false, + nir_op_bcsel, + { &replace512_0.value, &replace512_1.value, &replace512_2.value }, + NULL, +}; + +static const nir_search_variable search513_0 = { + { nir_search_value_variable, -4 }, + 0, /* d */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search513_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search513_1_1 = { + { nir_search_value_variable, -4 }, + 2, /* b */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search513_1_2 = { + { nir_search_value_variable, -4 }, + 3, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search513_1 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &search513_1_0.value, &search513_1_1.value, &search513_1_2.value }, + NULL, +}; +static const nir_search_expression search513 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &search513_0.value, &search513_1.value }, + NULL, +}; + +static const nir_search_variable replace513_0 = { + { nir_search_value_variable, 1 }, + 1, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace513_1_0 = { + { nir_search_value_variable, -4 }, + 0, /* d */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace513_1_1 = { + { nir_search_value_variable, -4 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace513_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &replace513_1_0.value, &replace513_1_1.value }, + NULL, +}; + +static const nir_search_variable replace513_2_0 = { + { nir_search_value_variable, -4 }, + 0, /* d */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace513_2_1 = { + { nir_search_value_variable, -4 }, + 3, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace513_2 = { + { nir_search_value_expression, 1 }, + false, + nir_op_ult, + { &replace513_2_0.value, &replace513_2_1.value }, + NULL, +}; +static const nir_search_expression replace513 = { + { nir_search_value_expression, 1 }, + false, + nir_op_bcsel, + { &replace513_0.value, &replace513_1.value, &replace513_2.value }, + NULL, +}; + +static const nir_search_variable search514_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search514_0_1 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search514_0_2 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search514_0 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &search514_0_0.value, &search514_0_1.value, &search514_0_2.value }, + NULL, +}; + +static const nir_search_variable search514_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search514 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &search514_0.value, &search514_1.value }, + NULL, +}; + +static const nir_search_variable replace514_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace514_1_0 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace514_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace514_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &replace514_1_0.value, &replace514_1_1.value }, + NULL, +}; + +static const nir_search_variable replace514_2_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace514_2_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace514_2 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &replace514_2_0.value, &replace514_2_1.value }, + NULL, +}; +static const nir_search_expression replace514 = { + { nir_search_value_expression, 1 }, + false, + nir_op_bcsel, + { &replace514_0.value, &replace514_1.value, &replace514_2.value }, + NULL, +}; + +static const nir_search_variable search515_0 = { + { nir_search_value_variable, -4 }, + 0, /* d */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search515_1_0 = { + { nir_search_value_variable, 1 }, + 1, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search515_1_1 = { + { nir_search_value_variable, -4 }, + 2, /* b */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search515_1_2 = { + { nir_search_value_variable, -4 }, + 3, /* c */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search515_1 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &search515_1_0.value, &search515_1_1.value, &search515_1_2.value }, + NULL, +}; +static const nir_search_expression search515 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &search515_0.value, &search515_1.value }, + NULL, +}; + +static const nir_search_variable replace515_0 = { + { nir_search_value_variable, 1 }, + 1, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace515_1_0 = { + { nir_search_value_variable, -4 }, + 0, /* d */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace515_1_1 = { + { nir_search_value_variable, -4 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace515_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &replace515_1_0.value, &replace515_1_1.value }, + NULL, +}; + +static const nir_search_variable replace515_2_0 = { + { nir_search_value_variable, -4 }, + 0, /* d */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace515_2_1 = { + { nir_search_value_variable, -4 }, + 3, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace515_2 = { + { nir_search_value_expression, 1 }, + false, + nir_op_uge, + { &replace515_2_0.value, &replace515_2_1.value }, + NULL, +}; +static const nir_search_expression replace515 = { + { nir_search_value_expression, 1 }, + false, + nir_op_bcsel, + { &replace515_0.value, &replace515_1.value, &replace515_2.value }, + NULL, +}; + +static const nir_search_variable search516_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search516_0_1 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search516_0_2 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search516_0 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &search516_0_0.value, &search516_0_1.value, &search516_0_2.value }, + (is_used_once), +}; + +static const nir_search_variable search516_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search516 = { + { nir_search_value_expression, -4 }, + false, + nir_op_fadd, + { &search516_0.value, &search516_1.value }, + NULL, +}; + +static const nir_search_variable replace516_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace516_1_0 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace516_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace516_1 = { + { nir_search_value_expression, -4 }, + false, + nir_op_fadd, + { &replace516_1_0.value, &replace516_1_1.value }, + NULL, +}; + +static const nir_search_variable replace516_2_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace516_2_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace516_2 = { + { nir_search_value_expression, -4 }, + false, + nir_op_fadd, + { &replace516_2_0.value, &replace516_2_1.value }, + NULL, +}; +static const nir_search_expression replace516 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &replace516_0.value, &replace516_1.value, &replace516_2.value }, + NULL, +}; + +static const nir_search_variable search517_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search517_0_1 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search517_0_2 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search517_0 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &search517_0_0.value, &search517_0_1.value, &search517_0_2.value }, + (is_used_once), +}; + +static const nir_search_variable search517_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search517 = { + { nir_search_value_expression, -4 }, + false, + nir_op_fmul, + { &search517_0.value, &search517_1.value }, + NULL, +}; + +static const nir_search_variable replace517_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace517_1_0 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace517_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace517_1 = { + { nir_search_value_expression, -4 }, + false, + nir_op_fmul, + { &replace517_1_0.value, &replace517_1_1.value }, + NULL, +}; + +static const nir_search_variable replace517_2_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace517_2_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace517_2 = { + { nir_search_value_expression, -4 }, + false, + nir_op_fmul, + { &replace517_2_0.value, &replace517_2_1.value }, + NULL, +}; +static const nir_search_expression replace517 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &replace517_0.value, &replace517_1.value, &replace517_2.value }, + NULL, +}; + +static const nir_search_variable search518_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search518_0_1 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search518_0_2 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search518_0 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &search518_0_0.value, &search518_0_1.value, &search518_0_2.value }, + (is_used_once), +}; + +static const nir_search_variable search518_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search518 = { + { nir_search_value_expression, -4 }, + false, + nir_op_iadd, + { &search518_0.value, &search518_1.value }, + NULL, +}; + +static const nir_search_variable replace518_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace518_1_0 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace518_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace518_1 = { + { nir_search_value_expression, -4 }, + false, + nir_op_iadd, + { &replace518_1_0.value, &replace518_1_1.value }, + NULL, +}; + +static const nir_search_variable replace518_2_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace518_2_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace518_2 = { + { nir_search_value_expression, -4 }, + false, + nir_op_iadd, + { &replace518_2_0.value, &replace518_2_1.value }, + NULL, +}; +static const nir_search_expression replace518 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &replace518_0.value, &replace518_1.value, &replace518_2.value }, + NULL, +}; + +static const nir_search_variable search519_0_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search519_0_1 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search519_0_2 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search519_0 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &search519_0_0.value, &search519_0_1.value, &search519_0_2.value }, + (is_used_once), +}; + +static const nir_search_variable search519_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search519 = { + { nir_search_value_expression, -4 }, + false, + nir_op_imul, + { &search519_0.value, &search519_1.value }, + NULL, +}; + +static const nir_search_variable replace519_0 = { + { nir_search_value_variable, 1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace519_1_0 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace519_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace519_1 = { + { nir_search_value_expression, -4 }, + false, + nir_op_imul, + { &replace519_1_0.value, &replace519_1_1.value }, + NULL, +}; + +static const nir_search_variable replace519_2_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace519_2_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace519_2 = { + { nir_search_value_expression, -4 }, + false, + nir_op_imul, + { &replace519_2_0.value, &replace519_2_1.value }, + NULL, +}; +static const nir_search_expression replace519 = { + { nir_search_value_expression, -4 }, + false, + nir_op_bcsel, + { &replace519_0.value, &replace519_1.value, &replace519_2.value }, + NULL, +}; + +static const struct transform nir_opt_algebraic_bcsel_xforms[] = { + { &search145, &replace145.value, 0 }, + { &search146, &replace146.value, 0 }, + { &search147, &replace147.value, 0 }, + { &search148, &replace148.value, 0 }, + { &search149, &replace149.value, 0 }, + { &search150, &replace150.value, 0 }, + { &search151, &replace151.value, 0 }, + { &search152, &replace152.value, 0 }, + { &search153, &replace153.value, 0 }, + { &search154, &replace154.value, 0 }, + { &search155, &replace155.value, 0 }, + { &search156, &replace156.value, 0 }, + { &search348, &replace348.value, 0 }, + { &search349, &replace349.value, 0 }, + { &search350, &replace350.value, 0 }, + { &search351, &replace351.value, 0 }, + { &search352, &replace352.value, 0 }, + { &search353, &replace353.value, 0 }, + { &search354, &replace354.value, 0 }, + { &search355, &replace355.value, 0 }, + { &search356, &replace356.value, 0 }, + { &search357, &replace357.value, 0 }, + { &search358, &replace358.value, 0 }, + { &search360, &replace360.value, 0 }, + { &search361, &replace361.value, 0 }, + { &search423, &replace423.value, 0 }, + { &search424, &replace424.value, 0 }, + { &search425, &replace425.value, 0 }, + { &search426, &replace426.value, 0 }, + { &search427, &replace427.value, 0 }, + { &search428, &replace428.value, 0 }, + { &search429, &replace429.value, 0 }, +}; +static const struct transform nir_opt_algebraic_bfm_xforms[] = { + { &search437, &replace437.value, 29 }, +}; +static const struct transform nir_opt_algebraic_bitfield_insert_xforms[] = { + { &search435, &replace435.value, 27 }, + { &search436, &replace436.value, 28 }, +}; +static const struct transform nir_opt_algebraic_extract_i16_xforms[] = { + { &search446, &replace446.value, 35 }, +}; +static const struct transform nir_opt_algebraic_extract_i8_xforms[] = { + { &search444, &replace444.value, 34 }, +}; +static const struct transform nir_opt_algebraic_extract_u16_xforms[] = { + { &search447, &replace447.value, 35 }, +}; +static const struct transform nir_opt_algebraic_extract_u8_xforms[] = { + { &search193, &replace193.value, 0 }, + { &search445, &replace445.value, 34 }, +}; +static const struct transform nir_opt_algebraic_f2b1_xforms[] = { + { &search17, &replace17.value, 0 }, + { &search476, &replace476.value, 0 }, +}; +static const struct transform nir_opt_algebraic_f2b32_xforms[] = { + { &search17, &replace17.value, 0 }, + { &search478, &replace478.value, 0 }, +}; +static const struct transform nir_opt_algebraic_f2f16_xforms[] = { + { &search480, &replace480.value, 0 }, +}; +static const struct transform nir_opt_algebraic_f2f32_xforms[] = { + { &search480, &replace480.value, 0 }, +}; +static const struct transform nir_opt_algebraic_f2f64_xforms[] = { + { &search480, &replace480.value, 0 }, +}; +static const struct transform nir_opt_algebraic_f2i1_xforms[] = { + { &search370, &replace370.value, 0 }, + { &search482, &replace482.value, 0 }, +}; +static const struct transform nir_opt_algebraic_f2i16_xforms[] = { + { &search370, &replace370.value, 0 }, + { &search482, &replace482.value, 0 }, +}; +static const struct transform nir_opt_algebraic_f2i32_xforms[] = { + { &search370, &replace370.value, 0 }, + { &search377, &replace377.value, 0 }, + { &search378, &replace378.value, 0 }, + { &search482, &replace482.value, 0 }, +}; +static const struct transform nir_opt_algebraic_f2i64_xforms[] = { + { &search370, &replace370.value, 0 }, + { &search482, &replace482.value, 0 }, +}; +static const struct transform nir_opt_algebraic_f2i8_xforms[] = { + { &search370, &replace370.value, 0 }, + { &search482, &replace482.value, 0 }, +}; +static const struct transform nir_opt_algebraic_f2u1_xforms[] = { + { &search371, &replace371.value, 0 }, + { &search481, &replace481.value, 0 }, +}; +static const struct transform nir_opt_algebraic_f2u16_xforms[] = { + { &search371, &replace371.value, 0 }, + { &search481, &replace481.value, 0 }, +}; +static const struct transform nir_opt_algebraic_f2u32_xforms[] = { + { &search371, &replace371.value, 0 }, + { &search379, &replace379.value, 0 }, + { &search380, &replace380.value, 0 }, + { &search481, &replace481.value, 0 }, +}; +static const struct transform nir_opt_algebraic_f2u64_xforms[] = { + { &search371, &replace371.value, 0 }, + { &search481, &replace481.value, 0 }, +}; +static const struct transform nir_opt_algebraic_f2u8_xforms[] = { + { &search371, &replace371.value, 0 }, + { &search481, &replace481.value, 0 }, +}; +static const struct transform nir_opt_algebraic_fabs_xforms[] = { + { &search12, &replace12.value, 0 }, + { &search13, &replace13.value, 0 }, + { &search14, &replace14.value, 0 }, + { &search269, &replace269.value, 0 }, + { &search270, &replace270.value, 0 }, + { &search271, &replace271.value, 0 }, + { &search272, &replace272.value, 0 }, + { &search374, &replace374.value, 0 }, + { &search410, &replace410.value, 0 }, +}; +static const struct transform nir_opt_algebraic_fadd_xforms[] = { + { &search19, &replace19.value, 0 }, + { &search23, &replace23.value, 0 }, + { &search25, &replace25.value, 0 }, + { &search29, &replace29.value, 0 }, + { &search30, &replace30.value, 0 }, + { &search57, &replace57.value, 2 }, + { &search58, &replace58.value, 7 }, + { &search59, &replace59.value, 8 }, + { &search60, &replace60.value, 2 }, + { &search61, &replace61.value, 7 }, + { &search62, &replace62.value, 8 }, + { &search64, &replace64.value, 10 }, + { &search408, &replace408.value, 0 }, + { &search416, &replace416.value, 0 }, + { &search420, &replace420.value, 0 }, + { &search421, &replace421.value, 0 }, + { &search516, &replace516.value, 0 }, +}; +static const struct transform nir_opt_algebraic_fand_xforms[] = { + { &search292, &replace292.value, 0 }, +}; +static const struct transform nir_opt_algebraic_fceil_xforms[] = { + { &search56, &replace56.value, 6 }, +}; +static const struct transform nir_opt_algebraic_fcsel_xforms[] = { + { &search359, &replace359.value, 0 }, +}; +static const struct transform nir_opt_algebraic_fdiv_xforms[] = { + { &search338, &replace338.value, 0 }, + { &search339, &replace339.value, 16 }, +}; +static const struct transform nir_opt_algebraic_fdot3_xforms[] = { + { &search69, &replace69.value, 0 }, + { &search70, &replace70.value, 0 }, +}; +static const struct transform nir_opt_algebraic_fdot4_xforms[] = { + { &search65, &replace65.value, 0 }, + { &search66, &replace66.value, 0 }, + { &search67, &replace67.value, 0 }, + { &search68, &replace68.value, 0 }, +}; +static const struct transform nir_opt_algebraic_feq_xforms[] = { + { &search95, &replace95.value, 0 }, + { &search96, &replace96.value, 0 }, + { &search97, &replace97.value, 0 }, + { &search98, &replace98.value, 0 }, + { &search99, &replace99.value, 0 }, + { &search100, &replace100.value, 0 }, + { &search101, &replace101.value, 0 }, + { &search102, &replace102.value, 0 }, + { &search103, &replace103.value, 0 }, + { &search104, &replace104.value, 0 }, + { &search112, &replace112.value, 0 }, + { &search117, &replace117.value, 0 }, + { &search118, &replace118.value, 0 }, + { &search123, &replace123.value, 0 }, + { &search129, &replace129.value, 0 }, + { &search278, &replace278.value, 0 }, + { &search500, &replace500.value, 0 }, + { &search501, &replace501.value, 0 }, +}; +static const struct transform nir_opt_algebraic_fexp2_xforms[] = { + { &search317, &replace317.value, 0 }, + { &search320, &replace320.value, 15 }, + { &search321, &replace321.value, 15 }, + { &search322, &replace322.value, 0 }, + { &search323, &replace323.value, 0 }, +}; +static const struct transform nir_opt_algebraic_ffloor_xforms[] = { + { &search54, &replace54.value, 4 }, +}; +static const struct transform nir_opt_algebraic_ffma_xforms[] = { + { &search41, &replace41.value, 0 }, + { &search42, &replace42.value, 0 }, + { &search43, &replace43.value, 0 }, + { &search44, &replace44.value, 0 }, + { &search45, &replace45.value, 0 }, + { &search63, &replace63.value, 9 }, +}; +static const struct transform nir_opt_algebraic_ffract_xforms[] = { + { &search55, &replace55.value, 5 }, +}; +static const struct transform nir_opt_algebraic_fge_xforms[] = { + { &search83, &replace83.value, 0 }, + { &search84, &replace84.value, 0 }, + { &search107, &replace107.value, 0 }, + { &search108, &replace108.value, 0 }, + { &search111, &replace111.value, 0 }, + { &search116, &replace116.value, 0 }, + { &search124, &replace124.value, 0 }, + { &search125, &replace125.value, 0 }, + { &search130, &replace130.value, 0 }, + { &search131, &replace131.value, 0 }, + { &search136, &replace136.value, 0 }, + { &search137, &replace137.value, 0 }, + { &search144, &replace144.value, 0 }, + { &search231, &replace231.value, 0 }, + { &search232, &replace232.value, 0 }, + { &search235, &replace235.value, 0 }, + { &search236, &replace236.value, 0 }, + { &search498, &replace498.value, 0 }, + { &search499, &replace499.value, 0 }, +}; +static const struct transform nir_opt_algebraic_find_lsb_xforms[] = { + { &search443, &replace443.value, 33 }, +}; +static const struct transform nir_opt_algebraic_flog2_xforms[] = { + { &search318, &replace318.value, 0 }, + { &search333, &replace333.value, 0 }, + { &search334, &replace334.value, 0 }, + { &search335, &replace335.value, 0 }, + { &search336, &replace336.value, 0 }, +}; +static const struct transform nir_opt_algebraic_flrp_xforms[] = { + { &search46, &replace46.value, 0 }, + { &search47, &replace47.value, 0 }, + { &search48, &replace48.value, 0 }, + { &search49, &replace49.value, 0 }, + { &search50, &replace50.value, 2 }, + { &search51, &replace51.value, 0 }, + { &search52, &replace52.value, 2 }, + { &search53, &replace53.value, 3 }, +}; +static const struct transform nir_opt_algebraic_flt_xforms[] = { + { &search105, &replace105.value, 0 }, + { &search106, &replace106.value, 0 }, + { &search109, &replace109.value, 0 }, + { &search110, &replace110.value, 0 }, + { &search126, &replace126.value, 0 }, + { &search127, &replace127.value, 0 }, + { &search132, &replace132.value, 0 }, + { &search133, &replace133.value, 0 }, + { &search134, &replace134.value, 0 }, + { &search135, &replace135.value, 0 }, + { &search143, &replace143.value, 0 }, + { &search229, &replace229.value, 0 }, + { &search230, &replace230.value, 0 }, + { &search233, &replace233.value, 0 }, + { &search234, &replace234.value, 0 }, + { &search284, &replace284.value, 0 }, + { &search285, &replace285.value, 0 }, + { &search496, &replace496.value, 0 }, + { &search497, &replace497.value, 0 }, +}; +static const struct transform nir_opt_algebraic_fmax_xforms[] = { + { &search138, &replace138.value, 0 }, + { &search139, &replace139.value, 0 }, + { &search158, &replace158.value, 0 }, + { &search163, &replace163.value, 0 }, + { &search169, &replace169.value, 0 }, + { &search177, &replace177.value, 0 }, + { &search179, &replace179.value, 0 }, + { &search181, &replace181.value, 0 }, + { &search184, &replace184.value, 11 }, + { &search191, &replace191.value, 0 }, +}; +static const struct transform nir_opt_algebraic_fmin_xforms[] = { + { &search140, &replace140.value, 0 }, + { &search141, &replace141.value, 0 }, + { &search142, &replace142.value, 0 }, + { &search157, &replace157.value, 0 }, + { &search166, &replace166.value, 0 }, + { &search171, &replace171.value, 0 }, + { &search173, &replace173.value, 0 }, + { &search175, &replace175.value, 0 }, + { &search183, &replace183.value, 11 }, + { &search188, &replace188.value, 0 }, + { &search192, &replace192.value, 0 }, +}; +static const struct transform nir_opt_algebraic_fmod_xforms[] = { + { &search430, &replace430.value, 23 }, + { &search431, &replace431.value, 24 }, +}; +static const struct transform nir_opt_algebraic_fmul_xforms[] = { + { &search31, &replace31.value, 0 }, + { &search35, &replace35.value, 0 }, + { &search37, &replace37.value, 0 }, + { &search39, &replace39.value, 0 }, + { &search40, &replace40.value, 0 }, + { &search280, &replace280.value, 0 }, + { &search337, &replace337.value, 0 }, + { &search412, &replace412.value, 0 }, + { &search414, &replace414.value, 0 }, + { &search418, &replace418.value, 0 }, + { &search517, &replace517.value, 0 }, +}; +static const struct transform nir_opt_algebraic_fne_xforms[] = { + { &search85, &replace85.value, 0 }, + { &search86, &replace86.value, 0 }, + { &search87, &replace87.value, 0 }, + { &search88, &replace88.value, 0 }, + { &search89, &replace89.value, 0 }, + { &search90, &replace90.value, 0 }, + { &search91, &replace91.value, 0 }, + { &search92, &replace92.value, 0 }, + { &search93, &replace93.value, 0 }, + { &search94, &replace94.value, 0 }, + { &search113, &replace113.value, 0 }, + { &search119, &replace119.value, 0 }, + { &search122, &replace122.value, 0 }, + { &search128, &replace128.value, 0 }, + { &search277, &replace277.value, 0 }, + { &search502, &replace502.value, 0 }, + { &search503, &replace503.value, 0 }, +}; +static const struct transform nir_opt_algebraic_fneg_xforms[] = { + { &search10, &replace10.value, 0 }, + { &search406, &replace406.value, 22 }, +}; +static const struct transform nir_opt_algebraic_fpow_xforms[] = { + { &search319, &replace319.value, 14 }, + { &search324, &replace324.value, 0 }, + { &search325, &replace325.value, 0 }, + { &search326, &replace326.value, 0 }, + { &search327, &replace327.value, 0 }, + { &search328, &replace328.value, 0 }, + { &search329, &replace329.value, 0 }, +}; +static const struct transform nir_opt_algebraic_frcp_xforms[] = { + { &search331, &replace331.value, 0 }, + { &search340, &replace340.value, 0 }, + { &search341, &replace341.value, 0 }, + { &search343, &replace343.value, 18 }, +}; +static const struct transform nir_opt_algebraic_frem_xforms[] = { + { &search432, &replace432.value, 23 }, +}; +static const struct transform nir_opt_algebraic_frsq_xforms[] = { + { &search332, &replace332.value, 0 }, +}; +static const struct transform nir_opt_algebraic_fsat_xforms[] = { + { &search185, &replace185.value, 0 }, + { &search186, &replace186.value, 12 }, + { &search187, &replace187.value, 0 }, + { &search281, &replace281.value, 0 }, +}; +static const struct transform nir_opt_algebraic_fsqrt_xforms[] = { + { &search330, &replace330.value, 0 }, + { &search342, &replace342.value, 17 }, +}; +static const struct transform nir_opt_algebraic_fsub_xforms[] = { + { &search400, &replace400.value, 0 }, + { &search404, &replace404.value, 21 }, +}; +static const struct transform nir_opt_algebraic_fxor_xforms[] = { + { &search299, &replace299.value, 0 }, +}; +static const struct transform nir_opt_algebraic_i2b1_xforms[] = { + { &search18, &replace18.value, 0 }, + { &search372, &replace372.value, 0 }, + { &search373, &replace373.value, 0 }, + { &search477, &replace477.value, 0 }, +}; +static const struct transform nir_opt_algebraic_i2b32_xforms[] = { + { &search18, &replace18.value, 0 }, + { &search369, &replace369.value, 0 }, + { &search372, &replace372.value, 0 }, + { &search373, &replace373.value, 0 }, + { &search479, &replace479.value, 0 }, +}; +static const struct transform nir_opt_algebraic_i2f16_xforms[] = { + { &search485, &replace485.value, 0 }, +}; +static const struct transform nir_opt_algebraic_i2f32_xforms[] = { + { &search485, &replace485.value, 0 }, +}; +static const struct transform nir_opt_algebraic_i2f64_xforms[] = { + { &search485, &replace485.value, 0 }, +}; +static const struct transform nir_opt_algebraic_i2i1_xforms[] = { + { &search486, &replace486.value, 0 }, +}; +static const struct transform nir_opt_algebraic_i2i16_xforms[] = { + { &search486, &replace486.value, 0 }, +}; +static const struct transform nir_opt_algebraic_i2i32_xforms[] = { + { &search486, &replace486.value, 0 }, +}; +static const struct transform nir_opt_algebraic_i2i64_xforms[] = { + { &search486, &replace486.value, 0 }, +}; +static const struct transform nir_opt_algebraic_i2i8_xforms[] = { + { &search486, &replace486.value, 0 }, +}; +static const struct transform nir_opt_algebraic_iabs_xforms[] = { + { &search15, &replace15.value, 0 }, + { &search16, &replace16.value, 0 }, + { &search375, &replace375.value, 0 }, + { &search411, &replace411.value, 0 }, +}; +static const struct transform nir_opt_algebraic_iadd_xforms[] = { + { &search20, &replace20.value, 0 }, + { &search24, &replace24.value, 0 }, + { &search26, &replace26.value, 0 }, + { &search27, &replace27.value, 0 }, + { &search28, &replace28.value, 0 }, + { &search409, &replace409.value, 0 }, + { &search417, &replace417.value, 0 }, + { &search422, &replace422.value, 0 }, + { &search518, &replace518.value, 0 }, +}; +static const struct transform nir_opt_algebraic_iand_xforms[] = { + { &search202, &replace202.value, 0 }, + { &search203, &replace203.value, 0 }, + { &search204, &replace204.value, 0 }, + { &search205, &replace205.value, 0 }, + { &search206, &replace206.value, 0 }, + { &search207, &replace207.value, 0 }, + { &search208, &replace208.value, 0 }, + { &search209, &replace209.value, 0 }, + { &search218, &replace218.value, 0 }, + { &search219, &replace219.value, 0 }, + { &search220, &replace220.value, 0 }, + { &search221, &replace221.value, 0 }, + { &search222, &replace222.value, 0 }, + { &search223, &replace223.value, 0 }, + { &search224, &replace224.value, 0 }, + { &search225, &replace225.value, 0 }, + { &search228, &replace228.value, 0 }, + { &search282, &replace282.value, 0 }, + { &search293, &replace293.value, 0 }, + { &search294, &replace294.value, 0 }, + { &search295, &replace295.value, 0 }, + { &search305, &replace305.value, 0 }, + { &search306, &replace306.value, 0 }, + { &search307, &replace307.value, 0 }, + { &search315, &replace315.value, 0 }, + { &search316, &replace316.value, 0 }, + { &search362, &replace362.value, 0 }, + { &search368, &replace368.value, 0 }, + { &search392, &replace392.value, 19 }, + { &search393, &replace393.value, 19 }, + { &search394, &replace394.value, 19 }, + { &search399, &replace399.value, 20 }, + { &search490, &replace490.value, 0 }, + { &search491, &replace491.value, 0 }, + { &search492, &replace492.value, 0 }, + { &search493, &replace493.value, 0 }, + { &search494, &replace494.value, 0 }, + { &search495, &replace495.value, 0 }, +}; +static const struct transform nir_opt_algebraic_ibitfield_extract_xforms[] = { + { &search438, &replace438.value, 30 }, + { &search440, &replace440.value, 31 }, +}; +static const struct transform nir_opt_algebraic_idiv_xforms[] = { + { &search3, &replace3.value, 0 }, + { &search7, &replace7.value, 1 }, + { &search8, &replace8.value, 1 }, +}; +static const struct transform nir_opt_algebraic_ieq_xforms[] = { + { &search114, &replace114.value, 0 }, + { &search120, &replace120.value, 0 }, + { &search288, &replace288.value, 0 }, + { &search344, &replace344.value, 0 }, + { &search347, &replace347.value, 0 }, + { &search364, &replace364.value, 0 }, + { &search365, &replace365.value, 0 }, + { &search508, &replace508.value, 0 }, + { &search509, &replace509.value, 0 }, +}; +static const struct transform nir_opt_algebraic_ifind_msb_xforms[] = { + { &search442, &replace442.value, 32 }, +}; +static const struct transform nir_opt_algebraic_ige_xforms[] = { + { &search239, &replace239.value, 0 }, + { &search240, &replace240.value, 0 }, + { &search247, &replace247.value, 0 }, + { &search248, &replace248.value, 0 }, + { &search255, &replace255.value, 0 }, + { &search256, &replace256.value, 0 }, + { &search263, &replace263.value, 0 }, + { &search264, &replace264.value, 0 }, + { &search287, &replace287.value, 0 }, + { &search506, &replace506.value, 0 }, + { &search507, &replace507.value, 0 }, +}; +static const struct transform nir_opt_algebraic_ilt_xforms[] = { + { &search237, &replace237.value, 0 }, + { &search238, &replace238.value, 0 }, + { &search245, &replace245.value, 0 }, + { &search246, &replace246.value, 0 }, + { &search253, &replace253.value, 0 }, + { &search254, &replace254.value, 0 }, + { &search261, &replace261.value, 0 }, + { &search262, &replace262.value, 0 }, + { &search286, &replace286.value, 0 }, + { &search504, &replace504.value, 0 }, + { &search505, &replace505.value, 0 }, +}; +static const struct transform nir_opt_algebraic_imax_xforms[] = { + { &search160, &replace160.value, 0 }, + { &search165, &replace165.value, 0 }, + { &search170, &replace170.value, 0 }, + { &search178, &replace178.value, 0 }, + { &search180, &replace180.value, 0 }, + { &search182, &replace182.value, 0 }, +}; +static const struct transform nir_opt_algebraic_imin_xforms[] = { + { &search159, &replace159.value, 0 }, + { &search168, &replace168.value, 0 }, + { &search172, &replace172.value, 0 }, + { &search174, &replace174.value, 0 }, + { &search176, &replace176.value, 0 }, + { &search189, &replace189.value, 0 }, +}; +static const struct transform nir_opt_algebraic_imod_xforms[] = { + { &search5, &replace5.value, 0 }, +}; +static const struct transform nir_opt_algebraic_imul_xforms[] = { + { &search0, &replace0.value, 0 }, + { &search1, &replace1.value, 0 }, + { &search32, &replace32.value, 0 }, + { &search36, &replace36.value, 0 }, + { &search38, &replace38.value, 0 }, + { &search279, &replace279.value, 0 }, + { &search413, &replace413.value, 0 }, + { &search415, &replace415.value, 0 }, + { &search419, &replace419.value, 0 }, + { &search519, &replace519.value, 0 }, +}; +static const struct transform nir_opt_algebraic_ine_xforms[] = { + { &search115, &replace115.value, 0 }, + { &search121, &replace121.value, 0 }, + { &search289, &replace289.value, 0 }, + { &search345, &replace345.value, 0 }, + { &search346, &replace346.value, 0 }, + { &search366, &replace366.value, 0 }, + { &search367, &replace367.value, 0 }, + { &search510, &replace510.value, 0 }, + { &search511, &replace511.value, 0 }, +}; +static const struct transform nir_opt_algebraic_ineg_xforms[] = { + { &search11, &replace11.value, 0 }, + { &search283, &replace283.value, 0 }, + { &search407, &replace407.value, 22 }, +}; +static const struct transform nir_opt_algebraic_inot_xforms[] = { + { &search73, &replace73.value, 0 }, + { &search74, &replace74.value, 0 }, + { &search75, &replace75.value, 0 }, + { &search76, &replace76.value, 0 }, + { &search77, &replace77.value, 0 }, + { &search78, &replace78.value, 0 }, + { &search79, &replace79.value, 0 }, + { &search80, &replace80.value, 0 }, + { &search81, &replace81.value, 0 }, + { &search82, &replace82.value, 0 }, + { &search302, &replace302.value, 0 }, + { &search376, &replace376.value, 0 }, + { &search456, &replace456.value, 0 }, + { &search457, &replace457.value, 0 }, + { &search458, &replace458.value, 0 }, + { &search459, &replace459.value, 0 }, + { &search460, &replace460.value, 0 }, + { &search461, &replace461.value, 0 }, + { &search462, &replace462.value, 0 }, + { &search463, &replace463.value, 0 }, + { &search464, &replace464.value, 0 }, + { &search465, &replace465.value, 0 }, + { &search466, &replace466.value, 0 }, + { &search467, &replace467.value, 0 }, + { &search468, &replace468.value, 0 }, + { &search469, &replace469.value, 0 }, + { &search470, &replace470.value, 0 }, + { &search471, &replace471.value, 0 }, + { &search472, &replace472.value, 0 }, + { &search473, &replace473.value, 0 }, + { &search474, &replace474.value, 0 }, + { &search475, &replace475.value, 0 }, +}; +static const struct transform nir_opt_algebraic_ior_xforms[] = { + { &search194, &replace194.value, 0 }, + { &search195, &replace195.value, 0 }, + { &search196, &replace196.value, 0 }, + { &search197, &replace197.value, 0 }, + { &search198, &replace198.value, 0 }, + { &search199, &replace199.value, 0 }, + { &search200, &replace200.value, 0 }, + { &search201, &replace201.value, 0 }, + { &search210, &replace210.value, 0 }, + { &search211, &replace211.value, 0 }, + { &search212, &replace212.value, 0 }, + { &search213, &replace213.value, 0 }, + { &search214, &replace214.value, 0 }, + { &search215, &replace215.value, 0 }, + { &search216, &replace216.value, 0 }, + { &search217, &replace217.value, 0 }, + { &search226, &replace226.value, 0 }, + { &search227, &replace227.value, 0 }, + { &search296, &replace296.value, 0 }, + { &search297, &replace297.value, 0 }, + { &search298, &replace298.value, 0 }, + { &search303, &replace303.value, 0 }, + { &search304, &replace304.value, 0 }, + { &search308, &replace308.value, 0 }, + { &search363, &replace363.value, 0 }, + { &search489, &replace489.value, 0 }, +}; +static const struct transform nir_opt_algebraic_ishl_xforms[] = { + { &search71, &replace71.value, 0 }, + { &search72, &replace72.value, 0 }, + { &search309, &replace309.value, 0 }, + { &search310, &replace310.value, 0 }, +}; +static const struct transform nir_opt_algebraic_ishr_xforms[] = { + { &search311, &replace311.value, 0 }, + { &search312, &replace312.value, 0 }, + { &search388, &replace388.value, 19 }, + { &search389, &replace389.value, 19 }, + { &search390, &replace390.value, 19 }, + { &search391, &replace391.value, 19 }, + { &search397, &replace397.value, 20 }, + { &search398, &replace398.value, 20 }, +}; +static const struct transform nir_opt_algebraic_isub_xforms[] = { + { &search401, &replace401.value, 0 }, + { &search405, &replace405.value, 21 }, +}; +static const struct transform nir_opt_algebraic_ixor_xforms[] = { + { &search300, &replace300.value, 0 }, + { &search301, &replace301.value, 0 }, +}; +static const struct transform nir_opt_algebraic_ldexp_xforms[] = { + { &search487, &replace487.value, 44 }, + { &search488, &replace488.value, 44 }, +}; +static const struct transform nir_opt_algebraic_pack_64_2x32_split_xforms[] = { + { &search383, &replace383.value, 0 }, +}; +static const struct transform nir_opt_algebraic_pack_snorm_2x16_xforms[] = { + { &search450, &replace450.value, 38 }, +}; +static const struct transform nir_opt_algebraic_pack_snorm_4x8_xforms[] = { + { &search451, &replace451.value, 39 }, +}; +static const struct transform nir_opt_algebraic_pack_unorm_2x16_xforms[] = { + { &search448, &replace448.value, 36 }, +}; +static const struct transform nir_opt_algebraic_pack_unorm_4x8_xforms[] = { + { &search449, &replace449.value, 37 }, +}; +static const struct transform nir_opt_algebraic_seq_xforms[] = { + { &search275, &replace275.value, 13 }, +}; +static const struct transform nir_opt_algebraic_sge_xforms[] = { + { &search274, &replace274.value, 13 }, +}; +static const struct transform nir_opt_algebraic_slt_xforms[] = { + { &search273, &replace273.value, 13 }, +}; +static const struct transform nir_opt_algebraic_sne_xforms[] = { + { &search276, &replace276.value, 13 }, +}; +static const struct transform nir_opt_algebraic_u2f16_xforms[] = { + { &search483, &replace483.value, 0 }, +}; +static const struct transform nir_opt_algebraic_u2f32_xforms[] = { + { &search483, &replace483.value, 0 }, +}; +static const struct transform nir_opt_algebraic_u2f64_xforms[] = { + { &search483, &replace483.value, 0 }, +}; +static const struct transform nir_opt_algebraic_u2u1_xforms[] = { + { &search484, &replace484.value, 0 }, +}; +static const struct transform nir_opt_algebraic_u2u16_xforms[] = { + { &search484, &replace484.value, 0 }, +}; +static const struct transform nir_opt_algebraic_u2u32_xforms[] = { + { &search484, &replace484.value, 0 }, +}; +static const struct transform nir_opt_algebraic_u2u64_xforms[] = { + { &search484, &replace484.value, 0 }, +}; +static const struct transform nir_opt_algebraic_u2u8_xforms[] = { + { &search484, &replace484.value, 0 }, +}; +static const struct transform nir_opt_algebraic_uadd_carry_xforms[] = { + { &search433, &replace433.value, 25 }, +}; +static const struct transform nir_opt_algebraic_ubitfield_extract_xforms[] = { + { &search439, &replace439.value, 30 }, + { &search441, &replace441.value, 31 }, +}; +static const struct transform nir_opt_algebraic_udiv_xforms[] = { + { &search2, &replace2.value, 0 }, + { &search6, &replace6.value, 0 }, +}; +static const struct transform nir_opt_algebraic_uge_xforms[] = { + { &search243, &replace243.value, 0 }, + { &search244, &replace244.value, 0 }, + { &search251, &replace251.value, 0 }, + { &search252, &replace252.value, 0 }, + { &search259, &replace259.value, 0 }, + { &search260, &replace260.value, 0 }, + { &search267, &replace267.value, 0 }, + { &search268, &replace268.value, 0 }, + { &search291, &replace291.value, 0 }, + { &search514, &replace514.value, 0 }, + { &search515, &replace515.value, 0 }, +}; +static const struct transform nir_opt_algebraic_ult_xforms[] = { + { &search241, &replace241.value, 0 }, + { &search242, &replace242.value, 0 }, + { &search249, &replace249.value, 0 }, + { &search250, &replace250.value, 0 }, + { &search257, &replace257.value, 0 }, + { &search258, &replace258.value, 0 }, + { &search265, &replace265.value, 0 }, + { &search266, &replace266.value, 0 }, + { &search290, &replace290.value, 0 }, + { &search512, &replace512.value, 0 }, + { &search513, &replace513.value, 0 }, +}; +static const struct transform nir_opt_algebraic_umax_xforms[] = { + { &search162, &replace162.value, 0 }, + { &search164, &replace164.value, 0 }, +}; +static const struct transform nir_opt_algebraic_umin_xforms[] = { + { &search161, &replace161.value, 0 }, + { &search167, &replace167.value, 0 }, + { &search190, &replace190.value, 0 }, +}; +static const struct transform nir_opt_algebraic_umod_xforms[] = { + { &search4, &replace4.value, 0 }, + { &search9, &replace9.value, 0 }, +}; +static const struct transform nir_opt_algebraic_umul_unorm_4x8_xforms[] = { + { &search33, &replace33.value, 0 }, + { &search34, &replace34.value, 0 }, +}; +static const struct transform nir_opt_algebraic_unpack_64_2x32_split_x_xforms[] = { + { &search381, &replace381.value, 0 }, +}; +static const struct transform nir_opt_algebraic_unpack_64_2x32_split_y_xforms[] = { + { &search382, &replace382.value, 0 }, +}; +static const struct transform nir_opt_algebraic_unpack_snorm_2x16_xforms[] = { + { &search454, &replace454.value, 42 }, +}; +static const struct transform nir_opt_algebraic_unpack_snorm_4x8_xforms[] = { + { &search455, &replace455.value, 43 }, +}; +static const struct transform nir_opt_algebraic_unpack_unorm_2x16_xforms[] = { + { &search452, &replace452.value, 40 }, +}; +static const struct transform nir_opt_algebraic_unpack_unorm_4x8_xforms[] = { + { &search453, &replace453.value, 41 }, +}; +static const struct transform nir_opt_algebraic_usadd_4x8_xforms[] = { + { &search21, &replace21.value, 0 }, + { &search22, &replace22.value, 0 }, +}; +static const struct transform nir_opt_algebraic_ushr_xforms[] = { + { &search313, &replace313.value, 0 }, + { &search314, &replace314.value, 0 }, + { &search384, &replace384.value, 19 }, + { &search385, &replace385.value, 19 }, + { &search386, &replace386.value, 19 }, + { &search387, &replace387.value, 19 }, + { &search395, &replace395.value, 20 }, + { &search396, &replace396.value, 20 }, +}; +static const struct transform nir_opt_algebraic_ussub_4x8_xforms[] = { + { &search402, &replace402.value, 0 }, + { &search403, &replace403.value, 0 }, +}; +static const struct transform nir_opt_algebraic_usub_borrow_xforms[] = { + { &search434, &replace434.value, 26 }, +}; + +static bool +nir_opt_algebraic_block(nir_builder *build, nir_block *block, + const bool *condition_flags) +{ + bool progress = false; + + nir_foreach_instr_reverse_safe(instr, block) { + if (instr->type != nir_instr_type_alu) + continue; + + nir_alu_instr *alu = nir_instr_as_alu(instr); + if (!alu->dest.dest.is_ssa) + continue; + + switch (alu->op) { + case nir_op_bcsel: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_bcsel_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_bcsel_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_bfm: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_bfm_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_bfm_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_bitfield_insert: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_bitfield_insert_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_bitfield_insert_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_extract_i16: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_extract_i16_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_extract_i16_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_extract_i8: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_extract_i8_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_extract_i8_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_extract_u16: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_extract_u16_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_extract_u16_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_extract_u8: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_extract_u8_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_extract_u8_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_f2b1: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_f2b1_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_f2b1_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_f2b32: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_f2b32_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_f2b32_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_f2f16: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_f2f16_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_f2f16_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_f2f32: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_f2f32_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_f2f32_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_f2f64: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_f2f64_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_f2f64_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_f2i1: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_f2i1_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_f2i1_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_f2i16: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_f2i16_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_f2i16_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_f2i32: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_f2i32_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_f2i32_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_f2i64: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_f2i64_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_f2i64_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_f2i8: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_f2i8_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_f2i8_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_f2u1: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_f2u1_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_f2u1_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_f2u16: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_f2u16_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_f2u16_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_f2u32: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_f2u32_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_f2u32_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_f2u64: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_f2u64_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_f2u64_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_f2u8: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_f2u8_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_f2u8_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_fabs: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_fabs_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_fabs_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_fadd: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_fadd_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_fadd_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_fand: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_fand_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_fand_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_fceil: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_fceil_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_fceil_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_fcsel: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_fcsel_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_fcsel_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_fdiv: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_fdiv_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_fdiv_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_fdot3: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_fdot3_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_fdot3_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_fdot4: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_fdot4_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_fdot4_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_feq: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_feq_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_feq_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_fexp2: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_fexp2_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_fexp2_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_ffloor: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_ffloor_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_ffloor_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_ffma: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_ffma_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_ffma_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_ffract: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_ffract_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_ffract_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_fge: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_fge_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_fge_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_find_lsb: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_find_lsb_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_find_lsb_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_flog2: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_flog2_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_flog2_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_flrp: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_flrp_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_flrp_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_flt: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_flt_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_flt_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_fmax: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_fmax_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_fmax_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_fmin: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_fmin_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_fmin_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_fmod: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_fmod_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_fmod_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_fmul: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_fmul_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_fmul_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_fne: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_fne_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_fne_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_fneg: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_fneg_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_fneg_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_fpow: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_fpow_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_fpow_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_frcp: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_frcp_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_frcp_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_frem: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_frem_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_frem_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_frsq: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_frsq_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_frsq_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_fsat: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_fsat_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_fsat_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_fsqrt: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_fsqrt_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_fsqrt_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_fsub: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_fsub_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_fsub_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_fxor: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_fxor_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_fxor_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_i2b1: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_i2b1_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_i2b1_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_i2b32: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_i2b32_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_i2b32_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_i2f16: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_i2f16_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_i2f16_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_i2f32: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_i2f32_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_i2f32_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_i2f64: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_i2f64_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_i2f64_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_i2i1: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_i2i1_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_i2i1_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_i2i16: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_i2i16_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_i2i16_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_i2i32: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_i2i32_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_i2i32_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_i2i64: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_i2i64_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_i2i64_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_i2i8: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_i2i8_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_i2i8_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_iabs: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_iabs_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_iabs_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_iadd: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_iadd_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_iadd_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_iand: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_iand_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_iand_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_ibitfield_extract: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_ibitfield_extract_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_ibitfield_extract_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_idiv: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_idiv_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_idiv_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_ieq: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_ieq_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_ieq_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_ifind_msb: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_ifind_msb_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_ifind_msb_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_ige: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_ige_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_ige_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_ilt: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_ilt_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_ilt_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_imax: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_imax_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_imax_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_imin: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_imin_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_imin_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_imod: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_imod_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_imod_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_imul: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_imul_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_imul_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_ine: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_ine_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_ine_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_ineg: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_ineg_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_ineg_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_inot: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_inot_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_inot_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_ior: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_ior_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_ior_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_ishl: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_ishl_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_ishl_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_ishr: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_ishr_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_ishr_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_isub: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_isub_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_isub_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_ixor: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_ixor_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_ixor_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_ldexp: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_ldexp_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_ldexp_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_pack_64_2x32_split: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_pack_64_2x32_split_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_pack_64_2x32_split_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_pack_snorm_2x16: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_pack_snorm_2x16_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_pack_snorm_2x16_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_pack_snorm_4x8: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_pack_snorm_4x8_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_pack_snorm_4x8_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_pack_unorm_2x16: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_pack_unorm_2x16_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_pack_unorm_2x16_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_pack_unorm_4x8: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_pack_unorm_4x8_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_pack_unorm_4x8_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_seq: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_seq_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_seq_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_sge: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_sge_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_sge_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_slt: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_slt_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_slt_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_sne: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_sne_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_sne_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_u2f16: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_u2f16_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_u2f16_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_u2f32: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_u2f32_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_u2f32_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_u2f64: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_u2f64_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_u2f64_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_u2u1: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_u2u1_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_u2u1_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_u2u16: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_u2u16_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_u2u16_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_u2u32: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_u2u32_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_u2u32_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_u2u64: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_u2u64_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_u2u64_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_u2u8: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_u2u8_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_u2u8_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_uadd_carry: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_uadd_carry_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_uadd_carry_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_ubitfield_extract: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_ubitfield_extract_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_ubitfield_extract_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_udiv: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_udiv_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_udiv_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_uge: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_uge_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_uge_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_ult: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_ult_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_ult_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_umax: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_umax_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_umax_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_umin: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_umin_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_umin_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_umod: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_umod_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_umod_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_umul_unorm_4x8: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_umul_unorm_4x8_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_umul_unorm_4x8_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_unpack_64_2x32_split_x: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_unpack_64_2x32_split_x_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_unpack_64_2x32_split_x_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_unpack_64_2x32_split_y: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_unpack_64_2x32_split_y_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_unpack_64_2x32_split_y_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_unpack_snorm_2x16: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_unpack_snorm_2x16_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_unpack_snorm_2x16_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_unpack_snorm_4x8: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_unpack_snorm_4x8_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_unpack_snorm_4x8_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_unpack_unorm_2x16: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_unpack_unorm_2x16_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_unpack_unorm_2x16_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_unpack_unorm_4x8: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_unpack_unorm_4x8_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_unpack_unorm_4x8_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_usadd_4x8: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_usadd_4x8_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_usadd_4x8_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_ushr: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_ushr_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_ushr_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_ussub_4x8: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_ussub_4x8_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_ussub_4x8_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_usub_borrow: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_usub_borrow_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_usub_borrow_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + default: + break; + } + } + + return progress; +} + +static bool +nir_opt_algebraic_impl(nir_function_impl *impl, const bool *condition_flags) +{ + bool progress = false; + + nir_builder build; + nir_builder_init(&build, impl); + + nir_foreach_block_reverse(block, impl) { + progress |= nir_opt_algebraic_block(&build, block, condition_flags); + } + + if (progress) { + nir_metadata_preserve(impl, nir_metadata_block_index | + nir_metadata_dominance); + } else { +#ifndef NDEBUG + impl->valid_metadata &= ~nir_metadata_not_properly_reset; +#endif + } + + return progress; +} + + +bool +nir_opt_algebraic(nir_shader *shader) +{ + bool progress = false; + bool condition_flags[45]; + const nir_shader_compiler_options *options = shader->options; + (void) options; + + condition_flags[0] = true; + condition_flags[1] = options->lower_idiv; + condition_flags[2] = options->lower_flrp32; + condition_flags[3] = options->lower_flrp64; + condition_flags[4] = options->lower_ffloor; + condition_flags[5] = options->lower_ffract; + condition_flags[6] = options->lower_fceil; + condition_flags[7] = !options->lower_flrp32; + condition_flags[8] = !options->lower_flrp64; + condition_flags[9] = options->lower_ffma; + condition_flags[10] = options->fuse_ffma; + condition_flags[11] = !options->lower_fsat; + condition_flags[12] = options->lower_fsat; + condition_flags[13] = options->lower_scmp; + condition_flags[14] = options->lower_fpow; + condition_flags[15] = !options->lower_fpow; + condition_flags[16] = options->lower_fdiv; + condition_flags[17] = options->lower_fsqrt; + condition_flags[18] = !options->lower_fsqrt; + condition_flags[19] = !options->lower_extract_byte; + condition_flags[20] = !options->lower_extract_word; + condition_flags[21] = options->lower_sub; + condition_flags[22] = options->lower_negate; + condition_flags[23] = options->lower_fmod32; + condition_flags[24] = options->lower_fmod64; + condition_flags[25] = options->lower_uadd_carry; + condition_flags[26] = options->lower_usub_borrow; + condition_flags[27] = options->lower_bitfield_insert; + condition_flags[28] = options->lower_bitfield_insert_to_shifts; + condition_flags[29] = options->lower_bfm; + condition_flags[30] = options->lower_bitfield_extract; + condition_flags[31] = options->lower_bitfield_extract_to_shifts; + condition_flags[32] = options->lower_ifind_msb; + condition_flags[33] = options->lower_find_lsb; + condition_flags[34] = options->lower_extract_byte; + condition_flags[35] = options->lower_extract_word; + condition_flags[36] = options->lower_pack_unorm_2x16; + condition_flags[37] = options->lower_pack_unorm_4x8; + condition_flags[38] = options->lower_pack_snorm_2x16; + condition_flags[39] = options->lower_pack_snorm_4x8; + condition_flags[40] = options->lower_unpack_unorm_2x16; + condition_flags[41] = options->lower_unpack_unorm_4x8; + condition_flags[42] = options->lower_unpack_snorm_2x16; + condition_flags[43] = options->lower_unpack_snorm_4x8; + condition_flags[44] = options->lower_ldexp; + + nir_foreach_function(function, shader) { + if (function->impl) + progress |= nir_opt_algebraic_impl(function->impl, condition_flags); + } + + return progress; +} + + +#include "nir.h" +#include "nir_builder.h" +#include "nir_search.h" +#include "nir_search_helpers.h" + +#ifndef NIR_OPT_ALGEBRAIC_STRUCT_DEFS +#define NIR_OPT_ALGEBRAIC_STRUCT_DEFS + +struct transform { + const nir_search_expression *search; + const nir_search_value *replace; + unsigned condition_offset; +}; + +#endif + + +static const nir_search_variable search520_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + (is_not_const), +}; + +static const nir_search_variable search520_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search520_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fmul, + { &search520_0_0.value, &search520_0_1.value }, + (is_used_once), +}; + +static const nir_search_variable search520_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + (is_not_const), +}; +static const nir_search_expression search520 = { + { nir_search_value_expression, -3 }, + true, + nir_op_fmul, + { &search520_0.value, &search520_1.value }, + (is_used_once), +}; + +static const nir_search_variable replace520_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace520_0_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace520_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fmul, + { &replace520_0_0.value, &replace520_0_1.value }, + NULL, +}; + +static const nir_search_variable replace520_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace520 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fmul, + { &replace520_0.value, &replace520_1.value }, + NULL, +}; + +static const nir_search_variable search521_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + (is_not_const), +}; + +static const nir_search_variable search521_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search521_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_imul, + { &search521_0_0.value, &search521_0_1.value }, + (is_used_once), +}; + +static const nir_search_variable search521_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + (is_not_const), +}; +static const nir_search_expression search521 = { + { nir_search_value_expression, -3 }, + false, + nir_op_imul, + { &search521_0.value, &search521_1.value }, + (is_used_once), +}; + +static const nir_search_variable replace521_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace521_0_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace521_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_imul, + { &replace521_0_0.value, &replace521_0_1.value }, + NULL, +}; + +static const nir_search_variable replace521_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace521 = { + { nir_search_value_expression, -3 }, + false, + nir_op_imul, + { &replace521_0.value, &replace521_1.value }, + NULL, +}; + +static const nir_search_variable search522_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + (is_not_const), +}; + +static const nir_search_variable search522_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search522_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fadd, + { &search522_0_0.value, &search522_0_1.value }, + (is_used_once), +}; + +static const nir_search_variable search522_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + (is_not_const), +}; +static const nir_search_expression search522 = { + { nir_search_value_expression, -3 }, + true, + nir_op_fadd, + { &search522_0.value, &search522_1.value }, + (is_used_once), +}; + +static const nir_search_variable replace522_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace522_0_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace522_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fadd, + { &replace522_0_0.value, &replace522_0_1.value }, + NULL, +}; + +static const nir_search_variable replace522_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace522 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fadd, + { &replace522_0.value, &replace522_1.value }, + NULL, +}; + +static const nir_search_variable search523_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + (is_not_const), +}; + +static const nir_search_variable search523_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + true, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search523_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_iadd, + { &search523_0_0.value, &search523_0_1.value }, + (is_used_once), +}; + +static const nir_search_variable search523_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + (is_not_const), +}; +static const nir_search_expression search523 = { + { nir_search_value_expression, -3 }, + false, + nir_op_iadd, + { &search523_0.value, &search523_1.value }, + (is_used_once), +}; + +static const nir_search_variable replace523_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace523_0_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace523_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_iadd, + { &replace523_0_0.value, &replace523_0_1.value }, + NULL, +}; + +static const nir_search_variable replace523_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace523 = { + { nir_search_value_expression, -3 }, + false, + nir_op_iadd, + { &replace523_0.value, &replace523_1.value }, + NULL, +}; + +static const nir_search_variable search524_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search524_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search524_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fmul, + { &search524_0_0.value, &search524_0_1.value }, + NULL, +}; + +static const nir_search_variable search524_1_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search524_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search524_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fmul, + { &search524_1_0.value, &search524_1_1.value }, + NULL, +}; +static const nir_search_expression search524 = { + { nir_search_value_expression, -3 }, + true, + nir_op_fadd, + { &search524_0.value, &search524_1.value }, + NULL, +}; + +static const nir_search_variable replace524_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace524_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace524_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace524_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fadd, + { &replace524_1_0.value, &replace524_1_1.value }, + NULL, +}; +static const nir_search_expression replace524 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fmul, + { &replace524_0.value, &replace524_1.value }, + NULL, +}; + +static const nir_search_variable search525_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search525_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search525_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_imul, + { &search525_0_0.value, &search525_0_1.value }, + NULL, +}; + +static const nir_search_variable search525_1_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search525_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search525_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_imul, + { &search525_1_0.value, &search525_1_1.value }, + NULL, +}; +static const nir_search_expression search525 = { + { nir_search_value_expression, -3 }, + false, + nir_op_iadd, + { &search525_0.value, &search525_1.value }, + NULL, +}; + +static const nir_search_variable replace525_0 = { + { nir_search_value_variable, -3 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace525_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace525_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace525_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_iadd, + { &replace525_1_0.value, &replace525_1_1.value }, + NULL, +}; +static const nir_search_expression replace525 = { + { nir_search_value_expression, -3 }, + false, + nir_op_imul, + { &replace525_0.value, &replace525_1.value }, + NULL, +}; + +static const nir_search_variable search526_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search526_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_fneg, + { &search526_0_0.value }, + NULL, +}; + +static const nir_search_variable search526_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search526 = { + { nir_search_value_expression, -1 }, + true, + nir_op_fadd, + { &search526_0.value, &search526_1.value }, + NULL, +}; + +static const nir_search_constant replace526 = { + { nir_search_value_constant, -1 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; + +static const nir_search_variable search527_0_0 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search527_0 = { + { nir_search_value_expression, -1 }, + false, + nir_op_ineg, + { &search527_0_0.value }, + NULL, +}; + +static const nir_search_variable search527_1 = { + { nir_search_value_variable, -1 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search527 = { + { nir_search_value_expression, -1 }, + false, + nir_op_iadd, + { &search527_0.value, &search527_1.value }, + NULL, +}; + +static const nir_search_constant replace527 = { + { nir_search_value_constant, -1 }, + nir_type_int, { 0x0 /* 0 */ }, +}; + +static const nir_search_variable search528_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search528_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_ineg, + { &search528_0_0.value }, + NULL, +}; + +static const nir_search_variable search528_1_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search528_1_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search528_1 = { + { nir_search_value_expression, -2 }, + false, + nir_op_iadd, + { &search528_1_0.value, &search528_1_1.value }, + NULL, +}; +static const nir_search_expression search528 = { + { nir_search_value_expression, -2 }, + false, + nir_op_iadd, + { &search528_0.value, &search528_1.value }, + NULL, +}; + +static const nir_search_variable replace528 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search529_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search529_1_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search529_1_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_ineg, + { &search529_1_0_0.value }, + NULL, +}; + +static const nir_search_variable search529_1_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search529_1 = { + { nir_search_value_expression, -2 }, + false, + nir_op_iadd, + { &search529_1_0.value, &search529_1_1.value }, + NULL, +}; +static const nir_search_expression search529 = { + { nir_search_value_expression, -2 }, + false, + nir_op_iadd, + { &search529_0.value, &search529_1.value }, + NULL, +}; + +static const nir_search_variable replace529 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search530_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search530_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fneg, + { &search530_0_0.value }, + NULL, +}; + +static const nir_search_variable search530_1_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search530_1_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search530_1 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fadd, + { &search530_1_0.value, &search530_1_1.value }, + NULL, +}; +static const nir_search_expression search530 = { + { nir_search_value_expression, -2 }, + true, + nir_op_fadd, + { &search530_0.value, &search530_1.value }, + NULL, +}; + +static const nir_search_variable replace530 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search531_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search531_1_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search531_1_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fneg, + { &search531_1_0_0.value }, + NULL, +}; + +static const nir_search_variable search531_1_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search531_1 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fadd, + { &search531_1_0.value, &search531_1_1.value }, + NULL, +}; +static const nir_search_expression search531 = { + { nir_search_value_expression, -2 }, + true, + nir_op_fadd, + { &search531_0.value, &search531_1.value }, + NULL, +}; + +static const nir_search_variable replace531 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; + +static const struct transform nir_opt_algebraic_before_ffma_fadd_xforms[] = { + { &search522, &replace522.value, 0 }, + { &search524, &replace524.value, 0 }, + { &search526, &replace526.value, 0 }, + { &search530, &replace530.value, 0 }, + { &search531, &replace531.value, 0 }, +}; +static const struct transform nir_opt_algebraic_before_ffma_fmul_xforms[] = { + { &search520, &replace520.value, 0 }, +}; +static const struct transform nir_opt_algebraic_before_ffma_iadd_xforms[] = { + { &search523, &replace523.value, 0 }, + { &search525, &replace525.value, 0 }, + { &search527, &replace527.value, 0 }, + { &search528, &replace528.value, 0 }, + { &search529, &replace529.value, 0 }, +}; +static const struct transform nir_opt_algebraic_before_ffma_imul_xforms[] = { + { &search521, &replace521.value, 0 }, +}; + +static bool +nir_opt_algebraic_before_ffma_block(nir_builder *build, nir_block *block, + const bool *condition_flags) +{ + bool progress = false; + + nir_foreach_instr_reverse_safe(instr, block) { + if (instr->type != nir_instr_type_alu) + continue; + + nir_alu_instr *alu = nir_instr_as_alu(instr); + if (!alu->dest.dest.is_ssa) + continue; + + switch (alu->op) { + case nir_op_fadd: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_before_ffma_fadd_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_before_ffma_fadd_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_fmul: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_before_ffma_fmul_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_before_ffma_fmul_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_iadd: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_before_ffma_iadd_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_before_ffma_iadd_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_imul: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_before_ffma_imul_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_before_ffma_imul_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + default: + break; + } + } + + return progress; +} + +static bool +nir_opt_algebraic_before_ffma_impl(nir_function_impl *impl, const bool *condition_flags) +{ + bool progress = false; + + nir_builder build; + nir_builder_init(&build, impl); + + nir_foreach_block_reverse(block, impl) { + progress |= nir_opt_algebraic_before_ffma_block(&build, block, condition_flags); + } + + if (progress) { + nir_metadata_preserve(impl, nir_metadata_block_index | + nir_metadata_dominance); + } else { +#ifndef NDEBUG + impl->valid_metadata &= ~nir_metadata_not_properly_reset; +#endif + } + + return progress; +} + + +bool +nir_opt_algebraic_before_ffma(nir_shader *shader) +{ + bool progress = false; + bool condition_flags[45]; + const nir_shader_compiler_options *options = shader->options; + (void) options; + + condition_flags[0] = true; + condition_flags[1] = options->lower_idiv; + condition_flags[2] = options->lower_flrp32; + condition_flags[3] = options->lower_flrp64; + condition_flags[4] = options->lower_ffloor; + condition_flags[5] = options->lower_ffract; + condition_flags[6] = options->lower_fceil; + condition_flags[7] = !options->lower_flrp32; + condition_flags[8] = !options->lower_flrp64; + condition_flags[9] = options->lower_ffma; + condition_flags[10] = options->fuse_ffma; + condition_flags[11] = !options->lower_fsat; + condition_flags[12] = options->lower_fsat; + condition_flags[13] = options->lower_scmp; + condition_flags[14] = options->lower_fpow; + condition_flags[15] = !options->lower_fpow; + condition_flags[16] = options->lower_fdiv; + condition_flags[17] = options->lower_fsqrt; + condition_flags[18] = !options->lower_fsqrt; + condition_flags[19] = !options->lower_extract_byte; + condition_flags[20] = !options->lower_extract_word; + condition_flags[21] = options->lower_sub; + condition_flags[22] = options->lower_negate; + condition_flags[23] = options->lower_fmod32; + condition_flags[24] = options->lower_fmod64; + condition_flags[25] = options->lower_uadd_carry; + condition_flags[26] = options->lower_usub_borrow; + condition_flags[27] = options->lower_bitfield_insert; + condition_flags[28] = options->lower_bitfield_insert_to_shifts; + condition_flags[29] = options->lower_bfm; + condition_flags[30] = options->lower_bitfield_extract; + condition_flags[31] = options->lower_bitfield_extract_to_shifts; + condition_flags[32] = options->lower_ifind_msb; + condition_flags[33] = options->lower_find_lsb; + condition_flags[34] = options->lower_extract_byte; + condition_flags[35] = options->lower_extract_word; + condition_flags[36] = options->lower_pack_unorm_2x16; + condition_flags[37] = options->lower_pack_unorm_4x8; + condition_flags[38] = options->lower_pack_snorm_2x16; + condition_flags[39] = options->lower_pack_snorm_4x8; + condition_flags[40] = options->lower_unpack_unorm_2x16; + condition_flags[41] = options->lower_unpack_unorm_4x8; + condition_flags[42] = options->lower_unpack_snorm_2x16; + condition_flags[43] = options->lower_unpack_snorm_4x8; + condition_flags[44] = options->lower_ldexp; + + nir_foreach_function(function, shader) { + if (function->impl) + progress |= nir_opt_algebraic_before_ffma_impl(function->impl, condition_flags); + } + + return progress; +} + + +#include "nir.h" +#include "nir_builder.h" +#include "nir_search.h" +#include "nir_search_helpers.h" + +#ifndef NIR_OPT_ALGEBRAIC_STRUCT_DEFS +#define NIR_OPT_ALGEBRAIC_STRUCT_DEFS + +struct transform { + const nir_search_expression *search; + const nir_search_value *replace; + unsigned condition_offset; +}; + +#endif + + +static const nir_search_variable search532_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search532_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search532_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fadd, + { &search532_0_0.value, &search532_0_1.value }, + NULL, +}; + +static const nir_search_constant search532_1 = { + { nir_search_value_constant, -2 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search532 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search532_0.value, &search532_1.value }, + NULL, +}; + +static const nir_search_variable replace532_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace532_1_0 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace532_1 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fneg, + { &replace532_1_0.value }, + NULL, +}; +static const nir_search_expression replace532 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &replace532_0.value, &replace532_1.value }, + NULL, +}; + +static const nir_search_variable search533_0_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search533_0_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search533_0_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fadd, + { &search533_0_0_0.value, &search533_0_0_1.value }, + NULL, +}; +static const nir_search_expression search533_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fneg, + { &search533_0_0.value }, + NULL, +}; + +static const nir_search_constant search533_1 = { + { nir_search_value_constant, -2 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search533 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &search533_0.value, &search533_1.value }, + NULL, +}; + +static const nir_search_variable replace533_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace533_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fneg, + { &replace533_0_0.value }, + NULL, +}; + +static const nir_search_variable replace533_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace533 = { + { nir_search_value_expression, 1 }, + false, + nir_op_flt, + { &replace533_0.value, &replace533_1.value }, + NULL, +}; + +static const nir_search_variable search534_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search534_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search534_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fadd, + { &search534_0_0.value, &search534_0_1.value }, + NULL, +}; + +static const nir_search_constant search534_1 = { + { nir_search_value_constant, -2 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search534 = { + { nir_search_value_expression, 1 }, + true, + nir_op_fge, + { &search534_0.value, &search534_1.value }, + NULL, +}; + +static const nir_search_variable replace534_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace534_1_0 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace534_1 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fneg, + { &replace534_1_0.value }, + NULL, +}; +static const nir_search_expression replace534 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &replace534_0.value, &replace534_1.value }, + NULL, +}; + +static const nir_search_variable search535_0_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search535_0_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search535_0_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fadd, + { &search535_0_0_0.value, &search535_0_0_1.value }, + NULL, +}; +static const nir_search_expression search535_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fneg, + { &search535_0_0.value }, + NULL, +}; + +static const nir_search_constant search535_1 = { + { nir_search_value_constant, -2 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search535 = { + { nir_search_value_expression, 1 }, + true, + nir_op_fge, + { &search535_0.value, &search535_1.value }, + NULL, +}; + +static const nir_search_variable replace535_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace535_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fneg, + { &replace535_0_0.value }, + NULL, +}; + +static const nir_search_variable replace535_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace535 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &replace535_0.value, &replace535_1.value }, + NULL, +}; + +static const nir_search_variable search536_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search536_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search536_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fadd, + { &search536_0_0.value, &search536_0_1.value }, + NULL, +}; + +static const nir_search_constant search536_1 = { + { nir_search_value_constant, -2 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search536 = { + { nir_search_value_expression, 1 }, + true, + nir_op_feq, + { &search536_0.value, &search536_1.value }, + NULL, +}; + +static const nir_search_variable replace536_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace536_1_0 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace536_1 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fneg, + { &replace536_1_0.value }, + NULL, +}; +static const nir_search_expression replace536 = { + { nir_search_value_expression, 1 }, + false, + nir_op_feq, + { &replace536_0.value, &replace536_1.value }, + NULL, +}; + +static const nir_search_variable search537_0_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search537_0_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search537_0 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fadd, + { &search537_0_0.value, &search537_0_1.value }, + NULL, +}; + +static const nir_search_constant search537_1 = { + { nir_search_value_constant, -2 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search537 = { + { nir_search_value_expression, 1 }, + true, + nir_op_fne, + { &search537_0.value, &search537_1.value }, + NULL, +}; + +static const nir_search_variable replace537_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace537_1_0 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace537_1 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fneg, + { &replace537_1_0.value }, + NULL, +}; +static const nir_search_expression replace537 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fne, + { &replace537_0.value, &replace537_1.value }, + NULL, +}; + +static const nir_search_variable search538_0_0_0 = { + { nir_search_value_variable, -4 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search538_0_0_1 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search538_0_0 = { + { nir_search_value_expression, -4 }, + false, + nir_op_fadd, + { &search538_0_0_0.value, &search538_0_0_1.value }, + (is_used_once), +}; + +static const nir_search_variable search538_0_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search538_0_1_1 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search538_0_1 = { + { nir_search_value_expression, -4 }, + false, + nir_op_fadd, + { &search538_0_1_0.value, &search538_0_1_1.value }, + NULL, +}; +static const nir_search_expression search538_0 = { + { nir_search_value_expression, -4 }, + false, + nir_op_fmin, + { &search538_0_0.value, &search538_0_1.value }, + (is_used_once), +}; + +static const nir_search_constant search538_1 = { + { nir_search_value_constant, -4 }, + nir_type_float, { 0x0 /* 0.0 */ }, +}; +static const nir_search_expression search538 = { + { nir_search_value_expression, 1 }, + true, + nir_op_fge, + { &search538_0.value, &search538_1.value }, + NULL, +}; + +static const nir_search_variable replace538_0_0 = { + { nir_search_value_variable, -4 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace538_0_1_0 = { + { nir_search_value_variable, -4 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace538_0_1 = { + { nir_search_value_expression, -4 }, + false, + nir_op_fneg, + { &replace538_0_1_0.value }, + NULL, +}; +static const nir_search_expression replace538_0 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &replace538_0_0.value, &replace538_0_1.value }, + NULL, +}; + +static const nir_search_variable replace538_1_0 = { + { nir_search_value_variable, -4 }, + 2, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace538_1_1_0 = { + { nir_search_value_variable, -4 }, + 3, /* d */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace538_1_1 = { + { nir_search_value_expression, -4 }, + false, + nir_op_fneg, + { &replace538_1_1_0.value }, + NULL, +}; +static const nir_search_expression replace538_1 = { + { nir_search_value_expression, 1 }, + false, + nir_op_fge, + { &replace538_1_0.value, &replace538_1_1.value }, + NULL, +}; +static const nir_search_expression replace538 = { + { nir_search_value_expression, 1 }, + false, + nir_op_iand, + { &replace538_0.value, &replace538_1.value }, + NULL, +}; + +static const nir_search_variable search539_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search539_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search539 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fdot2, + { &search539_0.value, &search539_1.value }, + NULL, +}; + +static const nir_search_variable replace539_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace539_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace539 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fdot_replicated2, + { &replace539_0.value, &replace539_1.value }, + NULL, +}; + +static const nir_search_variable search540_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search540_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search540 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fdot3, + { &search540_0.value, &search540_1.value }, + NULL, +}; + +static const nir_search_variable replace540_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace540_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace540 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fdot_replicated3, + { &replace540_0.value, &replace540_1.value }, + NULL, +}; + +static const nir_search_variable search541_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search541_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search541 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fdot4, + { &search541_0.value, &search541_1.value }, + NULL, +}; + +static const nir_search_variable replace541_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace541_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace541 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fdot_replicated4, + { &replace541_0.value, &replace541_1.value }, + NULL, +}; + +static const nir_search_variable search542_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search542_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search542 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fdph, + { &search542_0.value, &search542_1.value }, + NULL, +}; + +static const nir_search_variable replace542_0 = { + { nir_search_value_variable, -2 }, + 0, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace542_1 = { + { nir_search_value_variable, -2 }, + 1, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace542 = { + { nir_search_value_expression, -2 }, + false, + nir_op_fdph_replicated, + { &replace542_0.value, &replace542_1.value }, + NULL, +}; + +static const nir_search_variable search543_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* c */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search543_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search543_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fadd, + { &search543_0_0.value, &search543_0_1.value }, + (is_used_once), +}; + +static const nir_search_variable search543_1_0 = { + { nir_search_value_variable, -3 }, + 0, /* c */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search543_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search543_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fadd, + { &search543_1_0.value, &search543_1_1.value }, + (is_used_once), +}; +static const nir_search_expression search543 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fmin, + { &search543_0.value, &search543_1.value }, + NULL, +}; + +static const nir_search_variable replace543_0 = { + { nir_search_value_variable, -3 }, + 0, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace543_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace543_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace543_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fmin, + { &replace543_1_0.value, &replace543_1_1.value }, + NULL, +}; +static const nir_search_expression replace543 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fadd, + { &replace543_0.value, &replace543_1.value }, + NULL, +}; + +static const nir_search_variable search544_0_0 = { + { nir_search_value_variable, -3 }, + 0, /* c */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search544_0_1 = { + { nir_search_value_variable, -3 }, + 1, /* a */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search544_0 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fadd, + { &search544_0_0.value, &search544_0_1.value }, + (is_used_once), +}; + +static const nir_search_variable search544_1_0 = { + { nir_search_value_variable, -3 }, + 0, /* c */ + true, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable search544_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression search544_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fadd, + { &search544_1_0.value, &search544_1_1.value }, + (is_used_once), +}; +static const nir_search_expression search544 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fmax, + { &search544_0.value, &search544_1.value }, + NULL, +}; + +static const nir_search_variable replace544_0 = { + { nir_search_value_variable, -3 }, + 0, /* c */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace544_1_0 = { + { nir_search_value_variable, -3 }, + 1, /* a */ + false, + nir_type_invalid, + NULL, +}; + +static const nir_search_variable replace544_1_1 = { + { nir_search_value_variable, -3 }, + 2, /* b */ + false, + nir_type_invalid, + NULL, +}; +static const nir_search_expression replace544_1 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fmax, + { &replace544_1_0.value, &replace544_1_1.value }, + NULL, +}; +static const nir_search_expression replace544 = { + { nir_search_value_expression, -3 }, + false, + nir_op_fadd, + { &replace544_0.value, &replace544_1.value }, + NULL, +}; + +static const struct transform nir_opt_algebraic_late_fdot2_xforms[] = { + { &search539, &replace539.value, 45 }, +}; +static const struct transform nir_opt_algebraic_late_fdot3_xforms[] = { + { &search540, &replace540.value, 45 }, +}; +static const struct transform nir_opt_algebraic_late_fdot4_xforms[] = { + { &search541, &replace541.value, 45 }, +}; +static const struct transform nir_opt_algebraic_late_fdph_xforms[] = { + { &search542, &replace542.value, 45 }, +}; +static const struct transform nir_opt_algebraic_late_feq_xforms[] = { + { &search536, &replace536.value, 0 }, +}; +static const struct transform nir_opt_algebraic_late_fge_xforms[] = { + { &search534, &replace534.value, 0 }, + { &search535, &replace535.value, 0 }, + { &search538, &replace538.value, 0 }, +}; +static const struct transform nir_opt_algebraic_late_flt_xforms[] = { + { &search532, &replace532.value, 0 }, + { &search533, &replace533.value, 0 }, +}; +static const struct transform nir_opt_algebraic_late_fmax_xforms[] = { + { &search544, &replace544.value, 0 }, +}; +static const struct transform nir_opt_algebraic_late_fmin_xforms[] = { + { &search543, &replace543.value, 0 }, +}; +static const struct transform nir_opt_algebraic_late_fne_xforms[] = { + { &search537, &replace537.value, 0 }, +}; + +static bool +nir_opt_algebraic_late_block(nir_builder *build, nir_block *block, + const bool *condition_flags) +{ + bool progress = false; + + nir_foreach_instr_reverse_safe(instr, block) { + if (instr->type != nir_instr_type_alu) + continue; + + nir_alu_instr *alu = nir_instr_as_alu(instr); + if (!alu->dest.dest.is_ssa) + continue; + + switch (alu->op) { + case nir_op_fdot2: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_late_fdot2_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_late_fdot2_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_fdot3: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_late_fdot3_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_late_fdot3_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_fdot4: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_late_fdot4_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_late_fdot4_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_fdph: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_late_fdph_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_late_fdph_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_feq: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_late_feq_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_late_feq_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_fge: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_late_fge_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_late_fge_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_flt: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_late_flt_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_late_flt_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_fmax: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_late_fmax_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_late_fmax_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_fmin: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_late_fmin_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_late_fmin_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + case nir_op_fne: + for (unsigned i = 0; i < ARRAY_SIZE(nir_opt_algebraic_late_fne_xforms); i++) { + const struct transform *xform = &nir_opt_algebraic_late_fne_xforms[i]; + if (condition_flags[xform->condition_offset] && + nir_replace_instr(build, alu, xform->search, xform->replace)) { + progress = true; + break; + } + } + break; + default: + break; + } + } + + return progress; +} + +static bool +nir_opt_algebraic_late_impl(nir_function_impl *impl, const bool *condition_flags) +{ + bool progress = false; + + nir_builder build; + nir_builder_init(&build, impl); + + nir_foreach_block_reverse(block, impl) { + progress |= nir_opt_algebraic_late_block(&build, block, condition_flags); + } + + if (progress) { + nir_metadata_preserve(impl, nir_metadata_block_index | + nir_metadata_dominance); + } else { +#ifndef NDEBUG + impl->valid_metadata &= ~nir_metadata_not_properly_reset; +#endif + } + + return progress; +} + + +bool +nir_opt_algebraic_late(nir_shader *shader) +{ + bool progress = false; + bool condition_flags[46]; + const nir_shader_compiler_options *options = shader->options; + (void) options; + + condition_flags[0] = true; + condition_flags[1] = options->lower_idiv; + condition_flags[2] = options->lower_flrp32; + condition_flags[3] = options->lower_flrp64; + condition_flags[4] = options->lower_ffloor; + condition_flags[5] = options->lower_ffract; + condition_flags[6] = options->lower_fceil; + condition_flags[7] = !options->lower_flrp32; + condition_flags[8] = !options->lower_flrp64; + condition_flags[9] = options->lower_ffma; + condition_flags[10] = options->fuse_ffma; + condition_flags[11] = !options->lower_fsat; + condition_flags[12] = options->lower_fsat; + condition_flags[13] = options->lower_scmp; + condition_flags[14] = options->lower_fpow; + condition_flags[15] = !options->lower_fpow; + condition_flags[16] = options->lower_fdiv; + condition_flags[17] = options->lower_fsqrt; + condition_flags[18] = !options->lower_fsqrt; + condition_flags[19] = !options->lower_extract_byte; + condition_flags[20] = !options->lower_extract_word; + condition_flags[21] = options->lower_sub; + condition_flags[22] = options->lower_negate; + condition_flags[23] = options->lower_fmod32; + condition_flags[24] = options->lower_fmod64; + condition_flags[25] = options->lower_uadd_carry; + condition_flags[26] = options->lower_usub_borrow; + condition_flags[27] = options->lower_bitfield_insert; + condition_flags[28] = options->lower_bitfield_insert_to_shifts; + condition_flags[29] = options->lower_bfm; + condition_flags[30] = options->lower_bitfield_extract; + condition_flags[31] = options->lower_bitfield_extract_to_shifts; + condition_flags[32] = options->lower_ifind_msb; + condition_flags[33] = options->lower_find_lsb; + condition_flags[34] = options->lower_extract_byte; + condition_flags[35] = options->lower_extract_word; + condition_flags[36] = options->lower_pack_unorm_2x16; + condition_flags[37] = options->lower_pack_unorm_4x8; + condition_flags[38] = options->lower_pack_snorm_2x16; + condition_flags[39] = options->lower_pack_snorm_4x8; + condition_flags[40] = options->lower_unpack_unorm_2x16; + condition_flags[41] = options->lower_unpack_unorm_4x8; + condition_flags[42] = options->lower_unpack_snorm_2x16; + condition_flags[43] = options->lower_unpack_snorm_4x8; + condition_flags[44] = options->lower_ldexp; + condition_flags[45] = options->fdot_replicates; + + nir_foreach_function(function, shader) { + if (function->impl) + progress |= nir_opt_algebraic_late_impl(function->impl, condition_flags); + } + + return progress; +} + diff --git a/prebuilt-intermediates/spirv/spirv_info.c b/prebuilt-intermediates/spirv/spirv_info.c new file mode 100644 index 00000000000..158f6c42018 --- /dev/null +++ b/prebuilt-intermediates/spirv/spirv_info.c @@ -0,0 +1,678 @@ +/* DO NOT EDIT - This file is generated automatically by spirv_info_c.py script */ + +/* + * Copyright (C) 2017 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ +#include "spirv_info.h" + +const char * +spirv_capability_to_string(SpvCapability v) +{ + switch (v) { + case SpvCapabilityMatrix: return "SpvCapabilityMatrix"; + case SpvCapabilityShader: return "SpvCapabilityShader"; + case SpvCapabilityGeometry: return "SpvCapabilityGeometry"; + case SpvCapabilityTessellation: return "SpvCapabilityTessellation"; + case SpvCapabilityAddresses: return "SpvCapabilityAddresses"; + case SpvCapabilityLinkage: return "SpvCapabilityLinkage"; + case SpvCapabilityKernel: return "SpvCapabilityKernel"; + case SpvCapabilityVector16: return "SpvCapabilityVector16"; + case SpvCapabilityFloat16Buffer: return "SpvCapabilityFloat16Buffer"; + case SpvCapabilityFloat16: return "SpvCapabilityFloat16"; + case SpvCapabilityFloat64: return "SpvCapabilityFloat64"; + case SpvCapabilityInt64: return "SpvCapabilityInt64"; + case SpvCapabilityInt64Atomics: return "SpvCapabilityInt64Atomics"; + case SpvCapabilityImageBasic: return "SpvCapabilityImageBasic"; + case SpvCapabilityImageReadWrite: return "SpvCapabilityImageReadWrite"; + case SpvCapabilityImageMipmap: return "SpvCapabilityImageMipmap"; + case SpvCapabilityPipes: return "SpvCapabilityPipes"; + case SpvCapabilityGroups: return "SpvCapabilityGroups"; + case SpvCapabilityDeviceEnqueue: return "SpvCapabilityDeviceEnqueue"; + case SpvCapabilityLiteralSampler: return "SpvCapabilityLiteralSampler"; + case SpvCapabilityAtomicStorage: return "SpvCapabilityAtomicStorage"; + case SpvCapabilityInt16: return "SpvCapabilityInt16"; + case SpvCapabilityTessellationPointSize: return "SpvCapabilityTessellationPointSize"; + case SpvCapabilityGeometryPointSize: return "SpvCapabilityGeometryPointSize"; + case SpvCapabilityImageGatherExtended: return "SpvCapabilityImageGatherExtended"; + case SpvCapabilityStorageImageMultisample: return "SpvCapabilityStorageImageMultisample"; + case SpvCapabilityUniformBufferArrayDynamicIndexing: return "SpvCapabilityUniformBufferArrayDynamicIndexing"; + case SpvCapabilitySampledImageArrayDynamicIndexing: return "SpvCapabilitySampledImageArrayDynamicIndexing"; + case SpvCapabilityStorageBufferArrayDynamicIndexing: return "SpvCapabilityStorageBufferArrayDynamicIndexing"; + case SpvCapabilityStorageImageArrayDynamicIndexing: return "SpvCapabilityStorageImageArrayDynamicIndexing"; + case SpvCapabilityClipDistance: return "SpvCapabilityClipDistance"; + case SpvCapabilityCullDistance: return "SpvCapabilityCullDistance"; + case SpvCapabilityImageCubeArray: return "SpvCapabilityImageCubeArray"; + case SpvCapabilitySampleRateShading: return "SpvCapabilitySampleRateShading"; + case SpvCapabilityImageRect: return "SpvCapabilityImageRect"; + case SpvCapabilitySampledRect: return "SpvCapabilitySampledRect"; + case SpvCapabilityGenericPointer: return "SpvCapabilityGenericPointer"; + case SpvCapabilityInt8: return "SpvCapabilityInt8"; + case SpvCapabilityInputAttachment: return "SpvCapabilityInputAttachment"; + case SpvCapabilitySparseResidency: return "SpvCapabilitySparseResidency"; + case SpvCapabilityMinLod: return "SpvCapabilityMinLod"; + case SpvCapabilitySampled1D: return "SpvCapabilitySampled1D"; + case SpvCapabilityImage1D: return "SpvCapabilityImage1D"; + case SpvCapabilitySampledCubeArray: return "SpvCapabilitySampledCubeArray"; + case SpvCapabilitySampledBuffer: return "SpvCapabilitySampledBuffer"; + case SpvCapabilityImageBuffer: return "SpvCapabilityImageBuffer"; + case SpvCapabilityImageMSArray: return "SpvCapabilityImageMSArray"; + case SpvCapabilityStorageImageExtendedFormats: return "SpvCapabilityStorageImageExtendedFormats"; + case SpvCapabilityImageQuery: return "SpvCapabilityImageQuery"; + case SpvCapabilityDerivativeControl: return "SpvCapabilityDerivativeControl"; + case SpvCapabilityInterpolationFunction: return "SpvCapabilityInterpolationFunction"; + case SpvCapabilityTransformFeedback: return "SpvCapabilityTransformFeedback"; + case SpvCapabilityGeometryStreams: return "SpvCapabilityGeometryStreams"; + case SpvCapabilityStorageImageReadWithoutFormat: return "SpvCapabilityStorageImageReadWithoutFormat"; + case SpvCapabilityStorageImageWriteWithoutFormat: return "SpvCapabilityStorageImageWriteWithoutFormat"; + case SpvCapabilityMultiViewport: return "SpvCapabilityMultiViewport"; + case SpvCapabilitySubgroupDispatch: return "SpvCapabilitySubgroupDispatch"; + case SpvCapabilityNamedBarrier: return "SpvCapabilityNamedBarrier"; + case SpvCapabilityPipeStorage: return "SpvCapabilityPipeStorage"; + case SpvCapabilityGroupNonUniform: return "SpvCapabilityGroupNonUniform"; + case SpvCapabilityGroupNonUniformVote: return "SpvCapabilityGroupNonUniformVote"; + case SpvCapabilityGroupNonUniformArithmetic: return "SpvCapabilityGroupNonUniformArithmetic"; + case SpvCapabilityGroupNonUniformBallot: return "SpvCapabilityGroupNonUniformBallot"; + case SpvCapabilityGroupNonUniformShuffle: return "SpvCapabilityGroupNonUniformShuffle"; + case SpvCapabilityGroupNonUniformShuffleRelative: return "SpvCapabilityGroupNonUniformShuffleRelative"; + case SpvCapabilityGroupNonUniformClustered: return "SpvCapabilityGroupNonUniformClustered"; + case SpvCapabilityGroupNonUniformQuad: return "SpvCapabilityGroupNonUniformQuad"; + case SpvCapabilitySubgroupBallotKHR: return "SpvCapabilitySubgroupBallotKHR"; + case SpvCapabilityDrawParameters: return "SpvCapabilityDrawParameters"; + case SpvCapabilitySubgroupVoteKHR: return "SpvCapabilitySubgroupVoteKHR"; + case SpvCapabilityStorageBuffer16BitAccess: return "SpvCapabilityStorageBuffer16BitAccess"; + case SpvCapabilityUniformAndStorageBuffer16BitAccess: return "SpvCapabilityUniformAndStorageBuffer16BitAccess"; + case SpvCapabilityStoragePushConstant16: return "SpvCapabilityStoragePushConstant16"; + case SpvCapabilityStorageInputOutput16: return "SpvCapabilityStorageInputOutput16"; + case SpvCapabilityDeviceGroup: return "SpvCapabilityDeviceGroup"; + case SpvCapabilityMultiView: return "SpvCapabilityMultiView"; + case SpvCapabilityVariablePointersStorageBuffer: return "SpvCapabilityVariablePointersStorageBuffer"; + case SpvCapabilityVariablePointers: return "SpvCapabilityVariablePointers"; + case SpvCapabilityAtomicStorageOps: return "SpvCapabilityAtomicStorageOps"; + case SpvCapabilitySampleMaskPostDepthCoverage: return "SpvCapabilitySampleMaskPostDepthCoverage"; + case SpvCapabilityStorageBuffer8BitAccess: return "SpvCapabilityStorageBuffer8BitAccess"; + case SpvCapabilityUniformAndStorageBuffer8BitAccess: return "SpvCapabilityUniformAndStorageBuffer8BitAccess"; + case SpvCapabilityStoragePushConstant8: return "SpvCapabilityStoragePushConstant8"; + case SpvCapabilityDenormPreserve: return "SpvCapabilityDenormPreserve"; + case SpvCapabilityDenormFlushToZero: return "SpvCapabilityDenormFlushToZero"; + case SpvCapabilitySignedZeroInfNanPreserve: return "SpvCapabilitySignedZeroInfNanPreserve"; + case SpvCapabilityRoundingModeRTE: return "SpvCapabilityRoundingModeRTE"; + case SpvCapabilityRoundingModeRTZ: return "SpvCapabilityRoundingModeRTZ"; + case SpvCapabilityFloat16ImageAMD: return "SpvCapabilityFloat16ImageAMD"; + case SpvCapabilityImageGatherBiasLodAMD: return "SpvCapabilityImageGatherBiasLodAMD"; + case SpvCapabilityFragmentMaskAMD: return "SpvCapabilityFragmentMaskAMD"; + case SpvCapabilityStencilExportEXT: return "SpvCapabilityStencilExportEXT"; + case SpvCapabilityImageReadWriteLodAMD: return "SpvCapabilityImageReadWriteLodAMD"; + case SpvCapabilitySampleMaskOverrideCoverageNV: return "SpvCapabilitySampleMaskOverrideCoverageNV"; + case SpvCapabilityGeometryShaderPassthroughNV: return "SpvCapabilityGeometryShaderPassthroughNV"; + case SpvCapabilityShaderViewportIndexLayerEXT: return "SpvCapabilityShaderViewportIndexLayerEXT"; + case SpvCapabilityShaderViewportMaskNV: return "SpvCapabilityShaderViewportMaskNV"; + case SpvCapabilityShaderStereoViewNV: return "SpvCapabilityShaderStereoViewNV"; + case SpvCapabilityPerViewAttributesNV: return "SpvCapabilityPerViewAttributesNV"; + case SpvCapabilityFragmentFullyCoveredEXT: return "SpvCapabilityFragmentFullyCoveredEXT"; + case SpvCapabilityMeshShadingNV: return "SpvCapabilityMeshShadingNV"; + case SpvCapabilityShaderNonUniformEXT: return "SpvCapabilityShaderNonUniformEXT"; + case SpvCapabilityRuntimeDescriptorArrayEXT: return "SpvCapabilityRuntimeDescriptorArrayEXT"; + case SpvCapabilityInputAttachmentArrayDynamicIndexingEXT: return "SpvCapabilityInputAttachmentArrayDynamicIndexingEXT"; + case SpvCapabilityUniformTexelBufferArrayDynamicIndexingEXT: return "SpvCapabilityUniformTexelBufferArrayDynamicIndexingEXT"; + case SpvCapabilityStorageTexelBufferArrayDynamicIndexingEXT: return "SpvCapabilityStorageTexelBufferArrayDynamicIndexingEXT"; + case SpvCapabilityUniformBufferArrayNonUniformIndexingEXT: return "SpvCapabilityUniformBufferArrayNonUniformIndexingEXT"; + case SpvCapabilitySampledImageArrayNonUniformIndexingEXT: return "SpvCapabilitySampledImageArrayNonUniformIndexingEXT"; + case SpvCapabilityStorageBufferArrayNonUniformIndexingEXT: return "SpvCapabilityStorageBufferArrayNonUniformIndexingEXT"; + case SpvCapabilityStorageImageArrayNonUniformIndexingEXT: return "SpvCapabilityStorageImageArrayNonUniformIndexingEXT"; + case SpvCapabilityInputAttachmentArrayNonUniformIndexingEXT: return "SpvCapabilityInputAttachmentArrayNonUniformIndexingEXT"; + case SpvCapabilityUniformTexelBufferArrayNonUniformIndexingEXT: return "SpvCapabilityUniformTexelBufferArrayNonUniformIndexingEXT"; + case SpvCapabilityStorageTexelBufferArrayNonUniformIndexingEXT: return "SpvCapabilityStorageTexelBufferArrayNonUniformIndexingEXT"; + case SpvCapabilityRayTracingNV: return "SpvCapabilityRayTracingNV"; + case SpvCapabilitySubgroupShuffleINTEL: return "SpvCapabilitySubgroupShuffleINTEL"; + case SpvCapabilitySubgroupBufferBlockIOINTEL: return "SpvCapabilitySubgroupBufferBlockIOINTEL"; + case SpvCapabilitySubgroupImageBlockIOINTEL: return "SpvCapabilitySubgroupImageBlockIOINTEL"; + case SpvCapabilityGroupNonUniformPartitionedNV: return "SpvCapabilityGroupNonUniformPartitionedNV"; + case SpvCapabilityVulkanMemoryModelKHR: return "SpvCapabilityVulkanMemoryModelKHR"; + case SpvCapabilityVulkanMemoryModelDeviceScopeKHR: return "SpvCapabilityVulkanMemoryModelDeviceScopeKHR"; + case SpvCapabilityImageFootprintNV: return "SpvCapabilityImageFootprintNV"; + case SpvCapabilityFragmentBarycentricNV: return "SpvCapabilityFragmentBarycentricNV"; + case SpvCapabilityComputeDerivativeGroupQuadsNV: return "SpvCapabilityComputeDerivativeGroupQuadsNV"; + case SpvCapabilityComputeDerivativeGroupLinearNV: return "SpvCapabilityComputeDerivativeGroupLinearNV"; + case SpvCapabilityFragmentDensityEXT: return "SpvCapabilityFragmentDensityEXT"; + case SpvCapabilityPhysicalStorageBufferAddressesEXT: return "SpvCapabilityPhysicalStorageBufferAddressesEXT"; + case SpvCapabilityMax: break; /* silence warnings about unhandled enums. */ + } + + return "unknown"; +} + +const char * +spirv_decoration_to_string(SpvDecoration v) +{ + switch (v) { + case SpvDecorationRelaxedPrecision: return "SpvDecorationRelaxedPrecision"; + case SpvDecorationSpecId: return "SpvDecorationSpecId"; + case SpvDecorationBlock: return "SpvDecorationBlock"; + case SpvDecorationBufferBlock: return "SpvDecorationBufferBlock"; + case SpvDecorationRowMajor: return "SpvDecorationRowMajor"; + case SpvDecorationColMajor: return "SpvDecorationColMajor"; + case SpvDecorationArrayStride: return "SpvDecorationArrayStride"; + case SpvDecorationMatrixStride: return "SpvDecorationMatrixStride"; + case SpvDecorationGLSLShared: return "SpvDecorationGLSLShared"; + case SpvDecorationGLSLPacked: return "SpvDecorationGLSLPacked"; + case SpvDecorationCPacked: return "SpvDecorationCPacked"; + case SpvDecorationBuiltIn: return "SpvDecorationBuiltIn"; + case SpvDecorationNoPerspective: return "SpvDecorationNoPerspective"; + case SpvDecorationFlat: return "SpvDecorationFlat"; + case SpvDecorationPatch: return "SpvDecorationPatch"; + case SpvDecorationCentroid: return "SpvDecorationCentroid"; + case SpvDecorationSample: return "SpvDecorationSample"; + case SpvDecorationInvariant: return "SpvDecorationInvariant"; + case SpvDecorationRestrict: return "SpvDecorationRestrict"; + case SpvDecorationAliased: return "SpvDecorationAliased"; + case SpvDecorationVolatile: return "SpvDecorationVolatile"; + case SpvDecorationConstant: return "SpvDecorationConstant"; + case SpvDecorationCoherent: return "SpvDecorationCoherent"; + case SpvDecorationNonWritable: return "SpvDecorationNonWritable"; + case SpvDecorationNonReadable: return "SpvDecorationNonReadable"; + case SpvDecorationUniform: return "SpvDecorationUniform"; + case SpvDecorationSaturatedConversion: return "SpvDecorationSaturatedConversion"; + case SpvDecorationStream: return "SpvDecorationStream"; + case SpvDecorationLocation: return "SpvDecorationLocation"; + case SpvDecorationComponent: return "SpvDecorationComponent"; + case SpvDecorationIndex: return "SpvDecorationIndex"; + case SpvDecorationBinding: return "SpvDecorationBinding"; + case SpvDecorationDescriptorSet: return "SpvDecorationDescriptorSet"; + case SpvDecorationOffset: return "SpvDecorationOffset"; + case SpvDecorationXfbBuffer: return "SpvDecorationXfbBuffer"; + case SpvDecorationXfbStride: return "SpvDecorationXfbStride"; + case SpvDecorationFuncParamAttr: return "SpvDecorationFuncParamAttr"; + case SpvDecorationFPRoundingMode: return "SpvDecorationFPRoundingMode"; + case SpvDecorationFPFastMathMode: return "SpvDecorationFPFastMathMode"; + case SpvDecorationLinkageAttributes: return "SpvDecorationLinkageAttributes"; + case SpvDecorationNoContraction: return "SpvDecorationNoContraction"; + case SpvDecorationInputAttachmentIndex: return "SpvDecorationInputAttachmentIndex"; + case SpvDecorationAlignment: return "SpvDecorationAlignment"; + case SpvDecorationMaxByteOffset: return "SpvDecorationMaxByteOffset"; + case SpvDecorationAlignmentId: return "SpvDecorationAlignmentId"; + case SpvDecorationMaxByteOffsetId: return "SpvDecorationMaxByteOffsetId"; + case SpvDecorationNoSignedWrap: return "SpvDecorationNoSignedWrap"; + case SpvDecorationNoUnsignedWrap: return "SpvDecorationNoUnsignedWrap"; + case SpvDecorationExplicitInterpAMD: return "SpvDecorationExplicitInterpAMD"; + case SpvDecorationOverrideCoverageNV: return "SpvDecorationOverrideCoverageNV"; + case SpvDecorationPassthroughNV: return "SpvDecorationPassthroughNV"; + case SpvDecorationViewportRelativeNV: return "SpvDecorationViewportRelativeNV"; + case SpvDecorationSecondaryViewportRelativeNV: return "SpvDecorationSecondaryViewportRelativeNV"; + case SpvDecorationPerPrimitiveNV: return "SpvDecorationPerPrimitiveNV"; + case SpvDecorationPerViewNV: return "SpvDecorationPerViewNV"; + case SpvDecorationPerTaskNV: return "SpvDecorationPerTaskNV"; + case SpvDecorationPerVertexNV: return "SpvDecorationPerVertexNV"; + case SpvDecorationNonUniformEXT: return "SpvDecorationNonUniformEXT"; + case SpvDecorationHlslCounterBufferGOOGLE: return "SpvDecorationHlslCounterBufferGOOGLE"; + case SpvDecorationHlslSemanticGOOGLE: return "SpvDecorationHlslSemanticGOOGLE"; + case SpvDecorationRestrictPointerEXT: return "SpvDecorationRestrictPointerEXT"; + case SpvDecorationAliasedPointerEXT: return "SpvDecorationAliasedPointerEXT"; + case SpvDecorationMax: break; /* silence warnings about unhandled enums. */ + } + + return "unknown"; +} + +const char * +spirv_executionmode_to_string(SpvExecutionMode v) +{ + switch (v) { + case SpvExecutionModeInvocations: return "SpvExecutionModeInvocations"; + case SpvExecutionModeSpacingEqual: return "SpvExecutionModeSpacingEqual"; + case SpvExecutionModeSpacingFractionalEven: return "SpvExecutionModeSpacingFractionalEven"; + case SpvExecutionModeSpacingFractionalOdd: return "SpvExecutionModeSpacingFractionalOdd"; + case SpvExecutionModeVertexOrderCw: return "SpvExecutionModeVertexOrderCw"; + case SpvExecutionModeVertexOrderCcw: return "SpvExecutionModeVertexOrderCcw"; + case SpvExecutionModePixelCenterInteger: return "SpvExecutionModePixelCenterInteger"; + case SpvExecutionModeOriginUpperLeft: return "SpvExecutionModeOriginUpperLeft"; + case SpvExecutionModeOriginLowerLeft: return "SpvExecutionModeOriginLowerLeft"; + case SpvExecutionModeEarlyFragmentTests: return "SpvExecutionModeEarlyFragmentTests"; + case SpvExecutionModePointMode: return "SpvExecutionModePointMode"; + case SpvExecutionModeXfb: return "SpvExecutionModeXfb"; + case SpvExecutionModeDepthReplacing: return "SpvExecutionModeDepthReplacing"; + case SpvExecutionModeDepthGreater: return "SpvExecutionModeDepthGreater"; + case SpvExecutionModeDepthLess: return "SpvExecutionModeDepthLess"; + case SpvExecutionModeDepthUnchanged: return "SpvExecutionModeDepthUnchanged"; + case SpvExecutionModeLocalSize: return "SpvExecutionModeLocalSize"; + case SpvExecutionModeLocalSizeHint: return "SpvExecutionModeLocalSizeHint"; + case SpvExecutionModeInputPoints: return "SpvExecutionModeInputPoints"; + case SpvExecutionModeInputLines: return "SpvExecutionModeInputLines"; + case SpvExecutionModeInputLinesAdjacency: return "SpvExecutionModeInputLinesAdjacency"; + case SpvExecutionModeTriangles: return "SpvExecutionModeTriangles"; + case SpvExecutionModeInputTrianglesAdjacency: return "SpvExecutionModeInputTrianglesAdjacency"; + case SpvExecutionModeQuads: return "SpvExecutionModeQuads"; + case SpvExecutionModeIsolines: return "SpvExecutionModeIsolines"; + case SpvExecutionModeOutputVertices: return "SpvExecutionModeOutputVertices"; + case SpvExecutionModeOutputPoints: return "SpvExecutionModeOutputPoints"; + case SpvExecutionModeOutputLineStrip: return "SpvExecutionModeOutputLineStrip"; + case SpvExecutionModeOutputTriangleStrip: return "SpvExecutionModeOutputTriangleStrip"; + case SpvExecutionModeVecTypeHint: return "SpvExecutionModeVecTypeHint"; + case SpvExecutionModeContractionOff: return "SpvExecutionModeContractionOff"; + case SpvExecutionModeInitializer: return "SpvExecutionModeInitializer"; + case SpvExecutionModeFinalizer: return "SpvExecutionModeFinalizer"; + case SpvExecutionModeSubgroupSize: return "SpvExecutionModeSubgroupSize"; + case SpvExecutionModeSubgroupsPerWorkgroup: return "SpvExecutionModeSubgroupsPerWorkgroup"; + case SpvExecutionModeSubgroupsPerWorkgroupId: return "SpvExecutionModeSubgroupsPerWorkgroupId"; + case SpvExecutionModeLocalSizeId: return "SpvExecutionModeLocalSizeId"; + case SpvExecutionModeLocalSizeHintId: return "SpvExecutionModeLocalSizeHintId"; + case SpvExecutionModePostDepthCoverage: return "SpvExecutionModePostDepthCoverage"; + case SpvExecutionModeDenormPreserve: return "SpvExecutionModeDenormPreserve"; + case SpvExecutionModeDenormFlushToZero: return "SpvExecutionModeDenormFlushToZero"; + case SpvExecutionModeSignedZeroInfNanPreserve: return "SpvExecutionModeSignedZeroInfNanPreserve"; + case SpvExecutionModeRoundingModeRTE: return "SpvExecutionModeRoundingModeRTE"; + case SpvExecutionModeRoundingModeRTZ: return "SpvExecutionModeRoundingModeRTZ"; + case SpvExecutionModeStencilRefReplacingEXT: return "SpvExecutionModeStencilRefReplacingEXT"; + case SpvExecutionModeOutputLinesNV: return "SpvExecutionModeOutputLinesNV"; + case SpvExecutionModeOutputPrimitivesNV: return "SpvExecutionModeOutputPrimitivesNV"; + case SpvExecutionModeDerivativeGroupQuadsNV: return "SpvExecutionModeDerivativeGroupQuadsNV"; + case SpvExecutionModeDerivativeGroupLinearNV: return "SpvExecutionModeDerivativeGroupLinearNV"; + case SpvExecutionModeOutputTrianglesNV: return "SpvExecutionModeOutputTrianglesNV"; + case SpvExecutionModeMax: break; /* silence warnings about unhandled enums. */ + } + + return "unknown"; +} + +const char * +spirv_op_to_string(SpvOp v) +{ + switch (v) { + case SpvOpNop: return "SpvOpNop"; + case SpvOpUndef: return "SpvOpUndef"; + case SpvOpSourceContinued: return "SpvOpSourceContinued"; + case SpvOpSource: return "SpvOpSource"; + case SpvOpSourceExtension: return "SpvOpSourceExtension"; + case SpvOpName: return "SpvOpName"; + case SpvOpMemberName: return "SpvOpMemberName"; + case SpvOpString: return "SpvOpString"; + case SpvOpLine: return "SpvOpLine"; + case SpvOpExtension: return "SpvOpExtension"; + case SpvOpExtInstImport: return "SpvOpExtInstImport"; + case SpvOpExtInst: return "SpvOpExtInst"; + case SpvOpMemoryModel: return "SpvOpMemoryModel"; + case SpvOpEntryPoint: return "SpvOpEntryPoint"; + case SpvOpExecutionMode: return "SpvOpExecutionMode"; + case SpvOpCapability: return "SpvOpCapability"; + case SpvOpTypeVoid: return "SpvOpTypeVoid"; + case SpvOpTypeBool: return "SpvOpTypeBool"; + case SpvOpTypeInt: return "SpvOpTypeInt"; + case SpvOpTypeFloat: return "SpvOpTypeFloat"; + case SpvOpTypeVector: return "SpvOpTypeVector"; + case SpvOpTypeMatrix: return "SpvOpTypeMatrix"; + case SpvOpTypeImage: return "SpvOpTypeImage"; + case SpvOpTypeSampler: return "SpvOpTypeSampler"; + case SpvOpTypeSampledImage: return "SpvOpTypeSampledImage"; + case SpvOpTypeArray: return "SpvOpTypeArray"; + case SpvOpTypeRuntimeArray: return "SpvOpTypeRuntimeArray"; + case SpvOpTypeStruct: return "SpvOpTypeStruct"; + case SpvOpTypeOpaque: return "SpvOpTypeOpaque"; + case SpvOpTypePointer: return "SpvOpTypePointer"; + case SpvOpTypeFunction: return "SpvOpTypeFunction"; + case SpvOpTypeEvent: return "SpvOpTypeEvent"; + case SpvOpTypeDeviceEvent: return "SpvOpTypeDeviceEvent"; + case SpvOpTypeReserveId: return "SpvOpTypeReserveId"; + case SpvOpTypeQueue: return "SpvOpTypeQueue"; + case SpvOpTypePipe: return "SpvOpTypePipe"; + case SpvOpTypeForwardPointer: return "SpvOpTypeForwardPointer"; + case SpvOpConstantTrue: return "SpvOpConstantTrue"; + case SpvOpConstantFalse: return "SpvOpConstantFalse"; + case SpvOpConstant: return "SpvOpConstant"; + case SpvOpConstantComposite: return "SpvOpConstantComposite"; + case SpvOpConstantSampler: return "SpvOpConstantSampler"; + case SpvOpConstantNull: return "SpvOpConstantNull"; + case SpvOpSpecConstantTrue: return "SpvOpSpecConstantTrue"; + case SpvOpSpecConstantFalse: return "SpvOpSpecConstantFalse"; + case SpvOpSpecConstant: return "SpvOpSpecConstant"; + case SpvOpSpecConstantComposite: return "SpvOpSpecConstantComposite"; + case SpvOpSpecConstantOp: return "SpvOpSpecConstantOp"; + case SpvOpFunction: return "SpvOpFunction"; + case SpvOpFunctionParameter: return "SpvOpFunctionParameter"; + case SpvOpFunctionEnd: return "SpvOpFunctionEnd"; + case SpvOpFunctionCall: return "SpvOpFunctionCall"; + case SpvOpVariable: return "SpvOpVariable"; + case SpvOpImageTexelPointer: return "SpvOpImageTexelPointer"; + case SpvOpLoad: return "SpvOpLoad"; + case SpvOpStore: return "SpvOpStore"; + case SpvOpCopyMemory: return "SpvOpCopyMemory"; + case SpvOpCopyMemorySized: return "SpvOpCopyMemorySized"; + case SpvOpAccessChain: return "SpvOpAccessChain"; + case SpvOpInBoundsAccessChain: return "SpvOpInBoundsAccessChain"; + case SpvOpPtrAccessChain: return "SpvOpPtrAccessChain"; + case SpvOpArrayLength: return "SpvOpArrayLength"; + case SpvOpGenericPtrMemSemantics: return "SpvOpGenericPtrMemSemantics"; + case SpvOpInBoundsPtrAccessChain: return "SpvOpInBoundsPtrAccessChain"; + case SpvOpDecorate: return "SpvOpDecorate"; + case SpvOpMemberDecorate: return "SpvOpMemberDecorate"; + case SpvOpDecorationGroup: return "SpvOpDecorationGroup"; + case SpvOpGroupDecorate: return "SpvOpGroupDecorate"; + case SpvOpGroupMemberDecorate: return "SpvOpGroupMemberDecorate"; + case SpvOpVectorExtractDynamic: return "SpvOpVectorExtractDynamic"; + case SpvOpVectorInsertDynamic: return "SpvOpVectorInsertDynamic"; + case SpvOpVectorShuffle: return "SpvOpVectorShuffle"; + case SpvOpCompositeConstruct: return "SpvOpCompositeConstruct"; + case SpvOpCompositeExtract: return "SpvOpCompositeExtract"; + case SpvOpCompositeInsert: return "SpvOpCompositeInsert"; + case SpvOpCopyObject: return "SpvOpCopyObject"; + case SpvOpTranspose: return "SpvOpTranspose"; + case SpvOpSampledImage: return "SpvOpSampledImage"; + case SpvOpImageSampleImplicitLod: return "SpvOpImageSampleImplicitLod"; + case SpvOpImageSampleExplicitLod: return "SpvOpImageSampleExplicitLod"; + case SpvOpImageSampleDrefImplicitLod: return "SpvOpImageSampleDrefImplicitLod"; + case SpvOpImageSampleDrefExplicitLod: return "SpvOpImageSampleDrefExplicitLod"; + case SpvOpImageSampleProjImplicitLod: return "SpvOpImageSampleProjImplicitLod"; + case SpvOpImageSampleProjExplicitLod: return "SpvOpImageSampleProjExplicitLod"; + case SpvOpImageSampleProjDrefImplicitLod: return "SpvOpImageSampleProjDrefImplicitLod"; + case SpvOpImageSampleProjDrefExplicitLod: return "SpvOpImageSampleProjDrefExplicitLod"; + case SpvOpImageFetch: return "SpvOpImageFetch"; + case SpvOpImageGather: return "SpvOpImageGather"; + case SpvOpImageDrefGather: return "SpvOpImageDrefGather"; + case SpvOpImageRead: return "SpvOpImageRead"; + case SpvOpImageWrite: return "SpvOpImageWrite"; + case SpvOpImage: return "SpvOpImage"; + case SpvOpImageQueryFormat: return "SpvOpImageQueryFormat"; + case SpvOpImageQueryOrder: return "SpvOpImageQueryOrder"; + case SpvOpImageQuerySizeLod: return "SpvOpImageQuerySizeLod"; + case SpvOpImageQuerySize: return "SpvOpImageQuerySize"; + case SpvOpImageQueryLod: return "SpvOpImageQueryLod"; + case SpvOpImageQueryLevels: return "SpvOpImageQueryLevels"; + case SpvOpImageQuerySamples: return "SpvOpImageQuerySamples"; + case SpvOpConvertFToU: return "SpvOpConvertFToU"; + case SpvOpConvertFToS: return "SpvOpConvertFToS"; + case SpvOpConvertSToF: return "SpvOpConvertSToF"; + case SpvOpConvertUToF: return "SpvOpConvertUToF"; + case SpvOpUConvert: return "SpvOpUConvert"; + case SpvOpSConvert: return "SpvOpSConvert"; + case SpvOpFConvert: return "SpvOpFConvert"; + case SpvOpQuantizeToF16: return "SpvOpQuantizeToF16"; + case SpvOpConvertPtrToU: return "SpvOpConvertPtrToU"; + case SpvOpSatConvertSToU: return "SpvOpSatConvertSToU"; + case SpvOpSatConvertUToS: return "SpvOpSatConvertUToS"; + case SpvOpConvertUToPtr: return "SpvOpConvertUToPtr"; + case SpvOpPtrCastToGeneric: return "SpvOpPtrCastToGeneric"; + case SpvOpGenericCastToPtr: return "SpvOpGenericCastToPtr"; + case SpvOpGenericCastToPtrExplicit: return "SpvOpGenericCastToPtrExplicit"; + case SpvOpBitcast: return "SpvOpBitcast"; + case SpvOpSNegate: return "SpvOpSNegate"; + case SpvOpFNegate: return "SpvOpFNegate"; + case SpvOpIAdd: return "SpvOpIAdd"; + case SpvOpFAdd: return "SpvOpFAdd"; + case SpvOpISub: return "SpvOpISub"; + case SpvOpFSub: return "SpvOpFSub"; + case SpvOpIMul: return "SpvOpIMul"; + case SpvOpFMul: return "SpvOpFMul"; + case SpvOpUDiv: return "SpvOpUDiv"; + case SpvOpSDiv: return "SpvOpSDiv"; + case SpvOpFDiv: return "SpvOpFDiv"; + case SpvOpUMod: return "SpvOpUMod"; + case SpvOpSRem: return "SpvOpSRem"; + case SpvOpSMod: return "SpvOpSMod"; + case SpvOpFRem: return "SpvOpFRem"; + case SpvOpFMod: return "SpvOpFMod"; + case SpvOpVectorTimesScalar: return "SpvOpVectorTimesScalar"; + case SpvOpMatrixTimesScalar: return "SpvOpMatrixTimesScalar"; + case SpvOpVectorTimesMatrix: return "SpvOpVectorTimesMatrix"; + case SpvOpMatrixTimesVector: return "SpvOpMatrixTimesVector"; + case SpvOpMatrixTimesMatrix: return "SpvOpMatrixTimesMatrix"; + case SpvOpOuterProduct: return "SpvOpOuterProduct"; + case SpvOpDot: return "SpvOpDot"; + case SpvOpIAddCarry: return "SpvOpIAddCarry"; + case SpvOpISubBorrow: return "SpvOpISubBorrow"; + case SpvOpUMulExtended: return "SpvOpUMulExtended"; + case SpvOpSMulExtended: return "SpvOpSMulExtended"; + case SpvOpAny: return "SpvOpAny"; + case SpvOpAll: return "SpvOpAll"; + case SpvOpIsNan: return "SpvOpIsNan"; + case SpvOpIsInf: return "SpvOpIsInf"; + case SpvOpIsFinite: return "SpvOpIsFinite"; + case SpvOpIsNormal: return "SpvOpIsNormal"; + case SpvOpSignBitSet: return "SpvOpSignBitSet"; + case SpvOpLessOrGreater: return "SpvOpLessOrGreater"; + case SpvOpOrdered: return "SpvOpOrdered"; + case SpvOpUnordered: return "SpvOpUnordered"; + case SpvOpLogicalEqual: return "SpvOpLogicalEqual"; + case SpvOpLogicalNotEqual: return "SpvOpLogicalNotEqual"; + case SpvOpLogicalOr: return "SpvOpLogicalOr"; + case SpvOpLogicalAnd: return "SpvOpLogicalAnd"; + case SpvOpLogicalNot: return "SpvOpLogicalNot"; + case SpvOpSelect: return "SpvOpSelect"; + case SpvOpIEqual: return "SpvOpIEqual"; + case SpvOpINotEqual: return "SpvOpINotEqual"; + case SpvOpUGreaterThan: return "SpvOpUGreaterThan"; + case SpvOpSGreaterThan: return "SpvOpSGreaterThan"; + case SpvOpUGreaterThanEqual: return "SpvOpUGreaterThanEqual"; + case SpvOpSGreaterThanEqual: return "SpvOpSGreaterThanEqual"; + case SpvOpULessThan: return "SpvOpULessThan"; + case SpvOpSLessThan: return "SpvOpSLessThan"; + case SpvOpULessThanEqual: return "SpvOpULessThanEqual"; + case SpvOpSLessThanEqual: return "SpvOpSLessThanEqual"; + case SpvOpFOrdEqual: return "SpvOpFOrdEqual"; + case SpvOpFUnordEqual: return "SpvOpFUnordEqual"; + case SpvOpFOrdNotEqual: return "SpvOpFOrdNotEqual"; + case SpvOpFUnordNotEqual: return "SpvOpFUnordNotEqual"; + case SpvOpFOrdLessThan: return "SpvOpFOrdLessThan"; + case SpvOpFUnordLessThan: return "SpvOpFUnordLessThan"; + case SpvOpFOrdGreaterThan: return "SpvOpFOrdGreaterThan"; + case SpvOpFUnordGreaterThan: return "SpvOpFUnordGreaterThan"; + case SpvOpFOrdLessThanEqual: return "SpvOpFOrdLessThanEqual"; + case SpvOpFUnordLessThanEqual: return "SpvOpFUnordLessThanEqual"; + case SpvOpFOrdGreaterThanEqual: return "SpvOpFOrdGreaterThanEqual"; + case SpvOpFUnordGreaterThanEqual: return "SpvOpFUnordGreaterThanEqual"; + case SpvOpShiftRightLogical: return "SpvOpShiftRightLogical"; + case SpvOpShiftRightArithmetic: return "SpvOpShiftRightArithmetic"; + case SpvOpShiftLeftLogical: return "SpvOpShiftLeftLogical"; + case SpvOpBitwiseOr: return "SpvOpBitwiseOr"; + case SpvOpBitwiseXor: return "SpvOpBitwiseXor"; + case SpvOpBitwiseAnd: return "SpvOpBitwiseAnd"; + case SpvOpNot: return "SpvOpNot"; + case SpvOpBitFieldInsert: return "SpvOpBitFieldInsert"; + case SpvOpBitFieldSExtract: return "SpvOpBitFieldSExtract"; + case SpvOpBitFieldUExtract: return "SpvOpBitFieldUExtract"; + case SpvOpBitReverse: return "SpvOpBitReverse"; + case SpvOpBitCount: return "SpvOpBitCount"; + case SpvOpDPdx: return "SpvOpDPdx"; + case SpvOpDPdy: return "SpvOpDPdy"; + case SpvOpFwidth: return "SpvOpFwidth"; + case SpvOpDPdxFine: return "SpvOpDPdxFine"; + case SpvOpDPdyFine: return "SpvOpDPdyFine"; + case SpvOpFwidthFine: return "SpvOpFwidthFine"; + case SpvOpDPdxCoarse: return "SpvOpDPdxCoarse"; + case SpvOpDPdyCoarse: return "SpvOpDPdyCoarse"; + case SpvOpFwidthCoarse: return "SpvOpFwidthCoarse"; + case SpvOpEmitVertex: return "SpvOpEmitVertex"; + case SpvOpEndPrimitive: return "SpvOpEndPrimitive"; + case SpvOpEmitStreamVertex: return "SpvOpEmitStreamVertex"; + case SpvOpEndStreamPrimitive: return "SpvOpEndStreamPrimitive"; + case SpvOpControlBarrier: return "SpvOpControlBarrier"; + case SpvOpMemoryBarrier: return "SpvOpMemoryBarrier"; + case SpvOpAtomicLoad: return "SpvOpAtomicLoad"; + case SpvOpAtomicStore: return "SpvOpAtomicStore"; + case SpvOpAtomicExchange: return "SpvOpAtomicExchange"; + case SpvOpAtomicCompareExchange: return "SpvOpAtomicCompareExchange"; + case SpvOpAtomicCompareExchangeWeak: return "SpvOpAtomicCompareExchangeWeak"; + case SpvOpAtomicIIncrement: return "SpvOpAtomicIIncrement"; + case SpvOpAtomicIDecrement: return "SpvOpAtomicIDecrement"; + case SpvOpAtomicIAdd: return "SpvOpAtomicIAdd"; + case SpvOpAtomicISub: return "SpvOpAtomicISub"; + case SpvOpAtomicSMin: return "SpvOpAtomicSMin"; + case SpvOpAtomicUMin: return "SpvOpAtomicUMin"; + case SpvOpAtomicSMax: return "SpvOpAtomicSMax"; + case SpvOpAtomicUMax: return "SpvOpAtomicUMax"; + case SpvOpAtomicAnd: return "SpvOpAtomicAnd"; + case SpvOpAtomicOr: return "SpvOpAtomicOr"; + case SpvOpAtomicXor: return "SpvOpAtomicXor"; + case SpvOpPhi: return "SpvOpPhi"; + case SpvOpLoopMerge: return "SpvOpLoopMerge"; + case SpvOpSelectionMerge: return "SpvOpSelectionMerge"; + case SpvOpLabel: return "SpvOpLabel"; + case SpvOpBranch: return "SpvOpBranch"; + case SpvOpBranchConditional: return "SpvOpBranchConditional"; + case SpvOpSwitch: return "SpvOpSwitch"; + case SpvOpKill: return "SpvOpKill"; + case SpvOpReturn: return "SpvOpReturn"; + case SpvOpReturnValue: return "SpvOpReturnValue"; + case SpvOpUnreachable: return "SpvOpUnreachable"; + case SpvOpLifetimeStart: return "SpvOpLifetimeStart"; + case SpvOpLifetimeStop: return "SpvOpLifetimeStop"; + case SpvOpGroupAsyncCopy: return "SpvOpGroupAsyncCopy"; + case SpvOpGroupWaitEvents: return "SpvOpGroupWaitEvents"; + case SpvOpGroupAll: return "SpvOpGroupAll"; + case SpvOpGroupAny: return "SpvOpGroupAny"; + case SpvOpGroupBroadcast: return "SpvOpGroupBroadcast"; + case SpvOpGroupIAdd: return "SpvOpGroupIAdd"; + case SpvOpGroupFAdd: return "SpvOpGroupFAdd"; + case SpvOpGroupFMin: return "SpvOpGroupFMin"; + case SpvOpGroupUMin: return "SpvOpGroupUMin"; + case SpvOpGroupSMin: return "SpvOpGroupSMin"; + case SpvOpGroupFMax: return "SpvOpGroupFMax"; + case SpvOpGroupUMax: return "SpvOpGroupUMax"; + case SpvOpGroupSMax: return "SpvOpGroupSMax"; + case SpvOpReadPipe: return "SpvOpReadPipe"; + case SpvOpWritePipe: return "SpvOpWritePipe"; + case SpvOpReservedReadPipe: return "SpvOpReservedReadPipe"; + case SpvOpReservedWritePipe: return "SpvOpReservedWritePipe"; + case SpvOpReserveReadPipePackets: return "SpvOpReserveReadPipePackets"; + case SpvOpReserveWritePipePackets: return "SpvOpReserveWritePipePackets"; + case SpvOpCommitReadPipe: return "SpvOpCommitReadPipe"; + case SpvOpCommitWritePipe: return "SpvOpCommitWritePipe"; + case SpvOpIsValidReserveId: return "SpvOpIsValidReserveId"; + case SpvOpGetNumPipePackets: return "SpvOpGetNumPipePackets"; + case SpvOpGetMaxPipePackets: return "SpvOpGetMaxPipePackets"; + case SpvOpGroupReserveReadPipePackets: return "SpvOpGroupReserveReadPipePackets"; + case SpvOpGroupReserveWritePipePackets: return "SpvOpGroupReserveWritePipePackets"; + case SpvOpGroupCommitReadPipe: return "SpvOpGroupCommitReadPipe"; + case SpvOpGroupCommitWritePipe: return "SpvOpGroupCommitWritePipe"; + case SpvOpEnqueueMarker: return "SpvOpEnqueueMarker"; + case SpvOpEnqueueKernel: return "SpvOpEnqueueKernel"; + case SpvOpGetKernelNDrangeSubGroupCount: return "SpvOpGetKernelNDrangeSubGroupCount"; + case SpvOpGetKernelNDrangeMaxSubGroupSize: return "SpvOpGetKernelNDrangeMaxSubGroupSize"; + case SpvOpGetKernelWorkGroupSize: return "SpvOpGetKernelWorkGroupSize"; + case SpvOpGetKernelPreferredWorkGroupSizeMultiple: return "SpvOpGetKernelPreferredWorkGroupSizeMultiple"; + case SpvOpRetainEvent: return "SpvOpRetainEvent"; + case SpvOpReleaseEvent: return "SpvOpReleaseEvent"; + case SpvOpCreateUserEvent: return "SpvOpCreateUserEvent"; + case SpvOpIsValidEvent: return "SpvOpIsValidEvent"; + case SpvOpSetUserEventStatus: return "SpvOpSetUserEventStatus"; + case SpvOpCaptureEventProfilingInfo: return "SpvOpCaptureEventProfilingInfo"; + case SpvOpGetDefaultQueue: return "SpvOpGetDefaultQueue"; + case SpvOpBuildNDRange: return "SpvOpBuildNDRange"; + case SpvOpImageSparseSampleImplicitLod: return "SpvOpImageSparseSampleImplicitLod"; + case SpvOpImageSparseSampleExplicitLod: return "SpvOpImageSparseSampleExplicitLod"; + case SpvOpImageSparseSampleDrefImplicitLod: return "SpvOpImageSparseSampleDrefImplicitLod"; + case SpvOpImageSparseSampleDrefExplicitLod: return "SpvOpImageSparseSampleDrefExplicitLod"; + case SpvOpImageSparseSampleProjImplicitLod: return "SpvOpImageSparseSampleProjImplicitLod"; + case SpvOpImageSparseSampleProjExplicitLod: return "SpvOpImageSparseSampleProjExplicitLod"; + case SpvOpImageSparseSampleProjDrefImplicitLod: return "SpvOpImageSparseSampleProjDrefImplicitLod"; + case SpvOpImageSparseSampleProjDrefExplicitLod: return "SpvOpImageSparseSampleProjDrefExplicitLod"; + case SpvOpImageSparseFetch: return "SpvOpImageSparseFetch"; + case SpvOpImageSparseGather: return "SpvOpImageSparseGather"; + case SpvOpImageSparseDrefGather: return "SpvOpImageSparseDrefGather"; + case SpvOpImageSparseTexelsResident: return "SpvOpImageSparseTexelsResident"; + case SpvOpNoLine: return "SpvOpNoLine"; + case SpvOpAtomicFlagTestAndSet: return "SpvOpAtomicFlagTestAndSet"; + case SpvOpAtomicFlagClear: return "SpvOpAtomicFlagClear"; + case SpvOpImageSparseRead: return "SpvOpImageSparseRead"; + case SpvOpSizeOf: return "SpvOpSizeOf"; + case SpvOpTypePipeStorage: return "SpvOpTypePipeStorage"; + case SpvOpConstantPipeStorage: return "SpvOpConstantPipeStorage"; + case SpvOpCreatePipeFromPipeStorage: return "SpvOpCreatePipeFromPipeStorage"; + case SpvOpGetKernelLocalSizeForSubgroupCount: return "SpvOpGetKernelLocalSizeForSubgroupCount"; + case SpvOpGetKernelMaxNumSubgroups: return "SpvOpGetKernelMaxNumSubgroups"; + case SpvOpTypeNamedBarrier: return "SpvOpTypeNamedBarrier"; + case SpvOpNamedBarrierInitialize: return "SpvOpNamedBarrierInitialize"; + case SpvOpMemoryNamedBarrier: return "SpvOpMemoryNamedBarrier"; + case SpvOpModuleProcessed: return "SpvOpModuleProcessed"; + case SpvOpExecutionModeId: return "SpvOpExecutionModeId"; + case SpvOpDecorateId: return "SpvOpDecorateId"; + case SpvOpGroupNonUniformElect: return "SpvOpGroupNonUniformElect"; + case SpvOpGroupNonUniformAll: return "SpvOpGroupNonUniformAll"; + case SpvOpGroupNonUniformAny: return "SpvOpGroupNonUniformAny"; + case SpvOpGroupNonUniformAllEqual: return "SpvOpGroupNonUniformAllEqual"; + case SpvOpGroupNonUniformBroadcast: return "SpvOpGroupNonUniformBroadcast"; + case SpvOpGroupNonUniformBroadcastFirst: return "SpvOpGroupNonUniformBroadcastFirst"; + case SpvOpGroupNonUniformBallot: return "SpvOpGroupNonUniformBallot"; + case SpvOpGroupNonUniformInverseBallot: return "SpvOpGroupNonUniformInverseBallot"; + case SpvOpGroupNonUniformBallotBitExtract: return "SpvOpGroupNonUniformBallotBitExtract"; + case SpvOpGroupNonUniformBallotBitCount: return "SpvOpGroupNonUniformBallotBitCount"; + case SpvOpGroupNonUniformBallotFindLSB: return "SpvOpGroupNonUniformBallotFindLSB"; + case SpvOpGroupNonUniformBallotFindMSB: return "SpvOpGroupNonUniformBallotFindMSB"; + case SpvOpGroupNonUniformShuffle: return "SpvOpGroupNonUniformShuffle"; + case SpvOpGroupNonUniformShuffleXor: return "SpvOpGroupNonUniformShuffleXor"; + case SpvOpGroupNonUniformShuffleUp: return "SpvOpGroupNonUniformShuffleUp"; + case SpvOpGroupNonUniformShuffleDown: return "SpvOpGroupNonUniformShuffleDown"; + case SpvOpGroupNonUniformIAdd: return "SpvOpGroupNonUniformIAdd"; + case SpvOpGroupNonUniformFAdd: return "SpvOpGroupNonUniformFAdd"; + case SpvOpGroupNonUniformIMul: return "SpvOpGroupNonUniformIMul"; + case SpvOpGroupNonUniformFMul: return "SpvOpGroupNonUniformFMul"; + case SpvOpGroupNonUniformSMin: return "SpvOpGroupNonUniformSMin"; + case SpvOpGroupNonUniformUMin: return "SpvOpGroupNonUniformUMin"; + case SpvOpGroupNonUniformFMin: return "SpvOpGroupNonUniformFMin"; + case SpvOpGroupNonUniformSMax: return "SpvOpGroupNonUniformSMax"; + case SpvOpGroupNonUniformUMax: return "SpvOpGroupNonUniformUMax"; + case SpvOpGroupNonUniformFMax: return "SpvOpGroupNonUniformFMax"; + case SpvOpGroupNonUniformBitwiseAnd: return "SpvOpGroupNonUniformBitwiseAnd"; + case SpvOpGroupNonUniformBitwiseOr: return "SpvOpGroupNonUniformBitwiseOr"; + case SpvOpGroupNonUniformBitwiseXor: return "SpvOpGroupNonUniformBitwiseXor"; + case SpvOpGroupNonUniformLogicalAnd: return "SpvOpGroupNonUniformLogicalAnd"; + case SpvOpGroupNonUniformLogicalOr: return "SpvOpGroupNonUniformLogicalOr"; + case SpvOpGroupNonUniformLogicalXor: return "SpvOpGroupNonUniformLogicalXor"; + case SpvOpGroupNonUniformQuadBroadcast: return "SpvOpGroupNonUniformQuadBroadcast"; + case SpvOpGroupNonUniformQuadSwap: return "SpvOpGroupNonUniformQuadSwap"; + case SpvOpSubgroupBallotKHR: return "SpvOpSubgroupBallotKHR"; + case SpvOpSubgroupFirstInvocationKHR: return "SpvOpSubgroupFirstInvocationKHR"; + case SpvOpSubgroupAllKHR: return "SpvOpSubgroupAllKHR"; + case SpvOpSubgroupAnyKHR: return "SpvOpSubgroupAnyKHR"; + case SpvOpSubgroupAllEqualKHR: return "SpvOpSubgroupAllEqualKHR"; + case SpvOpSubgroupReadInvocationKHR: return "SpvOpSubgroupReadInvocationKHR"; + case SpvOpGroupIAddNonUniformAMD: return "SpvOpGroupIAddNonUniformAMD"; + case SpvOpGroupFAddNonUniformAMD: return "SpvOpGroupFAddNonUniformAMD"; + case SpvOpGroupFMinNonUniformAMD: return "SpvOpGroupFMinNonUniformAMD"; + case SpvOpGroupUMinNonUniformAMD: return "SpvOpGroupUMinNonUniformAMD"; + case SpvOpGroupSMinNonUniformAMD: return "SpvOpGroupSMinNonUniformAMD"; + case SpvOpGroupFMaxNonUniformAMD: return "SpvOpGroupFMaxNonUniformAMD"; + case SpvOpGroupUMaxNonUniformAMD: return "SpvOpGroupUMaxNonUniformAMD"; + case SpvOpGroupSMaxNonUniformAMD: return "SpvOpGroupSMaxNonUniformAMD"; + case SpvOpFragmentMaskFetchAMD: return "SpvOpFragmentMaskFetchAMD"; + case SpvOpFragmentFetchAMD: return "SpvOpFragmentFetchAMD"; + case SpvOpWritePackedPrimitiveIndices4x8NV: return "SpvOpWritePackedPrimitiveIndices4x8NV"; + case SpvOpReportIntersectionNV: return "SpvOpReportIntersectionNV"; + case SpvOpIgnoreIntersectionNV: return "SpvOpIgnoreIntersectionNV"; + case SpvOpTerminateRayNV: return "SpvOpTerminateRayNV"; + case SpvOpTraceNV: return "SpvOpTraceNV"; + case SpvOpTypeAccelerationStructureNV: return "SpvOpTypeAccelerationStructureNV"; + case SpvOpExecuteCallableNV: return "SpvOpExecuteCallableNV"; + case SpvOpSubgroupShuffleINTEL: return "SpvOpSubgroupShuffleINTEL"; + case SpvOpSubgroupShuffleDownINTEL: return "SpvOpSubgroupShuffleDownINTEL"; + case SpvOpSubgroupShuffleUpINTEL: return "SpvOpSubgroupShuffleUpINTEL"; + case SpvOpSubgroupShuffleXorINTEL: return "SpvOpSubgroupShuffleXorINTEL"; + case SpvOpSubgroupBlockReadINTEL: return "SpvOpSubgroupBlockReadINTEL"; + case SpvOpSubgroupBlockWriteINTEL: return "SpvOpSubgroupBlockWriteINTEL"; + case SpvOpSubgroupImageBlockReadINTEL: return "SpvOpSubgroupImageBlockReadINTEL"; + case SpvOpSubgroupImageBlockWriteINTEL: return "SpvOpSubgroupImageBlockWriteINTEL"; + case SpvOpDecorateStringGOOGLE: return "SpvOpDecorateStringGOOGLE"; + case SpvOpMemberDecorateStringGOOGLE: return "SpvOpMemberDecorateStringGOOGLE"; + case SpvOpGroupNonUniformPartitionNV: return "SpvOpGroupNonUniformPartitionNV"; + case SpvOpImageSampleFootprintNV: return "SpvOpImageSampleFootprintNV"; + case SpvOpMax: break; /* silence warnings about unhandled enums. */ + } + + return "unknown"; +} diff --git a/prebuilt-intermediates/spirv/vtn_gather_types.c b/prebuilt-intermediates/spirv/vtn_gather_types.c new file mode 100644 index 00000000000..764bcf768f0 --- /dev/null +++ b/prebuilt-intermediates/spirv/vtn_gather_types.c @@ -0,0 +1,368 @@ +/* + * Copyright (C) 2017 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER + * DEALINGS IN THE SOFTWARE. + */ + +/* DO NOT EDIT - This file is generated automatically by the + * vtn_gather_types_c.py script + */ + +#include "vtn_private.h" + +struct type_args { + int res_idx; + int res_type_idx; +}; + +static struct type_args +result_type_args_for_opcode(SpvOp opcode) +{ + switch (opcode) { + case SpvOpUndef: return (struct type_args){ 1, 0 }; + case SpvOpString: return (struct type_args){ 0, -1 }; + case SpvOpExtInstImport: return (struct type_args){ 0, -1 }; + case SpvOpExtInst: return (struct type_args){ 1, 0 }; + case SpvOpTypeVoid: return (struct type_args){ 0, -1 }; + case SpvOpTypeBool: return (struct type_args){ 0, -1 }; + case SpvOpTypeInt: return (struct type_args){ 0, -1 }; + case SpvOpTypeFloat: return (struct type_args){ 0, -1 }; + case SpvOpTypeVector: return (struct type_args){ 0, -1 }; + case SpvOpTypeMatrix: return (struct type_args){ 0, -1 }; + case SpvOpTypeImage: return (struct type_args){ 0, -1 }; + case SpvOpTypeSampler: return (struct type_args){ 0, -1 }; + case SpvOpTypeSampledImage: return (struct type_args){ 0, -1 }; + case SpvOpTypeArray: return (struct type_args){ 0, -1 }; + case SpvOpTypeRuntimeArray: return (struct type_args){ 0, -1 }; + case SpvOpTypeStruct: return (struct type_args){ 0, -1 }; + case SpvOpTypeOpaque: return (struct type_args){ 0, -1 }; + case SpvOpTypePointer: return (struct type_args){ 0, -1 }; + case SpvOpTypeFunction: return (struct type_args){ 0, -1 }; + case SpvOpTypeEvent: return (struct type_args){ 0, -1 }; + case SpvOpTypeDeviceEvent: return (struct type_args){ 0, -1 }; + case SpvOpTypeReserveId: return (struct type_args){ 0, -1 }; + case SpvOpTypeQueue: return (struct type_args){ 0, -1 }; + case SpvOpTypePipe: return (struct type_args){ 0, -1 }; + case SpvOpConstantTrue: return (struct type_args){ 1, 0 }; + case SpvOpConstantFalse: return (struct type_args){ 1, 0 }; + case SpvOpConstant: return (struct type_args){ 1, 0 }; + case SpvOpConstantComposite: return (struct type_args){ 1, 0 }; + case SpvOpConstantSampler: return (struct type_args){ 1, 0 }; + case SpvOpConstantNull: return (struct type_args){ 1, 0 }; + case SpvOpSpecConstantTrue: return (struct type_args){ 1, 0 }; + case SpvOpSpecConstantFalse: return (struct type_args){ 1, 0 }; + case SpvOpSpecConstant: return (struct type_args){ 1, 0 }; + case SpvOpSpecConstantComposite: return (struct type_args){ 1, 0 }; + case SpvOpSpecConstantOp: return (struct type_args){ 1, 0 }; + case SpvOpFunction: return (struct type_args){ 1, 0 }; + case SpvOpFunctionParameter: return (struct type_args){ 1, 0 }; + case SpvOpFunctionCall: return (struct type_args){ 1, 0 }; + case SpvOpVariable: return (struct type_args){ 1, 0 }; + case SpvOpImageTexelPointer: return (struct type_args){ 1, 0 }; + case SpvOpLoad: return (struct type_args){ 1, 0 }; + case SpvOpAccessChain: return (struct type_args){ 1, 0 }; + case SpvOpInBoundsAccessChain: return (struct type_args){ 1, 0 }; + case SpvOpPtrAccessChain: return (struct type_args){ 1, 0 }; + case SpvOpArrayLength: return (struct type_args){ 1, 0 }; + case SpvOpGenericPtrMemSemantics: return (struct type_args){ 1, 0 }; + case SpvOpInBoundsPtrAccessChain: return (struct type_args){ 1, 0 }; + case SpvOpDecorationGroup: return (struct type_args){ 0, -1 }; + case SpvOpVectorExtractDynamic: return (struct type_args){ 1, 0 }; + case SpvOpVectorInsertDynamic: return (struct type_args){ 1, 0 }; + case SpvOpVectorShuffle: return (struct type_args){ 1, 0 }; + case SpvOpCompositeConstruct: return (struct type_args){ 1, 0 }; + case SpvOpCompositeExtract: return (struct type_args){ 1, 0 }; + case SpvOpCompositeInsert: return (struct type_args){ 1, 0 }; + case SpvOpCopyObject: return (struct type_args){ 1, 0 }; + case SpvOpTranspose: return (struct type_args){ 1, 0 }; + case SpvOpSampledImage: return (struct type_args){ 1, 0 }; + case SpvOpImageSampleImplicitLod: return (struct type_args){ 1, 0 }; + case SpvOpImageSampleExplicitLod: return (struct type_args){ 1, 0 }; + case SpvOpImageSampleDrefImplicitLod: return (struct type_args){ 1, 0 }; + case SpvOpImageSampleDrefExplicitLod: return (struct type_args){ 1, 0 }; + case SpvOpImageSampleProjImplicitLod: return (struct type_args){ 1, 0 }; + case SpvOpImageSampleProjExplicitLod: return (struct type_args){ 1, 0 }; + case SpvOpImageSampleProjDrefImplicitLod: return (struct type_args){ 1, 0 }; + case SpvOpImageSampleProjDrefExplicitLod: return (struct type_args){ 1, 0 }; + case SpvOpImageFetch: return (struct type_args){ 1, 0 }; + case SpvOpImageGather: return (struct type_args){ 1, 0 }; + case SpvOpImageDrefGather: return (struct type_args){ 1, 0 }; + case SpvOpImageRead: return (struct type_args){ 1, 0 }; + case SpvOpImage: return (struct type_args){ 1, 0 }; + case SpvOpImageQueryFormat: return (struct type_args){ 1, 0 }; + case SpvOpImageQueryOrder: return (struct type_args){ 1, 0 }; + case SpvOpImageQuerySizeLod: return (struct type_args){ 1, 0 }; + case SpvOpImageQuerySize: return (struct type_args){ 1, 0 }; + case SpvOpImageQueryLod: return (struct type_args){ 1, 0 }; + case SpvOpImageQueryLevels: return (struct type_args){ 1, 0 }; + case SpvOpImageQuerySamples: return (struct type_args){ 1, 0 }; + case SpvOpConvertFToU: return (struct type_args){ 1, 0 }; + case SpvOpConvertFToS: return (struct type_args){ 1, 0 }; + case SpvOpConvertSToF: return (struct type_args){ 1, 0 }; + case SpvOpConvertUToF: return (struct type_args){ 1, 0 }; + case SpvOpUConvert: return (struct type_args){ 1, 0 }; + case SpvOpSConvert: return (struct type_args){ 1, 0 }; + case SpvOpFConvert: return (struct type_args){ 1, 0 }; + case SpvOpQuantizeToF16: return (struct type_args){ 1, 0 }; + case SpvOpConvertPtrToU: return (struct type_args){ 1, 0 }; + case SpvOpSatConvertSToU: return (struct type_args){ 1, 0 }; + case SpvOpSatConvertUToS: return (struct type_args){ 1, 0 }; + case SpvOpConvertUToPtr: return (struct type_args){ 1, 0 }; + case SpvOpPtrCastToGeneric: return (struct type_args){ 1, 0 }; + case SpvOpGenericCastToPtr: return (struct type_args){ 1, 0 }; + case SpvOpGenericCastToPtrExplicit: return (struct type_args){ 1, 0 }; + case SpvOpBitcast: return (struct type_args){ 1, 0 }; + case SpvOpSNegate: return (struct type_args){ 1, 0 }; + case SpvOpFNegate: return (struct type_args){ 1, 0 }; + case SpvOpIAdd: return (struct type_args){ 1, 0 }; + case SpvOpFAdd: return (struct type_args){ 1, 0 }; + case SpvOpISub: return (struct type_args){ 1, 0 }; + case SpvOpFSub: return (struct type_args){ 1, 0 }; + case SpvOpIMul: return (struct type_args){ 1, 0 }; + case SpvOpFMul: return (struct type_args){ 1, 0 }; + case SpvOpUDiv: return (struct type_args){ 1, 0 }; + case SpvOpSDiv: return (struct type_args){ 1, 0 }; + case SpvOpFDiv: return (struct type_args){ 1, 0 }; + case SpvOpUMod: return (struct type_args){ 1, 0 }; + case SpvOpSRem: return (struct type_args){ 1, 0 }; + case SpvOpSMod: return (struct type_args){ 1, 0 }; + case SpvOpFRem: return (struct type_args){ 1, 0 }; + case SpvOpFMod: return (struct type_args){ 1, 0 }; + case SpvOpVectorTimesScalar: return (struct type_args){ 1, 0 }; + case SpvOpMatrixTimesScalar: return (struct type_args){ 1, 0 }; + case SpvOpVectorTimesMatrix: return (struct type_args){ 1, 0 }; + case SpvOpMatrixTimesVector: return (struct type_args){ 1, 0 }; + case SpvOpMatrixTimesMatrix: return (struct type_args){ 1, 0 }; + case SpvOpOuterProduct: return (struct type_args){ 1, 0 }; + case SpvOpDot: return (struct type_args){ 1, 0 }; + case SpvOpIAddCarry: return (struct type_args){ 1, 0 }; + case SpvOpISubBorrow: return (struct type_args){ 1, 0 }; + case SpvOpUMulExtended: return (struct type_args){ 1, 0 }; + case SpvOpSMulExtended: return (struct type_args){ 1, 0 }; + case SpvOpAny: return (struct type_args){ 1, 0 }; + case SpvOpAll: return (struct type_args){ 1, 0 }; + case SpvOpIsNan: return (struct type_args){ 1, 0 }; + case SpvOpIsInf: return (struct type_args){ 1, 0 }; + case SpvOpIsFinite: return (struct type_args){ 1, 0 }; + case SpvOpIsNormal: return (struct type_args){ 1, 0 }; + case SpvOpSignBitSet: return (struct type_args){ 1, 0 }; + case SpvOpLessOrGreater: return (struct type_args){ 1, 0 }; + case SpvOpOrdered: return (struct type_args){ 1, 0 }; + case SpvOpUnordered: return (struct type_args){ 1, 0 }; + case SpvOpLogicalEqual: return (struct type_args){ 1, 0 }; + case SpvOpLogicalNotEqual: return (struct type_args){ 1, 0 }; + case SpvOpLogicalOr: return (struct type_args){ 1, 0 }; + case SpvOpLogicalAnd: return (struct type_args){ 1, 0 }; + case SpvOpLogicalNot: return (struct type_args){ 1, 0 }; + case SpvOpSelect: return (struct type_args){ 1, 0 }; + case SpvOpIEqual: return (struct type_args){ 1, 0 }; + case SpvOpINotEqual: return (struct type_args){ 1, 0 }; + case SpvOpUGreaterThan: return (struct type_args){ 1, 0 }; + case SpvOpSGreaterThan: return (struct type_args){ 1, 0 }; + case SpvOpUGreaterThanEqual: return (struct type_args){ 1, 0 }; + case SpvOpSGreaterThanEqual: return (struct type_args){ 1, 0 }; + case SpvOpULessThan: return (struct type_args){ 1, 0 }; + case SpvOpSLessThan: return (struct type_args){ 1, 0 }; + case SpvOpULessThanEqual: return (struct type_args){ 1, 0 }; + case SpvOpSLessThanEqual: return (struct type_args){ 1, 0 }; + case SpvOpFOrdEqual: return (struct type_args){ 1, 0 }; + case SpvOpFUnordEqual: return (struct type_args){ 1, 0 }; + case SpvOpFOrdNotEqual: return (struct type_args){ 1, 0 }; + case SpvOpFUnordNotEqual: return (struct type_args){ 1, 0 }; + case SpvOpFOrdLessThan: return (struct type_args){ 1, 0 }; + case SpvOpFUnordLessThan: return (struct type_args){ 1, 0 }; + case SpvOpFOrdGreaterThan: return (struct type_args){ 1, 0 }; + case SpvOpFUnordGreaterThan: return (struct type_args){ 1, 0 }; + case SpvOpFOrdLessThanEqual: return (struct type_args){ 1, 0 }; + case SpvOpFUnordLessThanEqual: return (struct type_args){ 1, 0 }; + case SpvOpFOrdGreaterThanEqual: return (struct type_args){ 1, 0 }; + case SpvOpFUnordGreaterThanEqual: return (struct type_args){ 1, 0 }; + case SpvOpShiftRightLogical: return (struct type_args){ 1, 0 }; + case SpvOpShiftRightArithmetic: return (struct type_args){ 1, 0 }; + case SpvOpShiftLeftLogical: return (struct type_args){ 1, 0 }; + case SpvOpBitwiseOr: return (struct type_args){ 1, 0 }; + case SpvOpBitwiseXor: return (struct type_args){ 1, 0 }; + case SpvOpBitwiseAnd: return (struct type_args){ 1, 0 }; + case SpvOpNot: return (struct type_args){ 1, 0 }; + case SpvOpBitFieldInsert: return (struct type_args){ 1, 0 }; + case SpvOpBitFieldSExtract: return (struct type_args){ 1, 0 }; + case SpvOpBitFieldUExtract: return (struct type_args){ 1, 0 }; + case SpvOpBitReverse: return (struct type_args){ 1, 0 }; + case SpvOpBitCount: return (struct type_args){ 1, 0 }; + case SpvOpDPdx: return (struct type_args){ 1, 0 }; + case SpvOpDPdy: return (struct type_args){ 1, 0 }; + case SpvOpFwidth: return (struct type_args){ 1, 0 }; + case SpvOpDPdxFine: return (struct type_args){ 1, 0 }; + case SpvOpDPdyFine: return (struct type_args){ 1, 0 }; + case SpvOpFwidthFine: return (struct type_args){ 1, 0 }; + case SpvOpDPdxCoarse: return (struct type_args){ 1, 0 }; + case SpvOpDPdyCoarse: return (struct type_args){ 1, 0 }; + case SpvOpFwidthCoarse: return (struct type_args){ 1, 0 }; + case SpvOpAtomicLoad: return (struct type_args){ 1, 0 }; + case SpvOpAtomicExchange: return (struct type_args){ 1, 0 }; + case SpvOpAtomicCompareExchange: return (struct type_args){ 1, 0 }; + case SpvOpAtomicCompareExchangeWeak: return (struct type_args){ 1, 0 }; + case SpvOpAtomicIIncrement: return (struct type_args){ 1, 0 }; + case SpvOpAtomicIDecrement: return (struct type_args){ 1, 0 }; + case SpvOpAtomicIAdd: return (struct type_args){ 1, 0 }; + case SpvOpAtomicISub: return (struct type_args){ 1, 0 }; + case SpvOpAtomicSMin: return (struct type_args){ 1, 0 }; + case SpvOpAtomicUMin: return (struct type_args){ 1, 0 }; + case SpvOpAtomicSMax: return (struct type_args){ 1, 0 }; + case SpvOpAtomicUMax: return (struct type_args){ 1, 0 }; + case SpvOpAtomicAnd: return (struct type_args){ 1, 0 }; + case SpvOpAtomicOr: return (struct type_args){ 1, 0 }; + case SpvOpAtomicXor: return (struct type_args){ 1, 0 }; + case SpvOpPhi: return (struct type_args){ 1, 0 }; + case SpvOpLabel: return (struct type_args){ 0, -1 }; + case SpvOpGroupAsyncCopy: return (struct type_args){ 1, 0 }; + case SpvOpGroupAll: return (struct type_args){ 1, 0 }; + case SpvOpGroupAny: return (struct type_args){ 1, 0 }; + case SpvOpGroupBroadcast: return (struct type_args){ 1, 0 }; + case SpvOpGroupIAdd: return (struct type_args){ 1, 0 }; + case SpvOpGroupFAdd: return (struct type_args){ 1, 0 }; + case SpvOpGroupFMin: return (struct type_args){ 1, 0 }; + case SpvOpGroupUMin: return (struct type_args){ 1, 0 }; + case SpvOpGroupSMin: return (struct type_args){ 1, 0 }; + case SpvOpGroupFMax: return (struct type_args){ 1, 0 }; + case SpvOpGroupUMax: return (struct type_args){ 1, 0 }; + case SpvOpGroupSMax: return (struct type_args){ 1, 0 }; + case SpvOpReadPipe: return (struct type_args){ 1, 0 }; + case SpvOpWritePipe: return (struct type_args){ 1, 0 }; + case SpvOpReservedReadPipe: return (struct type_args){ 1, 0 }; + case SpvOpReservedWritePipe: return (struct type_args){ 1, 0 }; + case SpvOpReserveReadPipePackets: return (struct type_args){ 1, 0 }; + case SpvOpReserveWritePipePackets: return (struct type_args){ 1, 0 }; + case SpvOpIsValidReserveId: return (struct type_args){ 1, 0 }; + case SpvOpGetNumPipePackets: return (struct type_args){ 1, 0 }; + case SpvOpGetMaxPipePackets: return (struct type_args){ 1, 0 }; + case SpvOpGroupReserveReadPipePackets: return (struct type_args){ 1, 0 }; + case SpvOpGroupReserveWritePipePackets: return (struct type_args){ 1, 0 }; + case SpvOpEnqueueMarker: return (struct type_args){ 1, 0 }; + case SpvOpEnqueueKernel: return (struct type_args){ 1, 0 }; + case SpvOpGetKernelNDrangeSubGroupCount: return (struct type_args){ 1, 0 }; + case SpvOpGetKernelNDrangeMaxSubGroupSize: return (struct type_args){ 1, 0 }; + case SpvOpGetKernelWorkGroupSize: return (struct type_args){ 1, 0 }; + case SpvOpGetKernelPreferredWorkGroupSizeMultiple: return (struct type_args){ 1, 0 }; + case SpvOpCreateUserEvent: return (struct type_args){ 1, 0 }; + case SpvOpIsValidEvent: return (struct type_args){ 1, 0 }; + case SpvOpGetDefaultQueue: return (struct type_args){ 1, 0 }; + case SpvOpBuildNDRange: return (struct type_args){ 1, 0 }; + case SpvOpImageSparseSampleImplicitLod: return (struct type_args){ 1, 0 }; + case SpvOpImageSparseSampleExplicitLod: return (struct type_args){ 1, 0 }; + case SpvOpImageSparseSampleDrefImplicitLod: return (struct type_args){ 1, 0 }; + case SpvOpImageSparseSampleDrefExplicitLod: return (struct type_args){ 1, 0 }; + case SpvOpImageSparseSampleProjImplicitLod: return (struct type_args){ 1, 0 }; + case SpvOpImageSparseSampleProjExplicitLod: return (struct type_args){ 1, 0 }; + case SpvOpImageSparseSampleProjDrefImplicitLod: return (struct type_args){ 1, 0 }; + case SpvOpImageSparseSampleProjDrefExplicitLod: return (struct type_args){ 1, 0 }; + case SpvOpImageSparseFetch: return (struct type_args){ 1, 0 }; + case SpvOpImageSparseGather: return (struct type_args){ 1, 0 }; + case SpvOpImageSparseDrefGather: return (struct type_args){ 1, 0 }; + case SpvOpImageSparseTexelsResident: return (struct type_args){ 1, 0 }; + case SpvOpAtomicFlagTestAndSet: return (struct type_args){ 1, 0 }; + case SpvOpImageSparseRead: return (struct type_args){ 1, 0 }; + case SpvOpSizeOf: return (struct type_args){ 1, 0 }; + case SpvOpTypePipeStorage: return (struct type_args){ 0, -1 }; + case SpvOpConstantPipeStorage: return (struct type_args){ 1, 0 }; + case SpvOpCreatePipeFromPipeStorage: return (struct type_args){ 1, 0 }; + case SpvOpGetKernelLocalSizeForSubgroupCount: return (struct type_args){ 1, 0 }; + case SpvOpGetKernelMaxNumSubgroups: return (struct type_args){ 1, 0 }; + case SpvOpTypeNamedBarrier: return (struct type_args){ 0, -1 }; + case SpvOpNamedBarrierInitialize: return (struct type_args){ 1, 0 }; + case SpvOpGroupNonUniformElect: return (struct type_args){ 1, 0 }; + case SpvOpGroupNonUniformAll: return (struct type_args){ 1, 0 }; + case SpvOpGroupNonUniformAny: return (struct type_args){ 1, 0 }; + case SpvOpGroupNonUniformAllEqual: return (struct type_args){ 1, 0 }; + case SpvOpGroupNonUniformBroadcast: return (struct type_args){ 1, 0 }; + case SpvOpGroupNonUniformBroadcastFirst: return (struct type_args){ 1, 0 }; + case SpvOpGroupNonUniformBallot: return (struct type_args){ 1, 0 }; + case SpvOpGroupNonUniformInverseBallot: return (struct type_args){ 1, 0 }; + case SpvOpGroupNonUniformBallotBitExtract: return (struct type_args){ 1, 0 }; + case SpvOpGroupNonUniformBallotBitCount: return (struct type_args){ 1, 0 }; + case SpvOpGroupNonUniformBallotFindLSB: return (struct type_args){ 1, 0 }; + case SpvOpGroupNonUniformBallotFindMSB: return (struct type_args){ 1, 0 }; + case SpvOpGroupNonUniformShuffle: return (struct type_args){ 1, 0 }; + case SpvOpGroupNonUniformShuffleXor: return (struct type_args){ 1, 0 }; + case SpvOpGroupNonUniformShuffleUp: return (struct type_args){ 1, 0 }; + case SpvOpGroupNonUniformShuffleDown: return (struct type_args){ 1, 0 }; + case SpvOpGroupNonUniformIAdd: return (struct type_args){ 1, 0 }; + case SpvOpGroupNonUniformFAdd: return (struct type_args){ 1, 0 }; + case SpvOpGroupNonUniformIMul: return (struct type_args){ 1, 0 }; + case SpvOpGroupNonUniformFMul: return (struct type_args){ 1, 0 }; + case SpvOpGroupNonUniformSMin: return (struct type_args){ 1, 0 }; + case SpvOpGroupNonUniformUMin: return (struct type_args){ 1, 0 }; + case SpvOpGroupNonUniformFMin: return (struct type_args){ 1, 0 }; + case SpvOpGroupNonUniformSMax: return (struct type_args){ 1, 0 }; + case SpvOpGroupNonUniformUMax: return (struct type_args){ 1, 0 }; + case SpvOpGroupNonUniformFMax: return (struct type_args){ 1, 0 }; + case SpvOpGroupNonUniformBitwiseAnd: return (struct type_args){ 1, 0 }; + case SpvOpGroupNonUniformBitwiseOr: return (struct type_args){ 1, 0 }; + case SpvOpGroupNonUniformBitwiseXor: return (struct type_args){ 1, 0 }; + case SpvOpGroupNonUniformLogicalAnd: return (struct type_args){ 1, 0 }; + case SpvOpGroupNonUniformLogicalOr: return (struct type_args){ 1, 0 }; + case SpvOpGroupNonUniformLogicalXor: return (struct type_args){ 1, 0 }; + case SpvOpGroupNonUniformQuadBroadcast: return (struct type_args){ 1, 0 }; + case SpvOpGroupNonUniformQuadSwap: return (struct type_args){ 1, 0 }; + case SpvOpSubgroupBallotKHR: return (struct type_args){ 1, 0 }; + case SpvOpSubgroupFirstInvocationKHR: return (struct type_args){ 1, 0 }; + case SpvOpSubgroupAllKHR: return (struct type_args){ 1, 0 }; + case SpvOpSubgroupAnyKHR: return (struct type_args){ 1, 0 }; + case SpvOpSubgroupAllEqualKHR: return (struct type_args){ 1, 0 }; + case SpvOpSubgroupReadInvocationKHR: return (struct type_args){ 1, 0 }; + case SpvOpGroupIAddNonUniformAMD: return (struct type_args){ 1, 0 }; + case SpvOpGroupFAddNonUniformAMD: return (struct type_args){ 1, 0 }; + case SpvOpGroupFMinNonUniformAMD: return (struct type_args){ 1, 0 }; + case SpvOpGroupUMinNonUniformAMD: return (struct type_args){ 1, 0 }; + case SpvOpGroupSMinNonUniformAMD: return (struct type_args){ 1, 0 }; + case SpvOpGroupFMaxNonUniformAMD: return (struct type_args){ 1, 0 }; + case SpvOpGroupUMaxNonUniformAMD: return (struct type_args){ 1, 0 }; + case SpvOpGroupSMaxNonUniformAMD: return (struct type_args){ 1, 0 }; + case SpvOpFragmentMaskFetchAMD: return (struct type_args){ 1, 0 }; + case SpvOpFragmentFetchAMD: return (struct type_args){ 1, 0 }; + case SpvOpReportIntersectionNV: return (struct type_args){ 1, 0 }; + case SpvOpTypeAccelerationStructureNV: return (struct type_args){ 0, -1 }; + case SpvOpSubgroupShuffleINTEL: return (struct type_args){ 1, 0 }; + case SpvOpSubgroupShuffleDownINTEL: return (struct type_args){ 1, 0 }; + case SpvOpSubgroupShuffleUpINTEL: return (struct type_args){ 1, 0 }; + case SpvOpSubgroupShuffleXorINTEL: return (struct type_args){ 1, 0 }; + case SpvOpSubgroupBlockReadINTEL: return (struct type_args){ 1, 0 }; + case SpvOpSubgroupImageBlockReadINTEL: return (struct type_args){ 1, 0 }; + case SpvOpGroupNonUniformPartitionNV: return (struct type_args){ 1, 0 }; + case SpvOpImageSampleFootprintNV: return (struct type_args){ 1, 0 }; + default: return (struct type_args){ -1, -1 }; + } +} + +bool +vtn_set_instruction_result_type(struct vtn_builder *b, SpvOp opcode, + const uint32_t *w, unsigned count) +{ + struct type_args args = result_type_args_for_opcode(opcode); + + if (args.res_idx >= 0 && args.res_type_idx >= 0) { + struct vtn_value *val = vtn_untyped_value(b, w[1 + args.res_idx]); + val->type = vtn_value(b, w[1 + args.res_type_idx], + vtn_value_type_type)->type; + } + + return true; +} + diff --git a/src/compiler/Android.glsl.gen.mk b/src/compiler/Android.glsl.gen.mk index 3b94ea7bd2f..be690941960 100644 --- a/src/compiler/Android.glsl.gen.mk +++ b/src/compiler/Android.glsl.gen.mk @@ -28,6 +28,7 @@ LOCAL_MODULE_CLASS := STATIC_LIBRARIES endif intermediates := $(call local-generated-sources-dir) +prebuilt_intermediates := $(MESA_TOP)/prebuilt-intermediates LOCAL_SRC_FILES := $(LOCAL_SRC_FILES) @@ -92,17 +93,27 @@ $(intermediates)/glsl/glcpp/glcpp-parse.c: $(LOCAL_PATH)/glsl/glcpp/glcpp-parse. $(LOCAL_PATH)/glsl/ir.h: $(intermediates)/glsl/ir_expression_operation.h -$(intermediates)/glsl/ir_expression_operation.h: $(LOCAL_PATH)/glsl/ir_expression_operation.py +#$(intermediates)/glsl/ir_expression_operation.h: $(LOCAL_PATH)/glsl/ir_expression_operation.py +# @mkdir -p $(dir $@) +# $(hide) $(MESA_PYTHON2) $< enum > $@ +$(intermediates)/glsl/ir_expression_operation.h: $(prebuilt_intermediates)/glsl/ir_expression_operation.h @mkdir -p $(dir $@) - $(hide) $(MESA_PYTHON2) $< enum > $@ + @cp -f $< $@ -$(intermediates)/glsl/ir_expression_operation_constant.h: $(LOCAL_PATH)/glsl/ir_expression_operation.py +#$(intermediates)/glsl/ir_expression_operation_constant.h: $(LOCAL_PATH)/glsl/ir_expression_operation.py +# @mkdir -p $(dir $@) +# $(hide) $(MESA_PYTHON2) $< constant > $@ +$(intermediates)/glsl/ir_expression_operation_constant.h: $(prebuilt_intermediates)/glsl/ir_expression_operation_constant.h @mkdir -p $(dir $@) - $(hide) $(MESA_PYTHON2) $< constant > $@ + @cp -f $< $@ -$(intermediates)/glsl/ir_expression_operation_strings.h: $(LOCAL_PATH)/glsl/ir_expression_operation.py +#$(intermediates)/glsl/ir_expression_operation_strings.h: $(LOCAL_PATH)/glsl/ir_expression_operation.py +# @mkdir -p $(dir $@) +# $(hide) $(MESA_PYTHON2) $< strings > $@ + +$(intermediates)/glsl/ir_expression_operation_strings.h: $(prebuilt_intermediates)/glsl/ir_expression_operation_strings.h @mkdir -p $(dir $@) - $(hide) $(MESA_PYTHON2) $< strings > $@ + @cp -f $< $@ $(intermediates)/glsl/float64_glsl.h: $(LOCAL_PATH)/glsl/xxd.py @mkdir -p $(dir $@) diff --git a/src/compiler/Android.nir.gen.mk b/src/compiler/Android.nir.gen.mk index 894fb12c4be..9d8061d0d1c 100644 --- a/src/compiler/Android.nir.gen.mk +++ b/src/compiler/Android.nir.gen.mk @@ -28,6 +28,7 @@ LOCAL_MODULE_CLASS := STATIC_LIBRARIES endif intermediates := $(call local-generated-sources-dir) +prebuilt_intermediates := $(MESA_TOP)/prebuilt-intermediates LOCAL_SRC_FILES := $(LOCAL_SRC_FILES) @@ -54,27 +55,36 @@ nir_builder_opcodes_deps := \ $(LOCAL_PATH)/nir/nir_opcodes.py \ $(LOCAL_PATH)/nir/nir_builder_opcodes_h.py -$(intermediates)/nir/nir_builder_opcodes.h: $(nir_builder_opcodes_deps) +#$(intermediates)/nir/nir_builder_opcodes.h: $(nir_builder_opcodes_deps) +# @mkdir -p $(dir $@) +# $(hide) $(MESA_PYTHON2) $(nir_builder_opcodes_gen) $< > $@ +$(intermediates)/nir/nir_builder_opcodes.h: $(prebuilt_intermediates)/nir/nir_builder_opcodes.h @mkdir -p $(dir $@) - $(hide) $(MESA_PYTHON2) $(nir_builder_opcodes_gen) $< > $@ + @cp -f $< $@ nir_constant_expressions_gen := $(LOCAL_PATH)/nir/nir_constant_expressions.py nir_constant_expressions_deps := \ $(LOCAL_PATH)/nir/nir_opcodes.py \ $(LOCAL_PATH)/nir/nir_constant_expressions.py -$(intermediates)/nir/nir_constant_expressions.c: $(nir_constant_expressions_deps) +#$(intermediates)/nir/nir_constant_expressions.c: $(nir_constant_expressions_deps) +# @mkdir -p $(dir $@) +# $(hide) $(MESA_PYTHON2) $(nir_constant_expressions_gen) $< > $@ +$(intermediates)/nir/nir_constant_expressions.c: $(prebuilt_intermediates)/nir/nir_constant_expressions.c @mkdir -p $(dir $@) - $(hide) $(MESA_PYTHON2) $(nir_constant_expressions_gen) $< > $@ + @cp -f $< $@ nir_opcodes_h_gen := $(LOCAL_PATH)/nir/nir_opcodes_h.py nir_opcodes_h_deps := \ $(LOCAL_PATH)/nir/nir_opcodes.py \ $(LOCAL_PATH)/nir/nir_opcodes_h.py -$(intermediates)/nir/nir_opcodes.h: $(nir_opcodes_h_deps) +#$(intermediates)/nir/nir_opcodes.h: $(nir_opcodes_h_deps) +# @mkdir -p $(dir $@) +# $(hide) $(MESA_PYTHON2) $(nir_opcodes_h_gen) $< > $@ +$(intermediates)/nir/nir_opcodes.h: $(prebuilt_intermediates)/nir/nir_opcodes.h @mkdir -p $(dir $@) - $(hide) $(MESA_PYTHON2) $(nir_opcodes_h_gen) $< > $@ + @cp -f $< $@ $(LOCAL_PATH)/nir/nir.h: $(intermediates)/nir/nir_opcodes.h @@ -83,33 +93,51 @@ nir_opcodes_c_deps := \ $(LOCAL_PATH)/nir/nir_opcodes.py \ $(LOCAL_PATH)/nir/nir_opcodes_c.py -$(intermediates)/nir/nir_opcodes.c: $(nir_opcodes_c_deps) +#$(intermediates)/nir/nir_opcodes.c: $(nir_opcodes_c_deps) +# @mkdir -p $(dir $@) +# $(hide) $(MESA_PYTHON2) $(nir_opcodes_c_gen) $< > $@ +$(intermediates)/nir/nir_opcodes.c: $(prebuilt_intermediates)/nir/nir_opcodes.c @mkdir -p $(dir $@) - $(hide) $(MESA_PYTHON2) $(nir_opcodes_c_gen) $< > $@ + @cp -f $< $@ nir_opt_algebraic_gen := $(LOCAL_PATH)/nir/nir_opt_algebraic.py nir_opt_algebraic_deps := \ $(LOCAL_PATH)/nir/nir_opt_algebraic.py \ $(LOCAL_PATH)/nir/nir_algebraic.py -$(intermediates)/nir/nir_opt_algebraic.c: $(nir_opt_algebraic_deps) +#$(intermediates)/nir/nir_opt_algebraic.c: $(nir_opt_algebraic_deps) +# @mkdir -p $(dir $@) +# $(hide) $(MESA_PYTHON2) $(nir_opt_algebraic_gen) $< > $@ +$(intermediates)/nir/nir_opt_algebraic.c: $(prebuilt_intermediates)/nir/nir_opt_algebraic.c + @mkdir -p $(dir $@) + @cp -f $< $@ + +#$(intermediates)/spirv/spirv_info.c: $(LOCAL_PATH)/spirv/spirv_info_c.py $(LOCAL_PATH)/spirv/spirv.core.grammar.json +# @mkdir -p $(dir $@) +# $(hide) $(MESA_PYTHON2) $^ $@ || ($(RM) $@; false) +$(intermediates)/spirv/spirv_info.c: $(prebuilt_intermediates)/spirv/spirv_info.c @mkdir -p $(dir $@) - $(hide) $(MESA_PYTHON2) $(nir_opt_algebraic_gen) $< > $@ + @cp -f $< $@ -$(intermediates)/spirv/spirv_info.c: $(LOCAL_PATH)/spirv/spirv_info_c.py $(LOCAL_PATH)/spirv/spirv.core.grammar.json +#$(intermediates)/spirv/vtn_gather_types.c:: $(LOCAL_PATH)/spirv/vtn_gather_types_c.py $(LOCAL_PATH)/spirv/spirv.core.grammar.json +# @mkdir -p $(dir $@) +# $(hide) $(MESA_PYTHON2) $^ $@ || ($(RM) $@; false) +$(intermediates)/spirv/vtn_gather_types.c: $(prebuilt_intermediates)/spirv/vtn_gather_types.c @mkdir -p $(dir $@) - $(hide) $(MESA_PYTHON2) $^ $@ || ($(RM) $@; false) + @cp -f $< $@ -$(intermediates)/spirv/vtn_gather_types.c:: $(LOCAL_PATH)/spirv/vtn_gather_types_c.py $(LOCAL_PATH)/spirv/spirv.core.grammar.json +#nir_intrinsics_h_gen := $(LOCAL_PATH)/nir/nir_intrinsics_h.py +#$(intermediates)/nir/nir_intrinsics.h: $(LOCAL_PATH)/nir/nir_intrinsics.py $(nir_intrinsics_h_gen) +# @mkdir -p $(dir $@) +# $(hide) $(MESA_PYTHON2) $(nir_intrinsics_h_gen) --outdir $(dir $@) || ($(RM) $@; false) +$(intermediates)/nir/nir_intrinsics.h: $(prebuilt_intermediates)/nir/nir_intrinsics.h @mkdir -p $(dir $@) - $(hide) $(MESA_PYTHON2) $^ $@ || ($(RM) $@; false) + @cp -f $< $@ -nir_intrinsics_h_gen := $(LOCAL_PATH)/nir/nir_intrinsics_h.py -$(intermediates)/nir/nir_intrinsics.h: $(LOCAL_PATH)/nir/nir_intrinsics.py $(nir_intrinsics_h_gen) +#nir_intrinsics_c_gen := $(LOCAL_PATH)/nir/nir_intrinsics_c.py +#$(intermediates)/nir/nir_intrinsics.c: $(LOCAL_PATH)/nir/nir_intrinsics.py $(nir_intrinsics_c_gen) +# @mkdir -p $(dir $@) +# $(hide) $(MESA_PYTHON2) $(nir_intrinsics_c_gen) --outdir $(dir $@) || ($(RM) $@; false) +$(intermediates)/nir/nir_intrinsics.c: $(prebuilt_intermediates)/nir/nir_intrinsics.c @mkdir -p $(dir $@) - $(hide) $(MESA_PYTHON2) $(nir_intrinsics_h_gen) --outdir $(dir $@) || ($(RM) $@; false) - -nir_intrinsics_c_gen := $(LOCAL_PATH)/nir/nir_intrinsics_c.py -$(intermediates)/nir/nir_intrinsics.c: $(LOCAL_PATH)/nir/nir_intrinsics.py $(nir_intrinsics_c_gen) - @mkdir -p $(dir $@) - $(hide) $(MESA_PYTHON2) $(nir_intrinsics_c_gen) --outdir $(dir $@) || ($(RM) $@; false) + @cp -f $< $@ diff --git a/src/intel/Android.compiler.mk b/src/intel/Android.compiler.mk index 41af7b20b9c..af82fbb74e2 100644 --- a/src/intel/Android.compiler.mk +++ b/src/intel/Android.compiler.mk @@ -51,10 +51,14 @@ brw_nir_trig_workarounds_deps := \ $(MESA_TOP)/src/compiler/nir/nir_algebraic.py intermediates := $(call local-generated-sources-dir) +prebuilt_intermediates := $(MESA_TOP)/prebuilt-intermediates -$(intermediates)/compiler/brw_nir_trig_workarounds.c: $(brw_nir_trig_workarounds_deps) - @mkdir -p $(dir $@) - $(hide) $(MESA_PYTHON2) $< -p $(MESA_TOP)/src/compiler/nir > $@ +#$(intermediates)/compiler/brw_nir_trig_workarounds.c: $(brw_nir_trig_workarounds_deps) +# @mkdir -p $(dir $@) +# $(hide) $(MESA_PYTHON2) $< -p $(MESA_TOP)/src/compiler/nir > $@ +$(intermediates)/compiler/brw_nir_trig_workarounds.c: $(prebuilt_intermediates)/compiler/brw_nir_trig_workarounds.c + @mkdir -p $(dir $@) + @cp -f $< $@ LOCAL_STATIC_LIBRARIES = libmesa_genxml diff --git a/src/intel/Android.genxml.mk b/src/intel/Android.genxml.mk index 8b867920c32..029ca5095a8 100644 --- a/src/intel/Android.genxml.mk +++ b/src/intel/Android.genxml.mk @@ -31,6 +31,7 @@ LOCAL_MODULE := libmesa_genxml LOCAL_MODULE_CLASS := STATIC_LIBRARIES intermediates := $(call local-generated-sources-dir) +prebuilt_intermediates := $(MESA_TOP)/prebuilt-intermediates # dummy.c source file is generated to meet the build system's rules. LOCAL_GENERATED_SOURCES += $(intermediates)/dummy.c @@ -49,12 +50,15 @@ define header-gen $(hide) $(PRIVATE_SCRIPT) $(PRIVATE_SCRIPT_FLAGS) $(PRIVATE_XML) > $@ endef -$(intermediates)/genxml/genX_bits.h: PRIVATE_SCRIPT := $(MESA_PYTHON2) $(LOCAL_PATH)/genxml/gen_bits_header.py -$(intermediates)/genxml/genX_bits.h: PRIVATE_SCRIPT_FLAGS := --cpp-guard=GENX_BITS_H -$(intermediates)/genxml/genX_bits.h: PRIVATE_XML := $(addprefix $(LOCAL_PATH)/,$(GENXML_XML_FILES)) -$(intermediates)/genxml/genX_bits.h: $(LOCAL_PATH)/genxml/gen_bits_header.py -$(intermediates)/genxml/genX_bits.h: $(addprefix $(LOCAL_PATH)/,$(GENXML_XML_FILES)) - $(call header-gen) +#$(intermediates)/genxml/genX_bits.h: PRIVATE_SCRIPT := $(MESA_PYTHON2) $(LOCAL_PATH)/genxml/gen_bits_header.py +#$(intermediates)/genxml/genX_bits.h: PRIVATE_SCRIPT_FLAGS := --cpp-guard=GENX_BITS_H +#$(intermediates)/genxml/genX_bits.h: PRIVATE_XML := $(addprefix $(LOCAL_PATH)/,$(GENXML_XML_FILES)) +#$(intermediates)/genxml/genX_bits.h: $(LOCAL_PATH)/genxml/gen_bits_header.py +#$(intermediates)/genxml/genX_bits.h: $(addprefix $(LOCAL_PATH)/,$(GENXML_XML_FILES)) +# $(call header-gen) +$(intermediates)/genxml/genX_bits.h: $(prebuilt_intermediates)/genxml/genX_bits.h + @mkdir -p $(dir $@) + @cp -f $< $@ $(intermediates)/genxml/gen4_pack.h: PRIVATE_SCRIPT := $(MESA_PYTHON2) $(LOCAL_PATH)/genxml/gen_pack_header.py $(intermediates)/genxml/gen4_pack.h: PRIVATE_XML := $(LOCAL_PATH)/genxml/gen4.xml @@ -106,10 +110,13 @@ $(intermediates)/genxml/gen11_pack.h: PRIVATE_XML := $(LOCAL_PATH)/genxml/gen11. $(intermediates)/genxml/gen11_pack.h: $(LOCAL_PATH)/genxml/gen11.xml $(LOCAL_PATH)/genxml/gen_pack_header.py $(call header-gen) -$(intermediates)/genxml/genX_xml.h: $(addprefix $(MESA_TOP)/src/intel/,$(GENXML_XML_FILES)) $(MESA_TOP)/src/intel/genxml/gen_zipped_file.py - @mkdir -p $(dir $@) - @echo "Gen Header: $(PRIVATE_MODULE) <= $(notdir $(@))" - $(hide) $(MESA_PYTHON2) $(MESA_TOP)/src/intel/genxml/gen_zipped_file.py $(addprefix $(MESA_TOP)/src/intel/,$(GENXML_XML_FILES)) > $@ || (rm -f $@; false) +#$(intermediates)/genxml/genX_xml.h: $(addprefix $(MESA_TOP)/src/intel/,$(GENXML_XML_FILES)) $(MESA_TOP)/src/intel/genxml/gen_zipped_file.py +# @mkdir -p $(dir $@) +# @echo "Gen Header: $(PRIVATE_MODULE) <= $(notdir $(@))" +# $(hide) $(MESA_PYTHON2) $(MESA_TOP)/src/intel/genxml/gen_zipped_file.py $(addprefix $(MESA_TOP)/src/intel/,$(GENXML_XML_FILES)) > $@ || (rm -f $@; false) +$(intermediates)/genxml/genX_xml.h: $(prebuilt_intermediates)/genxml/genX_xml.h + @mkdir -p $(dir $@) + @cp -f $< $@ LOCAL_EXPORT_C_INCLUDE_DIRS := \ $(MESA_TOP)/src/intel \ diff --git a/src/intel/Android.isl.mk b/src/intel/Android.isl.mk index 07a64b8ed1c..eda13931faa 100644 --- a/src/intel/Android.isl.mk +++ b/src/intel/Android.isl.mk @@ -27,6 +27,8 @@ LIBISL_GENX_COMMON_INCLUDES := \ $(MESA_TOP)/src/ +prebuilt_intermediates := $(MESA_TOP)/prebuilt-intermediates + # --------------------------------------- # Build libmesa_isl_gen4 # --------------------------------------- @@ -296,10 +298,13 @@ isl_format_layout_deps := \ $(LOCAL_PATH)/isl/gen_format_layout.py \ $(LOCAL_PATH)/isl/isl_format_layout.csv -$(intermediates)/isl/isl_format_layout.c: PRIVATE_SCRIPT := $(MESA_PYTHON2) $(LOCAL_PATH)/isl/gen_format_layout.py -$(intermediates)/isl/isl_format_layout.c: PRIVATE_CSV := $(LOCAL_PATH)/isl/isl_format_layout.csv -$(intermediates)/isl/isl_format_layout.c: $(isl_format_layout_deps) - $(call bash-gen) +#$(intermediates)/isl/isl_format_layout.c: PRIVATE_SCRIPT := $(MESA_PYTHON2) $(LOCAL_PATH)/isl/gen_format_layout.py +#$(intermediates)/isl/isl_format_layout.c: PRIVATE_CSV := $(LOCAL_PATH)/isl/isl_format_layout.csv +#$(intermediates)/isl/isl_format_layout.c: $(isl_format_layout_deps) +# $(call bash-gen) +$(intermediates)/isl/isl_format_layout.c: $(prebuilt_intermediates)/isl/isl_format_layout.c + @mkdir -p $(dir $@) + @cp -f $< $@ include $(MESA_COMMON_MK) include $(BUILD_STATIC_LIBRARY) diff --git a/src/mesa/Android.gen.mk b/src/mesa/Android.gen.mk index ee2d1dec2c7..a3fb92f4932 100644 --- a/src/mesa/Android.gen.mk +++ b/src/mesa/Android.gen.mk @@ -28,6 +28,7 @@ LOCAL_MODULE_CLASS := STATIC_LIBRARIES endif intermediates := $(call local-generated-sources-dir) +prebuilt_intermediates := $(MESA_TOP)/prebuilt-intermediates # This is the list of auto-generated files: sources and headers sources := \ @@ -75,7 +76,7 @@ matypes_deps := \ $(LOCAL_PATH)/main/mtypes.h \ $(LOCAL_PATH)/tnl/t_context.h -$(intermediates)/x86/matypes.h: $(matypes_deps) +$(intermediates)/x86/matypes.h: $(matypes_deps) @mkdir -p $(dir $@) @echo "MATYPES: $(PRIVATE_MODULE) <= $(notdir $@)" $(hide) $< > $@ @@ -130,10 +131,13 @@ format_fallback_deps := \ $(LOCAL_PATH)/main/format_parser.py \ $(FORMAT_FALLBACK) -$(intermediates)/main/format_fallback.c: PRIVATE_SCRIPT := $(MESA_PYTHON2) $(FORMAT_FALLBACK) -$(intermediates)/main/format_fallback.c: PRIVATE_XML := -$(intermediates)/main/format_fallback.c: $(format_fallback_deps) - $(call es-gen, $< /dev/stdout) +#$(intermediates)/main/format_fallback.c: PRIVATE_SCRIPT := $(MESA_PYTHON2) $(FORMAT_FALLBACK) +#$(intermediates)/main/format_fallback.c: PRIVATE_XML := +#$(intermediates)/main/format_fallback.c: $(format_fallback_deps) +# $(call es-gen, $< /dev/stdout) +$(intermediates)/main/format_fallback.c: $(prebuilt_intermediates)/main/format_fallback.c + @mkdir -p $(dir $@) + @cp -f $< $@ FORMAT_INFO := $(LOCAL_PATH)/main/format_info.py format_info_deps := \ @@ -152,10 +156,13 @@ format_pack_deps := \ $(LOCAL_PATH)/main/format_parser.py \ $(FORMAT_PACK) -$(intermediates)/main/format_pack.c: PRIVATE_SCRIPT := $(MESA_PYTHON2) $(FORMAT_PACK) -$(intermediates)/main/format_pack.c: PRIVATE_XML := -$(intermediates)/main/format_pack.c: $(format_pack_deps) - $(call es-gen, $<) +#$(intermediates)/main/format_pack.c: PRIVATE_SCRIPT := $(MESA_PYTHON2) $(FORMAT_PACK) +#$(intermediates)/main/format_pack.c: PRIVATE_XML := +#$(intermediates)/main/format_pack.c: $(format_pack_deps) +# $(call es-gen, $<) +$(intermediates)/main/format_pack.c: $(prebuilt_intermediates)/main/format_pack.c + @mkdir -p $(dir $@) + @cp -f $< $@ FORMAT_UNPACK := $(LOCAL_PATH)/main/format_unpack.py format_unpack_deps := \ @@ -163,7 +170,10 @@ format_unpack_deps := \ $(LOCAL_PATH)/main/format_parser.py \ $(FORMAT_UNPACK) -$(intermediates)/main/format_unpack.c: PRIVATE_SCRIPT := $(MESA_PYTHON2) $(FORMAT_UNPACK) -$(intermediates)/main/format_unpack.c: PRIVATE_XML := -$(intermediates)/main/format_unpack.c: $(format_unpack_deps) - $(call es-gen, $<) +#$(intermediates)/main/format_unpack.c: PRIVATE_SCRIPT := $(MESA_PYTHON2) $(FORMAT_UNPACK) +#$(intermediates)/main/format_unpack.c: PRIVATE_XML := +#$(intermediates)/main/format_unpack.c: $(format_unpack_deps) +# $(call es-gen, $<) +$(intermediates)/main/format_unpack.c: $(prebuilt_intermediates)/main/format_unpack.c + @mkdir -p $(dir $@) + @cp -f $< $@ diff --git a/src/mesa/drivers/dri/i965/Android.mk b/src/mesa/drivers/dri/i965/Android.mk index 97def8f03fe..7cbc9e055aa 100644 --- a/src/mesa/drivers/dri/i965/Android.mk +++ b/src/mesa/drivers/dri/i965/Android.mk @@ -24,6 +24,8 @@ LOCAL_PATH := $(call my-dir) +prebuilt_intermediates := $(MESA_TOP)/prebuilt-intermediates + # Import variables i965_FILES. include $(LOCAL_PATH)/Makefile.sources @@ -315,15 +317,22 @@ LOCAL_GENERATED_SOURCES += $(addprefix $(intermediates)/, \ i965_oa_xml_FILES := $(addprefix $(MESA_TOP)/src/mesa/drivers/dri/i965/, \ $(i965_oa_xml_FILES)) -$(intermediates)/brw_oa_metrics.c: $(LOCAL_PATH)/brw_oa.py $(i965_oa_xml_FILES) - @echo "target Generated: $(PRIVATE_MODULE) <= $(notdir $(@))" - @mkdir -p $(dir $@) - $(hide) $(MESA_PYTHON2) $< \ - --code=$@ \ - --header=$(call generated-sources-dir-for,SHARED_LIBRARIES,i965_dri,,)/brw_oa_metrics.h \ - $(i965_oa_xml_FILES) - -$(intermediates)/brw_oa_metrics.h: $(intermediates)/brw_oa_metrics.c +#$(intermediates)/brw_oa_metrics.c: $(LOCAL_PATH)/brw_oa.py $(i965_oa_xml_FILES) +# @echo "target Generated: $(PRIVATE_MODULE) <= $(notdir $(@))" +# @mkdir -p $(dir $@) +# $(hide) $(MESA_PYTHON2) $< \ +# --code=$@ \ +# --header=$(call generated-sources-dir-for,SHARED_LIBRARIES,i965_dri,,)/brw_oa_metrics.h \ +# $(i965_oa_xml_FILES) + +$(intermediates)/brw_oa_metrics.c: $(prebuilt_intermediates)/i965_dri_intermediates/brw_oa_metrics.c + @mkdir -p $(dir $@) + @cp -f $< $@ + +#$(intermediates)/brw_oa_metrics.h: $(intermediates)/brw_oa_metrics.c +$(intermediates)/brw_oa_metrics.h: $(prebuilt_intermediates)/i965_dri_intermediates/brw_oa_metrics.h + @mkdir -p $(dir $@) + @cp -f $< $@ include $(MESA_COMMON_MK) include $(BUILD_SHARED_LIBRARY) From 4f8362bb42f02bf59ccc671498e94459d1d1b964 Mon Sep 17 00:00:00 2001 From: renchenglei Date: Fri, 31 May 2019 10:00:13 +0800 Subject: [PATCH 25/27] mesa3d: dragonboards: add format_srgb.c to prebuilts While building Android for dragonboards, the build fails since it can't find the generated file format_srgb.c. To work around this problem, introduce prebuilt-intermediates for format_srgb.c from the current source tree. Change-Id: I4c96e040f6b7c633ccf7f3b34c742a7fb6ee6592 Signed-off-by: Sumit Semwal --- prebuilt-intermediates/util/format_srgb.c | 178 ++++++++++++++++++++++ src/util/Android.mk | 7 + 2 files changed, 185 insertions(+) create mode 100644 prebuilt-intermediates/util/format_srgb.c diff --git a/prebuilt-intermediates/util/format_srgb.c b/prebuilt-intermediates/util/format_srgb.c new file mode 100644 index 00000000000..a725880824b --- /dev/null +++ b/prebuilt-intermediates/util/format_srgb.c @@ -0,0 +1,178 @@ +/* This file is autogenerated by u_format_srgb.py. Do not edit directly. */ + +/************************************************************************** + * + * Copyright 2010 VMware, Inc. + * All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + **************************************************************************/ + +/** + * @file + * SRGB translation. + * + * @author Brian Paul + * @author Michal Krol + * @author Jose Fonseca + */ + +#include "format_srgb.h" + +const float +util_format_srgb_8unorm_to_linear_float_table[256] = { + 0.0000000e+00, 3.0352698e-04, 6.0705397e-04, 9.1058095e-04, + 1.2141079e-03, 1.5176349e-03, 1.8211619e-03, 2.1246889e-03, + 2.4282159e-03, 2.7317429e-03, 3.0352698e-03, 3.3465358e-03, + 3.6765073e-03, 4.0247170e-03, 4.3914420e-03, 4.7769535e-03, + 5.1815167e-03, 5.6053916e-03, 6.0488330e-03, 6.5120908e-03, + 6.9954102e-03, 7.4990320e-03, 8.0231930e-03, 8.5681256e-03, + 9.1340587e-03, 9.7212173e-03, 1.0329823e-02, 1.0960094e-02, + 1.1612245e-02, 1.2286488e-02, 1.2983032e-02, 1.3702083e-02, + 1.4443844e-02, 1.5208514e-02, 1.5996293e-02, 1.6807376e-02, + 1.7641954e-02, 1.8500220e-02, 1.9382361e-02, 2.0288563e-02, + 2.1219010e-02, 2.2173885e-02, 2.3153366e-02, 2.4157632e-02, + 2.5186860e-02, 2.6241222e-02, 2.7320892e-02, 2.8426040e-02, + 2.9556834e-02, 3.0713444e-02, 3.1896033e-02, 3.3104767e-02, + 3.4339807e-02, 3.5601315e-02, 3.6889450e-02, 3.8204372e-02, + 3.9546235e-02, 4.0915197e-02, 4.2311411e-02, 4.3735029e-02, + 4.5186204e-02, 4.6665086e-02, 4.8171824e-02, 4.9706566e-02, + 5.1269458e-02, 5.2860647e-02, 5.4480276e-02, 5.6128490e-02, + 5.7805430e-02, 5.9511238e-02, 6.1246054e-02, 6.3010018e-02, + 6.4803267e-02, 6.6625939e-02, 6.8478170e-02, 7.0360096e-02, + 7.2271851e-02, 7.4213568e-02, 7.6185381e-02, 7.8187422e-02, + 8.0219820e-02, 8.2282707e-02, 8.4376212e-02, 8.6500462e-02, + 8.8655586e-02, 9.0841711e-02, 9.3058963e-02, 9.5307467e-02, + 9.7587347e-02, 9.9898728e-02, 1.0224173e-01, 1.0461648e-01, + 1.0702310e-01, 1.0946171e-01, 1.1193243e-01, 1.1443537e-01, + 1.1697067e-01, 1.1953843e-01, 1.2213877e-01, 1.2477182e-01, + 1.2743768e-01, 1.3013648e-01, 1.3286832e-01, 1.3563333e-01, + 1.3843162e-01, 1.4126329e-01, 1.4412847e-01, 1.4702727e-01, + 1.4995979e-01, 1.5292615e-01, 1.5592646e-01, 1.5896084e-01, + 1.6202938e-01, 1.6513219e-01, 1.6826940e-01, 1.7144110e-01, + 1.7464740e-01, 1.7788842e-01, 1.8116424e-01, 1.8447499e-01, + 1.8782077e-01, 1.9120168e-01, 1.9461783e-01, 1.9806932e-01, + 2.0155625e-01, 2.0507874e-01, 2.0863687e-01, 2.1223076e-01, + 2.1586050e-01, 2.1952620e-01, 2.2322796e-01, 2.2696587e-01, + 2.3074005e-01, 2.3455058e-01, 2.3839757e-01, 2.4228112e-01, + 2.4620133e-01, 2.5015828e-01, 2.5415209e-01, 2.5818285e-01, + 2.6225066e-01, 2.6635560e-01, 2.7049779e-01, 2.7467731e-01, + 2.7889426e-01, 2.8314874e-01, 2.8744084e-01, 2.9177065e-01, + 2.9613827e-01, 3.0054379e-01, 3.0498731e-01, 3.0946892e-01, + 3.1398871e-01, 3.1854678e-01, 3.2314321e-01, 3.2777810e-01, + 3.3245154e-01, 3.3716362e-01, 3.4191442e-01, 3.4670406e-01, + 3.5153260e-01, 3.5640014e-01, 3.6130678e-01, 3.6625260e-01, + 3.7123768e-01, 3.7626212e-01, 3.8132601e-01, 3.8642943e-01, + 3.9157248e-01, 3.9675523e-01, 4.0197778e-01, 4.0724021e-01, + 4.1254261e-01, 4.1788507e-01, 4.2326767e-01, 4.2869050e-01, + 4.3415364e-01, 4.3965717e-01, 4.4520119e-01, 4.5078578e-01, + 4.5641102e-01, 4.6207700e-01, 4.6778380e-01, 4.7353150e-01, + 4.7932018e-01, 4.8514994e-01, 4.9102085e-01, 4.9693300e-01, + 5.0288646e-01, 5.0888132e-01, 5.1491767e-01, 5.2099557e-01, + 5.2711513e-01, 5.3327640e-01, 5.3947949e-01, 5.4572446e-01, + 5.5201140e-01, 5.5834039e-01, 5.6471151e-01, 5.7112483e-01, + 5.7758044e-01, 5.8407842e-01, 5.9061884e-01, 5.9720179e-01, + 6.0382734e-01, 6.1049557e-01, 6.1720656e-01, 6.2396039e-01, + 6.3075714e-01, 6.3759687e-01, 6.4447968e-01, 6.5140564e-01, + 6.5837482e-01, 6.6538730e-01, 6.7244316e-01, 6.7954247e-01, + 6.8668531e-01, 6.9387176e-01, 7.0110189e-01, 7.0837578e-01, + 7.1569350e-01, 7.2305513e-01, 7.3046074e-01, 7.3791041e-01, + 7.4540421e-01, 7.5294222e-01, 7.6052450e-01, 7.6815115e-01, + 7.7582222e-01, 7.8353779e-01, 7.9129794e-01, 7.9910274e-01, + 8.0695226e-01, 8.1484657e-01, 8.2278575e-01, 8.3076988e-01, + 8.3879901e-01, 8.4687323e-01, 8.5499261e-01, 8.6315721e-01, + 8.7136712e-01, 8.7962240e-01, 8.8792312e-01, 8.9626935e-01, + 9.0466117e-01, 9.1309865e-01, 9.2158186e-01, 9.3011086e-01, + 9.3868573e-01, 9.4730654e-01, 9.5597335e-01, 9.6468625e-01, + 9.7344529e-01, 9.8225055e-01, 9.9110210e-01, 1.0000000e+00, +}; + +const uint8_t +util_format_srgb_to_linear_8unorm_table[256] = { + 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 1, 1, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 3, 3, + 4, 4, 4, 4, 4, 5, 5, 5, 5, 6, 6, 6, 6, 7, 7, 7, + 8, 8, 8, 8, 9, 9, 9, 10, 10, 10, 11, 11, 12, 12, 12, 13, + 13, 13, 14, 14, 15, 15, 16, 16, 17, 17, 17, 18, 18, 19, 19, 20, + 20, 21, 22, 22, 23, 23, 24, 24, 25, 25, 26, 27, 27, 28, 29, 29, + 30, 30, 31, 32, 32, 33, 34, 35, 35, 36, 37, 37, 38, 39, 40, 41, + 41, 42, 43, 44, 45, 45, 46, 47, 48, 49, 50, 51, 51, 52, 53, 54, + 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, + 71, 72, 73, 74, 76, 77, 78, 79, 80, 81, 82, 84, 85, 86, 87, 88, + 90, 91, 92, 93, 95, 96, 97, 99, 100, 101, 103, 104, 105, 107, 108, 109, + 111, 112, 114, 115, 116, 118, 119, 121, 122, 124, 125, 127, 128, 130, 131, 133, + 134, 136, 138, 139, 141, 142, 144, 146, 147, 149, 151, 152, 154, 156, 157, 159, + 161, 163, 164, 166, 168, 170, 171, 173, 175, 177, 179, 181, 183, 184, 186, 188, + 190, 192, 194, 196, 198, 200, 202, 204, 206, 208, 210, 212, 214, 216, 218, 220, + 222, 224, 226, 229, 231, 233, 235, 237, 239, 242, 244, 246, 248, 250, 253, 255, +}; + +const uint8_t +util_format_linear_to_srgb_8unorm_table[256] = { + 0, 13, 22, 28, 34, 38, 42, 46, 50, 53, 56, 59, 61, 64, 66, 69, + 71, 73, 75, 77, 79, 81, 83, 85, 86, 88, 90, 92, 93, 95, 96, 98, + 99, 101, 102, 104, 105, 106, 108, 109, 110, 112, 113, 114, 115, 117, 118, 119, + 120, 121, 122, 124, 125, 126, 127, 128, 129, 130, 131, 132, 133, 134, 135, 136, + 137, 138, 139, 140, 141, 142, 143, 144, 145, 146, 147, 148, 148, 149, 150, 151, + 152, 153, 154, 155, 155, 156, 157, 158, 159, 159, 160, 161, 162, 163, 163, 164, + 165, 166, 167, 167, 168, 169, 170, 170, 171, 172, 173, 173, 174, 175, 175, 176, + 177, 178, 178, 179, 180, 180, 181, 182, 182, 183, 184, 185, 185, 186, 187, 187, + 188, 189, 189, 190, 190, 191, 192, 192, 193, 194, 194, 195, 196, 196, 197, 197, + 198, 199, 199, 200, 200, 201, 202, 202, 203, 203, 204, 205, 205, 206, 206, 207, + 208, 208, 209, 209, 210, 210, 211, 212, 212, 213, 213, 214, 214, 215, 215, 216, + 216, 217, 218, 218, 219, 219, 220, 220, 221, 221, 222, 222, 223, 223, 224, 224, + 225, 226, 226, 227, 227, 228, 228, 229, 229, 230, 230, 231, 231, 232, 232, 233, + 233, 234, 234, 235, 235, 236, 236, 237, 237, 238, 238, 238, 239, 239, 240, 240, + 241, 241, 242, 242, 243, 243, 244, 244, 245, 245, 246, 246, 246, 247, 247, 248, + 248, 249, 249, 250, 250, 251, 251, 251, 252, 252, 253, 253, 254, 254, 255, 255, +}; + +const unsigned +util_format_linear_to_srgb_helper_table[104] = { + 0x0073000d, 0x007a000d, 0x0080000d, 0x0087000d, + 0x008d000d, 0x0094000d, 0x009a000d, 0x00a1000d, + 0x00a7001a, 0x00b4001a, 0x00c1001a, 0x00ce001a, + 0x00da001a, 0x00e7001a, 0x00f4001a, 0x0101001a, + 0x010e0033, 0x01280033, 0x01410033, 0x015b0033, + 0x01750033, 0x018f0033, 0x01a80033, 0x01c20033, + 0x01dc0067, 0x020f0067, 0x02430067, 0x02760067, + 0x02aa0067, 0x02dd0067, 0x03110067, 0x03440067, + 0x037800ce, 0x03df00ce, 0x044600ce, 0x04ad00ce, + 0x051400ce, 0x057b00c5, 0x05dd00bc, 0x063b00b5, + 0x06970158, 0x07420142, 0x07e30130, 0x087b0120, + 0x090b0112, 0x09940106, 0x0a1700fc, 0x0a9500f2, + 0x0b0f01cb, 0x0bf401ae, 0x0ccb0195, 0x0d950180, + 0x0e56016e, 0x0f0d015e, 0x0fbc0150, 0x10630143, + 0x11070264, 0x1238023e, 0x1357021d, 0x14660201, + 0x156601e9, 0x165a01d3, 0x174401c0, 0x182401af, + 0x18fe0331, 0x1a9602fe, 0x1c1502d2, 0x1d7e02ad, + 0x1ed4028d, 0x201a0270, 0x21520256, 0x227d0240, + 0x239f0443, 0x25c003fe, 0x27bf03c4, 0x29a10392, + 0x2b6a0367, 0x2d1d0341, 0x2ebe031f, 0x304d0300, + 0x31d105b0, 0x34a80555, 0x37520507, 0x39d504c5, + 0x3c37048b, 0x3e7c0458, 0x40a8042a, 0x42bd0401, + 0x44c20798, 0x488e071e, 0x4c1c06b6, 0x4f76065d, + 0x52a50610, 0x55ac05cc, 0x5892058f, 0x5b590559, + 0x5e0c0a23, 0x631c0980, 0x67db08f6, 0x6c55087f, + 0x70940818, 0x74a007bd, 0x787d076c, 0x7c330723, +}; + diff --git a/src/util/Android.mk b/src/util/Android.mk index fe26cf035e3..5dac1f9f5f6 100644 --- a/src/util/Android.mk +++ b/src/util/Android.mk @@ -72,5 +72,12 @@ $(intermediates)/xmlpool/options.h: $(prebuilt_intermediates)/xmlpool/options.h MESA_DRI_OPTIONS_H := $(intermediates)/xmlpool/options.h LOCAL_GENERATED_SOURCES += $(MESA_DRI_OPTIONS_H) +$(intermediates)/format_srgb.c: $(prebuilt_intermediates)/util/format_srgb.c + @mkdir -p $(dir $@) + @cp -f $< $@ + +MESA_FORMAT_SRGB_C := $(intermediates)/format_srgb.c +LOCAL_GENERATED_SOURCES := $(MESA_FORMAT_SRGB_C) + include $(MESA_COMMON_MK) include $(BUILD_STATIC_LIBRARY) From 6e421e2c2b0e93e84e3b7cf0d1182e7786f1949a Mon Sep 17 00:00:00 2001 From: renchenglei Date: Fri, 31 May 2019 10:50:26 +0800 Subject: [PATCH 26/27] Add generated file for vulkan.broxton library --- prebuilt-intermediates/util/vk_enum_to_str.c | 2747 ++++++++ prebuilt-intermediates/util/vk_enum_to_str.h | 267 + .../vulkan/anv_entrypoints.c | 5878 +++++++++++++++++ .../vulkan/anv_entrypoints.h | 1678 +++++ .../vulkan/anv_extensions.c | 251 + .../vulkan/anv_extensions.h | 129 + src/intel/Android.vulkan.mk | 38 +- src/vulkan/Android.mk | 8 + 8 files changed, 10985 insertions(+), 11 deletions(-) create mode 100644 prebuilt-intermediates/util/vk_enum_to_str.c create mode 100644 prebuilt-intermediates/util/vk_enum_to_str.h create mode 100644 prebuilt-intermediates/vulkan/anv_entrypoints.c create mode 100644 prebuilt-intermediates/vulkan/anv_entrypoints.h create mode 100644 prebuilt-intermediates/vulkan/anv_extensions.c create mode 100644 prebuilt-intermediates/vulkan/anv_extensions.h diff --git a/prebuilt-intermediates/util/vk_enum_to_str.c b/prebuilt-intermediates/util/vk_enum_to_str.c new file mode 100644 index 00000000000..74dba8c1c72 --- /dev/null +++ b/prebuilt-intermediates/util/vk_enum_to_str.c @@ -0,0 +1,2747 @@ +/* Autogenerated file -- do not edit + * generated by gen_enum_to_str.py + * + * Copyright © 2017 Intel Corporation +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. + */ + +#include +#include +#include "util/macros.h" +#include "vk_enum_to_str.h" + + +const char * +vk_AccelerationStructureMemoryRequirementsTypeNV_to_str(VkAccelerationStructureMemoryRequirementsTypeNV input) +{ + switch(input) { + case 0: + return "VK_ACCELERATION_STRUCTURE_MEMORY_REQUIREMENTS_TYPE_OBJECT_NV"; + case 1: + return "VK_ACCELERATION_STRUCTURE_MEMORY_REQUIREMENTS_TYPE_BUILD_SCRATCH_NV"; + case 2: + return "VK_ACCELERATION_STRUCTURE_MEMORY_REQUIREMENTS_TYPE_UPDATE_SCRATCH_NV"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_AccelerationStructureTypeNV_to_str(VkAccelerationStructureTypeNV input) +{ + switch(input) { + case 0: + return "VK_ACCELERATION_STRUCTURE_TYPE_TOP_LEVEL_NV"; + case 1: + return "VK_ACCELERATION_STRUCTURE_TYPE_BOTTOM_LEVEL_NV"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_AttachmentLoadOp_to_str(VkAttachmentLoadOp input) +{ + switch(input) { + case 0: + return "VK_ATTACHMENT_LOAD_OP_LOAD"; + case 1: + return "VK_ATTACHMENT_LOAD_OP_CLEAR"; + case 2: + return "VK_ATTACHMENT_LOAD_OP_DONT_CARE"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_AttachmentStoreOp_to_str(VkAttachmentStoreOp input) +{ + switch(input) { + case 0: + return "VK_ATTACHMENT_STORE_OP_STORE"; + case 1: + return "VK_ATTACHMENT_STORE_OP_DONT_CARE"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_BlendFactor_to_str(VkBlendFactor input) +{ + switch(input) { + case 0: + return "VK_BLEND_FACTOR_ZERO"; + case 1: + return "VK_BLEND_FACTOR_ONE"; + case 2: + return "VK_BLEND_FACTOR_SRC_COLOR"; + case 3: + return "VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR"; + case 4: + return "VK_BLEND_FACTOR_DST_COLOR"; + case 5: + return "VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR"; + case 6: + return "VK_BLEND_FACTOR_SRC_ALPHA"; + case 7: + return "VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA"; + case 8: + return "VK_BLEND_FACTOR_DST_ALPHA"; + case 9: + return "VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA"; + case 10: + return "VK_BLEND_FACTOR_CONSTANT_COLOR"; + case 11: + return "VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR"; + case 12: + return "VK_BLEND_FACTOR_CONSTANT_ALPHA"; + case 13: + return "VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA"; + case 14: + return "VK_BLEND_FACTOR_SRC_ALPHA_SATURATE"; + case 15: + return "VK_BLEND_FACTOR_SRC1_COLOR"; + case 16: + return "VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR"; + case 17: + return "VK_BLEND_FACTOR_SRC1_ALPHA"; + case 18: + return "VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_BlendOp_to_str(VkBlendOp input) +{ + switch(input) { + case 0: + return "VK_BLEND_OP_ADD"; + case 1: + return "VK_BLEND_OP_SUBTRACT"; + case 2: + return "VK_BLEND_OP_REVERSE_SUBTRACT"; + case 3: + return "VK_BLEND_OP_MIN"; + case 4: + return "VK_BLEND_OP_MAX"; + case 1000148000: + return "VK_BLEND_OP_ZERO_EXT"; + case 1000148001: + return "VK_BLEND_OP_SRC_EXT"; + case 1000148002: + return "VK_BLEND_OP_DST_EXT"; + case 1000148003: + return "VK_BLEND_OP_SRC_OVER_EXT"; + case 1000148004: + return "VK_BLEND_OP_DST_OVER_EXT"; + case 1000148005: + return "VK_BLEND_OP_SRC_IN_EXT"; + case 1000148006: + return "VK_BLEND_OP_DST_IN_EXT"; + case 1000148007: + return "VK_BLEND_OP_SRC_OUT_EXT"; + case 1000148008: + return "VK_BLEND_OP_DST_OUT_EXT"; + case 1000148009: + return "VK_BLEND_OP_SRC_ATOP_EXT"; + case 1000148010: + return "VK_BLEND_OP_DST_ATOP_EXT"; + case 1000148011: + return "VK_BLEND_OP_XOR_EXT"; + case 1000148012: + return "VK_BLEND_OP_MULTIPLY_EXT"; + case 1000148013: + return "VK_BLEND_OP_SCREEN_EXT"; + case 1000148014: + return "VK_BLEND_OP_OVERLAY_EXT"; + case 1000148015: + return "VK_BLEND_OP_DARKEN_EXT"; + case 1000148016: + return "VK_BLEND_OP_LIGHTEN_EXT"; + case 1000148017: + return "VK_BLEND_OP_COLORDODGE_EXT"; + case 1000148018: + return "VK_BLEND_OP_COLORBURN_EXT"; + case 1000148019: + return "VK_BLEND_OP_HARDLIGHT_EXT"; + case 1000148020: + return "VK_BLEND_OP_SOFTLIGHT_EXT"; + case 1000148021: + return "VK_BLEND_OP_DIFFERENCE_EXT"; + case 1000148022: + return "VK_BLEND_OP_EXCLUSION_EXT"; + case 1000148023: + return "VK_BLEND_OP_INVERT_EXT"; + case 1000148024: + return "VK_BLEND_OP_INVERT_RGB_EXT"; + case 1000148025: + return "VK_BLEND_OP_LINEARDODGE_EXT"; + case 1000148026: + return "VK_BLEND_OP_LINEARBURN_EXT"; + case 1000148027: + return "VK_BLEND_OP_VIVIDLIGHT_EXT"; + case 1000148028: + return "VK_BLEND_OP_LINEARLIGHT_EXT"; + case 1000148029: + return "VK_BLEND_OP_PINLIGHT_EXT"; + case 1000148030: + return "VK_BLEND_OP_HARDMIX_EXT"; + case 1000148031: + return "VK_BLEND_OP_HSL_HUE_EXT"; + case 1000148032: + return "VK_BLEND_OP_HSL_SATURATION_EXT"; + case 1000148033: + return "VK_BLEND_OP_HSL_COLOR_EXT"; + case 1000148034: + return "VK_BLEND_OP_HSL_LUMINOSITY_EXT"; + case 1000148035: + return "VK_BLEND_OP_PLUS_EXT"; + case 1000148036: + return "VK_BLEND_OP_PLUS_CLAMPED_EXT"; + case 1000148037: + return "VK_BLEND_OP_PLUS_CLAMPED_ALPHA_EXT"; + case 1000148038: + return "VK_BLEND_OP_PLUS_DARKER_EXT"; + case 1000148039: + return "VK_BLEND_OP_MINUS_EXT"; + case 1000148040: + return "VK_BLEND_OP_MINUS_CLAMPED_EXT"; + case 1000148041: + return "VK_BLEND_OP_CONTRAST_EXT"; + case 1000148042: + return "VK_BLEND_OP_INVERT_OVG_EXT"; + case 1000148043: + return "VK_BLEND_OP_RED_EXT"; + case 1000148044: + return "VK_BLEND_OP_GREEN_EXT"; + case 1000148045: + return "VK_BLEND_OP_BLUE_EXT"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_BlendOverlapEXT_to_str(VkBlendOverlapEXT input) +{ + switch(input) { + case 0: + return "VK_BLEND_OVERLAP_UNCORRELATED_EXT"; + case 1: + return "VK_BLEND_OVERLAP_DISJOINT_EXT"; + case 2: + return "VK_BLEND_OVERLAP_CONJOINT_EXT"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_BorderColor_to_str(VkBorderColor input) +{ + switch(input) { + case 0: + return "VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK"; + case 1: + return "VK_BORDER_COLOR_INT_TRANSPARENT_BLACK"; + case 2: + return "VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK"; + case 3: + return "VK_BORDER_COLOR_INT_OPAQUE_BLACK"; + case 4: + return "VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE"; + case 5: + return "VK_BORDER_COLOR_INT_OPAQUE_WHITE"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_ChromaLocation_to_str(VkChromaLocation input) +{ + switch(input) { + case 0: + return "VK_CHROMA_LOCATION_COSITED_EVEN"; + case 1: + return "VK_CHROMA_LOCATION_MIDPOINT"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_CoarseSampleOrderTypeNV_to_str(VkCoarseSampleOrderTypeNV input) +{ + switch(input) { + case 0: + return "VK_COARSE_SAMPLE_ORDER_TYPE_DEFAULT_NV"; + case 1: + return "VK_COARSE_SAMPLE_ORDER_TYPE_CUSTOM_NV"; + case 2: + return "VK_COARSE_SAMPLE_ORDER_TYPE_PIXEL_MAJOR_NV"; + case 3: + return "VK_COARSE_SAMPLE_ORDER_TYPE_SAMPLE_MAJOR_NV"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_ColorSpaceKHR_to_str(VkColorSpaceKHR input) +{ + switch(input) { + case 0: + return "VK_COLORSPACE_SRGB_NONLINEAR_KHR"; + case 1000104001: + return "VK_COLOR_SPACE_DISPLAY_P3_NONLINEAR_EXT"; + case 1000104002: + return "VK_COLOR_SPACE_EXTENDED_SRGB_LINEAR_EXT"; + case 1000104003: + return "VK_COLOR_SPACE_DCI_P3_LINEAR_EXT"; + case 1000104004: + return "VK_COLOR_SPACE_DCI_P3_NONLINEAR_EXT"; + case 1000104005: + return "VK_COLOR_SPACE_BT709_LINEAR_EXT"; + case 1000104006: + return "VK_COLOR_SPACE_BT709_NONLINEAR_EXT"; + case 1000104007: + return "VK_COLOR_SPACE_BT2020_LINEAR_EXT"; + case 1000104008: + return "VK_COLOR_SPACE_HDR10_ST2084_EXT"; + case 1000104009: + return "VK_COLOR_SPACE_DOLBYVISION_EXT"; + case 1000104010: + return "VK_COLOR_SPACE_HDR10_HLG_EXT"; + case 1000104011: + return "VK_COLOR_SPACE_ADOBERGB_LINEAR_EXT"; + case 1000104012: + return "VK_COLOR_SPACE_ADOBERGB_NONLINEAR_EXT"; + case 1000104013: + return "VK_COLOR_SPACE_PASS_THROUGH_EXT"; + case 1000104014: + return "VK_COLOR_SPACE_EXTENDED_SRGB_NONLINEAR_EXT"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_CommandBufferLevel_to_str(VkCommandBufferLevel input) +{ + switch(input) { + case 0: + return "VK_COMMAND_BUFFER_LEVEL_PRIMARY"; + case 1: + return "VK_COMMAND_BUFFER_LEVEL_SECONDARY"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_CompareOp_to_str(VkCompareOp input) +{ + switch(input) { + case 0: + return "VK_COMPARE_OP_NEVER"; + case 1: + return "VK_COMPARE_OP_LESS"; + case 2: + return "VK_COMPARE_OP_EQUAL"; + case 3: + return "VK_COMPARE_OP_LESS_OR_EQUAL"; + case 4: + return "VK_COMPARE_OP_GREATER"; + case 5: + return "VK_COMPARE_OP_NOT_EQUAL"; + case 6: + return "VK_COMPARE_OP_GREATER_OR_EQUAL"; + case 7: + return "VK_COMPARE_OP_ALWAYS"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_ComponentSwizzle_to_str(VkComponentSwizzle input) +{ + switch(input) { + case 0: + return "VK_COMPONENT_SWIZZLE_IDENTITY"; + case 1: + return "VK_COMPONENT_SWIZZLE_ZERO"; + case 2: + return "VK_COMPONENT_SWIZZLE_ONE"; + case 3: + return "VK_COMPONENT_SWIZZLE_R"; + case 4: + return "VK_COMPONENT_SWIZZLE_G"; + case 5: + return "VK_COMPONENT_SWIZZLE_B"; + case 6: + return "VK_COMPONENT_SWIZZLE_A"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_ConservativeRasterizationModeEXT_to_str(VkConservativeRasterizationModeEXT input) +{ + switch(input) { + case 0: + return "VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT"; + case 1: + return "VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT"; + case 2: + return "VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_CopyAccelerationStructureModeNV_to_str(VkCopyAccelerationStructureModeNV input) +{ + switch(input) { + case 0: + return "VK_COPY_ACCELERATION_STRUCTURE_MODE_CLONE_NV"; + case 1: + return "VK_COPY_ACCELERATION_STRUCTURE_MODE_COMPACT_NV"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_CoverageModulationModeNV_to_str(VkCoverageModulationModeNV input) +{ + switch(input) { + case 0: + return "VK_COVERAGE_MODULATION_MODE_NONE_NV"; + case 1: + return "VK_COVERAGE_MODULATION_MODE_RGB_NV"; + case 2: + return "VK_COVERAGE_MODULATION_MODE_ALPHA_NV"; + case 3: + return "VK_COVERAGE_MODULATION_MODE_RGBA_NV"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_DebugReportObjectTypeEXT_to_str(VkDebugReportObjectTypeEXT input) +{ + switch(input) { + case 0: + return "VK_DEBUG_REPORT_OBJECT_TYPE_UNKNOWN_EXT"; + case 1: + return "VK_DEBUG_REPORT_OBJECT_TYPE_INSTANCE_EXT"; + case 2: + return "VK_DEBUG_REPORT_OBJECT_TYPE_PHYSICAL_DEVICE_EXT"; + case 3: + return "VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_EXT"; + case 4: + return "VK_DEBUG_REPORT_OBJECT_TYPE_QUEUE_EXT"; + case 5: + return "VK_DEBUG_REPORT_OBJECT_TYPE_SEMAPHORE_EXT"; + case 6: + return "VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_BUFFER_EXT"; + case 7: + return "VK_DEBUG_REPORT_OBJECT_TYPE_FENCE_EXT"; + case 8: + return "VK_DEBUG_REPORT_OBJECT_TYPE_DEVICE_MEMORY_EXT"; + case 9: + return "VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_EXT"; + case 10: + return "VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_EXT"; + case 11: + return "VK_DEBUG_REPORT_OBJECT_TYPE_EVENT_EXT"; + case 12: + return "VK_DEBUG_REPORT_OBJECT_TYPE_QUERY_POOL_EXT"; + case 13: + return "VK_DEBUG_REPORT_OBJECT_TYPE_BUFFER_VIEW_EXT"; + case 14: + return "VK_DEBUG_REPORT_OBJECT_TYPE_IMAGE_VIEW_EXT"; + case 15: + return "VK_DEBUG_REPORT_OBJECT_TYPE_SHADER_MODULE_EXT"; + case 16: + return "VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_CACHE_EXT"; + case 17: + return "VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_LAYOUT_EXT"; + case 18: + return "VK_DEBUG_REPORT_OBJECT_TYPE_RENDER_PASS_EXT"; + case 19: + return "VK_DEBUG_REPORT_OBJECT_TYPE_PIPELINE_EXT"; + case 20: + return "VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT_EXT"; + case 21: + return "VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_EXT"; + case 22: + return "VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_POOL_EXT"; + case 23: + return "VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_SET_EXT"; + case 24: + return "VK_DEBUG_REPORT_OBJECT_TYPE_FRAMEBUFFER_EXT"; + case 25: + return "VK_DEBUG_REPORT_OBJECT_TYPE_COMMAND_POOL_EXT"; + case 26: + return "VK_DEBUG_REPORT_OBJECT_TYPE_SURFACE_KHR_EXT"; + case 27: + return "VK_DEBUG_REPORT_OBJECT_TYPE_SWAPCHAIN_KHR_EXT"; + case 28: + return "VK_DEBUG_REPORT_OBJECT_TYPE_DEBUG_REPORT_EXT"; + case 29: + return "VK_DEBUG_REPORT_OBJECT_TYPE_DISPLAY_KHR_EXT"; + case 30: + return "VK_DEBUG_REPORT_OBJECT_TYPE_DISPLAY_MODE_KHR_EXT"; + case 31: + return "VK_DEBUG_REPORT_OBJECT_TYPE_OBJECT_TABLE_NVX_EXT"; + case 32: + return "VK_DEBUG_REPORT_OBJECT_TYPE_INDIRECT_COMMANDS_LAYOUT_NVX_EXT"; + case 33: + return "VK_DEBUG_REPORT_OBJECT_TYPE_VALIDATION_CACHE_EXT"; + case 1000085000: + return "VK_DEBUG_REPORT_OBJECT_TYPE_DESCRIPTOR_UPDATE_TEMPLATE_EXT"; + case 1000156000: + return "VK_DEBUG_REPORT_OBJECT_TYPE_SAMPLER_YCBCR_CONVERSION_EXT"; + case 1000165000: + return "VK_DEBUG_REPORT_OBJECT_TYPE_ACCELERATION_STRUCTURE_NV_EXT"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_DescriptorType_to_str(VkDescriptorType input) +{ + switch(input) { + case 0: + return "VK_DESCRIPTOR_TYPE_SAMPLER"; + case 1: + return "VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER"; + case 2: + return "VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE"; + case 3: + return "VK_DESCRIPTOR_TYPE_STORAGE_IMAGE"; + case 4: + return "VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER"; + case 5: + return "VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER"; + case 6: + return "VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER"; + case 7: + return "VK_DESCRIPTOR_TYPE_STORAGE_BUFFER"; + case 8: + return "VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC"; + case 9: + return "VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC"; + case 10: + return "VK_DESCRIPTOR_TYPE_INPUT_ATTACHMENT"; + case 1000138000: + return "VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT"; + case 1000165000: + return "VK_DESCRIPTOR_TYPE_ACCELERATION_STRUCTURE_NV"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_DescriptorUpdateTemplateType_to_str(VkDescriptorUpdateTemplateType input) +{ + switch(input) { + case 0: + return "VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_DESCRIPTOR_SET"; + case 1: + return "VK_DESCRIPTOR_UPDATE_TEMPLATE_TYPE_PUSH_DESCRIPTORS_KHR"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_DeviceEventTypeEXT_to_str(VkDeviceEventTypeEXT input) +{ + switch(input) { + case 0: + return "VK_DEVICE_EVENT_TYPE_DISPLAY_HOTPLUG_EXT"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_DiscardRectangleModeEXT_to_str(VkDiscardRectangleModeEXT input) +{ + switch(input) { + case 0: + return "VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT"; + case 1: + return "VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_DisplayEventTypeEXT_to_str(VkDisplayEventTypeEXT input) +{ + switch(input) { + case 0: + return "VK_DISPLAY_EVENT_TYPE_FIRST_PIXEL_OUT_EXT"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_DisplayPowerStateEXT_to_str(VkDisplayPowerStateEXT input) +{ + switch(input) { + case 0: + return "VK_DISPLAY_POWER_STATE_OFF_EXT"; + case 1: + return "VK_DISPLAY_POWER_STATE_SUSPEND_EXT"; + case 2: + return "VK_DISPLAY_POWER_STATE_ON_EXT"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_DriverIdKHR_to_str(VkDriverIdKHR input) +{ + switch(input) { + case 1: + return "VK_DRIVER_ID_AMD_PROPRIETARY_KHR"; + case 2: + return "VK_DRIVER_ID_AMD_OPEN_SOURCE_KHR"; + case 3: + return "VK_DRIVER_ID_MESA_RADV_KHR"; + case 4: + return "VK_DRIVER_ID_NVIDIA_PROPRIETARY_KHR"; + case 5: + return "VK_DRIVER_ID_INTEL_PROPRIETARY_WINDOWS_KHR"; + case 6: + return "VK_DRIVER_ID_INTEL_OPEN_SOURCE_MESA_KHR"; + case 7: + return "VK_DRIVER_ID_IMAGINATION_PROPRIETARY_KHR"; + case 8: + return "VK_DRIVER_ID_QUALCOMM_PROPRIETARY_KHR"; + case 9: + return "VK_DRIVER_ID_ARM_PROPRIETARY_KHR"; + case 10: + return "VK_DRIVER_ID_GOOGLE_PASTEL_KHR"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_DynamicState_to_str(VkDynamicState input) +{ + switch(input) { + case 0: + return "VK_DYNAMIC_STATE_VIEWPORT"; + case 1: + return "VK_DYNAMIC_STATE_SCISSOR"; + case 2: + return "VK_DYNAMIC_STATE_LINE_WIDTH"; + case 3: + return "VK_DYNAMIC_STATE_DEPTH_BIAS"; + case 4: + return "VK_DYNAMIC_STATE_BLEND_CONSTANTS"; + case 5: + return "VK_DYNAMIC_STATE_DEPTH_BOUNDS"; + case 6: + return "VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK"; + case 7: + return "VK_DYNAMIC_STATE_STENCIL_WRITE_MASK"; + case 8: + return "VK_DYNAMIC_STATE_STENCIL_REFERENCE"; + case 1000087000: + return "VK_DYNAMIC_STATE_VIEWPORT_W_SCALING_NV"; + case 1000099000: + return "VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT"; + case 1000143000: + return "VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT"; + case 1000164004: + return "VK_DYNAMIC_STATE_VIEWPORT_SHADING_RATE_PALETTE_NV"; + case 1000164006: + return "VK_DYNAMIC_STATE_VIEWPORT_COARSE_SAMPLE_ORDER_NV"; + case 1000205001: + return "VK_DYNAMIC_STATE_EXCLUSIVE_SCISSOR_NV"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_Filter_to_str(VkFilter input) +{ + switch(input) { + case 0: + return "VK_FILTER_NEAREST"; + case 1: + return "VK_FILTER_LINEAR"; + case 1000015000: + return "VK_FILTER_CUBIC_IMG"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_Format_to_str(VkFormat input) +{ + switch(input) { + case 0: + return "VK_FORMAT_UNDEFINED"; + case 1: + return "VK_FORMAT_R4G4_UNORM_PACK8"; + case 2: + return "VK_FORMAT_R4G4B4A4_UNORM_PACK16"; + case 3: + return "VK_FORMAT_B4G4R4A4_UNORM_PACK16"; + case 4: + return "VK_FORMAT_R5G6B5_UNORM_PACK16"; + case 5: + return "VK_FORMAT_B5G6R5_UNORM_PACK16"; + case 6: + return "VK_FORMAT_R5G5B5A1_UNORM_PACK16"; + case 7: + return "VK_FORMAT_B5G5R5A1_UNORM_PACK16"; + case 8: + return "VK_FORMAT_A1R5G5B5_UNORM_PACK16"; + case 9: + return "VK_FORMAT_R8_UNORM"; + case 10: + return "VK_FORMAT_R8_SNORM"; + case 11: + return "VK_FORMAT_R8_USCALED"; + case 12: + return "VK_FORMAT_R8_SSCALED"; + case 13: + return "VK_FORMAT_R8_UINT"; + case 14: + return "VK_FORMAT_R8_SINT"; + case 15: + return "VK_FORMAT_R8_SRGB"; + case 16: + return "VK_FORMAT_R8G8_UNORM"; + case 17: + return "VK_FORMAT_R8G8_SNORM"; + case 18: + return "VK_FORMAT_R8G8_USCALED"; + case 19: + return "VK_FORMAT_R8G8_SSCALED"; + case 20: + return "VK_FORMAT_R8G8_UINT"; + case 21: + return "VK_FORMAT_R8G8_SINT"; + case 22: + return "VK_FORMAT_R8G8_SRGB"; + case 23: + return "VK_FORMAT_R8G8B8_UNORM"; + case 24: + return "VK_FORMAT_R8G8B8_SNORM"; + case 25: + return "VK_FORMAT_R8G8B8_USCALED"; + case 26: + return "VK_FORMAT_R8G8B8_SSCALED"; + case 27: + return "VK_FORMAT_R8G8B8_UINT"; + case 28: + return "VK_FORMAT_R8G8B8_SINT"; + case 29: + return "VK_FORMAT_R8G8B8_SRGB"; + case 30: + return "VK_FORMAT_B8G8R8_UNORM"; + case 31: + return "VK_FORMAT_B8G8R8_SNORM"; + case 32: + return "VK_FORMAT_B8G8R8_USCALED"; + case 33: + return "VK_FORMAT_B8G8R8_SSCALED"; + case 34: + return "VK_FORMAT_B8G8R8_UINT"; + case 35: + return "VK_FORMAT_B8G8R8_SINT"; + case 36: + return "VK_FORMAT_B8G8R8_SRGB"; + case 37: + return "VK_FORMAT_R8G8B8A8_UNORM"; + case 38: + return "VK_FORMAT_R8G8B8A8_SNORM"; + case 39: + return "VK_FORMAT_R8G8B8A8_USCALED"; + case 40: + return "VK_FORMAT_R8G8B8A8_SSCALED"; + case 41: + return "VK_FORMAT_R8G8B8A8_UINT"; + case 42: + return "VK_FORMAT_R8G8B8A8_SINT"; + case 43: + return "VK_FORMAT_R8G8B8A8_SRGB"; + case 44: + return "VK_FORMAT_B8G8R8A8_UNORM"; + case 45: + return "VK_FORMAT_B8G8R8A8_SNORM"; + case 46: + return "VK_FORMAT_B8G8R8A8_USCALED"; + case 47: + return "VK_FORMAT_B8G8R8A8_SSCALED"; + case 48: + return "VK_FORMAT_B8G8R8A8_UINT"; + case 49: + return "VK_FORMAT_B8G8R8A8_SINT"; + case 50: + return "VK_FORMAT_B8G8R8A8_SRGB"; + case 51: + return "VK_FORMAT_A8B8G8R8_UNORM_PACK32"; + case 52: + return "VK_FORMAT_A8B8G8R8_SNORM_PACK32"; + case 53: + return "VK_FORMAT_A8B8G8R8_USCALED_PACK32"; + case 54: + return "VK_FORMAT_A8B8G8R8_SSCALED_PACK32"; + case 55: + return "VK_FORMAT_A8B8G8R8_UINT_PACK32"; + case 56: + return "VK_FORMAT_A8B8G8R8_SINT_PACK32"; + case 57: + return "VK_FORMAT_A8B8G8R8_SRGB_PACK32"; + case 58: + return "VK_FORMAT_A2R10G10B10_UNORM_PACK32"; + case 59: + return "VK_FORMAT_A2R10G10B10_SNORM_PACK32"; + case 60: + return "VK_FORMAT_A2R10G10B10_USCALED_PACK32"; + case 61: + return "VK_FORMAT_A2R10G10B10_SSCALED_PACK32"; + case 62: + return "VK_FORMAT_A2R10G10B10_UINT_PACK32"; + case 63: + return "VK_FORMAT_A2R10G10B10_SINT_PACK32"; + case 64: + return "VK_FORMAT_A2B10G10R10_UNORM_PACK32"; + case 65: + return "VK_FORMAT_A2B10G10R10_SNORM_PACK32"; + case 66: + return "VK_FORMAT_A2B10G10R10_USCALED_PACK32"; + case 67: + return "VK_FORMAT_A2B10G10R10_SSCALED_PACK32"; + case 68: + return "VK_FORMAT_A2B10G10R10_UINT_PACK32"; + case 69: + return "VK_FORMAT_A2B10G10R10_SINT_PACK32"; + case 70: + return "VK_FORMAT_R16_UNORM"; + case 71: + return "VK_FORMAT_R16_SNORM"; + case 72: + return "VK_FORMAT_R16_USCALED"; + case 73: + return "VK_FORMAT_R16_SSCALED"; + case 74: + return "VK_FORMAT_R16_UINT"; + case 75: + return "VK_FORMAT_R16_SINT"; + case 76: + return "VK_FORMAT_R16_SFLOAT"; + case 77: + return "VK_FORMAT_R16G16_UNORM"; + case 78: + return "VK_FORMAT_R16G16_SNORM"; + case 79: + return "VK_FORMAT_R16G16_USCALED"; + case 80: + return "VK_FORMAT_R16G16_SSCALED"; + case 81: + return "VK_FORMAT_R16G16_UINT"; + case 82: + return "VK_FORMAT_R16G16_SINT"; + case 83: + return "VK_FORMAT_R16G16_SFLOAT"; + case 84: + return "VK_FORMAT_R16G16B16_UNORM"; + case 85: + return "VK_FORMAT_R16G16B16_SNORM"; + case 86: + return "VK_FORMAT_R16G16B16_USCALED"; + case 87: + return "VK_FORMAT_R16G16B16_SSCALED"; + case 88: + return "VK_FORMAT_R16G16B16_UINT"; + case 89: + return "VK_FORMAT_R16G16B16_SINT"; + case 90: + return "VK_FORMAT_R16G16B16_SFLOAT"; + case 91: + return "VK_FORMAT_R16G16B16A16_UNORM"; + case 92: + return "VK_FORMAT_R16G16B16A16_SNORM"; + case 93: + return "VK_FORMAT_R16G16B16A16_USCALED"; + case 94: + return "VK_FORMAT_R16G16B16A16_SSCALED"; + case 95: + return "VK_FORMAT_R16G16B16A16_UINT"; + case 96: + return "VK_FORMAT_R16G16B16A16_SINT"; + case 97: + return "VK_FORMAT_R16G16B16A16_SFLOAT"; + case 98: + return "VK_FORMAT_R32_UINT"; + case 99: + return "VK_FORMAT_R32_SINT"; + case 100: + return "VK_FORMAT_R32_SFLOAT"; + case 101: + return "VK_FORMAT_R32G32_UINT"; + case 102: + return "VK_FORMAT_R32G32_SINT"; + case 103: + return "VK_FORMAT_R32G32_SFLOAT"; + case 104: + return "VK_FORMAT_R32G32B32_UINT"; + case 105: + return "VK_FORMAT_R32G32B32_SINT"; + case 106: + return "VK_FORMAT_R32G32B32_SFLOAT"; + case 107: + return "VK_FORMAT_R32G32B32A32_UINT"; + case 108: + return "VK_FORMAT_R32G32B32A32_SINT"; + case 109: + return "VK_FORMAT_R32G32B32A32_SFLOAT"; + case 110: + return "VK_FORMAT_R64_UINT"; + case 111: + return "VK_FORMAT_R64_SINT"; + case 112: + return "VK_FORMAT_R64_SFLOAT"; + case 113: + return "VK_FORMAT_R64G64_UINT"; + case 114: + return "VK_FORMAT_R64G64_SINT"; + case 115: + return "VK_FORMAT_R64G64_SFLOAT"; + case 116: + return "VK_FORMAT_R64G64B64_UINT"; + case 117: + return "VK_FORMAT_R64G64B64_SINT"; + case 118: + return "VK_FORMAT_R64G64B64_SFLOAT"; + case 119: + return "VK_FORMAT_R64G64B64A64_UINT"; + case 120: + return "VK_FORMAT_R64G64B64A64_SINT"; + case 121: + return "VK_FORMAT_R64G64B64A64_SFLOAT"; + case 122: + return "VK_FORMAT_B10G11R11_UFLOAT_PACK32"; + case 123: + return "VK_FORMAT_E5B9G9R9_UFLOAT_PACK32"; + case 124: + return "VK_FORMAT_D16_UNORM"; + case 125: + return "VK_FORMAT_X8_D24_UNORM_PACK32"; + case 126: + return "VK_FORMAT_D32_SFLOAT"; + case 127: + return "VK_FORMAT_S8_UINT"; + case 128: + return "VK_FORMAT_D16_UNORM_S8_UINT"; + case 129: + return "VK_FORMAT_D24_UNORM_S8_UINT"; + case 130: + return "VK_FORMAT_D32_SFLOAT_S8_UINT"; + case 131: + return "VK_FORMAT_BC1_RGB_UNORM_BLOCK"; + case 132: + return "VK_FORMAT_BC1_RGB_SRGB_BLOCK"; + case 133: + return "VK_FORMAT_BC1_RGBA_UNORM_BLOCK"; + case 134: + return "VK_FORMAT_BC1_RGBA_SRGB_BLOCK"; + case 135: + return "VK_FORMAT_BC2_UNORM_BLOCK"; + case 136: + return "VK_FORMAT_BC2_SRGB_BLOCK"; + case 137: + return "VK_FORMAT_BC3_UNORM_BLOCK"; + case 138: + return "VK_FORMAT_BC3_SRGB_BLOCK"; + case 139: + return "VK_FORMAT_BC4_UNORM_BLOCK"; + case 140: + return "VK_FORMAT_BC4_SNORM_BLOCK"; + case 141: + return "VK_FORMAT_BC5_UNORM_BLOCK"; + case 142: + return "VK_FORMAT_BC5_SNORM_BLOCK"; + case 143: + return "VK_FORMAT_BC6H_UFLOAT_BLOCK"; + case 144: + return "VK_FORMAT_BC6H_SFLOAT_BLOCK"; + case 145: + return "VK_FORMAT_BC7_UNORM_BLOCK"; + case 146: + return "VK_FORMAT_BC7_SRGB_BLOCK"; + case 147: + return "VK_FORMAT_ETC2_R8G8B8_UNORM_BLOCK"; + case 148: + return "VK_FORMAT_ETC2_R8G8B8_SRGB_BLOCK"; + case 149: + return "VK_FORMAT_ETC2_R8G8B8A1_UNORM_BLOCK"; + case 150: + return "VK_FORMAT_ETC2_R8G8B8A1_SRGB_BLOCK"; + case 151: + return "VK_FORMAT_ETC2_R8G8B8A8_UNORM_BLOCK"; + case 152: + return "VK_FORMAT_ETC2_R8G8B8A8_SRGB_BLOCK"; + case 153: + return "VK_FORMAT_EAC_R11_UNORM_BLOCK"; + case 154: + return "VK_FORMAT_EAC_R11_SNORM_BLOCK"; + case 155: + return "VK_FORMAT_EAC_R11G11_UNORM_BLOCK"; + case 156: + return "VK_FORMAT_EAC_R11G11_SNORM_BLOCK"; + case 157: + return "VK_FORMAT_ASTC_4x4_UNORM_BLOCK"; + case 158: + return "VK_FORMAT_ASTC_4x4_SRGB_BLOCK"; + case 159: + return "VK_FORMAT_ASTC_5x4_UNORM_BLOCK"; + case 160: + return "VK_FORMAT_ASTC_5x4_SRGB_BLOCK"; + case 161: + return "VK_FORMAT_ASTC_5x5_UNORM_BLOCK"; + case 162: + return "VK_FORMAT_ASTC_5x5_SRGB_BLOCK"; + case 163: + return "VK_FORMAT_ASTC_6x5_UNORM_BLOCK"; + case 164: + return "VK_FORMAT_ASTC_6x5_SRGB_BLOCK"; + case 165: + return "VK_FORMAT_ASTC_6x6_UNORM_BLOCK"; + case 166: + return "VK_FORMAT_ASTC_6x6_SRGB_BLOCK"; + case 167: + return "VK_FORMAT_ASTC_8x5_UNORM_BLOCK"; + case 168: + return "VK_FORMAT_ASTC_8x5_SRGB_BLOCK"; + case 169: + return "VK_FORMAT_ASTC_8x6_UNORM_BLOCK"; + case 170: + return "VK_FORMAT_ASTC_8x6_SRGB_BLOCK"; + case 171: + return "VK_FORMAT_ASTC_8x8_UNORM_BLOCK"; + case 172: + return "VK_FORMAT_ASTC_8x8_SRGB_BLOCK"; + case 173: + return "VK_FORMAT_ASTC_10x5_UNORM_BLOCK"; + case 174: + return "VK_FORMAT_ASTC_10x5_SRGB_BLOCK"; + case 175: + return "VK_FORMAT_ASTC_10x6_UNORM_BLOCK"; + case 176: + return "VK_FORMAT_ASTC_10x6_SRGB_BLOCK"; + case 177: + return "VK_FORMAT_ASTC_10x8_UNORM_BLOCK"; + case 178: + return "VK_FORMAT_ASTC_10x8_SRGB_BLOCK"; + case 179: + return "VK_FORMAT_ASTC_10x10_UNORM_BLOCK"; + case 180: + return "VK_FORMAT_ASTC_10x10_SRGB_BLOCK"; + case 181: + return "VK_FORMAT_ASTC_12x10_UNORM_BLOCK"; + case 182: + return "VK_FORMAT_ASTC_12x10_SRGB_BLOCK"; + case 183: + return "VK_FORMAT_ASTC_12x12_UNORM_BLOCK"; + case 184: + return "VK_FORMAT_ASTC_12x12_SRGB_BLOCK"; + case 1000054000: + return "VK_FORMAT_PVRTC1_2BPP_UNORM_BLOCK_IMG"; + case 1000054001: + return "VK_FORMAT_PVRTC1_4BPP_UNORM_BLOCK_IMG"; + case 1000054002: + return "VK_FORMAT_PVRTC2_2BPP_UNORM_BLOCK_IMG"; + case 1000054003: + return "VK_FORMAT_PVRTC2_4BPP_UNORM_BLOCK_IMG"; + case 1000054004: + return "VK_FORMAT_PVRTC1_2BPP_SRGB_BLOCK_IMG"; + case 1000054005: + return "VK_FORMAT_PVRTC1_4BPP_SRGB_BLOCK_IMG"; + case 1000054006: + return "VK_FORMAT_PVRTC2_2BPP_SRGB_BLOCK_IMG"; + case 1000054007: + return "VK_FORMAT_PVRTC2_4BPP_SRGB_BLOCK_IMG"; + case 1000156000: + return "VK_FORMAT_G8B8G8R8_422_UNORM"; + case 1000156001: + return "VK_FORMAT_B8G8R8G8_422_UNORM"; + case 1000156002: + return "VK_FORMAT_G8_B8_R8_3PLANE_420_UNORM"; + case 1000156003: + return "VK_FORMAT_G8_B8R8_2PLANE_420_UNORM"; + case 1000156004: + return "VK_FORMAT_G8_B8_R8_3PLANE_422_UNORM"; + case 1000156005: + return "VK_FORMAT_G8_B8R8_2PLANE_422_UNORM"; + case 1000156006: + return "VK_FORMAT_G8_B8_R8_3PLANE_444_UNORM"; + case 1000156007: + return "VK_FORMAT_R10X6_UNORM_PACK16"; + case 1000156008: + return "VK_FORMAT_R10X6G10X6_UNORM_2PACK16"; + case 1000156009: + return "VK_FORMAT_R10X6G10X6B10X6A10X6_UNORM_4PACK16"; + case 1000156010: + return "VK_FORMAT_G10X6B10X6G10X6R10X6_422_UNORM_4PACK16"; + case 1000156011: + return "VK_FORMAT_B10X6G10X6R10X6G10X6_422_UNORM_4PACK16"; + case 1000156012: + return "VK_FORMAT_G10X6_B10X6_R10X6_3PLANE_420_UNORM_3PACK16"; + case 1000156013: + return "VK_FORMAT_G10X6_B10X6R10X6_2PLANE_420_UNORM_3PACK16"; + case 1000156014: + return "VK_FORMAT_G10X6_B10X6_R10X6_3PLANE_422_UNORM_3PACK16"; + case 1000156015: + return "VK_FORMAT_G10X6_B10X6R10X6_2PLANE_422_UNORM_3PACK16"; + case 1000156016: + return "VK_FORMAT_G10X6_B10X6_R10X6_3PLANE_444_UNORM_3PACK16"; + case 1000156017: + return "VK_FORMAT_R12X4_UNORM_PACK16"; + case 1000156018: + return "VK_FORMAT_R12X4G12X4_UNORM_2PACK16"; + case 1000156019: + return "VK_FORMAT_R12X4G12X4B12X4A12X4_UNORM_4PACK16"; + case 1000156020: + return "VK_FORMAT_G12X4B12X4G12X4R12X4_422_UNORM_4PACK16"; + case 1000156021: + return "VK_FORMAT_B12X4G12X4R12X4G12X4_422_UNORM_4PACK16"; + case 1000156022: + return "VK_FORMAT_G12X4_B12X4_R12X4_3PLANE_420_UNORM_3PACK16"; + case 1000156023: + return "VK_FORMAT_G12X4_B12X4R12X4_2PLANE_420_UNORM_3PACK16"; + case 1000156024: + return "VK_FORMAT_G12X4_B12X4_R12X4_3PLANE_422_UNORM_3PACK16"; + case 1000156025: + return "VK_FORMAT_G12X4_B12X4R12X4_2PLANE_422_UNORM_3PACK16"; + case 1000156026: + return "VK_FORMAT_G12X4_B12X4_R12X4_3PLANE_444_UNORM_3PACK16"; + case 1000156027: + return "VK_FORMAT_G16B16G16R16_422_UNORM"; + case 1000156028: + return "VK_FORMAT_B16G16R16G16_422_UNORM"; + case 1000156029: + return "VK_FORMAT_G16_B16_R16_3PLANE_420_UNORM"; + case 1000156030: + return "VK_FORMAT_G16_B16R16_2PLANE_420_UNORM"; + case 1000156031: + return "VK_FORMAT_G16_B16_R16_3PLANE_422_UNORM"; + case 1000156032: + return "VK_FORMAT_G16_B16R16_2PLANE_422_UNORM"; + case 1000156033: + return "VK_FORMAT_G16_B16_R16_3PLANE_444_UNORM"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_FrontFace_to_str(VkFrontFace input) +{ + switch(input) { + case 0: + return "VK_FRONT_FACE_COUNTER_CLOCKWISE"; + case 1: + return "VK_FRONT_FACE_CLOCKWISE"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_GeometryTypeNV_to_str(VkGeometryTypeNV input) +{ + switch(input) { + case 0: + return "VK_GEOMETRY_TYPE_TRIANGLES_NV"; + case 1: + return "VK_GEOMETRY_TYPE_AABBS_NV"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_ImageLayout_to_str(VkImageLayout input) +{ + switch(input) { + case 0: + return "VK_IMAGE_LAYOUT_UNDEFINED"; + case 1: + return "VK_IMAGE_LAYOUT_GENERAL"; + case 2: + return "VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL"; + case 3: + return "VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL"; + case 4: + return "VK_IMAGE_LAYOUT_DEPTH_STENCIL_READ_ONLY_OPTIMAL"; + case 5: + return "VK_IMAGE_LAYOUT_SHADER_READ_ONLY_OPTIMAL"; + case 6: + return "VK_IMAGE_LAYOUT_TRANSFER_SRC_OPTIMAL"; + case 7: + return "VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL"; + case 8: + return "VK_IMAGE_LAYOUT_PREINITIALIZED"; + case 1000001002: + return "VK_IMAGE_LAYOUT_PRESENT_SRC_KHR"; + case 1000111000: + return "VK_IMAGE_LAYOUT_SHARED_PRESENT_KHR"; + case 1000117000: + return "VK_IMAGE_LAYOUT_DEPTH_READ_ONLY_STENCIL_ATTACHMENT_OPTIMAL"; + case 1000117001: + return "VK_IMAGE_LAYOUT_DEPTH_ATTACHMENT_STENCIL_READ_ONLY_OPTIMAL"; + case 1000164003: + return "VK_IMAGE_LAYOUT_SHADING_RATE_OPTIMAL_NV"; + case 1000218000: + return "VK_IMAGE_LAYOUT_FRAGMENT_DENSITY_MAP_OPTIMAL_EXT"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_ImageTiling_to_str(VkImageTiling input) +{ + switch(input) { + case 0: + return "VK_IMAGE_TILING_OPTIMAL"; + case 1: + return "VK_IMAGE_TILING_LINEAR"; + case 1000158000: + return "VK_IMAGE_TILING_DRM_FORMAT_MODIFIER_EXT"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_ImageType_to_str(VkImageType input) +{ + switch(input) { + case 0: + return "VK_IMAGE_TYPE_1D"; + case 1: + return "VK_IMAGE_TYPE_2D"; + case 2: + return "VK_IMAGE_TYPE_3D"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_ImageViewType_to_str(VkImageViewType input) +{ + switch(input) { + case 0: + return "VK_IMAGE_VIEW_TYPE_1D"; + case 1: + return "VK_IMAGE_VIEW_TYPE_2D"; + case 2: + return "VK_IMAGE_VIEW_TYPE_3D"; + case 3: + return "VK_IMAGE_VIEW_TYPE_CUBE"; + case 4: + return "VK_IMAGE_VIEW_TYPE_1D_ARRAY"; + case 5: + return "VK_IMAGE_VIEW_TYPE_2D_ARRAY"; + case 6: + return "VK_IMAGE_VIEW_TYPE_CUBE_ARRAY"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_IndexType_to_str(VkIndexType input) +{ + switch(input) { + case 0: + return "VK_INDEX_TYPE_UINT16"; + case 1: + return "VK_INDEX_TYPE_UINT32"; + case 1000165000: + return "VK_INDEX_TYPE_NONE_NV"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_IndirectCommandsTokenTypeNVX_to_str(VkIndirectCommandsTokenTypeNVX input) +{ + switch(input) { + case 0: + return "VK_INDIRECT_COMMANDS_TOKEN_TYPE_PIPELINE_NVX"; + case 1: + return "VK_INDIRECT_COMMANDS_TOKEN_TYPE_DESCRIPTOR_SET_NVX"; + case 2: + return "VK_INDIRECT_COMMANDS_TOKEN_TYPE_INDEX_BUFFER_NVX"; + case 3: + return "VK_INDIRECT_COMMANDS_TOKEN_TYPE_VERTEX_BUFFER_NVX"; + case 4: + return "VK_INDIRECT_COMMANDS_TOKEN_TYPE_PUSH_CONSTANT_NVX"; + case 5: + return "VK_INDIRECT_COMMANDS_TOKEN_TYPE_DRAW_INDEXED_NVX"; + case 6: + return "VK_INDIRECT_COMMANDS_TOKEN_TYPE_DRAW_NVX"; + case 7: + return "VK_INDIRECT_COMMANDS_TOKEN_TYPE_DISPATCH_NVX"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_InternalAllocationType_to_str(VkInternalAllocationType input) +{ + switch(input) { + case 0: + return "VK_INTERNAL_ALLOCATION_TYPE_EXECUTABLE"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_LogicOp_to_str(VkLogicOp input) +{ + switch(input) { + case 0: + return "VK_LOGIC_OP_CLEAR"; + case 1: + return "VK_LOGIC_OP_AND"; + case 2: + return "VK_LOGIC_OP_AND_REVERSE"; + case 3: + return "VK_LOGIC_OP_COPY"; + case 4: + return "VK_LOGIC_OP_AND_INVERTED"; + case 5: + return "VK_LOGIC_OP_NO_OP"; + case 6: + return "VK_LOGIC_OP_XOR"; + case 7: + return "VK_LOGIC_OP_OR"; + case 8: + return "VK_LOGIC_OP_NOR"; + case 9: + return "VK_LOGIC_OP_EQUIVALENT"; + case 10: + return "VK_LOGIC_OP_INVERT"; + case 11: + return "VK_LOGIC_OP_OR_REVERSE"; + case 12: + return "VK_LOGIC_OP_COPY_INVERTED"; + case 13: + return "VK_LOGIC_OP_OR_INVERTED"; + case 14: + return "VK_LOGIC_OP_NAND"; + case 15: + return "VK_LOGIC_OP_SET"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_MemoryOverallocationBehaviorAMD_to_str(VkMemoryOverallocationBehaviorAMD input) +{ + switch(input) { + case 0: + return "VK_MEMORY_OVERALLOCATION_BEHAVIOR_DEFAULT_AMD"; + case 1: + return "VK_MEMORY_OVERALLOCATION_BEHAVIOR_ALLOWED_AMD"; + case 2: + return "VK_MEMORY_OVERALLOCATION_BEHAVIOR_DISALLOWED_AMD"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_ObjectEntryTypeNVX_to_str(VkObjectEntryTypeNVX input) +{ + switch(input) { + case 0: + return "VK_OBJECT_ENTRY_TYPE_DESCRIPTOR_SET_NVX"; + case 1: + return "VK_OBJECT_ENTRY_TYPE_PIPELINE_NVX"; + case 2: + return "VK_OBJECT_ENTRY_TYPE_INDEX_BUFFER_NVX"; + case 3: + return "VK_OBJECT_ENTRY_TYPE_VERTEX_BUFFER_NVX"; + case 4: + return "VK_OBJECT_ENTRY_TYPE_PUSH_CONSTANT_NVX"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_ObjectType_to_str(VkObjectType input) +{ + switch(input) { + case 0: + return "VK_OBJECT_TYPE_UNKNOWN"; + case 1: + return "VK_OBJECT_TYPE_INSTANCE"; + case 2: + return "VK_OBJECT_TYPE_PHYSICAL_DEVICE"; + case 3: + return "VK_OBJECT_TYPE_DEVICE"; + case 4: + return "VK_OBJECT_TYPE_QUEUE"; + case 5: + return "VK_OBJECT_TYPE_SEMAPHORE"; + case 6: + return "VK_OBJECT_TYPE_COMMAND_BUFFER"; + case 7: + return "VK_OBJECT_TYPE_FENCE"; + case 8: + return "VK_OBJECT_TYPE_DEVICE_MEMORY"; + case 9: + return "VK_OBJECT_TYPE_BUFFER"; + case 10: + return "VK_OBJECT_TYPE_IMAGE"; + case 11: + return "VK_OBJECT_TYPE_EVENT"; + case 12: + return "VK_OBJECT_TYPE_QUERY_POOL"; + case 13: + return "VK_OBJECT_TYPE_BUFFER_VIEW"; + case 14: + return "VK_OBJECT_TYPE_IMAGE_VIEW"; + case 15: + return "VK_OBJECT_TYPE_SHADER_MODULE"; + case 16: + return "VK_OBJECT_TYPE_PIPELINE_CACHE"; + case 17: + return "VK_OBJECT_TYPE_PIPELINE_LAYOUT"; + case 18: + return "VK_OBJECT_TYPE_RENDER_PASS"; + case 19: + return "VK_OBJECT_TYPE_PIPELINE"; + case 20: + return "VK_OBJECT_TYPE_DESCRIPTOR_SET_LAYOUT"; + case 21: + return "VK_OBJECT_TYPE_SAMPLER"; + case 22: + return "VK_OBJECT_TYPE_DESCRIPTOR_POOL"; + case 23: + return "VK_OBJECT_TYPE_DESCRIPTOR_SET"; + case 24: + return "VK_OBJECT_TYPE_FRAMEBUFFER"; + case 25: + return "VK_OBJECT_TYPE_COMMAND_POOL"; + case 1000000000: + return "VK_OBJECT_TYPE_SURFACE_KHR"; + case 1000001000: + return "VK_OBJECT_TYPE_SWAPCHAIN_KHR"; + case 1000002000: + return "VK_OBJECT_TYPE_DISPLAY_KHR"; + case 1000002001: + return "VK_OBJECT_TYPE_DISPLAY_MODE_KHR"; + case 1000011000: + return "VK_OBJECT_TYPE_DEBUG_REPORT_CALLBACK_EXT"; + case 1000085000: + return "VK_OBJECT_TYPE_DESCRIPTOR_UPDATE_TEMPLATE"; + case 1000086000: + return "VK_OBJECT_TYPE_OBJECT_TABLE_NVX"; + case 1000086001: + return "VK_OBJECT_TYPE_INDIRECT_COMMANDS_LAYOUT_NVX"; + case 1000128000: + return "VK_OBJECT_TYPE_DEBUG_UTILS_MESSENGER_EXT"; + case 1000156000: + return "VK_OBJECT_TYPE_SAMPLER_YCBCR_CONVERSION"; + case 1000160000: + return "VK_OBJECT_TYPE_VALIDATION_CACHE_EXT"; + case 1000165000: + return "VK_OBJECT_TYPE_ACCELERATION_STRUCTURE_NV"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_PhysicalDeviceType_to_str(VkPhysicalDeviceType input) +{ + switch(input) { + case 0: + return "VK_PHYSICAL_DEVICE_TYPE_OTHER"; + case 1: + return "VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU"; + case 2: + return "VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU"; + case 3: + return "VK_PHYSICAL_DEVICE_TYPE_VIRTUAL_GPU"; + case 4: + return "VK_PHYSICAL_DEVICE_TYPE_CPU"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_PipelineBindPoint_to_str(VkPipelineBindPoint input) +{ + switch(input) { + case 0: + return "VK_PIPELINE_BIND_POINT_GRAPHICS"; + case 1: + return "VK_PIPELINE_BIND_POINT_COMPUTE"; + case 1000165000: + return "VK_PIPELINE_BIND_POINT_RAY_TRACING_NV"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_PipelineCacheHeaderVersion_to_str(VkPipelineCacheHeaderVersion input) +{ + switch(input) { + case 1: + return "VK_PIPELINE_CACHE_HEADER_VERSION_ONE"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_PointClippingBehavior_to_str(VkPointClippingBehavior input) +{ + switch(input) { + case 0: + return "VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES"; + case 1: + return "VK_POINT_CLIPPING_BEHAVIOR_USER_CLIP_PLANES_ONLY"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_PolygonMode_to_str(VkPolygonMode input) +{ + switch(input) { + case 0: + return "VK_POLYGON_MODE_FILL"; + case 1: + return "VK_POLYGON_MODE_LINE"; + case 2: + return "VK_POLYGON_MODE_POINT"; + case 1000153000: + return "VK_POLYGON_MODE_FILL_RECTANGLE_NV"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_PresentModeKHR_to_str(VkPresentModeKHR input) +{ + switch(input) { + case 0: + return "VK_PRESENT_MODE_IMMEDIATE_KHR"; + case 1: + return "VK_PRESENT_MODE_MAILBOX_KHR"; + case 2: + return "VK_PRESENT_MODE_FIFO_KHR"; + case 3: + return "VK_PRESENT_MODE_FIFO_RELAXED_KHR"; + case 1000111000: + return "VK_PRESENT_MODE_SHARED_DEMAND_REFRESH_KHR"; + case 1000111001: + return "VK_PRESENT_MODE_SHARED_CONTINUOUS_REFRESH_KHR"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_PrimitiveTopology_to_str(VkPrimitiveTopology input) +{ + switch(input) { + case 0: + return "VK_PRIMITIVE_TOPOLOGY_POINT_LIST"; + case 1: + return "VK_PRIMITIVE_TOPOLOGY_LINE_LIST"; + case 2: + return "VK_PRIMITIVE_TOPOLOGY_LINE_STRIP"; + case 3: + return "VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST"; + case 4: + return "VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP"; + case 5: + return "VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN"; + case 6: + return "VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY"; + case 7: + return "VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY"; + case 8: + return "VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY"; + case 9: + return "VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY"; + case 10: + return "VK_PRIMITIVE_TOPOLOGY_PATCH_LIST"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_QueryType_to_str(VkQueryType input) +{ + switch(input) { + case 0: + return "VK_QUERY_TYPE_OCCLUSION"; + case 1: + return "VK_QUERY_TYPE_PIPELINE_STATISTICS"; + case 2: + return "VK_QUERY_TYPE_TIMESTAMP"; + case 1000028004: + return "VK_QUERY_TYPE_TRANSFORM_FEEDBACK_STREAM_EXT"; + case 1000165000: + return "VK_QUERY_TYPE_ACCELERATION_STRUCTURE_COMPACTED_SIZE_NV"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_QueueGlobalPriorityEXT_to_str(VkQueueGlobalPriorityEXT input) +{ + switch(input) { + case 128: + return "VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT"; + case 256: + return "VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT"; + case 512: + return "VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT"; + case 1024: + return "VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_RasterizationOrderAMD_to_str(VkRasterizationOrderAMD input) +{ + switch(input) { + case 0: + return "VK_RASTERIZATION_ORDER_STRICT_AMD"; + case 1: + return "VK_RASTERIZATION_ORDER_RELAXED_AMD"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_RayTracingShaderGroupTypeNV_to_str(VkRayTracingShaderGroupTypeNV input) +{ + switch(input) { + case 0: + return "VK_RAY_TRACING_SHADER_GROUP_TYPE_GENERAL_NV"; + case 1: + return "VK_RAY_TRACING_SHADER_GROUP_TYPE_TRIANGLES_HIT_GROUP_NV"; + case 2: + return "VK_RAY_TRACING_SHADER_GROUP_TYPE_PROCEDURAL_HIT_GROUP_NV"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_Result_to_str(VkResult input) +{ + switch(input) { + case -1000244000: + return "VK_ERROR_INVALID_DEVICE_ADDRESS_EXT"; + case -1000174001: + return "VK_ERROR_NOT_PERMITTED_EXT"; + case -1000161000: + return "VK_ERROR_FRAGMENTATION_EXT"; + case -1000158000: + return "VK_ERROR_INVALID_DRM_FORMAT_MODIFIER_PLANE_LAYOUT_EXT"; + case -1000072003: + return "VK_ERROR_INVALID_EXTERNAL_HANDLE"; + case -1000069000: + return "VK_ERROR_OUT_OF_POOL_MEMORY"; + case -1000012000: + return "VK_ERROR_INVALID_SHADER_NV"; + case -1000011001: + return "VK_ERROR_VALIDATION_FAILED_EXT"; + case -1000003001: + return "VK_ERROR_INCOMPATIBLE_DISPLAY_KHR"; + case -1000001004: + return "VK_ERROR_OUT_OF_DATE_KHR"; + case -1000000001: + return "VK_ERROR_NATIVE_WINDOW_IN_USE_KHR"; + case -1000000000: + return "VK_ERROR_SURFACE_LOST_KHR"; + case -12: + return "VK_ERROR_FRAGMENTED_POOL"; + case -11: + return "VK_ERROR_FORMAT_NOT_SUPPORTED"; + case -10: + return "VK_ERROR_TOO_MANY_OBJECTS"; + case -9: + return "VK_ERROR_INCOMPATIBLE_DRIVER"; + case -8: + return "VK_ERROR_FEATURE_NOT_PRESENT"; + case -7: + return "VK_ERROR_EXTENSION_NOT_PRESENT"; + case -6: + return "VK_ERROR_LAYER_NOT_PRESENT"; + case -5: + return "VK_ERROR_MEMORY_MAP_FAILED"; + case -4: + return "VK_ERROR_DEVICE_LOST"; + case -3: + return "VK_ERROR_INITIALIZATION_FAILED"; + case -2: + return "VK_ERROR_OUT_OF_DEVICE_MEMORY"; + case -1: + return "VK_ERROR_OUT_OF_HOST_MEMORY"; + case 0: + return "VK_SUCCESS"; + case 1: + return "VK_NOT_READY"; + case 2: + return "VK_TIMEOUT"; + case 3: + return "VK_EVENT_SET"; + case 4: + return "VK_EVENT_RESET"; + case 5: + return "VK_INCOMPLETE"; + case 1000001003: + return "VK_SUBOPTIMAL_KHR"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_SamplerAddressMode_to_str(VkSamplerAddressMode input) +{ + switch(input) { + case 0: + return "VK_SAMPLER_ADDRESS_MODE_REPEAT"; + case 1: + return "VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT"; + case 2: + return "VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE"; + case 3: + return "VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER"; + case 4: + return "VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_SamplerMipmapMode_to_str(VkSamplerMipmapMode input) +{ + switch(input) { + case 0: + return "VK_SAMPLER_MIPMAP_MODE_NEAREST"; + case 1: + return "VK_SAMPLER_MIPMAP_MODE_LINEAR"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_SamplerReductionModeEXT_to_str(VkSamplerReductionModeEXT input) +{ + switch(input) { + case 0: + return "VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT"; + case 1: + return "VK_SAMPLER_REDUCTION_MODE_MIN_EXT"; + case 2: + return "VK_SAMPLER_REDUCTION_MODE_MAX_EXT"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_SamplerYcbcrModelConversion_to_str(VkSamplerYcbcrModelConversion input) +{ + switch(input) { + case 0: + return "VK_SAMPLER_YCBCR_MODEL_CONVERSION_RGB_IDENTITY"; + case 1: + return "VK_SAMPLER_YCBCR_MODEL_CONVERSION_YCBCR_IDENTITY"; + case 2: + return "VK_SAMPLER_YCBCR_MODEL_CONVERSION_YCBCR_709"; + case 3: + return "VK_SAMPLER_YCBCR_MODEL_CONVERSION_YCBCR_601"; + case 4: + return "VK_SAMPLER_YCBCR_MODEL_CONVERSION_YCBCR_2020"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_SamplerYcbcrRange_to_str(VkSamplerYcbcrRange input) +{ + switch(input) { + case 0: + return "VK_SAMPLER_YCBCR_RANGE_ITU_FULL"; + case 1: + return "VK_SAMPLER_YCBCR_RANGE_ITU_NARROW"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_ShaderInfoTypeAMD_to_str(VkShaderInfoTypeAMD input) +{ + switch(input) { + case 0: + return "VK_SHADER_INFO_TYPE_STATISTICS_AMD"; + case 1: + return "VK_SHADER_INFO_TYPE_BINARY_AMD"; + case 2: + return "VK_SHADER_INFO_TYPE_DISASSEMBLY_AMD"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_ShadingRatePaletteEntryNV_to_str(VkShadingRatePaletteEntryNV input) +{ + switch(input) { + case 0: + return "VK_SHADING_RATE_PALETTE_ENTRY_NO_INVOCATIONS_NV"; + case 1: + return "VK_SHADING_RATE_PALETTE_ENTRY_16_INVOCATIONS_PER_PIXEL_NV"; + case 2: + return "VK_SHADING_RATE_PALETTE_ENTRY_8_INVOCATIONS_PER_PIXEL_NV"; + case 3: + return "VK_SHADING_RATE_PALETTE_ENTRY_4_INVOCATIONS_PER_PIXEL_NV"; + case 4: + return "VK_SHADING_RATE_PALETTE_ENTRY_2_INVOCATIONS_PER_PIXEL_NV"; + case 5: + return "VK_SHADING_RATE_PALETTE_ENTRY_1_INVOCATION_PER_PIXEL_NV"; + case 6: + return "VK_SHADING_RATE_PALETTE_ENTRY_1_INVOCATION_PER_2X1_PIXELS_NV"; + case 7: + return "VK_SHADING_RATE_PALETTE_ENTRY_1_INVOCATION_PER_1X2_PIXELS_NV"; + case 8: + return "VK_SHADING_RATE_PALETTE_ENTRY_1_INVOCATION_PER_2X2_PIXELS_NV"; + case 9: + return "VK_SHADING_RATE_PALETTE_ENTRY_1_INVOCATION_PER_4X2_PIXELS_NV"; + case 10: + return "VK_SHADING_RATE_PALETTE_ENTRY_1_INVOCATION_PER_2X4_PIXELS_NV"; + case 11: + return "VK_SHADING_RATE_PALETTE_ENTRY_1_INVOCATION_PER_4X4_PIXELS_NV"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_SharingMode_to_str(VkSharingMode input) +{ + switch(input) { + case 0: + return "VK_SHARING_MODE_EXCLUSIVE"; + case 1: + return "VK_SHARING_MODE_CONCURRENT"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_StencilOp_to_str(VkStencilOp input) +{ + switch(input) { + case 0: + return "VK_STENCIL_OP_KEEP"; + case 1: + return "VK_STENCIL_OP_ZERO"; + case 2: + return "VK_STENCIL_OP_REPLACE"; + case 3: + return "VK_STENCIL_OP_INCREMENT_AND_CLAMP"; + case 4: + return "VK_STENCIL_OP_DECREMENT_AND_CLAMP"; + case 5: + return "VK_STENCIL_OP_INVERT"; + case 6: + return "VK_STENCIL_OP_INCREMENT_AND_WRAP"; + case 7: + return "VK_STENCIL_OP_DECREMENT_AND_WRAP"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_StructureType_to_str(VkStructureType input) +{ + switch(input) { + case 0: + return "VK_STRUCTURE_TYPE_APPLICATION_INFO"; + case 1: + return "VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO"; + case 2: + return "VK_STRUCTURE_TYPE_DEVICE_QUEUE_CREATE_INFO"; + case 3: + return "VK_STRUCTURE_TYPE_DEVICE_CREATE_INFO"; + case 4: + return "VK_STRUCTURE_TYPE_SUBMIT_INFO"; + case 5: + return "VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO"; + case 6: + return "VK_STRUCTURE_TYPE_MAPPED_MEMORY_RANGE"; + case 7: + return "VK_STRUCTURE_TYPE_BIND_SPARSE_INFO"; + case 8: + return "VK_STRUCTURE_TYPE_FENCE_CREATE_INFO"; + case 9: + return "VK_STRUCTURE_TYPE_SEMAPHORE_CREATE_INFO"; + case 10: + return "VK_STRUCTURE_TYPE_EVENT_CREATE_INFO"; + case 11: + return "VK_STRUCTURE_TYPE_QUERY_POOL_CREATE_INFO"; + case 12: + return "VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO"; + case 13: + return "VK_STRUCTURE_TYPE_BUFFER_VIEW_CREATE_INFO"; + case 14: + return "VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO"; + case 15: + return "VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO"; + case 16: + return "VK_STRUCTURE_TYPE_SHADER_MODULE_CREATE_INFO"; + case 17: + return "VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO"; + case 18: + return "VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO"; + case 19: + return "VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO"; + case 20: + return "VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO"; + case 21: + return "VK_STRUCTURE_TYPE_PIPELINE_TESSELLATION_STATE_CREATE_INFO"; + case 22: + return "VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO"; + case 23: + return "VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO"; + case 24: + return "VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO"; + case 25: + return "VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO"; + case 26: + return "VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO"; + case 27: + return "VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO"; + case 28: + return "VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO"; + case 29: + return "VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO"; + case 30: + return "VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO"; + case 31: + return "VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO"; + case 32: + return "VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO"; + case 33: + return "VK_STRUCTURE_TYPE_DESCRIPTOR_POOL_CREATE_INFO"; + case 34: + return "VK_STRUCTURE_TYPE_DESCRIPTOR_SET_ALLOCATE_INFO"; + case 35: + return "VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET"; + case 36: + return "VK_STRUCTURE_TYPE_COPY_DESCRIPTOR_SET"; + case 37: + return "VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO"; + case 38: + return "VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO"; + case 39: + return "VK_STRUCTURE_TYPE_COMMAND_POOL_CREATE_INFO"; + case 40: + return "VK_STRUCTURE_TYPE_COMMAND_BUFFER_ALLOCATE_INFO"; + case 41: + return "VK_STRUCTURE_TYPE_COMMAND_BUFFER_INHERITANCE_INFO"; + case 42: + return "VK_STRUCTURE_TYPE_COMMAND_BUFFER_BEGIN_INFO"; + case 43: + return "VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO"; + case 44: + return "VK_STRUCTURE_TYPE_BUFFER_MEMORY_BARRIER"; + case 45: + return "VK_STRUCTURE_TYPE_IMAGE_MEMORY_BARRIER"; + case 46: + return "VK_STRUCTURE_TYPE_MEMORY_BARRIER"; + case 47: + return "VK_STRUCTURE_TYPE_LOADER_INSTANCE_CREATE_INFO"; + case 48: + return "VK_STRUCTURE_TYPE_LOADER_DEVICE_CREATE_INFO"; + case 1000001000: + return "VK_STRUCTURE_TYPE_SWAPCHAIN_CREATE_INFO_KHR"; + case 1000001001: + return "VK_STRUCTURE_TYPE_PRESENT_INFO_KHR"; + case 1000002000: + return "VK_STRUCTURE_TYPE_DISPLAY_MODE_CREATE_INFO_KHR"; + case 1000002001: + return "VK_STRUCTURE_TYPE_DISPLAY_SURFACE_CREATE_INFO_KHR"; + case 1000003000: + return "VK_STRUCTURE_TYPE_DISPLAY_PRESENT_INFO_KHR"; + case 1000004000: + return "VK_STRUCTURE_TYPE_XLIB_SURFACE_CREATE_INFO_KHR"; + case 1000005000: + return "VK_STRUCTURE_TYPE_XCB_SURFACE_CREATE_INFO_KHR"; + case 1000006000: + return "VK_STRUCTURE_TYPE_WAYLAND_SURFACE_CREATE_INFO_KHR"; + case 1000008000: + return "VK_STRUCTURE_TYPE_ANDROID_SURFACE_CREATE_INFO_KHR"; + case 1000009000: + return "VK_STRUCTURE_TYPE_WIN32_SURFACE_CREATE_INFO_KHR"; + case 1000011000: + return "VK_STRUCTURE_TYPE_DEBUG_REPORT_CREATE_INFO_EXT"; + case 1000018000: + return "VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD"; + case 1000022000: + return "VK_STRUCTURE_TYPE_DEBUG_MARKER_OBJECT_NAME_INFO_EXT"; + case 1000022001: + return "VK_STRUCTURE_TYPE_DEBUG_MARKER_OBJECT_TAG_INFO_EXT"; + case 1000022002: + return "VK_STRUCTURE_TYPE_DEBUG_MARKER_MARKER_INFO_EXT"; + case 1000026000: + return "VK_STRUCTURE_TYPE_DEDICATED_ALLOCATION_IMAGE_CREATE_INFO_NV"; + case 1000026001: + return "VK_STRUCTURE_TYPE_DEDICATED_ALLOCATION_BUFFER_CREATE_INFO_NV"; + case 1000026002: + return "VK_STRUCTURE_TYPE_DEDICATED_ALLOCATION_MEMORY_ALLOCATE_INFO_NV"; + case 1000028000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT"; + case 1000028001: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT"; + case 1000028002: + return "VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_STREAM_CREATE_INFO_EXT"; + case 1000041000: + return "VK_STRUCTURE_TYPE_TEXTURE_LOD_GATHER_FORMAT_PROPERTIES_AMD"; + case 1000050000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CORNER_SAMPLED_IMAGE_FEATURES_NV"; + case 1000053000: + return "VK_STRUCTURE_TYPE_RENDER_PASS_MULTIVIEW_CREATE_INFO"; + case 1000053001: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES"; + case 1000053002: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES"; + case 1000056000: + return "VK_STRUCTURE_TYPE_EXTERNAL_MEMORY_IMAGE_CREATE_INFO_NV"; + case 1000056001: + return "VK_STRUCTURE_TYPE_EXPORT_MEMORY_ALLOCATE_INFO_NV"; + case 1000057000: + return "VK_STRUCTURE_TYPE_IMPORT_MEMORY_WIN32_HANDLE_INFO_NV"; + case 1000057001: + return "VK_STRUCTURE_TYPE_EXPORT_MEMORY_WIN32_HANDLE_INFO_NV"; + case 1000058000: + return "VK_STRUCTURE_TYPE_WIN32_KEYED_MUTEX_ACQUIRE_RELEASE_INFO_NV"; + case 1000059000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FEATURES_2"; + case 1000059001: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROPERTIES_2"; + case 1000059002: + return "VK_STRUCTURE_TYPE_FORMAT_PROPERTIES_2"; + case 1000059003: + return "VK_STRUCTURE_TYPE_IMAGE_FORMAT_PROPERTIES_2"; + case 1000059004: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGE_FORMAT_INFO_2"; + case 1000059005: + return "VK_STRUCTURE_TYPE_QUEUE_FAMILY_PROPERTIES_2"; + case 1000059006: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PROPERTIES_2"; + case 1000059007: + return "VK_STRUCTURE_TYPE_SPARSE_IMAGE_FORMAT_PROPERTIES_2"; + case 1000059008: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SPARSE_IMAGE_FORMAT_INFO_2"; + case 1000060000: + return "VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_FLAGS_INFO"; + case 1000060003: + return "VK_STRUCTURE_TYPE_DEVICE_GROUP_RENDER_PASS_BEGIN_INFO"; + case 1000060004: + return "VK_STRUCTURE_TYPE_DEVICE_GROUP_COMMAND_BUFFER_BEGIN_INFO"; + case 1000060005: + return "VK_STRUCTURE_TYPE_DEVICE_GROUP_SUBMIT_INFO"; + case 1000060006: + return "VK_STRUCTURE_TYPE_DEVICE_GROUP_BIND_SPARSE_INFO"; + case 1000060007: + return "VK_STRUCTURE_TYPE_DEVICE_GROUP_PRESENT_CAPABILITIES_KHR"; + case 1000060008: + return "VK_STRUCTURE_TYPE_IMAGE_SWAPCHAIN_CREATE_INFO_KHR"; + case 1000060009: + return "VK_STRUCTURE_TYPE_BIND_IMAGE_MEMORY_SWAPCHAIN_INFO_KHR"; + case 1000060010: + return "VK_STRUCTURE_TYPE_ACQUIRE_NEXT_IMAGE_INFO_KHR"; + case 1000060011: + return "VK_STRUCTURE_TYPE_DEVICE_GROUP_PRESENT_INFO_KHR"; + case 1000060012: + return "VK_STRUCTURE_TYPE_DEVICE_GROUP_SWAPCHAIN_CREATE_INFO_KHR"; + case 1000060013: + return "VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_DEVICE_GROUP_INFO"; + case 1000060014: + return "VK_STRUCTURE_TYPE_BIND_IMAGE_MEMORY_DEVICE_GROUP_INFO"; + case 1000061000: + return "VK_STRUCTURE_TYPE_VALIDATION_FLAGS_EXT"; + case 1000062000: + return "VK_STRUCTURE_TYPE_VI_SURFACE_CREATE_INFO_NN"; + case 1000063000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES"; + case 1000067000: + return "VK_STRUCTURE_TYPE_IMAGE_VIEW_ASTC_DECODE_MODE_EXT"; + case 1000067001: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ASTC_DECODE_FEATURES_EXT"; + case 1000070000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_GROUP_PROPERTIES"; + case 1000070001: + return "VK_STRUCTURE_TYPE_DEVICE_GROUP_DEVICE_CREATE_INFO"; + case 1000071000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_IMAGE_FORMAT_INFO"; + case 1000071001: + return "VK_STRUCTURE_TYPE_EXTERNAL_IMAGE_FORMAT_PROPERTIES"; + case 1000071002: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_BUFFER_INFO"; + case 1000071003: + return "VK_STRUCTURE_TYPE_EXTERNAL_BUFFER_PROPERTIES"; + case 1000071004: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES"; + case 1000072000: + return "VK_STRUCTURE_TYPE_EXTERNAL_MEMORY_BUFFER_CREATE_INFO"; + case 1000072001: + return "VK_STRUCTURE_TYPE_EXTERNAL_MEMORY_IMAGE_CREATE_INFO"; + case 1000072002: + return "VK_STRUCTURE_TYPE_EXPORT_MEMORY_ALLOCATE_INFO"; + case 1000073000: + return "VK_STRUCTURE_TYPE_IMPORT_MEMORY_WIN32_HANDLE_INFO_KHR"; + case 1000073001: + return "VK_STRUCTURE_TYPE_EXPORT_MEMORY_WIN32_HANDLE_INFO_KHR"; + case 1000073002: + return "VK_STRUCTURE_TYPE_MEMORY_WIN32_HANDLE_PROPERTIES_KHR"; + case 1000073003: + return "VK_STRUCTURE_TYPE_MEMORY_GET_WIN32_HANDLE_INFO_KHR"; + case 1000074000: + return "VK_STRUCTURE_TYPE_IMPORT_MEMORY_FD_INFO_KHR"; + case 1000074001: + return "VK_STRUCTURE_TYPE_MEMORY_FD_PROPERTIES_KHR"; + case 1000074002: + return "VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR"; + case 1000075000: + return "VK_STRUCTURE_TYPE_WIN32_KEYED_MUTEX_ACQUIRE_RELEASE_INFO_KHR"; + case 1000076000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_SEMAPHORE_INFO"; + case 1000076001: + return "VK_STRUCTURE_TYPE_EXTERNAL_SEMAPHORE_PROPERTIES"; + case 1000077000: + return "VK_STRUCTURE_TYPE_EXPORT_SEMAPHORE_CREATE_INFO"; + case 1000078000: + return "VK_STRUCTURE_TYPE_IMPORT_SEMAPHORE_WIN32_HANDLE_INFO_KHR"; + case 1000078001: + return "VK_STRUCTURE_TYPE_EXPORT_SEMAPHORE_WIN32_HANDLE_INFO_KHR"; + case 1000078002: + return "VK_STRUCTURE_TYPE_D3D12_FENCE_SUBMIT_INFO_KHR"; + case 1000078003: + return "VK_STRUCTURE_TYPE_SEMAPHORE_GET_WIN32_HANDLE_INFO_KHR"; + case 1000079000: + return "VK_STRUCTURE_TYPE_IMPORT_SEMAPHORE_FD_INFO_KHR"; + case 1000079001: + return "VK_STRUCTURE_TYPE_SEMAPHORE_GET_FD_INFO_KHR"; + case 1000080000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR"; + case 1000081000: + return "VK_STRUCTURE_TYPE_COMMAND_BUFFER_INHERITANCE_CONDITIONAL_RENDERING_INFO_EXT"; + case 1000081001: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT"; + case 1000081002: + return "VK_STRUCTURE_TYPE_CONDITIONAL_RENDERING_BEGIN_INFO_EXT"; + case 1000082000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR"; + case 1000083000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES"; + case 1000084000: + return "VK_STRUCTURE_TYPE_PRESENT_REGIONS_KHR"; + case 1000085000: + return "VK_STRUCTURE_TYPE_DESCRIPTOR_UPDATE_TEMPLATE_CREATE_INFO"; + case 1000086000: + return "VK_STRUCTURE_TYPE_OBJECT_TABLE_CREATE_INFO_NVX"; + case 1000086001: + return "VK_STRUCTURE_TYPE_INDIRECT_COMMANDS_LAYOUT_CREATE_INFO_NVX"; + case 1000086002: + return "VK_STRUCTURE_TYPE_CMD_PROCESS_COMMANDS_INFO_NVX"; + case 1000086003: + return "VK_STRUCTURE_TYPE_CMD_RESERVE_SPACE_FOR_COMMANDS_INFO_NVX"; + case 1000086004: + return "VK_STRUCTURE_TYPE_DEVICE_GENERATED_COMMANDS_LIMITS_NVX"; + case 1000086005: + return "VK_STRUCTURE_TYPE_DEVICE_GENERATED_COMMANDS_FEATURES_NVX"; + case 1000087000: + return "VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_W_SCALING_STATE_CREATE_INFO_NV"; + case 1000090000: + return "VK_STRUCTURE_TYPE_SURFACE_CAPABILITIES2_EXT"; + case 1000091000: + return "VK_STRUCTURE_TYPE_DISPLAY_POWER_INFO_EXT"; + case 1000091001: + return "VK_STRUCTURE_TYPE_DEVICE_EVENT_INFO_EXT"; + case 1000091002: + return "VK_STRUCTURE_TYPE_DISPLAY_EVENT_INFO_EXT"; + case 1000091003: + return "VK_STRUCTURE_TYPE_SWAPCHAIN_COUNTER_CREATE_INFO_EXT"; + case 1000092000: + return "VK_STRUCTURE_TYPE_PRESENT_TIMES_INFO_GOOGLE"; + case 1000094000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES"; + case 1000097000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PER_VIEW_ATTRIBUTES_PROPERTIES_NVX"; + case 1000098000: + return "VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_SWIZZLE_STATE_CREATE_INFO_NV"; + case 1000099000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT"; + case 1000099001: + return "VK_STRUCTURE_TYPE_PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT"; + case 1000101000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT"; + case 1000101001: + return "VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT"; + case 1000105000: + return "VK_STRUCTURE_TYPE_HDR_METADATA_EXT"; + case 1000109000: + return "VK_STRUCTURE_TYPE_ATTACHMENT_DESCRIPTION_2_KHR"; + case 1000109001: + return "VK_STRUCTURE_TYPE_ATTACHMENT_REFERENCE_2_KHR"; + case 1000109002: + return "VK_STRUCTURE_TYPE_SUBPASS_DESCRIPTION_2_KHR"; + case 1000109003: + return "VK_STRUCTURE_TYPE_SUBPASS_DEPENDENCY_2_KHR"; + case 1000109004: + return "VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO_2_KHR"; + case 1000109005: + return "VK_STRUCTURE_TYPE_SUBPASS_BEGIN_INFO_KHR"; + case 1000109006: + return "VK_STRUCTURE_TYPE_SUBPASS_END_INFO_KHR"; + case 1000111000: + return "VK_STRUCTURE_TYPE_SHARED_PRESENT_SURFACE_CAPABILITIES_KHR"; + case 1000112000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_FENCE_INFO"; + case 1000112001: + return "VK_STRUCTURE_TYPE_EXTERNAL_FENCE_PROPERTIES"; + case 1000113000: + return "VK_STRUCTURE_TYPE_EXPORT_FENCE_CREATE_INFO"; + case 1000114000: + return "VK_STRUCTURE_TYPE_IMPORT_FENCE_WIN32_HANDLE_INFO_KHR"; + case 1000114001: + return "VK_STRUCTURE_TYPE_EXPORT_FENCE_WIN32_HANDLE_INFO_KHR"; + case 1000114002: + return "VK_STRUCTURE_TYPE_FENCE_GET_WIN32_HANDLE_INFO_KHR"; + case 1000115000: + return "VK_STRUCTURE_TYPE_IMPORT_FENCE_FD_INFO_KHR"; + case 1000115001: + return "VK_STRUCTURE_TYPE_FENCE_GET_FD_INFO_KHR"; + case 1000117000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES"; + case 1000117001: + return "VK_STRUCTURE_TYPE_RENDER_PASS_INPUT_ATTACHMENT_ASPECT_CREATE_INFO"; + case 1000117002: + return "VK_STRUCTURE_TYPE_IMAGE_VIEW_USAGE_CREATE_INFO"; + case 1000117003: + return "VK_STRUCTURE_TYPE_PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO"; + case 1000119000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SURFACE_INFO_2_KHR"; + case 1000119001: + return "VK_STRUCTURE_TYPE_SURFACE_CAPABILITIES_2_KHR"; + case 1000119002: + return "VK_STRUCTURE_TYPE_SURFACE_FORMAT_2_KHR"; + case 1000120000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES"; + case 1000121000: + return "VK_STRUCTURE_TYPE_DISPLAY_PROPERTIES_2_KHR"; + case 1000121001: + return "VK_STRUCTURE_TYPE_DISPLAY_PLANE_PROPERTIES_2_KHR"; + case 1000121002: + return "VK_STRUCTURE_TYPE_DISPLAY_MODE_PROPERTIES_2_KHR"; + case 1000121003: + return "VK_STRUCTURE_TYPE_DISPLAY_PLANE_INFO_2_KHR"; + case 1000121004: + return "VK_STRUCTURE_TYPE_DISPLAY_PLANE_CAPABILITIES_2_KHR"; + case 1000122000: + return "VK_STRUCTURE_TYPE_IOS_SURFACE_CREATE_INFO_MVK"; + case 1000123000: + return "VK_STRUCTURE_TYPE_MACOS_SURFACE_CREATE_INFO_MVK"; + case 1000127000: + return "VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS"; + case 1000127001: + return "VK_STRUCTURE_TYPE_MEMORY_DEDICATED_ALLOCATE_INFO"; + case 1000128000: + return "VK_STRUCTURE_TYPE_DEBUG_UTILS_OBJECT_NAME_INFO_EXT"; + case 1000128001: + return "VK_STRUCTURE_TYPE_DEBUG_UTILS_OBJECT_TAG_INFO_EXT"; + case 1000128002: + return "VK_STRUCTURE_TYPE_DEBUG_UTILS_LABEL_EXT"; + case 1000128003: + return "VK_STRUCTURE_TYPE_DEBUG_UTILS_MESSENGER_CALLBACK_DATA_EXT"; + case 1000128004: + return "VK_STRUCTURE_TYPE_DEBUG_UTILS_MESSENGER_CREATE_INFO_EXT"; + case 1000129000: + return "VK_STRUCTURE_TYPE_ANDROID_HARDWARE_BUFFER_USAGE_ANDROID"; + case 1000129001: + return "VK_STRUCTURE_TYPE_ANDROID_HARDWARE_BUFFER_PROPERTIES_ANDROID"; + case 1000129002: + return "VK_STRUCTURE_TYPE_ANDROID_HARDWARE_BUFFER_FORMAT_PROPERTIES_ANDROID"; + case 1000129003: + return "VK_STRUCTURE_TYPE_IMPORT_ANDROID_HARDWARE_BUFFER_INFO_ANDROID"; + case 1000129004: + return "VK_STRUCTURE_TYPE_MEMORY_GET_ANDROID_HARDWARE_BUFFER_INFO_ANDROID"; + case 1000129005: + return "VK_STRUCTURE_TYPE_EXTERNAL_FORMAT_ANDROID"; + case 1000130000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT"; + case 1000130001: + return "VK_STRUCTURE_TYPE_SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT"; + case 1000138000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT"; + case 1000138001: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT"; + case 1000138002: + return "VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET_INLINE_UNIFORM_BLOCK_EXT"; + case 1000138003: + return "VK_STRUCTURE_TYPE_DESCRIPTOR_POOL_INLINE_UNIFORM_BLOCK_CREATE_INFO_EXT"; + case 1000143000: + return "VK_STRUCTURE_TYPE_SAMPLE_LOCATIONS_INFO_EXT"; + case 1000143001: + return "VK_STRUCTURE_TYPE_RENDER_PASS_SAMPLE_LOCATIONS_BEGIN_INFO_EXT"; + case 1000143002: + return "VK_STRUCTURE_TYPE_PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT"; + case 1000143003: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT"; + case 1000143004: + return "VK_STRUCTURE_TYPE_MULTISAMPLE_PROPERTIES_EXT"; + case 1000145000: + return "VK_STRUCTURE_TYPE_PROTECTED_SUBMIT_INFO"; + case 1000145001: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES"; + case 1000145002: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES"; + case 1000145003: + return "VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2"; + case 1000146000: + return "VK_STRUCTURE_TYPE_BUFFER_MEMORY_REQUIREMENTS_INFO_2"; + case 1000146001: + return "VK_STRUCTURE_TYPE_IMAGE_MEMORY_REQUIREMENTS_INFO_2"; + case 1000146002: + return "VK_STRUCTURE_TYPE_IMAGE_SPARSE_MEMORY_REQUIREMENTS_INFO_2"; + case 1000146003: + return "VK_STRUCTURE_TYPE_MEMORY_REQUIREMENTS_2"; + case 1000146004: + return "VK_STRUCTURE_TYPE_SPARSE_IMAGE_MEMORY_REQUIREMENTS_2"; + case 1000147000: + return "VK_STRUCTURE_TYPE_IMAGE_FORMAT_LIST_CREATE_INFO_KHR"; + case 1000148000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BLEND_OPERATION_ADVANCED_FEATURES_EXT"; + case 1000148001: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BLEND_OPERATION_ADVANCED_PROPERTIES_EXT"; + case 1000148002: + return "VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_ADVANCED_STATE_CREATE_INFO_EXT"; + case 1000149000: + return "VK_STRUCTURE_TYPE_PIPELINE_COVERAGE_TO_COLOR_STATE_CREATE_INFO_NV"; + case 1000152000: + return "VK_STRUCTURE_TYPE_PIPELINE_COVERAGE_MODULATION_STATE_CREATE_INFO_NV"; + case 1000156000: + return "VK_STRUCTURE_TYPE_SAMPLER_YCBCR_CONVERSION_CREATE_INFO"; + case 1000156001: + return "VK_STRUCTURE_TYPE_SAMPLER_YCBCR_CONVERSION_INFO"; + case 1000156002: + return "VK_STRUCTURE_TYPE_BIND_IMAGE_PLANE_MEMORY_INFO"; + case 1000156003: + return "VK_STRUCTURE_TYPE_IMAGE_PLANE_MEMORY_REQUIREMENTS_INFO"; + case 1000156004: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES"; + case 1000156005: + return "VK_STRUCTURE_TYPE_SAMPLER_YCBCR_CONVERSION_IMAGE_FORMAT_PROPERTIES"; + case 1000157000: + return "VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO"; + case 1000157001: + return "VK_STRUCTURE_TYPE_BIND_IMAGE_MEMORY_INFO"; + case 1000158000: + return "VK_STRUCTURE_TYPE_DRM_FORMAT_MODIFIER_PROPERTIES_LIST_EXT"; + case 1000158001: + return "VK_STRUCTURE_TYPE_DRM_FORMAT_MODIFIER_PROPERTIES_EXT"; + case 1000158002: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGE_DRM_FORMAT_MODIFIER_INFO_EXT"; + case 1000158003: + return "VK_STRUCTURE_TYPE_IMAGE_DRM_FORMAT_MODIFIER_LIST_CREATE_INFO_EXT"; + case 1000158004: + return "VK_STRUCTURE_TYPE_IMAGE_DRM_FORMAT_MODIFIER_EXPLICIT_CREATE_INFO_EXT"; + case 1000158005: + return "VK_STRUCTURE_TYPE_IMAGE_DRM_FORMAT_MODIFIER_PROPERTIES_EXT"; + case 1000160000: + return "VK_STRUCTURE_TYPE_VALIDATION_CACHE_CREATE_INFO_EXT"; + case 1000160001: + return "VK_STRUCTURE_TYPE_SHADER_MODULE_VALIDATION_CACHE_CREATE_INFO_EXT"; + case 1000161000: + return "VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_BINDING_FLAGS_CREATE_INFO_EXT"; + case 1000161001: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT"; + case 1000161002: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT"; + case 1000161003: + return "VK_STRUCTURE_TYPE_DESCRIPTOR_SET_VARIABLE_DESCRIPTOR_COUNT_ALLOCATE_INFO_EXT"; + case 1000161004: + return "VK_STRUCTURE_TYPE_DESCRIPTOR_SET_VARIABLE_DESCRIPTOR_COUNT_LAYOUT_SUPPORT_EXT"; + case 1000164000: + return "VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_SHADING_RATE_IMAGE_STATE_CREATE_INFO_NV"; + case 1000164001: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADING_RATE_IMAGE_FEATURES_NV"; + case 1000164002: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADING_RATE_IMAGE_PROPERTIES_NV"; + case 1000164005: + return "VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_COARSE_SAMPLE_ORDER_STATE_CREATE_INFO_NV"; + case 1000165000: + return "VK_STRUCTURE_TYPE_RAY_TRACING_PIPELINE_CREATE_INFO_NV"; + case 1000165001: + return "VK_STRUCTURE_TYPE_ACCELERATION_STRUCTURE_CREATE_INFO_NV"; + case 1000165003: + return "VK_STRUCTURE_TYPE_GEOMETRY_NV"; + case 1000165004: + return "VK_STRUCTURE_TYPE_GEOMETRY_TRIANGLES_NV"; + case 1000165005: + return "VK_STRUCTURE_TYPE_GEOMETRY_AABB_NV"; + case 1000165006: + return "VK_STRUCTURE_TYPE_BIND_ACCELERATION_STRUCTURE_MEMORY_INFO_NV"; + case 1000165007: + return "VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET_ACCELERATION_STRUCTURE_NV"; + case 1000165008: + return "VK_STRUCTURE_TYPE_ACCELERATION_STRUCTURE_MEMORY_REQUIREMENTS_INFO_NV"; + case 1000165009: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_RAY_TRACING_PROPERTIES_NV"; + case 1000165011: + return "VK_STRUCTURE_TYPE_RAY_TRACING_SHADER_GROUP_CREATE_INFO_NV"; + case 1000165012: + return "VK_STRUCTURE_TYPE_ACCELERATION_STRUCTURE_INFO_NV"; + case 1000166000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_REPRESENTATIVE_FRAGMENT_TEST_FEATURES_NV"; + case 1000166001: + return "VK_STRUCTURE_TYPE_PIPELINE_REPRESENTATIVE_FRAGMENT_TEST_STATE_CREATE_INFO_NV"; + case 1000168000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES"; + case 1000168001: + return "VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_SUPPORT"; + case 1000174000: + return "VK_STRUCTURE_TYPE_DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT"; + case 1000177000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR"; + case 1000178000: + return "VK_STRUCTURE_TYPE_IMPORT_MEMORY_HOST_POINTER_INFO_EXT"; + case 1000178001: + return "VK_STRUCTURE_TYPE_MEMORY_HOST_POINTER_PROPERTIES_EXT"; + case 1000178002: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT"; + case 1000180000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR"; + case 1000184000: + return "VK_STRUCTURE_TYPE_CALIBRATED_TIMESTAMP_INFO_EXT"; + case 1000185000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD"; + case 1000189000: + return "VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD"; + case 1000190000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT"; + case 1000190001: + return "VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT"; + case 1000190002: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT"; + case 1000196000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR"; + case 1000197000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT_CONTROLS_PROPERTIES_KHR"; + case 1000199000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES_KHR"; + case 1000199001: + return "VK_STRUCTURE_TYPE_SUBPASS_DESCRIPTION_DEPTH_STENCIL_RESOLVE_KHR"; + case 1000201000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV"; + case 1000202000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MESH_SHADER_FEATURES_NV"; + case 1000202001: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MESH_SHADER_PROPERTIES_NV"; + case 1000203000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FRAGMENT_SHADER_BARYCENTRIC_FEATURES_NV"; + case 1000204000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_IMAGE_FOOTPRINT_FEATURES_NV"; + case 1000205000: + return "VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_EXCLUSIVE_SCISSOR_STATE_CREATE_INFO_NV"; + case 1000205002: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXCLUSIVE_SCISSOR_FEATURES_NV"; + case 1000206000: + return "VK_STRUCTURE_TYPE_CHECKPOINT_DATA_NV"; + case 1000206001: + return "VK_STRUCTURE_TYPE_QUEUE_FAMILY_CHECKPOINT_PROPERTIES_NV"; + case 1000211000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_MEMORY_MODEL_FEATURES_KHR"; + case 1000212000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT"; + case 1000214000: + return "VK_STRUCTURE_TYPE_IMAGEPIPE_SURFACE_CREATE_INFO_FUCHSIA"; + case 1000218000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FRAGMENT_DENSITY_MAP_FEATURES_EXT"; + case 1000218001: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FRAGMENT_DENSITY_MAP_PROPERTIES_EXT"; + case 1000218002: + return "VK_STRUCTURE_TYPE_RENDER_PASS_FRAGMENT_DENSITY_MAP_CREATE_INFO_EXT"; + case 1000221000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT"; + case 1000237000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT"; + case 1000238000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT"; + case 1000238001: + return "VK_STRUCTURE_TYPE_MEMORY_PRIORITY_ALLOCATE_INFO_EXT"; + case 1000244000: + return "VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_ADDRESS_FEATURES_EXT"; + case 1000244001: + return "VK_STRUCTURE_TYPE_BUFFER_DEVICE_ADDRESS_INFO_EXT"; + case 1000244002: + return "VK_STRUCTURE_TYPE_BUFFER_DEVICE_ADDRESS_CREATE_INFO_EXT"; + case 1000246000: + return "VK_STRUCTURE_TYPE_IMAGE_STENCIL_USAGE_CREATE_INFO_EXT"; + case 1000247000: + return "VK_STRUCTURE_TYPE_VALIDATION_FEATURES_EXT"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_SubpassContents_to_str(VkSubpassContents input) +{ + switch(input) { + case 0: + return "VK_SUBPASS_CONTENTS_INLINE"; + case 1: + return "VK_SUBPASS_CONTENTS_SECONDARY_COMMAND_BUFFERS"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_SystemAllocationScope_to_str(VkSystemAllocationScope input) +{ + switch(input) { + case 0: + return "VK_SYSTEM_ALLOCATION_SCOPE_COMMAND"; + case 1: + return "VK_SYSTEM_ALLOCATION_SCOPE_OBJECT"; + case 2: + return "VK_SYSTEM_ALLOCATION_SCOPE_CACHE"; + case 3: + return "VK_SYSTEM_ALLOCATION_SCOPE_DEVICE"; + case 4: + return "VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_TessellationDomainOrigin_to_str(VkTessellationDomainOrigin input) +{ + switch(input) { + case 0: + return "VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT"; + case 1: + return "VK_TESSELLATION_DOMAIN_ORIGIN_LOWER_LEFT"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_TimeDomainEXT_to_str(VkTimeDomainEXT input) +{ + switch(input) { + case 0: + return "VK_TIME_DOMAIN_DEVICE_EXT"; + case 1: + return "VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT"; + case 2: + return "VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT"; + case 3: + return "VK_TIME_DOMAIN_QUERY_PERFORMANCE_COUNTER_EXT"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_ValidationCacheHeaderVersionEXT_to_str(VkValidationCacheHeaderVersionEXT input) +{ + switch(input) { + case 1: + return "VK_VALIDATION_CACHE_HEADER_VERSION_ONE_EXT"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_ValidationCheckEXT_to_str(VkValidationCheckEXT input) +{ + switch(input) { + case 0: + return "VK_VALIDATION_CHECK_ALL_EXT"; + case 1: + return "VK_VALIDATION_CHECK_SHADERS_EXT"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_ValidationFeatureDisableEXT_to_str(VkValidationFeatureDisableEXT input) +{ + switch(input) { + case 0: + return "VK_VALIDATION_FEATURE_DISABLE_ALL_EXT"; + case 1: + return "VK_VALIDATION_FEATURE_DISABLE_SHADERS_EXT"; + case 2: + return "VK_VALIDATION_FEATURE_DISABLE_THREAD_SAFETY_EXT"; + case 3: + return "VK_VALIDATION_FEATURE_DISABLE_API_PARAMETERS_EXT"; + case 4: + return "VK_VALIDATION_FEATURE_DISABLE_OBJECT_LIFETIMES_EXT"; + case 5: + return "VK_VALIDATION_FEATURE_DISABLE_CORE_CHECKS_EXT"; + case 6: + return "VK_VALIDATION_FEATURE_DISABLE_UNIQUE_HANDLES_EXT"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_ValidationFeatureEnableEXT_to_str(VkValidationFeatureEnableEXT input) +{ + switch(input) { + case 0: + return "VK_VALIDATION_FEATURE_ENABLE_GPU_ASSISTED_EXT"; + case 1: + return "VK_VALIDATION_FEATURE_ENABLE_GPU_ASSISTED_RESERVE_BINDING_SLOT_EXT"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_VendorId_to_str(VkVendorId input) +{ + switch(input) { + case 65537: + return "VK_VENDOR_ID_VIV"; + case 65538: + return "VK_VENDOR_ID_VSI"; + case 65539: + return "VK_VENDOR_ID_KAZAN"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_VertexInputRate_to_str(VkVertexInputRate input) +{ + switch(input) { + case 0: + return "VK_VERTEX_INPUT_RATE_VERTEX"; + case 1: + return "VK_VERTEX_INPUT_RATE_INSTANCE"; + default: + unreachable("Undefined enum value."); + } +} + +const char * +vk_ViewportCoordinateSwizzleNV_to_str(VkViewportCoordinateSwizzleNV input) +{ + switch(input) { + case 0: + return "VK_VIEWPORT_COORDINATE_SWIZZLE_POSITIVE_X_NV"; + case 1: + return "VK_VIEWPORT_COORDINATE_SWIZZLE_NEGATIVE_X_NV"; + case 2: + return "VK_VIEWPORT_COORDINATE_SWIZZLE_POSITIVE_Y_NV"; + case 3: + return "VK_VIEWPORT_COORDINATE_SWIZZLE_NEGATIVE_Y_NV"; + case 4: + return "VK_VIEWPORT_COORDINATE_SWIZZLE_POSITIVE_Z_NV"; + case 5: + return "VK_VIEWPORT_COORDINATE_SWIZZLE_NEGATIVE_Z_NV"; + case 6: + return "VK_VIEWPORT_COORDINATE_SWIZZLE_POSITIVE_W_NV"; + case 7: + return "VK_VIEWPORT_COORDINATE_SWIZZLE_NEGATIVE_W_NV"; + default: + unreachable("Undefined enum value."); + } +} diff --git a/prebuilt-intermediates/util/vk_enum_to_str.h b/prebuilt-intermediates/util/vk_enum_to_str.h new file mode 100644 index 00000000000..95dbdcdd942 --- /dev/null +++ b/prebuilt-intermediates/util/vk_enum_to_str.h @@ -0,0 +1,267 @@ +/* Autogenerated file -- do not edit + * generated by gen_enum_to_str.py + * + * Copyright © 2017 Intel Corporation +* +* Permission is hereby granted, free of charge, to any person obtaining a copy +* of this software and associated documentation files (the "Software"), to deal +* in the Software without restriction, including without limitation the rights +* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +* copies of the Software, and to permit persons to whom the Software is +* furnished to do so, subject to the following conditions: +* +* The above copyright notice and this permission notice shall be included in +* all copies or substantial portions of the Software. +* +* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +* SOFTWARE. + */ + +#ifndef MESA_VK_ENUM_TO_STR_H +#define MESA_VK_ENUM_TO_STR_H + +#include +#include + +#ifdef __cplusplus +extern "C" { +#endif + +#define _VK_AMD_buffer_marker_number (180) +#define _VK_AMD_draw_indirect_count_number (34) +#define _VK_AMD_gcn_shader_number (26) +#define _VK_AMD_gpu_shader_half_float_number (37) +#define _VK_AMD_gpu_shader_int16_number (133) +#define _VK_AMD_memory_overallocation_behavior_number (190) +#define _VK_AMD_mixed_attachment_samples_number (137) +#define _VK_AMD_negative_viewport_height_number (36) +#define _VK_AMD_rasterization_order_number (19) +#define _VK_AMD_shader_ballot_number (38) +#define _VK_AMD_shader_core_properties_number (186) +#define _VK_AMD_shader_explicit_vertex_parameter_number (22) +#define _VK_AMD_shader_fragment_mask_number (138) +#define _VK_AMD_shader_image_load_store_lod_number (47) +#define _VK_AMD_shader_info_number (43) +#define _VK_AMD_shader_trinary_minmax_number (21) +#define _VK_AMD_texture_gather_bias_lod_number (42) +#define _VK_ANDROID_external_memory_android_hardware_buffer_number (130) +#define _VK_EXT_acquire_xlib_display_number (90) +#define _VK_EXT_astc_decode_mode_number (68) +#define _VK_EXT_blend_operation_advanced_number (149) +#define _VK_EXT_buffer_device_address_number (245) +#define _VK_EXT_calibrated_timestamps_number (185) +#define _VK_EXT_conditional_rendering_number (82) +#define _VK_EXT_conservative_rasterization_number (102) +#define _VK_EXT_debug_marker_number (23) +#define _VK_EXT_debug_report_number (12) +#define _VK_EXT_debug_utils_number (129) +#define _VK_EXT_depth_range_unrestricted_number (14) +#define _VK_EXT_descriptor_indexing_number (162) +#define _VK_EXT_direct_mode_display_number (89) +#define _VK_EXT_discard_rectangles_number (100) +#define _VK_EXT_display_control_number (92) +#define _VK_EXT_display_surface_counter_number (91) +#define _VK_EXT_external_memory_dma_buf_number (126) +#define _VK_EXT_external_memory_host_number (179) +#define _VK_EXT_fragment_density_map_number (219) +#define _VK_EXT_global_priority_number (175) +#define _VK_EXT_hdr_metadata_number (106) +#define _VK_EXT_image_drm_format_modifier_number (159) +#define _VK_EXT_inline_uniform_block_number (139) +#define _VK_EXT_memory_budget_number (238) +#define _VK_EXT_memory_priority_number (239) +#define _VK_EXT_pci_bus_info_number (213) +#define _VK_EXT_post_depth_coverage_number (156) +#define _VK_EXT_queue_family_foreign_number (127) +#define _VK_EXT_sample_locations_number (144) +#define _VK_EXT_sampler_filter_minmax_number (131) +#define _VK_EXT_scalar_block_layout_number (222) +#define _VK_EXT_separate_stencil_usage_number (247) +#define _VK_EXT_shader_stencil_export_number (141) +#define _VK_EXT_shader_subgroup_ballot_number (65) +#define _VK_EXT_shader_subgroup_vote_number (66) +#define _VK_EXT_shader_viewport_index_layer_number (163) +#define _VK_EXT_swapchain_colorspace_number (105) +#define _VK_EXT_transform_feedback_number (29) +#define _VK_EXT_validation_cache_number (161) +#define _VK_EXT_validation_features_number (248) +#define _VK_EXT_validation_flags_number (62) +#define _VK_EXT_vertex_attribute_divisor_number (191) +#define _VK_FUCHSIA_imagepipe_surface_number (215) +#define _VK_GOOGLE_decorate_string_number (225) +#define _VK_GOOGLE_display_timing_number (93) +#define _VK_GOOGLE_hlsl_functionality1_number (224) +#define _VK_IMG_filter_cubic_number (16) +#define _VK_IMG_format_pvrtc_number (55) +#define _VK_KHR_16bit_storage_number (84) +#define _VK_KHR_8bit_storage_number (178) +#define _VK_KHR_android_surface_number (9) +#define _VK_KHR_bind_memory2_number (158) +#define _VK_KHR_create_renderpass2_number (110) +#define _VK_KHR_dedicated_allocation_number (128) +#define _VK_KHR_depth_stencil_resolve_number (200) +#define _VK_KHR_descriptor_update_template_number (86) +#define _VK_KHR_device_group_number (61) +#define _VK_KHR_device_group_creation_number (71) +#define _VK_KHR_display_number (3) +#define _VK_KHR_display_swapchain_number (4) +#define _VK_KHR_draw_indirect_count_number (170) +#define _VK_KHR_driver_properties_number (197) +#define _VK_KHR_external_fence_number (114) +#define _VK_KHR_external_fence_capabilities_number (113) +#define _VK_KHR_external_fence_fd_number (116) +#define _VK_KHR_external_fence_win32_number (115) +#define _VK_KHR_external_memory_number (73) +#define _VK_KHR_external_memory_capabilities_number (72) +#define _VK_KHR_external_memory_fd_number (75) +#define _VK_KHR_external_memory_win32_number (74) +#define _VK_KHR_external_semaphore_number (78) +#define _VK_KHR_external_semaphore_capabilities_number (77) +#define _VK_KHR_external_semaphore_fd_number (80) +#define _VK_KHR_external_semaphore_win32_number (79) +#define _VK_KHR_get_display_properties2_number (122) +#define _VK_KHR_get_memory_requirements2_number (147) +#define _VK_KHR_get_physical_device_properties2_number (60) +#define _VK_KHR_get_surface_capabilities2_number (120) +#define _VK_KHR_image_format_list_number (148) +#define _VK_KHR_incremental_present_number (85) +#define _VK_KHR_maintenance1_number (70) +#define _VK_KHR_maintenance2_number (118) +#define _VK_KHR_maintenance3_number (169) +#define _VK_KHR_multiview_number (54) +#define _VK_KHR_push_descriptor_number (81) +#define _VK_KHR_relaxed_block_layout_number (145) +#define _VK_KHR_sampler_mirror_clamp_to_edge_number (15) +#define _VK_KHR_sampler_ycbcr_conversion_number (157) +#define _VK_KHR_shader_atomic_int64_number (181) +#define _VK_KHR_shader_draw_parameters_number (64) +#define _VK_KHR_shader_float16_int8_number (83) +#define _VK_KHR_shader_float_controls_number (198) +#define _VK_KHR_shared_presentable_image_number (112) +#define _VK_KHR_storage_buffer_storage_class_number (132) +#define _VK_KHR_surface_number (1) +#define _VK_KHR_swapchain_number (2) +#define _VK_KHR_swapchain_mutable_format_number (201) +#define _VK_KHR_variable_pointers_number (121) +#define _VK_KHR_vulkan_memory_model_number (212) +#define _VK_KHR_wayland_surface_number (7) +#define _VK_KHR_win32_keyed_mutex_number (76) +#define _VK_KHR_win32_surface_number (10) +#define _VK_KHR_xcb_surface_number (6) +#define _VK_KHR_xlib_surface_number (5) +#define _VK_MVK_ios_surface_number (123) +#define _VK_MVK_macos_surface_number (124) +#define _VK_NN_vi_surface_number (63) +#define _VK_NVX_device_generated_commands_number (87) +#define _VK_NVX_multiview_per_view_attributes_number (98) +#define _VK_NV_clip_space_w_scaling_number (88) +#define _VK_NV_compute_shader_derivatives_number (202) +#define _VK_NV_corner_sampled_image_number (51) +#define _VK_NV_dedicated_allocation_number (27) +#define _VK_NV_device_diagnostic_checkpoints_number (207) +#define _VK_NV_external_memory_number (57) +#define _VK_NV_external_memory_capabilities_number (56) +#define _VK_NV_external_memory_win32_number (58) +#define _VK_NV_fill_rectangle_number (154) +#define _VK_NV_fragment_coverage_to_color_number (150) +#define _VK_NV_fragment_shader_barycentric_number (204) +#define _VK_NV_framebuffer_mixed_samples_number (153) +#define _VK_NV_geometry_shader_passthrough_number (96) +#define _VK_NV_glsl_shader_number (13) +#define _VK_NV_mesh_shader_number (203) +#define _VK_NV_ray_tracing_number (166) +#define _VK_NV_representative_fragment_test_number (167) +#define _VK_NV_sample_mask_override_coverage_number (95) +#define _VK_NV_scissor_exclusive_number (206) +#define _VK_NV_shader_image_footprint_number (205) +#define _VK_NV_shader_subgroup_partitioned_number (199) +#define _VK_NV_shading_rate_image_number (165) +#define _VK_NV_viewport_array2_number (97) +#define _VK_NV_viewport_swizzle_number (99) +#define _VK_NV_win32_keyed_mutex_number (59) + +const char * vk_AccelerationStructureMemoryRequirementsTypeNV_to_str(VkAccelerationStructureMemoryRequirementsTypeNV input); +const char * vk_AccelerationStructureTypeNV_to_str(VkAccelerationStructureTypeNV input); +const char * vk_AttachmentLoadOp_to_str(VkAttachmentLoadOp input); +const char * vk_AttachmentStoreOp_to_str(VkAttachmentStoreOp input); +const char * vk_BlendFactor_to_str(VkBlendFactor input); +const char * vk_BlendOp_to_str(VkBlendOp input); +const char * vk_BlendOverlapEXT_to_str(VkBlendOverlapEXT input); +const char * vk_BorderColor_to_str(VkBorderColor input); +const char * vk_ChromaLocation_to_str(VkChromaLocation input); +const char * vk_CoarseSampleOrderTypeNV_to_str(VkCoarseSampleOrderTypeNV input); +const char * vk_ColorSpaceKHR_to_str(VkColorSpaceKHR input); +const char * vk_CommandBufferLevel_to_str(VkCommandBufferLevel input); +const char * vk_CompareOp_to_str(VkCompareOp input); +const char * vk_ComponentSwizzle_to_str(VkComponentSwizzle input); +const char * vk_ConservativeRasterizationModeEXT_to_str(VkConservativeRasterizationModeEXT input); +const char * vk_CopyAccelerationStructureModeNV_to_str(VkCopyAccelerationStructureModeNV input); +const char * vk_CoverageModulationModeNV_to_str(VkCoverageModulationModeNV input); +const char * vk_DebugReportObjectTypeEXT_to_str(VkDebugReportObjectTypeEXT input); +const char * vk_DescriptorType_to_str(VkDescriptorType input); +const char * vk_DescriptorUpdateTemplateType_to_str(VkDescriptorUpdateTemplateType input); +const char * vk_DeviceEventTypeEXT_to_str(VkDeviceEventTypeEXT input); +const char * vk_DiscardRectangleModeEXT_to_str(VkDiscardRectangleModeEXT input); +const char * vk_DisplayEventTypeEXT_to_str(VkDisplayEventTypeEXT input); +const char * vk_DisplayPowerStateEXT_to_str(VkDisplayPowerStateEXT input); +const char * vk_DriverIdKHR_to_str(VkDriverIdKHR input); +const char * vk_DynamicState_to_str(VkDynamicState input); +const char * vk_Filter_to_str(VkFilter input); +const char * vk_Format_to_str(VkFormat input); +const char * vk_FrontFace_to_str(VkFrontFace input); +const char * vk_GeometryTypeNV_to_str(VkGeometryTypeNV input); +const char * vk_ImageLayout_to_str(VkImageLayout input); +const char * vk_ImageTiling_to_str(VkImageTiling input); +const char * vk_ImageType_to_str(VkImageType input); +const char * vk_ImageViewType_to_str(VkImageViewType input); +const char * vk_IndexType_to_str(VkIndexType input); +const char * vk_IndirectCommandsTokenTypeNVX_to_str(VkIndirectCommandsTokenTypeNVX input); +const char * vk_InternalAllocationType_to_str(VkInternalAllocationType input); +const char * vk_LogicOp_to_str(VkLogicOp input); +const char * vk_MemoryOverallocationBehaviorAMD_to_str(VkMemoryOverallocationBehaviorAMD input); +const char * vk_ObjectEntryTypeNVX_to_str(VkObjectEntryTypeNVX input); +const char * vk_ObjectType_to_str(VkObjectType input); +const char * vk_PhysicalDeviceType_to_str(VkPhysicalDeviceType input); +const char * vk_PipelineBindPoint_to_str(VkPipelineBindPoint input); +const char * vk_PipelineCacheHeaderVersion_to_str(VkPipelineCacheHeaderVersion input); +const char * vk_PointClippingBehavior_to_str(VkPointClippingBehavior input); +const char * vk_PolygonMode_to_str(VkPolygonMode input); +const char * vk_PresentModeKHR_to_str(VkPresentModeKHR input); +const char * vk_PrimitiveTopology_to_str(VkPrimitiveTopology input); +const char * vk_QueryType_to_str(VkQueryType input); +const char * vk_QueueGlobalPriorityEXT_to_str(VkQueueGlobalPriorityEXT input); +const char * vk_RasterizationOrderAMD_to_str(VkRasterizationOrderAMD input); +const char * vk_RayTracingShaderGroupTypeNV_to_str(VkRayTracingShaderGroupTypeNV input); +const char * vk_Result_to_str(VkResult input); +const char * vk_SamplerAddressMode_to_str(VkSamplerAddressMode input); +const char * vk_SamplerMipmapMode_to_str(VkSamplerMipmapMode input); +const char * vk_SamplerReductionModeEXT_to_str(VkSamplerReductionModeEXT input); +const char * vk_SamplerYcbcrModelConversion_to_str(VkSamplerYcbcrModelConversion input); +const char * vk_SamplerYcbcrRange_to_str(VkSamplerYcbcrRange input); +const char * vk_ShaderInfoTypeAMD_to_str(VkShaderInfoTypeAMD input); +const char * vk_ShadingRatePaletteEntryNV_to_str(VkShadingRatePaletteEntryNV input); +const char * vk_SharingMode_to_str(VkSharingMode input); +const char * vk_StencilOp_to_str(VkStencilOp input); +const char * vk_StructureType_to_str(VkStructureType input); +const char * vk_SubpassContents_to_str(VkSubpassContents input); +const char * vk_SystemAllocationScope_to_str(VkSystemAllocationScope input); +const char * vk_TessellationDomainOrigin_to_str(VkTessellationDomainOrigin input); +const char * vk_TimeDomainEXT_to_str(VkTimeDomainEXT input); +const char * vk_ValidationCacheHeaderVersionEXT_to_str(VkValidationCacheHeaderVersionEXT input); +const char * vk_ValidationCheckEXT_to_str(VkValidationCheckEXT input); +const char * vk_ValidationFeatureDisableEXT_to_str(VkValidationFeatureDisableEXT input); +const char * vk_ValidationFeatureEnableEXT_to_str(VkValidationFeatureEnableEXT input); +const char * vk_VendorId_to_str(VkVendorId input); +const char * vk_VertexInputRate_to_str(VkVertexInputRate input); +const char * vk_ViewportCoordinateSwizzleNV_to_str(VkViewportCoordinateSwizzleNV input); + +#ifdef __cplusplus +} /* extern "C" */ +#endif + +#endif \ No newline at end of file diff --git a/prebuilt-intermediates/vulkan/anv_entrypoints.c b/prebuilt-intermediates/vulkan/anv_entrypoints.c new file mode 100644 index 00000000000..3d8938e8a5f --- /dev/null +++ b/prebuilt-intermediates/vulkan/anv_entrypoints.c @@ -0,0 +1,5878 @@ +/* + * Copyright © 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +/* This file generated from anv_entrypoints_gen.py, don't edit directly. */ + +#include "anv_private.h" + +struct string_map_entry { + uint32_t name; + uint32_t hash; + uint32_t num; +}; + +/* We use a big string constant to avoid lots of reloctions from the entry + * point table to lots of little strings. The entries in the entry point table + * store the index into this big string. + */ + + + + +static const char instance_strings[] = + "vkAcquireXlibDisplayEXT\0" + "vkCreateDebugReportCallbackEXT\0" + "vkCreateDevice\0" + "vkCreateDisplayModeKHR\0" + "vkCreateDisplayPlaneSurfaceKHR\0" + "vkCreateInstance\0" + "vkCreateWaylandSurfaceKHR\0" + "vkCreateXcbSurfaceKHR\0" + "vkCreateXlibSurfaceKHR\0" + "vkDebugReportMessageEXT\0" + "vkDestroyDebugReportCallbackEXT\0" + "vkDestroyInstance\0" + "vkDestroySurfaceKHR\0" + "vkEnumerateDeviceExtensionProperties\0" + "vkEnumerateDeviceLayerProperties\0" + "vkEnumerateInstanceExtensionProperties\0" + "vkEnumerateInstanceLayerProperties\0" + "vkEnumerateInstanceVersion\0" + "vkEnumeratePhysicalDeviceGroups\0" + "vkEnumeratePhysicalDeviceGroupsKHR\0" + "vkEnumeratePhysicalDevices\0" + "vkGetDisplayModeProperties2KHR\0" + "vkGetDisplayModePropertiesKHR\0" + "vkGetDisplayPlaneCapabilities2KHR\0" + "vkGetDisplayPlaneCapabilitiesKHR\0" + "vkGetDisplayPlaneSupportedDisplaysKHR\0" + "vkGetInstanceProcAddr\0" + "vkGetPhysicalDeviceCalibrateableTimeDomainsEXT\0" + "vkGetPhysicalDeviceDisplayPlaneProperties2KHR\0" + "vkGetPhysicalDeviceDisplayPlanePropertiesKHR\0" + "vkGetPhysicalDeviceDisplayProperties2KHR\0" + "vkGetPhysicalDeviceDisplayPropertiesKHR\0" + "vkGetPhysicalDeviceExternalBufferProperties\0" + "vkGetPhysicalDeviceExternalBufferPropertiesKHR\0" + "vkGetPhysicalDeviceExternalFenceProperties\0" + "vkGetPhysicalDeviceExternalFencePropertiesKHR\0" + "vkGetPhysicalDeviceExternalSemaphoreProperties\0" + "vkGetPhysicalDeviceExternalSemaphorePropertiesKHR\0" + "vkGetPhysicalDeviceFeatures\0" + "vkGetPhysicalDeviceFeatures2\0" + "vkGetPhysicalDeviceFeatures2KHR\0" + "vkGetPhysicalDeviceFormatProperties\0" + "vkGetPhysicalDeviceFormatProperties2\0" + "vkGetPhysicalDeviceFormatProperties2KHR\0" + "vkGetPhysicalDeviceImageFormatProperties\0" + "vkGetPhysicalDeviceImageFormatProperties2\0" + "vkGetPhysicalDeviceImageFormatProperties2KHR\0" + "vkGetPhysicalDeviceMemoryProperties\0" + "vkGetPhysicalDeviceMemoryProperties2\0" + "vkGetPhysicalDeviceMemoryProperties2KHR\0" + "vkGetPhysicalDevicePresentRectanglesKHR\0" + "vkGetPhysicalDeviceProperties\0" + "vkGetPhysicalDeviceProperties2\0" + "vkGetPhysicalDeviceProperties2KHR\0" + "vkGetPhysicalDeviceQueueFamilyProperties\0" + "vkGetPhysicalDeviceQueueFamilyProperties2\0" + "vkGetPhysicalDeviceQueueFamilyProperties2KHR\0" + "vkGetPhysicalDeviceSparseImageFormatProperties\0" + "vkGetPhysicalDeviceSparseImageFormatProperties2\0" + "vkGetPhysicalDeviceSparseImageFormatProperties2KHR\0" + "vkGetPhysicalDeviceSurfaceCapabilities2EXT\0" + "vkGetPhysicalDeviceSurfaceCapabilities2KHR\0" + "vkGetPhysicalDeviceSurfaceCapabilitiesKHR\0" + "vkGetPhysicalDeviceSurfaceFormats2KHR\0" + "vkGetPhysicalDeviceSurfaceFormatsKHR\0" + "vkGetPhysicalDeviceSurfacePresentModesKHR\0" + "vkGetPhysicalDeviceSurfaceSupportKHR\0" + "vkGetPhysicalDeviceWaylandPresentationSupportKHR\0" + "vkGetPhysicalDeviceXcbPresentationSupportKHR\0" + "vkGetPhysicalDeviceXlibPresentationSupportKHR\0" + "vkGetRandROutputDisplayEXT\0" + "vkReleaseDisplayEXT\0" +; + +static const struct string_map_entry instance_string_map_entries[] = { + { 0, 0x60df100d, 59 }, /* vkAcquireXlibDisplayEXT */ + { 24, 0x987ef56, 35 }, /* vkCreateDebugReportCallbackEXT */ + { 55, 0x85ed23f, 10 }, /* vkCreateDevice */ + { 70, 0xcc0bde41, 21 }, /* vkCreateDisplayModeKHR */ + { 93, 0x7ac4dacb, 23 }, /* vkCreateDisplayPlaneSurfaceKHR */ + { 124, 0x38a581a6, 0 }, /* vkCreateInstance */ + { 141, 0x2b2a4b79, 29 }, /* vkCreateWaylandSurfaceKHR */ + { 167, 0xc5e5b106, 33 }, /* vkCreateXcbSurfaceKHR */ + { 189, 0xa693bc66, 31 }, /* vkCreateXlibSurfaceKHR */ + { 212, 0xa4e75334, 37 }, /* vkDebugReportMessageEXT */ + { 236, 0x43d4c4e2, 36 }, /* vkDestroyDebugReportCallbackEXT */ + { 268, 0x9bd21af2, 1 }, /* vkDestroyInstance */ + { 286, 0xf204ce7d, 24 }, /* vkDestroySurfaceKHR */ + { 306, 0x5fd13eed, 15 }, /* vkEnumerateDeviceExtensionProperties */ + { 343, 0x2f8566e7, 14 }, /* vkEnumerateDeviceLayerProperties */ + { 376, 0xeb27627e, 13 }, /* vkEnumerateInstanceExtensionProperties */ + { 415, 0x81f69d8, 12 }, /* vkEnumerateInstanceLayerProperties */ + { 450, 0xd0481e5c, 11 }, /* vkEnumerateInstanceVersion */ + { 477, 0x270514f0, 62 }, /* vkEnumeratePhysicalDeviceGroups */ + { 509, 0x549ce595, 63 }, /* vkEnumeratePhysicalDeviceGroupsKHR */ + { 544, 0x5787c327, 2 }, /* vkEnumeratePhysicalDevices */ + { 571, 0x3e613e42, 69 }, /* vkGetDisplayModeProperties2KHR */ + { 602, 0x36b8a8de, 20 }, /* vkGetDisplayModePropertiesKHR */ + { 632, 0xff1655a4, 70 }, /* vkGetDisplayPlaneCapabilities2KHR */ + { 666, 0x4b60d48c, 22 }, /* vkGetDisplayPlaneCapabilitiesKHR */ + { 699, 0xabef4889, 19 }, /* vkGetDisplayPlaneSupportedDisplaysKHR */ + { 737, 0x3d2ae9ad, 3 }, /* vkGetInstanceProcAddr */ + { 759, 0xea07da1a, 71 }, /* vkGetPhysicalDeviceCalibrateableTimeDomainsEXT */ + { 806, 0xb7bc4386, 68 }, /* vkGetPhysicalDeviceDisplayPlaneProperties2KHR */ + { 852, 0xb9b8ddba, 18 }, /* vkGetPhysicalDeviceDisplayPlanePropertiesKHR */ + { 897, 0x540c0372, 67 }, /* vkGetPhysicalDeviceDisplayProperties2KHR */ + { 938, 0xfa0cd2e, 17 }, /* vkGetPhysicalDeviceDisplayPropertiesKHR */ + { 978, 0x944476dc, 52 }, /* vkGetPhysicalDeviceExternalBufferProperties */ + { 1022, 0xee68b389, 53 }, /* vkGetPhysicalDeviceExternalBufferPropertiesKHR */ + { 1069, 0x3bc965eb, 56 }, /* vkGetPhysicalDeviceExternalFenceProperties */ + { 1112, 0x99b35492, 57 }, /* vkGetPhysicalDeviceExternalFencePropertiesKHR */ + { 1158, 0xcf251b0e, 54 }, /* vkGetPhysicalDeviceExternalSemaphoreProperties */ + { 1205, 0x984c3fa7, 55 }, /* vkGetPhysicalDeviceExternalSemaphorePropertiesKHR */ + { 1255, 0x113e2f33, 7 }, /* vkGetPhysicalDeviceFeatures */ + { 1283, 0x63c068a7, 38 }, /* vkGetPhysicalDeviceFeatures2 */ + { 1312, 0x6a9a3636, 39 }, /* vkGetPhysicalDeviceFeatures2KHR */ + { 1344, 0x3e54b398, 8 }, /* vkGetPhysicalDeviceFormatProperties */ + { 1380, 0xca3bb9da, 42 }, /* vkGetPhysicalDeviceFormatProperties2 */ + { 1417, 0x9099cbbb, 43 }, /* vkGetPhysicalDeviceFormatProperties2KHR */ + { 1457, 0xdd36a867, 9 }, /* vkGetPhysicalDeviceImageFormatProperties */ + { 1498, 0x35d260d3, 44 }, /* vkGetPhysicalDeviceImageFormatProperties2 */ + { 1540, 0x102ff7ea, 45 }, /* vkGetPhysicalDeviceImageFormatProperties2KHR */ + { 1585, 0xa90da4da, 6 }, /* vkGetPhysicalDeviceMemoryProperties */ + { 1621, 0xcb4cc208, 48 }, /* vkGetPhysicalDeviceMemoryProperties2 */ + { 1658, 0xc8c3da3d, 49 }, /* vkGetPhysicalDeviceMemoryProperties2KHR */ + { 1698, 0x100341b4, 64 }, /* vkGetPhysicalDevicePresentRectanglesKHR */ + { 1738, 0x52fe22c9, 4 }, /* vkGetPhysicalDeviceProperties */ + { 1768, 0x6c4d8ee1, 40 }, /* vkGetPhysicalDeviceProperties2 */ + { 1799, 0xcd15838c, 41 }, /* vkGetPhysicalDeviceProperties2KHR */ + { 1833, 0x4e5fc88a, 5 }, /* vkGetPhysicalDeviceQueueFamilyProperties */ + { 1874, 0xcad374d8, 46 }, /* vkGetPhysicalDeviceQueueFamilyProperties2 */ + { 1916, 0x5ceb2bed, 47 }, /* vkGetPhysicalDeviceQueueFamilyProperties2KHR */ + { 1961, 0x272ef8ef, 16 }, /* vkGetPhysicalDeviceSparseImageFormatProperties */ + { 2008, 0xebddba0b, 50 }, /* vkGetPhysicalDeviceSparseImageFormatProperties2 */ + { 2056, 0x8746ed72, 51 }, /* vkGetPhysicalDeviceSparseImageFormatProperties2KHR */ + { 2107, 0x5a5fba04, 61 }, /* vkGetPhysicalDeviceSurfaceCapabilities2EXT */ + { 2150, 0x9497e378, 65 }, /* vkGetPhysicalDeviceSurfaceCapabilities2KHR */ + { 2193, 0x77890558, 26 }, /* vkGetPhysicalDeviceSurfaceCapabilitiesKHR */ + { 2235, 0xd00b7188, 66 }, /* vkGetPhysicalDeviceSurfaceFormats2KHR */ + { 2273, 0xe32227c8, 27 }, /* vkGetPhysicalDeviceSurfaceFormatsKHR */ + { 2310, 0x31c3cbd1, 28 }, /* vkGetPhysicalDeviceSurfacePresentModesKHR */ + { 2352, 0x1a687885, 25 }, /* vkGetPhysicalDeviceSurfaceSupportKHR */ + { 2389, 0x84e085ac, 30 }, /* vkGetPhysicalDeviceWaylandPresentationSupportKHR */ + { 2438, 0x41782cb9, 34 }, /* vkGetPhysicalDeviceXcbPresentationSupportKHR */ + { 2483, 0x34a063ab, 32 }, /* vkGetPhysicalDeviceXlibPresentationSupportKHR */ + { 2529, 0xb87cdd6c, 60 }, /* vkGetRandROutputDisplayEXT */ + { 2556, 0x4207f4f1, 58 }, /* vkReleaseDisplayEXT */ +}; + +/* Hash table stats: + * size 72 entries + * collisions entries: + * 0 54 + * 1 9 + * 2 3 + * 3 5 + * 4 0 + * 5 1 + * 6 0 + * 7 0 + * 8 0 + * 9+ 0 + */ + +#define none 0xffff +static const uint16_t instance_string_map[128] = { + 0x002f, + none, + 0x0039, + none, + 0x003c, + 0x001e, + 0x0007, + none, + 0x0030, + 0x0019, + 0x0036, + 0x003a, + 0x0018, + 0x0000, + 0x0024, + none, + none, + 0x0037, + 0x0023, + 0x0038, + none, + 0x0013, + none, + none, + 0x0029, + 0x001c, + 0x001b, + 0x003f, + 0x0021, + none, + none, + 0x0035, + none, + none, + none, + none, + 0x0017, + none, + 0x0005, + 0x0014, + none, + none, + none, + 0x003b, + 0x0043, + 0x001a, + 0x001f, + none, + none, + none, + none, + 0x0026, + 0x0009, + none, + 0x0028, + 0x003e, + none, + 0x0044, + 0x001d, + 0x002b, + none, + 0x0031, + 0x0042, + 0x0002, + none, + 0x0003, + 0x0015, + none, + none, + none, + none, + 0x0032, + 0x0040, + 0x0033, + none, + 0x0004, + none, + 0x0025, + none, + none, + none, + 0x0041, + none, + 0x002d, + none, + none, + 0x0001, + none, + 0x0010, + none, + 0x002a, + none, + 0x0011, + none, + 0x0016, + none, + 0x0027, + 0x0034, + 0x000a, + none, + 0x0045, + none, + 0x0008, + 0x000e, + none, + none, + 0x002e, + 0x0022, + 0x0046, + 0x000d, + none, + 0x0020, + 0x0012, + 0x0047, + 0x000b, + none, + none, + none, + none, + none, + 0x003d, + 0x0006, + 0x002c, + none, + none, + 0x000c, + 0x000f, + none, +}; + +static int +instance_string_map_lookup(const char *str) +{ + static const uint32_t prime_factor = 5024183; + static const uint32_t prime_step = 19; + const struct string_map_entry *e; + uint32_t hash, h; + uint16_t i; + const char *p; + + hash = 0; + for (p = str; *p; p++) + hash = hash * prime_factor + *p; + + h = hash; + while (1) { + i = instance_string_map[h & 127]; + if (i == none) + return -1; + e = &instance_string_map_entries[i]; + if (e->hash == hash && strcmp(str, instance_strings + e->name) == 0) + return e->num; + h += prime_step; + } + + return -1; +} + + +static const char device_strings[] = + "vkAcquireImageANDROID\0" + "vkAcquireNextImage2KHR\0" + "vkAcquireNextImageKHR\0" + "vkAllocateCommandBuffers\0" + "vkAllocateDescriptorSets\0" + "vkAllocateMemory\0" + "vkBeginCommandBuffer\0" + "vkBindBufferMemory\0" + "vkBindBufferMemory2\0" + "vkBindBufferMemory2KHR\0" + "vkBindImageMemory\0" + "vkBindImageMemory2\0" + "vkBindImageMemory2KHR\0" + "vkCmdBeginConditionalRenderingEXT\0" + "vkCmdBeginQuery\0" + "vkCmdBeginQueryIndexedEXT\0" + "vkCmdBeginRenderPass\0" + "vkCmdBeginRenderPass2KHR\0" + "vkCmdBeginTransformFeedbackEXT\0" + "vkCmdBindDescriptorSets\0" + "vkCmdBindIndexBuffer\0" + "vkCmdBindPipeline\0" + "vkCmdBindTransformFeedbackBuffersEXT\0" + "vkCmdBindVertexBuffers\0" + "vkCmdBlitImage\0" + "vkCmdClearAttachments\0" + "vkCmdClearColorImage\0" + "vkCmdClearDepthStencilImage\0" + "vkCmdCopyBuffer\0" + "vkCmdCopyBufferToImage\0" + "vkCmdCopyImage\0" + "vkCmdCopyImageToBuffer\0" + "vkCmdCopyQueryPoolResults\0" + "vkCmdDispatch\0" + "vkCmdDispatchBase\0" + "vkCmdDispatchBaseKHR\0" + "vkCmdDispatchIndirect\0" + "vkCmdDraw\0" + "vkCmdDrawIndexed\0" + "vkCmdDrawIndexedIndirect\0" + "vkCmdDrawIndexedIndirectCountKHR\0" + "vkCmdDrawIndirect\0" + "vkCmdDrawIndirectByteCountEXT\0" + "vkCmdDrawIndirectCountKHR\0" + "vkCmdEndConditionalRenderingEXT\0" + "vkCmdEndQuery\0" + "vkCmdEndQueryIndexedEXT\0" + "vkCmdEndRenderPass\0" + "vkCmdEndRenderPass2KHR\0" + "vkCmdEndTransformFeedbackEXT\0" + "vkCmdExecuteCommands\0" + "vkCmdFillBuffer\0" + "vkCmdNextSubpass\0" + "vkCmdNextSubpass2KHR\0" + "vkCmdPipelineBarrier\0" + "vkCmdPushConstants\0" + "vkCmdPushDescriptorSetKHR\0" + "vkCmdPushDescriptorSetWithTemplateKHR\0" + "vkCmdResetEvent\0" + "vkCmdResetQueryPool\0" + "vkCmdResolveImage\0" + "vkCmdSetBlendConstants\0" + "vkCmdSetDepthBias\0" + "vkCmdSetDepthBounds\0" + "vkCmdSetDeviceMask\0" + "vkCmdSetDeviceMaskKHR\0" + "vkCmdSetEvent\0" + "vkCmdSetLineWidth\0" + "vkCmdSetScissor\0" + "vkCmdSetStencilCompareMask\0" + "vkCmdSetStencilReference\0" + "vkCmdSetStencilWriteMask\0" + "vkCmdSetViewport\0" + "vkCmdUpdateBuffer\0" + "vkCmdWaitEvents\0" + "vkCmdWriteTimestamp\0" + "vkCreateBuffer\0" + "vkCreateBufferView\0" + "vkCreateCommandPool\0" + "vkCreateComputePipelines\0" + "vkCreateDescriptorPool\0" + "vkCreateDescriptorSetLayout\0" + "vkCreateDescriptorUpdateTemplate\0" + "vkCreateDescriptorUpdateTemplateKHR\0" + "vkCreateDmaBufImageINTEL\0" + "vkCreateEvent\0" + "vkCreateFence\0" + "vkCreateFramebuffer\0" + "vkCreateGraphicsPipelines\0" + "vkCreateImage\0" + "vkCreateImageView\0" + "vkCreatePipelineCache\0" + "vkCreatePipelineLayout\0" + "vkCreateQueryPool\0" + "vkCreateRenderPass\0" + "vkCreateRenderPass2KHR\0" + "vkCreateSampler\0" + "vkCreateSamplerYcbcrConversion\0" + "vkCreateSamplerYcbcrConversionKHR\0" + "vkCreateSemaphore\0" + "vkCreateShaderModule\0" + "vkCreateSwapchainKHR\0" + "vkDestroyBuffer\0" + "vkDestroyBufferView\0" + "vkDestroyCommandPool\0" + "vkDestroyDescriptorPool\0" + "vkDestroyDescriptorSetLayout\0" + "vkDestroyDescriptorUpdateTemplate\0" + "vkDestroyDescriptorUpdateTemplateKHR\0" + "vkDestroyDevice\0" + "vkDestroyEvent\0" + "vkDestroyFence\0" + "vkDestroyFramebuffer\0" + "vkDestroyImage\0" + "vkDestroyImageView\0" + "vkDestroyPipeline\0" + "vkDestroyPipelineCache\0" + "vkDestroyPipelineLayout\0" + "vkDestroyQueryPool\0" + "vkDestroyRenderPass\0" + "vkDestroySampler\0" + "vkDestroySamplerYcbcrConversion\0" + "vkDestroySamplerYcbcrConversionKHR\0" + "vkDestroySemaphore\0" + "vkDestroyShaderModule\0" + "vkDestroySwapchainKHR\0" + "vkDeviceWaitIdle\0" + "vkDisplayPowerControlEXT\0" + "vkEndCommandBuffer\0" + "vkFlushMappedMemoryRanges\0" + "vkFreeCommandBuffers\0" + "vkFreeDescriptorSets\0" + "vkFreeMemory\0" + "vkGetAndroidHardwareBufferPropertiesANDROID\0" + "vkGetBufferMemoryRequirements\0" + "vkGetBufferMemoryRequirements2\0" + "vkGetBufferMemoryRequirements2KHR\0" + "vkGetCalibratedTimestampsEXT\0" + "vkGetDescriptorSetLayoutSupport\0" + "vkGetDescriptorSetLayoutSupportKHR\0" + "vkGetDeviceGroupPeerMemoryFeatures\0" + "vkGetDeviceGroupPeerMemoryFeaturesKHR\0" + "vkGetDeviceGroupPresentCapabilitiesKHR\0" + "vkGetDeviceGroupSurfacePresentModesKHR\0" + "vkGetDeviceMemoryCommitment\0" + "vkGetDeviceProcAddr\0" + "vkGetDeviceQueue\0" + "vkGetDeviceQueue2\0" + "vkGetEventStatus\0" + "vkGetFenceFdKHR\0" + "vkGetFenceStatus\0" + "vkGetImageMemoryRequirements\0" + "vkGetImageMemoryRequirements2\0" + "vkGetImageMemoryRequirements2KHR\0" + "vkGetImageSparseMemoryRequirements\0" + "vkGetImageSparseMemoryRequirements2\0" + "vkGetImageSparseMemoryRequirements2KHR\0" + "vkGetImageSubresourceLayout\0" + "vkGetMemoryAndroidHardwareBufferANDROID\0" + "vkGetMemoryFdKHR\0" + "vkGetMemoryFdPropertiesKHR\0" + "vkGetPipelineCacheData\0" + "vkGetQueryPoolResults\0" + "vkGetRenderAreaGranularity\0" + "vkGetSemaphoreFdKHR\0" + "vkGetSwapchainCounterEXT\0" + "vkGetSwapchainGrallocUsageANDROID\0" + "vkGetSwapchainImagesKHR\0" + "vkImportFenceFdKHR\0" + "vkImportSemaphoreFdKHR\0" + "vkInvalidateMappedMemoryRanges\0" + "vkMapMemory\0" + "vkMergePipelineCaches\0" + "vkQueueBindSparse\0" + "vkQueuePresentKHR\0" + "vkQueueSignalReleaseImageANDROID\0" + "vkQueueSubmit\0" + "vkQueueWaitIdle\0" + "vkRegisterDeviceEventEXT\0" + "vkRegisterDisplayEventEXT\0" + "vkResetCommandBuffer\0" + "vkResetCommandPool\0" + "vkResetDescriptorPool\0" + "vkResetEvent\0" + "vkResetFences\0" + "vkSetEvent\0" + "vkTrimCommandPool\0" + "vkTrimCommandPoolKHR\0" + "vkUnmapMemory\0" + "vkUpdateDescriptorSetWithTemplate\0" + "vkUpdateDescriptorSetWithTemplateKHR\0" + "vkUpdateDescriptorSets\0" + "vkWaitForFences\0" +; + +static const struct string_map_entry device_string_map_entries[] = { + { 0, 0x6bf780dd, 175 }, /* vkAcquireImageANDROID */ + { 22, 0x82860572, 151 }, /* vkAcquireNextImage2KHR */ + { 45, 0xc3fedb2e, 126 }, /* vkAcquireNextImageKHR */ + { 67, 0x8c0c811a, 72 }, /* vkAllocateCommandBuffers */ + { 92, 0x4c449d3a, 61 }, /* vkAllocateDescriptorSets */ + { 117, 0x522b85d3, 6 }, /* vkAllocateMemory */ + { 134, 0xc54f7327, 74 }, /* vkBeginCommandBuffer */ + { 155, 0x6bcbdcb, 14 }, /* vkBindBufferMemory */ + { 174, 0xc27aaf4f, 143 }, /* vkBindBufferMemory2 */ + { 194, 0x6878d3ce, 144 }, /* vkBindBufferMemory2KHR */ + { 217, 0x5caaae4a, 16 }, /* vkBindImageMemory */ + { 235, 0xa9097118, 145 }, /* vkBindImageMemory2 */ + { 254, 0xf18729ad, 146 }, /* vkBindImageMemory2KHR */ + { 276, 0xe561c19f, 113 }, /* vkCmdBeginConditionalRenderingEXT */ + { 310, 0xf5064ea4, 111 }, /* vkCmdBeginQuery */ + { 326, 0x73251a2c, 189 }, /* vkCmdBeginQueryIndexedEXT */ + { 352, 0xcb7a58e3, 119 }, /* vkCmdBeginRenderPass */ + { 373, 0x8b6b4de6, 179 }, /* vkCmdBeginRenderPass2KHR */ + { 398, 0xb217c94, 187 }, /* vkCmdBeginTransformFeedbackEXT */ + { 429, 0x28c7a5da, 87 }, /* vkCmdBindDescriptorSets */ + { 453, 0x4c22d870, 88 }, /* vkCmdBindIndexBuffer */ + { 474, 0x3af9fd84, 77 }, /* vkCmdBindPipeline */ + { 492, 0x98fdb5cd, 186 }, /* vkCmdBindTransformFeedbackBuffersEXT */ + { 529, 0xa9c83f1d, 89 }, /* vkCmdBindVertexBuffers */ + { 552, 0x331ebf89, 98 }, /* vkCmdBlitImage */ + { 567, 0x93cb5cb8, 105 }, /* vkCmdClearAttachments */ + { 589, 0xb4bc8d08, 103 }, /* vkCmdClearColorImage */ + { 610, 0x4f88e4ba, 104 }, /* vkCmdClearDepthStencilImage */ + { 638, 0xc939a0da, 96 }, /* vkCmdCopyBuffer */ + { 654, 0x929847e, 99 }, /* vkCmdCopyBufferToImage */ + { 677, 0x278effa9, 97 }, /* vkCmdCopyImage */ + { 692, 0x68cddbac, 100 }, /* vkCmdCopyImageToBuffer */ + { 715, 0xdee8c6d4, 117 }, /* vkCmdCopyQueryPoolResults */ + { 741, 0xbd58e867, 94 }, /* vkCmdDispatch */ + { 755, 0xfb767220, 152 }, /* vkCmdDispatchBase */ + { 773, 0x402403e5, 153 }, /* vkCmdDispatchBaseKHR */ + { 794, 0xd6353005, 95 }, /* vkCmdDispatchIndirect */ + { 816, 0x9912c1a1, 90 }, /* vkCmdDraw */ + { 826, 0xbe5a8058, 91 }, /* vkCmdDrawIndexed */ + { 843, 0x94e7ed36, 93 }, /* vkCmdDrawIndexedIndirect */ + { 868, 0xda9e8a2c, 185 }, /* vkCmdDrawIndexedIndirectCountKHR */ + { 901, 0xe9ac41bf, 92 }, /* vkCmdDrawIndirect */ + { 919, 0x80c3b089, 191 }, /* vkCmdDrawIndirectByteCountEXT */ + { 949, 0xf7dd01f5, 184 }, /* vkCmdDrawIndirectCountKHR */ + { 975, 0x18c8217d, 114 }, /* vkCmdEndConditionalRenderingEXT */ + { 1007, 0xd556fd22, 112 }, /* vkCmdEndQuery */ + { 1021, 0xd5c2f48a, 190 }, /* vkCmdEndQueryIndexedEXT */ + { 1045, 0xdcdb0235, 121 }, /* vkCmdEndRenderPass */ + { 1064, 0x57eebe78, 181 }, /* vkCmdEndRenderPass2KHR */ + { 1087, 0xf008d706, 188 }, /* vkCmdEndTransformFeedbackEXT */ + { 1116, 0x9eaabe40, 122 }, /* vkCmdExecuteCommands */ + { 1137, 0x5bdd2ae0, 102 }, /* vkCmdFillBuffer */ + { 1153, 0x2eeec2f9, 120 }, /* vkCmdNextSubpass */ + { 1170, 0x25b621bc, 180 }, /* vkCmdNextSubpass2KHR */ + { 1191, 0x97fccfe8, 110 }, /* vkCmdPipelineBarrier */ + { 1212, 0xb1c6b468, 118 }, /* vkCmdPushConstants */ + { 1231, 0xf17232a1, 128 }, /* vkCmdPushDescriptorSetKHR */ + { 1257, 0x3d528981, 160 }, /* vkCmdPushDescriptorSetWithTemplateKHR */ + { 1295, 0x4fccce28, 108 }, /* vkCmdResetEvent */ + { 1311, 0x2f614082, 115 }, /* vkCmdResetQueryPool */ + { 1331, 0x671bb594, 106 }, /* vkCmdResolveImage */ + { 1349, 0x1c989dfb, 82 }, /* vkCmdSetBlendConstants */ + { 1372, 0x30f14d07, 81 }, /* vkCmdSetDepthBias */ + { 1390, 0x7b3a8a63, 83 }, /* vkCmdSetDepthBounds */ + { 1410, 0xaecdae87, 147 }, /* vkCmdSetDeviceMask */ + { 1429, 0xfbb79356, 148 }, /* vkCmdSetDeviceMaskKHR */ + { 1451, 0xe257f075, 107 }, /* vkCmdSetEvent */ + { 1465, 0x32282165, 80 }, /* vkCmdSetLineWidth */ + { 1483, 0x48f28c7f, 79 }, /* vkCmdSetScissor */ + { 1499, 0xa8f534e2, 84 }, /* vkCmdSetStencilCompareMask */ + { 1526, 0x83e2b024, 86 }, /* vkCmdSetStencilReference */ + { 1551, 0xe7c4b134, 85 }, /* vkCmdSetStencilWriteMask */ + { 1576, 0x53d6c2b, 78 }, /* vkCmdSetViewport */ + { 1593, 0xd2986b5e, 101 }, /* vkCmdUpdateBuffer */ + { 1611, 0x3b9346b3, 109 }, /* vkCmdWaitEvents */ + { 1627, 0xec4d324c, 116 }, /* vkCmdWriteTimestamp */ + { 1647, 0x7d4282b9, 34 }, /* vkCreateBuffer */ + { 1662, 0x925bd256, 36 }, /* vkCreateBufferView */ + { 1681, 0x820fe476, 69 }, /* vkCreateCommandPool */ + { 1701, 0xf70c85eb, 50 }, /* vkCreateComputePipelines */ + { 1726, 0xfb95a8a4, 58 }, /* vkCreateDescriptorPool */ + { 1749, 0x3c14cc74, 56 }, /* vkCreateDescriptorSetLayout */ + { 1777, 0xad3ce733, 154 }, /* vkCreateDescriptorUpdateTemplate */ + { 1810, 0x5189488a, 155 }, /* vkCreateDescriptorUpdateTemplateKHR */ + { 1846, 0x6392dfa7, 192 }, /* vkCreateDmaBufImageINTEL */ + { 1871, 0xe7188731, 26 }, /* vkCreateEvent */ + { 1885, 0x958af968, 19 }, /* vkCreateFence */ + { 1899, 0x887a38c4, 64 }, /* vkCreateFramebuffer */ + { 1919, 0x4b59f96d, 49 }, /* vkCreateGraphicsPipelines */ + { 1945, 0x652128c2, 38 }, /* vkCreateImage */ + { 1959, 0xdce077ff, 41 }, /* vkCreateImageView */ + { 1977, 0xcbf6489f, 45 }, /* vkCreatePipelineCache */ + { 1999, 0x451ef1ed, 52 }, /* vkCreatePipelineLayout */ + { 2022, 0x5edcd92b, 31 }, /* vkCreateQueryPool */ + { 2040, 0x109a9c18, 66 }, /* vkCreateRenderPass */ + { 2059, 0xfa16043b, 178 }, /* vkCreateRenderPass2KHR */ + { 2082, 0x13cf03f, 54 }, /* vkCreateSampler */ + { 2098, 0xe6a58c26, 167 }, /* vkCreateSamplerYcbcrConversion */ + { 2129, 0x7482104f, 168 }, /* vkCreateSamplerYcbcrConversionKHR */ + { 2163, 0xf2065e5b, 24 }, /* vkCreateSemaphore */ + { 2181, 0xa0d3cea2, 43 }, /* vkCreateShaderModule */ + { 2202, 0xcdefcaa8, 123 }, /* vkCreateSwapchainKHR */ + { 2223, 0x94a07a45, 35 }, /* vkDestroyBuffer */ + { 2239, 0x98b27962, 37 }, /* vkDestroyBufferView */ + { 2259, 0xd5d83a0a, 70 }, /* vkDestroyCommandPool */ + { 2280, 0x47bdaf30, 59 }, /* vkDestroyDescriptorPool */ + { 2304, 0xa4227b08, 57 }, /* vkDestroyDescriptorSetLayout */ + { 2333, 0xbb2cbe7f, 156 }, /* vkDestroyDescriptorUpdateTemplate */ + { 2367, 0xaa83901e, 157 }, /* vkDestroyDescriptorUpdateTemplateKHR */ + { 2404, 0x1fbcc9cb, 1 }, /* vkDestroyDevice */ + { 2420, 0x4df27c05, 27 }, /* vkDestroyEvent */ + { 2435, 0xfc64ee3c, 20 }, /* vkDestroyFence */ + { 2450, 0xdc428e58, 65 }, /* vkDestroyFramebuffer */ + { 2471, 0xcbfb1d96, 39 }, /* vkDestroyImage */ + { 2486, 0xb5853953, 42 }, /* vkDestroyImageView */ + { 2505, 0x6aac68af, 51 }, /* vkDestroyPipeline */ + { 2523, 0x4112a673, 46 }, /* vkDestroyPipelineCache */ + { 2546, 0x9146f879, 53 }, /* vkDestroyPipelineLayout */ + { 2570, 0x37819a7f, 32 }, /* vkDestroyQueryPool */ + { 2589, 0x16f14324, 67 }, /* vkDestroyRenderPass */ + { 2609, 0x3b645153, 55 }, /* vkDestroySampler */ + { 2626, 0x20f261b2, 169 }, /* vkDestroySamplerYcbcrConversion */ + { 2658, 0xaaa623a3, 170 }, /* vkDestroySamplerYcbcrConversionKHR */ + { 2693, 0xcaab1faf, 25 }, /* vkDestroySemaphore */ + { 2712, 0x2d77af6e, 44 }, /* vkDestroyShaderModule */ + { 2734, 0x5a93ab74, 124 }, /* vkDestroySwapchainKHR */ + { 2756, 0xd46c5f24, 5 }, /* vkDeviceWaitIdle */ + { 2773, 0xdbb064, 137 }, /* vkDisplayPowerControlEXT */ + { 2798, 0xaffb5725, 75 }, /* vkEndCommandBuffer */ + { 2817, 0xff52f051, 10 }, /* vkFlushMappedMemoryRanges */ + { 2843, 0xb9db2b91, 73 }, /* vkFreeCommandBuffers */ + { 2864, 0x7a1347b1, 62 }, /* vkFreeDescriptorSets */ + { 2885, 0x8f6f838a, 7 }, /* vkFreeMemory */ + { 2898, 0xb891b5e, 182 }, /* vkGetAndroidHardwareBufferPropertiesANDROID */ + { 2942, 0xab98422a, 13 }, /* vkGetBufferMemoryRequirements */ + { 2972, 0xd1fd0638, 161 }, /* vkGetBufferMemoryRequirements2 */ + { 3003, 0x78dbe98d, 162 }, /* vkGetBufferMemoryRequirements2KHR */ + { 3037, 0xcf3070fe, 177 }, /* vkGetCalibratedTimestampsEXT */ + { 3066, 0xfeac9573, 172 }, /* vkGetDescriptorSetLayoutSupport */ + { 3098, 0xd7e44a, 173 }, /* vkGetDescriptorSetLayoutSupportKHR */ + { 3133, 0x2e218c10, 141 }, /* vkGetDeviceGroupPeerMemoryFeatures */ + { 3168, 0xa3809375, 142 }, /* vkGetDeviceGroupPeerMemoryFeaturesKHR */ + { 3206, 0xf72c87d4, 149 }, /* vkGetDeviceGroupPresentCapabilitiesKHR */ + { 3245, 0x6b9448c3, 150 }, /* vkGetDeviceGroupSurfacePresentModesKHR */ + { 3284, 0x46e38db5, 12 }, /* vkGetDeviceMemoryCommitment */ + { 3312, 0xba013486, 0 }, /* vkGetDeviceProcAddr */ + { 3332, 0xcc920d9a, 2 }, /* vkGetDeviceQueue */ + { 3349, 0xb11a6348, 171 }, /* vkGetDeviceQueue2 */ + { 3367, 0x96d834b, 28 }, /* vkGetEventStatus */ + { 3384, 0x69a5d6af, 135 }, /* vkGetFenceFdKHR */ + { 3400, 0x5f391892, 22 }, /* vkGetFenceStatus */ + { 3417, 0x916f1e63, 15 }, /* vkGetImageMemoryRequirements */ + { 3446, 0x56e213f7, 163 }, /* vkGetImageMemoryRequirements2 */ + { 3476, 0x8de28366, 164 }, /* vkGetImageMemoryRequirements2KHR */ + { 3509, 0x15855f5b, 17 }, /* vkGetImageSparseMemoryRequirements */ + { 3544, 0xbd4e3d3f, 165 }, /* vkGetImageSparseMemoryRequirements2 */ + { 3580, 0x3df40f5e, 166 }, /* vkGetImageSparseMemoryRequirements2KHR */ + { 3619, 0x9163b686, 40 }, /* vkGetImageSubresourceLayout */ + { 3647, 0x71220e82, 183 }, /* vkGetMemoryAndroidHardwareBufferANDROID */ + { 3687, 0x503c14c5, 131 }, /* vkGetMemoryFdKHR */ + { 3704, 0xb028a792, 132 }, /* vkGetMemoryFdPropertiesKHR */ + { 3731, 0x2092a349, 47 }, /* vkGetPipelineCacheData */ + { 3754, 0xbf3f2cb3, 33 }, /* vkGetQueryPoolResults */ + { 3776, 0xa9820d22, 68 }, /* vkGetRenderAreaGranularity */ + { 3803, 0x3e0e9884, 133 }, /* vkGetSemaphoreFdKHR */ + { 3823, 0xa4aeb5a, 140 }, /* vkGetSwapchainCounterEXT */ + { 3848, 0x4979c9a3, 174 }, /* vkGetSwapchainGrallocUsageANDROID */ + { 3882, 0x57695f28, 125 }, /* vkGetSwapchainImagesKHR */ + { 3906, 0x51df0390, 136 }, /* vkImportFenceFdKHR */ + { 3925, 0x36337c05, 134 }, /* vkImportSemaphoreFdKHR */ + { 3948, 0x1e115cca, 11 }, /* vkInvalidateMappedMemoryRanges */ + { 3979, 0xcb977bd8, 8 }, /* vkMapMemory */ + { 3991, 0xc3499606, 48 }, /* vkMergePipelineCaches */ + { 4013, 0xc3628a09, 18 }, /* vkQueueBindSparse */ + { 4031, 0xfc5fb6ce, 127 }, /* vkQueuePresentKHR */ + { 4049, 0xa0313eef, 176 }, /* vkQueueSignalReleaseImageANDROID */ + { 4082, 0xfa4713ec, 3 }, /* vkQueueSubmit */ + { 4096, 0x6f8fc2a5, 4 }, /* vkQueueWaitIdle */ + { 4112, 0x26cc78f5, 138 }, /* vkRegisterDeviceEventEXT */ + { 4137, 0x4a0bd849, 139 }, /* vkRegisterDisplayEventEXT */ + { 4163, 0x847dc731, 76 }, /* vkResetCommandBuffer */ + { 4184, 0x6da9f7fd, 71 }, /* vkResetCommandPool */ + { 4203, 0x9bd85f5, 60 }, /* vkResetDescriptorPool */ + { 4225, 0x6d373ba8, 30 }, /* vkResetEvent */ + { 4238, 0x684781dc, 21 }, /* vkResetFences */ + { 4252, 0x592ae5f5, 29 }, /* vkSetEvent */ + { 4263, 0xfef2fb38, 129 }, /* vkTrimCommandPool */ + { 4281, 0x51177c8d, 130 }, /* vkTrimCommandPoolKHR */ + { 4302, 0x1a1a0e2f, 9 }, /* vkUnmapMemory */ + { 4316, 0x5349c9d, 158 }, /* vkUpdateDescriptorSetWithTemplate */ + { 4350, 0x214ad230, 159 }, /* vkUpdateDescriptorSetWithTemplateKHR */ + { 4387, 0xbfd090ae, 63 }, /* vkUpdateDescriptorSets */ + { 4410, 0x19d64c81, 23 }, /* vkWaitForFences */ +}; + +/* Hash table stats: + * size 193 entries + * collisions entries: + * 0 121 + * 1 37 + * 2 9 + * 3 6 + * 4 4 + * 5 6 + * 6 2 + * 7 2 + * 8 0 + * 9+ 6 + */ + +#define none 0xffff +static const uint16_t device_string_map[256] = { + 0x005c, + none, + none, + none, + 0x00a0, + 0x0024, + 0x0031, + 0x003e, + 0x001a, + 0x00ad, + 0x0068, + none, + none, + none, + 0x0095, + none, + 0x008c, + 0x00ab, + none, + none, + none, + none, + none, + 0x00b1, + 0x000b, + 0x009a, + 0x0003, + 0x006a, + none, + 0x0017, + 0x006c, + none, + 0x0022, + 0x0097, + 0x002d, + none, + 0x0046, + 0x0080, + 0x0061, + 0x0006, + 0x003a, + none, + 0x0086, + 0x0048, + 0x000f, + none, + 0x0002, + 0x00bc, + 0x0069, + 0x0055, + none, + 0x0052, + 0x0047, + 0x002f, + 0x0027, + 0x0077, + 0x0087, + none, + 0x0004, + 0x005f, + 0x006f, + none, + 0x005d, + 0x0028, + 0x0032, + 0x00b2, + none, + 0x00be, + 0x00b4, + 0x0066, + none, + none, + 0x0093, + 0x00a1, + 0x000a, + 0x0094, + 0x004b, + none, + 0x00a7, + 0x0008, + none, + 0x005e, + 0x0060, + 0x0072, + 0x00b6, + none, + 0x0041, + none, + 0x0026, + none, + 0x00a5, + 0x0063, + 0x00b3, + 0x007e, + 0x0049, + none, + none, + none, + 0x0062, + 0x003f, + 0x006e, + 0x0043, + 0x0078, + 0x0021, + 0x0037, + 0x004d, + none, + 0x0070, + none, + 0x0058, + 0x007c, + none, + 0x0014, + 0x0085, + 0x0001, + 0x0074, + 0x0051, + 0x0042, + 0x004e, + 0x007f, + 0x0030, + 0x0075, + 0x00b9, + 0x0056, + none, + 0x002c, + 0x001d, + 0x0044, + none, + 0x0039, + 0x003b, + 0x008b, + 0x0015, + none, + 0x008a, + 0x0040, + 0x0067, + 0x0018, + 0x002e, + 0x009b, + 0x0099, + 0x0088, + none, + none, + 0x00a8, + 0x0082, + 0x006b, + none, + 0x0012, + 0x009e, + 0x0071, + 0x009c, + none, + 0x0091, + 0x007d, + 0x008d, + 0x002a, + 0x0053, + 0x00a3, + 0x000d, + 0x00bb, + 0x0025, + 0x0064, + 0x007a, + 0x000e, + 0x0076, + none, + 0x003c, + 0x0065, + 0x001e, + 0x00a4, + none, + 0x001f, + 0x000c, + 0x00bf, + 0x0073, + 0x0081, + 0x0083, + 0x005b, + 0x004a, + 0x0038, + 0x0090, + 0x00a6, + 0x0050, + 0x0019, + 0x004c, + 0x001b, + 0x00b7, + 0x0035, + 0x00ba, + none, + 0x0029, + 0x0092, + none, + 0x0059, + 0x0084, + 0x0057, + 0x0079, + 0x00a2, + none, + none, + none, + 0x00aa, + 0x0007, + none, + 0x0016, + 0x0009, + none, + none, + none, + 0x009d, + 0x0005, + 0x0020, + 0x007b, + 0x008f, + 0x00ac, + 0x009f, + none, + 0x0013, + none, + 0x00b8, + 0x0000, + 0x006d, + none, + 0x0033, + 0x00ae, + 0x0045, + 0x0010, + none, + 0x0023, + 0x0011, + 0x008e, + 0x0036, + 0x00a9, + 0x00c0, + 0x004f, + 0x00b0, + 0x001c, + none, + 0x00af, + none, + 0x0096, + none, + 0x0054, + none, + 0x002b, + none, + 0x0098, + none, + 0x0034, + none, + 0x003d, + 0x00bd, + 0x00b5, + 0x0089, + 0x005a, +}; + +static int +device_string_map_lookup(const char *str) +{ + static const uint32_t prime_factor = 5024183; + static const uint32_t prime_step = 19; + const struct string_map_entry *e; + uint32_t hash, h; + uint16_t i; + const char *p; + + hash = 0; + for (p = str; *p; p++) + hash = hash * prime_factor + *p; + + h = hash; + while (1) { + i = device_string_map[h & 255]; + if (i == none) + return -1; + e = &device_string_map_entries[i]; + if (e->hash == hash && strcmp(str, device_strings + e->name) == 0) + return e->num; + h += prime_step; + } + + return -1; +} + + +/* Weak aliases for all potential implementations. These will resolve to + * NULL if they're not defined, which lets the resolve_entrypoint() function + * either pick the correct entry point. + */ + + VkResult anv_CreateInstance(const VkInstanceCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkInstance* pInstance) __attribute__ ((weak)); + void anv_DestroyInstance(VkInstance instance, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult anv_EnumeratePhysicalDevices(VkInstance instance, uint32_t* pPhysicalDeviceCount, VkPhysicalDevice* pPhysicalDevices) __attribute__ ((weak)); + PFN_vkVoidFunction anv_GetInstanceProcAddr(VkInstance instance, const char* pName) __attribute__ ((weak)); + void anv_GetPhysicalDeviceProperties(VkPhysicalDevice physicalDevice, VkPhysicalDeviceProperties* pProperties) __attribute__ ((weak)); + void anv_GetPhysicalDeviceQueueFamilyProperties(VkPhysicalDevice physicalDevice, uint32_t* pQueueFamilyPropertyCount, VkQueueFamilyProperties* pQueueFamilyProperties) __attribute__ ((weak)); + void anv_GetPhysicalDeviceMemoryProperties(VkPhysicalDevice physicalDevice, VkPhysicalDeviceMemoryProperties* pMemoryProperties) __attribute__ ((weak)); + void anv_GetPhysicalDeviceFeatures(VkPhysicalDevice physicalDevice, VkPhysicalDeviceFeatures* pFeatures) __attribute__ ((weak)); + void anv_GetPhysicalDeviceFormatProperties(VkPhysicalDevice physicalDevice, VkFormat format, VkFormatProperties* pFormatProperties) __attribute__ ((weak)); + VkResult anv_GetPhysicalDeviceImageFormatProperties(VkPhysicalDevice physicalDevice, VkFormat format, VkImageType type, VkImageTiling tiling, VkImageUsageFlags usage, VkImageCreateFlags flags, VkImageFormatProperties* pImageFormatProperties) __attribute__ ((weak)); + VkResult anv_CreateDevice(VkPhysicalDevice physicalDevice, const VkDeviceCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDevice* pDevice) __attribute__ ((weak)); + VkResult anv_EnumerateInstanceVersion(uint32_t* pApiVersion) __attribute__ ((weak)); + VkResult anv_EnumerateInstanceLayerProperties(uint32_t* pPropertyCount, VkLayerProperties* pProperties) __attribute__ ((weak)); + VkResult anv_EnumerateInstanceExtensionProperties(const char* pLayerName, uint32_t* pPropertyCount, VkExtensionProperties* pProperties) __attribute__ ((weak)); + VkResult anv_EnumerateDeviceLayerProperties(VkPhysicalDevice physicalDevice, uint32_t* pPropertyCount, VkLayerProperties* pProperties) __attribute__ ((weak)); + VkResult anv_EnumerateDeviceExtensionProperties(VkPhysicalDevice physicalDevice, const char* pLayerName, uint32_t* pPropertyCount, VkExtensionProperties* pProperties) __attribute__ ((weak)); + void anv_GetPhysicalDeviceSparseImageFormatProperties(VkPhysicalDevice physicalDevice, VkFormat format, VkImageType type, VkSampleCountFlagBits samples, VkImageUsageFlags usage, VkImageTiling tiling, uint32_t* pPropertyCount, VkSparseImageFormatProperties* pProperties) __attribute__ ((weak)); + VkResult anv_GetPhysicalDeviceDisplayPropertiesKHR(VkPhysicalDevice physicalDevice, uint32_t* pPropertyCount, VkDisplayPropertiesKHR* pProperties) __attribute__ ((weak)); + VkResult anv_GetPhysicalDeviceDisplayPlanePropertiesKHR(VkPhysicalDevice physicalDevice, uint32_t* pPropertyCount, VkDisplayPlanePropertiesKHR* pProperties) __attribute__ ((weak)); + VkResult anv_GetDisplayPlaneSupportedDisplaysKHR(VkPhysicalDevice physicalDevice, uint32_t planeIndex, uint32_t* pDisplayCount, VkDisplayKHR* pDisplays) __attribute__ ((weak)); + VkResult anv_GetDisplayModePropertiesKHR(VkPhysicalDevice physicalDevice, VkDisplayKHR display, uint32_t* pPropertyCount, VkDisplayModePropertiesKHR* pProperties) __attribute__ ((weak)); + VkResult anv_CreateDisplayModeKHR(VkPhysicalDevice physicalDevice, VkDisplayKHR display, const VkDisplayModeCreateInfoKHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDisplayModeKHR* pMode) __attribute__ ((weak)); + VkResult anv_GetDisplayPlaneCapabilitiesKHR(VkPhysicalDevice physicalDevice, VkDisplayModeKHR mode, uint32_t planeIndex, VkDisplayPlaneCapabilitiesKHR* pCapabilities) __attribute__ ((weak)); + VkResult anv_CreateDisplayPlaneSurfaceKHR(VkInstance instance, const VkDisplaySurfaceCreateInfoKHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSurfaceKHR* pSurface) __attribute__ ((weak)); + void anv_DestroySurfaceKHR(VkInstance instance, VkSurfaceKHR surface, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult anv_GetPhysicalDeviceSurfaceSupportKHR(VkPhysicalDevice physicalDevice, uint32_t queueFamilyIndex, VkSurfaceKHR surface, VkBool32* pSupported) __attribute__ ((weak)); + VkResult anv_GetPhysicalDeviceSurfaceCapabilitiesKHR(VkPhysicalDevice physicalDevice, VkSurfaceKHR surface, VkSurfaceCapabilitiesKHR* pSurfaceCapabilities) __attribute__ ((weak)); + VkResult anv_GetPhysicalDeviceSurfaceFormatsKHR(VkPhysicalDevice physicalDevice, VkSurfaceKHR surface, uint32_t* pSurfaceFormatCount, VkSurfaceFormatKHR* pSurfaceFormats) __attribute__ ((weak)); + VkResult anv_GetPhysicalDeviceSurfacePresentModesKHR(VkPhysicalDevice physicalDevice, VkSurfaceKHR surface, uint32_t* pPresentModeCount, VkPresentModeKHR* pPresentModes) __attribute__ ((weak)); +#ifdef VK_USE_PLATFORM_WAYLAND_KHR + VkResult anv_CreateWaylandSurfaceKHR(VkInstance instance, const VkWaylandSurfaceCreateInfoKHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSurfaceKHR* pSurface) __attribute__ ((weak)); +#endif // VK_USE_PLATFORM_WAYLAND_KHR +#ifdef VK_USE_PLATFORM_WAYLAND_KHR + VkBool32 anv_GetPhysicalDeviceWaylandPresentationSupportKHR(VkPhysicalDevice physicalDevice, uint32_t queueFamilyIndex, struct wl_display* display) __attribute__ ((weak)); +#endif // VK_USE_PLATFORM_WAYLAND_KHR +#ifdef VK_USE_PLATFORM_XLIB_KHR + VkResult anv_CreateXlibSurfaceKHR(VkInstance instance, const VkXlibSurfaceCreateInfoKHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSurfaceKHR* pSurface) __attribute__ ((weak)); +#endif // VK_USE_PLATFORM_XLIB_KHR +#ifdef VK_USE_PLATFORM_XLIB_KHR + VkBool32 anv_GetPhysicalDeviceXlibPresentationSupportKHR(VkPhysicalDevice physicalDevice, uint32_t queueFamilyIndex, Display* dpy, VisualID visualID) __attribute__ ((weak)); +#endif // VK_USE_PLATFORM_XLIB_KHR +#ifdef VK_USE_PLATFORM_XCB_KHR + VkResult anv_CreateXcbSurfaceKHR(VkInstance instance, const VkXcbSurfaceCreateInfoKHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSurfaceKHR* pSurface) __attribute__ ((weak)); +#endif // VK_USE_PLATFORM_XCB_KHR +#ifdef VK_USE_PLATFORM_XCB_KHR + VkBool32 anv_GetPhysicalDeviceXcbPresentationSupportKHR(VkPhysicalDevice physicalDevice, uint32_t queueFamilyIndex, xcb_connection_t* connection, xcb_visualid_t visual_id) __attribute__ ((weak)); +#endif // VK_USE_PLATFORM_XCB_KHR + VkResult anv_CreateDebugReportCallbackEXT(VkInstance instance, const VkDebugReportCallbackCreateInfoEXT* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDebugReportCallbackEXT* pCallback) __attribute__ ((weak)); + void anv_DestroyDebugReportCallbackEXT(VkInstance instance, VkDebugReportCallbackEXT callback, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + void anv_DebugReportMessageEXT(VkInstance instance, VkDebugReportFlagsEXT flags, VkDebugReportObjectTypeEXT objectType, uint64_t object, size_t location, int32_t messageCode, const char* pLayerPrefix, const char* pMessage) __attribute__ ((weak)); + void anv_GetPhysicalDeviceFeatures2(VkPhysicalDevice physicalDevice, VkPhysicalDeviceFeatures2* pFeatures) __attribute__ ((weak)); + void anv_GetPhysicalDeviceProperties2(VkPhysicalDevice physicalDevice, VkPhysicalDeviceProperties2* pProperties) __attribute__ ((weak)); + void anv_GetPhysicalDeviceFormatProperties2(VkPhysicalDevice physicalDevice, VkFormat format, VkFormatProperties2* pFormatProperties) __attribute__ ((weak)); + VkResult anv_GetPhysicalDeviceImageFormatProperties2(VkPhysicalDevice physicalDevice, const VkPhysicalDeviceImageFormatInfo2* pImageFormatInfo, VkImageFormatProperties2* pImageFormatProperties) __attribute__ ((weak)); + void anv_GetPhysicalDeviceQueueFamilyProperties2(VkPhysicalDevice physicalDevice, uint32_t* pQueueFamilyPropertyCount, VkQueueFamilyProperties2* pQueueFamilyProperties) __attribute__ ((weak)); + void anv_GetPhysicalDeviceMemoryProperties2(VkPhysicalDevice physicalDevice, VkPhysicalDeviceMemoryProperties2* pMemoryProperties) __attribute__ ((weak)); + void anv_GetPhysicalDeviceSparseImageFormatProperties2(VkPhysicalDevice physicalDevice, const VkPhysicalDeviceSparseImageFormatInfo2* pFormatInfo, uint32_t* pPropertyCount, VkSparseImageFormatProperties2* pProperties) __attribute__ ((weak)); + void anv_GetPhysicalDeviceExternalBufferProperties(VkPhysicalDevice physicalDevice, const VkPhysicalDeviceExternalBufferInfo* pExternalBufferInfo, VkExternalBufferProperties* pExternalBufferProperties) __attribute__ ((weak)); + void anv_GetPhysicalDeviceExternalSemaphoreProperties(VkPhysicalDevice physicalDevice, const VkPhysicalDeviceExternalSemaphoreInfo* pExternalSemaphoreInfo, VkExternalSemaphoreProperties* pExternalSemaphoreProperties) __attribute__ ((weak)); + void anv_GetPhysicalDeviceExternalFenceProperties(VkPhysicalDevice physicalDevice, const VkPhysicalDeviceExternalFenceInfo* pExternalFenceInfo, VkExternalFenceProperties* pExternalFenceProperties) __attribute__ ((weak)); + VkResult anv_ReleaseDisplayEXT(VkPhysicalDevice physicalDevice, VkDisplayKHR display) __attribute__ ((weak)); +#ifdef VK_USE_PLATFORM_XLIB_XRANDR_EXT + VkResult anv_AcquireXlibDisplayEXT(VkPhysicalDevice physicalDevice, Display* dpy, VkDisplayKHR display) __attribute__ ((weak)); +#endif // VK_USE_PLATFORM_XLIB_XRANDR_EXT +#ifdef VK_USE_PLATFORM_XLIB_XRANDR_EXT + VkResult anv_GetRandROutputDisplayEXT(VkPhysicalDevice physicalDevice, Display* dpy, RROutput rrOutput, VkDisplayKHR* pDisplay) __attribute__ ((weak)); +#endif // VK_USE_PLATFORM_XLIB_XRANDR_EXT + VkResult anv_GetPhysicalDeviceSurfaceCapabilities2EXT(VkPhysicalDevice physicalDevice, VkSurfaceKHR surface, VkSurfaceCapabilities2EXT* pSurfaceCapabilities) __attribute__ ((weak)); + VkResult anv_EnumeratePhysicalDeviceGroups(VkInstance instance, uint32_t* pPhysicalDeviceGroupCount, VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties) __attribute__ ((weak)); + VkResult anv_GetPhysicalDevicePresentRectanglesKHR(VkPhysicalDevice physicalDevice, VkSurfaceKHR surface, uint32_t* pRectCount, VkRect2D* pRects) __attribute__ ((weak)); + VkResult anv_GetPhysicalDeviceSurfaceCapabilities2KHR(VkPhysicalDevice physicalDevice, const VkPhysicalDeviceSurfaceInfo2KHR* pSurfaceInfo, VkSurfaceCapabilities2KHR* pSurfaceCapabilities) __attribute__ ((weak)); + VkResult anv_GetPhysicalDeviceSurfaceFormats2KHR(VkPhysicalDevice physicalDevice, const VkPhysicalDeviceSurfaceInfo2KHR* pSurfaceInfo, uint32_t* pSurfaceFormatCount, VkSurfaceFormat2KHR* pSurfaceFormats) __attribute__ ((weak)); + VkResult anv_GetPhysicalDeviceDisplayProperties2KHR(VkPhysicalDevice physicalDevice, uint32_t* pPropertyCount, VkDisplayProperties2KHR* pProperties) __attribute__ ((weak)); + VkResult anv_GetPhysicalDeviceDisplayPlaneProperties2KHR(VkPhysicalDevice physicalDevice, uint32_t* pPropertyCount, VkDisplayPlaneProperties2KHR* pProperties) __attribute__ ((weak)); + VkResult anv_GetDisplayModeProperties2KHR(VkPhysicalDevice physicalDevice, VkDisplayKHR display, uint32_t* pPropertyCount, VkDisplayModeProperties2KHR* pProperties) __attribute__ ((weak)); + VkResult anv_GetDisplayPlaneCapabilities2KHR(VkPhysicalDevice physicalDevice, const VkDisplayPlaneInfo2KHR* pDisplayPlaneInfo, VkDisplayPlaneCapabilities2KHR* pCapabilities) __attribute__ ((weak)); + VkResult anv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(VkPhysicalDevice physicalDevice, uint32_t* pTimeDomainCount, VkTimeDomainEXT* pTimeDomains) __attribute__ ((weak)); + +const struct anv_instance_dispatch_table anv_instance_dispatch_table = { + .vkCreateInstance = anv_CreateInstance, + .vkDestroyInstance = anv_DestroyInstance, + .vkEnumeratePhysicalDevices = anv_EnumeratePhysicalDevices, + .vkGetInstanceProcAddr = anv_GetInstanceProcAddr, + .vkGetPhysicalDeviceProperties = anv_GetPhysicalDeviceProperties, + .vkGetPhysicalDeviceQueueFamilyProperties = anv_GetPhysicalDeviceQueueFamilyProperties, + .vkGetPhysicalDeviceMemoryProperties = anv_GetPhysicalDeviceMemoryProperties, + .vkGetPhysicalDeviceFeatures = anv_GetPhysicalDeviceFeatures, + .vkGetPhysicalDeviceFormatProperties = anv_GetPhysicalDeviceFormatProperties, + .vkGetPhysicalDeviceImageFormatProperties = anv_GetPhysicalDeviceImageFormatProperties, + .vkCreateDevice = anv_CreateDevice, + .vkEnumerateInstanceVersion = anv_EnumerateInstanceVersion, + .vkEnumerateInstanceLayerProperties = anv_EnumerateInstanceLayerProperties, + .vkEnumerateInstanceExtensionProperties = anv_EnumerateInstanceExtensionProperties, + .vkEnumerateDeviceLayerProperties = anv_EnumerateDeviceLayerProperties, + .vkEnumerateDeviceExtensionProperties = anv_EnumerateDeviceExtensionProperties, + .vkGetPhysicalDeviceSparseImageFormatProperties = anv_GetPhysicalDeviceSparseImageFormatProperties, + .vkGetPhysicalDeviceDisplayPropertiesKHR = anv_GetPhysicalDeviceDisplayPropertiesKHR, + .vkGetPhysicalDeviceDisplayPlanePropertiesKHR = anv_GetPhysicalDeviceDisplayPlanePropertiesKHR, + .vkGetDisplayPlaneSupportedDisplaysKHR = anv_GetDisplayPlaneSupportedDisplaysKHR, + .vkGetDisplayModePropertiesKHR = anv_GetDisplayModePropertiesKHR, + .vkCreateDisplayModeKHR = anv_CreateDisplayModeKHR, + .vkGetDisplayPlaneCapabilitiesKHR = anv_GetDisplayPlaneCapabilitiesKHR, + .vkCreateDisplayPlaneSurfaceKHR = anv_CreateDisplayPlaneSurfaceKHR, + .vkDestroySurfaceKHR = anv_DestroySurfaceKHR, + .vkGetPhysicalDeviceSurfaceSupportKHR = anv_GetPhysicalDeviceSurfaceSupportKHR, + .vkGetPhysicalDeviceSurfaceCapabilitiesKHR = anv_GetPhysicalDeviceSurfaceCapabilitiesKHR, + .vkGetPhysicalDeviceSurfaceFormatsKHR = anv_GetPhysicalDeviceSurfaceFormatsKHR, + .vkGetPhysicalDeviceSurfacePresentModesKHR = anv_GetPhysicalDeviceSurfacePresentModesKHR, +#ifdef VK_USE_PLATFORM_WAYLAND_KHR + .vkCreateWaylandSurfaceKHR = anv_CreateWaylandSurfaceKHR, +#endif // VK_USE_PLATFORM_WAYLAND_KHR +#ifdef VK_USE_PLATFORM_WAYLAND_KHR + .vkGetPhysicalDeviceWaylandPresentationSupportKHR = anv_GetPhysicalDeviceWaylandPresentationSupportKHR, +#endif // VK_USE_PLATFORM_WAYLAND_KHR +#ifdef VK_USE_PLATFORM_XLIB_KHR + .vkCreateXlibSurfaceKHR = anv_CreateXlibSurfaceKHR, +#endif // VK_USE_PLATFORM_XLIB_KHR +#ifdef VK_USE_PLATFORM_XLIB_KHR + .vkGetPhysicalDeviceXlibPresentationSupportKHR = anv_GetPhysicalDeviceXlibPresentationSupportKHR, +#endif // VK_USE_PLATFORM_XLIB_KHR +#ifdef VK_USE_PLATFORM_XCB_KHR + .vkCreateXcbSurfaceKHR = anv_CreateXcbSurfaceKHR, +#endif // VK_USE_PLATFORM_XCB_KHR +#ifdef VK_USE_PLATFORM_XCB_KHR + .vkGetPhysicalDeviceXcbPresentationSupportKHR = anv_GetPhysicalDeviceXcbPresentationSupportKHR, +#endif // VK_USE_PLATFORM_XCB_KHR + .vkCreateDebugReportCallbackEXT = anv_CreateDebugReportCallbackEXT, + .vkDestroyDebugReportCallbackEXT = anv_DestroyDebugReportCallbackEXT, + .vkDebugReportMessageEXT = anv_DebugReportMessageEXT, + .vkGetPhysicalDeviceFeatures2 = anv_GetPhysicalDeviceFeatures2, + .vkGetPhysicalDeviceFeatures2KHR = anv_GetPhysicalDeviceFeatures2, + .vkGetPhysicalDeviceProperties2 = anv_GetPhysicalDeviceProperties2, + .vkGetPhysicalDeviceProperties2KHR = anv_GetPhysicalDeviceProperties2, + .vkGetPhysicalDeviceFormatProperties2 = anv_GetPhysicalDeviceFormatProperties2, + .vkGetPhysicalDeviceFormatProperties2KHR = anv_GetPhysicalDeviceFormatProperties2, + .vkGetPhysicalDeviceImageFormatProperties2 = anv_GetPhysicalDeviceImageFormatProperties2, + .vkGetPhysicalDeviceImageFormatProperties2KHR = anv_GetPhysicalDeviceImageFormatProperties2, + .vkGetPhysicalDeviceQueueFamilyProperties2 = anv_GetPhysicalDeviceQueueFamilyProperties2, + .vkGetPhysicalDeviceQueueFamilyProperties2KHR = anv_GetPhysicalDeviceQueueFamilyProperties2, + .vkGetPhysicalDeviceMemoryProperties2 = anv_GetPhysicalDeviceMemoryProperties2, + .vkGetPhysicalDeviceMemoryProperties2KHR = anv_GetPhysicalDeviceMemoryProperties2, + .vkGetPhysicalDeviceSparseImageFormatProperties2 = anv_GetPhysicalDeviceSparseImageFormatProperties2, + .vkGetPhysicalDeviceSparseImageFormatProperties2KHR = anv_GetPhysicalDeviceSparseImageFormatProperties2, + .vkGetPhysicalDeviceExternalBufferProperties = anv_GetPhysicalDeviceExternalBufferProperties, + .vkGetPhysicalDeviceExternalBufferPropertiesKHR = anv_GetPhysicalDeviceExternalBufferProperties, + .vkGetPhysicalDeviceExternalSemaphoreProperties = anv_GetPhysicalDeviceExternalSemaphoreProperties, + .vkGetPhysicalDeviceExternalSemaphorePropertiesKHR = anv_GetPhysicalDeviceExternalSemaphoreProperties, + .vkGetPhysicalDeviceExternalFenceProperties = anv_GetPhysicalDeviceExternalFenceProperties, + .vkGetPhysicalDeviceExternalFencePropertiesKHR = anv_GetPhysicalDeviceExternalFenceProperties, + .vkReleaseDisplayEXT = anv_ReleaseDisplayEXT, +#ifdef VK_USE_PLATFORM_XLIB_XRANDR_EXT + .vkAcquireXlibDisplayEXT = anv_AcquireXlibDisplayEXT, +#endif // VK_USE_PLATFORM_XLIB_XRANDR_EXT +#ifdef VK_USE_PLATFORM_XLIB_XRANDR_EXT + .vkGetRandROutputDisplayEXT = anv_GetRandROutputDisplayEXT, +#endif // VK_USE_PLATFORM_XLIB_XRANDR_EXT + .vkGetPhysicalDeviceSurfaceCapabilities2EXT = anv_GetPhysicalDeviceSurfaceCapabilities2EXT, + .vkEnumeratePhysicalDeviceGroups = anv_EnumeratePhysicalDeviceGroups, + .vkEnumeratePhysicalDeviceGroupsKHR = anv_EnumeratePhysicalDeviceGroups, + .vkGetPhysicalDevicePresentRectanglesKHR = anv_GetPhysicalDevicePresentRectanglesKHR, + .vkGetPhysicalDeviceSurfaceCapabilities2KHR = anv_GetPhysicalDeviceSurfaceCapabilities2KHR, + .vkGetPhysicalDeviceSurfaceFormats2KHR = anv_GetPhysicalDeviceSurfaceFormats2KHR, + .vkGetPhysicalDeviceDisplayProperties2KHR = anv_GetPhysicalDeviceDisplayProperties2KHR, + .vkGetPhysicalDeviceDisplayPlaneProperties2KHR = anv_GetPhysicalDeviceDisplayPlaneProperties2KHR, + .vkGetDisplayModeProperties2KHR = anv_GetDisplayModeProperties2KHR, + .vkGetDisplayPlaneCapabilities2KHR = anv_GetDisplayPlaneCapabilities2KHR, + .vkGetPhysicalDeviceCalibrateableTimeDomainsEXT = anv_GetPhysicalDeviceCalibrateableTimeDomainsEXT, +}; + + PFN_vkVoidFunction __attribute__ ((weak)) + anv_GetDeviceProcAddr(VkDevice device, const char* pName) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkGetDeviceProcAddr(device, pName); + } + void __attribute__ ((weak)) + anv_DestroyDevice(VkDevice device, const VkAllocationCallbacks* pAllocator) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkDestroyDevice(device, pAllocator); + } + void __attribute__ ((weak)) + anv_GetDeviceQueue(VkDevice device, uint32_t queueFamilyIndex, uint32_t queueIndex, VkQueue* pQueue) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkGetDeviceQueue(device, queueFamilyIndex, queueIndex, pQueue); + } + VkResult __attribute__ ((weak)) + anv_QueueSubmit(VkQueue queue, uint32_t submitCount, const VkSubmitInfo* pSubmits, VkFence fence) + { + ANV_FROM_HANDLE(anv_queue, anv_queue, queue); + return anv_queue->device->dispatch.vkQueueSubmit(queue, submitCount, pSubmits, fence); + } + VkResult __attribute__ ((weak)) + anv_QueueWaitIdle(VkQueue queue) + { + ANV_FROM_HANDLE(anv_queue, anv_queue, queue); + return anv_queue->device->dispatch.vkQueueWaitIdle(queue); + } + VkResult __attribute__ ((weak)) + anv_DeviceWaitIdle(VkDevice device) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkDeviceWaitIdle(device); + } + VkResult __attribute__ ((weak)) + anv_AllocateMemory(VkDevice device, const VkMemoryAllocateInfo* pAllocateInfo, const VkAllocationCallbacks* pAllocator, VkDeviceMemory* pMemory) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkAllocateMemory(device, pAllocateInfo, pAllocator, pMemory); + } + void __attribute__ ((weak)) + anv_FreeMemory(VkDevice device, VkDeviceMemory memory, const VkAllocationCallbacks* pAllocator) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkFreeMemory(device, memory, pAllocator); + } + VkResult __attribute__ ((weak)) + anv_MapMemory(VkDevice device, VkDeviceMemory memory, VkDeviceSize offset, VkDeviceSize size, VkMemoryMapFlags flags, void** ppData) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkMapMemory(device, memory, offset, size, flags, ppData); + } + void __attribute__ ((weak)) + anv_UnmapMemory(VkDevice device, VkDeviceMemory memory) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkUnmapMemory(device, memory); + } + VkResult __attribute__ ((weak)) + anv_FlushMappedMemoryRanges(VkDevice device, uint32_t memoryRangeCount, const VkMappedMemoryRange* pMemoryRanges) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkFlushMappedMemoryRanges(device, memoryRangeCount, pMemoryRanges); + } + VkResult __attribute__ ((weak)) + anv_InvalidateMappedMemoryRanges(VkDevice device, uint32_t memoryRangeCount, const VkMappedMemoryRange* pMemoryRanges) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkInvalidateMappedMemoryRanges(device, memoryRangeCount, pMemoryRanges); + } + void __attribute__ ((weak)) + anv_GetDeviceMemoryCommitment(VkDevice device, VkDeviceMemory memory, VkDeviceSize* pCommittedMemoryInBytes) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkGetDeviceMemoryCommitment(device, memory, pCommittedMemoryInBytes); + } + void __attribute__ ((weak)) + anv_GetBufferMemoryRequirements(VkDevice device, VkBuffer buffer, VkMemoryRequirements* pMemoryRequirements) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkGetBufferMemoryRequirements(device, buffer, pMemoryRequirements); + } + VkResult __attribute__ ((weak)) + anv_BindBufferMemory(VkDevice device, VkBuffer buffer, VkDeviceMemory memory, VkDeviceSize memoryOffset) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkBindBufferMemory(device, buffer, memory, memoryOffset); + } + void __attribute__ ((weak)) + anv_GetImageMemoryRequirements(VkDevice device, VkImage image, VkMemoryRequirements* pMemoryRequirements) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkGetImageMemoryRequirements(device, image, pMemoryRequirements); + } + VkResult __attribute__ ((weak)) + anv_BindImageMemory(VkDevice device, VkImage image, VkDeviceMemory memory, VkDeviceSize memoryOffset) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkBindImageMemory(device, image, memory, memoryOffset); + } + void __attribute__ ((weak)) + anv_GetImageSparseMemoryRequirements(VkDevice device, VkImage image, uint32_t* pSparseMemoryRequirementCount, VkSparseImageMemoryRequirements* pSparseMemoryRequirements) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkGetImageSparseMemoryRequirements(device, image, pSparseMemoryRequirementCount, pSparseMemoryRequirements); + } + VkResult __attribute__ ((weak)) + anv_QueueBindSparse(VkQueue queue, uint32_t bindInfoCount, const VkBindSparseInfo* pBindInfo, VkFence fence) + { + ANV_FROM_HANDLE(anv_queue, anv_queue, queue); + return anv_queue->device->dispatch.vkQueueBindSparse(queue, bindInfoCount, pBindInfo, fence); + } + VkResult __attribute__ ((weak)) + anv_CreateFence(VkDevice device, const VkFenceCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkCreateFence(device, pCreateInfo, pAllocator, pFence); + } + void __attribute__ ((weak)) + anv_DestroyFence(VkDevice device, VkFence fence, const VkAllocationCallbacks* pAllocator) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkDestroyFence(device, fence, pAllocator); + } + VkResult __attribute__ ((weak)) + anv_ResetFences(VkDevice device, uint32_t fenceCount, const VkFence* pFences) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkResetFences(device, fenceCount, pFences); + } + VkResult __attribute__ ((weak)) + anv_GetFenceStatus(VkDevice device, VkFence fence) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkGetFenceStatus(device, fence); + } + VkResult __attribute__ ((weak)) + anv_WaitForFences(VkDevice device, uint32_t fenceCount, const VkFence* pFences, VkBool32 waitAll, uint64_t timeout) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkWaitForFences(device, fenceCount, pFences, waitAll, timeout); + } + VkResult __attribute__ ((weak)) + anv_CreateSemaphore(VkDevice device, const VkSemaphoreCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSemaphore* pSemaphore) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkCreateSemaphore(device, pCreateInfo, pAllocator, pSemaphore); + } + void __attribute__ ((weak)) + anv_DestroySemaphore(VkDevice device, VkSemaphore semaphore, const VkAllocationCallbacks* pAllocator) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkDestroySemaphore(device, semaphore, pAllocator); + } + VkResult __attribute__ ((weak)) + anv_CreateEvent(VkDevice device, const VkEventCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkEvent* pEvent) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkCreateEvent(device, pCreateInfo, pAllocator, pEvent); + } + void __attribute__ ((weak)) + anv_DestroyEvent(VkDevice device, VkEvent event, const VkAllocationCallbacks* pAllocator) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkDestroyEvent(device, event, pAllocator); + } + VkResult __attribute__ ((weak)) + anv_GetEventStatus(VkDevice device, VkEvent event) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkGetEventStatus(device, event); + } + VkResult __attribute__ ((weak)) + anv_SetEvent(VkDevice device, VkEvent event) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkSetEvent(device, event); + } + VkResult __attribute__ ((weak)) + anv_ResetEvent(VkDevice device, VkEvent event) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkResetEvent(device, event); + } + VkResult __attribute__ ((weak)) + anv_CreateQueryPool(VkDevice device, const VkQueryPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkQueryPool* pQueryPool) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkCreateQueryPool(device, pCreateInfo, pAllocator, pQueryPool); + } + void __attribute__ ((weak)) + anv_DestroyQueryPool(VkDevice device, VkQueryPool queryPool, const VkAllocationCallbacks* pAllocator) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkDestroyQueryPool(device, queryPool, pAllocator); + } + VkResult __attribute__ ((weak)) + anv_GetQueryPoolResults(VkDevice device, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount, size_t dataSize, void* pData, VkDeviceSize stride, VkQueryResultFlags flags) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkGetQueryPoolResults(device, queryPool, firstQuery, queryCount, dataSize, pData, stride, flags); + } + VkResult __attribute__ ((weak)) + anv_CreateBuffer(VkDevice device, const VkBufferCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkBuffer* pBuffer) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkCreateBuffer(device, pCreateInfo, pAllocator, pBuffer); + } + void __attribute__ ((weak)) + anv_DestroyBuffer(VkDevice device, VkBuffer buffer, const VkAllocationCallbacks* pAllocator) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkDestroyBuffer(device, buffer, pAllocator); + } + VkResult __attribute__ ((weak)) + anv_CreateBufferView(VkDevice device, const VkBufferViewCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkBufferView* pView) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkCreateBufferView(device, pCreateInfo, pAllocator, pView); + } + void __attribute__ ((weak)) + anv_DestroyBufferView(VkDevice device, VkBufferView bufferView, const VkAllocationCallbacks* pAllocator) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkDestroyBufferView(device, bufferView, pAllocator); + } + VkResult __attribute__ ((weak)) + anv_CreateImage(VkDevice device, const VkImageCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkImage* pImage) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkCreateImage(device, pCreateInfo, pAllocator, pImage); + } + void __attribute__ ((weak)) + anv_DestroyImage(VkDevice device, VkImage image, const VkAllocationCallbacks* pAllocator) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkDestroyImage(device, image, pAllocator); + } + void __attribute__ ((weak)) + anv_GetImageSubresourceLayout(VkDevice device, VkImage image, const VkImageSubresource* pSubresource, VkSubresourceLayout* pLayout) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkGetImageSubresourceLayout(device, image, pSubresource, pLayout); + } + VkResult __attribute__ ((weak)) + anv_CreateImageView(VkDevice device, const VkImageViewCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkImageView* pView) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkCreateImageView(device, pCreateInfo, pAllocator, pView); + } + void __attribute__ ((weak)) + anv_DestroyImageView(VkDevice device, VkImageView imageView, const VkAllocationCallbacks* pAllocator) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkDestroyImageView(device, imageView, pAllocator); + } + VkResult __attribute__ ((weak)) + anv_CreateShaderModule(VkDevice device, const VkShaderModuleCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkShaderModule* pShaderModule) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkCreateShaderModule(device, pCreateInfo, pAllocator, pShaderModule); + } + void __attribute__ ((weak)) + anv_DestroyShaderModule(VkDevice device, VkShaderModule shaderModule, const VkAllocationCallbacks* pAllocator) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkDestroyShaderModule(device, shaderModule, pAllocator); + } + VkResult __attribute__ ((weak)) + anv_CreatePipelineCache(VkDevice device, const VkPipelineCacheCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkPipelineCache* pPipelineCache) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkCreatePipelineCache(device, pCreateInfo, pAllocator, pPipelineCache); + } + void __attribute__ ((weak)) + anv_DestroyPipelineCache(VkDevice device, VkPipelineCache pipelineCache, const VkAllocationCallbacks* pAllocator) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkDestroyPipelineCache(device, pipelineCache, pAllocator); + } + VkResult __attribute__ ((weak)) + anv_GetPipelineCacheData(VkDevice device, VkPipelineCache pipelineCache, size_t* pDataSize, void* pData) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkGetPipelineCacheData(device, pipelineCache, pDataSize, pData); + } + VkResult __attribute__ ((weak)) + anv_MergePipelineCaches(VkDevice device, VkPipelineCache dstCache, uint32_t srcCacheCount, const VkPipelineCache* pSrcCaches) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkMergePipelineCaches(device, dstCache, srcCacheCount, pSrcCaches); + } + VkResult __attribute__ ((weak)) + anv_CreateGraphicsPipelines(VkDevice device, VkPipelineCache pipelineCache, uint32_t createInfoCount, const VkGraphicsPipelineCreateInfo* pCreateInfos, const VkAllocationCallbacks* pAllocator, VkPipeline* pPipelines) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkCreateGraphicsPipelines(device, pipelineCache, createInfoCount, pCreateInfos, pAllocator, pPipelines); + } + VkResult __attribute__ ((weak)) + anv_CreateComputePipelines(VkDevice device, VkPipelineCache pipelineCache, uint32_t createInfoCount, const VkComputePipelineCreateInfo* pCreateInfos, const VkAllocationCallbacks* pAllocator, VkPipeline* pPipelines) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkCreateComputePipelines(device, pipelineCache, createInfoCount, pCreateInfos, pAllocator, pPipelines); + } + void __attribute__ ((weak)) + anv_DestroyPipeline(VkDevice device, VkPipeline pipeline, const VkAllocationCallbacks* pAllocator) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkDestroyPipeline(device, pipeline, pAllocator); + } + VkResult __attribute__ ((weak)) + anv_CreatePipelineLayout(VkDevice device, const VkPipelineLayoutCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkPipelineLayout* pPipelineLayout) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkCreatePipelineLayout(device, pCreateInfo, pAllocator, pPipelineLayout); + } + void __attribute__ ((weak)) + anv_DestroyPipelineLayout(VkDevice device, VkPipelineLayout pipelineLayout, const VkAllocationCallbacks* pAllocator) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkDestroyPipelineLayout(device, pipelineLayout, pAllocator); + } + VkResult __attribute__ ((weak)) + anv_CreateSampler(VkDevice device, const VkSamplerCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSampler* pSampler) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkCreateSampler(device, pCreateInfo, pAllocator, pSampler); + } + void __attribute__ ((weak)) + anv_DestroySampler(VkDevice device, VkSampler sampler, const VkAllocationCallbacks* pAllocator) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkDestroySampler(device, sampler, pAllocator); + } + VkResult __attribute__ ((weak)) + anv_CreateDescriptorSetLayout(VkDevice device, const VkDescriptorSetLayoutCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorSetLayout* pSetLayout) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkCreateDescriptorSetLayout(device, pCreateInfo, pAllocator, pSetLayout); + } + void __attribute__ ((weak)) + anv_DestroyDescriptorSetLayout(VkDevice device, VkDescriptorSetLayout descriptorSetLayout, const VkAllocationCallbacks* pAllocator) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkDestroyDescriptorSetLayout(device, descriptorSetLayout, pAllocator); + } + VkResult __attribute__ ((weak)) + anv_CreateDescriptorPool(VkDevice device, const VkDescriptorPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorPool* pDescriptorPool) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkCreateDescriptorPool(device, pCreateInfo, pAllocator, pDescriptorPool); + } + void __attribute__ ((weak)) + anv_DestroyDescriptorPool(VkDevice device, VkDescriptorPool descriptorPool, const VkAllocationCallbacks* pAllocator) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkDestroyDescriptorPool(device, descriptorPool, pAllocator); + } + VkResult __attribute__ ((weak)) + anv_ResetDescriptorPool(VkDevice device, VkDescriptorPool descriptorPool, VkDescriptorPoolResetFlags flags) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkResetDescriptorPool(device, descriptorPool, flags); + } + VkResult __attribute__ ((weak)) + anv_AllocateDescriptorSets(VkDevice device, const VkDescriptorSetAllocateInfo* pAllocateInfo, VkDescriptorSet* pDescriptorSets) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkAllocateDescriptorSets(device, pAllocateInfo, pDescriptorSets); + } + VkResult __attribute__ ((weak)) + anv_FreeDescriptorSets(VkDevice device, VkDescriptorPool descriptorPool, uint32_t descriptorSetCount, const VkDescriptorSet* pDescriptorSets) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkFreeDescriptorSets(device, descriptorPool, descriptorSetCount, pDescriptorSets); + } + void __attribute__ ((weak)) + anv_UpdateDescriptorSets(VkDevice device, uint32_t descriptorWriteCount, const VkWriteDescriptorSet* pDescriptorWrites, uint32_t descriptorCopyCount, const VkCopyDescriptorSet* pDescriptorCopies) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkUpdateDescriptorSets(device, descriptorWriteCount, pDescriptorWrites, descriptorCopyCount, pDescriptorCopies); + } + VkResult __attribute__ ((weak)) + anv_CreateFramebuffer(VkDevice device, const VkFramebufferCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkFramebuffer* pFramebuffer) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkCreateFramebuffer(device, pCreateInfo, pAllocator, pFramebuffer); + } + void __attribute__ ((weak)) + anv_DestroyFramebuffer(VkDevice device, VkFramebuffer framebuffer, const VkAllocationCallbacks* pAllocator) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkDestroyFramebuffer(device, framebuffer, pAllocator); + } + VkResult __attribute__ ((weak)) + anv_CreateRenderPass(VkDevice device, const VkRenderPassCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkRenderPass* pRenderPass) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkCreateRenderPass(device, pCreateInfo, pAllocator, pRenderPass); + } + void __attribute__ ((weak)) + anv_DestroyRenderPass(VkDevice device, VkRenderPass renderPass, const VkAllocationCallbacks* pAllocator) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkDestroyRenderPass(device, renderPass, pAllocator); + } + void __attribute__ ((weak)) + anv_GetRenderAreaGranularity(VkDevice device, VkRenderPass renderPass, VkExtent2D* pGranularity) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkGetRenderAreaGranularity(device, renderPass, pGranularity); + } + VkResult __attribute__ ((weak)) + anv_CreateCommandPool(VkDevice device, const VkCommandPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkCommandPool* pCommandPool) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkCreateCommandPool(device, pCreateInfo, pAllocator, pCommandPool); + } + void __attribute__ ((weak)) + anv_DestroyCommandPool(VkDevice device, VkCommandPool commandPool, const VkAllocationCallbacks* pAllocator) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkDestroyCommandPool(device, commandPool, pAllocator); + } + VkResult __attribute__ ((weak)) + anv_ResetCommandPool(VkDevice device, VkCommandPool commandPool, VkCommandPoolResetFlags flags) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkResetCommandPool(device, commandPool, flags); + } + VkResult __attribute__ ((weak)) + anv_AllocateCommandBuffers(VkDevice device, const VkCommandBufferAllocateInfo* pAllocateInfo, VkCommandBuffer* pCommandBuffers) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkAllocateCommandBuffers(device, pAllocateInfo, pCommandBuffers); + } + void __attribute__ ((weak)) + anv_FreeCommandBuffers(VkDevice device, VkCommandPool commandPool, uint32_t commandBufferCount, const VkCommandBuffer* pCommandBuffers) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkFreeCommandBuffers(device, commandPool, commandBufferCount, pCommandBuffers); + } + VkResult __attribute__ ((weak)) + anv_BeginCommandBuffer(VkCommandBuffer commandBuffer, const VkCommandBufferBeginInfo* pBeginInfo) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkBeginCommandBuffer(commandBuffer, pBeginInfo); + } + VkResult __attribute__ ((weak)) + anv_EndCommandBuffer(VkCommandBuffer commandBuffer) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkEndCommandBuffer(commandBuffer); + } + VkResult __attribute__ ((weak)) + anv_ResetCommandBuffer(VkCommandBuffer commandBuffer, VkCommandBufferResetFlags flags) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkResetCommandBuffer(commandBuffer, flags); + } + void __attribute__ ((weak)) + anv_CmdBindPipeline(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipeline pipeline) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdBindPipeline(commandBuffer, pipelineBindPoint, pipeline); + } + void __attribute__ ((weak)) + anv_CmdSetViewport(VkCommandBuffer commandBuffer, uint32_t firstViewport, uint32_t viewportCount, const VkViewport* pViewports) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdSetViewport(commandBuffer, firstViewport, viewportCount, pViewports); + } + void __attribute__ ((weak)) + anv_CmdSetScissor(VkCommandBuffer commandBuffer, uint32_t firstScissor, uint32_t scissorCount, const VkRect2D* pScissors) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdSetScissor(commandBuffer, firstScissor, scissorCount, pScissors); + } + void __attribute__ ((weak)) + anv_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdSetLineWidth(commandBuffer, lineWidth); + } + void __attribute__ ((weak)) + anv_CmdSetDepthBias(VkCommandBuffer commandBuffer, float depthBiasConstantFactor, float depthBiasClamp, float depthBiasSlopeFactor) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdSetDepthBias(commandBuffer, depthBiasConstantFactor, depthBiasClamp, depthBiasSlopeFactor); + } + void __attribute__ ((weak)) + anv_CmdSetBlendConstants(VkCommandBuffer commandBuffer, const float blendConstants[4]) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdSetBlendConstants(commandBuffer, blendConstants); + } + void __attribute__ ((weak)) + anv_CmdSetDepthBounds(VkCommandBuffer commandBuffer, float minDepthBounds, float maxDepthBounds) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdSetDepthBounds(commandBuffer, minDepthBounds, maxDepthBounds); + } + void __attribute__ ((weak)) + anv_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t compareMask) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdSetStencilCompareMask(commandBuffer, faceMask, compareMask); + } + void __attribute__ ((weak)) + anv_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t writeMask) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdSetStencilWriteMask(commandBuffer, faceMask, writeMask); + } + void __attribute__ ((weak)) + anv_CmdSetStencilReference(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t reference) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdSetStencilReference(commandBuffer, faceMask, reference); + } + void __attribute__ ((weak)) + anv_CmdBindDescriptorSets(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipelineLayout layout, uint32_t firstSet, uint32_t descriptorSetCount, const VkDescriptorSet* pDescriptorSets, uint32_t dynamicOffsetCount, const uint32_t* pDynamicOffsets) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdBindDescriptorSets(commandBuffer, pipelineBindPoint, layout, firstSet, descriptorSetCount, pDescriptorSets, dynamicOffsetCount, pDynamicOffsets); + } + void __attribute__ ((weak)) + anv_CmdBindIndexBuffer(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkIndexType indexType) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdBindIndexBuffer(commandBuffer, buffer, offset, indexType); + } + void __attribute__ ((weak)) + anv_CmdBindVertexBuffers(VkCommandBuffer commandBuffer, uint32_t firstBinding, uint32_t bindingCount, const VkBuffer* pBuffers, const VkDeviceSize* pOffsets) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdBindVertexBuffers(commandBuffer, firstBinding, bindingCount, pBuffers, pOffsets); + } + void __attribute__ ((weak)) + anv_CmdDraw(VkCommandBuffer commandBuffer, uint32_t vertexCount, uint32_t instanceCount, uint32_t firstVertex, uint32_t firstInstance) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdDraw(commandBuffer, vertexCount, instanceCount, firstVertex, firstInstance); + } + void __attribute__ ((weak)) + anv_CmdDrawIndexed(VkCommandBuffer commandBuffer, uint32_t indexCount, uint32_t instanceCount, uint32_t firstIndex, int32_t vertexOffset, uint32_t firstInstance) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdDrawIndexed(commandBuffer, indexCount, instanceCount, firstIndex, vertexOffset, firstInstance); + } + void __attribute__ ((weak)) + anv_CmdDrawIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, uint32_t drawCount, uint32_t stride) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdDrawIndirect(commandBuffer, buffer, offset, drawCount, stride); + } + void __attribute__ ((weak)) + anv_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, uint32_t drawCount, uint32_t stride) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdDrawIndexedIndirect(commandBuffer, buffer, offset, drawCount, stride); + } + void __attribute__ ((weak)) + anv_CmdDispatch(VkCommandBuffer commandBuffer, uint32_t groupCountX, uint32_t groupCountY, uint32_t groupCountZ) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdDispatch(commandBuffer, groupCountX, groupCountY, groupCountZ); + } + void __attribute__ ((weak)) + anv_CmdDispatchIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdDispatchIndirect(commandBuffer, buffer, offset); + } + void __attribute__ ((weak)) + anv_CmdCopyBuffer(VkCommandBuffer commandBuffer, VkBuffer srcBuffer, VkBuffer dstBuffer, uint32_t regionCount, const VkBufferCopy* pRegions) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdCopyBuffer(commandBuffer, srcBuffer, dstBuffer, regionCount, pRegions); + } + void __attribute__ ((weak)) + anv_CmdCopyImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageCopy* pRegions) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdCopyImage(commandBuffer, srcImage, srcImageLayout, dstImage, dstImageLayout, regionCount, pRegions); + } + void __attribute__ ((weak)) + anv_CmdBlitImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageBlit* pRegions, VkFilter filter) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdBlitImage(commandBuffer, srcImage, srcImageLayout, dstImage, dstImageLayout, regionCount, pRegions, filter); + } + void __attribute__ ((weak)) + anv_CmdCopyBufferToImage(VkCommandBuffer commandBuffer, VkBuffer srcBuffer, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkBufferImageCopy* pRegions) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdCopyBufferToImage(commandBuffer, srcBuffer, dstImage, dstImageLayout, regionCount, pRegions); + } + void __attribute__ ((weak)) + anv_CmdCopyImageToBuffer(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkBuffer dstBuffer, uint32_t regionCount, const VkBufferImageCopy* pRegions) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdCopyImageToBuffer(commandBuffer, srcImage, srcImageLayout, dstBuffer, regionCount, pRegions); + } + void __attribute__ ((weak)) + anv_CmdUpdateBuffer(VkCommandBuffer commandBuffer, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize dataSize, const void* pData) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdUpdateBuffer(commandBuffer, dstBuffer, dstOffset, dataSize, pData); + } + void __attribute__ ((weak)) + anv_CmdFillBuffer(VkCommandBuffer commandBuffer, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize size, uint32_t data) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdFillBuffer(commandBuffer, dstBuffer, dstOffset, size, data); + } + void __attribute__ ((weak)) + anv_CmdClearColorImage(VkCommandBuffer commandBuffer, VkImage image, VkImageLayout imageLayout, const VkClearColorValue* pColor, uint32_t rangeCount, const VkImageSubresourceRange* pRanges) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdClearColorImage(commandBuffer, image, imageLayout, pColor, rangeCount, pRanges); + } + void __attribute__ ((weak)) + anv_CmdClearDepthStencilImage(VkCommandBuffer commandBuffer, VkImage image, VkImageLayout imageLayout, const VkClearDepthStencilValue* pDepthStencil, uint32_t rangeCount, const VkImageSubresourceRange* pRanges) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdClearDepthStencilImage(commandBuffer, image, imageLayout, pDepthStencil, rangeCount, pRanges); + } + void __attribute__ ((weak)) + anv_CmdClearAttachments(VkCommandBuffer commandBuffer, uint32_t attachmentCount, const VkClearAttachment* pAttachments, uint32_t rectCount, const VkClearRect* pRects) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdClearAttachments(commandBuffer, attachmentCount, pAttachments, rectCount, pRects); + } + void __attribute__ ((weak)) + anv_CmdResolveImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageResolve* pRegions) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdResolveImage(commandBuffer, srcImage, srcImageLayout, dstImage, dstImageLayout, regionCount, pRegions); + } + void __attribute__ ((weak)) + anv_CmdSetEvent(VkCommandBuffer commandBuffer, VkEvent event, VkPipelineStageFlags stageMask) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdSetEvent(commandBuffer, event, stageMask); + } + void __attribute__ ((weak)) + anv_CmdResetEvent(VkCommandBuffer commandBuffer, VkEvent event, VkPipelineStageFlags stageMask) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdResetEvent(commandBuffer, event, stageMask); + } + void __attribute__ ((weak)) + anv_CmdWaitEvents(VkCommandBuffer commandBuffer, uint32_t eventCount, const VkEvent* pEvents, VkPipelineStageFlags srcStageMask, VkPipelineStageFlags dstStageMask, uint32_t memoryBarrierCount, const VkMemoryBarrier* pMemoryBarriers, uint32_t bufferMemoryBarrierCount, const VkBufferMemoryBarrier* pBufferMemoryBarriers, uint32_t imageMemoryBarrierCount, const VkImageMemoryBarrier* pImageMemoryBarriers) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdWaitEvents(commandBuffer, eventCount, pEvents, srcStageMask, dstStageMask, memoryBarrierCount, pMemoryBarriers, bufferMemoryBarrierCount, pBufferMemoryBarriers, imageMemoryBarrierCount, pImageMemoryBarriers); + } + void __attribute__ ((weak)) + anv_CmdPipelineBarrier(VkCommandBuffer commandBuffer, VkPipelineStageFlags srcStageMask, VkPipelineStageFlags dstStageMask, VkDependencyFlags dependencyFlags, uint32_t memoryBarrierCount, const VkMemoryBarrier* pMemoryBarriers, uint32_t bufferMemoryBarrierCount, const VkBufferMemoryBarrier* pBufferMemoryBarriers, uint32_t imageMemoryBarrierCount, const VkImageMemoryBarrier* pImageMemoryBarriers) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdPipelineBarrier(commandBuffer, srcStageMask, dstStageMask, dependencyFlags, memoryBarrierCount, pMemoryBarriers, bufferMemoryBarrierCount, pBufferMemoryBarriers, imageMemoryBarrierCount, pImageMemoryBarriers); + } + void __attribute__ ((weak)) + anv_CmdBeginQuery(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, VkQueryControlFlags flags) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdBeginQuery(commandBuffer, queryPool, query, flags); + } + void __attribute__ ((weak)) + anv_CmdEndQuery(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdEndQuery(commandBuffer, queryPool, query); + } + void __attribute__ ((weak)) + anv_CmdBeginConditionalRenderingEXT(VkCommandBuffer commandBuffer, const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdBeginConditionalRenderingEXT(commandBuffer, pConditionalRenderingBegin); + } + void __attribute__ ((weak)) + anv_CmdEndConditionalRenderingEXT(VkCommandBuffer commandBuffer) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdEndConditionalRenderingEXT(commandBuffer); + } + void __attribute__ ((weak)) + anv_CmdResetQueryPool(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdResetQueryPool(commandBuffer, queryPool, firstQuery, queryCount); + } + void __attribute__ ((weak)) + anv_CmdWriteTimestamp(VkCommandBuffer commandBuffer, VkPipelineStageFlagBits pipelineStage, VkQueryPool queryPool, uint32_t query) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdWriteTimestamp(commandBuffer, pipelineStage, queryPool, query); + } + void __attribute__ ((weak)) + anv_CmdCopyQueryPoolResults(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize stride, VkQueryResultFlags flags) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdCopyQueryPoolResults(commandBuffer, queryPool, firstQuery, queryCount, dstBuffer, dstOffset, stride, flags); + } + void __attribute__ ((weak)) + anv_CmdPushConstants(VkCommandBuffer commandBuffer, VkPipelineLayout layout, VkShaderStageFlags stageFlags, uint32_t offset, uint32_t size, const void* pValues) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdPushConstants(commandBuffer, layout, stageFlags, offset, size, pValues); + } + void __attribute__ ((weak)) + anv_CmdBeginRenderPass(VkCommandBuffer commandBuffer, const VkRenderPassBeginInfo* pRenderPassBegin, VkSubpassContents contents) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdBeginRenderPass(commandBuffer, pRenderPassBegin, contents); + } + void __attribute__ ((weak)) + anv_CmdNextSubpass(VkCommandBuffer commandBuffer, VkSubpassContents contents) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdNextSubpass(commandBuffer, contents); + } + void __attribute__ ((weak)) + anv_CmdEndRenderPass(VkCommandBuffer commandBuffer) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdEndRenderPass(commandBuffer); + } + void __attribute__ ((weak)) + anv_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCount, const VkCommandBuffer* pCommandBuffers) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdExecuteCommands(commandBuffer, commandBufferCount, pCommandBuffers); + } + VkResult __attribute__ ((weak)) + anv_CreateSwapchainKHR(VkDevice device, const VkSwapchainCreateInfoKHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSwapchainKHR* pSwapchain) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkCreateSwapchainKHR(device, pCreateInfo, pAllocator, pSwapchain); + } + void __attribute__ ((weak)) + anv_DestroySwapchainKHR(VkDevice device, VkSwapchainKHR swapchain, const VkAllocationCallbacks* pAllocator) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkDestroySwapchainKHR(device, swapchain, pAllocator); + } + VkResult __attribute__ ((weak)) + anv_GetSwapchainImagesKHR(VkDevice device, VkSwapchainKHR swapchain, uint32_t* pSwapchainImageCount, VkImage* pSwapchainImages) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkGetSwapchainImagesKHR(device, swapchain, pSwapchainImageCount, pSwapchainImages); + } + VkResult __attribute__ ((weak)) + anv_AcquireNextImageKHR(VkDevice device, VkSwapchainKHR swapchain, uint64_t timeout, VkSemaphore semaphore, VkFence fence, uint32_t* pImageIndex) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkAcquireNextImageKHR(device, swapchain, timeout, semaphore, fence, pImageIndex); + } + VkResult __attribute__ ((weak)) + anv_QueuePresentKHR(VkQueue queue, const VkPresentInfoKHR* pPresentInfo) + { + ANV_FROM_HANDLE(anv_queue, anv_queue, queue); + return anv_queue->device->dispatch.vkQueuePresentKHR(queue, pPresentInfo); + } + void __attribute__ ((weak)) + anv_CmdPushDescriptorSetKHR(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipelineLayout layout, uint32_t set, uint32_t descriptorWriteCount, const VkWriteDescriptorSet* pDescriptorWrites) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdPushDescriptorSetKHR(commandBuffer, pipelineBindPoint, layout, set, descriptorWriteCount, pDescriptorWrites); + } + void __attribute__ ((weak)) + anv_TrimCommandPool(VkDevice device, VkCommandPool commandPool, VkCommandPoolTrimFlags flags) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkTrimCommandPool(device, commandPool, flags); + } + VkResult __attribute__ ((weak)) + anv_GetMemoryFdKHR(VkDevice device, const VkMemoryGetFdInfoKHR* pGetFdInfo, int* pFd) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkGetMemoryFdKHR(device, pGetFdInfo, pFd); + } + VkResult __attribute__ ((weak)) + anv_GetMemoryFdPropertiesKHR(VkDevice device, VkExternalMemoryHandleTypeFlagBits handleType, int fd, VkMemoryFdPropertiesKHR* pMemoryFdProperties) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkGetMemoryFdPropertiesKHR(device, handleType, fd, pMemoryFdProperties); + } + VkResult __attribute__ ((weak)) + anv_GetSemaphoreFdKHR(VkDevice device, const VkSemaphoreGetFdInfoKHR* pGetFdInfo, int* pFd) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkGetSemaphoreFdKHR(device, pGetFdInfo, pFd); + } + VkResult __attribute__ ((weak)) + anv_ImportSemaphoreFdKHR(VkDevice device, const VkImportSemaphoreFdInfoKHR* pImportSemaphoreFdInfo) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkImportSemaphoreFdKHR(device, pImportSemaphoreFdInfo); + } + VkResult __attribute__ ((weak)) + anv_GetFenceFdKHR(VkDevice device, const VkFenceGetFdInfoKHR* pGetFdInfo, int* pFd) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkGetFenceFdKHR(device, pGetFdInfo, pFd); + } + VkResult __attribute__ ((weak)) + anv_ImportFenceFdKHR(VkDevice device, const VkImportFenceFdInfoKHR* pImportFenceFdInfo) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkImportFenceFdKHR(device, pImportFenceFdInfo); + } + VkResult __attribute__ ((weak)) + anv_DisplayPowerControlEXT(VkDevice device, VkDisplayKHR display, const VkDisplayPowerInfoEXT* pDisplayPowerInfo) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkDisplayPowerControlEXT(device, display, pDisplayPowerInfo); + } + VkResult __attribute__ ((weak)) + anv_RegisterDeviceEventEXT(VkDevice device, const VkDeviceEventInfoEXT* pDeviceEventInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkRegisterDeviceEventEXT(device, pDeviceEventInfo, pAllocator, pFence); + } + VkResult __attribute__ ((weak)) + anv_RegisterDisplayEventEXT(VkDevice device, VkDisplayKHR display, const VkDisplayEventInfoEXT* pDisplayEventInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkRegisterDisplayEventEXT(device, display, pDisplayEventInfo, pAllocator, pFence); + } + VkResult __attribute__ ((weak)) + anv_GetSwapchainCounterEXT(VkDevice device, VkSwapchainKHR swapchain, VkSurfaceCounterFlagBitsEXT counter, uint64_t* pCounterValue) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkGetSwapchainCounterEXT(device, swapchain, counter, pCounterValue); + } + void __attribute__ ((weak)) + anv_GetDeviceGroupPeerMemoryFeatures(VkDevice device, uint32_t heapIndex, uint32_t localDeviceIndex, uint32_t remoteDeviceIndex, VkPeerMemoryFeatureFlags* pPeerMemoryFeatures) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkGetDeviceGroupPeerMemoryFeatures(device, heapIndex, localDeviceIndex, remoteDeviceIndex, pPeerMemoryFeatures); + } + VkResult __attribute__ ((weak)) + anv_BindBufferMemory2(VkDevice device, uint32_t bindInfoCount, const VkBindBufferMemoryInfo* pBindInfos) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkBindBufferMemory2(device, bindInfoCount, pBindInfos); + } + VkResult __attribute__ ((weak)) + anv_BindImageMemory2(VkDevice device, uint32_t bindInfoCount, const VkBindImageMemoryInfo* pBindInfos) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkBindImageMemory2(device, bindInfoCount, pBindInfos); + } + void __attribute__ ((weak)) + anv_CmdSetDeviceMask(VkCommandBuffer commandBuffer, uint32_t deviceMask) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdSetDeviceMask(commandBuffer, deviceMask); + } + VkResult __attribute__ ((weak)) + anv_GetDeviceGroupPresentCapabilitiesKHR(VkDevice device, VkDeviceGroupPresentCapabilitiesKHR* pDeviceGroupPresentCapabilities) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkGetDeviceGroupPresentCapabilitiesKHR(device, pDeviceGroupPresentCapabilities); + } + VkResult __attribute__ ((weak)) + anv_GetDeviceGroupSurfacePresentModesKHR(VkDevice device, VkSurfaceKHR surface, VkDeviceGroupPresentModeFlagsKHR* pModes) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkGetDeviceGroupSurfacePresentModesKHR(device, surface, pModes); + } + VkResult __attribute__ ((weak)) + anv_AcquireNextImage2KHR(VkDevice device, const VkAcquireNextImageInfoKHR* pAcquireInfo, uint32_t* pImageIndex) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkAcquireNextImage2KHR(device, pAcquireInfo, pImageIndex); + } + void __attribute__ ((weak)) + anv_CmdDispatchBase(VkCommandBuffer commandBuffer, uint32_t baseGroupX, uint32_t baseGroupY, uint32_t baseGroupZ, uint32_t groupCountX, uint32_t groupCountY, uint32_t groupCountZ) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdDispatchBase(commandBuffer, baseGroupX, baseGroupY, baseGroupZ, groupCountX, groupCountY, groupCountZ); + } + VkResult __attribute__ ((weak)) + anv_CreateDescriptorUpdateTemplate(VkDevice device, const VkDescriptorUpdateTemplateCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorUpdateTemplate* pDescriptorUpdateTemplate) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkCreateDescriptorUpdateTemplate(device, pCreateInfo, pAllocator, pDescriptorUpdateTemplate); + } + void __attribute__ ((weak)) + anv_DestroyDescriptorUpdateTemplate(VkDevice device, VkDescriptorUpdateTemplate descriptorUpdateTemplate, const VkAllocationCallbacks* pAllocator) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkDestroyDescriptorUpdateTemplate(device, descriptorUpdateTemplate, pAllocator); + } + void __attribute__ ((weak)) + anv_UpdateDescriptorSetWithTemplate(VkDevice device, VkDescriptorSet descriptorSet, VkDescriptorUpdateTemplate descriptorUpdateTemplate, const void* pData) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkUpdateDescriptorSetWithTemplate(device, descriptorSet, descriptorUpdateTemplate, pData); + } + void __attribute__ ((weak)) + anv_CmdPushDescriptorSetWithTemplateKHR(VkCommandBuffer commandBuffer, VkDescriptorUpdateTemplate descriptorUpdateTemplate, VkPipelineLayout layout, uint32_t set, const void* pData) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdPushDescriptorSetWithTemplateKHR(commandBuffer, descriptorUpdateTemplate, layout, set, pData); + } + void __attribute__ ((weak)) + anv_GetBufferMemoryRequirements2(VkDevice device, const VkBufferMemoryRequirementsInfo2* pInfo, VkMemoryRequirements2* pMemoryRequirements) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkGetBufferMemoryRequirements2(device, pInfo, pMemoryRequirements); + } + void __attribute__ ((weak)) + anv_GetImageMemoryRequirements2(VkDevice device, const VkImageMemoryRequirementsInfo2* pInfo, VkMemoryRequirements2* pMemoryRequirements) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkGetImageMemoryRequirements2(device, pInfo, pMemoryRequirements); + } + void __attribute__ ((weak)) + anv_GetImageSparseMemoryRequirements2(VkDevice device, const VkImageSparseMemoryRequirementsInfo2* pInfo, uint32_t* pSparseMemoryRequirementCount, VkSparseImageMemoryRequirements2* pSparseMemoryRequirements) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkGetImageSparseMemoryRequirements2(device, pInfo, pSparseMemoryRequirementCount, pSparseMemoryRequirements); + } + VkResult __attribute__ ((weak)) + anv_CreateSamplerYcbcrConversion(VkDevice device, const VkSamplerYcbcrConversionCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSamplerYcbcrConversion* pYcbcrConversion) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkCreateSamplerYcbcrConversion(device, pCreateInfo, pAllocator, pYcbcrConversion); + } + void __attribute__ ((weak)) + anv_DestroySamplerYcbcrConversion(VkDevice device, VkSamplerYcbcrConversion ycbcrConversion, const VkAllocationCallbacks* pAllocator) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkDestroySamplerYcbcrConversion(device, ycbcrConversion, pAllocator); + } + void __attribute__ ((weak)) + anv_GetDeviceQueue2(VkDevice device, const VkDeviceQueueInfo2* pQueueInfo, VkQueue* pQueue) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkGetDeviceQueue2(device, pQueueInfo, pQueue); + } + void __attribute__ ((weak)) + anv_GetDescriptorSetLayoutSupport(VkDevice device, const VkDescriptorSetLayoutCreateInfo* pCreateInfo, VkDescriptorSetLayoutSupport* pSupport) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkGetDescriptorSetLayoutSupport(device, pCreateInfo, pSupport); + } + #ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult __attribute__ ((weak)) + anv_GetSwapchainGrallocUsageANDROID(VkDevice device, VkFormat format, VkImageUsageFlags imageUsage, int* grallocUsage) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkGetSwapchainGrallocUsageANDROID(device, format, imageUsage, grallocUsage); + } +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult __attribute__ ((weak)) + anv_AcquireImageANDROID(VkDevice device, VkImage image, int nativeFenceFd, VkSemaphore semaphore, VkFence fence) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkAcquireImageANDROID(device, image, nativeFenceFd, semaphore, fence); + } +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult __attribute__ ((weak)) + anv_QueueSignalReleaseImageANDROID(VkQueue queue, uint32_t waitSemaphoreCount, const VkSemaphore* pWaitSemaphores, VkImage image, int* pNativeFenceFd) + { + ANV_FROM_HANDLE(anv_queue, anv_queue, queue); + return anv_queue->device->dispatch.vkQueueSignalReleaseImageANDROID(queue, waitSemaphoreCount, pWaitSemaphores, image, pNativeFenceFd); + } +#endif // VK_USE_PLATFORM_ANDROID_KHR + VkResult __attribute__ ((weak)) + anv_GetCalibratedTimestampsEXT(VkDevice device, uint32_t timestampCount, const VkCalibratedTimestampInfoEXT* pTimestampInfos, uint64_t* pTimestamps, uint64_t* pMaxDeviation) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkGetCalibratedTimestampsEXT(device, timestampCount, pTimestampInfos, pTimestamps, pMaxDeviation); + } + VkResult __attribute__ ((weak)) + anv_CreateRenderPass2KHR(VkDevice device, const VkRenderPassCreateInfo2KHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkRenderPass* pRenderPass) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkCreateRenderPass2KHR(device, pCreateInfo, pAllocator, pRenderPass); + } + void __attribute__ ((weak)) + anv_CmdBeginRenderPass2KHR(VkCommandBuffer commandBuffer, const VkRenderPassBeginInfo* pRenderPassBegin, const VkSubpassBeginInfoKHR* pSubpassBeginInfo) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdBeginRenderPass2KHR(commandBuffer, pRenderPassBegin, pSubpassBeginInfo); + } + void __attribute__ ((weak)) + anv_CmdNextSubpass2KHR(VkCommandBuffer commandBuffer, const VkSubpassBeginInfoKHR* pSubpassBeginInfo, const VkSubpassEndInfoKHR* pSubpassEndInfo) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdNextSubpass2KHR(commandBuffer, pSubpassBeginInfo, pSubpassEndInfo); + } + void __attribute__ ((weak)) + anv_CmdEndRenderPass2KHR(VkCommandBuffer commandBuffer, const VkSubpassEndInfoKHR* pSubpassEndInfo) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdEndRenderPass2KHR(commandBuffer, pSubpassEndInfo); + } +#ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult __attribute__ ((weak)) + anv_GetAndroidHardwareBufferPropertiesANDROID(VkDevice device, const struct AHardwareBuffer* buffer, VkAndroidHardwareBufferPropertiesANDROID* pProperties) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkGetAndroidHardwareBufferPropertiesANDROID(device, buffer, pProperties); + } +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult __attribute__ ((weak)) + anv_GetMemoryAndroidHardwareBufferANDROID(VkDevice device, const VkMemoryGetAndroidHardwareBufferInfoANDROID* pInfo, struct AHardwareBuffer** pBuffer) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkGetMemoryAndroidHardwareBufferANDROID(device, pInfo, pBuffer); + } +#endif // VK_USE_PLATFORM_ANDROID_KHR + void __attribute__ ((weak)) + anv_CmdDrawIndirectCountKHR(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkBuffer countBuffer, VkDeviceSize countBufferOffset, uint32_t maxDrawCount, uint32_t stride) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdDrawIndirectCountKHR(commandBuffer, buffer, offset, countBuffer, countBufferOffset, maxDrawCount, stride); + } + void __attribute__ ((weak)) + anv_CmdDrawIndexedIndirectCountKHR(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkBuffer countBuffer, VkDeviceSize countBufferOffset, uint32_t maxDrawCount, uint32_t stride) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdDrawIndexedIndirectCountKHR(commandBuffer, buffer, offset, countBuffer, countBufferOffset, maxDrawCount, stride); + } + void __attribute__ ((weak)) + anv_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer, uint32_t firstBinding, uint32_t bindingCount, const VkBuffer* pBuffers, const VkDeviceSize* pOffsets, const VkDeviceSize* pSizes) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdBindTransformFeedbackBuffersEXT(commandBuffer, firstBinding, bindingCount, pBuffers, pOffsets, pSizes); + } + void __attribute__ ((weak)) + anv_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstCounterBuffer, uint32_t counterBufferCount, const VkBuffer* pCounterBuffers, const VkDeviceSize* pCounterBufferOffsets) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdBeginTransformFeedbackEXT(commandBuffer, firstCounterBuffer, counterBufferCount, pCounterBuffers, pCounterBufferOffsets); + } + void __attribute__ ((weak)) + anv_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstCounterBuffer, uint32_t counterBufferCount, const VkBuffer* pCounterBuffers, const VkDeviceSize* pCounterBufferOffsets) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdEndTransformFeedbackEXT(commandBuffer, firstCounterBuffer, counterBufferCount, pCounterBuffers, pCounterBufferOffsets); + } + void __attribute__ ((weak)) + anv_CmdBeginQueryIndexedEXT(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, VkQueryControlFlags flags, uint32_t index) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdBeginQueryIndexedEXT(commandBuffer, queryPool, query, flags, index); + } + void __attribute__ ((weak)) + anv_CmdEndQueryIndexedEXT(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, uint32_t index) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdEndQueryIndexedEXT(commandBuffer, queryPool, query, index); + } + void __attribute__ ((weak)) + anv_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer, uint32_t instanceCount, uint32_t firstInstance, VkBuffer counterBuffer, VkDeviceSize counterBufferOffset, uint32_t counterOffset, uint32_t vertexStride) + { + ANV_FROM_HANDLE(anv_cmd_buffer, anv_cmd_buffer, commandBuffer); + return anv_cmd_buffer->device->dispatch.vkCmdDrawIndirectByteCountEXT(commandBuffer, instanceCount, firstInstance, counterBuffer, counterBufferOffset, counterOffset, vertexStride); + } + VkResult __attribute__ ((weak)) + anv_CreateDmaBufImageINTEL(VkDevice device, const VkDmaBufImageCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDeviceMemory* pMem, VkImage* pImage) + { + ANV_FROM_HANDLE(anv_device, anv_device, device); + return anv_device->dispatch.vkCreateDmaBufImageINTEL(device, pCreateInfo, pAllocator, pMem, pImage); + } + + const struct anv_device_dispatch_table anv_device_dispatch_table = { + .vkGetDeviceProcAddr = anv_GetDeviceProcAddr, + .vkDestroyDevice = anv_DestroyDevice, + .vkGetDeviceQueue = anv_GetDeviceQueue, + .vkQueueSubmit = anv_QueueSubmit, + .vkQueueWaitIdle = anv_QueueWaitIdle, + .vkDeviceWaitIdle = anv_DeviceWaitIdle, + .vkAllocateMemory = anv_AllocateMemory, + .vkFreeMemory = anv_FreeMemory, + .vkMapMemory = anv_MapMemory, + .vkUnmapMemory = anv_UnmapMemory, + .vkFlushMappedMemoryRanges = anv_FlushMappedMemoryRanges, + .vkInvalidateMappedMemoryRanges = anv_InvalidateMappedMemoryRanges, + .vkGetDeviceMemoryCommitment = anv_GetDeviceMemoryCommitment, + .vkGetBufferMemoryRequirements = anv_GetBufferMemoryRequirements, + .vkBindBufferMemory = anv_BindBufferMemory, + .vkGetImageMemoryRequirements = anv_GetImageMemoryRequirements, + .vkBindImageMemory = anv_BindImageMemory, + .vkGetImageSparseMemoryRequirements = anv_GetImageSparseMemoryRequirements, + .vkQueueBindSparse = anv_QueueBindSparse, + .vkCreateFence = anv_CreateFence, + .vkDestroyFence = anv_DestroyFence, + .vkResetFences = anv_ResetFences, + .vkGetFenceStatus = anv_GetFenceStatus, + .vkWaitForFences = anv_WaitForFences, + .vkCreateSemaphore = anv_CreateSemaphore, + .vkDestroySemaphore = anv_DestroySemaphore, + .vkCreateEvent = anv_CreateEvent, + .vkDestroyEvent = anv_DestroyEvent, + .vkGetEventStatus = anv_GetEventStatus, + .vkSetEvent = anv_SetEvent, + .vkResetEvent = anv_ResetEvent, + .vkCreateQueryPool = anv_CreateQueryPool, + .vkDestroyQueryPool = anv_DestroyQueryPool, + .vkGetQueryPoolResults = anv_GetQueryPoolResults, + .vkCreateBuffer = anv_CreateBuffer, + .vkDestroyBuffer = anv_DestroyBuffer, + .vkCreateBufferView = anv_CreateBufferView, + .vkDestroyBufferView = anv_DestroyBufferView, + .vkCreateImage = anv_CreateImage, + .vkDestroyImage = anv_DestroyImage, + .vkGetImageSubresourceLayout = anv_GetImageSubresourceLayout, + .vkCreateImageView = anv_CreateImageView, + .vkDestroyImageView = anv_DestroyImageView, + .vkCreateShaderModule = anv_CreateShaderModule, + .vkDestroyShaderModule = anv_DestroyShaderModule, + .vkCreatePipelineCache = anv_CreatePipelineCache, + .vkDestroyPipelineCache = anv_DestroyPipelineCache, + .vkGetPipelineCacheData = anv_GetPipelineCacheData, + .vkMergePipelineCaches = anv_MergePipelineCaches, + .vkCreateGraphicsPipelines = anv_CreateGraphicsPipelines, + .vkCreateComputePipelines = anv_CreateComputePipelines, + .vkDestroyPipeline = anv_DestroyPipeline, + .vkCreatePipelineLayout = anv_CreatePipelineLayout, + .vkDestroyPipelineLayout = anv_DestroyPipelineLayout, + .vkCreateSampler = anv_CreateSampler, + .vkDestroySampler = anv_DestroySampler, + .vkCreateDescriptorSetLayout = anv_CreateDescriptorSetLayout, + .vkDestroyDescriptorSetLayout = anv_DestroyDescriptorSetLayout, + .vkCreateDescriptorPool = anv_CreateDescriptorPool, + .vkDestroyDescriptorPool = anv_DestroyDescriptorPool, + .vkResetDescriptorPool = anv_ResetDescriptorPool, + .vkAllocateDescriptorSets = anv_AllocateDescriptorSets, + .vkFreeDescriptorSets = anv_FreeDescriptorSets, + .vkUpdateDescriptorSets = anv_UpdateDescriptorSets, + .vkCreateFramebuffer = anv_CreateFramebuffer, + .vkDestroyFramebuffer = anv_DestroyFramebuffer, + .vkCreateRenderPass = anv_CreateRenderPass, + .vkDestroyRenderPass = anv_DestroyRenderPass, + .vkGetRenderAreaGranularity = anv_GetRenderAreaGranularity, + .vkCreateCommandPool = anv_CreateCommandPool, + .vkDestroyCommandPool = anv_DestroyCommandPool, + .vkResetCommandPool = anv_ResetCommandPool, + .vkAllocateCommandBuffers = anv_AllocateCommandBuffers, + .vkFreeCommandBuffers = anv_FreeCommandBuffers, + .vkBeginCommandBuffer = anv_BeginCommandBuffer, + .vkEndCommandBuffer = anv_EndCommandBuffer, + .vkResetCommandBuffer = anv_ResetCommandBuffer, + .vkCmdBindPipeline = anv_CmdBindPipeline, + .vkCmdSetViewport = anv_CmdSetViewport, + .vkCmdSetScissor = anv_CmdSetScissor, + .vkCmdSetLineWidth = anv_CmdSetLineWidth, + .vkCmdSetDepthBias = anv_CmdSetDepthBias, + .vkCmdSetBlendConstants = anv_CmdSetBlendConstants, + .vkCmdSetDepthBounds = anv_CmdSetDepthBounds, + .vkCmdSetStencilCompareMask = anv_CmdSetStencilCompareMask, + .vkCmdSetStencilWriteMask = anv_CmdSetStencilWriteMask, + .vkCmdSetStencilReference = anv_CmdSetStencilReference, + .vkCmdBindDescriptorSets = anv_CmdBindDescriptorSets, + .vkCmdBindIndexBuffer = anv_CmdBindIndexBuffer, + .vkCmdBindVertexBuffers = anv_CmdBindVertexBuffers, + .vkCmdDraw = anv_CmdDraw, + .vkCmdDrawIndexed = anv_CmdDrawIndexed, + .vkCmdDrawIndirect = anv_CmdDrawIndirect, + .vkCmdDrawIndexedIndirect = anv_CmdDrawIndexedIndirect, + .vkCmdDispatch = anv_CmdDispatch, + .vkCmdDispatchIndirect = anv_CmdDispatchIndirect, + .vkCmdCopyBuffer = anv_CmdCopyBuffer, + .vkCmdCopyImage = anv_CmdCopyImage, + .vkCmdBlitImage = anv_CmdBlitImage, + .vkCmdCopyBufferToImage = anv_CmdCopyBufferToImage, + .vkCmdCopyImageToBuffer = anv_CmdCopyImageToBuffer, + .vkCmdUpdateBuffer = anv_CmdUpdateBuffer, + .vkCmdFillBuffer = anv_CmdFillBuffer, + .vkCmdClearColorImage = anv_CmdClearColorImage, + .vkCmdClearDepthStencilImage = anv_CmdClearDepthStencilImage, + .vkCmdClearAttachments = anv_CmdClearAttachments, + .vkCmdResolveImage = anv_CmdResolveImage, + .vkCmdSetEvent = anv_CmdSetEvent, + .vkCmdResetEvent = anv_CmdResetEvent, + .vkCmdWaitEvents = anv_CmdWaitEvents, + .vkCmdPipelineBarrier = anv_CmdPipelineBarrier, + .vkCmdBeginQuery = anv_CmdBeginQuery, + .vkCmdEndQuery = anv_CmdEndQuery, + .vkCmdBeginConditionalRenderingEXT = anv_CmdBeginConditionalRenderingEXT, + .vkCmdEndConditionalRenderingEXT = anv_CmdEndConditionalRenderingEXT, + .vkCmdResetQueryPool = anv_CmdResetQueryPool, + .vkCmdWriteTimestamp = anv_CmdWriteTimestamp, + .vkCmdCopyQueryPoolResults = anv_CmdCopyQueryPoolResults, + .vkCmdPushConstants = anv_CmdPushConstants, + .vkCmdBeginRenderPass = anv_CmdBeginRenderPass, + .vkCmdNextSubpass = anv_CmdNextSubpass, + .vkCmdEndRenderPass = anv_CmdEndRenderPass, + .vkCmdExecuteCommands = anv_CmdExecuteCommands, + .vkCreateSwapchainKHR = anv_CreateSwapchainKHR, + .vkDestroySwapchainKHR = anv_DestroySwapchainKHR, + .vkGetSwapchainImagesKHR = anv_GetSwapchainImagesKHR, + .vkAcquireNextImageKHR = anv_AcquireNextImageKHR, + .vkQueuePresentKHR = anv_QueuePresentKHR, + .vkCmdPushDescriptorSetKHR = anv_CmdPushDescriptorSetKHR, + .vkTrimCommandPool = anv_TrimCommandPool, + .vkTrimCommandPoolKHR = anv_TrimCommandPool, + .vkGetMemoryFdKHR = anv_GetMemoryFdKHR, + .vkGetMemoryFdPropertiesKHR = anv_GetMemoryFdPropertiesKHR, + .vkGetSemaphoreFdKHR = anv_GetSemaphoreFdKHR, + .vkImportSemaphoreFdKHR = anv_ImportSemaphoreFdKHR, + .vkGetFenceFdKHR = anv_GetFenceFdKHR, + .vkImportFenceFdKHR = anv_ImportFenceFdKHR, + .vkDisplayPowerControlEXT = anv_DisplayPowerControlEXT, + .vkRegisterDeviceEventEXT = anv_RegisterDeviceEventEXT, + .vkRegisterDisplayEventEXT = anv_RegisterDisplayEventEXT, + .vkGetSwapchainCounterEXT = anv_GetSwapchainCounterEXT, + .vkGetDeviceGroupPeerMemoryFeatures = anv_GetDeviceGroupPeerMemoryFeatures, + .vkGetDeviceGroupPeerMemoryFeaturesKHR = anv_GetDeviceGroupPeerMemoryFeatures, + .vkBindBufferMemory2 = anv_BindBufferMemory2, + .vkBindBufferMemory2KHR = anv_BindBufferMemory2, + .vkBindImageMemory2 = anv_BindImageMemory2, + .vkBindImageMemory2KHR = anv_BindImageMemory2, + .vkCmdSetDeviceMask = anv_CmdSetDeviceMask, + .vkCmdSetDeviceMaskKHR = anv_CmdSetDeviceMask, + .vkGetDeviceGroupPresentCapabilitiesKHR = anv_GetDeviceGroupPresentCapabilitiesKHR, + .vkGetDeviceGroupSurfacePresentModesKHR = anv_GetDeviceGroupSurfacePresentModesKHR, + .vkAcquireNextImage2KHR = anv_AcquireNextImage2KHR, + .vkCmdDispatchBase = anv_CmdDispatchBase, + .vkCmdDispatchBaseKHR = anv_CmdDispatchBase, + .vkCreateDescriptorUpdateTemplate = anv_CreateDescriptorUpdateTemplate, + .vkCreateDescriptorUpdateTemplateKHR = anv_CreateDescriptorUpdateTemplate, + .vkDestroyDescriptorUpdateTemplate = anv_DestroyDescriptorUpdateTemplate, + .vkDestroyDescriptorUpdateTemplateKHR = anv_DestroyDescriptorUpdateTemplate, + .vkUpdateDescriptorSetWithTemplate = anv_UpdateDescriptorSetWithTemplate, + .vkUpdateDescriptorSetWithTemplateKHR = anv_UpdateDescriptorSetWithTemplate, + .vkCmdPushDescriptorSetWithTemplateKHR = anv_CmdPushDescriptorSetWithTemplateKHR, + .vkGetBufferMemoryRequirements2 = anv_GetBufferMemoryRequirements2, + .vkGetBufferMemoryRequirements2KHR = anv_GetBufferMemoryRequirements2, + .vkGetImageMemoryRequirements2 = anv_GetImageMemoryRequirements2, + .vkGetImageMemoryRequirements2KHR = anv_GetImageMemoryRequirements2, + .vkGetImageSparseMemoryRequirements2 = anv_GetImageSparseMemoryRequirements2, + .vkGetImageSparseMemoryRequirements2KHR = anv_GetImageSparseMemoryRequirements2, + .vkCreateSamplerYcbcrConversion = anv_CreateSamplerYcbcrConversion, + .vkCreateSamplerYcbcrConversionKHR = anv_CreateSamplerYcbcrConversion, + .vkDestroySamplerYcbcrConversion = anv_DestroySamplerYcbcrConversion, + .vkDestroySamplerYcbcrConversionKHR = anv_DestroySamplerYcbcrConversion, + .vkGetDeviceQueue2 = anv_GetDeviceQueue2, + .vkGetDescriptorSetLayoutSupport = anv_GetDescriptorSetLayoutSupport, + .vkGetDescriptorSetLayoutSupportKHR = anv_GetDescriptorSetLayoutSupport, +#ifdef VK_USE_PLATFORM_ANDROID_KHR + .vkGetSwapchainGrallocUsageANDROID = anv_GetSwapchainGrallocUsageANDROID, +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + .vkAcquireImageANDROID = anv_AcquireImageANDROID, +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + .vkQueueSignalReleaseImageANDROID = anv_QueueSignalReleaseImageANDROID, +#endif // VK_USE_PLATFORM_ANDROID_KHR + .vkGetCalibratedTimestampsEXT = anv_GetCalibratedTimestampsEXT, + .vkCreateRenderPass2KHR = anv_CreateRenderPass2KHR, + .vkCmdBeginRenderPass2KHR = anv_CmdBeginRenderPass2KHR, + .vkCmdNextSubpass2KHR = anv_CmdNextSubpass2KHR, + .vkCmdEndRenderPass2KHR = anv_CmdEndRenderPass2KHR, +#ifdef VK_USE_PLATFORM_ANDROID_KHR + .vkGetAndroidHardwareBufferPropertiesANDROID = anv_GetAndroidHardwareBufferPropertiesANDROID, +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + .vkGetMemoryAndroidHardwareBufferANDROID = anv_GetMemoryAndroidHardwareBufferANDROID, +#endif // VK_USE_PLATFORM_ANDROID_KHR + .vkCmdDrawIndirectCountKHR = anv_CmdDrawIndirectCountKHR, + .vkCmdDrawIndexedIndirectCountKHR = anv_CmdDrawIndexedIndirectCountKHR, + .vkCmdBindTransformFeedbackBuffersEXT = anv_CmdBindTransformFeedbackBuffersEXT, + .vkCmdBeginTransformFeedbackEXT = anv_CmdBeginTransformFeedbackEXT, + .vkCmdEndTransformFeedbackEXT = anv_CmdEndTransformFeedbackEXT, + .vkCmdBeginQueryIndexedEXT = anv_CmdBeginQueryIndexedEXT, + .vkCmdEndQueryIndexedEXT = anv_CmdEndQueryIndexedEXT, + .vkCmdDrawIndirectByteCountEXT = anv_CmdDrawIndirectByteCountEXT, + .vkCreateDmaBufImageINTEL = anv_CreateDmaBufImageINTEL, + }; + PFN_vkVoidFunction gen7_GetDeviceProcAddr(VkDevice device, const char* pName) __attribute__ ((weak)); + void gen7_DestroyDevice(VkDevice device, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + void gen7_GetDeviceQueue(VkDevice device, uint32_t queueFamilyIndex, uint32_t queueIndex, VkQueue* pQueue) __attribute__ ((weak)); + VkResult gen7_QueueSubmit(VkQueue queue, uint32_t submitCount, const VkSubmitInfo* pSubmits, VkFence fence) __attribute__ ((weak)); + VkResult gen7_QueueWaitIdle(VkQueue queue) __attribute__ ((weak)); + VkResult gen7_DeviceWaitIdle(VkDevice device) __attribute__ ((weak)); + VkResult gen7_AllocateMemory(VkDevice device, const VkMemoryAllocateInfo* pAllocateInfo, const VkAllocationCallbacks* pAllocator, VkDeviceMemory* pMemory) __attribute__ ((weak)); + void gen7_FreeMemory(VkDevice device, VkDeviceMemory memory, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen7_MapMemory(VkDevice device, VkDeviceMemory memory, VkDeviceSize offset, VkDeviceSize size, VkMemoryMapFlags flags, void** ppData) __attribute__ ((weak)); + void gen7_UnmapMemory(VkDevice device, VkDeviceMemory memory) __attribute__ ((weak)); + VkResult gen7_FlushMappedMemoryRanges(VkDevice device, uint32_t memoryRangeCount, const VkMappedMemoryRange* pMemoryRanges) __attribute__ ((weak)); + VkResult gen7_InvalidateMappedMemoryRanges(VkDevice device, uint32_t memoryRangeCount, const VkMappedMemoryRange* pMemoryRanges) __attribute__ ((weak)); + void gen7_GetDeviceMemoryCommitment(VkDevice device, VkDeviceMemory memory, VkDeviceSize* pCommittedMemoryInBytes) __attribute__ ((weak)); + void gen7_GetBufferMemoryRequirements(VkDevice device, VkBuffer buffer, VkMemoryRequirements* pMemoryRequirements) __attribute__ ((weak)); + VkResult gen7_BindBufferMemory(VkDevice device, VkBuffer buffer, VkDeviceMemory memory, VkDeviceSize memoryOffset) __attribute__ ((weak)); + void gen7_GetImageMemoryRequirements(VkDevice device, VkImage image, VkMemoryRequirements* pMemoryRequirements) __attribute__ ((weak)); + VkResult gen7_BindImageMemory(VkDevice device, VkImage image, VkDeviceMemory memory, VkDeviceSize memoryOffset) __attribute__ ((weak)); + void gen7_GetImageSparseMemoryRequirements(VkDevice device, VkImage image, uint32_t* pSparseMemoryRequirementCount, VkSparseImageMemoryRequirements* pSparseMemoryRequirements) __attribute__ ((weak)); + VkResult gen7_QueueBindSparse(VkQueue queue, uint32_t bindInfoCount, const VkBindSparseInfo* pBindInfo, VkFence fence) __attribute__ ((weak)); + VkResult gen7_CreateFence(VkDevice device, const VkFenceCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence) __attribute__ ((weak)); + void gen7_DestroyFence(VkDevice device, VkFence fence, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen7_ResetFences(VkDevice device, uint32_t fenceCount, const VkFence* pFences) __attribute__ ((weak)); + VkResult gen7_GetFenceStatus(VkDevice device, VkFence fence) __attribute__ ((weak)); + VkResult gen7_WaitForFences(VkDevice device, uint32_t fenceCount, const VkFence* pFences, VkBool32 waitAll, uint64_t timeout) __attribute__ ((weak)); + VkResult gen7_CreateSemaphore(VkDevice device, const VkSemaphoreCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSemaphore* pSemaphore) __attribute__ ((weak)); + void gen7_DestroySemaphore(VkDevice device, VkSemaphore semaphore, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen7_CreateEvent(VkDevice device, const VkEventCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkEvent* pEvent) __attribute__ ((weak)); + void gen7_DestroyEvent(VkDevice device, VkEvent event, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen7_GetEventStatus(VkDevice device, VkEvent event) __attribute__ ((weak)); + VkResult gen7_SetEvent(VkDevice device, VkEvent event) __attribute__ ((weak)); + VkResult gen7_ResetEvent(VkDevice device, VkEvent event) __attribute__ ((weak)); + VkResult gen7_CreateQueryPool(VkDevice device, const VkQueryPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkQueryPool* pQueryPool) __attribute__ ((weak)); + void gen7_DestroyQueryPool(VkDevice device, VkQueryPool queryPool, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen7_GetQueryPoolResults(VkDevice device, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount, size_t dataSize, void* pData, VkDeviceSize stride, VkQueryResultFlags flags) __attribute__ ((weak)); + VkResult gen7_CreateBuffer(VkDevice device, const VkBufferCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkBuffer* pBuffer) __attribute__ ((weak)); + void gen7_DestroyBuffer(VkDevice device, VkBuffer buffer, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen7_CreateBufferView(VkDevice device, const VkBufferViewCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkBufferView* pView) __attribute__ ((weak)); + void gen7_DestroyBufferView(VkDevice device, VkBufferView bufferView, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen7_CreateImage(VkDevice device, const VkImageCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkImage* pImage) __attribute__ ((weak)); + void gen7_DestroyImage(VkDevice device, VkImage image, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + void gen7_GetImageSubresourceLayout(VkDevice device, VkImage image, const VkImageSubresource* pSubresource, VkSubresourceLayout* pLayout) __attribute__ ((weak)); + VkResult gen7_CreateImageView(VkDevice device, const VkImageViewCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkImageView* pView) __attribute__ ((weak)); + void gen7_DestroyImageView(VkDevice device, VkImageView imageView, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen7_CreateShaderModule(VkDevice device, const VkShaderModuleCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkShaderModule* pShaderModule) __attribute__ ((weak)); + void gen7_DestroyShaderModule(VkDevice device, VkShaderModule shaderModule, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen7_CreatePipelineCache(VkDevice device, const VkPipelineCacheCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkPipelineCache* pPipelineCache) __attribute__ ((weak)); + void gen7_DestroyPipelineCache(VkDevice device, VkPipelineCache pipelineCache, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen7_GetPipelineCacheData(VkDevice device, VkPipelineCache pipelineCache, size_t* pDataSize, void* pData) __attribute__ ((weak)); + VkResult gen7_MergePipelineCaches(VkDevice device, VkPipelineCache dstCache, uint32_t srcCacheCount, const VkPipelineCache* pSrcCaches) __attribute__ ((weak)); + VkResult gen7_CreateGraphicsPipelines(VkDevice device, VkPipelineCache pipelineCache, uint32_t createInfoCount, const VkGraphicsPipelineCreateInfo* pCreateInfos, const VkAllocationCallbacks* pAllocator, VkPipeline* pPipelines) __attribute__ ((weak)); + VkResult gen7_CreateComputePipelines(VkDevice device, VkPipelineCache pipelineCache, uint32_t createInfoCount, const VkComputePipelineCreateInfo* pCreateInfos, const VkAllocationCallbacks* pAllocator, VkPipeline* pPipelines) __attribute__ ((weak)); + void gen7_DestroyPipeline(VkDevice device, VkPipeline pipeline, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen7_CreatePipelineLayout(VkDevice device, const VkPipelineLayoutCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkPipelineLayout* pPipelineLayout) __attribute__ ((weak)); + void gen7_DestroyPipelineLayout(VkDevice device, VkPipelineLayout pipelineLayout, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen7_CreateSampler(VkDevice device, const VkSamplerCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSampler* pSampler) __attribute__ ((weak)); + void gen7_DestroySampler(VkDevice device, VkSampler sampler, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen7_CreateDescriptorSetLayout(VkDevice device, const VkDescriptorSetLayoutCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorSetLayout* pSetLayout) __attribute__ ((weak)); + void gen7_DestroyDescriptorSetLayout(VkDevice device, VkDescriptorSetLayout descriptorSetLayout, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen7_CreateDescriptorPool(VkDevice device, const VkDescriptorPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorPool* pDescriptorPool) __attribute__ ((weak)); + void gen7_DestroyDescriptorPool(VkDevice device, VkDescriptorPool descriptorPool, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen7_ResetDescriptorPool(VkDevice device, VkDescriptorPool descriptorPool, VkDescriptorPoolResetFlags flags) __attribute__ ((weak)); + VkResult gen7_AllocateDescriptorSets(VkDevice device, const VkDescriptorSetAllocateInfo* pAllocateInfo, VkDescriptorSet* pDescriptorSets) __attribute__ ((weak)); + VkResult gen7_FreeDescriptorSets(VkDevice device, VkDescriptorPool descriptorPool, uint32_t descriptorSetCount, const VkDescriptorSet* pDescriptorSets) __attribute__ ((weak)); + void gen7_UpdateDescriptorSets(VkDevice device, uint32_t descriptorWriteCount, const VkWriteDescriptorSet* pDescriptorWrites, uint32_t descriptorCopyCount, const VkCopyDescriptorSet* pDescriptorCopies) __attribute__ ((weak)); + VkResult gen7_CreateFramebuffer(VkDevice device, const VkFramebufferCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkFramebuffer* pFramebuffer) __attribute__ ((weak)); + void gen7_DestroyFramebuffer(VkDevice device, VkFramebuffer framebuffer, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen7_CreateRenderPass(VkDevice device, const VkRenderPassCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkRenderPass* pRenderPass) __attribute__ ((weak)); + void gen7_DestroyRenderPass(VkDevice device, VkRenderPass renderPass, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + void gen7_GetRenderAreaGranularity(VkDevice device, VkRenderPass renderPass, VkExtent2D* pGranularity) __attribute__ ((weak)); + VkResult gen7_CreateCommandPool(VkDevice device, const VkCommandPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkCommandPool* pCommandPool) __attribute__ ((weak)); + void gen7_DestroyCommandPool(VkDevice device, VkCommandPool commandPool, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen7_ResetCommandPool(VkDevice device, VkCommandPool commandPool, VkCommandPoolResetFlags flags) __attribute__ ((weak)); + VkResult gen7_AllocateCommandBuffers(VkDevice device, const VkCommandBufferAllocateInfo* pAllocateInfo, VkCommandBuffer* pCommandBuffers) __attribute__ ((weak)); + void gen7_FreeCommandBuffers(VkDevice device, VkCommandPool commandPool, uint32_t commandBufferCount, const VkCommandBuffer* pCommandBuffers) __attribute__ ((weak)); + VkResult gen7_BeginCommandBuffer(VkCommandBuffer commandBuffer, const VkCommandBufferBeginInfo* pBeginInfo) __attribute__ ((weak)); + VkResult gen7_EndCommandBuffer(VkCommandBuffer commandBuffer) __attribute__ ((weak)); + VkResult gen7_ResetCommandBuffer(VkCommandBuffer commandBuffer, VkCommandBufferResetFlags flags) __attribute__ ((weak)); + void gen7_CmdBindPipeline(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipeline pipeline) __attribute__ ((weak)); + void gen7_CmdSetViewport(VkCommandBuffer commandBuffer, uint32_t firstViewport, uint32_t viewportCount, const VkViewport* pViewports) __attribute__ ((weak)); + void gen7_CmdSetScissor(VkCommandBuffer commandBuffer, uint32_t firstScissor, uint32_t scissorCount, const VkRect2D* pScissors) __attribute__ ((weak)); + void gen7_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth) __attribute__ ((weak)); + void gen7_CmdSetDepthBias(VkCommandBuffer commandBuffer, float depthBiasConstantFactor, float depthBiasClamp, float depthBiasSlopeFactor) __attribute__ ((weak)); + void gen7_CmdSetBlendConstants(VkCommandBuffer commandBuffer, const float blendConstants[4]) __attribute__ ((weak)); + void gen7_CmdSetDepthBounds(VkCommandBuffer commandBuffer, float minDepthBounds, float maxDepthBounds) __attribute__ ((weak)); + void gen7_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t compareMask) __attribute__ ((weak)); + void gen7_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t writeMask) __attribute__ ((weak)); + void gen7_CmdSetStencilReference(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t reference) __attribute__ ((weak)); + void gen7_CmdBindDescriptorSets(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipelineLayout layout, uint32_t firstSet, uint32_t descriptorSetCount, const VkDescriptorSet* pDescriptorSets, uint32_t dynamicOffsetCount, const uint32_t* pDynamicOffsets) __attribute__ ((weak)); + void gen7_CmdBindIndexBuffer(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkIndexType indexType) __attribute__ ((weak)); + void gen7_CmdBindVertexBuffers(VkCommandBuffer commandBuffer, uint32_t firstBinding, uint32_t bindingCount, const VkBuffer* pBuffers, const VkDeviceSize* pOffsets) __attribute__ ((weak)); + void gen7_CmdDraw(VkCommandBuffer commandBuffer, uint32_t vertexCount, uint32_t instanceCount, uint32_t firstVertex, uint32_t firstInstance) __attribute__ ((weak)); + void gen7_CmdDrawIndexed(VkCommandBuffer commandBuffer, uint32_t indexCount, uint32_t instanceCount, uint32_t firstIndex, int32_t vertexOffset, uint32_t firstInstance) __attribute__ ((weak)); + void gen7_CmdDrawIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, uint32_t drawCount, uint32_t stride) __attribute__ ((weak)); + void gen7_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, uint32_t drawCount, uint32_t stride) __attribute__ ((weak)); + void gen7_CmdDispatch(VkCommandBuffer commandBuffer, uint32_t groupCountX, uint32_t groupCountY, uint32_t groupCountZ) __attribute__ ((weak)); + void gen7_CmdDispatchIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset) __attribute__ ((weak)); + void gen7_CmdCopyBuffer(VkCommandBuffer commandBuffer, VkBuffer srcBuffer, VkBuffer dstBuffer, uint32_t regionCount, const VkBufferCopy* pRegions) __attribute__ ((weak)); + void gen7_CmdCopyImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageCopy* pRegions) __attribute__ ((weak)); + void gen7_CmdBlitImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageBlit* pRegions, VkFilter filter) __attribute__ ((weak)); + void gen7_CmdCopyBufferToImage(VkCommandBuffer commandBuffer, VkBuffer srcBuffer, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkBufferImageCopy* pRegions) __attribute__ ((weak)); + void gen7_CmdCopyImageToBuffer(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkBuffer dstBuffer, uint32_t regionCount, const VkBufferImageCopy* pRegions) __attribute__ ((weak)); + void gen7_CmdUpdateBuffer(VkCommandBuffer commandBuffer, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize dataSize, const void* pData) __attribute__ ((weak)); + void gen7_CmdFillBuffer(VkCommandBuffer commandBuffer, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize size, uint32_t data) __attribute__ ((weak)); + void gen7_CmdClearColorImage(VkCommandBuffer commandBuffer, VkImage image, VkImageLayout imageLayout, const VkClearColorValue* pColor, uint32_t rangeCount, const VkImageSubresourceRange* pRanges) __attribute__ ((weak)); + void gen7_CmdClearDepthStencilImage(VkCommandBuffer commandBuffer, VkImage image, VkImageLayout imageLayout, const VkClearDepthStencilValue* pDepthStencil, uint32_t rangeCount, const VkImageSubresourceRange* pRanges) __attribute__ ((weak)); + void gen7_CmdClearAttachments(VkCommandBuffer commandBuffer, uint32_t attachmentCount, const VkClearAttachment* pAttachments, uint32_t rectCount, const VkClearRect* pRects) __attribute__ ((weak)); + void gen7_CmdResolveImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageResolve* pRegions) __attribute__ ((weak)); + void gen7_CmdSetEvent(VkCommandBuffer commandBuffer, VkEvent event, VkPipelineStageFlags stageMask) __attribute__ ((weak)); + void gen7_CmdResetEvent(VkCommandBuffer commandBuffer, VkEvent event, VkPipelineStageFlags stageMask) __attribute__ ((weak)); + void gen7_CmdWaitEvents(VkCommandBuffer commandBuffer, uint32_t eventCount, const VkEvent* pEvents, VkPipelineStageFlags srcStageMask, VkPipelineStageFlags dstStageMask, uint32_t memoryBarrierCount, const VkMemoryBarrier* pMemoryBarriers, uint32_t bufferMemoryBarrierCount, const VkBufferMemoryBarrier* pBufferMemoryBarriers, uint32_t imageMemoryBarrierCount, const VkImageMemoryBarrier* pImageMemoryBarriers) __attribute__ ((weak)); + void gen7_CmdPipelineBarrier(VkCommandBuffer commandBuffer, VkPipelineStageFlags srcStageMask, VkPipelineStageFlags dstStageMask, VkDependencyFlags dependencyFlags, uint32_t memoryBarrierCount, const VkMemoryBarrier* pMemoryBarriers, uint32_t bufferMemoryBarrierCount, const VkBufferMemoryBarrier* pBufferMemoryBarriers, uint32_t imageMemoryBarrierCount, const VkImageMemoryBarrier* pImageMemoryBarriers) __attribute__ ((weak)); + void gen7_CmdBeginQuery(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, VkQueryControlFlags flags) __attribute__ ((weak)); + void gen7_CmdEndQuery(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query) __attribute__ ((weak)); + void gen7_CmdBeginConditionalRenderingEXT(VkCommandBuffer commandBuffer, const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin) __attribute__ ((weak)); + void gen7_CmdEndConditionalRenderingEXT(VkCommandBuffer commandBuffer) __attribute__ ((weak)); + void gen7_CmdResetQueryPool(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount) __attribute__ ((weak)); + void gen7_CmdWriteTimestamp(VkCommandBuffer commandBuffer, VkPipelineStageFlagBits pipelineStage, VkQueryPool queryPool, uint32_t query) __attribute__ ((weak)); + void gen7_CmdCopyQueryPoolResults(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize stride, VkQueryResultFlags flags) __attribute__ ((weak)); + void gen7_CmdPushConstants(VkCommandBuffer commandBuffer, VkPipelineLayout layout, VkShaderStageFlags stageFlags, uint32_t offset, uint32_t size, const void* pValues) __attribute__ ((weak)); + void gen7_CmdBeginRenderPass(VkCommandBuffer commandBuffer, const VkRenderPassBeginInfo* pRenderPassBegin, VkSubpassContents contents) __attribute__ ((weak)); + void gen7_CmdNextSubpass(VkCommandBuffer commandBuffer, VkSubpassContents contents) __attribute__ ((weak)); + void gen7_CmdEndRenderPass(VkCommandBuffer commandBuffer) __attribute__ ((weak)); + void gen7_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCount, const VkCommandBuffer* pCommandBuffers) __attribute__ ((weak)); + VkResult gen7_CreateSwapchainKHR(VkDevice device, const VkSwapchainCreateInfoKHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSwapchainKHR* pSwapchain) __attribute__ ((weak)); + void gen7_DestroySwapchainKHR(VkDevice device, VkSwapchainKHR swapchain, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen7_GetSwapchainImagesKHR(VkDevice device, VkSwapchainKHR swapchain, uint32_t* pSwapchainImageCount, VkImage* pSwapchainImages) __attribute__ ((weak)); + VkResult gen7_AcquireNextImageKHR(VkDevice device, VkSwapchainKHR swapchain, uint64_t timeout, VkSemaphore semaphore, VkFence fence, uint32_t* pImageIndex) __attribute__ ((weak)); + VkResult gen7_QueuePresentKHR(VkQueue queue, const VkPresentInfoKHR* pPresentInfo) __attribute__ ((weak)); + void gen7_CmdPushDescriptorSetKHR(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipelineLayout layout, uint32_t set, uint32_t descriptorWriteCount, const VkWriteDescriptorSet* pDescriptorWrites) __attribute__ ((weak)); + void gen7_TrimCommandPool(VkDevice device, VkCommandPool commandPool, VkCommandPoolTrimFlags flags) __attribute__ ((weak)); + VkResult gen7_GetMemoryFdKHR(VkDevice device, const VkMemoryGetFdInfoKHR* pGetFdInfo, int* pFd) __attribute__ ((weak)); + VkResult gen7_GetMemoryFdPropertiesKHR(VkDevice device, VkExternalMemoryHandleTypeFlagBits handleType, int fd, VkMemoryFdPropertiesKHR* pMemoryFdProperties) __attribute__ ((weak)); + VkResult gen7_GetSemaphoreFdKHR(VkDevice device, const VkSemaphoreGetFdInfoKHR* pGetFdInfo, int* pFd) __attribute__ ((weak)); + VkResult gen7_ImportSemaphoreFdKHR(VkDevice device, const VkImportSemaphoreFdInfoKHR* pImportSemaphoreFdInfo) __attribute__ ((weak)); + VkResult gen7_GetFenceFdKHR(VkDevice device, const VkFenceGetFdInfoKHR* pGetFdInfo, int* pFd) __attribute__ ((weak)); + VkResult gen7_ImportFenceFdKHR(VkDevice device, const VkImportFenceFdInfoKHR* pImportFenceFdInfo) __attribute__ ((weak)); + VkResult gen7_DisplayPowerControlEXT(VkDevice device, VkDisplayKHR display, const VkDisplayPowerInfoEXT* pDisplayPowerInfo) __attribute__ ((weak)); + VkResult gen7_RegisterDeviceEventEXT(VkDevice device, const VkDeviceEventInfoEXT* pDeviceEventInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence) __attribute__ ((weak)); + VkResult gen7_RegisterDisplayEventEXT(VkDevice device, VkDisplayKHR display, const VkDisplayEventInfoEXT* pDisplayEventInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence) __attribute__ ((weak)); + VkResult gen7_GetSwapchainCounterEXT(VkDevice device, VkSwapchainKHR swapchain, VkSurfaceCounterFlagBitsEXT counter, uint64_t* pCounterValue) __attribute__ ((weak)); + void gen7_GetDeviceGroupPeerMemoryFeatures(VkDevice device, uint32_t heapIndex, uint32_t localDeviceIndex, uint32_t remoteDeviceIndex, VkPeerMemoryFeatureFlags* pPeerMemoryFeatures) __attribute__ ((weak)); + VkResult gen7_BindBufferMemory2(VkDevice device, uint32_t bindInfoCount, const VkBindBufferMemoryInfo* pBindInfos) __attribute__ ((weak)); + VkResult gen7_BindImageMemory2(VkDevice device, uint32_t bindInfoCount, const VkBindImageMemoryInfo* pBindInfos) __attribute__ ((weak)); + void gen7_CmdSetDeviceMask(VkCommandBuffer commandBuffer, uint32_t deviceMask) __attribute__ ((weak)); + VkResult gen7_GetDeviceGroupPresentCapabilitiesKHR(VkDevice device, VkDeviceGroupPresentCapabilitiesKHR* pDeviceGroupPresentCapabilities) __attribute__ ((weak)); + VkResult gen7_GetDeviceGroupSurfacePresentModesKHR(VkDevice device, VkSurfaceKHR surface, VkDeviceGroupPresentModeFlagsKHR* pModes) __attribute__ ((weak)); + VkResult gen7_AcquireNextImage2KHR(VkDevice device, const VkAcquireNextImageInfoKHR* pAcquireInfo, uint32_t* pImageIndex) __attribute__ ((weak)); + void gen7_CmdDispatchBase(VkCommandBuffer commandBuffer, uint32_t baseGroupX, uint32_t baseGroupY, uint32_t baseGroupZ, uint32_t groupCountX, uint32_t groupCountY, uint32_t groupCountZ) __attribute__ ((weak)); + VkResult gen7_CreateDescriptorUpdateTemplate(VkDevice device, const VkDescriptorUpdateTemplateCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorUpdateTemplate* pDescriptorUpdateTemplate) __attribute__ ((weak)); + void gen7_DestroyDescriptorUpdateTemplate(VkDevice device, VkDescriptorUpdateTemplate descriptorUpdateTemplate, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + void gen7_UpdateDescriptorSetWithTemplate(VkDevice device, VkDescriptorSet descriptorSet, VkDescriptorUpdateTemplate descriptorUpdateTemplate, const void* pData) __attribute__ ((weak)); + void gen7_CmdPushDescriptorSetWithTemplateKHR(VkCommandBuffer commandBuffer, VkDescriptorUpdateTemplate descriptorUpdateTemplate, VkPipelineLayout layout, uint32_t set, const void* pData) __attribute__ ((weak)); + void gen7_GetBufferMemoryRequirements2(VkDevice device, const VkBufferMemoryRequirementsInfo2* pInfo, VkMemoryRequirements2* pMemoryRequirements) __attribute__ ((weak)); + void gen7_GetImageMemoryRequirements2(VkDevice device, const VkImageMemoryRequirementsInfo2* pInfo, VkMemoryRequirements2* pMemoryRequirements) __attribute__ ((weak)); + void gen7_GetImageSparseMemoryRequirements2(VkDevice device, const VkImageSparseMemoryRequirementsInfo2* pInfo, uint32_t* pSparseMemoryRequirementCount, VkSparseImageMemoryRequirements2* pSparseMemoryRequirements) __attribute__ ((weak)); + VkResult gen7_CreateSamplerYcbcrConversion(VkDevice device, const VkSamplerYcbcrConversionCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSamplerYcbcrConversion* pYcbcrConversion) __attribute__ ((weak)); + void gen7_DestroySamplerYcbcrConversion(VkDevice device, VkSamplerYcbcrConversion ycbcrConversion, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + void gen7_GetDeviceQueue2(VkDevice device, const VkDeviceQueueInfo2* pQueueInfo, VkQueue* pQueue) __attribute__ ((weak)); + void gen7_GetDescriptorSetLayoutSupport(VkDevice device, const VkDescriptorSetLayoutCreateInfo* pCreateInfo, VkDescriptorSetLayoutSupport* pSupport) __attribute__ ((weak)); + #ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult gen7_GetSwapchainGrallocUsageANDROID(VkDevice device, VkFormat format, VkImageUsageFlags imageUsage, int* grallocUsage) __attribute__ ((weak)); +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult gen7_AcquireImageANDROID(VkDevice device, VkImage image, int nativeFenceFd, VkSemaphore semaphore, VkFence fence) __attribute__ ((weak)); +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult gen7_QueueSignalReleaseImageANDROID(VkQueue queue, uint32_t waitSemaphoreCount, const VkSemaphore* pWaitSemaphores, VkImage image, int* pNativeFenceFd) __attribute__ ((weak)); +#endif // VK_USE_PLATFORM_ANDROID_KHR + VkResult gen7_GetCalibratedTimestampsEXT(VkDevice device, uint32_t timestampCount, const VkCalibratedTimestampInfoEXT* pTimestampInfos, uint64_t* pTimestamps, uint64_t* pMaxDeviation) __attribute__ ((weak)); + VkResult gen7_CreateRenderPass2KHR(VkDevice device, const VkRenderPassCreateInfo2KHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkRenderPass* pRenderPass) __attribute__ ((weak)); + void gen7_CmdBeginRenderPass2KHR(VkCommandBuffer commandBuffer, const VkRenderPassBeginInfo* pRenderPassBegin, const VkSubpassBeginInfoKHR* pSubpassBeginInfo) __attribute__ ((weak)); + void gen7_CmdNextSubpass2KHR(VkCommandBuffer commandBuffer, const VkSubpassBeginInfoKHR* pSubpassBeginInfo, const VkSubpassEndInfoKHR* pSubpassEndInfo) __attribute__ ((weak)); + void gen7_CmdEndRenderPass2KHR(VkCommandBuffer commandBuffer, const VkSubpassEndInfoKHR* pSubpassEndInfo) __attribute__ ((weak)); +#ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult gen7_GetAndroidHardwareBufferPropertiesANDROID(VkDevice device, const struct AHardwareBuffer* buffer, VkAndroidHardwareBufferPropertiesANDROID* pProperties) __attribute__ ((weak)); +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult gen7_GetMemoryAndroidHardwareBufferANDROID(VkDevice device, const VkMemoryGetAndroidHardwareBufferInfoANDROID* pInfo, struct AHardwareBuffer** pBuffer) __attribute__ ((weak)); +#endif // VK_USE_PLATFORM_ANDROID_KHR + void gen7_CmdDrawIndirectCountKHR(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkBuffer countBuffer, VkDeviceSize countBufferOffset, uint32_t maxDrawCount, uint32_t stride) __attribute__ ((weak)); + void gen7_CmdDrawIndexedIndirectCountKHR(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkBuffer countBuffer, VkDeviceSize countBufferOffset, uint32_t maxDrawCount, uint32_t stride) __attribute__ ((weak)); + void gen7_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer, uint32_t firstBinding, uint32_t bindingCount, const VkBuffer* pBuffers, const VkDeviceSize* pOffsets, const VkDeviceSize* pSizes) __attribute__ ((weak)); + void gen7_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstCounterBuffer, uint32_t counterBufferCount, const VkBuffer* pCounterBuffers, const VkDeviceSize* pCounterBufferOffsets) __attribute__ ((weak)); + void gen7_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstCounterBuffer, uint32_t counterBufferCount, const VkBuffer* pCounterBuffers, const VkDeviceSize* pCounterBufferOffsets) __attribute__ ((weak)); + void gen7_CmdBeginQueryIndexedEXT(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, VkQueryControlFlags flags, uint32_t index) __attribute__ ((weak)); + void gen7_CmdEndQueryIndexedEXT(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, uint32_t index) __attribute__ ((weak)); + void gen7_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer, uint32_t instanceCount, uint32_t firstInstance, VkBuffer counterBuffer, VkDeviceSize counterBufferOffset, uint32_t counterOffset, uint32_t vertexStride) __attribute__ ((weak)); + VkResult gen7_CreateDmaBufImageINTEL(VkDevice device, const VkDmaBufImageCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDeviceMemory* pMem, VkImage* pImage) __attribute__ ((weak)); + + const struct anv_device_dispatch_table gen7_device_dispatch_table = { + .vkGetDeviceProcAddr = gen7_GetDeviceProcAddr, + .vkDestroyDevice = gen7_DestroyDevice, + .vkGetDeviceQueue = gen7_GetDeviceQueue, + .vkQueueSubmit = gen7_QueueSubmit, + .vkQueueWaitIdle = gen7_QueueWaitIdle, + .vkDeviceWaitIdle = gen7_DeviceWaitIdle, + .vkAllocateMemory = gen7_AllocateMemory, + .vkFreeMemory = gen7_FreeMemory, + .vkMapMemory = gen7_MapMemory, + .vkUnmapMemory = gen7_UnmapMemory, + .vkFlushMappedMemoryRanges = gen7_FlushMappedMemoryRanges, + .vkInvalidateMappedMemoryRanges = gen7_InvalidateMappedMemoryRanges, + .vkGetDeviceMemoryCommitment = gen7_GetDeviceMemoryCommitment, + .vkGetBufferMemoryRequirements = gen7_GetBufferMemoryRequirements, + .vkBindBufferMemory = gen7_BindBufferMemory, + .vkGetImageMemoryRequirements = gen7_GetImageMemoryRequirements, + .vkBindImageMemory = gen7_BindImageMemory, + .vkGetImageSparseMemoryRequirements = gen7_GetImageSparseMemoryRequirements, + .vkQueueBindSparse = gen7_QueueBindSparse, + .vkCreateFence = gen7_CreateFence, + .vkDestroyFence = gen7_DestroyFence, + .vkResetFences = gen7_ResetFences, + .vkGetFenceStatus = gen7_GetFenceStatus, + .vkWaitForFences = gen7_WaitForFences, + .vkCreateSemaphore = gen7_CreateSemaphore, + .vkDestroySemaphore = gen7_DestroySemaphore, + .vkCreateEvent = gen7_CreateEvent, + .vkDestroyEvent = gen7_DestroyEvent, + .vkGetEventStatus = gen7_GetEventStatus, + .vkSetEvent = gen7_SetEvent, + .vkResetEvent = gen7_ResetEvent, + .vkCreateQueryPool = gen7_CreateQueryPool, + .vkDestroyQueryPool = gen7_DestroyQueryPool, + .vkGetQueryPoolResults = gen7_GetQueryPoolResults, + .vkCreateBuffer = gen7_CreateBuffer, + .vkDestroyBuffer = gen7_DestroyBuffer, + .vkCreateBufferView = gen7_CreateBufferView, + .vkDestroyBufferView = gen7_DestroyBufferView, + .vkCreateImage = gen7_CreateImage, + .vkDestroyImage = gen7_DestroyImage, + .vkGetImageSubresourceLayout = gen7_GetImageSubresourceLayout, + .vkCreateImageView = gen7_CreateImageView, + .vkDestroyImageView = gen7_DestroyImageView, + .vkCreateShaderModule = gen7_CreateShaderModule, + .vkDestroyShaderModule = gen7_DestroyShaderModule, + .vkCreatePipelineCache = gen7_CreatePipelineCache, + .vkDestroyPipelineCache = gen7_DestroyPipelineCache, + .vkGetPipelineCacheData = gen7_GetPipelineCacheData, + .vkMergePipelineCaches = gen7_MergePipelineCaches, + .vkCreateGraphicsPipelines = gen7_CreateGraphicsPipelines, + .vkCreateComputePipelines = gen7_CreateComputePipelines, + .vkDestroyPipeline = gen7_DestroyPipeline, + .vkCreatePipelineLayout = gen7_CreatePipelineLayout, + .vkDestroyPipelineLayout = gen7_DestroyPipelineLayout, + .vkCreateSampler = gen7_CreateSampler, + .vkDestroySampler = gen7_DestroySampler, + .vkCreateDescriptorSetLayout = gen7_CreateDescriptorSetLayout, + .vkDestroyDescriptorSetLayout = gen7_DestroyDescriptorSetLayout, + .vkCreateDescriptorPool = gen7_CreateDescriptorPool, + .vkDestroyDescriptorPool = gen7_DestroyDescriptorPool, + .vkResetDescriptorPool = gen7_ResetDescriptorPool, + .vkAllocateDescriptorSets = gen7_AllocateDescriptorSets, + .vkFreeDescriptorSets = gen7_FreeDescriptorSets, + .vkUpdateDescriptorSets = gen7_UpdateDescriptorSets, + .vkCreateFramebuffer = gen7_CreateFramebuffer, + .vkDestroyFramebuffer = gen7_DestroyFramebuffer, + .vkCreateRenderPass = gen7_CreateRenderPass, + .vkDestroyRenderPass = gen7_DestroyRenderPass, + .vkGetRenderAreaGranularity = gen7_GetRenderAreaGranularity, + .vkCreateCommandPool = gen7_CreateCommandPool, + .vkDestroyCommandPool = gen7_DestroyCommandPool, + .vkResetCommandPool = gen7_ResetCommandPool, + .vkAllocateCommandBuffers = gen7_AllocateCommandBuffers, + .vkFreeCommandBuffers = gen7_FreeCommandBuffers, + .vkBeginCommandBuffer = gen7_BeginCommandBuffer, + .vkEndCommandBuffer = gen7_EndCommandBuffer, + .vkResetCommandBuffer = gen7_ResetCommandBuffer, + .vkCmdBindPipeline = gen7_CmdBindPipeline, + .vkCmdSetViewport = gen7_CmdSetViewport, + .vkCmdSetScissor = gen7_CmdSetScissor, + .vkCmdSetLineWidth = gen7_CmdSetLineWidth, + .vkCmdSetDepthBias = gen7_CmdSetDepthBias, + .vkCmdSetBlendConstants = gen7_CmdSetBlendConstants, + .vkCmdSetDepthBounds = gen7_CmdSetDepthBounds, + .vkCmdSetStencilCompareMask = gen7_CmdSetStencilCompareMask, + .vkCmdSetStencilWriteMask = gen7_CmdSetStencilWriteMask, + .vkCmdSetStencilReference = gen7_CmdSetStencilReference, + .vkCmdBindDescriptorSets = gen7_CmdBindDescriptorSets, + .vkCmdBindIndexBuffer = gen7_CmdBindIndexBuffer, + .vkCmdBindVertexBuffers = gen7_CmdBindVertexBuffers, + .vkCmdDraw = gen7_CmdDraw, + .vkCmdDrawIndexed = gen7_CmdDrawIndexed, + .vkCmdDrawIndirect = gen7_CmdDrawIndirect, + .vkCmdDrawIndexedIndirect = gen7_CmdDrawIndexedIndirect, + .vkCmdDispatch = gen7_CmdDispatch, + .vkCmdDispatchIndirect = gen7_CmdDispatchIndirect, + .vkCmdCopyBuffer = gen7_CmdCopyBuffer, + .vkCmdCopyImage = gen7_CmdCopyImage, + .vkCmdBlitImage = gen7_CmdBlitImage, + .vkCmdCopyBufferToImage = gen7_CmdCopyBufferToImage, + .vkCmdCopyImageToBuffer = gen7_CmdCopyImageToBuffer, + .vkCmdUpdateBuffer = gen7_CmdUpdateBuffer, + .vkCmdFillBuffer = gen7_CmdFillBuffer, + .vkCmdClearColorImage = gen7_CmdClearColorImage, + .vkCmdClearDepthStencilImage = gen7_CmdClearDepthStencilImage, + .vkCmdClearAttachments = gen7_CmdClearAttachments, + .vkCmdResolveImage = gen7_CmdResolveImage, + .vkCmdSetEvent = gen7_CmdSetEvent, + .vkCmdResetEvent = gen7_CmdResetEvent, + .vkCmdWaitEvents = gen7_CmdWaitEvents, + .vkCmdPipelineBarrier = gen7_CmdPipelineBarrier, + .vkCmdBeginQuery = gen7_CmdBeginQuery, + .vkCmdEndQuery = gen7_CmdEndQuery, + .vkCmdBeginConditionalRenderingEXT = gen7_CmdBeginConditionalRenderingEXT, + .vkCmdEndConditionalRenderingEXT = gen7_CmdEndConditionalRenderingEXT, + .vkCmdResetQueryPool = gen7_CmdResetQueryPool, + .vkCmdWriteTimestamp = gen7_CmdWriteTimestamp, + .vkCmdCopyQueryPoolResults = gen7_CmdCopyQueryPoolResults, + .vkCmdPushConstants = gen7_CmdPushConstants, + .vkCmdBeginRenderPass = gen7_CmdBeginRenderPass, + .vkCmdNextSubpass = gen7_CmdNextSubpass, + .vkCmdEndRenderPass = gen7_CmdEndRenderPass, + .vkCmdExecuteCommands = gen7_CmdExecuteCommands, + .vkCreateSwapchainKHR = gen7_CreateSwapchainKHR, + .vkDestroySwapchainKHR = gen7_DestroySwapchainKHR, + .vkGetSwapchainImagesKHR = gen7_GetSwapchainImagesKHR, + .vkAcquireNextImageKHR = gen7_AcquireNextImageKHR, + .vkQueuePresentKHR = gen7_QueuePresentKHR, + .vkCmdPushDescriptorSetKHR = gen7_CmdPushDescriptorSetKHR, + .vkTrimCommandPool = gen7_TrimCommandPool, + .vkTrimCommandPoolKHR = gen7_TrimCommandPool, + .vkGetMemoryFdKHR = gen7_GetMemoryFdKHR, + .vkGetMemoryFdPropertiesKHR = gen7_GetMemoryFdPropertiesKHR, + .vkGetSemaphoreFdKHR = gen7_GetSemaphoreFdKHR, + .vkImportSemaphoreFdKHR = gen7_ImportSemaphoreFdKHR, + .vkGetFenceFdKHR = gen7_GetFenceFdKHR, + .vkImportFenceFdKHR = gen7_ImportFenceFdKHR, + .vkDisplayPowerControlEXT = gen7_DisplayPowerControlEXT, + .vkRegisterDeviceEventEXT = gen7_RegisterDeviceEventEXT, + .vkRegisterDisplayEventEXT = gen7_RegisterDisplayEventEXT, + .vkGetSwapchainCounterEXT = gen7_GetSwapchainCounterEXT, + .vkGetDeviceGroupPeerMemoryFeatures = gen7_GetDeviceGroupPeerMemoryFeatures, + .vkGetDeviceGroupPeerMemoryFeaturesKHR = gen7_GetDeviceGroupPeerMemoryFeatures, + .vkBindBufferMemory2 = gen7_BindBufferMemory2, + .vkBindBufferMemory2KHR = gen7_BindBufferMemory2, + .vkBindImageMemory2 = gen7_BindImageMemory2, + .vkBindImageMemory2KHR = gen7_BindImageMemory2, + .vkCmdSetDeviceMask = gen7_CmdSetDeviceMask, + .vkCmdSetDeviceMaskKHR = gen7_CmdSetDeviceMask, + .vkGetDeviceGroupPresentCapabilitiesKHR = gen7_GetDeviceGroupPresentCapabilitiesKHR, + .vkGetDeviceGroupSurfacePresentModesKHR = gen7_GetDeviceGroupSurfacePresentModesKHR, + .vkAcquireNextImage2KHR = gen7_AcquireNextImage2KHR, + .vkCmdDispatchBase = gen7_CmdDispatchBase, + .vkCmdDispatchBaseKHR = gen7_CmdDispatchBase, + .vkCreateDescriptorUpdateTemplate = gen7_CreateDescriptorUpdateTemplate, + .vkCreateDescriptorUpdateTemplateKHR = gen7_CreateDescriptorUpdateTemplate, + .vkDestroyDescriptorUpdateTemplate = gen7_DestroyDescriptorUpdateTemplate, + .vkDestroyDescriptorUpdateTemplateKHR = gen7_DestroyDescriptorUpdateTemplate, + .vkUpdateDescriptorSetWithTemplate = gen7_UpdateDescriptorSetWithTemplate, + .vkUpdateDescriptorSetWithTemplateKHR = gen7_UpdateDescriptorSetWithTemplate, + .vkCmdPushDescriptorSetWithTemplateKHR = gen7_CmdPushDescriptorSetWithTemplateKHR, + .vkGetBufferMemoryRequirements2 = gen7_GetBufferMemoryRequirements2, + .vkGetBufferMemoryRequirements2KHR = gen7_GetBufferMemoryRequirements2, + .vkGetImageMemoryRequirements2 = gen7_GetImageMemoryRequirements2, + .vkGetImageMemoryRequirements2KHR = gen7_GetImageMemoryRequirements2, + .vkGetImageSparseMemoryRequirements2 = gen7_GetImageSparseMemoryRequirements2, + .vkGetImageSparseMemoryRequirements2KHR = gen7_GetImageSparseMemoryRequirements2, + .vkCreateSamplerYcbcrConversion = gen7_CreateSamplerYcbcrConversion, + .vkCreateSamplerYcbcrConversionKHR = gen7_CreateSamplerYcbcrConversion, + .vkDestroySamplerYcbcrConversion = gen7_DestroySamplerYcbcrConversion, + .vkDestroySamplerYcbcrConversionKHR = gen7_DestroySamplerYcbcrConversion, + .vkGetDeviceQueue2 = gen7_GetDeviceQueue2, + .vkGetDescriptorSetLayoutSupport = gen7_GetDescriptorSetLayoutSupport, + .vkGetDescriptorSetLayoutSupportKHR = gen7_GetDescriptorSetLayoutSupport, +#ifdef VK_USE_PLATFORM_ANDROID_KHR + .vkGetSwapchainGrallocUsageANDROID = gen7_GetSwapchainGrallocUsageANDROID, +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + .vkAcquireImageANDROID = gen7_AcquireImageANDROID, +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + .vkQueueSignalReleaseImageANDROID = gen7_QueueSignalReleaseImageANDROID, +#endif // VK_USE_PLATFORM_ANDROID_KHR + .vkGetCalibratedTimestampsEXT = gen7_GetCalibratedTimestampsEXT, + .vkCreateRenderPass2KHR = gen7_CreateRenderPass2KHR, + .vkCmdBeginRenderPass2KHR = gen7_CmdBeginRenderPass2KHR, + .vkCmdNextSubpass2KHR = gen7_CmdNextSubpass2KHR, + .vkCmdEndRenderPass2KHR = gen7_CmdEndRenderPass2KHR, +#ifdef VK_USE_PLATFORM_ANDROID_KHR + .vkGetAndroidHardwareBufferPropertiesANDROID = gen7_GetAndroidHardwareBufferPropertiesANDROID, +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + .vkGetMemoryAndroidHardwareBufferANDROID = gen7_GetMemoryAndroidHardwareBufferANDROID, +#endif // VK_USE_PLATFORM_ANDROID_KHR + .vkCmdDrawIndirectCountKHR = gen7_CmdDrawIndirectCountKHR, + .vkCmdDrawIndexedIndirectCountKHR = gen7_CmdDrawIndexedIndirectCountKHR, + .vkCmdBindTransformFeedbackBuffersEXT = gen7_CmdBindTransformFeedbackBuffersEXT, + .vkCmdBeginTransformFeedbackEXT = gen7_CmdBeginTransformFeedbackEXT, + .vkCmdEndTransformFeedbackEXT = gen7_CmdEndTransformFeedbackEXT, + .vkCmdBeginQueryIndexedEXT = gen7_CmdBeginQueryIndexedEXT, + .vkCmdEndQueryIndexedEXT = gen7_CmdEndQueryIndexedEXT, + .vkCmdDrawIndirectByteCountEXT = gen7_CmdDrawIndirectByteCountEXT, + .vkCreateDmaBufImageINTEL = gen7_CreateDmaBufImageINTEL, + }; + PFN_vkVoidFunction gen75_GetDeviceProcAddr(VkDevice device, const char* pName) __attribute__ ((weak)); + void gen75_DestroyDevice(VkDevice device, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + void gen75_GetDeviceQueue(VkDevice device, uint32_t queueFamilyIndex, uint32_t queueIndex, VkQueue* pQueue) __attribute__ ((weak)); + VkResult gen75_QueueSubmit(VkQueue queue, uint32_t submitCount, const VkSubmitInfo* pSubmits, VkFence fence) __attribute__ ((weak)); + VkResult gen75_QueueWaitIdle(VkQueue queue) __attribute__ ((weak)); + VkResult gen75_DeviceWaitIdle(VkDevice device) __attribute__ ((weak)); + VkResult gen75_AllocateMemory(VkDevice device, const VkMemoryAllocateInfo* pAllocateInfo, const VkAllocationCallbacks* pAllocator, VkDeviceMemory* pMemory) __attribute__ ((weak)); + void gen75_FreeMemory(VkDevice device, VkDeviceMemory memory, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen75_MapMemory(VkDevice device, VkDeviceMemory memory, VkDeviceSize offset, VkDeviceSize size, VkMemoryMapFlags flags, void** ppData) __attribute__ ((weak)); + void gen75_UnmapMemory(VkDevice device, VkDeviceMemory memory) __attribute__ ((weak)); + VkResult gen75_FlushMappedMemoryRanges(VkDevice device, uint32_t memoryRangeCount, const VkMappedMemoryRange* pMemoryRanges) __attribute__ ((weak)); + VkResult gen75_InvalidateMappedMemoryRanges(VkDevice device, uint32_t memoryRangeCount, const VkMappedMemoryRange* pMemoryRanges) __attribute__ ((weak)); + void gen75_GetDeviceMemoryCommitment(VkDevice device, VkDeviceMemory memory, VkDeviceSize* pCommittedMemoryInBytes) __attribute__ ((weak)); + void gen75_GetBufferMemoryRequirements(VkDevice device, VkBuffer buffer, VkMemoryRequirements* pMemoryRequirements) __attribute__ ((weak)); + VkResult gen75_BindBufferMemory(VkDevice device, VkBuffer buffer, VkDeviceMemory memory, VkDeviceSize memoryOffset) __attribute__ ((weak)); + void gen75_GetImageMemoryRequirements(VkDevice device, VkImage image, VkMemoryRequirements* pMemoryRequirements) __attribute__ ((weak)); + VkResult gen75_BindImageMemory(VkDevice device, VkImage image, VkDeviceMemory memory, VkDeviceSize memoryOffset) __attribute__ ((weak)); + void gen75_GetImageSparseMemoryRequirements(VkDevice device, VkImage image, uint32_t* pSparseMemoryRequirementCount, VkSparseImageMemoryRequirements* pSparseMemoryRequirements) __attribute__ ((weak)); + VkResult gen75_QueueBindSparse(VkQueue queue, uint32_t bindInfoCount, const VkBindSparseInfo* pBindInfo, VkFence fence) __attribute__ ((weak)); + VkResult gen75_CreateFence(VkDevice device, const VkFenceCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence) __attribute__ ((weak)); + void gen75_DestroyFence(VkDevice device, VkFence fence, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen75_ResetFences(VkDevice device, uint32_t fenceCount, const VkFence* pFences) __attribute__ ((weak)); + VkResult gen75_GetFenceStatus(VkDevice device, VkFence fence) __attribute__ ((weak)); + VkResult gen75_WaitForFences(VkDevice device, uint32_t fenceCount, const VkFence* pFences, VkBool32 waitAll, uint64_t timeout) __attribute__ ((weak)); + VkResult gen75_CreateSemaphore(VkDevice device, const VkSemaphoreCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSemaphore* pSemaphore) __attribute__ ((weak)); + void gen75_DestroySemaphore(VkDevice device, VkSemaphore semaphore, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen75_CreateEvent(VkDevice device, const VkEventCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkEvent* pEvent) __attribute__ ((weak)); + void gen75_DestroyEvent(VkDevice device, VkEvent event, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen75_GetEventStatus(VkDevice device, VkEvent event) __attribute__ ((weak)); + VkResult gen75_SetEvent(VkDevice device, VkEvent event) __attribute__ ((weak)); + VkResult gen75_ResetEvent(VkDevice device, VkEvent event) __attribute__ ((weak)); + VkResult gen75_CreateQueryPool(VkDevice device, const VkQueryPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkQueryPool* pQueryPool) __attribute__ ((weak)); + void gen75_DestroyQueryPool(VkDevice device, VkQueryPool queryPool, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen75_GetQueryPoolResults(VkDevice device, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount, size_t dataSize, void* pData, VkDeviceSize stride, VkQueryResultFlags flags) __attribute__ ((weak)); + VkResult gen75_CreateBuffer(VkDevice device, const VkBufferCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkBuffer* pBuffer) __attribute__ ((weak)); + void gen75_DestroyBuffer(VkDevice device, VkBuffer buffer, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen75_CreateBufferView(VkDevice device, const VkBufferViewCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkBufferView* pView) __attribute__ ((weak)); + void gen75_DestroyBufferView(VkDevice device, VkBufferView bufferView, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen75_CreateImage(VkDevice device, const VkImageCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkImage* pImage) __attribute__ ((weak)); + void gen75_DestroyImage(VkDevice device, VkImage image, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + void gen75_GetImageSubresourceLayout(VkDevice device, VkImage image, const VkImageSubresource* pSubresource, VkSubresourceLayout* pLayout) __attribute__ ((weak)); + VkResult gen75_CreateImageView(VkDevice device, const VkImageViewCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkImageView* pView) __attribute__ ((weak)); + void gen75_DestroyImageView(VkDevice device, VkImageView imageView, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen75_CreateShaderModule(VkDevice device, const VkShaderModuleCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkShaderModule* pShaderModule) __attribute__ ((weak)); + void gen75_DestroyShaderModule(VkDevice device, VkShaderModule shaderModule, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen75_CreatePipelineCache(VkDevice device, const VkPipelineCacheCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkPipelineCache* pPipelineCache) __attribute__ ((weak)); + void gen75_DestroyPipelineCache(VkDevice device, VkPipelineCache pipelineCache, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen75_GetPipelineCacheData(VkDevice device, VkPipelineCache pipelineCache, size_t* pDataSize, void* pData) __attribute__ ((weak)); + VkResult gen75_MergePipelineCaches(VkDevice device, VkPipelineCache dstCache, uint32_t srcCacheCount, const VkPipelineCache* pSrcCaches) __attribute__ ((weak)); + VkResult gen75_CreateGraphicsPipelines(VkDevice device, VkPipelineCache pipelineCache, uint32_t createInfoCount, const VkGraphicsPipelineCreateInfo* pCreateInfos, const VkAllocationCallbacks* pAllocator, VkPipeline* pPipelines) __attribute__ ((weak)); + VkResult gen75_CreateComputePipelines(VkDevice device, VkPipelineCache pipelineCache, uint32_t createInfoCount, const VkComputePipelineCreateInfo* pCreateInfos, const VkAllocationCallbacks* pAllocator, VkPipeline* pPipelines) __attribute__ ((weak)); + void gen75_DestroyPipeline(VkDevice device, VkPipeline pipeline, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen75_CreatePipelineLayout(VkDevice device, const VkPipelineLayoutCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkPipelineLayout* pPipelineLayout) __attribute__ ((weak)); + void gen75_DestroyPipelineLayout(VkDevice device, VkPipelineLayout pipelineLayout, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen75_CreateSampler(VkDevice device, const VkSamplerCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSampler* pSampler) __attribute__ ((weak)); + void gen75_DestroySampler(VkDevice device, VkSampler sampler, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen75_CreateDescriptorSetLayout(VkDevice device, const VkDescriptorSetLayoutCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorSetLayout* pSetLayout) __attribute__ ((weak)); + void gen75_DestroyDescriptorSetLayout(VkDevice device, VkDescriptorSetLayout descriptorSetLayout, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen75_CreateDescriptorPool(VkDevice device, const VkDescriptorPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorPool* pDescriptorPool) __attribute__ ((weak)); + void gen75_DestroyDescriptorPool(VkDevice device, VkDescriptorPool descriptorPool, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen75_ResetDescriptorPool(VkDevice device, VkDescriptorPool descriptorPool, VkDescriptorPoolResetFlags flags) __attribute__ ((weak)); + VkResult gen75_AllocateDescriptorSets(VkDevice device, const VkDescriptorSetAllocateInfo* pAllocateInfo, VkDescriptorSet* pDescriptorSets) __attribute__ ((weak)); + VkResult gen75_FreeDescriptorSets(VkDevice device, VkDescriptorPool descriptorPool, uint32_t descriptorSetCount, const VkDescriptorSet* pDescriptorSets) __attribute__ ((weak)); + void gen75_UpdateDescriptorSets(VkDevice device, uint32_t descriptorWriteCount, const VkWriteDescriptorSet* pDescriptorWrites, uint32_t descriptorCopyCount, const VkCopyDescriptorSet* pDescriptorCopies) __attribute__ ((weak)); + VkResult gen75_CreateFramebuffer(VkDevice device, const VkFramebufferCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkFramebuffer* pFramebuffer) __attribute__ ((weak)); + void gen75_DestroyFramebuffer(VkDevice device, VkFramebuffer framebuffer, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen75_CreateRenderPass(VkDevice device, const VkRenderPassCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkRenderPass* pRenderPass) __attribute__ ((weak)); + void gen75_DestroyRenderPass(VkDevice device, VkRenderPass renderPass, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + void gen75_GetRenderAreaGranularity(VkDevice device, VkRenderPass renderPass, VkExtent2D* pGranularity) __attribute__ ((weak)); + VkResult gen75_CreateCommandPool(VkDevice device, const VkCommandPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkCommandPool* pCommandPool) __attribute__ ((weak)); + void gen75_DestroyCommandPool(VkDevice device, VkCommandPool commandPool, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen75_ResetCommandPool(VkDevice device, VkCommandPool commandPool, VkCommandPoolResetFlags flags) __attribute__ ((weak)); + VkResult gen75_AllocateCommandBuffers(VkDevice device, const VkCommandBufferAllocateInfo* pAllocateInfo, VkCommandBuffer* pCommandBuffers) __attribute__ ((weak)); + void gen75_FreeCommandBuffers(VkDevice device, VkCommandPool commandPool, uint32_t commandBufferCount, const VkCommandBuffer* pCommandBuffers) __attribute__ ((weak)); + VkResult gen75_BeginCommandBuffer(VkCommandBuffer commandBuffer, const VkCommandBufferBeginInfo* pBeginInfo) __attribute__ ((weak)); + VkResult gen75_EndCommandBuffer(VkCommandBuffer commandBuffer) __attribute__ ((weak)); + VkResult gen75_ResetCommandBuffer(VkCommandBuffer commandBuffer, VkCommandBufferResetFlags flags) __attribute__ ((weak)); + void gen75_CmdBindPipeline(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipeline pipeline) __attribute__ ((weak)); + void gen75_CmdSetViewport(VkCommandBuffer commandBuffer, uint32_t firstViewport, uint32_t viewportCount, const VkViewport* pViewports) __attribute__ ((weak)); + void gen75_CmdSetScissor(VkCommandBuffer commandBuffer, uint32_t firstScissor, uint32_t scissorCount, const VkRect2D* pScissors) __attribute__ ((weak)); + void gen75_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth) __attribute__ ((weak)); + void gen75_CmdSetDepthBias(VkCommandBuffer commandBuffer, float depthBiasConstantFactor, float depthBiasClamp, float depthBiasSlopeFactor) __attribute__ ((weak)); + void gen75_CmdSetBlendConstants(VkCommandBuffer commandBuffer, const float blendConstants[4]) __attribute__ ((weak)); + void gen75_CmdSetDepthBounds(VkCommandBuffer commandBuffer, float minDepthBounds, float maxDepthBounds) __attribute__ ((weak)); + void gen75_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t compareMask) __attribute__ ((weak)); + void gen75_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t writeMask) __attribute__ ((weak)); + void gen75_CmdSetStencilReference(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t reference) __attribute__ ((weak)); + void gen75_CmdBindDescriptorSets(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipelineLayout layout, uint32_t firstSet, uint32_t descriptorSetCount, const VkDescriptorSet* pDescriptorSets, uint32_t dynamicOffsetCount, const uint32_t* pDynamicOffsets) __attribute__ ((weak)); + void gen75_CmdBindIndexBuffer(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkIndexType indexType) __attribute__ ((weak)); + void gen75_CmdBindVertexBuffers(VkCommandBuffer commandBuffer, uint32_t firstBinding, uint32_t bindingCount, const VkBuffer* pBuffers, const VkDeviceSize* pOffsets) __attribute__ ((weak)); + void gen75_CmdDraw(VkCommandBuffer commandBuffer, uint32_t vertexCount, uint32_t instanceCount, uint32_t firstVertex, uint32_t firstInstance) __attribute__ ((weak)); + void gen75_CmdDrawIndexed(VkCommandBuffer commandBuffer, uint32_t indexCount, uint32_t instanceCount, uint32_t firstIndex, int32_t vertexOffset, uint32_t firstInstance) __attribute__ ((weak)); + void gen75_CmdDrawIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, uint32_t drawCount, uint32_t stride) __attribute__ ((weak)); + void gen75_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, uint32_t drawCount, uint32_t stride) __attribute__ ((weak)); + void gen75_CmdDispatch(VkCommandBuffer commandBuffer, uint32_t groupCountX, uint32_t groupCountY, uint32_t groupCountZ) __attribute__ ((weak)); + void gen75_CmdDispatchIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset) __attribute__ ((weak)); + void gen75_CmdCopyBuffer(VkCommandBuffer commandBuffer, VkBuffer srcBuffer, VkBuffer dstBuffer, uint32_t regionCount, const VkBufferCopy* pRegions) __attribute__ ((weak)); + void gen75_CmdCopyImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageCopy* pRegions) __attribute__ ((weak)); + void gen75_CmdBlitImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageBlit* pRegions, VkFilter filter) __attribute__ ((weak)); + void gen75_CmdCopyBufferToImage(VkCommandBuffer commandBuffer, VkBuffer srcBuffer, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkBufferImageCopy* pRegions) __attribute__ ((weak)); + void gen75_CmdCopyImageToBuffer(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkBuffer dstBuffer, uint32_t regionCount, const VkBufferImageCopy* pRegions) __attribute__ ((weak)); + void gen75_CmdUpdateBuffer(VkCommandBuffer commandBuffer, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize dataSize, const void* pData) __attribute__ ((weak)); + void gen75_CmdFillBuffer(VkCommandBuffer commandBuffer, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize size, uint32_t data) __attribute__ ((weak)); + void gen75_CmdClearColorImage(VkCommandBuffer commandBuffer, VkImage image, VkImageLayout imageLayout, const VkClearColorValue* pColor, uint32_t rangeCount, const VkImageSubresourceRange* pRanges) __attribute__ ((weak)); + void gen75_CmdClearDepthStencilImage(VkCommandBuffer commandBuffer, VkImage image, VkImageLayout imageLayout, const VkClearDepthStencilValue* pDepthStencil, uint32_t rangeCount, const VkImageSubresourceRange* pRanges) __attribute__ ((weak)); + void gen75_CmdClearAttachments(VkCommandBuffer commandBuffer, uint32_t attachmentCount, const VkClearAttachment* pAttachments, uint32_t rectCount, const VkClearRect* pRects) __attribute__ ((weak)); + void gen75_CmdResolveImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageResolve* pRegions) __attribute__ ((weak)); + void gen75_CmdSetEvent(VkCommandBuffer commandBuffer, VkEvent event, VkPipelineStageFlags stageMask) __attribute__ ((weak)); + void gen75_CmdResetEvent(VkCommandBuffer commandBuffer, VkEvent event, VkPipelineStageFlags stageMask) __attribute__ ((weak)); + void gen75_CmdWaitEvents(VkCommandBuffer commandBuffer, uint32_t eventCount, const VkEvent* pEvents, VkPipelineStageFlags srcStageMask, VkPipelineStageFlags dstStageMask, uint32_t memoryBarrierCount, const VkMemoryBarrier* pMemoryBarriers, uint32_t bufferMemoryBarrierCount, const VkBufferMemoryBarrier* pBufferMemoryBarriers, uint32_t imageMemoryBarrierCount, const VkImageMemoryBarrier* pImageMemoryBarriers) __attribute__ ((weak)); + void gen75_CmdPipelineBarrier(VkCommandBuffer commandBuffer, VkPipelineStageFlags srcStageMask, VkPipelineStageFlags dstStageMask, VkDependencyFlags dependencyFlags, uint32_t memoryBarrierCount, const VkMemoryBarrier* pMemoryBarriers, uint32_t bufferMemoryBarrierCount, const VkBufferMemoryBarrier* pBufferMemoryBarriers, uint32_t imageMemoryBarrierCount, const VkImageMemoryBarrier* pImageMemoryBarriers) __attribute__ ((weak)); + void gen75_CmdBeginQuery(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, VkQueryControlFlags flags) __attribute__ ((weak)); + void gen75_CmdEndQuery(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query) __attribute__ ((weak)); + void gen75_CmdBeginConditionalRenderingEXT(VkCommandBuffer commandBuffer, const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin) __attribute__ ((weak)); + void gen75_CmdEndConditionalRenderingEXT(VkCommandBuffer commandBuffer) __attribute__ ((weak)); + void gen75_CmdResetQueryPool(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount) __attribute__ ((weak)); + void gen75_CmdWriteTimestamp(VkCommandBuffer commandBuffer, VkPipelineStageFlagBits pipelineStage, VkQueryPool queryPool, uint32_t query) __attribute__ ((weak)); + void gen75_CmdCopyQueryPoolResults(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize stride, VkQueryResultFlags flags) __attribute__ ((weak)); + void gen75_CmdPushConstants(VkCommandBuffer commandBuffer, VkPipelineLayout layout, VkShaderStageFlags stageFlags, uint32_t offset, uint32_t size, const void* pValues) __attribute__ ((weak)); + void gen75_CmdBeginRenderPass(VkCommandBuffer commandBuffer, const VkRenderPassBeginInfo* pRenderPassBegin, VkSubpassContents contents) __attribute__ ((weak)); + void gen75_CmdNextSubpass(VkCommandBuffer commandBuffer, VkSubpassContents contents) __attribute__ ((weak)); + void gen75_CmdEndRenderPass(VkCommandBuffer commandBuffer) __attribute__ ((weak)); + void gen75_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCount, const VkCommandBuffer* pCommandBuffers) __attribute__ ((weak)); + VkResult gen75_CreateSwapchainKHR(VkDevice device, const VkSwapchainCreateInfoKHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSwapchainKHR* pSwapchain) __attribute__ ((weak)); + void gen75_DestroySwapchainKHR(VkDevice device, VkSwapchainKHR swapchain, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen75_GetSwapchainImagesKHR(VkDevice device, VkSwapchainKHR swapchain, uint32_t* pSwapchainImageCount, VkImage* pSwapchainImages) __attribute__ ((weak)); + VkResult gen75_AcquireNextImageKHR(VkDevice device, VkSwapchainKHR swapchain, uint64_t timeout, VkSemaphore semaphore, VkFence fence, uint32_t* pImageIndex) __attribute__ ((weak)); + VkResult gen75_QueuePresentKHR(VkQueue queue, const VkPresentInfoKHR* pPresentInfo) __attribute__ ((weak)); + void gen75_CmdPushDescriptorSetKHR(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipelineLayout layout, uint32_t set, uint32_t descriptorWriteCount, const VkWriteDescriptorSet* pDescriptorWrites) __attribute__ ((weak)); + void gen75_TrimCommandPool(VkDevice device, VkCommandPool commandPool, VkCommandPoolTrimFlags flags) __attribute__ ((weak)); + VkResult gen75_GetMemoryFdKHR(VkDevice device, const VkMemoryGetFdInfoKHR* pGetFdInfo, int* pFd) __attribute__ ((weak)); + VkResult gen75_GetMemoryFdPropertiesKHR(VkDevice device, VkExternalMemoryHandleTypeFlagBits handleType, int fd, VkMemoryFdPropertiesKHR* pMemoryFdProperties) __attribute__ ((weak)); + VkResult gen75_GetSemaphoreFdKHR(VkDevice device, const VkSemaphoreGetFdInfoKHR* pGetFdInfo, int* pFd) __attribute__ ((weak)); + VkResult gen75_ImportSemaphoreFdKHR(VkDevice device, const VkImportSemaphoreFdInfoKHR* pImportSemaphoreFdInfo) __attribute__ ((weak)); + VkResult gen75_GetFenceFdKHR(VkDevice device, const VkFenceGetFdInfoKHR* pGetFdInfo, int* pFd) __attribute__ ((weak)); + VkResult gen75_ImportFenceFdKHR(VkDevice device, const VkImportFenceFdInfoKHR* pImportFenceFdInfo) __attribute__ ((weak)); + VkResult gen75_DisplayPowerControlEXT(VkDevice device, VkDisplayKHR display, const VkDisplayPowerInfoEXT* pDisplayPowerInfo) __attribute__ ((weak)); + VkResult gen75_RegisterDeviceEventEXT(VkDevice device, const VkDeviceEventInfoEXT* pDeviceEventInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence) __attribute__ ((weak)); + VkResult gen75_RegisterDisplayEventEXT(VkDevice device, VkDisplayKHR display, const VkDisplayEventInfoEXT* pDisplayEventInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence) __attribute__ ((weak)); + VkResult gen75_GetSwapchainCounterEXT(VkDevice device, VkSwapchainKHR swapchain, VkSurfaceCounterFlagBitsEXT counter, uint64_t* pCounterValue) __attribute__ ((weak)); + void gen75_GetDeviceGroupPeerMemoryFeatures(VkDevice device, uint32_t heapIndex, uint32_t localDeviceIndex, uint32_t remoteDeviceIndex, VkPeerMemoryFeatureFlags* pPeerMemoryFeatures) __attribute__ ((weak)); + VkResult gen75_BindBufferMemory2(VkDevice device, uint32_t bindInfoCount, const VkBindBufferMemoryInfo* pBindInfos) __attribute__ ((weak)); + VkResult gen75_BindImageMemory2(VkDevice device, uint32_t bindInfoCount, const VkBindImageMemoryInfo* pBindInfos) __attribute__ ((weak)); + void gen75_CmdSetDeviceMask(VkCommandBuffer commandBuffer, uint32_t deviceMask) __attribute__ ((weak)); + VkResult gen75_GetDeviceGroupPresentCapabilitiesKHR(VkDevice device, VkDeviceGroupPresentCapabilitiesKHR* pDeviceGroupPresentCapabilities) __attribute__ ((weak)); + VkResult gen75_GetDeviceGroupSurfacePresentModesKHR(VkDevice device, VkSurfaceKHR surface, VkDeviceGroupPresentModeFlagsKHR* pModes) __attribute__ ((weak)); + VkResult gen75_AcquireNextImage2KHR(VkDevice device, const VkAcquireNextImageInfoKHR* pAcquireInfo, uint32_t* pImageIndex) __attribute__ ((weak)); + void gen75_CmdDispatchBase(VkCommandBuffer commandBuffer, uint32_t baseGroupX, uint32_t baseGroupY, uint32_t baseGroupZ, uint32_t groupCountX, uint32_t groupCountY, uint32_t groupCountZ) __attribute__ ((weak)); + VkResult gen75_CreateDescriptorUpdateTemplate(VkDevice device, const VkDescriptorUpdateTemplateCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorUpdateTemplate* pDescriptorUpdateTemplate) __attribute__ ((weak)); + void gen75_DestroyDescriptorUpdateTemplate(VkDevice device, VkDescriptorUpdateTemplate descriptorUpdateTemplate, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + void gen75_UpdateDescriptorSetWithTemplate(VkDevice device, VkDescriptorSet descriptorSet, VkDescriptorUpdateTemplate descriptorUpdateTemplate, const void* pData) __attribute__ ((weak)); + void gen75_CmdPushDescriptorSetWithTemplateKHR(VkCommandBuffer commandBuffer, VkDescriptorUpdateTemplate descriptorUpdateTemplate, VkPipelineLayout layout, uint32_t set, const void* pData) __attribute__ ((weak)); + void gen75_GetBufferMemoryRequirements2(VkDevice device, const VkBufferMemoryRequirementsInfo2* pInfo, VkMemoryRequirements2* pMemoryRequirements) __attribute__ ((weak)); + void gen75_GetImageMemoryRequirements2(VkDevice device, const VkImageMemoryRequirementsInfo2* pInfo, VkMemoryRequirements2* pMemoryRequirements) __attribute__ ((weak)); + void gen75_GetImageSparseMemoryRequirements2(VkDevice device, const VkImageSparseMemoryRequirementsInfo2* pInfo, uint32_t* pSparseMemoryRequirementCount, VkSparseImageMemoryRequirements2* pSparseMemoryRequirements) __attribute__ ((weak)); + VkResult gen75_CreateSamplerYcbcrConversion(VkDevice device, const VkSamplerYcbcrConversionCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSamplerYcbcrConversion* pYcbcrConversion) __attribute__ ((weak)); + void gen75_DestroySamplerYcbcrConversion(VkDevice device, VkSamplerYcbcrConversion ycbcrConversion, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + void gen75_GetDeviceQueue2(VkDevice device, const VkDeviceQueueInfo2* pQueueInfo, VkQueue* pQueue) __attribute__ ((weak)); + void gen75_GetDescriptorSetLayoutSupport(VkDevice device, const VkDescriptorSetLayoutCreateInfo* pCreateInfo, VkDescriptorSetLayoutSupport* pSupport) __attribute__ ((weak)); + #ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult gen75_GetSwapchainGrallocUsageANDROID(VkDevice device, VkFormat format, VkImageUsageFlags imageUsage, int* grallocUsage) __attribute__ ((weak)); +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult gen75_AcquireImageANDROID(VkDevice device, VkImage image, int nativeFenceFd, VkSemaphore semaphore, VkFence fence) __attribute__ ((weak)); +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult gen75_QueueSignalReleaseImageANDROID(VkQueue queue, uint32_t waitSemaphoreCount, const VkSemaphore* pWaitSemaphores, VkImage image, int* pNativeFenceFd) __attribute__ ((weak)); +#endif // VK_USE_PLATFORM_ANDROID_KHR + VkResult gen75_GetCalibratedTimestampsEXT(VkDevice device, uint32_t timestampCount, const VkCalibratedTimestampInfoEXT* pTimestampInfos, uint64_t* pTimestamps, uint64_t* pMaxDeviation) __attribute__ ((weak)); + VkResult gen75_CreateRenderPass2KHR(VkDevice device, const VkRenderPassCreateInfo2KHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkRenderPass* pRenderPass) __attribute__ ((weak)); + void gen75_CmdBeginRenderPass2KHR(VkCommandBuffer commandBuffer, const VkRenderPassBeginInfo* pRenderPassBegin, const VkSubpassBeginInfoKHR* pSubpassBeginInfo) __attribute__ ((weak)); + void gen75_CmdNextSubpass2KHR(VkCommandBuffer commandBuffer, const VkSubpassBeginInfoKHR* pSubpassBeginInfo, const VkSubpassEndInfoKHR* pSubpassEndInfo) __attribute__ ((weak)); + void gen75_CmdEndRenderPass2KHR(VkCommandBuffer commandBuffer, const VkSubpassEndInfoKHR* pSubpassEndInfo) __attribute__ ((weak)); +#ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult gen75_GetAndroidHardwareBufferPropertiesANDROID(VkDevice device, const struct AHardwareBuffer* buffer, VkAndroidHardwareBufferPropertiesANDROID* pProperties) __attribute__ ((weak)); +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult gen75_GetMemoryAndroidHardwareBufferANDROID(VkDevice device, const VkMemoryGetAndroidHardwareBufferInfoANDROID* pInfo, struct AHardwareBuffer** pBuffer) __attribute__ ((weak)); +#endif // VK_USE_PLATFORM_ANDROID_KHR + void gen75_CmdDrawIndirectCountKHR(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkBuffer countBuffer, VkDeviceSize countBufferOffset, uint32_t maxDrawCount, uint32_t stride) __attribute__ ((weak)); + void gen75_CmdDrawIndexedIndirectCountKHR(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkBuffer countBuffer, VkDeviceSize countBufferOffset, uint32_t maxDrawCount, uint32_t stride) __attribute__ ((weak)); + void gen75_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer, uint32_t firstBinding, uint32_t bindingCount, const VkBuffer* pBuffers, const VkDeviceSize* pOffsets, const VkDeviceSize* pSizes) __attribute__ ((weak)); + void gen75_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstCounterBuffer, uint32_t counterBufferCount, const VkBuffer* pCounterBuffers, const VkDeviceSize* pCounterBufferOffsets) __attribute__ ((weak)); + void gen75_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstCounterBuffer, uint32_t counterBufferCount, const VkBuffer* pCounterBuffers, const VkDeviceSize* pCounterBufferOffsets) __attribute__ ((weak)); + void gen75_CmdBeginQueryIndexedEXT(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, VkQueryControlFlags flags, uint32_t index) __attribute__ ((weak)); + void gen75_CmdEndQueryIndexedEXT(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, uint32_t index) __attribute__ ((weak)); + void gen75_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer, uint32_t instanceCount, uint32_t firstInstance, VkBuffer counterBuffer, VkDeviceSize counterBufferOffset, uint32_t counterOffset, uint32_t vertexStride) __attribute__ ((weak)); + VkResult gen75_CreateDmaBufImageINTEL(VkDevice device, const VkDmaBufImageCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDeviceMemory* pMem, VkImage* pImage) __attribute__ ((weak)); + + const struct anv_device_dispatch_table gen75_device_dispatch_table = { + .vkGetDeviceProcAddr = gen75_GetDeviceProcAddr, + .vkDestroyDevice = gen75_DestroyDevice, + .vkGetDeviceQueue = gen75_GetDeviceQueue, + .vkQueueSubmit = gen75_QueueSubmit, + .vkQueueWaitIdle = gen75_QueueWaitIdle, + .vkDeviceWaitIdle = gen75_DeviceWaitIdle, + .vkAllocateMemory = gen75_AllocateMemory, + .vkFreeMemory = gen75_FreeMemory, + .vkMapMemory = gen75_MapMemory, + .vkUnmapMemory = gen75_UnmapMemory, + .vkFlushMappedMemoryRanges = gen75_FlushMappedMemoryRanges, + .vkInvalidateMappedMemoryRanges = gen75_InvalidateMappedMemoryRanges, + .vkGetDeviceMemoryCommitment = gen75_GetDeviceMemoryCommitment, + .vkGetBufferMemoryRequirements = gen75_GetBufferMemoryRequirements, + .vkBindBufferMemory = gen75_BindBufferMemory, + .vkGetImageMemoryRequirements = gen75_GetImageMemoryRequirements, + .vkBindImageMemory = gen75_BindImageMemory, + .vkGetImageSparseMemoryRequirements = gen75_GetImageSparseMemoryRequirements, + .vkQueueBindSparse = gen75_QueueBindSparse, + .vkCreateFence = gen75_CreateFence, + .vkDestroyFence = gen75_DestroyFence, + .vkResetFences = gen75_ResetFences, + .vkGetFenceStatus = gen75_GetFenceStatus, + .vkWaitForFences = gen75_WaitForFences, + .vkCreateSemaphore = gen75_CreateSemaphore, + .vkDestroySemaphore = gen75_DestroySemaphore, + .vkCreateEvent = gen75_CreateEvent, + .vkDestroyEvent = gen75_DestroyEvent, + .vkGetEventStatus = gen75_GetEventStatus, + .vkSetEvent = gen75_SetEvent, + .vkResetEvent = gen75_ResetEvent, + .vkCreateQueryPool = gen75_CreateQueryPool, + .vkDestroyQueryPool = gen75_DestroyQueryPool, + .vkGetQueryPoolResults = gen75_GetQueryPoolResults, + .vkCreateBuffer = gen75_CreateBuffer, + .vkDestroyBuffer = gen75_DestroyBuffer, + .vkCreateBufferView = gen75_CreateBufferView, + .vkDestroyBufferView = gen75_DestroyBufferView, + .vkCreateImage = gen75_CreateImage, + .vkDestroyImage = gen75_DestroyImage, + .vkGetImageSubresourceLayout = gen75_GetImageSubresourceLayout, + .vkCreateImageView = gen75_CreateImageView, + .vkDestroyImageView = gen75_DestroyImageView, + .vkCreateShaderModule = gen75_CreateShaderModule, + .vkDestroyShaderModule = gen75_DestroyShaderModule, + .vkCreatePipelineCache = gen75_CreatePipelineCache, + .vkDestroyPipelineCache = gen75_DestroyPipelineCache, + .vkGetPipelineCacheData = gen75_GetPipelineCacheData, + .vkMergePipelineCaches = gen75_MergePipelineCaches, + .vkCreateGraphicsPipelines = gen75_CreateGraphicsPipelines, + .vkCreateComputePipelines = gen75_CreateComputePipelines, + .vkDestroyPipeline = gen75_DestroyPipeline, + .vkCreatePipelineLayout = gen75_CreatePipelineLayout, + .vkDestroyPipelineLayout = gen75_DestroyPipelineLayout, + .vkCreateSampler = gen75_CreateSampler, + .vkDestroySampler = gen75_DestroySampler, + .vkCreateDescriptorSetLayout = gen75_CreateDescriptorSetLayout, + .vkDestroyDescriptorSetLayout = gen75_DestroyDescriptorSetLayout, + .vkCreateDescriptorPool = gen75_CreateDescriptorPool, + .vkDestroyDescriptorPool = gen75_DestroyDescriptorPool, + .vkResetDescriptorPool = gen75_ResetDescriptorPool, + .vkAllocateDescriptorSets = gen75_AllocateDescriptorSets, + .vkFreeDescriptorSets = gen75_FreeDescriptorSets, + .vkUpdateDescriptorSets = gen75_UpdateDescriptorSets, + .vkCreateFramebuffer = gen75_CreateFramebuffer, + .vkDestroyFramebuffer = gen75_DestroyFramebuffer, + .vkCreateRenderPass = gen75_CreateRenderPass, + .vkDestroyRenderPass = gen75_DestroyRenderPass, + .vkGetRenderAreaGranularity = gen75_GetRenderAreaGranularity, + .vkCreateCommandPool = gen75_CreateCommandPool, + .vkDestroyCommandPool = gen75_DestroyCommandPool, + .vkResetCommandPool = gen75_ResetCommandPool, + .vkAllocateCommandBuffers = gen75_AllocateCommandBuffers, + .vkFreeCommandBuffers = gen75_FreeCommandBuffers, + .vkBeginCommandBuffer = gen75_BeginCommandBuffer, + .vkEndCommandBuffer = gen75_EndCommandBuffer, + .vkResetCommandBuffer = gen75_ResetCommandBuffer, + .vkCmdBindPipeline = gen75_CmdBindPipeline, + .vkCmdSetViewport = gen75_CmdSetViewport, + .vkCmdSetScissor = gen75_CmdSetScissor, + .vkCmdSetLineWidth = gen75_CmdSetLineWidth, + .vkCmdSetDepthBias = gen75_CmdSetDepthBias, + .vkCmdSetBlendConstants = gen75_CmdSetBlendConstants, + .vkCmdSetDepthBounds = gen75_CmdSetDepthBounds, + .vkCmdSetStencilCompareMask = gen75_CmdSetStencilCompareMask, + .vkCmdSetStencilWriteMask = gen75_CmdSetStencilWriteMask, + .vkCmdSetStencilReference = gen75_CmdSetStencilReference, + .vkCmdBindDescriptorSets = gen75_CmdBindDescriptorSets, + .vkCmdBindIndexBuffer = gen75_CmdBindIndexBuffer, + .vkCmdBindVertexBuffers = gen75_CmdBindVertexBuffers, + .vkCmdDraw = gen75_CmdDraw, + .vkCmdDrawIndexed = gen75_CmdDrawIndexed, + .vkCmdDrawIndirect = gen75_CmdDrawIndirect, + .vkCmdDrawIndexedIndirect = gen75_CmdDrawIndexedIndirect, + .vkCmdDispatch = gen75_CmdDispatch, + .vkCmdDispatchIndirect = gen75_CmdDispatchIndirect, + .vkCmdCopyBuffer = gen75_CmdCopyBuffer, + .vkCmdCopyImage = gen75_CmdCopyImage, + .vkCmdBlitImage = gen75_CmdBlitImage, + .vkCmdCopyBufferToImage = gen75_CmdCopyBufferToImage, + .vkCmdCopyImageToBuffer = gen75_CmdCopyImageToBuffer, + .vkCmdUpdateBuffer = gen75_CmdUpdateBuffer, + .vkCmdFillBuffer = gen75_CmdFillBuffer, + .vkCmdClearColorImage = gen75_CmdClearColorImage, + .vkCmdClearDepthStencilImage = gen75_CmdClearDepthStencilImage, + .vkCmdClearAttachments = gen75_CmdClearAttachments, + .vkCmdResolveImage = gen75_CmdResolveImage, + .vkCmdSetEvent = gen75_CmdSetEvent, + .vkCmdResetEvent = gen75_CmdResetEvent, + .vkCmdWaitEvents = gen75_CmdWaitEvents, + .vkCmdPipelineBarrier = gen75_CmdPipelineBarrier, + .vkCmdBeginQuery = gen75_CmdBeginQuery, + .vkCmdEndQuery = gen75_CmdEndQuery, + .vkCmdBeginConditionalRenderingEXT = gen75_CmdBeginConditionalRenderingEXT, + .vkCmdEndConditionalRenderingEXT = gen75_CmdEndConditionalRenderingEXT, + .vkCmdResetQueryPool = gen75_CmdResetQueryPool, + .vkCmdWriteTimestamp = gen75_CmdWriteTimestamp, + .vkCmdCopyQueryPoolResults = gen75_CmdCopyQueryPoolResults, + .vkCmdPushConstants = gen75_CmdPushConstants, + .vkCmdBeginRenderPass = gen75_CmdBeginRenderPass, + .vkCmdNextSubpass = gen75_CmdNextSubpass, + .vkCmdEndRenderPass = gen75_CmdEndRenderPass, + .vkCmdExecuteCommands = gen75_CmdExecuteCommands, + .vkCreateSwapchainKHR = gen75_CreateSwapchainKHR, + .vkDestroySwapchainKHR = gen75_DestroySwapchainKHR, + .vkGetSwapchainImagesKHR = gen75_GetSwapchainImagesKHR, + .vkAcquireNextImageKHR = gen75_AcquireNextImageKHR, + .vkQueuePresentKHR = gen75_QueuePresentKHR, + .vkCmdPushDescriptorSetKHR = gen75_CmdPushDescriptorSetKHR, + .vkTrimCommandPool = gen75_TrimCommandPool, + .vkTrimCommandPoolKHR = gen75_TrimCommandPool, + .vkGetMemoryFdKHR = gen75_GetMemoryFdKHR, + .vkGetMemoryFdPropertiesKHR = gen75_GetMemoryFdPropertiesKHR, + .vkGetSemaphoreFdKHR = gen75_GetSemaphoreFdKHR, + .vkImportSemaphoreFdKHR = gen75_ImportSemaphoreFdKHR, + .vkGetFenceFdKHR = gen75_GetFenceFdKHR, + .vkImportFenceFdKHR = gen75_ImportFenceFdKHR, + .vkDisplayPowerControlEXT = gen75_DisplayPowerControlEXT, + .vkRegisterDeviceEventEXT = gen75_RegisterDeviceEventEXT, + .vkRegisterDisplayEventEXT = gen75_RegisterDisplayEventEXT, + .vkGetSwapchainCounterEXT = gen75_GetSwapchainCounterEXT, + .vkGetDeviceGroupPeerMemoryFeatures = gen75_GetDeviceGroupPeerMemoryFeatures, + .vkGetDeviceGroupPeerMemoryFeaturesKHR = gen75_GetDeviceGroupPeerMemoryFeatures, + .vkBindBufferMemory2 = gen75_BindBufferMemory2, + .vkBindBufferMemory2KHR = gen75_BindBufferMemory2, + .vkBindImageMemory2 = gen75_BindImageMemory2, + .vkBindImageMemory2KHR = gen75_BindImageMemory2, + .vkCmdSetDeviceMask = gen75_CmdSetDeviceMask, + .vkCmdSetDeviceMaskKHR = gen75_CmdSetDeviceMask, + .vkGetDeviceGroupPresentCapabilitiesKHR = gen75_GetDeviceGroupPresentCapabilitiesKHR, + .vkGetDeviceGroupSurfacePresentModesKHR = gen75_GetDeviceGroupSurfacePresentModesKHR, + .vkAcquireNextImage2KHR = gen75_AcquireNextImage2KHR, + .vkCmdDispatchBase = gen75_CmdDispatchBase, + .vkCmdDispatchBaseKHR = gen75_CmdDispatchBase, + .vkCreateDescriptorUpdateTemplate = gen75_CreateDescriptorUpdateTemplate, + .vkCreateDescriptorUpdateTemplateKHR = gen75_CreateDescriptorUpdateTemplate, + .vkDestroyDescriptorUpdateTemplate = gen75_DestroyDescriptorUpdateTemplate, + .vkDestroyDescriptorUpdateTemplateKHR = gen75_DestroyDescriptorUpdateTemplate, + .vkUpdateDescriptorSetWithTemplate = gen75_UpdateDescriptorSetWithTemplate, + .vkUpdateDescriptorSetWithTemplateKHR = gen75_UpdateDescriptorSetWithTemplate, + .vkCmdPushDescriptorSetWithTemplateKHR = gen75_CmdPushDescriptorSetWithTemplateKHR, + .vkGetBufferMemoryRequirements2 = gen75_GetBufferMemoryRequirements2, + .vkGetBufferMemoryRequirements2KHR = gen75_GetBufferMemoryRequirements2, + .vkGetImageMemoryRequirements2 = gen75_GetImageMemoryRequirements2, + .vkGetImageMemoryRequirements2KHR = gen75_GetImageMemoryRequirements2, + .vkGetImageSparseMemoryRequirements2 = gen75_GetImageSparseMemoryRequirements2, + .vkGetImageSparseMemoryRequirements2KHR = gen75_GetImageSparseMemoryRequirements2, + .vkCreateSamplerYcbcrConversion = gen75_CreateSamplerYcbcrConversion, + .vkCreateSamplerYcbcrConversionKHR = gen75_CreateSamplerYcbcrConversion, + .vkDestroySamplerYcbcrConversion = gen75_DestroySamplerYcbcrConversion, + .vkDestroySamplerYcbcrConversionKHR = gen75_DestroySamplerYcbcrConversion, + .vkGetDeviceQueue2 = gen75_GetDeviceQueue2, + .vkGetDescriptorSetLayoutSupport = gen75_GetDescriptorSetLayoutSupport, + .vkGetDescriptorSetLayoutSupportKHR = gen75_GetDescriptorSetLayoutSupport, +#ifdef VK_USE_PLATFORM_ANDROID_KHR + .vkGetSwapchainGrallocUsageANDROID = gen75_GetSwapchainGrallocUsageANDROID, +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + .vkAcquireImageANDROID = gen75_AcquireImageANDROID, +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + .vkQueueSignalReleaseImageANDROID = gen75_QueueSignalReleaseImageANDROID, +#endif // VK_USE_PLATFORM_ANDROID_KHR + .vkGetCalibratedTimestampsEXT = gen75_GetCalibratedTimestampsEXT, + .vkCreateRenderPass2KHR = gen75_CreateRenderPass2KHR, + .vkCmdBeginRenderPass2KHR = gen75_CmdBeginRenderPass2KHR, + .vkCmdNextSubpass2KHR = gen75_CmdNextSubpass2KHR, + .vkCmdEndRenderPass2KHR = gen75_CmdEndRenderPass2KHR, +#ifdef VK_USE_PLATFORM_ANDROID_KHR + .vkGetAndroidHardwareBufferPropertiesANDROID = gen75_GetAndroidHardwareBufferPropertiesANDROID, +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + .vkGetMemoryAndroidHardwareBufferANDROID = gen75_GetMemoryAndroidHardwareBufferANDROID, +#endif // VK_USE_PLATFORM_ANDROID_KHR + .vkCmdDrawIndirectCountKHR = gen75_CmdDrawIndirectCountKHR, + .vkCmdDrawIndexedIndirectCountKHR = gen75_CmdDrawIndexedIndirectCountKHR, + .vkCmdBindTransformFeedbackBuffersEXT = gen75_CmdBindTransformFeedbackBuffersEXT, + .vkCmdBeginTransformFeedbackEXT = gen75_CmdBeginTransformFeedbackEXT, + .vkCmdEndTransformFeedbackEXT = gen75_CmdEndTransformFeedbackEXT, + .vkCmdBeginQueryIndexedEXT = gen75_CmdBeginQueryIndexedEXT, + .vkCmdEndQueryIndexedEXT = gen75_CmdEndQueryIndexedEXT, + .vkCmdDrawIndirectByteCountEXT = gen75_CmdDrawIndirectByteCountEXT, + .vkCreateDmaBufImageINTEL = gen75_CreateDmaBufImageINTEL, + }; + PFN_vkVoidFunction gen8_GetDeviceProcAddr(VkDevice device, const char* pName) __attribute__ ((weak)); + void gen8_DestroyDevice(VkDevice device, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + void gen8_GetDeviceQueue(VkDevice device, uint32_t queueFamilyIndex, uint32_t queueIndex, VkQueue* pQueue) __attribute__ ((weak)); + VkResult gen8_QueueSubmit(VkQueue queue, uint32_t submitCount, const VkSubmitInfo* pSubmits, VkFence fence) __attribute__ ((weak)); + VkResult gen8_QueueWaitIdle(VkQueue queue) __attribute__ ((weak)); + VkResult gen8_DeviceWaitIdle(VkDevice device) __attribute__ ((weak)); + VkResult gen8_AllocateMemory(VkDevice device, const VkMemoryAllocateInfo* pAllocateInfo, const VkAllocationCallbacks* pAllocator, VkDeviceMemory* pMemory) __attribute__ ((weak)); + void gen8_FreeMemory(VkDevice device, VkDeviceMemory memory, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen8_MapMemory(VkDevice device, VkDeviceMemory memory, VkDeviceSize offset, VkDeviceSize size, VkMemoryMapFlags flags, void** ppData) __attribute__ ((weak)); + void gen8_UnmapMemory(VkDevice device, VkDeviceMemory memory) __attribute__ ((weak)); + VkResult gen8_FlushMappedMemoryRanges(VkDevice device, uint32_t memoryRangeCount, const VkMappedMemoryRange* pMemoryRanges) __attribute__ ((weak)); + VkResult gen8_InvalidateMappedMemoryRanges(VkDevice device, uint32_t memoryRangeCount, const VkMappedMemoryRange* pMemoryRanges) __attribute__ ((weak)); + void gen8_GetDeviceMemoryCommitment(VkDevice device, VkDeviceMemory memory, VkDeviceSize* pCommittedMemoryInBytes) __attribute__ ((weak)); + void gen8_GetBufferMemoryRequirements(VkDevice device, VkBuffer buffer, VkMemoryRequirements* pMemoryRequirements) __attribute__ ((weak)); + VkResult gen8_BindBufferMemory(VkDevice device, VkBuffer buffer, VkDeviceMemory memory, VkDeviceSize memoryOffset) __attribute__ ((weak)); + void gen8_GetImageMemoryRequirements(VkDevice device, VkImage image, VkMemoryRequirements* pMemoryRequirements) __attribute__ ((weak)); + VkResult gen8_BindImageMemory(VkDevice device, VkImage image, VkDeviceMemory memory, VkDeviceSize memoryOffset) __attribute__ ((weak)); + void gen8_GetImageSparseMemoryRequirements(VkDevice device, VkImage image, uint32_t* pSparseMemoryRequirementCount, VkSparseImageMemoryRequirements* pSparseMemoryRequirements) __attribute__ ((weak)); + VkResult gen8_QueueBindSparse(VkQueue queue, uint32_t bindInfoCount, const VkBindSparseInfo* pBindInfo, VkFence fence) __attribute__ ((weak)); + VkResult gen8_CreateFence(VkDevice device, const VkFenceCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence) __attribute__ ((weak)); + void gen8_DestroyFence(VkDevice device, VkFence fence, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen8_ResetFences(VkDevice device, uint32_t fenceCount, const VkFence* pFences) __attribute__ ((weak)); + VkResult gen8_GetFenceStatus(VkDevice device, VkFence fence) __attribute__ ((weak)); + VkResult gen8_WaitForFences(VkDevice device, uint32_t fenceCount, const VkFence* pFences, VkBool32 waitAll, uint64_t timeout) __attribute__ ((weak)); + VkResult gen8_CreateSemaphore(VkDevice device, const VkSemaphoreCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSemaphore* pSemaphore) __attribute__ ((weak)); + void gen8_DestroySemaphore(VkDevice device, VkSemaphore semaphore, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen8_CreateEvent(VkDevice device, const VkEventCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkEvent* pEvent) __attribute__ ((weak)); + void gen8_DestroyEvent(VkDevice device, VkEvent event, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen8_GetEventStatus(VkDevice device, VkEvent event) __attribute__ ((weak)); + VkResult gen8_SetEvent(VkDevice device, VkEvent event) __attribute__ ((weak)); + VkResult gen8_ResetEvent(VkDevice device, VkEvent event) __attribute__ ((weak)); + VkResult gen8_CreateQueryPool(VkDevice device, const VkQueryPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkQueryPool* pQueryPool) __attribute__ ((weak)); + void gen8_DestroyQueryPool(VkDevice device, VkQueryPool queryPool, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen8_GetQueryPoolResults(VkDevice device, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount, size_t dataSize, void* pData, VkDeviceSize stride, VkQueryResultFlags flags) __attribute__ ((weak)); + VkResult gen8_CreateBuffer(VkDevice device, const VkBufferCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkBuffer* pBuffer) __attribute__ ((weak)); + void gen8_DestroyBuffer(VkDevice device, VkBuffer buffer, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen8_CreateBufferView(VkDevice device, const VkBufferViewCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkBufferView* pView) __attribute__ ((weak)); + void gen8_DestroyBufferView(VkDevice device, VkBufferView bufferView, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen8_CreateImage(VkDevice device, const VkImageCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkImage* pImage) __attribute__ ((weak)); + void gen8_DestroyImage(VkDevice device, VkImage image, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + void gen8_GetImageSubresourceLayout(VkDevice device, VkImage image, const VkImageSubresource* pSubresource, VkSubresourceLayout* pLayout) __attribute__ ((weak)); + VkResult gen8_CreateImageView(VkDevice device, const VkImageViewCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkImageView* pView) __attribute__ ((weak)); + void gen8_DestroyImageView(VkDevice device, VkImageView imageView, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen8_CreateShaderModule(VkDevice device, const VkShaderModuleCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkShaderModule* pShaderModule) __attribute__ ((weak)); + void gen8_DestroyShaderModule(VkDevice device, VkShaderModule shaderModule, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen8_CreatePipelineCache(VkDevice device, const VkPipelineCacheCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkPipelineCache* pPipelineCache) __attribute__ ((weak)); + void gen8_DestroyPipelineCache(VkDevice device, VkPipelineCache pipelineCache, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen8_GetPipelineCacheData(VkDevice device, VkPipelineCache pipelineCache, size_t* pDataSize, void* pData) __attribute__ ((weak)); + VkResult gen8_MergePipelineCaches(VkDevice device, VkPipelineCache dstCache, uint32_t srcCacheCount, const VkPipelineCache* pSrcCaches) __attribute__ ((weak)); + VkResult gen8_CreateGraphicsPipelines(VkDevice device, VkPipelineCache pipelineCache, uint32_t createInfoCount, const VkGraphicsPipelineCreateInfo* pCreateInfos, const VkAllocationCallbacks* pAllocator, VkPipeline* pPipelines) __attribute__ ((weak)); + VkResult gen8_CreateComputePipelines(VkDevice device, VkPipelineCache pipelineCache, uint32_t createInfoCount, const VkComputePipelineCreateInfo* pCreateInfos, const VkAllocationCallbacks* pAllocator, VkPipeline* pPipelines) __attribute__ ((weak)); + void gen8_DestroyPipeline(VkDevice device, VkPipeline pipeline, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen8_CreatePipelineLayout(VkDevice device, const VkPipelineLayoutCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkPipelineLayout* pPipelineLayout) __attribute__ ((weak)); + void gen8_DestroyPipelineLayout(VkDevice device, VkPipelineLayout pipelineLayout, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen8_CreateSampler(VkDevice device, const VkSamplerCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSampler* pSampler) __attribute__ ((weak)); + void gen8_DestroySampler(VkDevice device, VkSampler sampler, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen8_CreateDescriptorSetLayout(VkDevice device, const VkDescriptorSetLayoutCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorSetLayout* pSetLayout) __attribute__ ((weak)); + void gen8_DestroyDescriptorSetLayout(VkDevice device, VkDescriptorSetLayout descriptorSetLayout, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen8_CreateDescriptorPool(VkDevice device, const VkDescriptorPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorPool* pDescriptorPool) __attribute__ ((weak)); + void gen8_DestroyDescriptorPool(VkDevice device, VkDescriptorPool descriptorPool, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen8_ResetDescriptorPool(VkDevice device, VkDescriptorPool descriptorPool, VkDescriptorPoolResetFlags flags) __attribute__ ((weak)); + VkResult gen8_AllocateDescriptorSets(VkDevice device, const VkDescriptorSetAllocateInfo* pAllocateInfo, VkDescriptorSet* pDescriptorSets) __attribute__ ((weak)); + VkResult gen8_FreeDescriptorSets(VkDevice device, VkDescriptorPool descriptorPool, uint32_t descriptorSetCount, const VkDescriptorSet* pDescriptorSets) __attribute__ ((weak)); + void gen8_UpdateDescriptorSets(VkDevice device, uint32_t descriptorWriteCount, const VkWriteDescriptorSet* pDescriptorWrites, uint32_t descriptorCopyCount, const VkCopyDescriptorSet* pDescriptorCopies) __attribute__ ((weak)); + VkResult gen8_CreateFramebuffer(VkDevice device, const VkFramebufferCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkFramebuffer* pFramebuffer) __attribute__ ((weak)); + void gen8_DestroyFramebuffer(VkDevice device, VkFramebuffer framebuffer, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen8_CreateRenderPass(VkDevice device, const VkRenderPassCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkRenderPass* pRenderPass) __attribute__ ((weak)); + void gen8_DestroyRenderPass(VkDevice device, VkRenderPass renderPass, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + void gen8_GetRenderAreaGranularity(VkDevice device, VkRenderPass renderPass, VkExtent2D* pGranularity) __attribute__ ((weak)); + VkResult gen8_CreateCommandPool(VkDevice device, const VkCommandPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkCommandPool* pCommandPool) __attribute__ ((weak)); + void gen8_DestroyCommandPool(VkDevice device, VkCommandPool commandPool, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen8_ResetCommandPool(VkDevice device, VkCommandPool commandPool, VkCommandPoolResetFlags flags) __attribute__ ((weak)); + VkResult gen8_AllocateCommandBuffers(VkDevice device, const VkCommandBufferAllocateInfo* pAllocateInfo, VkCommandBuffer* pCommandBuffers) __attribute__ ((weak)); + void gen8_FreeCommandBuffers(VkDevice device, VkCommandPool commandPool, uint32_t commandBufferCount, const VkCommandBuffer* pCommandBuffers) __attribute__ ((weak)); + VkResult gen8_BeginCommandBuffer(VkCommandBuffer commandBuffer, const VkCommandBufferBeginInfo* pBeginInfo) __attribute__ ((weak)); + VkResult gen8_EndCommandBuffer(VkCommandBuffer commandBuffer) __attribute__ ((weak)); + VkResult gen8_ResetCommandBuffer(VkCommandBuffer commandBuffer, VkCommandBufferResetFlags flags) __attribute__ ((weak)); + void gen8_CmdBindPipeline(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipeline pipeline) __attribute__ ((weak)); + void gen8_CmdSetViewport(VkCommandBuffer commandBuffer, uint32_t firstViewport, uint32_t viewportCount, const VkViewport* pViewports) __attribute__ ((weak)); + void gen8_CmdSetScissor(VkCommandBuffer commandBuffer, uint32_t firstScissor, uint32_t scissorCount, const VkRect2D* pScissors) __attribute__ ((weak)); + void gen8_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth) __attribute__ ((weak)); + void gen8_CmdSetDepthBias(VkCommandBuffer commandBuffer, float depthBiasConstantFactor, float depthBiasClamp, float depthBiasSlopeFactor) __attribute__ ((weak)); + void gen8_CmdSetBlendConstants(VkCommandBuffer commandBuffer, const float blendConstants[4]) __attribute__ ((weak)); + void gen8_CmdSetDepthBounds(VkCommandBuffer commandBuffer, float minDepthBounds, float maxDepthBounds) __attribute__ ((weak)); + void gen8_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t compareMask) __attribute__ ((weak)); + void gen8_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t writeMask) __attribute__ ((weak)); + void gen8_CmdSetStencilReference(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t reference) __attribute__ ((weak)); + void gen8_CmdBindDescriptorSets(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipelineLayout layout, uint32_t firstSet, uint32_t descriptorSetCount, const VkDescriptorSet* pDescriptorSets, uint32_t dynamicOffsetCount, const uint32_t* pDynamicOffsets) __attribute__ ((weak)); + void gen8_CmdBindIndexBuffer(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkIndexType indexType) __attribute__ ((weak)); + void gen8_CmdBindVertexBuffers(VkCommandBuffer commandBuffer, uint32_t firstBinding, uint32_t bindingCount, const VkBuffer* pBuffers, const VkDeviceSize* pOffsets) __attribute__ ((weak)); + void gen8_CmdDraw(VkCommandBuffer commandBuffer, uint32_t vertexCount, uint32_t instanceCount, uint32_t firstVertex, uint32_t firstInstance) __attribute__ ((weak)); + void gen8_CmdDrawIndexed(VkCommandBuffer commandBuffer, uint32_t indexCount, uint32_t instanceCount, uint32_t firstIndex, int32_t vertexOffset, uint32_t firstInstance) __attribute__ ((weak)); + void gen8_CmdDrawIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, uint32_t drawCount, uint32_t stride) __attribute__ ((weak)); + void gen8_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, uint32_t drawCount, uint32_t stride) __attribute__ ((weak)); + void gen8_CmdDispatch(VkCommandBuffer commandBuffer, uint32_t groupCountX, uint32_t groupCountY, uint32_t groupCountZ) __attribute__ ((weak)); + void gen8_CmdDispatchIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset) __attribute__ ((weak)); + void gen8_CmdCopyBuffer(VkCommandBuffer commandBuffer, VkBuffer srcBuffer, VkBuffer dstBuffer, uint32_t regionCount, const VkBufferCopy* pRegions) __attribute__ ((weak)); + void gen8_CmdCopyImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageCopy* pRegions) __attribute__ ((weak)); + void gen8_CmdBlitImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageBlit* pRegions, VkFilter filter) __attribute__ ((weak)); + void gen8_CmdCopyBufferToImage(VkCommandBuffer commandBuffer, VkBuffer srcBuffer, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkBufferImageCopy* pRegions) __attribute__ ((weak)); + void gen8_CmdCopyImageToBuffer(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkBuffer dstBuffer, uint32_t regionCount, const VkBufferImageCopy* pRegions) __attribute__ ((weak)); + void gen8_CmdUpdateBuffer(VkCommandBuffer commandBuffer, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize dataSize, const void* pData) __attribute__ ((weak)); + void gen8_CmdFillBuffer(VkCommandBuffer commandBuffer, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize size, uint32_t data) __attribute__ ((weak)); + void gen8_CmdClearColorImage(VkCommandBuffer commandBuffer, VkImage image, VkImageLayout imageLayout, const VkClearColorValue* pColor, uint32_t rangeCount, const VkImageSubresourceRange* pRanges) __attribute__ ((weak)); + void gen8_CmdClearDepthStencilImage(VkCommandBuffer commandBuffer, VkImage image, VkImageLayout imageLayout, const VkClearDepthStencilValue* pDepthStencil, uint32_t rangeCount, const VkImageSubresourceRange* pRanges) __attribute__ ((weak)); + void gen8_CmdClearAttachments(VkCommandBuffer commandBuffer, uint32_t attachmentCount, const VkClearAttachment* pAttachments, uint32_t rectCount, const VkClearRect* pRects) __attribute__ ((weak)); + void gen8_CmdResolveImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageResolve* pRegions) __attribute__ ((weak)); + void gen8_CmdSetEvent(VkCommandBuffer commandBuffer, VkEvent event, VkPipelineStageFlags stageMask) __attribute__ ((weak)); + void gen8_CmdResetEvent(VkCommandBuffer commandBuffer, VkEvent event, VkPipelineStageFlags stageMask) __attribute__ ((weak)); + void gen8_CmdWaitEvents(VkCommandBuffer commandBuffer, uint32_t eventCount, const VkEvent* pEvents, VkPipelineStageFlags srcStageMask, VkPipelineStageFlags dstStageMask, uint32_t memoryBarrierCount, const VkMemoryBarrier* pMemoryBarriers, uint32_t bufferMemoryBarrierCount, const VkBufferMemoryBarrier* pBufferMemoryBarriers, uint32_t imageMemoryBarrierCount, const VkImageMemoryBarrier* pImageMemoryBarriers) __attribute__ ((weak)); + void gen8_CmdPipelineBarrier(VkCommandBuffer commandBuffer, VkPipelineStageFlags srcStageMask, VkPipelineStageFlags dstStageMask, VkDependencyFlags dependencyFlags, uint32_t memoryBarrierCount, const VkMemoryBarrier* pMemoryBarriers, uint32_t bufferMemoryBarrierCount, const VkBufferMemoryBarrier* pBufferMemoryBarriers, uint32_t imageMemoryBarrierCount, const VkImageMemoryBarrier* pImageMemoryBarriers) __attribute__ ((weak)); + void gen8_CmdBeginQuery(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, VkQueryControlFlags flags) __attribute__ ((weak)); + void gen8_CmdEndQuery(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query) __attribute__ ((weak)); + void gen8_CmdBeginConditionalRenderingEXT(VkCommandBuffer commandBuffer, const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin) __attribute__ ((weak)); + void gen8_CmdEndConditionalRenderingEXT(VkCommandBuffer commandBuffer) __attribute__ ((weak)); + void gen8_CmdResetQueryPool(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount) __attribute__ ((weak)); + void gen8_CmdWriteTimestamp(VkCommandBuffer commandBuffer, VkPipelineStageFlagBits pipelineStage, VkQueryPool queryPool, uint32_t query) __attribute__ ((weak)); + void gen8_CmdCopyQueryPoolResults(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize stride, VkQueryResultFlags flags) __attribute__ ((weak)); + void gen8_CmdPushConstants(VkCommandBuffer commandBuffer, VkPipelineLayout layout, VkShaderStageFlags stageFlags, uint32_t offset, uint32_t size, const void* pValues) __attribute__ ((weak)); + void gen8_CmdBeginRenderPass(VkCommandBuffer commandBuffer, const VkRenderPassBeginInfo* pRenderPassBegin, VkSubpassContents contents) __attribute__ ((weak)); + void gen8_CmdNextSubpass(VkCommandBuffer commandBuffer, VkSubpassContents contents) __attribute__ ((weak)); + void gen8_CmdEndRenderPass(VkCommandBuffer commandBuffer) __attribute__ ((weak)); + void gen8_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCount, const VkCommandBuffer* pCommandBuffers) __attribute__ ((weak)); + VkResult gen8_CreateSwapchainKHR(VkDevice device, const VkSwapchainCreateInfoKHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSwapchainKHR* pSwapchain) __attribute__ ((weak)); + void gen8_DestroySwapchainKHR(VkDevice device, VkSwapchainKHR swapchain, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen8_GetSwapchainImagesKHR(VkDevice device, VkSwapchainKHR swapchain, uint32_t* pSwapchainImageCount, VkImage* pSwapchainImages) __attribute__ ((weak)); + VkResult gen8_AcquireNextImageKHR(VkDevice device, VkSwapchainKHR swapchain, uint64_t timeout, VkSemaphore semaphore, VkFence fence, uint32_t* pImageIndex) __attribute__ ((weak)); + VkResult gen8_QueuePresentKHR(VkQueue queue, const VkPresentInfoKHR* pPresentInfo) __attribute__ ((weak)); + void gen8_CmdPushDescriptorSetKHR(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipelineLayout layout, uint32_t set, uint32_t descriptorWriteCount, const VkWriteDescriptorSet* pDescriptorWrites) __attribute__ ((weak)); + void gen8_TrimCommandPool(VkDevice device, VkCommandPool commandPool, VkCommandPoolTrimFlags flags) __attribute__ ((weak)); + VkResult gen8_GetMemoryFdKHR(VkDevice device, const VkMemoryGetFdInfoKHR* pGetFdInfo, int* pFd) __attribute__ ((weak)); + VkResult gen8_GetMemoryFdPropertiesKHR(VkDevice device, VkExternalMemoryHandleTypeFlagBits handleType, int fd, VkMemoryFdPropertiesKHR* pMemoryFdProperties) __attribute__ ((weak)); + VkResult gen8_GetSemaphoreFdKHR(VkDevice device, const VkSemaphoreGetFdInfoKHR* pGetFdInfo, int* pFd) __attribute__ ((weak)); + VkResult gen8_ImportSemaphoreFdKHR(VkDevice device, const VkImportSemaphoreFdInfoKHR* pImportSemaphoreFdInfo) __attribute__ ((weak)); + VkResult gen8_GetFenceFdKHR(VkDevice device, const VkFenceGetFdInfoKHR* pGetFdInfo, int* pFd) __attribute__ ((weak)); + VkResult gen8_ImportFenceFdKHR(VkDevice device, const VkImportFenceFdInfoKHR* pImportFenceFdInfo) __attribute__ ((weak)); + VkResult gen8_DisplayPowerControlEXT(VkDevice device, VkDisplayKHR display, const VkDisplayPowerInfoEXT* pDisplayPowerInfo) __attribute__ ((weak)); + VkResult gen8_RegisterDeviceEventEXT(VkDevice device, const VkDeviceEventInfoEXT* pDeviceEventInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence) __attribute__ ((weak)); + VkResult gen8_RegisterDisplayEventEXT(VkDevice device, VkDisplayKHR display, const VkDisplayEventInfoEXT* pDisplayEventInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence) __attribute__ ((weak)); + VkResult gen8_GetSwapchainCounterEXT(VkDevice device, VkSwapchainKHR swapchain, VkSurfaceCounterFlagBitsEXT counter, uint64_t* pCounterValue) __attribute__ ((weak)); + void gen8_GetDeviceGroupPeerMemoryFeatures(VkDevice device, uint32_t heapIndex, uint32_t localDeviceIndex, uint32_t remoteDeviceIndex, VkPeerMemoryFeatureFlags* pPeerMemoryFeatures) __attribute__ ((weak)); + VkResult gen8_BindBufferMemory2(VkDevice device, uint32_t bindInfoCount, const VkBindBufferMemoryInfo* pBindInfos) __attribute__ ((weak)); + VkResult gen8_BindImageMemory2(VkDevice device, uint32_t bindInfoCount, const VkBindImageMemoryInfo* pBindInfos) __attribute__ ((weak)); + void gen8_CmdSetDeviceMask(VkCommandBuffer commandBuffer, uint32_t deviceMask) __attribute__ ((weak)); + VkResult gen8_GetDeviceGroupPresentCapabilitiesKHR(VkDevice device, VkDeviceGroupPresentCapabilitiesKHR* pDeviceGroupPresentCapabilities) __attribute__ ((weak)); + VkResult gen8_GetDeviceGroupSurfacePresentModesKHR(VkDevice device, VkSurfaceKHR surface, VkDeviceGroupPresentModeFlagsKHR* pModes) __attribute__ ((weak)); + VkResult gen8_AcquireNextImage2KHR(VkDevice device, const VkAcquireNextImageInfoKHR* pAcquireInfo, uint32_t* pImageIndex) __attribute__ ((weak)); + void gen8_CmdDispatchBase(VkCommandBuffer commandBuffer, uint32_t baseGroupX, uint32_t baseGroupY, uint32_t baseGroupZ, uint32_t groupCountX, uint32_t groupCountY, uint32_t groupCountZ) __attribute__ ((weak)); + VkResult gen8_CreateDescriptorUpdateTemplate(VkDevice device, const VkDescriptorUpdateTemplateCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorUpdateTemplate* pDescriptorUpdateTemplate) __attribute__ ((weak)); + void gen8_DestroyDescriptorUpdateTemplate(VkDevice device, VkDescriptorUpdateTemplate descriptorUpdateTemplate, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + void gen8_UpdateDescriptorSetWithTemplate(VkDevice device, VkDescriptorSet descriptorSet, VkDescriptorUpdateTemplate descriptorUpdateTemplate, const void* pData) __attribute__ ((weak)); + void gen8_CmdPushDescriptorSetWithTemplateKHR(VkCommandBuffer commandBuffer, VkDescriptorUpdateTemplate descriptorUpdateTemplate, VkPipelineLayout layout, uint32_t set, const void* pData) __attribute__ ((weak)); + void gen8_GetBufferMemoryRequirements2(VkDevice device, const VkBufferMemoryRequirementsInfo2* pInfo, VkMemoryRequirements2* pMemoryRequirements) __attribute__ ((weak)); + void gen8_GetImageMemoryRequirements2(VkDevice device, const VkImageMemoryRequirementsInfo2* pInfo, VkMemoryRequirements2* pMemoryRequirements) __attribute__ ((weak)); + void gen8_GetImageSparseMemoryRequirements2(VkDevice device, const VkImageSparseMemoryRequirementsInfo2* pInfo, uint32_t* pSparseMemoryRequirementCount, VkSparseImageMemoryRequirements2* pSparseMemoryRequirements) __attribute__ ((weak)); + VkResult gen8_CreateSamplerYcbcrConversion(VkDevice device, const VkSamplerYcbcrConversionCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSamplerYcbcrConversion* pYcbcrConversion) __attribute__ ((weak)); + void gen8_DestroySamplerYcbcrConversion(VkDevice device, VkSamplerYcbcrConversion ycbcrConversion, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + void gen8_GetDeviceQueue2(VkDevice device, const VkDeviceQueueInfo2* pQueueInfo, VkQueue* pQueue) __attribute__ ((weak)); + void gen8_GetDescriptorSetLayoutSupport(VkDevice device, const VkDescriptorSetLayoutCreateInfo* pCreateInfo, VkDescriptorSetLayoutSupport* pSupport) __attribute__ ((weak)); + #ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult gen8_GetSwapchainGrallocUsageANDROID(VkDevice device, VkFormat format, VkImageUsageFlags imageUsage, int* grallocUsage) __attribute__ ((weak)); +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult gen8_AcquireImageANDROID(VkDevice device, VkImage image, int nativeFenceFd, VkSemaphore semaphore, VkFence fence) __attribute__ ((weak)); +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult gen8_QueueSignalReleaseImageANDROID(VkQueue queue, uint32_t waitSemaphoreCount, const VkSemaphore* pWaitSemaphores, VkImage image, int* pNativeFenceFd) __attribute__ ((weak)); +#endif // VK_USE_PLATFORM_ANDROID_KHR + VkResult gen8_GetCalibratedTimestampsEXT(VkDevice device, uint32_t timestampCount, const VkCalibratedTimestampInfoEXT* pTimestampInfos, uint64_t* pTimestamps, uint64_t* pMaxDeviation) __attribute__ ((weak)); + VkResult gen8_CreateRenderPass2KHR(VkDevice device, const VkRenderPassCreateInfo2KHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkRenderPass* pRenderPass) __attribute__ ((weak)); + void gen8_CmdBeginRenderPass2KHR(VkCommandBuffer commandBuffer, const VkRenderPassBeginInfo* pRenderPassBegin, const VkSubpassBeginInfoKHR* pSubpassBeginInfo) __attribute__ ((weak)); + void gen8_CmdNextSubpass2KHR(VkCommandBuffer commandBuffer, const VkSubpassBeginInfoKHR* pSubpassBeginInfo, const VkSubpassEndInfoKHR* pSubpassEndInfo) __attribute__ ((weak)); + void gen8_CmdEndRenderPass2KHR(VkCommandBuffer commandBuffer, const VkSubpassEndInfoKHR* pSubpassEndInfo) __attribute__ ((weak)); +#ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult gen8_GetAndroidHardwareBufferPropertiesANDROID(VkDevice device, const struct AHardwareBuffer* buffer, VkAndroidHardwareBufferPropertiesANDROID* pProperties) __attribute__ ((weak)); +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult gen8_GetMemoryAndroidHardwareBufferANDROID(VkDevice device, const VkMemoryGetAndroidHardwareBufferInfoANDROID* pInfo, struct AHardwareBuffer** pBuffer) __attribute__ ((weak)); +#endif // VK_USE_PLATFORM_ANDROID_KHR + void gen8_CmdDrawIndirectCountKHR(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkBuffer countBuffer, VkDeviceSize countBufferOffset, uint32_t maxDrawCount, uint32_t stride) __attribute__ ((weak)); + void gen8_CmdDrawIndexedIndirectCountKHR(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkBuffer countBuffer, VkDeviceSize countBufferOffset, uint32_t maxDrawCount, uint32_t stride) __attribute__ ((weak)); + void gen8_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer, uint32_t firstBinding, uint32_t bindingCount, const VkBuffer* pBuffers, const VkDeviceSize* pOffsets, const VkDeviceSize* pSizes) __attribute__ ((weak)); + void gen8_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstCounterBuffer, uint32_t counterBufferCount, const VkBuffer* pCounterBuffers, const VkDeviceSize* pCounterBufferOffsets) __attribute__ ((weak)); + void gen8_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstCounterBuffer, uint32_t counterBufferCount, const VkBuffer* pCounterBuffers, const VkDeviceSize* pCounterBufferOffsets) __attribute__ ((weak)); + void gen8_CmdBeginQueryIndexedEXT(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, VkQueryControlFlags flags, uint32_t index) __attribute__ ((weak)); + void gen8_CmdEndQueryIndexedEXT(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, uint32_t index) __attribute__ ((weak)); + void gen8_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer, uint32_t instanceCount, uint32_t firstInstance, VkBuffer counterBuffer, VkDeviceSize counterBufferOffset, uint32_t counterOffset, uint32_t vertexStride) __attribute__ ((weak)); + VkResult gen8_CreateDmaBufImageINTEL(VkDevice device, const VkDmaBufImageCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDeviceMemory* pMem, VkImage* pImage) __attribute__ ((weak)); + + const struct anv_device_dispatch_table gen8_device_dispatch_table = { + .vkGetDeviceProcAddr = gen8_GetDeviceProcAddr, + .vkDestroyDevice = gen8_DestroyDevice, + .vkGetDeviceQueue = gen8_GetDeviceQueue, + .vkQueueSubmit = gen8_QueueSubmit, + .vkQueueWaitIdle = gen8_QueueWaitIdle, + .vkDeviceWaitIdle = gen8_DeviceWaitIdle, + .vkAllocateMemory = gen8_AllocateMemory, + .vkFreeMemory = gen8_FreeMemory, + .vkMapMemory = gen8_MapMemory, + .vkUnmapMemory = gen8_UnmapMemory, + .vkFlushMappedMemoryRanges = gen8_FlushMappedMemoryRanges, + .vkInvalidateMappedMemoryRanges = gen8_InvalidateMappedMemoryRanges, + .vkGetDeviceMemoryCommitment = gen8_GetDeviceMemoryCommitment, + .vkGetBufferMemoryRequirements = gen8_GetBufferMemoryRequirements, + .vkBindBufferMemory = gen8_BindBufferMemory, + .vkGetImageMemoryRequirements = gen8_GetImageMemoryRequirements, + .vkBindImageMemory = gen8_BindImageMemory, + .vkGetImageSparseMemoryRequirements = gen8_GetImageSparseMemoryRequirements, + .vkQueueBindSparse = gen8_QueueBindSparse, + .vkCreateFence = gen8_CreateFence, + .vkDestroyFence = gen8_DestroyFence, + .vkResetFences = gen8_ResetFences, + .vkGetFenceStatus = gen8_GetFenceStatus, + .vkWaitForFences = gen8_WaitForFences, + .vkCreateSemaphore = gen8_CreateSemaphore, + .vkDestroySemaphore = gen8_DestroySemaphore, + .vkCreateEvent = gen8_CreateEvent, + .vkDestroyEvent = gen8_DestroyEvent, + .vkGetEventStatus = gen8_GetEventStatus, + .vkSetEvent = gen8_SetEvent, + .vkResetEvent = gen8_ResetEvent, + .vkCreateQueryPool = gen8_CreateQueryPool, + .vkDestroyQueryPool = gen8_DestroyQueryPool, + .vkGetQueryPoolResults = gen8_GetQueryPoolResults, + .vkCreateBuffer = gen8_CreateBuffer, + .vkDestroyBuffer = gen8_DestroyBuffer, + .vkCreateBufferView = gen8_CreateBufferView, + .vkDestroyBufferView = gen8_DestroyBufferView, + .vkCreateImage = gen8_CreateImage, + .vkDestroyImage = gen8_DestroyImage, + .vkGetImageSubresourceLayout = gen8_GetImageSubresourceLayout, + .vkCreateImageView = gen8_CreateImageView, + .vkDestroyImageView = gen8_DestroyImageView, + .vkCreateShaderModule = gen8_CreateShaderModule, + .vkDestroyShaderModule = gen8_DestroyShaderModule, + .vkCreatePipelineCache = gen8_CreatePipelineCache, + .vkDestroyPipelineCache = gen8_DestroyPipelineCache, + .vkGetPipelineCacheData = gen8_GetPipelineCacheData, + .vkMergePipelineCaches = gen8_MergePipelineCaches, + .vkCreateGraphicsPipelines = gen8_CreateGraphicsPipelines, + .vkCreateComputePipelines = gen8_CreateComputePipelines, + .vkDestroyPipeline = gen8_DestroyPipeline, + .vkCreatePipelineLayout = gen8_CreatePipelineLayout, + .vkDestroyPipelineLayout = gen8_DestroyPipelineLayout, + .vkCreateSampler = gen8_CreateSampler, + .vkDestroySampler = gen8_DestroySampler, + .vkCreateDescriptorSetLayout = gen8_CreateDescriptorSetLayout, + .vkDestroyDescriptorSetLayout = gen8_DestroyDescriptorSetLayout, + .vkCreateDescriptorPool = gen8_CreateDescriptorPool, + .vkDestroyDescriptorPool = gen8_DestroyDescriptorPool, + .vkResetDescriptorPool = gen8_ResetDescriptorPool, + .vkAllocateDescriptorSets = gen8_AllocateDescriptorSets, + .vkFreeDescriptorSets = gen8_FreeDescriptorSets, + .vkUpdateDescriptorSets = gen8_UpdateDescriptorSets, + .vkCreateFramebuffer = gen8_CreateFramebuffer, + .vkDestroyFramebuffer = gen8_DestroyFramebuffer, + .vkCreateRenderPass = gen8_CreateRenderPass, + .vkDestroyRenderPass = gen8_DestroyRenderPass, + .vkGetRenderAreaGranularity = gen8_GetRenderAreaGranularity, + .vkCreateCommandPool = gen8_CreateCommandPool, + .vkDestroyCommandPool = gen8_DestroyCommandPool, + .vkResetCommandPool = gen8_ResetCommandPool, + .vkAllocateCommandBuffers = gen8_AllocateCommandBuffers, + .vkFreeCommandBuffers = gen8_FreeCommandBuffers, + .vkBeginCommandBuffer = gen8_BeginCommandBuffer, + .vkEndCommandBuffer = gen8_EndCommandBuffer, + .vkResetCommandBuffer = gen8_ResetCommandBuffer, + .vkCmdBindPipeline = gen8_CmdBindPipeline, + .vkCmdSetViewport = gen8_CmdSetViewport, + .vkCmdSetScissor = gen8_CmdSetScissor, + .vkCmdSetLineWidth = gen8_CmdSetLineWidth, + .vkCmdSetDepthBias = gen8_CmdSetDepthBias, + .vkCmdSetBlendConstants = gen8_CmdSetBlendConstants, + .vkCmdSetDepthBounds = gen8_CmdSetDepthBounds, + .vkCmdSetStencilCompareMask = gen8_CmdSetStencilCompareMask, + .vkCmdSetStencilWriteMask = gen8_CmdSetStencilWriteMask, + .vkCmdSetStencilReference = gen8_CmdSetStencilReference, + .vkCmdBindDescriptorSets = gen8_CmdBindDescriptorSets, + .vkCmdBindIndexBuffer = gen8_CmdBindIndexBuffer, + .vkCmdBindVertexBuffers = gen8_CmdBindVertexBuffers, + .vkCmdDraw = gen8_CmdDraw, + .vkCmdDrawIndexed = gen8_CmdDrawIndexed, + .vkCmdDrawIndirect = gen8_CmdDrawIndirect, + .vkCmdDrawIndexedIndirect = gen8_CmdDrawIndexedIndirect, + .vkCmdDispatch = gen8_CmdDispatch, + .vkCmdDispatchIndirect = gen8_CmdDispatchIndirect, + .vkCmdCopyBuffer = gen8_CmdCopyBuffer, + .vkCmdCopyImage = gen8_CmdCopyImage, + .vkCmdBlitImage = gen8_CmdBlitImage, + .vkCmdCopyBufferToImage = gen8_CmdCopyBufferToImage, + .vkCmdCopyImageToBuffer = gen8_CmdCopyImageToBuffer, + .vkCmdUpdateBuffer = gen8_CmdUpdateBuffer, + .vkCmdFillBuffer = gen8_CmdFillBuffer, + .vkCmdClearColorImage = gen8_CmdClearColorImage, + .vkCmdClearDepthStencilImage = gen8_CmdClearDepthStencilImage, + .vkCmdClearAttachments = gen8_CmdClearAttachments, + .vkCmdResolveImage = gen8_CmdResolveImage, + .vkCmdSetEvent = gen8_CmdSetEvent, + .vkCmdResetEvent = gen8_CmdResetEvent, + .vkCmdWaitEvents = gen8_CmdWaitEvents, + .vkCmdPipelineBarrier = gen8_CmdPipelineBarrier, + .vkCmdBeginQuery = gen8_CmdBeginQuery, + .vkCmdEndQuery = gen8_CmdEndQuery, + .vkCmdBeginConditionalRenderingEXT = gen8_CmdBeginConditionalRenderingEXT, + .vkCmdEndConditionalRenderingEXT = gen8_CmdEndConditionalRenderingEXT, + .vkCmdResetQueryPool = gen8_CmdResetQueryPool, + .vkCmdWriteTimestamp = gen8_CmdWriteTimestamp, + .vkCmdCopyQueryPoolResults = gen8_CmdCopyQueryPoolResults, + .vkCmdPushConstants = gen8_CmdPushConstants, + .vkCmdBeginRenderPass = gen8_CmdBeginRenderPass, + .vkCmdNextSubpass = gen8_CmdNextSubpass, + .vkCmdEndRenderPass = gen8_CmdEndRenderPass, + .vkCmdExecuteCommands = gen8_CmdExecuteCommands, + .vkCreateSwapchainKHR = gen8_CreateSwapchainKHR, + .vkDestroySwapchainKHR = gen8_DestroySwapchainKHR, + .vkGetSwapchainImagesKHR = gen8_GetSwapchainImagesKHR, + .vkAcquireNextImageKHR = gen8_AcquireNextImageKHR, + .vkQueuePresentKHR = gen8_QueuePresentKHR, + .vkCmdPushDescriptorSetKHR = gen8_CmdPushDescriptorSetKHR, + .vkTrimCommandPool = gen8_TrimCommandPool, + .vkTrimCommandPoolKHR = gen8_TrimCommandPool, + .vkGetMemoryFdKHR = gen8_GetMemoryFdKHR, + .vkGetMemoryFdPropertiesKHR = gen8_GetMemoryFdPropertiesKHR, + .vkGetSemaphoreFdKHR = gen8_GetSemaphoreFdKHR, + .vkImportSemaphoreFdKHR = gen8_ImportSemaphoreFdKHR, + .vkGetFenceFdKHR = gen8_GetFenceFdKHR, + .vkImportFenceFdKHR = gen8_ImportFenceFdKHR, + .vkDisplayPowerControlEXT = gen8_DisplayPowerControlEXT, + .vkRegisterDeviceEventEXT = gen8_RegisterDeviceEventEXT, + .vkRegisterDisplayEventEXT = gen8_RegisterDisplayEventEXT, + .vkGetSwapchainCounterEXT = gen8_GetSwapchainCounterEXT, + .vkGetDeviceGroupPeerMemoryFeatures = gen8_GetDeviceGroupPeerMemoryFeatures, + .vkGetDeviceGroupPeerMemoryFeaturesKHR = gen8_GetDeviceGroupPeerMemoryFeatures, + .vkBindBufferMemory2 = gen8_BindBufferMemory2, + .vkBindBufferMemory2KHR = gen8_BindBufferMemory2, + .vkBindImageMemory2 = gen8_BindImageMemory2, + .vkBindImageMemory2KHR = gen8_BindImageMemory2, + .vkCmdSetDeviceMask = gen8_CmdSetDeviceMask, + .vkCmdSetDeviceMaskKHR = gen8_CmdSetDeviceMask, + .vkGetDeviceGroupPresentCapabilitiesKHR = gen8_GetDeviceGroupPresentCapabilitiesKHR, + .vkGetDeviceGroupSurfacePresentModesKHR = gen8_GetDeviceGroupSurfacePresentModesKHR, + .vkAcquireNextImage2KHR = gen8_AcquireNextImage2KHR, + .vkCmdDispatchBase = gen8_CmdDispatchBase, + .vkCmdDispatchBaseKHR = gen8_CmdDispatchBase, + .vkCreateDescriptorUpdateTemplate = gen8_CreateDescriptorUpdateTemplate, + .vkCreateDescriptorUpdateTemplateKHR = gen8_CreateDescriptorUpdateTemplate, + .vkDestroyDescriptorUpdateTemplate = gen8_DestroyDescriptorUpdateTemplate, + .vkDestroyDescriptorUpdateTemplateKHR = gen8_DestroyDescriptorUpdateTemplate, + .vkUpdateDescriptorSetWithTemplate = gen8_UpdateDescriptorSetWithTemplate, + .vkUpdateDescriptorSetWithTemplateKHR = gen8_UpdateDescriptorSetWithTemplate, + .vkCmdPushDescriptorSetWithTemplateKHR = gen8_CmdPushDescriptorSetWithTemplateKHR, + .vkGetBufferMemoryRequirements2 = gen8_GetBufferMemoryRequirements2, + .vkGetBufferMemoryRequirements2KHR = gen8_GetBufferMemoryRequirements2, + .vkGetImageMemoryRequirements2 = gen8_GetImageMemoryRequirements2, + .vkGetImageMemoryRequirements2KHR = gen8_GetImageMemoryRequirements2, + .vkGetImageSparseMemoryRequirements2 = gen8_GetImageSparseMemoryRequirements2, + .vkGetImageSparseMemoryRequirements2KHR = gen8_GetImageSparseMemoryRequirements2, + .vkCreateSamplerYcbcrConversion = gen8_CreateSamplerYcbcrConversion, + .vkCreateSamplerYcbcrConversionKHR = gen8_CreateSamplerYcbcrConversion, + .vkDestroySamplerYcbcrConversion = gen8_DestroySamplerYcbcrConversion, + .vkDestroySamplerYcbcrConversionKHR = gen8_DestroySamplerYcbcrConversion, + .vkGetDeviceQueue2 = gen8_GetDeviceQueue2, + .vkGetDescriptorSetLayoutSupport = gen8_GetDescriptorSetLayoutSupport, + .vkGetDescriptorSetLayoutSupportKHR = gen8_GetDescriptorSetLayoutSupport, +#ifdef VK_USE_PLATFORM_ANDROID_KHR + .vkGetSwapchainGrallocUsageANDROID = gen8_GetSwapchainGrallocUsageANDROID, +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + .vkAcquireImageANDROID = gen8_AcquireImageANDROID, +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + .vkQueueSignalReleaseImageANDROID = gen8_QueueSignalReleaseImageANDROID, +#endif // VK_USE_PLATFORM_ANDROID_KHR + .vkGetCalibratedTimestampsEXT = gen8_GetCalibratedTimestampsEXT, + .vkCreateRenderPass2KHR = gen8_CreateRenderPass2KHR, + .vkCmdBeginRenderPass2KHR = gen8_CmdBeginRenderPass2KHR, + .vkCmdNextSubpass2KHR = gen8_CmdNextSubpass2KHR, + .vkCmdEndRenderPass2KHR = gen8_CmdEndRenderPass2KHR, +#ifdef VK_USE_PLATFORM_ANDROID_KHR + .vkGetAndroidHardwareBufferPropertiesANDROID = gen8_GetAndroidHardwareBufferPropertiesANDROID, +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + .vkGetMemoryAndroidHardwareBufferANDROID = gen8_GetMemoryAndroidHardwareBufferANDROID, +#endif // VK_USE_PLATFORM_ANDROID_KHR + .vkCmdDrawIndirectCountKHR = gen8_CmdDrawIndirectCountKHR, + .vkCmdDrawIndexedIndirectCountKHR = gen8_CmdDrawIndexedIndirectCountKHR, + .vkCmdBindTransformFeedbackBuffersEXT = gen8_CmdBindTransformFeedbackBuffersEXT, + .vkCmdBeginTransformFeedbackEXT = gen8_CmdBeginTransformFeedbackEXT, + .vkCmdEndTransformFeedbackEXT = gen8_CmdEndTransformFeedbackEXT, + .vkCmdBeginQueryIndexedEXT = gen8_CmdBeginQueryIndexedEXT, + .vkCmdEndQueryIndexedEXT = gen8_CmdEndQueryIndexedEXT, + .vkCmdDrawIndirectByteCountEXT = gen8_CmdDrawIndirectByteCountEXT, + .vkCreateDmaBufImageINTEL = gen8_CreateDmaBufImageINTEL, + }; + PFN_vkVoidFunction gen9_GetDeviceProcAddr(VkDevice device, const char* pName) __attribute__ ((weak)); + void gen9_DestroyDevice(VkDevice device, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + void gen9_GetDeviceQueue(VkDevice device, uint32_t queueFamilyIndex, uint32_t queueIndex, VkQueue* pQueue) __attribute__ ((weak)); + VkResult gen9_QueueSubmit(VkQueue queue, uint32_t submitCount, const VkSubmitInfo* pSubmits, VkFence fence) __attribute__ ((weak)); + VkResult gen9_QueueWaitIdle(VkQueue queue) __attribute__ ((weak)); + VkResult gen9_DeviceWaitIdle(VkDevice device) __attribute__ ((weak)); + VkResult gen9_AllocateMemory(VkDevice device, const VkMemoryAllocateInfo* pAllocateInfo, const VkAllocationCallbacks* pAllocator, VkDeviceMemory* pMemory) __attribute__ ((weak)); + void gen9_FreeMemory(VkDevice device, VkDeviceMemory memory, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen9_MapMemory(VkDevice device, VkDeviceMemory memory, VkDeviceSize offset, VkDeviceSize size, VkMemoryMapFlags flags, void** ppData) __attribute__ ((weak)); + void gen9_UnmapMemory(VkDevice device, VkDeviceMemory memory) __attribute__ ((weak)); + VkResult gen9_FlushMappedMemoryRanges(VkDevice device, uint32_t memoryRangeCount, const VkMappedMemoryRange* pMemoryRanges) __attribute__ ((weak)); + VkResult gen9_InvalidateMappedMemoryRanges(VkDevice device, uint32_t memoryRangeCount, const VkMappedMemoryRange* pMemoryRanges) __attribute__ ((weak)); + void gen9_GetDeviceMemoryCommitment(VkDevice device, VkDeviceMemory memory, VkDeviceSize* pCommittedMemoryInBytes) __attribute__ ((weak)); + void gen9_GetBufferMemoryRequirements(VkDevice device, VkBuffer buffer, VkMemoryRequirements* pMemoryRequirements) __attribute__ ((weak)); + VkResult gen9_BindBufferMemory(VkDevice device, VkBuffer buffer, VkDeviceMemory memory, VkDeviceSize memoryOffset) __attribute__ ((weak)); + void gen9_GetImageMemoryRequirements(VkDevice device, VkImage image, VkMemoryRequirements* pMemoryRequirements) __attribute__ ((weak)); + VkResult gen9_BindImageMemory(VkDevice device, VkImage image, VkDeviceMemory memory, VkDeviceSize memoryOffset) __attribute__ ((weak)); + void gen9_GetImageSparseMemoryRequirements(VkDevice device, VkImage image, uint32_t* pSparseMemoryRequirementCount, VkSparseImageMemoryRequirements* pSparseMemoryRequirements) __attribute__ ((weak)); + VkResult gen9_QueueBindSparse(VkQueue queue, uint32_t bindInfoCount, const VkBindSparseInfo* pBindInfo, VkFence fence) __attribute__ ((weak)); + VkResult gen9_CreateFence(VkDevice device, const VkFenceCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence) __attribute__ ((weak)); + void gen9_DestroyFence(VkDevice device, VkFence fence, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen9_ResetFences(VkDevice device, uint32_t fenceCount, const VkFence* pFences) __attribute__ ((weak)); + VkResult gen9_GetFenceStatus(VkDevice device, VkFence fence) __attribute__ ((weak)); + VkResult gen9_WaitForFences(VkDevice device, uint32_t fenceCount, const VkFence* pFences, VkBool32 waitAll, uint64_t timeout) __attribute__ ((weak)); + VkResult gen9_CreateSemaphore(VkDevice device, const VkSemaphoreCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSemaphore* pSemaphore) __attribute__ ((weak)); + void gen9_DestroySemaphore(VkDevice device, VkSemaphore semaphore, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen9_CreateEvent(VkDevice device, const VkEventCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkEvent* pEvent) __attribute__ ((weak)); + void gen9_DestroyEvent(VkDevice device, VkEvent event, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen9_GetEventStatus(VkDevice device, VkEvent event) __attribute__ ((weak)); + VkResult gen9_SetEvent(VkDevice device, VkEvent event) __attribute__ ((weak)); + VkResult gen9_ResetEvent(VkDevice device, VkEvent event) __attribute__ ((weak)); + VkResult gen9_CreateQueryPool(VkDevice device, const VkQueryPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkQueryPool* pQueryPool) __attribute__ ((weak)); + void gen9_DestroyQueryPool(VkDevice device, VkQueryPool queryPool, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen9_GetQueryPoolResults(VkDevice device, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount, size_t dataSize, void* pData, VkDeviceSize stride, VkQueryResultFlags flags) __attribute__ ((weak)); + VkResult gen9_CreateBuffer(VkDevice device, const VkBufferCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkBuffer* pBuffer) __attribute__ ((weak)); + void gen9_DestroyBuffer(VkDevice device, VkBuffer buffer, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen9_CreateBufferView(VkDevice device, const VkBufferViewCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkBufferView* pView) __attribute__ ((weak)); + void gen9_DestroyBufferView(VkDevice device, VkBufferView bufferView, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen9_CreateImage(VkDevice device, const VkImageCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkImage* pImage) __attribute__ ((weak)); + void gen9_DestroyImage(VkDevice device, VkImage image, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + void gen9_GetImageSubresourceLayout(VkDevice device, VkImage image, const VkImageSubresource* pSubresource, VkSubresourceLayout* pLayout) __attribute__ ((weak)); + VkResult gen9_CreateImageView(VkDevice device, const VkImageViewCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkImageView* pView) __attribute__ ((weak)); + void gen9_DestroyImageView(VkDevice device, VkImageView imageView, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen9_CreateShaderModule(VkDevice device, const VkShaderModuleCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkShaderModule* pShaderModule) __attribute__ ((weak)); + void gen9_DestroyShaderModule(VkDevice device, VkShaderModule shaderModule, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen9_CreatePipelineCache(VkDevice device, const VkPipelineCacheCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkPipelineCache* pPipelineCache) __attribute__ ((weak)); + void gen9_DestroyPipelineCache(VkDevice device, VkPipelineCache pipelineCache, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen9_GetPipelineCacheData(VkDevice device, VkPipelineCache pipelineCache, size_t* pDataSize, void* pData) __attribute__ ((weak)); + VkResult gen9_MergePipelineCaches(VkDevice device, VkPipelineCache dstCache, uint32_t srcCacheCount, const VkPipelineCache* pSrcCaches) __attribute__ ((weak)); + VkResult gen9_CreateGraphicsPipelines(VkDevice device, VkPipelineCache pipelineCache, uint32_t createInfoCount, const VkGraphicsPipelineCreateInfo* pCreateInfos, const VkAllocationCallbacks* pAllocator, VkPipeline* pPipelines) __attribute__ ((weak)); + VkResult gen9_CreateComputePipelines(VkDevice device, VkPipelineCache pipelineCache, uint32_t createInfoCount, const VkComputePipelineCreateInfo* pCreateInfos, const VkAllocationCallbacks* pAllocator, VkPipeline* pPipelines) __attribute__ ((weak)); + void gen9_DestroyPipeline(VkDevice device, VkPipeline pipeline, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen9_CreatePipelineLayout(VkDevice device, const VkPipelineLayoutCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkPipelineLayout* pPipelineLayout) __attribute__ ((weak)); + void gen9_DestroyPipelineLayout(VkDevice device, VkPipelineLayout pipelineLayout, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen9_CreateSampler(VkDevice device, const VkSamplerCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSampler* pSampler) __attribute__ ((weak)); + void gen9_DestroySampler(VkDevice device, VkSampler sampler, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen9_CreateDescriptorSetLayout(VkDevice device, const VkDescriptorSetLayoutCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorSetLayout* pSetLayout) __attribute__ ((weak)); + void gen9_DestroyDescriptorSetLayout(VkDevice device, VkDescriptorSetLayout descriptorSetLayout, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen9_CreateDescriptorPool(VkDevice device, const VkDescriptorPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorPool* pDescriptorPool) __attribute__ ((weak)); + void gen9_DestroyDescriptorPool(VkDevice device, VkDescriptorPool descriptorPool, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen9_ResetDescriptorPool(VkDevice device, VkDescriptorPool descriptorPool, VkDescriptorPoolResetFlags flags) __attribute__ ((weak)); + VkResult gen9_AllocateDescriptorSets(VkDevice device, const VkDescriptorSetAllocateInfo* pAllocateInfo, VkDescriptorSet* pDescriptorSets) __attribute__ ((weak)); + VkResult gen9_FreeDescriptorSets(VkDevice device, VkDescriptorPool descriptorPool, uint32_t descriptorSetCount, const VkDescriptorSet* pDescriptorSets) __attribute__ ((weak)); + void gen9_UpdateDescriptorSets(VkDevice device, uint32_t descriptorWriteCount, const VkWriteDescriptorSet* pDescriptorWrites, uint32_t descriptorCopyCount, const VkCopyDescriptorSet* pDescriptorCopies) __attribute__ ((weak)); + VkResult gen9_CreateFramebuffer(VkDevice device, const VkFramebufferCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkFramebuffer* pFramebuffer) __attribute__ ((weak)); + void gen9_DestroyFramebuffer(VkDevice device, VkFramebuffer framebuffer, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen9_CreateRenderPass(VkDevice device, const VkRenderPassCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkRenderPass* pRenderPass) __attribute__ ((weak)); + void gen9_DestroyRenderPass(VkDevice device, VkRenderPass renderPass, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + void gen9_GetRenderAreaGranularity(VkDevice device, VkRenderPass renderPass, VkExtent2D* pGranularity) __attribute__ ((weak)); + VkResult gen9_CreateCommandPool(VkDevice device, const VkCommandPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkCommandPool* pCommandPool) __attribute__ ((weak)); + void gen9_DestroyCommandPool(VkDevice device, VkCommandPool commandPool, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen9_ResetCommandPool(VkDevice device, VkCommandPool commandPool, VkCommandPoolResetFlags flags) __attribute__ ((weak)); + VkResult gen9_AllocateCommandBuffers(VkDevice device, const VkCommandBufferAllocateInfo* pAllocateInfo, VkCommandBuffer* pCommandBuffers) __attribute__ ((weak)); + void gen9_FreeCommandBuffers(VkDevice device, VkCommandPool commandPool, uint32_t commandBufferCount, const VkCommandBuffer* pCommandBuffers) __attribute__ ((weak)); + VkResult gen9_BeginCommandBuffer(VkCommandBuffer commandBuffer, const VkCommandBufferBeginInfo* pBeginInfo) __attribute__ ((weak)); + VkResult gen9_EndCommandBuffer(VkCommandBuffer commandBuffer) __attribute__ ((weak)); + VkResult gen9_ResetCommandBuffer(VkCommandBuffer commandBuffer, VkCommandBufferResetFlags flags) __attribute__ ((weak)); + void gen9_CmdBindPipeline(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipeline pipeline) __attribute__ ((weak)); + void gen9_CmdSetViewport(VkCommandBuffer commandBuffer, uint32_t firstViewport, uint32_t viewportCount, const VkViewport* pViewports) __attribute__ ((weak)); + void gen9_CmdSetScissor(VkCommandBuffer commandBuffer, uint32_t firstScissor, uint32_t scissorCount, const VkRect2D* pScissors) __attribute__ ((weak)); + void gen9_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth) __attribute__ ((weak)); + void gen9_CmdSetDepthBias(VkCommandBuffer commandBuffer, float depthBiasConstantFactor, float depthBiasClamp, float depthBiasSlopeFactor) __attribute__ ((weak)); + void gen9_CmdSetBlendConstants(VkCommandBuffer commandBuffer, const float blendConstants[4]) __attribute__ ((weak)); + void gen9_CmdSetDepthBounds(VkCommandBuffer commandBuffer, float minDepthBounds, float maxDepthBounds) __attribute__ ((weak)); + void gen9_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t compareMask) __attribute__ ((weak)); + void gen9_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t writeMask) __attribute__ ((weak)); + void gen9_CmdSetStencilReference(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t reference) __attribute__ ((weak)); + void gen9_CmdBindDescriptorSets(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipelineLayout layout, uint32_t firstSet, uint32_t descriptorSetCount, const VkDescriptorSet* pDescriptorSets, uint32_t dynamicOffsetCount, const uint32_t* pDynamicOffsets) __attribute__ ((weak)); + void gen9_CmdBindIndexBuffer(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkIndexType indexType) __attribute__ ((weak)); + void gen9_CmdBindVertexBuffers(VkCommandBuffer commandBuffer, uint32_t firstBinding, uint32_t bindingCount, const VkBuffer* pBuffers, const VkDeviceSize* pOffsets) __attribute__ ((weak)); + void gen9_CmdDraw(VkCommandBuffer commandBuffer, uint32_t vertexCount, uint32_t instanceCount, uint32_t firstVertex, uint32_t firstInstance) __attribute__ ((weak)); + void gen9_CmdDrawIndexed(VkCommandBuffer commandBuffer, uint32_t indexCount, uint32_t instanceCount, uint32_t firstIndex, int32_t vertexOffset, uint32_t firstInstance) __attribute__ ((weak)); + void gen9_CmdDrawIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, uint32_t drawCount, uint32_t stride) __attribute__ ((weak)); + void gen9_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, uint32_t drawCount, uint32_t stride) __attribute__ ((weak)); + void gen9_CmdDispatch(VkCommandBuffer commandBuffer, uint32_t groupCountX, uint32_t groupCountY, uint32_t groupCountZ) __attribute__ ((weak)); + void gen9_CmdDispatchIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset) __attribute__ ((weak)); + void gen9_CmdCopyBuffer(VkCommandBuffer commandBuffer, VkBuffer srcBuffer, VkBuffer dstBuffer, uint32_t regionCount, const VkBufferCopy* pRegions) __attribute__ ((weak)); + void gen9_CmdCopyImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageCopy* pRegions) __attribute__ ((weak)); + void gen9_CmdBlitImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageBlit* pRegions, VkFilter filter) __attribute__ ((weak)); + void gen9_CmdCopyBufferToImage(VkCommandBuffer commandBuffer, VkBuffer srcBuffer, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkBufferImageCopy* pRegions) __attribute__ ((weak)); + void gen9_CmdCopyImageToBuffer(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkBuffer dstBuffer, uint32_t regionCount, const VkBufferImageCopy* pRegions) __attribute__ ((weak)); + void gen9_CmdUpdateBuffer(VkCommandBuffer commandBuffer, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize dataSize, const void* pData) __attribute__ ((weak)); + void gen9_CmdFillBuffer(VkCommandBuffer commandBuffer, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize size, uint32_t data) __attribute__ ((weak)); + void gen9_CmdClearColorImage(VkCommandBuffer commandBuffer, VkImage image, VkImageLayout imageLayout, const VkClearColorValue* pColor, uint32_t rangeCount, const VkImageSubresourceRange* pRanges) __attribute__ ((weak)); + void gen9_CmdClearDepthStencilImage(VkCommandBuffer commandBuffer, VkImage image, VkImageLayout imageLayout, const VkClearDepthStencilValue* pDepthStencil, uint32_t rangeCount, const VkImageSubresourceRange* pRanges) __attribute__ ((weak)); + void gen9_CmdClearAttachments(VkCommandBuffer commandBuffer, uint32_t attachmentCount, const VkClearAttachment* pAttachments, uint32_t rectCount, const VkClearRect* pRects) __attribute__ ((weak)); + void gen9_CmdResolveImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageResolve* pRegions) __attribute__ ((weak)); + void gen9_CmdSetEvent(VkCommandBuffer commandBuffer, VkEvent event, VkPipelineStageFlags stageMask) __attribute__ ((weak)); + void gen9_CmdResetEvent(VkCommandBuffer commandBuffer, VkEvent event, VkPipelineStageFlags stageMask) __attribute__ ((weak)); + void gen9_CmdWaitEvents(VkCommandBuffer commandBuffer, uint32_t eventCount, const VkEvent* pEvents, VkPipelineStageFlags srcStageMask, VkPipelineStageFlags dstStageMask, uint32_t memoryBarrierCount, const VkMemoryBarrier* pMemoryBarriers, uint32_t bufferMemoryBarrierCount, const VkBufferMemoryBarrier* pBufferMemoryBarriers, uint32_t imageMemoryBarrierCount, const VkImageMemoryBarrier* pImageMemoryBarriers) __attribute__ ((weak)); + void gen9_CmdPipelineBarrier(VkCommandBuffer commandBuffer, VkPipelineStageFlags srcStageMask, VkPipelineStageFlags dstStageMask, VkDependencyFlags dependencyFlags, uint32_t memoryBarrierCount, const VkMemoryBarrier* pMemoryBarriers, uint32_t bufferMemoryBarrierCount, const VkBufferMemoryBarrier* pBufferMemoryBarriers, uint32_t imageMemoryBarrierCount, const VkImageMemoryBarrier* pImageMemoryBarriers) __attribute__ ((weak)); + void gen9_CmdBeginQuery(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, VkQueryControlFlags flags) __attribute__ ((weak)); + void gen9_CmdEndQuery(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query) __attribute__ ((weak)); + void gen9_CmdBeginConditionalRenderingEXT(VkCommandBuffer commandBuffer, const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin) __attribute__ ((weak)); + void gen9_CmdEndConditionalRenderingEXT(VkCommandBuffer commandBuffer) __attribute__ ((weak)); + void gen9_CmdResetQueryPool(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount) __attribute__ ((weak)); + void gen9_CmdWriteTimestamp(VkCommandBuffer commandBuffer, VkPipelineStageFlagBits pipelineStage, VkQueryPool queryPool, uint32_t query) __attribute__ ((weak)); + void gen9_CmdCopyQueryPoolResults(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize stride, VkQueryResultFlags flags) __attribute__ ((weak)); + void gen9_CmdPushConstants(VkCommandBuffer commandBuffer, VkPipelineLayout layout, VkShaderStageFlags stageFlags, uint32_t offset, uint32_t size, const void* pValues) __attribute__ ((weak)); + void gen9_CmdBeginRenderPass(VkCommandBuffer commandBuffer, const VkRenderPassBeginInfo* pRenderPassBegin, VkSubpassContents contents) __attribute__ ((weak)); + void gen9_CmdNextSubpass(VkCommandBuffer commandBuffer, VkSubpassContents contents) __attribute__ ((weak)); + void gen9_CmdEndRenderPass(VkCommandBuffer commandBuffer) __attribute__ ((weak)); + void gen9_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCount, const VkCommandBuffer* pCommandBuffers) __attribute__ ((weak)); + VkResult gen9_CreateSwapchainKHR(VkDevice device, const VkSwapchainCreateInfoKHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSwapchainKHR* pSwapchain) __attribute__ ((weak)); + void gen9_DestroySwapchainKHR(VkDevice device, VkSwapchainKHR swapchain, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen9_GetSwapchainImagesKHR(VkDevice device, VkSwapchainKHR swapchain, uint32_t* pSwapchainImageCount, VkImage* pSwapchainImages) __attribute__ ((weak)); + VkResult gen9_AcquireNextImageKHR(VkDevice device, VkSwapchainKHR swapchain, uint64_t timeout, VkSemaphore semaphore, VkFence fence, uint32_t* pImageIndex) __attribute__ ((weak)); + VkResult gen9_QueuePresentKHR(VkQueue queue, const VkPresentInfoKHR* pPresentInfo) __attribute__ ((weak)); + void gen9_CmdPushDescriptorSetKHR(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipelineLayout layout, uint32_t set, uint32_t descriptorWriteCount, const VkWriteDescriptorSet* pDescriptorWrites) __attribute__ ((weak)); + void gen9_TrimCommandPool(VkDevice device, VkCommandPool commandPool, VkCommandPoolTrimFlags flags) __attribute__ ((weak)); + VkResult gen9_GetMemoryFdKHR(VkDevice device, const VkMemoryGetFdInfoKHR* pGetFdInfo, int* pFd) __attribute__ ((weak)); + VkResult gen9_GetMemoryFdPropertiesKHR(VkDevice device, VkExternalMemoryHandleTypeFlagBits handleType, int fd, VkMemoryFdPropertiesKHR* pMemoryFdProperties) __attribute__ ((weak)); + VkResult gen9_GetSemaphoreFdKHR(VkDevice device, const VkSemaphoreGetFdInfoKHR* pGetFdInfo, int* pFd) __attribute__ ((weak)); + VkResult gen9_ImportSemaphoreFdKHR(VkDevice device, const VkImportSemaphoreFdInfoKHR* pImportSemaphoreFdInfo) __attribute__ ((weak)); + VkResult gen9_GetFenceFdKHR(VkDevice device, const VkFenceGetFdInfoKHR* pGetFdInfo, int* pFd) __attribute__ ((weak)); + VkResult gen9_ImportFenceFdKHR(VkDevice device, const VkImportFenceFdInfoKHR* pImportFenceFdInfo) __attribute__ ((weak)); + VkResult gen9_DisplayPowerControlEXT(VkDevice device, VkDisplayKHR display, const VkDisplayPowerInfoEXT* pDisplayPowerInfo) __attribute__ ((weak)); + VkResult gen9_RegisterDeviceEventEXT(VkDevice device, const VkDeviceEventInfoEXT* pDeviceEventInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence) __attribute__ ((weak)); + VkResult gen9_RegisterDisplayEventEXT(VkDevice device, VkDisplayKHR display, const VkDisplayEventInfoEXT* pDisplayEventInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence) __attribute__ ((weak)); + VkResult gen9_GetSwapchainCounterEXT(VkDevice device, VkSwapchainKHR swapchain, VkSurfaceCounterFlagBitsEXT counter, uint64_t* pCounterValue) __attribute__ ((weak)); + void gen9_GetDeviceGroupPeerMemoryFeatures(VkDevice device, uint32_t heapIndex, uint32_t localDeviceIndex, uint32_t remoteDeviceIndex, VkPeerMemoryFeatureFlags* pPeerMemoryFeatures) __attribute__ ((weak)); + VkResult gen9_BindBufferMemory2(VkDevice device, uint32_t bindInfoCount, const VkBindBufferMemoryInfo* pBindInfos) __attribute__ ((weak)); + VkResult gen9_BindImageMemory2(VkDevice device, uint32_t bindInfoCount, const VkBindImageMemoryInfo* pBindInfos) __attribute__ ((weak)); + void gen9_CmdSetDeviceMask(VkCommandBuffer commandBuffer, uint32_t deviceMask) __attribute__ ((weak)); + VkResult gen9_GetDeviceGroupPresentCapabilitiesKHR(VkDevice device, VkDeviceGroupPresentCapabilitiesKHR* pDeviceGroupPresentCapabilities) __attribute__ ((weak)); + VkResult gen9_GetDeviceGroupSurfacePresentModesKHR(VkDevice device, VkSurfaceKHR surface, VkDeviceGroupPresentModeFlagsKHR* pModes) __attribute__ ((weak)); + VkResult gen9_AcquireNextImage2KHR(VkDevice device, const VkAcquireNextImageInfoKHR* pAcquireInfo, uint32_t* pImageIndex) __attribute__ ((weak)); + void gen9_CmdDispatchBase(VkCommandBuffer commandBuffer, uint32_t baseGroupX, uint32_t baseGroupY, uint32_t baseGroupZ, uint32_t groupCountX, uint32_t groupCountY, uint32_t groupCountZ) __attribute__ ((weak)); + VkResult gen9_CreateDescriptorUpdateTemplate(VkDevice device, const VkDescriptorUpdateTemplateCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorUpdateTemplate* pDescriptorUpdateTemplate) __attribute__ ((weak)); + void gen9_DestroyDescriptorUpdateTemplate(VkDevice device, VkDescriptorUpdateTemplate descriptorUpdateTemplate, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + void gen9_UpdateDescriptorSetWithTemplate(VkDevice device, VkDescriptorSet descriptorSet, VkDescriptorUpdateTemplate descriptorUpdateTemplate, const void* pData) __attribute__ ((weak)); + void gen9_CmdPushDescriptorSetWithTemplateKHR(VkCommandBuffer commandBuffer, VkDescriptorUpdateTemplate descriptorUpdateTemplate, VkPipelineLayout layout, uint32_t set, const void* pData) __attribute__ ((weak)); + void gen9_GetBufferMemoryRequirements2(VkDevice device, const VkBufferMemoryRequirementsInfo2* pInfo, VkMemoryRequirements2* pMemoryRequirements) __attribute__ ((weak)); + void gen9_GetImageMemoryRequirements2(VkDevice device, const VkImageMemoryRequirementsInfo2* pInfo, VkMemoryRequirements2* pMemoryRequirements) __attribute__ ((weak)); + void gen9_GetImageSparseMemoryRequirements2(VkDevice device, const VkImageSparseMemoryRequirementsInfo2* pInfo, uint32_t* pSparseMemoryRequirementCount, VkSparseImageMemoryRequirements2* pSparseMemoryRequirements) __attribute__ ((weak)); + VkResult gen9_CreateSamplerYcbcrConversion(VkDevice device, const VkSamplerYcbcrConversionCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSamplerYcbcrConversion* pYcbcrConversion) __attribute__ ((weak)); + void gen9_DestroySamplerYcbcrConversion(VkDevice device, VkSamplerYcbcrConversion ycbcrConversion, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + void gen9_GetDeviceQueue2(VkDevice device, const VkDeviceQueueInfo2* pQueueInfo, VkQueue* pQueue) __attribute__ ((weak)); + void gen9_GetDescriptorSetLayoutSupport(VkDevice device, const VkDescriptorSetLayoutCreateInfo* pCreateInfo, VkDescriptorSetLayoutSupport* pSupport) __attribute__ ((weak)); + #ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult gen9_GetSwapchainGrallocUsageANDROID(VkDevice device, VkFormat format, VkImageUsageFlags imageUsage, int* grallocUsage) __attribute__ ((weak)); +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult gen9_AcquireImageANDROID(VkDevice device, VkImage image, int nativeFenceFd, VkSemaphore semaphore, VkFence fence) __attribute__ ((weak)); +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult gen9_QueueSignalReleaseImageANDROID(VkQueue queue, uint32_t waitSemaphoreCount, const VkSemaphore* pWaitSemaphores, VkImage image, int* pNativeFenceFd) __attribute__ ((weak)); +#endif // VK_USE_PLATFORM_ANDROID_KHR + VkResult gen9_GetCalibratedTimestampsEXT(VkDevice device, uint32_t timestampCount, const VkCalibratedTimestampInfoEXT* pTimestampInfos, uint64_t* pTimestamps, uint64_t* pMaxDeviation) __attribute__ ((weak)); + VkResult gen9_CreateRenderPass2KHR(VkDevice device, const VkRenderPassCreateInfo2KHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkRenderPass* pRenderPass) __attribute__ ((weak)); + void gen9_CmdBeginRenderPass2KHR(VkCommandBuffer commandBuffer, const VkRenderPassBeginInfo* pRenderPassBegin, const VkSubpassBeginInfoKHR* pSubpassBeginInfo) __attribute__ ((weak)); + void gen9_CmdNextSubpass2KHR(VkCommandBuffer commandBuffer, const VkSubpassBeginInfoKHR* pSubpassBeginInfo, const VkSubpassEndInfoKHR* pSubpassEndInfo) __attribute__ ((weak)); + void gen9_CmdEndRenderPass2KHR(VkCommandBuffer commandBuffer, const VkSubpassEndInfoKHR* pSubpassEndInfo) __attribute__ ((weak)); +#ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult gen9_GetAndroidHardwareBufferPropertiesANDROID(VkDevice device, const struct AHardwareBuffer* buffer, VkAndroidHardwareBufferPropertiesANDROID* pProperties) __attribute__ ((weak)); +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult gen9_GetMemoryAndroidHardwareBufferANDROID(VkDevice device, const VkMemoryGetAndroidHardwareBufferInfoANDROID* pInfo, struct AHardwareBuffer** pBuffer) __attribute__ ((weak)); +#endif // VK_USE_PLATFORM_ANDROID_KHR + void gen9_CmdDrawIndirectCountKHR(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkBuffer countBuffer, VkDeviceSize countBufferOffset, uint32_t maxDrawCount, uint32_t stride) __attribute__ ((weak)); + void gen9_CmdDrawIndexedIndirectCountKHR(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkBuffer countBuffer, VkDeviceSize countBufferOffset, uint32_t maxDrawCount, uint32_t stride) __attribute__ ((weak)); + void gen9_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer, uint32_t firstBinding, uint32_t bindingCount, const VkBuffer* pBuffers, const VkDeviceSize* pOffsets, const VkDeviceSize* pSizes) __attribute__ ((weak)); + void gen9_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstCounterBuffer, uint32_t counterBufferCount, const VkBuffer* pCounterBuffers, const VkDeviceSize* pCounterBufferOffsets) __attribute__ ((weak)); + void gen9_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstCounterBuffer, uint32_t counterBufferCount, const VkBuffer* pCounterBuffers, const VkDeviceSize* pCounterBufferOffsets) __attribute__ ((weak)); + void gen9_CmdBeginQueryIndexedEXT(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, VkQueryControlFlags flags, uint32_t index) __attribute__ ((weak)); + void gen9_CmdEndQueryIndexedEXT(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, uint32_t index) __attribute__ ((weak)); + void gen9_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer, uint32_t instanceCount, uint32_t firstInstance, VkBuffer counterBuffer, VkDeviceSize counterBufferOffset, uint32_t counterOffset, uint32_t vertexStride) __attribute__ ((weak)); + VkResult gen9_CreateDmaBufImageINTEL(VkDevice device, const VkDmaBufImageCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDeviceMemory* pMem, VkImage* pImage) __attribute__ ((weak)); + + const struct anv_device_dispatch_table gen9_device_dispatch_table = { + .vkGetDeviceProcAddr = gen9_GetDeviceProcAddr, + .vkDestroyDevice = gen9_DestroyDevice, + .vkGetDeviceQueue = gen9_GetDeviceQueue, + .vkQueueSubmit = gen9_QueueSubmit, + .vkQueueWaitIdle = gen9_QueueWaitIdle, + .vkDeviceWaitIdle = gen9_DeviceWaitIdle, + .vkAllocateMemory = gen9_AllocateMemory, + .vkFreeMemory = gen9_FreeMemory, + .vkMapMemory = gen9_MapMemory, + .vkUnmapMemory = gen9_UnmapMemory, + .vkFlushMappedMemoryRanges = gen9_FlushMappedMemoryRanges, + .vkInvalidateMappedMemoryRanges = gen9_InvalidateMappedMemoryRanges, + .vkGetDeviceMemoryCommitment = gen9_GetDeviceMemoryCommitment, + .vkGetBufferMemoryRequirements = gen9_GetBufferMemoryRequirements, + .vkBindBufferMemory = gen9_BindBufferMemory, + .vkGetImageMemoryRequirements = gen9_GetImageMemoryRequirements, + .vkBindImageMemory = gen9_BindImageMemory, + .vkGetImageSparseMemoryRequirements = gen9_GetImageSparseMemoryRequirements, + .vkQueueBindSparse = gen9_QueueBindSparse, + .vkCreateFence = gen9_CreateFence, + .vkDestroyFence = gen9_DestroyFence, + .vkResetFences = gen9_ResetFences, + .vkGetFenceStatus = gen9_GetFenceStatus, + .vkWaitForFences = gen9_WaitForFences, + .vkCreateSemaphore = gen9_CreateSemaphore, + .vkDestroySemaphore = gen9_DestroySemaphore, + .vkCreateEvent = gen9_CreateEvent, + .vkDestroyEvent = gen9_DestroyEvent, + .vkGetEventStatus = gen9_GetEventStatus, + .vkSetEvent = gen9_SetEvent, + .vkResetEvent = gen9_ResetEvent, + .vkCreateQueryPool = gen9_CreateQueryPool, + .vkDestroyQueryPool = gen9_DestroyQueryPool, + .vkGetQueryPoolResults = gen9_GetQueryPoolResults, + .vkCreateBuffer = gen9_CreateBuffer, + .vkDestroyBuffer = gen9_DestroyBuffer, + .vkCreateBufferView = gen9_CreateBufferView, + .vkDestroyBufferView = gen9_DestroyBufferView, + .vkCreateImage = gen9_CreateImage, + .vkDestroyImage = gen9_DestroyImage, + .vkGetImageSubresourceLayout = gen9_GetImageSubresourceLayout, + .vkCreateImageView = gen9_CreateImageView, + .vkDestroyImageView = gen9_DestroyImageView, + .vkCreateShaderModule = gen9_CreateShaderModule, + .vkDestroyShaderModule = gen9_DestroyShaderModule, + .vkCreatePipelineCache = gen9_CreatePipelineCache, + .vkDestroyPipelineCache = gen9_DestroyPipelineCache, + .vkGetPipelineCacheData = gen9_GetPipelineCacheData, + .vkMergePipelineCaches = gen9_MergePipelineCaches, + .vkCreateGraphicsPipelines = gen9_CreateGraphicsPipelines, + .vkCreateComputePipelines = gen9_CreateComputePipelines, + .vkDestroyPipeline = gen9_DestroyPipeline, + .vkCreatePipelineLayout = gen9_CreatePipelineLayout, + .vkDestroyPipelineLayout = gen9_DestroyPipelineLayout, + .vkCreateSampler = gen9_CreateSampler, + .vkDestroySampler = gen9_DestroySampler, + .vkCreateDescriptorSetLayout = gen9_CreateDescriptorSetLayout, + .vkDestroyDescriptorSetLayout = gen9_DestroyDescriptorSetLayout, + .vkCreateDescriptorPool = gen9_CreateDescriptorPool, + .vkDestroyDescriptorPool = gen9_DestroyDescriptorPool, + .vkResetDescriptorPool = gen9_ResetDescriptorPool, + .vkAllocateDescriptorSets = gen9_AllocateDescriptorSets, + .vkFreeDescriptorSets = gen9_FreeDescriptorSets, + .vkUpdateDescriptorSets = gen9_UpdateDescriptorSets, + .vkCreateFramebuffer = gen9_CreateFramebuffer, + .vkDestroyFramebuffer = gen9_DestroyFramebuffer, + .vkCreateRenderPass = gen9_CreateRenderPass, + .vkDestroyRenderPass = gen9_DestroyRenderPass, + .vkGetRenderAreaGranularity = gen9_GetRenderAreaGranularity, + .vkCreateCommandPool = gen9_CreateCommandPool, + .vkDestroyCommandPool = gen9_DestroyCommandPool, + .vkResetCommandPool = gen9_ResetCommandPool, + .vkAllocateCommandBuffers = gen9_AllocateCommandBuffers, + .vkFreeCommandBuffers = gen9_FreeCommandBuffers, + .vkBeginCommandBuffer = gen9_BeginCommandBuffer, + .vkEndCommandBuffer = gen9_EndCommandBuffer, + .vkResetCommandBuffer = gen9_ResetCommandBuffer, + .vkCmdBindPipeline = gen9_CmdBindPipeline, + .vkCmdSetViewport = gen9_CmdSetViewport, + .vkCmdSetScissor = gen9_CmdSetScissor, + .vkCmdSetLineWidth = gen9_CmdSetLineWidth, + .vkCmdSetDepthBias = gen9_CmdSetDepthBias, + .vkCmdSetBlendConstants = gen9_CmdSetBlendConstants, + .vkCmdSetDepthBounds = gen9_CmdSetDepthBounds, + .vkCmdSetStencilCompareMask = gen9_CmdSetStencilCompareMask, + .vkCmdSetStencilWriteMask = gen9_CmdSetStencilWriteMask, + .vkCmdSetStencilReference = gen9_CmdSetStencilReference, + .vkCmdBindDescriptorSets = gen9_CmdBindDescriptorSets, + .vkCmdBindIndexBuffer = gen9_CmdBindIndexBuffer, + .vkCmdBindVertexBuffers = gen9_CmdBindVertexBuffers, + .vkCmdDraw = gen9_CmdDraw, + .vkCmdDrawIndexed = gen9_CmdDrawIndexed, + .vkCmdDrawIndirect = gen9_CmdDrawIndirect, + .vkCmdDrawIndexedIndirect = gen9_CmdDrawIndexedIndirect, + .vkCmdDispatch = gen9_CmdDispatch, + .vkCmdDispatchIndirect = gen9_CmdDispatchIndirect, + .vkCmdCopyBuffer = gen9_CmdCopyBuffer, + .vkCmdCopyImage = gen9_CmdCopyImage, + .vkCmdBlitImage = gen9_CmdBlitImage, + .vkCmdCopyBufferToImage = gen9_CmdCopyBufferToImage, + .vkCmdCopyImageToBuffer = gen9_CmdCopyImageToBuffer, + .vkCmdUpdateBuffer = gen9_CmdUpdateBuffer, + .vkCmdFillBuffer = gen9_CmdFillBuffer, + .vkCmdClearColorImage = gen9_CmdClearColorImage, + .vkCmdClearDepthStencilImage = gen9_CmdClearDepthStencilImage, + .vkCmdClearAttachments = gen9_CmdClearAttachments, + .vkCmdResolveImage = gen9_CmdResolveImage, + .vkCmdSetEvent = gen9_CmdSetEvent, + .vkCmdResetEvent = gen9_CmdResetEvent, + .vkCmdWaitEvents = gen9_CmdWaitEvents, + .vkCmdPipelineBarrier = gen9_CmdPipelineBarrier, + .vkCmdBeginQuery = gen9_CmdBeginQuery, + .vkCmdEndQuery = gen9_CmdEndQuery, + .vkCmdBeginConditionalRenderingEXT = gen9_CmdBeginConditionalRenderingEXT, + .vkCmdEndConditionalRenderingEXT = gen9_CmdEndConditionalRenderingEXT, + .vkCmdResetQueryPool = gen9_CmdResetQueryPool, + .vkCmdWriteTimestamp = gen9_CmdWriteTimestamp, + .vkCmdCopyQueryPoolResults = gen9_CmdCopyQueryPoolResults, + .vkCmdPushConstants = gen9_CmdPushConstants, + .vkCmdBeginRenderPass = gen9_CmdBeginRenderPass, + .vkCmdNextSubpass = gen9_CmdNextSubpass, + .vkCmdEndRenderPass = gen9_CmdEndRenderPass, + .vkCmdExecuteCommands = gen9_CmdExecuteCommands, + .vkCreateSwapchainKHR = gen9_CreateSwapchainKHR, + .vkDestroySwapchainKHR = gen9_DestroySwapchainKHR, + .vkGetSwapchainImagesKHR = gen9_GetSwapchainImagesKHR, + .vkAcquireNextImageKHR = gen9_AcquireNextImageKHR, + .vkQueuePresentKHR = gen9_QueuePresentKHR, + .vkCmdPushDescriptorSetKHR = gen9_CmdPushDescriptorSetKHR, + .vkTrimCommandPool = gen9_TrimCommandPool, + .vkTrimCommandPoolKHR = gen9_TrimCommandPool, + .vkGetMemoryFdKHR = gen9_GetMemoryFdKHR, + .vkGetMemoryFdPropertiesKHR = gen9_GetMemoryFdPropertiesKHR, + .vkGetSemaphoreFdKHR = gen9_GetSemaphoreFdKHR, + .vkImportSemaphoreFdKHR = gen9_ImportSemaphoreFdKHR, + .vkGetFenceFdKHR = gen9_GetFenceFdKHR, + .vkImportFenceFdKHR = gen9_ImportFenceFdKHR, + .vkDisplayPowerControlEXT = gen9_DisplayPowerControlEXT, + .vkRegisterDeviceEventEXT = gen9_RegisterDeviceEventEXT, + .vkRegisterDisplayEventEXT = gen9_RegisterDisplayEventEXT, + .vkGetSwapchainCounterEXT = gen9_GetSwapchainCounterEXT, + .vkGetDeviceGroupPeerMemoryFeatures = gen9_GetDeviceGroupPeerMemoryFeatures, + .vkGetDeviceGroupPeerMemoryFeaturesKHR = gen9_GetDeviceGroupPeerMemoryFeatures, + .vkBindBufferMemory2 = gen9_BindBufferMemory2, + .vkBindBufferMemory2KHR = gen9_BindBufferMemory2, + .vkBindImageMemory2 = gen9_BindImageMemory2, + .vkBindImageMemory2KHR = gen9_BindImageMemory2, + .vkCmdSetDeviceMask = gen9_CmdSetDeviceMask, + .vkCmdSetDeviceMaskKHR = gen9_CmdSetDeviceMask, + .vkGetDeviceGroupPresentCapabilitiesKHR = gen9_GetDeviceGroupPresentCapabilitiesKHR, + .vkGetDeviceGroupSurfacePresentModesKHR = gen9_GetDeviceGroupSurfacePresentModesKHR, + .vkAcquireNextImage2KHR = gen9_AcquireNextImage2KHR, + .vkCmdDispatchBase = gen9_CmdDispatchBase, + .vkCmdDispatchBaseKHR = gen9_CmdDispatchBase, + .vkCreateDescriptorUpdateTemplate = gen9_CreateDescriptorUpdateTemplate, + .vkCreateDescriptorUpdateTemplateKHR = gen9_CreateDescriptorUpdateTemplate, + .vkDestroyDescriptorUpdateTemplate = gen9_DestroyDescriptorUpdateTemplate, + .vkDestroyDescriptorUpdateTemplateKHR = gen9_DestroyDescriptorUpdateTemplate, + .vkUpdateDescriptorSetWithTemplate = gen9_UpdateDescriptorSetWithTemplate, + .vkUpdateDescriptorSetWithTemplateKHR = gen9_UpdateDescriptorSetWithTemplate, + .vkCmdPushDescriptorSetWithTemplateKHR = gen9_CmdPushDescriptorSetWithTemplateKHR, + .vkGetBufferMemoryRequirements2 = gen9_GetBufferMemoryRequirements2, + .vkGetBufferMemoryRequirements2KHR = gen9_GetBufferMemoryRequirements2, + .vkGetImageMemoryRequirements2 = gen9_GetImageMemoryRequirements2, + .vkGetImageMemoryRequirements2KHR = gen9_GetImageMemoryRequirements2, + .vkGetImageSparseMemoryRequirements2 = gen9_GetImageSparseMemoryRequirements2, + .vkGetImageSparseMemoryRequirements2KHR = gen9_GetImageSparseMemoryRequirements2, + .vkCreateSamplerYcbcrConversion = gen9_CreateSamplerYcbcrConversion, + .vkCreateSamplerYcbcrConversionKHR = gen9_CreateSamplerYcbcrConversion, + .vkDestroySamplerYcbcrConversion = gen9_DestroySamplerYcbcrConversion, + .vkDestroySamplerYcbcrConversionKHR = gen9_DestroySamplerYcbcrConversion, + .vkGetDeviceQueue2 = gen9_GetDeviceQueue2, + .vkGetDescriptorSetLayoutSupport = gen9_GetDescriptorSetLayoutSupport, + .vkGetDescriptorSetLayoutSupportKHR = gen9_GetDescriptorSetLayoutSupport, +#ifdef VK_USE_PLATFORM_ANDROID_KHR + .vkGetSwapchainGrallocUsageANDROID = gen9_GetSwapchainGrallocUsageANDROID, +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + .vkAcquireImageANDROID = gen9_AcquireImageANDROID, +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + .vkQueueSignalReleaseImageANDROID = gen9_QueueSignalReleaseImageANDROID, +#endif // VK_USE_PLATFORM_ANDROID_KHR + .vkGetCalibratedTimestampsEXT = gen9_GetCalibratedTimestampsEXT, + .vkCreateRenderPass2KHR = gen9_CreateRenderPass2KHR, + .vkCmdBeginRenderPass2KHR = gen9_CmdBeginRenderPass2KHR, + .vkCmdNextSubpass2KHR = gen9_CmdNextSubpass2KHR, + .vkCmdEndRenderPass2KHR = gen9_CmdEndRenderPass2KHR, +#ifdef VK_USE_PLATFORM_ANDROID_KHR + .vkGetAndroidHardwareBufferPropertiesANDROID = gen9_GetAndroidHardwareBufferPropertiesANDROID, +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + .vkGetMemoryAndroidHardwareBufferANDROID = gen9_GetMemoryAndroidHardwareBufferANDROID, +#endif // VK_USE_PLATFORM_ANDROID_KHR + .vkCmdDrawIndirectCountKHR = gen9_CmdDrawIndirectCountKHR, + .vkCmdDrawIndexedIndirectCountKHR = gen9_CmdDrawIndexedIndirectCountKHR, + .vkCmdBindTransformFeedbackBuffersEXT = gen9_CmdBindTransformFeedbackBuffersEXT, + .vkCmdBeginTransformFeedbackEXT = gen9_CmdBeginTransformFeedbackEXT, + .vkCmdEndTransformFeedbackEXT = gen9_CmdEndTransformFeedbackEXT, + .vkCmdBeginQueryIndexedEXT = gen9_CmdBeginQueryIndexedEXT, + .vkCmdEndQueryIndexedEXT = gen9_CmdEndQueryIndexedEXT, + .vkCmdDrawIndirectByteCountEXT = gen9_CmdDrawIndirectByteCountEXT, + .vkCreateDmaBufImageINTEL = gen9_CreateDmaBufImageINTEL, + }; + PFN_vkVoidFunction gen10_GetDeviceProcAddr(VkDevice device, const char* pName) __attribute__ ((weak)); + void gen10_DestroyDevice(VkDevice device, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + void gen10_GetDeviceQueue(VkDevice device, uint32_t queueFamilyIndex, uint32_t queueIndex, VkQueue* pQueue) __attribute__ ((weak)); + VkResult gen10_QueueSubmit(VkQueue queue, uint32_t submitCount, const VkSubmitInfo* pSubmits, VkFence fence) __attribute__ ((weak)); + VkResult gen10_QueueWaitIdle(VkQueue queue) __attribute__ ((weak)); + VkResult gen10_DeviceWaitIdle(VkDevice device) __attribute__ ((weak)); + VkResult gen10_AllocateMemory(VkDevice device, const VkMemoryAllocateInfo* pAllocateInfo, const VkAllocationCallbacks* pAllocator, VkDeviceMemory* pMemory) __attribute__ ((weak)); + void gen10_FreeMemory(VkDevice device, VkDeviceMemory memory, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen10_MapMemory(VkDevice device, VkDeviceMemory memory, VkDeviceSize offset, VkDeviceSize size, VkMemoryMapFlags flags, void** ppData) __attribute__ ((weak)); + void gen10_UnmapMemory(VkDevice device, VkDeviceMemory memory) __attribute__ ((weak)); + VkResult gen10_FlushMappedMemoryRanges(VkDevice device, uint32_t memoryRangeCount, const VkMappedMemoryRange* pMemoryRanges) __attribute__ ((weak)); + VkResult gen10_InvalidateMappedMemoryRanges(VkDevice device, uint32_t memoryRangeCount, const VkMappedMemoryRange* pMemoryRanges) __attribute__ ((weak)); + void gen10_GetDeviceMemoryCommitment(VkDevice device, VkDeviceMemory memory, VkDeviceSize* pCommittedMemoryInBytes) __attribute__ ((weak)); + void gen10_GetBufferMemoryRequirements(VkDevice device, VkBuffer buffer, VkMemoryRequirements* pMemoryRequirements) __attribute__ ((weak)); + VkResult gen10_BindBufferMemory(VkDevice device, VkBuffer buffer, VkDeviceMemory memory, VkDeviceSize memoryOffset) __attribute__ ((weak)); + void gen10_GetImageMemoryRequirements(VkDevice device, VkImage image, VkMemoryRequirements* pMemoryRequirements) __attribute__ ((weak)); + VkResult gen10_BindImageMemory(VkDevice device, VkImage image, VkDeviceMemory memory, VkDeviceSize memoryOffset) __attribute__ ((weak)); + void gen10_GetImageSparseMemoryRequirements(VkDevice device, VkImage image, uint32_t* pSparseMemoryRequirementCount, VkSparseImageMemoryRequirements* pSparseMemoryRequirements) __attribute__ ((weak)); + VkResult gen10_QueueBindSparse(VkQueue queue, uint32_t bindInfoCount, const VkBindSparseInfo* pBindInfo, VkFence fence) __attribute__ ((weak)); + VkResult gen10_CreateFence(VkDevice device, const VkFenceCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence) __attribute__ ((weak)); + void gen10_DestroyFence(VkDevice device, VkFence fence, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen10_ResetFences(VkDevice device, uint32_t fenceCount, const VkFence* pFences) __attribute__ ((weak)); + VkResult gen10_GetFenceStatus(VkDevice device, VkFence fence) __attribute__ ((weak)); + VkResult gen10_WaitForFences(VkDevice device, uint32_t fenceCount, const VkFence* pFences, VkBool32 waitAll, uint64_t timeout) __attribute__ ((weak)); + VkResult gen10_CreateSemaphore(VkDevice device, const VkSemaphoreCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSemaphore* pSemaphore) __attribute__ ((weak)); + void gen10_DestroySemaphore(VkDevice device, VkSemaphore semaphore, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen10_CreateEvent(VkDevice device, const VkEventCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkEvent* pEvent) __attribute__ ((weak)); + void gen10_DestroyEvent(VkDevice device, VkEvent event, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen10_GetEventStatus(VkDevice device, VkEvent event) __attribute__ ((weak)); + VkResult gen10_SetEvent(VkDevice device, VkEvent event) __attribute__ ((weak)); + VkResult gen10_ResetEvent(VkDevice device, VkEvent event) __attribute__ ((weak)); + VkResult gen10_CreateQueryPool(VkDevice device, const VkQueryPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkQueryPool* pQueryPool) __attribute__ ((weak)); + void gen10_DestroyQueryPool(VkDevice device, VkQueryPool queryPool, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen10_GetQueryPoolResults(VkDevice device, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount, size_t dataSize, void* pData, VkDeviceSize stride, VkQueryResultFlags flags) __attribute__ ((weak)); + VkResult gen10_CreateBuffer(VkDevice device, const VkBufferCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkBuffer* pBuffer) __attribute__ ((weak)); + void gen10_DestroyBuffer(VkDevice device, VkBuffer buffer, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen10_CreateBufferView(VkDevice device, const VkBufferViewCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkBufferView* pView) __attribute__ ((weak)); + void gen10_DestroyBufferView(VkDevice device, VkBufferView bufferView, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen10_CreateImage(VkDevice device, const VkImageCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkImage* pImage) __attribute__ ((weak)); + void gen10_DestroyImage(VkDevice device, VkImage image, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + void gen10_GetImageSubresourceLayout(VkDevice device, VkImage image, const VkImageSubresource* pSubresource, VkSubresourceLayout* pLayout) __attribute__ ((weak)); + VkResult gen10_CreateImageView(VkDevice device, const VkImageViewCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkImageView* pView) __attribute__ ((weak)); + void gen10_DestroyImageView(VkDevice device, VkImageView imageView, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen10_CreateShaderModule(VkDevice device, const VkShaderModuleCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkShaderModule* pShaderModule) __attribute__ ((weak)); + void gen10_DestroyShaderModule(VkDevice device, VkShaderModule shaderModule, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen10_CreatePipelineCache(VkDevice device, const VkPipelineCacheCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkPipelineCache* pPipelineCache) __attribute__ ((weak)); + void gen10_DestroyPipelineCache(VkDevice device, VkPipelineCache pipelineCache, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen10_GetPipelineCacheData(VkDevice device, VkPipelineCache pipelineCache, size_t* pDataSize, void* pData) __attribute__ ((weak)); + VkResult gen10_MergePipelineCaches(VkDevice device, VkPipelineCache dstCache, uint32_t srcCacheCount, const VkPipelineCache* pSrcCaches) __attribute__ ((weak)); + VkResult gen10_CreateGraphicsPipelines(VkDevice device, VkPipelineCache pipelineCache, uint32_t createInfoCount, const VkGraphicsPipelineCreateInfo* pCreateInfos, const VkAllocationCallbacks* pAllocator, VkPipeline* pPipelines) __attribute__ ((weak)); + VkResult gen10_CreateComputePipelines(VkDevice device, VkPipelineCache pipelineCache, uint32_t createInfoCount, const VkComputePipelineCreateInfo* pCreateInfos, const VkAllocationCallbacks* pAllocator, VkPipeline* pPipelines) __attribute__ ((weak)); + void gen10_DestroyPipeline(VkDevice device, VkPipeline pipeline, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen10_CreatePipelineLayout(VkDevice device, const VkPipelineLayoutCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkPipelineLayout* pPipelineLayout) __attribute__ ((weak)); + void gen10_DestroyPipelineLayout(VkDevice device, VkPipelineLayout pipelineLayout, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen10_CreateSampler(VkDevice device, const VkSamplerCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSampler* pSampler) __attribute__ ((weak)); + void gen10_DestroySampler(VkDevice device, VkSampler sampler, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen10_CreateDescriptorSetLayout(VkDevice device, const VkDescriptorSetLayoutCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorSetLayout* pSetLayout) __attribute__ ((weak)); + void gen10_DestroyDescriptorSetLayout(VkDevice device, VkDescriptorSetLayout descriptorSetLayout, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen10_CreateDescriptorPool(VkDevice device, const VkDescriptorPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorPool* pDescriptorPool) __attribute__ ((weak)); + void gen10_DestroyDescriptorPool(VkDevice device, VkDescriptorPool descriptorPool, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen10_ResetDescriptorPool(VkDevice device, VkDescriptorPool descriptorPool, VkDescriptorPoolResetFlags flags) __attribute__ ((weak)); + VkResult gen10_AllocateDescriptorSets(VkDevice device, const VkDescriptorSetAllocateInfo* pAllocateInfo, VkDescriptorSet* pDescriptorSets) __attribute__ ((weak)); + VkResult gen10_FreeDescriptorSets(VkDevice device, VkDescriptorPool descriptorPool, uint32_t descriptorSetCount, const VkDescriptorSet* pDescriptorSets) __attribute__ ((weak)); + void gen10_UpdateDescriptorSets(VkDevice device, uint32_t descriptorWriteCount, const VkWriteDescriptorSet* pDescriptorWrites, uint32_t descriptorCopyCount, const VkCopyDescriptorSet* pDescriptorCopies) __attribute__ ((weak)); + VkResult gen10_CreateFramebuffer(VkDevice device, const VkFramebufferCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkFramebuffer* pFramebuffer) __attribute__ ((weak)); + void gen10_DestroyFramebuffer(VkDevice device, VkFramebuffer framebuffer, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen10_CreateRenderPass(VkDevice device, const VkRenderPassCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkRenderPass* pRenderPass) __attribute__ ((weak)); + void gen10_DestroyRenderPass(VkDevice device, VkRenderPass renderPass, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + void gen10_GetRenderAreaGranularity(VkDevice device, VkRenderPass renderPass, VkExtent2D* pGranularity) __attribute__ ((weak)); + VkResult gen10_CreateCommandPool(VkDevice device, const VkCommandPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkCommandPool* pCommandPool) __attribute__ ((weak)); + void gen10_DestroyCommandPool(VkDevice device, VkCommandPool commandPool, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen10_ResetCommandPool(VkDevice device, VkCommandPool commandPool, VkCommandPoolResetFlags flags) __attribute__ ((weak)); + VkResult gen10_AllocateCommandBuffers(VkDevice device, const VkCommandBufferAllocateInfo* pAllocateInfo, VkCommandBuffer* pCommandBuffers) __attribute__ ((weak)); + void gen10_FreeCommandBuffers(VkDevice device, VkCommandPool commandPool, uint32_t commandBufferCount, const VkCommandBuffer* pCommandBuffers) __attribute__ ((weak)); + VkResult gen10_BeginCommandBuffer(VkCommandBuffer commandBuffer, const VkCommandBufferBeginInfo* pBeginInfo) __attribute__ ((weak)); + VkResult gen10_EndCommandBuffer(VkCommandBuffer commandBuffer) __attribute__ ((weak)); + VkResult gen10_ResetCommandBuffer(VkCommandBuffer commandBuffer, VkCommandBufferResetFlags flags) __attribute__ ((weak)); + void gen10_CmdBindPipeline(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipeline pipeline) __attribute__ ((weak)); + void gen10_CmdSetViewport(VkCommandBuffer commandBuffer, uint32_t firstViewport, uint32_t viewportCount, const VkViewport* pViewports) __attribute__ ((weak)); + void gen10_CmdSetScissor(VkCommandBuffer commandBuffer, uint32_t firstScissor, uint32_t scissorCount, const VkRect2D* pScissors) __attribute__ ((weak)); + void gen10_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth) __attribute__ ((weak)); + void gen10_CmdSetDepthBias(VkCommandBuffer commandBuffer, float depthBiasConstantFactor, float depthBiasClamp, float depthBiasSlopeFactor) __attribute__ ((weak)); + void gen10_CmdSetBlendConstants(VkCommandBuffer commandBuffer, const float blendConstants[4]) __attribute__ ((weak)); + void gen10_CmdSetDepthBounds(VkCommandBuffer commandBuffer, float minDepthBounds, float maxDepthBounds) __attribute__ ((weak)); + void gen10_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t compareMask) __attribute__ ((weak)); + void gen10_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t writeMask) __attribute__ ((weak)); + void gen10_CmdSetStencilReference(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t reference) __attribute__ ((weak)); + void gen10_CmdBindDescriptorSets(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipelineLayout layout, uint32_t firstSet, uint32_t descriptorSetCount, const VkDescriptorSet* pDescriptorSets, uint32_t dynamicOffsetCount, const uint32_t* pDynamicOffsets) __attribute__ ((weak)); + void gen10_CmdBindIndexBuffer(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkIndexType indexType) __attribute__ ((weak)); + void gen10_CmdBindVertexBuffers(VkCommandBuffer commandBuffer, uint32_t firstBinding, uint32_t bindingCount, const VkBuffer* pBuffers, const VkDeviceSize* pOffsets) __attribute__ ((weak)); + void gen10_CmdDraw(VkCommandBuffer commandBuffer, uint32_t vertexCount, uint32_t instanceCount, uint32_t firstVertex, uint32_t firstInstance) __attribute__ ((weak)); + void gen10_CmdDrawIndexed(VkCommandBuffer commandBuffer, uint32_t indexCount, uint32_t instanceCount, uint32_t firstIndex, int32_t vertexOffset, uint32_t firstInstance) __attribute__ ((weak)); + void gen10_CmdDrawIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, uint32_t drawCount, uint32_t stride) __attribute__ ((weak)); + void gen10_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, uint32_t drawCount, uint32_t stride) __attribute__ ((weak)); + void gen10_CmdDispatch(VkCommandBuffer commandBuffer, uint32_t groupCountX, uint32_t groupCountY, uint32_t groupCountZ) __attribute__ ((weak)); + void gen10_CmdDispatchIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset) __attribute__ ((weak)); + void gen10_CmdCopyBuffer(VkCommandBuffer commandBuffer, VkBuffer srcBuffer, VkBuffer dstBuffer, uint32_t regionCount, const VkBufferCopy* pRegions) __attribute__ ((weak)); + void gen10_CmdCopyImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageCopy* pRegions) __attribute__ ((weak)); + void gen10_CmdBlitImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageBlit* pRegions, VkFilter filter) __attribute__ ((weak)); + void gen10_CmdCopyBufferToImage(VkCommandBuffer commandBuffer, VkBuffer srcBuffer, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkBufferImageCopy* pRegions) __attribute__ ((weak)); + void gen10_CmdCopyImageToBuffer(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkBuffer dstBuffer, uint32_t regionCount, const VkBufferImageCopy* pRegions) __attribute__ ((weak)); + void gen10_CmdUpdateBuffer(VkCommandBuffer commandBuffer, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize dataSize, const void* pData) __attribute__ ((weak)); + void gen10_CmdFillBuffer(VkCommandBuffer commandBuffer, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize size, uint32_t data) __attribute__ ((weak)); + void gen10_CmdClearColorImage(VkCommandBuffer commandBuffer, VkImage image, VkImageLayout imageLayout, const VkClearColorValue* pColor, uint32_t rangeCount, const VkImageSubresourceRange* pRanges) __attribute__ ((weak)); + void gen10_CmdClearDepthStencilImage(VkCommandBuffer commandBuffer, VkImage image, VkImageLayout imageLayout, const VkClearDepthStencilValue* pDepthStencil, uint32_t rangeCount, const VkImageSubresourceRange* pRanges) __attribute__ ((weak)); + void gen10_CmdClearAttachments(VkCommandBuffer commandBuffer, uint32_t attachmentCount, const VkClearAttachment* pAttachments, uint32_t rectCount, const VkClearRect* pRects) __attribute__ ((weak)); + void gen10_CmdResolveImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageResolve* pRegions) __attribute__ ((weak)); + void gen10_CmdSetEvent(VkCommandBuffer commandBuffer, VkEvent event, VkPipelineStageFlags stageMask) __attribute__ ((weak)); + void gen10_CmdResetEvent(VkCommandBuffer commandBuffer, VkEvent event, VkPipelineStageFlags stageMask) __attribute__ ((weak)); + void gen10_CmdWaitEvents(VkCommandBuffer commandBuffer, uint32_t eventCount, const VkEvent* pEvents, VkPipelineStageFlags srcStageMask, VkPipelineStageFlags dstStageMask, uint32_t memoryBarrierCount, const VkMemoryBarrier* pMemoryBarriers, uint32_t bufferMemoryBarrierCount, const VkBufferMemoryBarrier* pBufferMemoryBarriers, uint32_t imageMemoryBarrierCount, const VkImageMemoryBarrier* pImageMemoryBarriers) __attribute__ ((weak)); + void gen10_CmdPipelineBarrier(VkCommandBuffer commandBuffer, VkPipelineStageFlags srcStageMask, VkPipelineStageFlags dstStageMask, VkDependencyFlags dependencyFlags, uint32_t memoryBarrierCount, const VkMemoryBarrier* pMemoryBarriers, uint32_t bufferMemoryBarrierCount, const VkBufferMemoryBarrier* pBufferMemoryBarriers, uint32_t imageMemoryBarrierCount, const VkImageMemoryBarrier* pImageMemoryBarriers) __attribute__ ((weak)); + void gen10_CmdBeginQuery(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, VkQueryControlFlags flags) __attribute__ ((weak)); + void gen10_CmdEndQuery(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query) __attribute__ ((weak)); + void gen10_CmdBeginConditionalRenderingEXT(VkCommandBuffer commandBuffer, const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin) __attribute__ ((weak)); + void gen10_CmdEndConditionalRenderingEXT(VkCommandBuffer commandBuffer) __attribute__ ((weak)); + void gen10_CmdResetQueryPool(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount) __attribute__ ((weak)); + void gen10_CmdWriteTimestamp(VkCommandBuffer commandBuffer, VkPipelineStageFlagBits pipelineStage, VkQueryPool queryPool, uint32_t query) __attribute__ ((weak)); + void gen10_CmdCopyQueryPoolResults(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize stride, VkQueryResultFlags flags) __attribute__ ((weak)); + void gen10_CmdPushConstants(VkCommandBuffer commandBuffer, VkPipelineLayout layout, VkShaderStageFlags stageFlags, uint32_t offset, uint32_t size, const void* pValues) __attribute__ ((weak)); + void gen10_CmdBeginRenderPass(VkCommandBuffer commandBuffer, const VkRenderPassBeginInfo* pRenderPassBegin, VkSubpassContents contents) __attribute__ ((weak)); + void gen10_CmdNextSubpass(VkCommandBuffer commandBuffer, VkSubpassContents contents) __attribute__ ((weak)); + void gen10_CmdEndRenderPass(VkCommandBuffer commandBuffer) __attribute__ ((weak)); + void gen10_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCount, const VkCommandBuffer* pCommandBuffers) __attribute__ ((weak)); + VkResult gen10_CreateSwapchainKHR(VkDevice device, const VkSwapchainCreateInfoKHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSwapchainKHR* pSwapchain) __attribute__ ((weak)); + void gen10_DestroySwapchainKHR(VkDevice device, VkSwapchainKHR swapchain, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen10_GetSwapchainImagesKHR(VkDevice device, VkSwapchainKHR swapchain, uint32_t* pSwapchainImageCount, VkImage* pSwapchainImages) __attribute__ ((weak)); + VkResult gen10_AcquireNextImageKHR(VkDevice device, VkSwapchainKHR swapchain, uint64_t timeout, VkSemaphore semaphore, VkFence fence, uint32_t* pImageIndex) __attribute__ ((weak)); + VkResult gen10_QueuePresentKHR(VkQueue queue, const VkPresentInfoKHR* pPresentInfo) __attribute__ ((weak)); + void gen10_CmdPushDescriptorSetKHR(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipelineLayout layout, uint32_t set, uint32_t descriptorWriteCount, const VkWriteDescriptorSet* pDescriptorWrites) __attribute__ ((weak)); + void gen10_TrimCommandPool(VkDevice device, VkCommandPool commandPool, VkCommandPoolTrimFlags flags) __attribute__ ((weak)); + VkResult gen10_GetMemoryFdKHR(VkDevice device, const VkMemoryGetFdInfoKHR* pGetFdInfo, int* pFd) __attribute__ ((weak)); + VkResult gen10_GetMemoryFdPropertiesKHR(VkDevice device, VkExternalMemoryHandleTypeFlagBits handleType, int fd, VkMemoryFdPropertiesKHR* pMemoryFdProperties) __attribute__ ((weak)); + VkResult gen10_GetSemaphoreFdKHR(VkDevice device, const VkSemaphoreGetFdInfoKHR* pGetFdInfo, int* pFd) __attribute__ ((weak)); + VkResult gen10_ImportSemaphoreFdKHR(VkDevice device, const VkImportSemaphoreFdInfoKHR* pImportSemaphoreFdInfo) __attribute__ ((weak)); + VkResult gen10_GetFenceFdKHR(VkDevice device, const VkFenceGetFdInfoKHR* pGetFdInfo, int* pFd) __attribute__ ((weak)); + VkResult gen10_ImportFenceFdKHR(VkDevice device, const VkImportFenceFdInfoKHR* pImportFenceFdInfo) __attribute__ ((weak)); + VkResult gen10_DisplayPowerControlEXT(VkDevice device, VkDisplayKHR display, const VkDisplayPowerInfoEXT* pDisplayPowerInfo) __attribute__ ((weak)); + VkResult gen10_RegisterDeviceEventEXT(VkDevice device, const VkDeviceEventInfoEXT* pDeviceEventInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence) __attribute__ ((weak)); + VkResult gen10_RegisterDisplayEventEXT(VkDevice device, VkDisplayKHR display, const VkDisplayEventInfoEXT* pDisplayEventInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence) __attribute__ ((weak)); + VkResult gen10_GetSwapchainCounterEXT(VkDevice device, VkSwapchainKHR swapchain, VkSurfaceCounterFlagBitsEXT counter, uint64_t* pCounterValue) __attribute__ ((weak)); + void gen10_GetDeviceGroupPeerMemoryFeatures(VkDevice device, uint32_t heapIndex, uint32_t localDeviceIndex, uint32_t remoteDeviceIndex, VkPeerMemoryFeatureFlags* pPeerMemoryFeatures) __attribute__ ((weak)); + VkResult gen10_BindBufferMemory2(VkDevice device, uint32_t bindInfoCount, const VkBindBufferMemoryInfo* pBindInfos) __attribute__ ((weak)); + VkResult gen10_BindImageMemory2(VkDevice device, uint32_t bindInfoCount, const VkBindImageMemoryInfo* pBindInfos) __attribute__ ((weak)); + void gen10_CmdSetDeviceMask(VkCommandBuffer commandBuffer, uint32_t deviceMask) __attribute__ ((weak)); + VkResult gen10_GetDeviceGroupPresentCapabilitiesKHR(VkDevice device, VkDeviceGroupPresentCapabilitiesKHR* pDeviceGroupPresentCapabilities) __attribute__ ((weak)); + VkResult gen10_GetDeviceGroupSurfacePresentModesKHR(VkDevice device, VkSurfaceKHR surface, VkDeviceGroupPresentModeFlagsKHR* pModes) __attribute__ ((weak)); + VkResult gen10_AcquireNextImage2KHR(VkDevice device, const VkAcquireNextImageInfoKHR* pAcquireInfo, uint32_t* pImageIndex) __attribute__ ((weak)); + void gen10_CmdDispatchBase(VkCommandBuffer commandBuffer, uint32_t baseGroupX, uint32_t baseGroupY, uint32_t baseGroupZ, uint32_t groupCountX, uint32_t groupCountY, uint32_t groupCountZ) __attribute__ ((weak)); + VkResult gen10_CreateDescriptorUpdateTemplate(VkDevice device, const VkDescriptorUpdateTemplateCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorUpdateTemplate* pDescriptorUpdateTemplate) __attribute__ ((weak)); + void gen10_DestroyDescriptorUpdateTemplate(VkDevice device, VkDescriptorUpdateTemplate descriptorUpdateTemplate, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + void gen10_UpdateDescriptorSetWithTemplate(VkDevice device, VkDescriptorSet descriptorSet, VkDescriptorUpdateTemplate descriptorUpdateTemplate, const void* pData) __attribute__ ((weak)); + void gen10_CmdPushDescriptorSetWithTemplateKHR(VkCommandBuffer commandBuffer, VkDescriptorUpdateTemplate descriptorUpdateTemplate, VkPipelineLayout layout, uint32_t set, const void* pData) __attribute__ ((weak)); + void gen10_GetBufferMemoryRequirements2(VkDevice device, const VkBufferMemoryRequirementsInfo2* pInfo, VkMemoryRequirements2* pMemoryRequirements) __attribute__ ((weak)); + void gen10_GetImageMemoryRequirements2(VkDevice device, const VkImageMemoryRequirementsInfo2* pInfo, VkMemoryRequirements2* pMemoryRequirements) __attribute__ ((weak)); + void gen10_GetImageSparseMemoryRequirements2(VkDevice device, const VkImageSparseMemoryRequirementsInfo2* pInfo, uint32_t* pSparseMemoryRequirementCount, VkSparseImageMemoryRequirements2* pSparseMemoryRequirements) __attribute__ ((weak)); + VkResult gen10_CreateSamplerYcbcrConversion(VkDevice device, const VkSamplerYcbcrConversionCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSamplerYcbcrConversion* pYcbcrConversion) __attribute__ ((weak)); + void gen10_DestroySamplerYcbcrConversion(VkDevice device, VkSamplerYcbcrConversion ycbcrConversion, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + void gen10_GetDeviceQueue2(VkDevice device, const VkDeviceQueueInfo2* pQueueInfo, VkQueue* pQueue) __attribute__ ((weak)); + void gen10_GetDescriptorSetLayoutSupport(VkDevice device, const VkDescriptorSetLayoutCreateInfo* pCreateInfo, VkDescriptorSetLayoutSupport* pSupport) __attribute__ ((weak)); + #ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult gen10_GetSwapchainGrallocUsageANDROID(VkDevice device, VkFormat format, VkImageUsageFlags imageUsage, int* grallocUsage) __attribute__ ((weak)); +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult gen10_AcquireImageANDROID(VkDevice device, VkImage image, int nativeFenceFd, VkSemaphore semaphore, VkFence fence) __attribute__ ((weak)); +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult gen10_QueueSignalReleaseImageANDROID(VkQueue queue, uint32_t waitSemaphoreCount, const VkSemaphore* pWaitSemaphores, VkImage image, int* pNativeFenceFd) __attribute__ ((weak)); +#endif // VK_USE_PLATFORM_ANDROID_KHR + VkResult gen10_GetCalibratedTimestampsEXT(VkDevice device, uint32_t timestampCount, const VkCalibratedTimestampInfoEXT* pTimestampInfos, uint64_t* pTimestamps, uint64_t* pMaxDeviation) __attribute__ ((weak)); + VkResult gen10_CreateRenderPass2KHR(VkDevice device, const VkRenderPassCreateInfo2KHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkRenderPass* pRenderPass) __attribute__ ((weak)); + void gen10_CmdBeginRenderPass2KHR(VkCommandBuffer commandBuffer, const VkRenderPassBeginInfo* pRenderPassBegin, const VkSubpassBeginInfoKHR* pSubpassBeginInfo) __attribute__ ((weak)); + void gen10_CmdNextSubpass2KHR(VkCommandBuffer commandBuffer, const VkSubpassBeginInfoKHR* pSubpassBeginInfo, const VkSubpassEndInfoKHR* pSubpassEndInfo) __attribute__ ((weak)); + void gen10_CmdEndRenderPass2KHR(VkCommandBuffer commandBuffer, const VkSubpassEndInfoKHR* pSubpassEndInfo) __attribute__ ((weak)); +#ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult gen10_GetAndroidHardwareBufferPropertiesANDROID(VkDevice device, const struct AHardwareBuffer* buffer, VkAndroidHardwareBufferPropertiesANDROID* pProperties) __attribute__ ((weak)); +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult gen10_GetMemoryAndroidHardwareBufferANDROID(VkDevice device, const VkMemoryGetAndroidHardwareBufferInfoANDROID* pInfo, struct AHardwareBuffer** pBuffer) __attribute__ ((weak)); +#endif // VK_USE_PLATFORM_ANDROID_KHR + void gen10_CmdDrawIndirectCountKHR(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkBuffer countBuffer, VkDeviceSize countBufferOffset, uint32_t maxDrawCount, uint32_t stride) __attribute__ ((weak)); + void gen10_CmdDrawIndexedIndirectCountKHR(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkBuffer countBuffer, VkDeviceSize countBufferOffset, uint32_t maxDrawCount, uint32_t stride) __attribute__ ((weak)); + void gen10_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer, uint32_t firstBinding, uint32_t bindingCount, const VkBuffer* pBuffers, const VkDeviceSize* pOffsets, const VkDeviceSize* pSizes) __attribute__ ((weak)); + void gen10_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstCounterBuffer, uint32_t counterBufferCount, const VkBuffer* pCounterBuffers, const VkDeviceSize* pCounterBufferOffsets) __attribute__ ((weak)); + void gen10_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstCounterBuffer, uint32_t counterBufferCount, const VkBuffer* pCounterBuffers, const VkDeviceSize* pCounterBufferOffsets) __attribute__ ((weak)); + void gen10_CmdBeginQueryIndexedEXT(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, VkQueryControlFlags flags, uint32_t index) __attribute__ ((weak)); + void gen10_CmdEndQueryIndexedEXT(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, uint32_t index) __attribute__ ((weak)); + void gen10_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer, uint32_t instanceCount, uint32_t firstInstance, VkBuffer counterBuffer, VkDeviceSize counterBufferOffset, uint32_t counterOffset, uint32_t vertexStride) __attribute__ ((weak)); + VkResult gen10_CreateDmaBufImageINTEL(VkDevice device, const VkDmaBufImageCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDeviceMemory* pMem, VkImage* pImage) __attribute__ ((weak)); + + const struct anv_device_dispatch_table gen10_device_dispatch_table = { + .vkGetDeviceProcAddr = gen10_GetDeviceProcAddr, + .vkDestroyDevice = gen10_DestroyDevice, + .vkGetDeviceQueue = gen10_GetDeviceQueue, + .vkQueueSubmit = gen10_QueueSubmit, + .vkQueueWaitIdle = gen10_QueueWaitIdle, + .vkDeviceWaitIdle = gen10_DeviceWaitIdle, + .vkAllocateMemory = gen10_AllocateMemory, + .vkFreeMemory = gen10_FreeMemory, + .vkMapMemory = gen10_MapMemory, + .vkUnmapMemory = gen10_UnmapMemory, + .vkFlushMappedMemoryRanges = gen10_FlushMappedMemoryRanges, + .vkInvalidateMappedMemoryRanges = gen10_InvalidateMappedMemoryRanges, + .vkGetDeviceMemoryCommitment = gen10_GetDeviceMemoryCommitment, + .vkGetBufferMemoryRequirements = gen10_GetBufferMemoryRequirements, + .vkBindBufferMemory = gen10_BindBufferMemory, + .vkGetImageMemoryRequirements = gen10_GetImageMemoryRequirements, + .vkBindImageMemory = gen10_BindImageMemory, + .vkGetImageSparseMemoryRequirements = gen10_GetImageSparseMemoryRequirements, + .vkQueueBindSparse = gen10_QueueBindSparse, + .vkCreateFence = gen10_CreateFence, + .vkDestroyFence = gen10_DestroyFence, + .vkResetFences = gen10_ResetFences, + .vkGetFenceStatus = gen10_GetFenceStatus, + .vkWaitForFences = gen10_WaitForFences, + .vkCreateSemaphore = gen10_CreateSemaphore, + .vkDestroySemaphore = gen10_DestroySemaphore, + .vkCreateEvent = gen10_CreateEvent, + .vkDestroyEvent = gen10_DestroyEvent, + .vkGetEventStatus = gen10_GetEventStatus, + .vkSetEvent = gen10_SetEvent, + .vkResetEvent = gen10_ResetEvent, + .vkCreateQueryPool = gen10_CreateQueryPool, + .vkDestroyQueryPool = gen10_DestroyQueryPool, + .vkGetQueryPoolResults = gen10_GetQueryPoolResults, + .vkCreateBuffer = gen10_CreateBuffer, + .vkDestroyBuffer = gen10_DestroyBuffer, + .vkCreateBufferView = gen10_CreateBufferView, + .vkDestroyBufferView = gen10_DestroyBufferView, + .vkCreateImage = gen10_CreateImage, + .vkDestroyImage = gen10_DestroyImage, + .vkGetImageSubresourceLayout = gen10_GetImageSubresourceLayout, + .vkCreateImageView = gen10_CreateImageView, + .vkDestroyImageView = gen10_DestroyImageView, + .vkCreateShaderModule = gen10_CreateShaderModule, + .vkDestroyShaderModule = gen10_DestroyShaderModule, + .vkCreatePipelineCache = gen10_CreatePipelineCache, + .vkDestroyPipelineCache = gen10_DestroyPipelineCache, + .vkGetPipelineCacheData = gen10_GetPipelineCacheData, + .vkMergePipelineCaches = gen10_MergePipelineCaches, + .vkCreateGraphicsPipelines = gen10_CreateGraphicsPipelines, + .vkCreateComputePipelines = gen10_CreateComputePipelines, + .vkDestroyPipeline = gen10_DestroyPipeline, + .vkCreatePipelineLayout = gen10_CreatePipelineLayout, + .vkDestroyPipelineLayout = gen10_DestroyPipelineLayout, + .vkCreateSampler = gen10_CreateSampler, + .vkDestroySampler = gen10_DestroySampler, + .vkCreateDescriptorSetLayout = gen10_CreateDescriptorSetLayout, + .vkDestroyDescriptorSetLayout = gen10_DestroyDescriptorSetLayout, + .vkCreateDescriptorPool = gen10_CreateDescriptorPool, + .vkDestroyDescriptorPool = gen10_DestroyDescriptorPool, + .vkResetDescriptorPool = gen10_ResetDescriptorPool, + .vkAllocateDescriptorSets = gen10_AllocateDescriptorSets, + .vkFreeDescriptorSets = gen10_FreeDescriptorSets, + .vkUpdateDescriptorSets = gen10_UpdateDescriptorSets, + .vkCreateFramebuffer = gen10_CreateFramebuffer, + .vkDestroyFramebuffer = gen10_DestroyFramebuffer, + .vkCreateRenderPass = gen10_CreateRenderPass, + .vkDestroyRenderPass = gen10_DestroyRenderPass, + .vkGetRenderAreaGranularity = gen10_GetRenderAreaGranularity, + .vkCreateCommandPool = gen10_CreateCommandPool, + .vkDestroyCommandPool = gen10_DestroyCommandPool, + .vkResetCommandPool = gen10_ResetCommandPool, + .vkAllocateCommandBuffers = gen10_AllocateCommandBuffers, + .vkFreeCommandBuffers = gen10_FreeCommandBuffers, + .vkBeginCommandBuffer = gen10_BeginCommandBuffer, + .vkEndCommandBuffer = gen10_EndCommandBuffer, + .vkResetCommandBuffer = gen10_ResetCommandBuffer, + .vkCmdBindPipeline = gen10_CmdBindPipeline, + .vkCmdSetViewport = gen10_CmdSetViewport, + .vkCmdSetScissor = gen10_CmdSetScissor, + .vkCmdSetLineWidth = gen10_CmdSetLineWidth, + .vkCmdSetDepthBias = gen10_CmdSetDepthBias, + .vkCmdSetBlendConstants = gen10_CmdSetBlendConstants, + .vkCmdSetDepthBounds = gen10_CmdSetDepthBounds, + .vkCmdSetStencilCompareMask = gen10_CmdSetStencilCompareMask, + .vkCmdSetStencilWriteMask = gen10_CmdSetStencilWriteMask, + .vkCmdSetStencilReference = gen10_CmdSetStencilReference, + .vkCmdBindDescriptorSets = gen10_CmdBindDescriptorSets, + .vkCmdBindIndexBuffer = gen10_CmdBindIndexBuffer, + .vkCmdBindVertexBuffers = gen10_CmdBindVertexBuffers, + .vkCmdDraw = gen10_CmdDraw, + .vkCmdDrawIndexed = gen10_CmdDrawIndexed, + .vkCmdDrawIndirect = gen10_CmdDrawIndirect, + .vkCmdDrawIndexedIndirect = gen10_CmdDrawIndexedIndirect, + .vkCmdDispatch = gen10_CmdDispatch, + .vkCmdDispatchIndirect = gen10_CmdDispatchIndirect, + .vkCmdCopyBuffer = gen10_CmdCopyBuffer, + .vkCmdCopyImage = gen10_CmdCopyImage, + .vkCmdBlitImage = gen10_CmdBlitImage, + .vkCmdCopyBufferToImage = gen10_CmdCopyBufferToImage, + .vkCmdCopyImageToBuffer = gen10_CmdCopyImageToBuffer, + .vkCmdUpdateBuffer = gen10_CmdUpdateBuffer, + .vkCmdFillBuffer = gen10_CmdFillBuffer, + .vkCmdClearColorImage = gen10_CmdClearColorImage, + .vkCmdClearDepthStencilImage = gen10_CmdClearDepthStencilImage, + .vkCmdClearAttachments = gen10_CmdClearAttachments, + .vkCmdResolveImage = gen10_CmdResolveImage, + .vkCmdSetEvent = gen10_CmdSetEvent, + .vkCmdResetEvent = gen10_CmdResetEvent, + .vkCmdWaitEvents = gen10_CmdWaitEvents, + .vkCmdPipelineBarrier = gen10_CmdPipelineBarrier, + .vkCmdBeginQuery = gen10_CmdBeginQuery, + .vkCmdEndQuery = gen10_CmdEndQuery, + .vkCmdBeginConditionalRenderingEXT = gen10_CmdBeginConditionalRenderingEXT, + .vkCmdEndConditionalRenderingEXT = gen10_CmdEndConditionalRenderingEXT, + .vkCmdResetQueryPool = gen10_CmdResetQueryPool, + .vkCmdWriteTimestamp = gen10_CmdWriteTimestamp, + .vkCmdCopyQueryPoolResults = gen10_CmdCopyQueryPoolResults, + .vkCmdPushConstants = gen10_CmdPushConstants, + .vkCmdBeginRenderPass = gen10_CmdBeginRenderPass, + .vkCmdNextSubpass = gen10_CmdNextSubpass, + .vkCmdEndRenderPass = gen10_CmdEndRenderPass, + .vkCmdExecuteCommands = gen10_CmdExecuteCommands, + .vkCreateSwapchainKHR = gen10_CreateSwapchainKHR, + .vkDestroySwapchainKHR = gen10_DestroySwapchainKHR, + .vkGetSwapchainImagesKHR = gen10_GetSwapchainImagesKHR, + .vkAcquireNextImageKHR = gen10_AcquireNextImageKHR, + .vkQueuePresentKHR = gen10_QueuePresentKHR, + .vkCmdPushDescriptorSetKHR = gen10_CmdPushDescriptorSetKHR, + .vkTrimCommandPool = gen10_TrimCommandPool, + .vkTrimCommandPoolKHR = gen10_TrimCommandPool, + .vkGetMemoryFdKHR = gen10_GetMemoryFdKHR, + .vkGetMemoryFdPropertiesKHR = gen10_GetMemoryFdPropertiesKHR, + .vkGetSemaphoreFdKHR = gen10_GetSemaphoreFdKHR, + .vkImportSemaphoreFdKHR = gen10_ImportSemaphoreFdKHR, + .vkGetFenceFdKHR = gen10_GetFenceFdKHR, + .vkImportFenceFdKHR = gen10_ImportFenceFdKHR, + .vkDisplayPowerControlEXT = gen10_DisplayPowerControlEXT, + .vkRegisterDeviceEventEXT = gen10_RegisterDeviceEventEXT, + .vkRegisterDisplayEventEXT = gen10_RegisterDisplayEventEXT, + .vkGetSwapchainCounterEXT = gen10_GetSwapchainCounterEXT, + .vkGetDeviceGroupPeerMemoryFeatures = gen10_GetDeviceGroupPeerMemoryFeatures, + .vkGetDeviceGroupPeerMemoryFeaturesKHR = gen10_GetDeviceGroupPeerMemoryFeatures, + .vkBindBufferMemory2 = gen10_BindBufferMemory2, + .vkBindBufferMemory2KHR = gen10_BindBufferMemory2, + .vkBindImageMemory2 = gen10_BindImageMemory2, + .vkBindImageMemory2KHR = gen10_BindImageMemory2, + .vkCmdSetDeviceMask = gen10_CmdSetDeviceMask, + .vkCmdSetDeviceMaskKHR = gen10_CmdSetDeviceMask, + .vkGetDeviceGroupPresentCapabilitiesKHR = gen10_GetDeviceGroupPresentCapabilitiesKHR, + .vkGetDeviceGroupSurfacePresentModesKHR = gen10_GetDeviceGroupSurfacePresentModesKHR, + .vkAcquireNextImage2KHR = gen10_AcquireNextImage2KHR, + .vkCmdDispatchBase = gen10_CmdDispatchBase, + .vkCmdDispatchBaseKHR = gen10_CmdDispatchBase, + .vkCreateDescriptorUpdateTemplate = gen10_CreateDescriptorUpdateTemplate, + .vkCreateDescriptorUpdateTemplateKHR = gen10_CreateDescriptorUpdateTemplate, + .vkDestroyDescriptorUpdateTemplate = gen10_DestroyDescriptorUpdateTemplate, + .vkDestroyDescriptorUpdateTemplateKHR = gen10_DestroyDescriptorUpdateTemplate, + .vkUpdateDescriptorSetWithTemplate = gen10_UpdateDescriptorSetWithTemplate, + .vkUpdateDescriptorSetWithTemplateKHR = gen10_UpdateDescriptorSetWithTemplate, + .vkCmdPushDescriptorSetWithTemplateKHR = gen10_CmdPushDescriptorSetWithTemplateKHR, + .vkGetBufferMemoryRequirements2 = gen10_GetBufferMemoryRequirements2, + .vkGetBufferMemoryRequirements2KHR = gen10_GetBufferMemoryRequirements2, + .vkGetImageMemoryRequirements2 = gen10_GetImageMemoryRequirements2, + .vkGetImageMemoryRequirements2KHR = gen10_GetImageMemoryRequirements2, + .vkGetImageSparseMemoryRequirements2 = gen10_GetImageSparseMemoryRequirements2, + .vkGetImageSparseMemoryRequirements2KHR = gen10_GetImageSparseMemoryRequirements2, + .vkCreateSamplerYcbcrConversion = gen10_CreateSamplerYcbcrConversion, + .vkCreateSamplerYcbcrConversionKHR = gen10_CreateSamplerYcbcrConversion, + .vkDestroySamplerYcbcrConversion = gen10_DestroySamplerYcbcrConversion, + .vkDestroySamplerYcbcrConversionKHR = gen10_DestroySamplerYcbcrConversion, + .vkGetDeviceQueue2 = gen10_GetDeviceQueue2, + .vkGetDescriptorSetLayoutSupport = gen10_GetDescriptorSetLayoutSupport, + .vkGetDescriptorSetLayoutSupportKHR = gen10_GetDescriptorSetLayoutSupport, +#ifdef VK_USE_PLATFORM_ANDROID_KHR + .vkGetSwapchainGrallocUsageANDROID = gen10_GetSwapchainGrallocUsageANDROID, +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + .vkAcquireImageANDROID = gen10_AcquireImageANDROID, +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + .vkQueueSignalReleaseImageANDROID = gen10_QueueSignalReleaseImageANDROID, +#endif // VK_USE_PLATFORM_ANDROID_KHR + .vkGetCalibratedTimestampsEXT = gen10_GetCalibratedTimestampsEXT, + .vkCreateRenderPass2KHR = gen10_CreateRenderPass2KHR, + .vkCmdBeginRenderPass2KHR = gen10_CmdBeginRenderPass2KHR, + .vkCmdNextSubpass2KHR = gen10_CmdNextSubpass2KHR, + .vkCmdEndRenderPass2KHR = gen10_CmdEndRenderPass2KHR, +#ifdef VK_USE_PLATFORM_ANDROID_KHR + .vkGetAndroidHardwareBufferPropertiesANDROID = gen10_GetAndroidHardwareBufferPropertiesANDROID, +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + .vkGetMemoryAndroidHardwareBufferANDROID = gen10_GetMemoryAndroidHardwareBufferANDROID, +#endif // VK_USE_PLATFORM_ANDROID_KHR + .vkCmdDrawIndirectCountKHR = gen10_CmdDrawIndirectCountKHR, + .vkCmdDrawIndexedIndirectCountKHR = gen10_CmdDrawIndexedIndirectCountKHR, + .vkCmdBindTransformFeedbackBuffersEXT = gen10_CmdBindTransformFeedbackBuffersEXT, + .vkCmdBeginTransformFeedbackEXT = gen10_CmdBeginTransformFeedbackEXT, + .vkCmdEndTransformFeedbackEXT = gen10_CmdEndTransformFeedbackEXT, + .vkCmdBeginQueryIndexedEXT = gen10_CmdBeginQueryIndexedEXT, + .vkCmdEndQueryIndexedEXT = gen10_CmdEndQueryIndexedEXT, + .vkCmdDrawIndirectByteCountEXT = gen10_CmdDrawIndirectByteCountEXT, + .vkCreateDmaBufImageINTEL = gen10_CreateDmaBufImageINTEL, + }; + PFN_vkVoidFunction gen11_GetDeviceProcAddr(VkDevice device, const char* pName) __attribute__ ((weak)); + void gen11_DestroyDevice(VkDevice device, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + void gen11_GetDeviceQueue(VkDevice device, uint32_t queueFamilyIndex, uint32_t queueIndex, VkQueue* pQueue) __attribute__ ((weak)); + VkResult gen11_QueueSubmit(VkQueue queue, uint32_t submitCount, const VkSubmitInfo* pSubmits, VkFence fence) __attribute__ ((weak)); + VkResult gen11_QueueWaitIdle(VkQueue queue) __attribute__ ((weak)); + VkResult gen11_DeviceWaitIdle(VkDevice device) __attribute__ ((weak)); + VkResult gen11_AllocateMemory(VkDevice device, const VkMemoryAllocateInfo* pAllocateInfo, const VkAllocationCallbacks* pAllocator, VkDeviceMemory* pMemory) __attribute__ ((weak)); + void gen11_FreeMemory(VkDevice device, VkDeviceMemory memory, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen11_MapMemory(VkDevice device, VkDeviceMemory memory, VkDeviceSize offset, VkDeviceSize size, VkMemoryMapFlags flags, void** ppData) __attribute__ ((weak)); + void gen11_UnmapMemory(VkDevice device, VkDeviceMemory memory) __attribute__ ((weak)); + VkResult gen11_FlushMappedMemoryRanges(VkDevice device, uint32_t memoryRangeCount, const VkMappedMemoryRange* pMemoryRanges) __attribute__ ((weak)); + VkResult gen11_InvalidateMappedMemoryRanges(VkDevice device, uint32_t memoryRangeCount, const VkMappedMemoryRange* pMemoryRanges) __attribute__ ((weak)); + void gen11_GetDeviceMemoryCommitment(VkDevice device, VkDeviceMemory memory, VkDeviceSize* pCommittedMemoryInBytes) __attribute__ ((weak)); + void gen11_GetBufferMemoryRequirements(VkDevice device, VkBuffer buffer, VkMemoryRequirements* pMemoryRequirements) __attribute__ ((weak)); + VkResult gen11_BindBufferMemory(VkDevice device, VkBuffer buffer, VkDeviceMemory memory, VkDeviceSize memoryOffset) __attribute__ ((weak)); + void gen11_GetImageMemoryRequirements(VkDevice device, VkImage image, VkMemoryRequirements* pMemoryRequirements) __attribute__ ((weak)); + VkResult gen11_BindImageMemory(VkDevice device, VkImage image, VkDeviceMemory memory, VkDeviceSize memoryOffset) __attribute__ ((weak)); + void gen11_GetImageSparseMemoryRequirements(VkDevice device, VkImage image, uint32_t* pSparseMemoryRequirementCount, VkSparseImageMemoryRequirements* pSparseMemoryRequirements) __attribute__ ((weak)); + VkResult gen11_QueueBindSparse(VkQueue queue, uint32_t bindInfoCount, const VkBindSparseInfo* pBindInfo, VkFence fence) __attribute__ ((weak)); + VkResult gen11_CreateFence(VkDevice device, const VkFenceCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence) __attribute__ ((weak)); + void gen11_DestroyFence(VkDevice device, VkFence fence, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen11_ResetFences(VkDevice device, uint32_t fenceCount, const VkFence* pFences) __attribute__ ((weak)); + VkResult gen11_GetFenceStatus(VkDevice device, VkFence fence) __attribute__ ((weak)); + VkResult gen11_WaitForFences(VkDevice device, uint32_t fenceCount, const VkFence* pFences, VkBool32 waitAll, uint64_t timeout) __attribute__ ((weak)); + VkResult gen11_CreateSemaphore(VkDevice device, const VkSemaphoreCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSemaphore* pSemaphore) __attribute__ ((weak)); + void gen11_DestroySemaphore(VkDevice device, VkSemaphore semaphore, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen11_CreateEvent(VkDevice device, const VkEventCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkEvent* pEvent) __attribute__ ((weak)); + void gen11_DestroyEvent(VkDevice device, VkEvent event, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen11_GetEventStatus(VkDevice device, VkEvent event) __attribute__ ((weak)); + VkResult gen11_SetEvent(VkDevice device, VkEvent event) __attribute__ ((weak)); + VkResult gen11_ResetEvent(VkDevice device, VkEvent event) __attribute__ ((weak)); + VkResult gen11_CreateQueryPool(VkDevice device, const VkQueryPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkQueryPool* pQueryPool) __attribute__ ((weak)); + void gen11_DestroyQueryPool(VkDevice device, VkQueryPool queryPool, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen11_GetQueryPoolResults(VkDevice device, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount, size_t dataSize, void* pData, VkDeviceSize stride, VkQueryResultFlags flags) __attribute__ ((weak)); + VkResult gen11_CreateBuffer(VkDevice device, const VkBufferCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkBuffer* pBuffer) __attribute__ ((weak)); + void gen11_DestroyBuffer(VkDevice device, VkBuffer buffer, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen11_CreateBufferView(VkDevice device, const VkBufferViewCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkBufferView* pView) __attribute__ ((weak)); + void gen11_DestroyBufferView(VkDevice device, VkBufferView bufferView, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen11_CreateImage(VkDevice device, const VkImageCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkImage* pImage) __attribute__ ((weak)); + void gen11_DestroyImage(VkDevice device, VkImage image, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + void gen11_GetImageSubresourceLayout(VkDevice device, VkImage image, const VkImageSubresource* pSubresource, VkSubresourceLayout* pLayout) __attribute__ ((weak)); + VkResult gen11_CreateImageView(VkDevice device, const VkImageViewCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkImageView* pView) __attribute__ ((weak)); + void gen11_DestroyImageView(VkDevice device, VkImageView imageView, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen11_CreateShaderModule(VkDevice device, const VkShaderModuleCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkShaderModule* pShaderModule) __attribute__ ((weak)); + void gen11_DestroyShaderModule(VkDevice device, VkShaderModule shaderModule, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen11_CreatePipelineCache(VkDevice device, const VkPipelineCacheCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkPipelineCache* pPipelineCache) __attribute__ ((weak)); + void gen11_DestroyPipelineCache(VkDevice device, VkPipelineCache pipelineCache, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen11_GetPipelineCacheData(VkDevice device, VkPipelineCache pipelineCache, size_t* pDataSize, void* pData) __attribute__ ((weak)); + VkResult gen11_MergePipelineCaches(VkDevice device, VkPipelineCache dstCache, uint32_t srcCacheCount, const VkPipelineCache* pSrcCaches) __attribute__ ((weak)); + VkResult gen11_CreateGraphicsPipelines(VkDevice device, VkPipelineCache pipelineCache, uint32_t createInfoCount, const VkGraphicsPipelineCreateInfo* pCreateInfos, const VkAllocationCallbacks* pAllocator, VkPipeline* pPipelines) __attribute__ ((weak)); + VkResult gen11_CreateComputePipelines(VkDevice device, VkPipelineCache pipelineCache, uint32_t createInfoCount, const VkComputePipelineCreateInfo* pCreateInfos, const VkAllocationCallbacks* pAllocator, VkPipeline* pPipelines) __attribute__ ((weak)); + void gen11_DestroyPipeline(VkDevice device, VkPipeline pipeline, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen11_CreatePipelineLayout(VkDevice device, const VkPipelineLayoutCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkPipelineLayout* pPipelineLayout) __attribute__ ((weak)); + void gen11_DestroyPipelineLayout(VkDevice device, VkPipelineLayout pipelineLayout, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen11_CreateSampler(VkDevice device, const VkSamplerCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSampler* pSampler) __attribute__ ((weak)); + void gen11_DestroySampler(VkDevice device, VkSampler sampler, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen11_CreateDescriptorSetLayout(VkDevice device, const VkDescriptorSetLayoutCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorSetLayout* pSetLayout) __attribute__ ((weak)); + void gen11_DestroyDescriptorSetLayout(VkDevice device, VkDescriptorSetLayout descriptorSetLayout, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen11_CreateDescriptorPool(VkDevice device, const VkDescriptorPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorPool* pDescriptorPool) __attribute__ ((weak)); + void gen11_DestroyDescriptorPool(VkDevice device, VkDescriptorPool descriptorPool, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen11_ResetDescriptorPool(VkDevice device, VkDescriptorPool descriptorPool, VkDescriptorPoolResetFlags flags) __attribute__ ((weak)); + VkResult gen11_AllocateDescriptorSets(VkDevice device, const VkDescriptorSetAllocateInfo* pAllocateInfo, VkDescriptorSet* pDescriptorSets) __attribute__ ((weak)); + VkResult gen11_FreeDescriptorSets(VkDevice device, VkDescriptorPool descriptorPool, uint32_t descriptorSetCount, const VkDescriptorSet* pDescriptorSets) __attribute__ ((weak)); + void gen11_UpdateDescriptorSets(VkDevice device, uint32_t descriptorWriteCount, const VkWriteDescriptorSet* pDescriptorWrites, uint32_t descriptorCopyCount, const VkCopyDescriptorSet* pDescriptorCopies) __attribute__ ((weak)); + VkResult gen11_CreateFramebuffer(VkDevice device, const VkFramebufferCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkFramebuffer* pFramebuffer) __attribute__ ((weak)); + void gen11_DestroyFramebuffer(VkDevice device, VkFramebuffer framebuffer, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen11_CreateRenderPass(VkDevice device, const VkRenderPassCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkRenderPass* pRenderPass) __attribute__ ((weak)); + void gen11_DestroyRenderPass(VkDevice device, VkRenderPass renderPass, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + void gen11_GetRenderAreaGranularity(VkDevice device, VkRenderPass renderPass, VkExtent2D* pGranularity) __attribute__ ((weak)); + VkResult gen11_CreateCommandPool(VkDevice device, const VkCommandPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkCommandPool* pCommandPool) __attribute__ ((weak)); + void gen11_DestroyCommandPool(VkDevice device, VkCommandPool commandPool, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen11_ResetCommandPool(VkDevice device, VkCommandPool commandPool, VkCommandPoolResetFlags flags) __attribute__ ((weak)); + VkResult gen11_AllocateCommandBuffers(VkDevice device, const VkCommandBufferAllocateInfo* pAllocateInfo, VkCommandBuffer* pCommandBuffers) __attribute__ ((weak)); + void gen11_FreeCommandBuffers(VkDevice device, VkCommandPool commandPool, uint32_t commandBufferCount, const VkCommandBuffer* pCommandBuffers) __attribute__ ((weak)); + VkResult gen11_BeginCommandBuffer(VkCommandBuffer commandBuffer, const VkCommandBufferBeginInfo* pBeginInfo) __attribute__ ((weak)); + VkResult gen11_EndCommandBuffer(VkCommandBuffer commandBuffer) __attribute__ ((weak)); + VkResult gen11_ResetCommandBuffer(VkCommandBuffer commandBuffer, VkCommandBufferResetFlags flags) __attribute__ ((weak)); + void gen11_CmdBindPipeline(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipeline pipeline) __attribute__ ((weak)); + void gen11_CmdSetViewport(VkCommandBuffer commandBuffer, uint32_t firstViewport, uint32_t viewportCount, const VkViewport* pViewports) __attribute__ ((weak)); + void gen11_CmdSetScissor(VkCommandBuffer commandBuffer, uint32_t firstScissor, uint32_t scissorCount, const VkRect2D* pScissors) __attribute__ ((weak)); + void gen11_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth) __attribute__ ((weak)); + void gen11_CmdSetDepthBias(VkCommandBuffer commandBuffer, float depthBiasConstantFactor, float depthBiasClamp, float depthBiasSlopeFactor) __attribute__ ((weak)); + void gen11_CmdSetBlendConstants(VkCommandBuffer commandBuffer, const float blendConstants[4]) __attribute__ ((weak)); + void gen11_CmdSetDepthBounds(VkCommandBuffer commandBuffer, float minDepthBounds, float maxDepthBounds) __attribute__ ((weak)); + void gen11_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t compareMask) __attribute__ ((weak)); + void gen11_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t writeMask) __attribute__ ((weak)); + void gen11_CmdSetStencilReference(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t reference) __attribute__ ((weak)); + void gen11_CmdBindDescriptorSets(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipelineLayout layout, uint32_t firstSet, uint32_t descriptorSetCount, const VkDescriptorSet* pDescriptorSets, uint32_t dynamicOffsetCount, const uint32_t* pDynamicOffsets) __attribute__ ((weak)); + void gen11_CmdBindIndexBuffer(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkIndexType indexType) __attribute__ ((weak)); + void gen11_CmdBindVertexBuffers(VkCommandBuffer commandBuffer, uint32_t firstBinding, uint32_t bindingCount, const VkBuffer* pBuffers, const VkDeviceSize* pOffsets) __attribute__ ((weak)); + void gen11_CmdDraw(VkCommandBuffer commandBuffer, uint32_t vertexCount, uint32_t instanceCount, uint32_t firstVertex, uint32_t firstInstance) __attribute__ ((weak)); + void gen11_CmdDrawIndexed(VkCommandBuffer commandBuffer, uint32_t indexCount, uint32_t instanceCount, uint32_t firstIndex, int32_t vertexOffset, uint32_t firstInstance) __attribute__ ((weak)); + void gen11_CmdDrawIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, uint32_t drawCount, uint32_t stride) __attribute__ ((weak)); + void gen11_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, uint32_t drawCount, uint32_t stride) __attribute__ ((weak)); + void gen11_CmdDispatch(VkCommandBuffer commandBuffer, uint32_t groupCountX, uint32_t groupCountY, uint32_t groupCountZ) __attribute__ ((weak)); + void gen11_CmdDispatchIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset) __attribute__ ((weak)); + void gen11_CmdCopyBuffer(VkCommandBuffer commandBuffer, VkBuffer srcBuffer, VkBuffer dstBuffer, uint32_t regionCount, const VkBufferCopy* pRegions) __attribute__ ((weak)); + void gen11_CmdCopyImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageCopy* pRegions) __attribute__ ((weak)); + void gen11_CmdBlitImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageBlit* pRegions, VkFilter filter) __attribute__ ((weak)); + void gen11_CmdCopyBufferToImage(VkCommandBuffer commandBuffer, VkBuffer srcBuffer, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkBufferImageCopy* pRegions) __attribute__ ((weak)); + void gen11_CmdCopyImageToBuffer(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkBuffer dstBuffer, uint32_t regionCount, const VkBufferImageCopy* pRegions) __attribute__ ((weak)); + void gen11_CmdUpdateBuffer(VkCommandBuffer commandBuffer, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize dataSize, const void* pData) __attribute__ ((weak)); + void gen11_CmdFillBuffer(VkCommandBuffer commandBuffer, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize size, uint32_t data) __attribute__ ((weak)); + void gen11_CmdClearColorImage(VkCommandBuffer commandBuffer, VkImage image, VkImageLayout imageLayout, const VkClearColorValue* pColor, uint32_t rangeCount, const VkImageSubresourceRange* pRanges) __attribute__ ((weak)); + void gen11_CmdClearDepthStencilImage(VkCommandBuffer commandBuffer, VkImage image, VkImageLayout imageLayout, const VkClearDepthStencilValue* pDepthStencil, uint32_t rangeCount, const VkImageSubresourceRange* pRanges) __attribute__ ((weak)); + void gen11_CmdClearAttachments(VkCommandBuffer commandBuffer, uint32_t attachmentCount, const VkClearAttachment* pAttachments, uint32_t rectCount, const VkClearRect* pRects) __attribute__ ((weak)); + void gen11_CmdResolveImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageResolve* pRegions) __attribute__ ((weak)); + void gen11_CmdSetEvent(VkCommandBuffer commandBuffer, VkEvent event, VkPipelineStageFlags stageMask) __attribute__ ((weak)); + void gen11_CmdResetEvent(VkCommandBuffer commandBuffer, VkEvent event, VkPipelineStageFlags stageMask) __attribute__ ((weak)); + void gen11_CmdWaitEvents(VkCommandBuffer commandBuffer, uint32_t eventCount, const VkEvent* pEvents, VkPipelineStageFlags srcStageMask, VkPipelineStageFlags dstStageMask, uint32_t memoryBarrierCount, const VkMemoryBarrier* pMemoryBarriers, uint32_t bufferMemoryBarrierCount, const VkBufferMemoryBarrier* pBufferMemoryBarriers, uint32_t imageMemoryBarrierCount, const VkImageMemoryBarrier* pImageMemoryBarriers) __attribute__ ((weak)); + void gen11_CmdPipelineBarrier(VkCommandBuffer commandBuffer, VkPipelineStageFlags srcStageMask, VkPipelineStageFlags dstStageMask, VkDependencyFlags dependencyFlags, uint32_t memoryBarrierCount, const VkMemoryBarrier* pMemoryBarriers, uint32_t bufferMemoryBarrierCount, const VkBufferMemoryBarrier* pBufferMemoryBarriers, uint32_t imageMemoryBarrierCount, const VkImageMemoryBarrier* pImageMemoryBarriers) __attribute__ ((weak)); + void gen11_CmdBeginQuery(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, VkQueryControlFlags flags) __attribute__ ((weak)); + void gen11_CmdEndQuery(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query) __attribute__ ((weak)); + void gen11_CmdBeginConditionalRenderingEXT(VkCommandBuffer commandBuffer, const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin) __attribute__ ((weak)); + void gen11_CmdEndConditionalRenderingEXT(VkCommandBuffer commandBuffer) __attribute__ ((weak)); + void gen11_CmdResetQueryPool(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount) __attribute__ ((weak)); + void gen11_CmdWriteTimestamp(VkCommandBuffer commandBuffer, VkPipelineStageFlagBits pipelineStage, VkQueryPool queryPool, uint32_t query) __attribute__ ((weak)); + void gen11_CmdCopyQueryPoolResults(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize stride, VkQueryResultFlags flags) __attribute__ ((weak)); + void gen11_CmdPushConstants(VkCommandBuffer commandBuffer, VkPipelineLayout layout, VkShaderStageFlags stageFlags, uint32_t offset, uint32_t size, const void* pValues) __attribute__ ((weak)); + void gen11_CmdBeginRenderPass(VkCommandBuffer commandBuffer, const VkRenderPassBeginInfo* pRenderPassBegin, VkSubpassContents contents) __attribute__ ((weak)); + void gen11_CmdNextSubpass(VkCommandBuffer commandBuffer, VkSubpassContents contents) __attribute__ ((weak)); + void gen11_CmdEndRenderPass(VkCommandBuffer commandBuffer) __attribute__ ((weak)); + void gen11_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCount, const VkCommandBuffer* pCommandBuffers) __attribute__ ((weak)); + VkResult gen11_CreateSwapchainKHR(VkDevice device, const VkSwapchainCreateInfoKHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSwapchainKHR* pSwapchain) __attribute__ ((weak)); + void gen11_DestroySwapchainKHR(VkDevice device, VkSwapchainKHR swapchain, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + VkResult gen11_GetSwapchainImagesKHR(VkDevice device, VkSwapchainKHR swapchain, uint32_t* pSwapchainImageCount, VkImage* pSwapchainImages) __attribute__ ((weak)); + VkResult gen11_AcquireNextImageKHR(VkDevice device, VkSwapchainKHR swapchain, uint64_t timeout, VkSemaphore semaphore, VkFence fence, uint32_t* pImageIndex) __attribute__ ((weak)); + VkResult gen11_QueuePresentKHR(VkQueue queue, const VkPresentInfoKHR* pPresentInfo) __attribute__ ((weak)); + void gen11_CmdPushDescriptorSetKHR(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipelineLayout layout, uint32_t set, uint32_t descriptorWriteCount, const VkWriteDescriptorSet* pDescriptorWrites) __attribute__ ((weak)); + void gen11_TrimCommandPool(VkDevice device, VkCommandPool commandPool, VkCommandPoolTrimFlags flags) __attribute__ ((weak)); + VkResult gen11_GetMemoryFdKHR(VkDevice device, const VkMemoryGetFdInfoKHR* pGetFdInfo, int* pFd) __attribute__ ((weak)); + VkResult gen11_GetMemoryFdPropertiesKHR(VkDevice device, VkExternalMemoryHandleTypeFlagBits handleType, int fd, VkMemoryFdPropertiesKHR* pMemoryFdProperties) __attribute__ ((weak)); + VkResult gen11_GetSemaphoreFdKHR(VkDevice device, const VkSemaphoreGetFdInfoKHR* pGetFdInfo, int* pFd) __attribute__ ((weak)); + VkResult gen11_ImportSemaphoreFdKHR(VkDevice device, const VkImportSemaphoreFdInfoKHR* pImportSemaphoreFdInfo) __attribute__ ((weak)); + VkResult gen11_GetFenceFdKHR(VkDevice device, const VkFenceGetFdInfoKHR* pGetFdInfo, int* pFd) __attribute__ ((weak)); + VkResult gen11_ImportFenceFdKHR(VkDevice device, const VkImportFenceFdInfoKHR* pImportFenceFdInfo) __attribute__ ((weak)); + VkResult gen11_DisplayPowerControlEXT(VkDevice device, VkDisplayKHR display, const VkDisplayPowerInfoEXT* pDisplayPowerInfo) __attribute__ ((weak)); + VkResult gen11_RegisterDeviceEventEXT(VkDevice device, const VkDeviceEventInfoEXT* pDeviceEventInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence) __attribute__ ((weak)); + VkResult gen11_RegisterDisplayEventEXT(VkDevice device, VkDisplayKHR display, const VkDisplayEventInfoEXT* pDisplayEventInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence) __attribute__ ((weak)); + VkResult gen11_GetSwapchainCounterEXT(VkDevice device, VkSwapchainKHR swapchain, VkSurfaceCounterFlagBitsEXT counter, uint64_t* pCounterValue) __attribute__ ((weak)); + void gen11_GetDeviceGroupPeerMemoryFeatures(VkDevice device, uint32_t heapIndex, uint32_t localDeviceIndex, uint32_t remoteDeviceIndex, VkPeerMemoryFeatureFlags* pPeerMemoryFeatures) __attribute__ ((weak)); + VkResult gen11_BindBufferMemory2(VkDevice device, uint32_t bindInfoCount, const VkBindBufferMemoryInfo* pBindInfos) __attribute__ ((weak)); + VkResult gen11_BindImageMemory2(VkDevice device, uint32_t bindInfoCount, const VkBindImageMemoryInfo* pBindInfos) __attribute__ ((weak)); + void gen11_CmdSetDeviceMask(VkCommandBuffer commandBuffer, uint32_t deviceMask) __attribute__ ((weak)); + VkResult gen11_GetDeviceGroupPresentCapabilitiesKHR(VkDevice device, VkDeviceGroupPresentCapabilitiesKHR* pDeviceGroupPresentCapabilities) __attribute__ ((weak)); + VkResult gen11_GetDeviceGroupSurfacePresentModesKHR(VkDevice device, VkSurfaceKHR surface, VkDeviceGroupPresentModeFlagsKHR* pModes) __attribute__ ((weak)); + VkResult gen11_AcquireNextImage2KHR(VkDevice device, const VkAcquireNextImageInfoKHR* pAcquireInfo, uint32_t* pImageIndex) __attribute__ ((weak)); + void gen11_CmdDispatchBase(VkCommandBuffer commandBuffer, uint32_t baseGroupX, uint32_t baseGroupY, uint32_t baseGroupZ, uint32_t groupCountX, uint32_t groupCountY, uint32_t groupCountZ) __attribute__ ((weak)); + VkResult gen11_CreateDescriptorUpdateTemplate(VkDevice device, const VkDescriptorUpdateTemplateCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorUpdateTemplate* pDescriptorUpdateTemplate) __attribute__ ((weak)); + void gen11_DestroyDescriptorUpdateTemplate(VkDevice device, VkDescriptorUpdateTemplate descriptorUpdateTemplate, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + void gen11_UpdateDescriptorSetWithTemplate(VkDevice device, VkDescriptorSet descriptorSet, VkDescriptorUpdateTemplate descriptorUpdateTemplate, const void* pData) __attribute__ ((weak)); + void gen11_CmdPushDescriptorSetWithTemplateKHR(VkCommandBuffer commandBuffer, VkDescriptorUpdateTemplate descriptorUpdateTemplate, VkPipelineLayout layout, uint32_t set, const void* pData) __attribute__ ((weak)); + void gen11_GetBufferMemoryRequirements2(VkDevice device, const VkBufferMemoryRequirementsInfo2* pInfo, VkMemoryRequirements2* pMemoryRequirements) __attribute__ ((weak)); + void gen11_GetImageMemoryRequirements2(VkDevice device, const VkImageMemoryRequirementsInfo2* pInfo, VkMemoryRequirements2* pMemoryRequirements) __attribute__ ((weak)); + void gen11_GetImageSparseMemoryRequirements2(VkDevice device, const VkImageSparseMemoryRequirementsInfo2* pInfo, uint32_t* pSparseMemoryRequirementCount, VkSparseImageMemoryRequirements2* pSparseMemoryRequirements) __attribute__ ((weak)); + VkResult gen11_CreateSamplerYcbcrConversion(VkDevice device, const VkSamplerYcbcrConversionCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSamplerYcbcrConversion* pYcbcrConversion) __attribute__ ((weak)); + void gen11_DestroySamplerYcbcrConversion(VkDevice device, VkSamplerYcbcrConversion ycbcrConversion, const VkAllocationCallbacks* pAllocator) __attribute__ ((weak)); + void gen11_GetDeviceQueue2(VkDevice device, const VkDeviceQueueInfo2* pQueueInfo, VkQueue* pQueue) __attribute__ ((weak)); + void gen11_GetDescriptorSetLayoutSupport(VkDevice device, const VkDescriptorSetLayoutCreateInfo* pCreateInfo, VkDescriptorSetLayoutSupport* pSupport) __attribute__ ((weak)); + #ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult gen11_GetSwapchainGrallocUsageANDROID(VkDevice device, VkFormat format, VkImageUsageFlags imageUsage, int* grallocUsage) __attribute__ ((weak)); +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult gen11_AcquireImageANDROID(VkDevice device, VkImage image, int nativeFenceFd, VkSemaphore semaphore, VkFence fence) __attribute__ ((weak)); +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult gen11_QueueSignalReleaseImageANDROID(VkQueue queue, uint32_t waitSemaphoreCount, const VkSemaphore* pWaitSemaphores, VkImage image, int* pNativeFenceFd) __attribute__ ((weak)); +#endif // VK_USE_PLATFORM_ANDROID_KHR + VkResult gen11_GetCalibratedTimestampsEXT(VkDevice device, uint32_t timestampCount, const VkCalibratedTimestampInfoEXT* pTimestampInfos, uint64_t* pTimestamps, uint64_t* pMaxDeviation) __attribute__ ((weak)); + VkResult gen11_CreateRenderPass2KHR(VkDevice device, const VkRenderPassCreateInfo2KHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkRenderPass* pRenderPass) __attribute__ ((weak)); + void gen11_CmdBeginRenderPass2KHR(VkCommandBuffer commandBuffer, const VkRenderPassBeginInfo* pRenderPassBegin, const VkSubpassBeginInfoKHR* pSubpassBeginInfo) __attribute__ ((weak)); + void gen11_CmdNextSubpass2KHR(VkCommandBuffer commandBuffer, const VkSubpassBeginInfoKHR* pSubpassBeginInfo, const VkSubpassEndInfoKHR* pSubpassEndInfo) __attribute__ ((weak)); + void gen11_CmdEndRenderPass2KHR(VkCommandBuffer commandBuffer, const VkSubpassEndInfoKHR* pSubpassEndInfo) __attribute__ ((weak)); +#ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult gen11_GetAndroidHardwareBufferPropertiesANDROID(VkDevice device, const struct AHardwareBuffer* buffer, VkAndroidHardwareBufferPropertiesANDROID* pProperties) __attribute__ ((weak)); +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult gen11_GetMemoryAndroidHardwareBufferANDROID(VkDevice device, const VkMemoryGetAndroidHardwareBufferInfoANDROID* pInfo, struct AHardwareBuffer** pBuffer) __attribute__ ((weak)); +#endif // VK_USE_PLATFORM_ANDROID_KHR + void gen11_CmdDrawIndirectCountKHR(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkBuffer countBuffer, VkDeviceSize countBufferOffset, uint32_t maxDrawCount, uint32_t stride) __attribute__ ((weak)); + void gen11_CmdDrawIndexedIndirectCountKHR(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkBuffer countBuffer, VkDeviceSize countBufferOffset, uint32_t maxDrawCount, uint32_t stride) __attribute__ ((weak)); + void gen11_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer, uint32_t firstBinding, uint32_t bindingCount, const VkBuffer* pBuffers, const VkDeviceSize* pOffsets, const VkDeviceSize* pSizes) __attribute__ ((weak)); + void gen11_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstCounterBuffer, uint32_t counterBufferCount, const VkBuffer* pCounterBuffers, const VkDeviceSize* pCounterBufferOffsets) __attribute__ ((weak)); + void gen11_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstCounterBuffer, uint32_t counterBufferCount, const VkBuffer* pCounterBuffers, const VkDeviceSize* pCounterBufferOffsets) __attribute__ ((weak)); + void gen11_CmdBeginQueryIndexedEXT(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, VkQueryControlFlags flags, uint32_t index) __attribute__ ((weak)); + void gen11_CmdEndQueryIndexedEXT(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, uint32_t index) __attribute__ ((weak)); + void gen11_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer, uint32_t instanceCount, uint32_t firstInstance, VkBuffer counterBuffer, VkDeviceSize counterBufferOffset, uint32_t counterOffset, uint32_t vertexStride) __attribute__ ((weak)); + VkResult gen11_CreateDmaBufImageINTEL(VkDevice device, const VkDmaBufImageCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDeviceMemory* pMem, VkImage* pImage) __attribute__ ((weak)); + + const struct anv_device_dispatch_table gen11_device_dispatch_table = { + .vkGetDeviceProcAddr = gen11_GetDeviceProcAddr, + .vkDestroyDevice = gen11_DestroyDevice, + .vkGetDeviceQueue = gen11_GetDeviceQueue, + .vkQueueSubmit = gen11_QueueSubmit, + .vkQueueWaitIdle = gen11_QueueWaitIdle, + .vkDeviceWaitIdle = gen11_DeviceWaitIdle, + .vkAllocateMemory = gen11_AllocateMemory, + .vkFreeMemory = gen11_FreeMemory, + .vkMapMemory = gen11_MapMemory, + .vkUnmapMemory = gen11_UnmapMemory, + .vkFlushMappedMemoryRanges = gen11_FlushMappedMemoryRanges, + .vkInvalidateMappedMemoryRanges = gen11_InvalidateMappedMemoryRanges, + .vkGetDeviceMemoryCommitment = gen11_GetDeviceMemoryCommitment, + .vkGetBufferMemoryRequirements = gen11_GetBufferMemoryRequirements, + .vkBindBufferMemory = gen11_BindBufferMemory, + .vkGetImageMemoryRequirements = gen11_GetImageMemoryRequirements, + .vkBindImageMemory = gen11_BindImageMemory, + .vkGetImageSparseMemoryRequirements = gen11_GetImageSparseMemoryRequirements, + .vkQueueBindSparse = gen11_QueueBindSparse, + .vkCreateFence = gen11_CreateFence, + .vkDestroyFence = gen11_DestroyFence, + .vkResetFences = gen11_ResetFences, + .vkGetFenceStatus = gen11_GetFenceStatus, + .vkWaitForFences = gen11_WaitForFences, + .vkCreateSemaphore = gen11_CreateSemaphore, + .vkDestroySemaphore = gen11_DestroySemaphore, + .vkCreateEvent = gen11_CreateEvent, + .vkDestroyEvent = gen11_DestroyEvent, + .vkGetEventStatus = gen11_GetEventStatus, + .vkSetEvent = gen11_SetEvent, + .vkResetEvent = gen11_ResetEvent, + .vkCreateQueryPool = gen11_CreateQueryPool, + .vkDestroyQueryPool = gen11_DestroyQueryPool, + .vkGetQueryPoolResults = gen11_GetQueryPoolResults, + .vkCreateBuffer = gen11_CreateBuffer, + .vkDestroyBuffer = gen11_DestroyBuffer, + .vkCreateBufferView = gen11_CreateBufferView, + .vkDestroyBufferView = gen11_DestroyBufferView, + .vkCreateImage = gen11_CreateImage, + .vkDestroyImage = gen11_DestroyImage, + .vkGetImageSubresourceLayout = gen11_GetImageSubresourceLayout, + .vkCreateImageView = gen11_CreateImageView, + .vkDestroyImageView = gen11_DestroyImageView, + .vkCreateShaderModule = gen11_CreateShaderModule, + .vkDestroyShaderModule = gen11_DestroyShaderModule, + .vkCreatePipelineCache = gen11_CreatePipelineCache, + .vkDestroyPipelineCache = gen11_DestroyPipelineCache, + .vkGetPipelineCacheData = gen11_GetPipelineCacheData, + .vkMergePipelineCaches = gen11_MergePipelineCaches, + .vkCreateGraphicsPipelines = gen11_CreateGraphicsPipelines, + .vkCreateComputePipelines = gen11_CreateComputePipelines, + .vkDestroyPipeline = gen11_DestroyPipeline, + .vkCreatePipelineLayout = gen11_CreatePipelineLayout, + .vkDestroyPipelineLayout = gen11_DestroyPipelineLayout, + .vkCreateSampler = gen11_CreateSampler, + .vkDestroySampler = gen11_DestroySampler, + .vkCreateDescriptorSetLayout = gen11_CreateDescriptorSetLayout, + .vkDestroyDescriptorSetLayout = gen11_DestroyDescriptorSetLayout, + .vkCreateDescriptorPool = gen11_CreateDescriptorPool, + .vkDestroyDescriptorPool = gen11_DestroyDescriptorPool, + .vkResetDescriptorPool = gen11_ResetDescriptorPool, + .vkAllocateDescriptorSets = gen11_AllocateDescriptorSets, + .vkFreeDescriptorSets = gen11_FreeDescriptorSets, + .vkUpdateDescriptorSets = gen11_UpdateDescriptorSets, + .vkCreateFramebuffer = gen11_CreateFramebuffer, + .vkDestroyFramebuffer = gen11_DestroyFramebuffer, + .vkCreateRenderPass = gen11_CreateRenderPass, + .vkDestroyRenderPass = gen11_DestroyRenderPass, + .vkGetRenderAreaGranularity = gen11_GetRenderAreaGranularity, + .vkCreateCommandPool = gen11_CreateCommandPool, + .vkDestroyCommandPool = gen11_DestroyCommandPool, + .vkResetCommandPool = gen11_ResetCommandPool, + .vkAllocateCommandBuffers = gen11_AllocateCommandBuffers, + .vkFreeCommandBuffers = gen11_FreeCommandBuffers, + .vkBeginCommandBuffer = gen11_BeginCommandBuffer, + .vkEndCommandBuffer = gen11_EndCommandBuffer, + .vkResetCommandBuffer = gen11_ResetCommandBuffer, + .vkCmdBindPipeline = gen11_CmdBindPipeline, + .vkCmdSetViewport = gen11_CmdSetViewport, + .vkCmdSetScissor = gen11_CmdSetScissor, + .vkCmdSetLineWidth = gen11_CmdSetLineWidth, + .vkCmdSetDepthBias = gen11_CmdSetDepthBias, + .vkCmdSetBlendConstants = gen11_CmdSetBlendConstants, + .vkCmdSetDepthBounds = gen11_CmdSetDepthBounds, + .vkCmdSetStencilCompareMask = gen11_CmdSetStencilCompareMask, + .vkCmdSetStencilWriteMask = gen11_CmdSetStencilWriteMask, + .vkCmdSetStencilReference = gen11_CmdSetStencilReference, + .vkCmdBindDescriptorSets = gen11_CmdBindDescriptorSets, + .vkCmdBindIndexBuffer = gen11_CmdBindIndexBuffer, + .vkCmdBindVertexBuffers = gen11_CmdBindVertexBuffers, + .vkCmdDraw = gen11_CmdDraw, + .vkCmdDrawIndexed = gen11_CmdDrawIndexed, + .vkCmdDrawIndirect = gen11_CmdDrawIndirect, + .vkCmdDrawIndexedIndirect = gen11_CmdDrawIndexedIndirect, + .vkCmdDispatch = gen11_CmdDispatch, + .vkCmdDispatchIndirect = gen11_CmdDispatchIndirect, + .vkCmdCopyBuffer = gen11_CmdCopyBuffer, + .vkCmdCopyImage = gen11_CmdCopyImage, + .vkCmdBlitImage = gen11_CmdBlitImage, + .vkCmdCopyBufferToImage = gen11_CmdCopyBufferToImage, + .vkCmdCopyImageToBuffer = gen11_CmdCopyImageToBuffer, + .vkCmdUpdateBuffer = gen11_CmdUpdateBuffer, + .vkCmdFillBuffer = gen11_CmdFillBuffer, + .vkCmdClearColorImage = gen11_CmdClearColorImage, + .vkCmdClearDepthStencilImage = gen11_CmdClearDepthStencilImage, + .vkCmdClearAttachments = gen11_CmdClearAttachments, + .vkCmdResolveImage = gen11_CmdResolveImage, + .vkCmdSetEvent = gen11_CmdSetEvent, + .vkCmdResetEvent = gen11_CmdResetEvent, + .vkCmdWaitEvents = gen11_CmdWaitEvents, + .vkCmdPipelineBarrier = gen11_CmdPipelineBarrier, + .vkCmdBeginQuery = gen11_CmdBeginQuery, + .vkCmdEndQuery = gen11_CmdEndQuery, + .vkCmdBeginConditionalRenderingEXT = gen11_CmdBeginConditionalRenderingEXT, + .vkCmdEndConditionalRenderingEXT = gen11_CmdEndConditionalRenderingEXT, + .vkCmdResetQueryPool = gen11_CmdResetQueryPool, + .vkCmdWriteTimestamp = gen11_CmdWriteTimestamp, + .vkCmdCopyQueryPoolResults = gen11_CmdCopyQueryPoolResults, + .vkCmdPushConstants = gen11_CmdPushConstants, + .vkCmdBeginRenderPass = gen11_CmdBeginRenderPass, + .vkCmdNextSubpass = gen11_CmdNextSubpass, + .vkCmdEndRenderPass = gen11_CmdEndRenderPass, + .vkCmdExecuteCommands = gen11_CmdExecuteCommands, + .vkCreateSwapchainKHR = gen11_CreateSwapchainKHR, + .vkDestroySwapchainKHR = gen11_DestroySwapchainKHR, + .vkGetSwapchainImagesKHR = gen11_GetSwapchainImagesKHR, + .vkAcquireNextImageKHR = gen11_AcquireNextImageKHR, + .vkQueuePresentKHR = gen11_QueuePresentKHR, + .vkCmdPushDescriptorSetKHR = gen11_CmdPushDescriptorSetKHR, + .vkTrimCommandPool = gen11_TrimCommandPool, + .vkTrimCommandPoolKHR = gen11_TrimCommandPool, + .vkGetMemoryFdKHR = gen11_GetMemoryFdKHR, + .vkGetMemoryFdPropertiesKHR = gen11_GetMemoryFdPropertiesKHR, + .vkGetSemaphoreFdKHR = gen11_GetSemaphoreFdKHR, + .vkImportSemaphoreFdKHR = gen11_ImportSemaphoreFdKHR, + .vkGetFenceFdKHR = gen11_GetFenceFdKHR, + .vkImportFenceFdKHR = gen11_ImportFenceFdKHR, + .vkDisplayPowerControlEXT = gen11_DisplayPowerControlEXT, + .vkRegisterDeviceEventEXT = gen11_RegisterDeviceEventEXT, + .vkRegisterDisplayEventEXT = gen11_RegisterDisplayEventEXT, + .vkGetSwapchainCounterEXT = gen11_GetSwapchainCounterEXT, + .vkGetDeviceGroupPeerMemoryFeatures = gen11_GetDeviceGroupPeerMemoryFeatures, + .vkGetDeviceGroupPeerMemoryFeaturesKHR = gen11_GetDeviceGroupPeerMemoryFeatures, + .vkBindBufferMemory2 = gen11_BindBufferMemory2, + .vkBindBufferMemory2KHR = gen11_BindBufferMemory2, + .vkBindImageMemory2 = gen11_BindImageMemory2, + .vkBindImageMemory2KHR = gen11_BindImageMemory2, + .vkCmdSetDeviceMask = gen11_CmdSetDeviceMask, + .vkCmdSetDeviceMaskKHR = gen11_CmdSetDeviceMask, + .vkGetDeviceGroupPresentCapabilitiesKHR = gen11_GetDeviceGroupPresentCapabilitiesKHR, + .vkGetDeviceGroupSurfacePresentModesKHR = gen11_GetDeviceGroupSurfacePresentModesKHR, + .vkAcquireNextImage2KHR = gen11_AcquireNextImage2KHR, + .vkCmdDispatchBase = gen11_CmdDispatchBase, + .vkCmdDispatchBaseKHR = gen11_CmdDispatchBase, + .vkCreateDescriptorUpdateTemplate = gen11_CreateDescriptorUpdateTemplate, + .vkCreateDescriptorUpdateTemplateKHR = gen11_CreateDescriptorUpdateTemplate, + .vkDestroyDescriptorUpdateTemplate = gen11_DestroyDescriptorUpdateTemplate, + .vkDestroyDescriptorUpdateTemplateKHR = gen11_DestroyDescriptorUpdateTemplate, + .vkUpdateDescriptorSetWithTemplate = gen11_UpdateDescriptorSetWithTemplate, + .vkUpdateDescriptorSetWithTemplateKHR = gen11_UpdateDescriptorSetWithTemplate, + .vkCmdPushDescriptorSetWithTemplateKHR = gen11_CmdPushDescriptorSetWithTemplateKHR, + .vkGetBufferMemoryRequirements2 = gen11_GetBufferMemoryRequirements2, + .vkGetBufferMemoryRequirements2KHR = gen11_GetBufferMemoryRequirements2, + .vkGetImageMemoryRequirements2 = gen11_GetImageMemoryRequirements2, + .vkGetImageMemoryRequirements2KHR = gen11_GetImageMemoryRequirements2, + .vkGetImageSparseMemoryRequirements2 = gen11_GetImageSparseMemoryRequirements2, + .vkGetImageSparseMemoryRequirements2KHR = gen11_GetImageSparseMemoryRequirements2, + .vkCreateSamplerYcbcrConversion = gen11_CreateSamplerYcbcrConversion, + .vkCreateSamplerYcbcrConversionKHR = gen11_CreateSamplerYcbcrConversion, + .vkDestroySamplerYcbcrConversion = gen11_DestroySamplerYcbcrConversion, + .vkDestroySamplerYcbcrConversionKHR = gen11_DestroySamplerYcbcrConversion, + .vkGetDeviceQueue2 = gen11_GetDeviceQueue2, + .vkGetDescriptorSetLayoutSupport = gen11_GetDescriptorSetLayoutSupport, + .vkGetDescriptorSetLayoutSupportKHR = gen11_GetDescriptorSetLayoutSupport, +#ifdef VK_USE_PLATFORM_ANDROID_KHR + .vkGetSwapchainGrallocUsageANDROID = gen11_GetSwapchainGrallocUsageANDROID, +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + .vkAcquireImageANDROID = gen11_AcquireImageANDROID, +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + .vkQueueSignalReleaseImageANDROID = gen11_QueueSignalReleaseImageANDROID, +#endif // VK_USE_PLATFORM_ANDROID_KHR + .vkGetCalibratedTimestampsEXT = gen11_GetCalibratedTimestampsEXT, + .vkCreateRenderPass2KHR = gen11_CreateRenderPass2KHR, + .vkCmdBeginRenderPass2KHR = gen11_CmdBeginRenderPass2KHR, + .vkCmdNextSubpass2KHR = gen11_CmdNextSubpass2KHR, + .vkCmdEndRenderPass2KHR = gen11_CmdEndRenderPass2KHR, +#ifdef VK_USE_PLATFORM_ANDROID_KHR + .vkGetAndroidHardwareBufferPropertiesANDROID = gen11_GetAndroidHardwareBufferPropertiesANDROID, +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + .vkGetMemoryAndroidHardwareBufferANDROID = gen11_GetMemoryAndroidHardwareBufferANDROID, +#endif // VK_USE_PLATFORM_ANDROID_KHR + .vkCmdDrawIndirectCountKHR = gen11_CmdDrawIndirectCountKHR, + .vkCmdDrawIndexedIndirectCountKHR = gen11_CmdDrawIndexedIndirectCountKHR, + .vkCmdBindTransformFeedbackBuffersEXT = gen11_CmdBindTransformFeedbackBuffersEXT, + .vkCmdBeginTransformFeedbackEXT = gen11_CmdBeginTransformFeedbackEXT, + .vkCmdEndTransformFeedbackEXT = gen11_CmdEndTransformFeedbackEXT, + .vkCmdBeginQueryIndexedEXT = gen11_CmdBeginQueryIndexedEXT, + .vkCmdEndQueryIndexedEXT = gen11_CmdEndQueryIndexedEXT, + .vkCmdDrawIndirectByteCountEXT = gen11_CmdDrawIndirectByteCountEXT, + .vkCreateDmaBufImageINTEL = gen11_CreateDmaBufImageINTEL, + }; + + +/** Return true if the core version or extension in which the given entrypoint + * is defined is enabled. + * + * If device is NULL, all device extensions are considered enabled. + */ +bool +anv_instance_entrypoint_is_enabled(int index, uint32_t core_version, + const struct anv_instance_extension_table *instance) +{ + switch (index) { + case 0: + /* vkCreateInstance */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 1: + /* vkDestroyInstance */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 2: + /* vkEnumeratePhysicalDevices */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 3: + /* vkGetInstanceProcAddr */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 4: + /* vkGetPhysicalDeviceProperties */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 5: + /* vkGetPhysicalDeviceQueueFamilyProperties */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 6: + /* vkGetPhysicalDeviceMemoryProperties */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 7: + /* vkGetPhysicalDeviceFeatures */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 8: + /* vkGetPhysicalDeviceFormatProperties */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 9: + /* vkGetPhysicalDeviceImageFormatProperties */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 10: + /* vkCreateDevice */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 11: + /* vkEnumerateInstanceVersion */ + return VK_MAKE_VERSION(1, 1, 0) <= core_version; + case 12: + /* vkEnumerateInstanceLayerProperties */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 13: + /* vkEnumerateInstanceExtensionProperties */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 14: + /* vkEnumerateDeviceLayerProperties */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 15: + /* vkEnumerateDeviceExtensionProperties */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 16: + /* vkGetPhysicalDeviceSparseImageFormatProperties */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 17: + /* vkGetPhysicalDeviceDisplayPropertiesKHR */ + if (instance->KHR_display) return true; + return false; + case 18: + /* vkGetPhysicalDeviceDisplayPlanePropertiesKHR */ + if (instance->KHR_display) return true; + return false; + case 19: + /* vkGetDisplayPlaneSupportedDisplaysKHR */ + if (instance->KHR_display) return true; + return false; + case 20: + /* vkGetDisplayModePropertiesKHR */ + if (instance->KHR_display) return true; + return false; + case 21: + /* vkCreateDisplayModeKHR */ + if (instance->KHR_display) return true; + return false; + case 22: + /* vkGetDisplayPlaneCapabilitiesKHR */ + if (instance->KHR_display) return true; + return false; + case 23: + /* vkCreateDisplayPlaneSurfaceKHR */ + if (instance->KHR_display) return true; + return false; + case 24: + /* vkDestroySurfaceKHR */ + if (instance->KHR_surface) return true; + return false; + case 25: + /* vkGetPhysicalDeviceSurfaceSupportKHR */ + if (instance->KHR_surface) return true; + return false; + case 26: + /* vkGetPhysicalDeviceSurfaceCapabilitiesKHR */ + if (instance->KHR_surface) return true; + return false; + case 27: + /* vkGetPhysicalDeviceSurfaceFormatsKHR */ + if (instance->KHR_surface) return true; + return false; + case 28: + /* vkGetPhysicalDeviceSurfacePresentModesKHR */ + if (instance->KHR_surface) return true; + return false; + case 29: + /* vkCreateWaylandSurfaceKHR */ + if (instance->KHR_wayland_surface) return true; + return false; + case 30: + /* vkGetPhysicalDeviceWaylandPresentationSupportKHR */ + if (instance->KHR_wayland_surface) return true; + return false; + case 31: + /* vkCreateXlibSurfaceKHR */ + if (instance->KHR_xlib_surface) return true; + return false; + case 32: + /* vkGetPhysicalDeviceXlibPresentationSupportKHR */ + if (instance->KHR_xlib_surface) return true; + return false; + case 33: + /* vkCreateXcbSurfaceKHR */ + if (instance->KHR_xcb_surface) return true; + return false; + case 34: + /* vkGetPhysicalDeviceXcbPresentationSupportKHR */ + if (instance->KHR_xcb_surface) return true; + return false; + case 35: + /* vkCreateDebugReportCallbackEXT */ + if (instance->EXT_debug_report) return true; + return false; + case 36: + /* vkDestroyDebugReportCallbackEXT */ + if (instance->EXT_debug_report) return true; + return false; + case 37: + /* vkDebugReportMessageEXT */ + if (instance->EXT_debug_report) return true; + return false; + case 38: + /* vkGetPhysicalDeviceFeatures2 */ + return VK_MAKE_VERSION(1, 1, 0) <= core_version; + case 39: + /* vkGetPhysicalDeviceFeatures2KHR */ + if (instance->KHR_get_physical_device_properties2) return true; + return false; + case 40: + /* vkGetPhysicalDeviceProperties2 */ + return VK_MAKE_VERSION(1, 1, 0) <= core_version; + case 41: + /* vkGetPhysicalDeviceProperties2KHR */ + if (instance->KHR_get_physical_device_properties2) return true; + return false; + case 42: + /* vkGetPhysicalDeviceFormatProperties2 */ + return VK_MAKE_VERSION(1, 1, 0) <= core_version; + case 43: + /* vkGetPhysicalDeviceFormatProperties2KHR */ + if (instance->KHR_get_physical_device_properties2) return true; + return false; + case 44: + /* vkGetPhysicalDeviceImageFormatProperties2 */ + return VK_MAKE_VERSION(1, 1, 0) <= core_version; + case 45: + /* vkGetPhysicalDeviceImageFormatProperties2KHR */ + if (instance->KHR_get_physical_device_properties2) return true; + return false; + case 46: + /* vkGetPhysicalDeviceQueueFamilyProperties2 */ + return VK_MAKE_VERSION(1, 1, 0) <= core_version; + case 47: + /* vkGetPhysicalDeviceQueueFamilyProperties2KHR */ + if (instance->KHR_get_physical_device_properties2) return true; + return false; + case 48: + /* vkGetPhysicalDeviceMemoryProperties2 */ + return VK_MAKE_VERSION(1, 1, 0) <= core_version; + case 49: + /* vkGetPhysicalDeviceMemoryProperties2KHR */ + if (instance->KHR_get_physical_device_properties2) return true; + return false; + case 50: + /* vkGetPhysicalDeviceSparseImageFormatProperties2 */ + return VK_MAKE_VERSION(1, 1, 0) <= core_version; + case 51: + /* vkGetPhysicalDeviceSparseImageFormatProperties2KHR */ + if (instance->KHR_get_physical_device_properties2) return true; + return false; + case 52: + /* vkGetPhysicalDeviceExternalBufferProperties */ + return VK_MAKE_VERSION(1, 1, 0) <= core_version; + case 53: + /* vkGetPhysicalDeviceExternalBufferPropertiesKHR */ + if (instance->KHR_external_memory_capabilities) return true; + return false; + case 54: + /* vkGetPhysicalDeviceExternalSemaphoreProperties */ + return VK_MAKE_VERSION(1, 1, 0) <= core_version; + case 55: + /* vkGetPhysicalDeviceExternalSemaphorePropertiesKHR */ + if (instance->KHR_external_semaphore_capabilities) return true; + return false; + case 56: + /* vkGetPhysicalDeviceExternalFenceProperties */ + return VK_MAKE_VERSION(1, 1, 0) <= core_version; + case 57: + /* vkGetPhysicalDeviceExternalFencePropertiesKHR */ + if (instance->KHR_external_fence_capabilities) return true; + return false; + case 58: + /* vkReleaseDisplayEXT */ + if (instance->EXT_direct_mode_display) return true; + return false; + case 59: + /* vkAcquireXlibDisplayEXT */ + if (instance->EXT_acquire_xlib_display) return true; + return false; + case 60: + /* vkGetRandROutputDisplayEXT */ + if (instance->EXT_acquire_xlib_display) return true; + return false; + case 61: + /* vkGetPhysicalDeviceSurfaceCapabilities2EXT */ + if (instance->EXT_display_surface_counter) return true; + return false; + case 62: + /* vkEnumeratePhysicalDeviceGroups */ + return VK_MAKE_VERSION(1, 1, 0) <= core_version; + case 63: + /* vkEnumeratePhysicalDeviceGroupsKHR */ + if (instance->KHR_device_group_creation) return true; + return false; + case 64: + /* vkGetPhysicalDevicePresentRectanglesKHR */ + /* All device extensions are considered enabled at the instance level */ + return true; + /* All device extensions are considered enabled at the instance level */ + return true; + return false; + case 65: + /* vkGetPhysicalDeviceSurfaceCapabilities2KHR */ + if (instance->KHR_get_surface_capabilities2) return true; + return false; + case 66: + /* vkGetPhysicalDeviceSurfaceFormats2KHR */ + if (instance->KHR_get_surface_capabilities2) return true; + return false; + case 67: + /* vkGetPhysicalDeviceDisplayProperties2KHR */ + if (instance->KHR_get_display_properties2) return true; + return false; + case 68: + /* vkGetPhysicalDeviceDisplayPlaneProperties2KHR */ + if (instance->KHR_get_display_properties2) return true; + return false; + case 69: + /* vkGetDisplayModeProperties2KHR */ + if (instance->KHR_get_display_properties2) return true; + return false; + case 70: + /* vkGetDisplayPlaneCapabilities2KHR */ + if (instance->KHR_get_display_properties2) return true; + return false; + case 71: + /* vkGetPhysicalDeviceCalibrateableTimeDomainsEXT */ + /* All device extensions are considered enabled at the instance level */ + return true; + return false; + default: + return false; + } +} + +/** Return true if the core version or extension in which the given entrypoint + * is defined is enabled. + * + * If device is NULL, all device extensions are considered enabled. + */ +bool +anv_device_entrypoint_is_enabled(int index, uint32_t core_version, + const struct anv_instance_extension_table *instance, + const struct anv_device_extension_table *device) +{ + switch (index) { + case 0: + /* vkGetDeviceProcAddr */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 1: + /* vkDestroyDevice */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 2: + /* vkGetDeviceQueue */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 3: + /* vkQueueSubmit */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 4: + /* vkQueueWaitIdle */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 5: + /* vkDeviceWaitIdle */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 6: + /* vkAllocateMemory */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 7: + /* vkFreeMemory */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 8: + /* vkMapMemory */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 9: + /* vkUnmapMemory */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 10: + /* vkFlushMappedMemoryRanges */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 11: + /* vkInvalidateMappedMemoryRanges */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 12: + /* vkGetDeviceMemoryCommitment */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 13: + /* vkGetBufferMemoryRequirements */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 14: + /* vkBindBufferMemory */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 15: + /* vkGetImageMemoryRequirements */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 16: + /* vkBindImageMemory */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 17: + /* vkGetImageSparseMemoryRequirements */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 18: + /* vkQueueBindSparse */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 19: + /* vkCreateFence */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 20: + /* vkDestroyFence */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 21: + /* vkResetFences */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 22: + /* vkGetFenceStatus */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 23: + /* vkWaitForFences */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 24: + /* vkCreateSemaphore */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 25: + /* vkDestroySemaphore */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 26: + /* vkCreateEvent */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 27: + /* vkDestroyEvent */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 28: + /* vkGetEventStatus */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 29: + /* vkSetEvent */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 30: + /* vkResetEvent */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 31: + /* vkCreateQueryPool */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 32: + /* vkDestroyQueryPool */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 33: + /* vkGetQueryPoolResults */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 34: + /* vkCreateBuffer */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 35: + /* vkDestroyBuffer */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 36: + /* vkCreateBufferView */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 37: + /* vkDestroyBufferView */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 38: + /* vkCreateImage */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 39: + /* vkDestroyImage */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 40: + /* vkGetImageSubresourceLayout */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 41: + /* vkCreateImageView */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 42: + /* vkDestroyImageView */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 43: + /* vkCreateShaderModule */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 44: + /* vkDestroyShaderModule */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 45: + /* vkCreatePipelineCache */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 46: + /* vkDestroyPipelineCache */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 47: + /* vkGetPipelineCacheData */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 48: + /* vkMergePipelineCaches */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 49: + /* vkCreateGraphicsPipelines */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 50: + /* vkCreateComputePipelines */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 51: + /* vkDestroyPipeline */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 52: + /* vkCreatePipelineLayout */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 53: + /* vkDestroyPipelineLayout */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 54: + /* vkCreateSampler */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 55: + /* vkDestroySampler */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 56: + /* vkCreateDescriptorSetLayout */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 57: + /* vkDestroyDescriptorSetLayout */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 58: + /* vkCreateDescriptorPool */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 59: + /* vkDestroyDescriptorPool */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 60: + /* vkResetDescriptorPool */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 61: + /* vkAllocateDescriptorSets */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 62: + /* vkFreeDescriptorSets */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 63: + /* vkUpdateDescriptorSets */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 64: + /* vkCreateFramebuffer */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 65: + /* vkDestroyFramebuffer */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 66: + /* vkCreateRenderPass */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 67: + /* vkDestroyRenderPass */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 68: + /* vkGetRenderAreaGranularity */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 69: + /* vkCreateCommandPool */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 70: + /* vkDestroyCommandPool */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 71: + /* vkResetCommandPool */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 72: + /* vkAllocateCommandBuffers */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 73: + /* vkFreeCommandBuffers */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 74: + /* vkBeginCommandBuffer */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 75: + /* vkEndCommandBuffer */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 76: + /* vkResetCommandBuffer */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 77: + /* vkCmdBindPipeline */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 78: + /* vkCmdSetViewport */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 79: + /* vkCmdSetScissor */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 80: + /* vkCmdSetLineWidth */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 81: + /* vkCmdSetDepthBias */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 82: + /* vkCmdSetBlendConstants */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 83: + /* vkCmdSetDepthBounds */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 84: + /* vkCmdSetStencilCompareMask */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 85: + /* vkCmdSetStencilWriteMask */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 86: + /* vkCmdSetStencilReference */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 87: + /* vkCmdBindDescriptorSets */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 88: + /* vkCmdBindIndexBuffer */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 89: + /* vkCmdBindVertexBuffers */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 90: + /* vkCmdDraw */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 91: + /* vkCmdDrawIndexed */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 92: + /* vkCmdDrawIndirect */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 93: + /* vkCmdDrawIndexedIndirect */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 94: + /* vkCmdDispatch */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 95: + /* vkCmdDispatchIndirect */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 96: + /* vkCmdCopyBuffer */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 97: + /* vkCmdCopyImage */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 98: + /* vkCmdBlitImage */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 99: + /* vkCmdCopyBufferToImage */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 100: + /* vkCmdCopyImageToBuffer */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 101: + /* vkCmdUpdateBuffer */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 102: + /* vkCmdFillBuffer */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 103: + /* vkCmdClearColorImage */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 104: + /* vkCmdClearDepthStencilImage */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 105: + /* vkCmdClearAttachments */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 106: + /* vkCmdResolveImage */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 107: + /* vkCmdSetEvent */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 108: + /* vkCmdResetEvent */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 109: + /* vkCmdWaitEvents */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 110: + /* vkCmdPipelineBarrier */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 111: + /* vkCmdBeginQuery */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 112: + /* vkCmdEndQuery */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 113: + /* vkCmdBeginConditionalRenderingEXT */ + if (!device || device->EXT_conditional_rendering) return true; + return false; + case 114: + /* vkCmdEndConditionalRenderingEXT */ + if (!device || device->EXT_conditional_rendering) return true; + return false; + case 115: + /* vkCmdResetQueryPool */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 116: + /* vkCmdWriteTimestamp */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 117: + /* vkCmdCopyQueryPoolResults */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 118: + /* vkCmdPushConstants */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 119: + /* vkCmdBeginRenderPass */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 120: + /* vkCmdNextSubpass */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 121: + /* vkCmdEndRenderPass */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 122: + /* vkCmdExecuteCommands */ + return VK_MAKE_VERSION(1, 0, 0) <= core_version; + case 123: + /* vkCreateSwapchainKHR */ + if (!device || device->KHR_swapchain) return true; + return false; + case 124: + /* vkDestroySwapchainKHR */ + if (!device || device->KHR_swapchain) return true; + return false; + case 125: + /* vkGetSwapchainImagesKHR */ + if (!device || device->KHR_swapchain) return true; + return false; + case 126: + /* vkAcquireNextImageKHR */ + if (!device || device->KHR_swapchain) return true; + return false; + case 127: + /* vkQueuePresentKHR */ + if (!device || device->KHR_swapchain) return true; + return false; + case 128: + /* vkCmdPushDescriptorSetKHR */ + if (!device || device->KHR_push_descriptor) return true; + return false; + case 129: + /* vkTrimCommandPool */ + return VK_MAKE_VERSION(1, 1, 0) <= core_version; + case 130: + /* vkTrimCommandPoolKHR */ + if (!device || device->KHR_maintenance1) return true; + return false; + case 131: + /* vkGetMemoryFdKHR */ + if (!device || device->KHR_external_memory_fd) return true; + return false; + case 132: + /* vkGetMemoryFdPropertiesKHR */ + if (!device || device->KHR_external_memory_fd) return true; + return false; + case 133: + /* vkGetSemaphoreFdKHR */ + if (!device || device->KHR_external_semaphore_fd) return true; + return false; + case 134: + /* vkImportSemaphoreFdKHR */ + if (!device || device->KHR_external_semaphore_fd) return true; + return false; + case 135: + /* vkGetFenceFdKHR */ + if (!device || device->KHR_external_fence_fd) return true; + return false; + case 136: + /* vkImportFenceFdKHR */ + if (!device || device->KHR_external_fence_fd) return true; + return false; + case 137: + /* vkDisplayPowerControlEXT */ + if (!device || device->EXT_display_control) return true; + return false; + case 138: + /* vkRegisterDeviceEventEXT */ + if (!device || device->EXT_display_control) return true; + return false; + case 139: + /* vkRegisterDisplayEventEXT */ + if (!device || device->EXT_display_control) return true; + return false; + case 140: + /* vkGetSwapchainCounterEXT */ + if (!device || device->EXT_display_control) return true; + return false; + case 141: + /* vkGetDeviceGroupPeerMemoryFeatures */ + return VK_MAKE_VERSION(1, 1, 0) <= core_version; + case 142: + /* vkGetDeviceGroupPeerMemoryFeaturesKHR */ + if (!device || device->KHR_device_group) return true; + return false; + case 143: + /* vkBindBufferMemory2 */ + return VK_MAKE_VERSION(1, 1, 0) <= core_version; + case 144: + /* vkBindBufferMemory2KHR */ + if (!device || device->KHR_bind_memory2) return true; + return false; + case 145: + /* vkBindImageMemory2 */ + return VK_MAKE_VERSION(1, 1, 0) <= core_version; + case 146: + /* vkBindImageMemory2KHR */ + if (!device || device->KHR_bind_memory2) return true; + return false; + case 147: + /* vkCmdSetDeviceMask */ + return VK_MAKE_VERSION(1, 1, 0) <= core_version; + case 148: + /* vkCmdSetDeviceMaskKHR */ + if (!device || device->KHR_device_group) return true; + return false; + case 149: + /* vkGetDeviceGroupPresentCapabilitiesKHR */ + if (!device || device->KHR_swapchain) return true; + if (!device || device->KHR_device_group) return true; + return false; + case 150: + /* vkGetDeviceGroupSurfacePresentModesKHR */ + if (!device || device->KHR_swapchain) return true; + if (!device || device->KHR_device_group) return true; + return false; + case 151: + /* vkAcquireNextImage2KHR */ + if (!device || device->KHR_swapchain) return true; + if (!device || device->KHR_device_group) return true; + return false; + case 152: + /* vkCmdDispatchBase */ + return VK_MAKE_VERSION(1, 1, 0) <= core_version; + case 153: + /* vkCmdDispatchBaseKHR */ + if (!device || device->KHR_device_group) return true; + return false; + case 154: + /* vkCreateDescriptorUpdateTemplate */ + return VK_MAKE_VERSION(1, 1, 0) <= core_version; + case 155: + /* vkCreateDescriptorUpdateTemplateKHR */ + if (!device || device->KHR_descriptor_update_template) return true; + return false; + case 156: + /* vkDestroyDescriptorUpdateTemplate */ + return VK_MAKE_VERSION(1, 1, 0) <= core_version; + case 157: + /* vkDestroyDescriptorUpdateTemplateKHR */ + if (!device || device->KHR_descriptor_update_template) return true; + return false; + case 158: + /* vkUpdateDescriptorSetWithTemplate */ + return VK_MAKE_VERSION(1, 1, 0) <= core_version; + case 159: + /* vkUpdateDescriptorSetWithTemplateKHR */ + if (!device || device->KHR_descriptor_update_template) return true; + return false; + case 160: + /* vkCmdPushDescriptorSetWithTemplateKHR */ + if (!device || device->KHR_push_descriptor) return true; + if (!device || device->KHR_descriptor_update_template) return true; + return false; + case 161: + /* vkGetBufferMemoryRequirements2 */ + return VK_MAKE_VERSION(1, 1, 0) <= core_version; + case 162: + /* vkGetBufferMemoryRequirements2KHR */ + if (!device || device->KHR_get_memory_requirements2) return true; + return false; + case 163: + /* vkGetImageMemoryRequirements2 */ + return VK_MAKE_VERSION(1, 1, 0) <= core_version; + case 164: + /* vkGetImageMemoryRequirements2KHR */ + if (!device || device->KHR_get_memory_requirements2) return true; + return false; + case 165: + /* vkGetImageSparseMemoryRequirements2 */ + return VK_MAKE_VERSION(1, 1, 0) <= core_version; + case 166: + /* vkGetImageSparseMemoryRequirements2KHR */ + if (!device || device->KHR_get_memory_requirements2) return true; + return false; + case 167: + /* vkCreateSamplerYcbcrConversion */ + return VK_MAKE_VERSION(1, 1, 0) <= core_version; + case 168: + /* vkCreateSamplerYcbcrConversionKHR */ + if (!device || device->KHR_sampler_ycbcr_conversion) return true; + return false; + case 169: + /* vkDestroySamplerYcbcrConversion */ + return VK_MAKE_VERSION(1, 1, 0) <= core_version; + case 170: + /* vkDestroySamplerYcbcrConversionKHR */ + if (!device || device->KHR_sampler_ycbcr_conversion) return true; + return false; + case 171: + /* vkGetDeviceQueue2 */ + return VK_MAKE_VERSION(1, 1, 0) <= core_version; + case 172: + /* vkGetDescriptorSetLayoutSupport */ + return VK_MAKE_VERSION(1, 1, 0) <= core_version; + case 173: + /* vkGetDescriptorSetLayoutSupportKHR */ + if (!device || device->KHR_maintenance3) return true; + return false; + case 174: + /* vkGetSwapchainGrallocUsageANDROID */ + if (!device || device->ANDROID_native_buffer) return true; + return false; + case 175: + /* vkAcquireImageANDROID */ + if (!device || device->ANDROID_native_buffer) return true; + return false; + case 176: + /* vkQueueSignalReleaseImageANDROID */ + if (!device || device->ANDROID_native_buffer) return true; + return false; + case 177: + /* vkGetCalibratedTimestampsEXT */ + if (!device || device->EXT_calibrated_timestamps) return true; + return false; + case 178: + /* vkCreateRenderPass2KHR */ + if (!device || device->KHR_create_renderpass2) return true; + return false; + case 179: + /* vkCmdBeginRenderPass2KHR */ + if (!device || device->KHR_create_renderpass2) return true; + return false; + case 180: + /* vkCmdNextSubpass2KHR */ + if (!device || device->KHR_create_renderpass2) return true; + return false; + case 181: + /* vkCmdEndRenderPass2KHR */ + if (!device || device->KHR_create_renderpass2) return true; + return false; + case 182: + /* vkGetAndroidHardwareBufferPropertiesANDROID */ + if (!device || device->ANDROID_external_memory_android_hardware_buffer) return true; + return false; + case 183: + /* vkGetMemoryAndroidHardwareBufferANDROID */ + if (!device || device->ANDROID_external_memory_android_hardware_buffer) return true; + return false; + case 184: + /* vkCmdDrawIndirectCountKHR */ + if (!device || device->KHR_draw_indirect_count) return true; + return false; + case 185: + /* vkCmdDrawIndexedIndirectCountKHR */ + if (!device || device->KHR_draw_indirect_count) return true; + return false; + case 186: + /* vkCmdBindTransformFeedbackBuffersEXT */ + if (!device || device->EXT_transform_feedback) return true; + return false; + case 187: + /* vkCmdBeginTransformFeedbackEXT */ + if (!device || device->EXT_transform_feedback) return true; + return false; + case 188: + /* vkCmdEndTransformFeedbackEXT */ + if (!device || device->EXT_transform_feedback) return true; + return false; + case 189: + /* vkCmdBeginQueryIndexedEXT */ + if (!device || device->EXT_transform_feedback) return true; + return false; + case 190: + /* vkCmdEndQueryIndexedEXT */ + if (!device || device->EXT_transform_feedback) return true; + return false; + case 191: + /* vkCmdDrawIndirectByteCountEXT */ + if (!device || device->EXT_transform_feedback) return true; + return false; + case 192: + /* vkCreateDmaBufImageINTEL */ + return true; + default: + return false; + } +} + +int +anv_get_instance_entrypoint_index(const char *name) +{ + return instance_string_map_lookup(name); +} + +int +anv_get_device_entrypoint_index(const char *name) +{ + return device_string_map_lookup(name); +} + +static void * __attribute__ ((noinline)) +anv_resolve_device_entrypoint(const struct gen_device_info *devinfo, uint32_t index) +{ + const struct anv_device_dispatch_table *genX_table; + switch (devinfo->gen) { + case 11: + genX_table = &gen11_device_dispatch_table; + break; + case 10: + genX_table = &gen10_device_dispatch_table; + break; + case 9: + genX_table = &gen9_device_dispatch_table; + break; + case 8: + genX_table = &gen8_device_dispatch_table; + break; + case 7: + if (devinfo->is_haswell) + genX_table = &gen75_device_dispatch_table; + else + genX_table = &gen7_device_dispatch_table; + break; + default: + unreachable("unsupported gen\n"); + } + + if (genX_table->entrypoints[index]) + return genX_table->entrypoints[index]; + else + return anv_device_dispatch_table.entrypoints[index]; +} + +void * +anv_lookup_entrypoint(const struct gen_device_info *devinfo, const char *name) +{ + int idx = anv_get_instance_entrypoint_index(name); + if (idx >= 0) + return anv_instance_dispatch_table.entrypoints[idx]; + + idx = anv_get_device_entrypoint_index(name); + if (idx >= 0) + return anv_resolve_device_entrypoint(devinfo, idx); + + return NULL; +} \ No newline at end of file diff --git a/prebuilt-intermediates/vulkan/anv_entrypoints.h b/prebuilt-intermediates/vulkan/anv_entrypoints.h new file mode 100644 index 00000000000..0792ee3f77b --- /dev/null +++ b/prebuilt-intermediates/vulkan/anv_entrypoints.h @@ -0,0 +1,1678 @@ +/* This file generated from anv_entrypoints_gen.py, don't edit directly. */ + +struct anv_instance_dispatch_table { + union { + void *entrypoints[72]; + struct { + PFN_vkCreateInstance vkCreateInstance; + PFN_vkDestroyInstance vkDestroyInstance; + PFN_vkEnumeratePhysicalDevices vkEnumeratePhysicalDevices; + PFN_vkGetInstanceProcAddr vkGetInstanceProcAddr; + PFN_vkGetPhysicalDeviceProperties vkGetPhysicalDeviceProperties; + PFN_vkGetPhysicalDeviceQueueFamilyProperties vkGetPhysicalDeviceQueueFamilyProperties; + PFN_vkGetPhysicalDeviceMemoryProperties vkGetPhysicalDeviceMemoryProperties; + PFN_vkGetPhysicalDeviceFeatures vkGetPhysicalDeviceFeatures; + PFN_vkGetPhysicalDeviceFormatProperties vkGetPhysicalDeviceFormatProperties; + PFN_vkGetPhysicalDeviceImageFormatProperties vkGetPhysicalDeviceImageFormatProperties; + PFN_vkCreateDevice vkCreateDevice; + PFN_vkEnumerateInstanceVersion vkEnumerateInstanceVersion; + PFN_vkEnumerateInstanceLayerProperties vkEnumerateInstanceLayerProperties; + PFN_vkEnumerateInstanceExtensionProperties vkEnumerateInstanceExtensionProperties; + PFN_vkEnumerateDeviceLayerProperties vkEnumerateDeviceLayerProperties; + PFN_vkEnumerateDeviceExtensionProperties vkEnumerateDeviceExtensionProperties; + PFN_vkGetPhysicalDeviceSparseImageFormatProperties vkGetPhysicalDeviceSparseImageFormatProperties; + PFN_vkGetPhysicalDeviceDisplayPropertiesKHR vkGetPhysicalDeviceDisplayPropertiesKHR; + PFN_vkGetPhysicalDeviceDisplayPlanePropertiesKHR vkGetPhysicalDeviceDisplayPlanePropertiesKHR; + PFN_vkGetDisplayPlaneSupportedDisplaysKHR vkGetDisplayPlaneSupportedDisplaysKHR; + PFN_vkGetDisplayModePropertiesKHR vkGetDisplayModePropertiesKHR; + PFN_vkCreateDisplayModeKHR vkCreateDisplayModeKHR; + PFN_vkGetDisplayPlaneCapabilitiesKHR vkGetDisplayPlaneCapabilitiesKHR; + PFN_vkCreateDisplayPlaneSurfaceKHR vkCreateDisplayPlaneSurfaceKHR; + PFN_vkDestroySurfaceKHR vkDestroySurfaceKHR; + PFN_vkGetPhysicalDeviceSurfaceSupportKHR vkGetPhysicalDeviceSurfaceSupportKHR; + PFN_vkGetPhysicalDeviceSurfaceCapabilitiesKHR vkGetPhysicalDeviceSurfaceCapabilitiesKHR; + PFN_vkGetPhysicalDeviceSurfaceFormatsKHR vkGetPhysicalDeviceSurfaceFormatsKHR; + PFN_vkGetPhysicalDeviceSurfacePresentModesKHR vkGetPhysicalDeviceSurfacePresentModesKHR; +#ifdef VK_USE_PLATFORM_WAYLAND_KHR + PFN_vkCreateWaylandSurfaceKHR vkCreateWaylandSurfaceKHR; +#else + void *vkCreateWaylandSurfaceKHR; +# endif +#ifdef VK_USE_PLATFORM_WAYLAND_KHR + PFN_vkGetPhysicalDeviceWaylandPresentationSupportKHR vkGetPhysicalDeviceWaylandPresentationSupportKHR; +#else + void *vkGetPhysicalDeviceWaylandPresentationSupportKHR; +# endif +#ifdef VK_USE_PLATFORM_XLIB_KHR + PFN_vkCreateXlibSurfaceKHR vkCreateXlibSurfaceKHR; +#else + void *vkCreateXlibSurfaceKHR; +# endif +#ifdef VK_USE_PLATFORM_XLIB_KHR + PFN_vkGetPhysicalDeviceXlibPresentationSupportKHR vkGetPhysicalDeviceXlibPresentationSupportKHR; +#else + void *vkGetPhysicalDeviceXlibPresentationSupportKHR; +# endif +#ifdef VK_USE_PLATFORM_XCB_KHR + PFN_vkCreateXcbSurfaceKHR vkCreateXcbSurfaceKHR; +#else + void *vkCreateXcbSurfaceKHR; +# endif +#ifdef VK_USE_PLATFORM_XCB_KHR + PFN_vkGetPhysicalDeviceXcbPresentationSupportKHR vkGetPhysicalDeviceXcbPresentationSupportKHR; +#else + void *vkGetPhysicalDeviceXcbPresentationSupportKHR; +# endif + PFN_vkCreateDebugReportCallbackEXT vkCreateDebugReportCallbackEXT; + PFN_vkDestroyDebugReportCallbackEXT vkDestroyDebugReportCallbackEXT; + PFN_vkDebugReportMessageEXT vkDebugReportMessageEXT; + PFN_vkGetPhysicalDeviceFeatures2 vkGetPhysicalDeviceFeatures2; + PFN_vkGetPhysicalDeviceFeatures2KHR vkGetPhysicalDeviceFeatures2KHR; + PFN_vkGetPhysicalDeviceProperties2 vkGetPhysicalDeviceProperties2; + PFN_vkGetPhysicalDeviceProperties2KHR vkGetPhysicalDeviceProperties2KHR; + PFN_vkGetPhysicalDeviceFormatProperties2 vkGetPhysicalDeviceFormatProperties2; + PFN_vkGetPhysicalDeviceFormatProperties2KHR vkGetPhysicalDeviceFormatProperties2KHR; + PFN_vkGetPhysicalDeviceImageFormatProperties2 vkGetPhysicalDeviceImageFormatProperties2; + PFN_vkGetPhysicalDeviceImageFormatProperties2KHR vkGetPhysicalDeviceImageFormatProperties2KHR; + PFN_vkGetPhysicalDeviceQueueFamilyProperties2 vkGetPhysicalDeviceQueueFamilyProperties2; + PFN_vkGetPhysicalDeviceQueueFamilyProperties2KHR vkGetPhysicalDeviceQueueFamilyProperties2KHR; + PFN_vkGetPhysicalDeviceMemoryProperties2 vkGetPhysicalDeviceMemoryProperties2; + PFN_vkGetPhysicalDeviceMemoryProperties2KHR vkGetPhysicalDeviceMemoryProperties2KHR; + PFN_vkGetPhysicalDeviceSparseImageFormatProperties2 vkGetPhysicalDeviceSparseImageFormatProperties2; + PFN_vkGetPhysicalDeviceSparseImageFormatProperties2KHR vkGetPhysicalDeviceSparseImageFormatProperties2KHR; + PFN_vkGetPhysicalDeviceExternalBufferProperties vkGetPhysicalDeviceExternalBufferProperties; + PFN_vkGetPhysicalDeviceExternalBufferPropertiesKHR vkGetPhysicalDeviceExternalBufferPropertiesKHR; + PFN_vkGetPhysicalDeviceExternalSemaphoreProperties vkGetPhysicalDeviceExternalSemaphoreProperties; + PFN_vkGetPhysicalDeviceExternalSemaphorePropertiesKHR vkGetPhysicalDeviceExternalSemaphorePropertiesKHR; + PFN_vkGetPhysicalDeviceExternalFenceProperties vkGetPhysicalDeviceExternalFenceProperties; + PFN_vkGetPhysicalDeviceExternalFencePropertiesKHR vkGetPhysicalDeviceExternalFencePropertiesKHR; + PFN_vkReleaseDisplayEXT vkReleaseDisplayEXT; +#ifdef VK_USE_PLATFORM_XLIB_XRANDR_EXT + PFN_vkAcquireXlibDisplayEXT vkAcquireXlibDisplayEXT; +#else + void *vkAcquireXlibDisplayEXT; +# endif +#ifdef VK_USE_PLATFORM_XLIB_XRANDR_EXT + PFN_vkGetRandROutputDisplayEXT vkGetRandROutputDisplayEXT; +#else + void *vkGetRandROutputDisplayEXT; +# endif + PFN_vkGetPhysicalDeviceSurfaceCapabilities2EXT vkGetPhysicalDeviceSurfaceCapabilities2EXT; + PFN_vkEnumeratePhysicalDeviceGroups vkEnumeratePhysicalDeviceGroups; + PFN_vkEnumeratePhysicalDeviceGroupsKHR vkEnumeratePhysicalDeviceGroupsKHR; + PFN_vkGetPhysicalDevicePresentRectanglesKHR vkGetPhysicalDevicePresentRectanglesKHR; + PFN_vkGetPhysicalDeviceSurfaceCapabilities2KHR vkGetPhysicalDeviceSurfaceCapabilities2KHR; + PFN_vkGetPhysicalDeviceSurfaceFormats2KHR vkGetPhysicalDeviceSurfaceFormats2KHR; + PFN_vkGetPhysicalDeviceDisplayProperties2KHR vkGetPhysicalDeviceDisplayProperties2KHR; + PFN_vkGetPhysicalDeviceDisplayPlaneProperties2KHR vkGetPhysicalDeviceDisplayPlaneProperties2KHR; + PFN_vkGetDisplayModeProperties2KHR vkGetDisplayModeProperties2KHR; + PFN_vkGetDisplayPlaneCapabilities2KHR vkGetDisplayPlaneCapabilities2KHR; + PFN_vkGetPhysicalDeviceCalibrateableTimeDomainsEXT vkGetPhysicalDeviceCalibrateableTimeDomainsEXT; + }; + }; +}; + +struct anv_device_dispatch_table { + union { + void *entrypoints[193]; + struct { + PFN_vkGetDeviceProcAddr vkGetDeviceProcAddr; + PFN_vkDestroyDevice vkDestroyDevice; + PFN_vkGetDeviceQueue vkGetDeviceQueue; + PFN_vkQueueSubmit vkQueueSubmit; + PFN_vkQueueWaitIdle vkQueueWaitIdle; + PFN_vkDeviceWaitIdle vkDeviceWaitIdle; + PFN_vkAllocateMemory vkAllocateMemory; + PFN_vkFreeMemory vkFreeMemory; + PFN_vkMapMemory vkMapMemory; + PFN_vkUnmapMemory vkUnmapMemory; + PFN_vkFlushMappedMemoryRanges vkFlushMappedMemoryRanges; + PFN_vkInvalidateMappedMemoryRanges vkInvalidateMappedMemoryRanges; + PFN_vkGetDeviceMemoryCommitment vkGetDeviceMemoryCommitment; + PFN_vkGetBufferMemoryRequirements vkGetBufferMemoryRequirements; + PFN_vkBindBufferMemory vkBindBufferMemory; + PFN_vkGetImageMemoryRequirements vkGetImageMemoryRequirements; + PFN_vkBindImageMemory vkBindImageMemory; + PFN_vkGetImageSparseMemoryRequirements vkGetImageSparseMemoryRequirements; + PFN_vkQueueBindSparse vkQueueBindSparse; + PFN_vkCreateFence vkCreateFence; + PFN_vkDestroyFence vkDestroyFence; + PFN_vkResetFences vkResetFences; + PFN_vkGetFenceStatus vkGetFenceStatus; + PFN_vkWaitForFences vkWaitForFences; + PFN_vkCreateSemaphore vkCreateSemaphore; + PFN_vkDestroySemaphore vkDestroySemaphore; + PFN_vkCreateEvent vkCreateEvent; + PFN_vkDestroyEvent vkDestroyEvent; + PFN_vkGetEventStatus vkGetEventStatus; + PFN_vkSetEvent vkSetEvent; + PFN_vkResetEvent vkResetEvent; + PFN_vkCreateQueryPool vkCreateQueryPool; + PFN_vkDestroyQueryPool vkDestroyQueryPool; + PFN_vkGetQueryPoolResults vkGetQueryPoolResults; + PFN_vkCreateBuffer vkCreateBuffer; + PFN_vkDestroyBuffer vkDestroyBuffer; + PFN_vkCreateBufferView vkCreateBufferView; + PFN_vkDestroyBufferView vkDestroyBufferView; + PFN_vkCreateImage vkCreateImage; + PFN_vkDestroyImage vkDestroyImage; + PFN_vkGetImageSubresourceLayout vkGetImageSubresourceLayout; + PFN_vkCreateImageView vkCreateImageView; + PFN_vkDestroyImageView vkDestroyImageView; + PFN_vkCreateShaderModule vkCreateShaderModule; + PFN_vkDestroyShaderModule vkDestroyShaderModule; + PFN_vkCreatePipelineCache vkCreatePipelineCache; + PFN_vkDestroyPipelineCache vkDestroyPipelineCache; + PFN_vkGetPipelineCacheData vkGetPipelineCacheData; + PFN_vkMergePipelineCaches vkMergePipelineCaches; + PFN_vkCreateGraphicsPipelines vkCreateGraphicsPipelines; + PFN_vkCreateComputePipelines vkCreateComputePipelines; + PFN_vkDestroyPipeline vkDestroyPipeline; + PFN_vkCreatePipelineLayout vkCreatePipelineLayout; + PFN_vkDestroyPipelineLayout vkDestroyPipelineLayout; + PFN_vkCreateSampler vkCreateSampler; + PFN_vkDestroySampler vkDestroySampler; + PFN_vkCreateDescriptorSetLayout vkCreateDescriptorSetLayout; + PFN_vkDestroyDescriptorSetLayout vkDestroyDescriptorSetLayout; + PFN_vkCreateDescriptorPool vkCreateDescriptorPool; + PFN_vkDestroyDescriptorPool vkDestroyDescriptorPool; + PFN_vkResetDescriptorPool vkResetDescriptorPool; + PFN_vkAllocateDescriptorSets vkAllocateDescriptorSets; + PFN_vkFreeDescriptorSets vkFreeDescriptorSets; + PFN_vkUpdateDescriptorSets vkUpdateDescriptorSets; + PFN_vkCreateFramebuffer vkCreateFramebuffer; + PFN_vkDestroyFramebuffer vkDestroyFramebuffer; + PFN_vkCreateRenderPass vkCreateRenderPass; + PFN_vkDestroyRenderPass vkDestroyRenderPass; + PFN_vkGetRenderAreaGranularity vkGetRenderAreaGranularity; + PFN_vkCreateCommandPool vkCreateCommandPool; + PFN_vkDestroyCommandPool vkDestroyCommandPool; + PFN_vkResetCommandPool vkResetCommandPool; + PFN_vkAllocateCommandBuffers vkAllocateCommandBuffers; + PFN_vkFreeCommandBuffers vkFreeCommandBuffers; + PFN_vkBeginCommandBuffer vkBeginCommandBuffer; + PFN_vkEndCommandBuffer vkEndCommandBuffer; + PFN_vkResetCommandBuffer vkResetCommandBuffer; + PFN_vkCmdBindPipeline vkCmdBindPipeline; + PFN_vkCmdSetViewport vkCmdSetViewport; + PFN_vkCmdSetScissor vkCmdSetScissor; + PFN_vkCmdSetLineWidth vkCmdSetLineWidth; + PFN_vkCmdSetDepthBias vkCmdSetDepthBias; + PFN_vkCmdSetBlendConstants vkCmdSetBlendConstants; + PFN_vkCmdSetDepthBounds vkCmdSetDepthBounds; + PFN_vkCmdSetStencilCompareMask vkCmdSetStencilCompareMask; + PFN_vkCmdSetStencilWriteMask vkCmdSetStencilWriteMask; + PFN_vkCmdSetStencilReference vkCmdSetStencilReference; + PFN_vkCmdBindDescriptorSets vkCmdBindDescriptorSets; + PFN_vkCmdBindIndexBuffer vkCmdBindIndexBuffer; + PFN_vkCmdBindVertexBuffers vkCmdBindVertexBuffers; + PFN_vkCmdDraw vkCmdDraw; + PFN_vkCmdDrawIndexed vkCmdDrawIndexed; + PFN_vkCmdDrawIndirect vkCmdDrawIndirect; + PFN_vkCmdDrawIndexedIndirect vkCmdDrawIndexedIndirect; + PFN_vkCmdDispatch vkCmdDispatch; + PFN_vkCmdDispatchIndirect vkCmdDispatchIndirect; + PFN_vkCmdCopyBuffer vkCmdCopyBuffer; + PFN_vkCmdCopyImage vkCmdCopyImage; + PFN_vkCmdBlitImage vkCmdBlitImage; + PFN_vkCmdCopyBufferToImage vkCmdCopyBufferToImage; + PFN_vkCmdCopyImageToBuffer vkCmdCopyImageToBuffer; + PFN_vkCmdUpdateBuffer vkCmdUpdateBuffer; + PFN_vkCmdFillBuffer vkCmdFillBuffer; + PFN_vkCmdClearColorImage vkCmdClearColorImage; + PFN_vkCmdClearDepthStencilImage vkCmdClearDepthStencilImage; + PFN_vkCmdClearAttachments vkCmdClearAttachments; + PFN_vkCmdResolveImage vkCmdResolveImage; + PFN_vkCmdSetEvent vkCmdSetEvent; + PFN_vkCmdResetEvent vkCmdResetEvent; + PFN_vkCmdWaitEvents vkCmdWaitEvents; + PFN_vkCmdPipelineBarrier vkCmdPipelineBarrier; + PFN_vkCmdBeginQuery vkCmdBeginQuery; + PFN_vkCmdEndQuery vkCmdEndQuery; + PFN_vkCmdBeginConditionalRenderingEXT vkCmdBeginConditionalRenderingEXT; + PFN_vkCmdEndConditionalRenderingEXT vkCmdEndConditionalRenderingEXT; + PFN_vkCmdResetQueryPool vkCmdResetQueryPool; + PFN_vkCmdWriteTimestamp vkCmdWriteTimestamp; + PFN_vkCmdCopyQueryPoolResults vkCmdCopyQueryPoolResults; + PFN_vkCmdPushConstants vkCmdPushConstants; + PFN_vkCmdBeginRenderPass vkCmdBeginRenderPass; + PFN_vkCmdNextSubpass vkCmdNextSubpass; + PFN_vkCmdEndRenderPass vkCmdEndRenderPass; + PFN_vkCmdExecuteCommands vkCmdExecuteCommands; + PFN_vkCreateSwapchainKHR vkCreateSwapchainKHR; + PFN_vkDestroySwapchainKHR vkDestroySwapchainKHR; + PFN_vkGetSwapchainImagesKHR vkGetSwapchainImagesKHR; + PFN_vkAcquireNextImageKHR vkAcquireNextImageKHR; + PFN_vkQueuePresentKHR vkQueuePresentKHR; + PFN_vkCmdPushDescriptorSetKHR vkCmdPushDescriptorSetKHR; + PFN_vkTrimCommandPool vkTrimCommandPool; + PFN_vkTrimCommandPoolKHR vkTrimCommandPoolKHR; + PFN_vkGetMemoryFdKHR vkGetMemoryFdKHR; + PFN_vkGetMemoryFdPropertiesKHR vkGetMemoryFdPropertiesKHR; + PFN_vkGetSemaphoreFdKHR vkGetSemaphoreFdKHR; + PFN_vkImportSemaphoreFdKHR vkImportSemaphoreFdKHR; + PFN_vkGetFenceFdKHR vkGetFenceFdKHR; + PFN_vkImportFenceFdKHR vkImportFenceFdKHR; + PFN_vkDisplayPowerControlEXT vkDisplayPowerControlEXT; + PFN_vkRegisterDeviceEventEXT vkRegisterDeviceEventEXT; + PFN_vkRegisterDisplayEventEXT vkRegisterDisplayEventEXT; + PFN_vkGetSwapchainCounterEXT vkGetSwapchainCounterEXT; + PFN_vkGetDeviceGroupPeerMemoryFeatures vkGetDeviceGroupPeerMemoryFeatures; + PFN_vkGetDeviceGroupPeerMemoryFeaturesKHR vkGetDeviceGroupPeerMemoryFeaturesKHR; + PFN_vkBindBufferMemory2 vkBindBufferMemory2; + PFN_vkBindBufferMemory2KHR vkBindBufferMemory2KHR; + PFN_vkBindImageMemory2 vkBindImageMemory2; + PFN_vkBindImageMemory2KHR vkBindImageMemory2KHR; + PFN_vkCmdSetDeviceMask vkCmdSetDeviceMask; + PFN_vkCmdSetDeviceMaskKHR vkCmdSetDeviceMaskKHR; + PFN_vkGetDeviceGroupPresentCapabilitiesKHR vkGetDeviceGroupPresentCapabilitiesKHR; + PFN_vkGetDeviceGroupSurfacePresentModesKHR vkGetDeviceGroupSurfacePresentModesKHR; + PFN_vkAcquireNextImage2KHR vkAcquireNextImage2KHR; + PFN_vkCmdDispatchBase vkCmdDispatchBase; + PFN_vkCmdDispatchBaseKHR vkCmdDispatchBaseKHR; + PFN_vkCreateDescriptorUpdateTemplate vkCreateDescriptorUpdateTemplate; + PFN_vkCreateDescriptorUpdateTemplateKHR vkCreateDescriptorUpdateTemplateKHR; + PFN_vkDestroyDescriptorUpdateTemplate vkDestroyDescriptorUpdateTemplate; + PFN_vkDestroyDescriptorUpdateTemplateKHR vkDestroyDescriptorUpdateTemplateKHR; + PFN_vkUpdateDescriptorSetWithTemplate vkUpdateDescriptorSetWithTemplate; + PFN_vkUpdateDescriptorSetWithTemplateKHR vkUpdateDescriptorSetWithTemplateKHR; + PFN_vkCmdPushDescriptorSetWithTemplateKHR vkCmdPushDescriptorSetWithTemplateKHR; + PFN_vkGetBufferMemoryRequirements2 vkGetBufferMemoryRequirements2; + PFN_vkGetBufferMemoryRequirements2KHR vkGetBufferMemoryRequirements2KHR; + PFN_vkGetImageMemoryRequirements2 vkGetImageMemoryRequirements2; + PFN_vkGetImageMemoryRequirements2KHR vkGetImageMemoryRequirements2KHR; + PFN_vkGetImageSparseMemoryRequirements2 vkGetImageSparseMemoryRequirements2; + PFN_vkGetImageSparseMemoryRequirements2KHR vkGetImageSparseMemoryRequirements2KHR; + PFN_vkCreateSamplerYcbcrConversion vkCreateSamplerYcbcrConversion; + PFN_vkCreateSamplerYcbcrConversionKHR vkCreateSamplerYcbcrConversionKHR; + PFN_vkDestroySamplerYcbcrConversion vkDestroySamplerYcbcrConversion; + PFN_vkDestroySamplerYcbcrConversionKHR vkDestroySamplerYcbcrConversionKHR; + PFN_vkGetDeviceQueue2 vkGetDeviceQueue2; + PFN_vkGetDescriptorSetLayoutSupport vkGetDescriptorSetLayoutSupport; + PFN_vkGetDescriptorSetLayoutSupportKHR vkGetDescriptorSetLayoutSupportKHR; +#ifdef VK_USE_PLATFORM_ANDROID_KHR + PFN_vkGetSwapchainGrallocUsageANDROID vkGetSwapchainGrallocUsageANDROID; +#else + void *vkGetSwapchainGrallocUsageANDROID; +# endif +#ifdef VK_USE_PLATFORM_ANDROID_KHR + PFN_vkAcquireImageANDROID vkAcquireImageANDROID; +#else + void *vkAcquireImageANDROID; +# endif +#ifdef VK_USE_PLATFORM_ANDROID_KHR + PFN_vkQueueSignalReleaseImageANDROID vkQueueSignalReleaseImageANDROID; +#else + void *vkQueueSignalReleaseImageANDROID; +# endif + PFN_vkGetCalibratedTimestampsEXT vkGetCalibratedTimestampsEXT; + PFN_vkCreateRenderPass2KHR vkCreateRenderPass2KHR; + PFN_vkCmdBeginRenderPass2KHR vkCmdBeginRenderPass2KHR; + PFN_vkCmdNextSubpass2KHR vkCmdNextSubpass2KHR; + PFN_vkCmdEndRenderPass2KHR vkCmdEndRenderPass2KHR; +#ifdef VK_USE_PLATFORM_ANDROID_KHR + PFN_vkGetAndroidHardwareBufferPropertiesANDROID vkGetAndroidHardwareBufferPropertiesANDROID; +#else + void *vkGetAndroidHardwareBufferPropertiesANDROID; +# endif +#ifdef VK_USE_PLATFORM_ANDROID_KHR + PFN_vkGetMemoryAndroidHardwareBufferANDROID vkGetMemoryAndroidHardwareBufferANDROID; +#else + void *vkGetMemoryAndroidHardwareBufferANDROID; +# endif + PFN_vkCmdDrawIndirectCountKHR vkCmdDrawIndirectCountKHR; + PFN_vkCmdDrawIndexedIndirectCountKHR vkCmdDrawIndexedIndirectCountKHR; + PFN_vkCmdBindTransformFeedbackBuffersEXT vkCmdBindTransformFeedbackBuffersEXT; + PFN_vkCmdBeginTransformFeedbackEXT vkCmdBeginTransformFeedbackEXT; + PFN_vkCmdEndTransformFeedbackEXT vkCmdEndTransformFeedbackEXT; + PFN_vkCmdBeginQueryIndexedEXT vkCmdBeginQueryIndexedEXT; + PFN_vkCmdEndQueryIndexedEXT vkCmdEndQueryIndexedEXT; + PFN_vkCmdDrawIndirectByteCountEXT vkCmdDrawIndirectByteCountEXT; + PFN_vkCreateDmaBufImageINTEL vkCreateDmaBufImageINTEL; + }; + }; +}; + +extern const struct anv_instance_dispatch_table anv_instance_dispatch_table; +extern const struct anv_device_dispatch_table anv_device_dispatch_table; +extern const struct anv_device_dispatch_table gen7_device_dispatch_table; +extern const struct anv_device_dispatch_table gen75_device_dispatch_table; +extern const struct anv_device_dispatch_table gen8_device_dispatch_table; +extern const struct anv_device_dispatch_table gen9_device_dispatch_table; +extern const struct anv_device_dispatch_table gen10_device_dispatch_table; +extern const struct anv_device_dispatch_table gen11_device_dispatch_table; + + VkResult anv_CreateInstance(const VkInstanceCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkInstance* pInstance); + void anv_DestroyInstance(VkInstance instance, const VkAllocationCallbacks* pAllocator); + VkResult anv_EnumeratePhysicalDevices(VkInstance instance, uint32_t* pPhysicalDeviceCount, VkPhysicalDevice* pPhysicalDevices); + PFN_vkVoidFunction anv_GetInstanceProcAddr(VkInstance instance, const char* pName); + void anv_GetPhysicalDeviceProperties(VkPhysicalDevice physicalDevice, VkPhysicalDeviceProperties* pProperties); + void anv_GetPhysicalDeviceQueueFamilyProperties(VkPhysicalDevice physicalDevice, uint32_t* pQueueFamilyPropertyCount, VkQueueFamilyProperties* pQueueFamilyProperties); + void anv_GetPhysicalDeviceMemoryProperties(VkPhysicalDevice physicalDevice, VkPhysicalDeviceMemoryProperties* pMemoryProperties); + void anv_GetPhysicalDeviceFeatures(VkPhysicalDevice physicalDevice, VkPhysicalDeviceFeatures* pFeatures); + void anv_GetPhysicalDeviceFormatProperties(VkPhysicalDevice physicalDevice, VkFormat format, VkFormatProperties* pFormatProperties); + VkResult anv_GetPhysicalDeviceImageFormatProperties(VkPhysicalDevice physicalDevice, VkFormat format, VkImageType type, VkImageTiling tiling, VkImageUsageFlags usage, VkImageCreateFlags flags, VkImageFormatProperties* pImageFormatProperties); + VkResult anv_CreateDevice(VkPhysicalDevice physicalDevice, const VkDeviceCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDevice* pDevice); + VkResult anv_EnumerateInstanceVersion(uint32_t* pApiVersion); + VkResult anv_EnumerateInstanceLayerProperties(uint32_t* pPropertyCount, VkLayerProperties* pProperties); + VkResult anv_EnumerateInstanceExtensionProperties(const char* pLayerName, uint32_t* pPropertyCount, VkExtensionProperties* pProperties); + VkResult anv_EnumerateDeviceLayerProperties(VkPhysicalDevice physicalDevice, uint32_t* pPropertyCount, VkLayerProperties* pProperties); + VkResult anv_EnumerateDeviceExtensionProperties(VkPhysicalDevice physicalDevice, const char* pLayerName, uint32_t* pPropertyCount, VkExtensionProperties* pProperties); + void anv_GetPhysicalDeviceSparseImageFormatProperties(VkPhysicalDevice physicalDevice, VkFormat format, VkImageType type, VkSampleCountFlagBits samples, VkImageUsageFlags usage, VkImageTiling tiling, uint32_t* pPropertyCount, VkSparseImageFormatProperties* pProperties); + VkResult anv_GetPhysicalDeviceDisplayPropertiesKHR(VkPhysicalDevice physicalDevice, uint32_t* pPropertyCount, VkDisplayPropertiesKHR* pProperties); + VkResult anv_GetPhysicalDeviceDisplayPlanePropertiesKHR(VkPhysicalDevice physicalDevice, uint32_t* pPropertyCount, VkDisplayPlanePropertiesKHR* pProperties); + VkResult anv_GetDisplayPlaneSupportedDisplaysKHR(VkPhysicalDevice physicalDevice, uint32_t planeIndex, uint32_t* pDisplayCount, VkDisplayKHR* pDisplays); + VkResult anv_GetDisplayModePropertiesKHR(VkPhysicalDevice physicalDevice, VkDisplayKHR display, uint32_t* pPropertyCount, VkDisplayModePropertiesKHR* pProperties); + VkResult anv_CreateDisplayModeKHR(VkPhysicalDevice physicalDevice, VkDisplayKHR display, const VkDisplayModeCreateInfoKHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDisplayModeKHR* pMode); + VkResult anv_GetDisplayPlaneCapabilitiesKHR(VkPhysicalDevice physicalDevice, VkDisplayModeKHR mode, uint32_t planeIndex, VkDisplayPlaneCapabilitiesKHR* pCapabilities); + VkResult anv_CreateDisplayPlaneSurfaceKHR(VkInstance instance, const VkDisplaySurfaceCreateInfoKHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSurfaceKHR* pSurface); + void anv_DestroySurfaceKHR(VkInstance instance, VkSurfaceKHR surface, const VkAllocationCallbacks* pAllocator); + VkResult anv_GetPhysicalDeviceSurfaceSupportKHR(VkPhysicalDevice physicalDevice, uint32_t queueFamilyIndex, VkSurfaceKHR surface, VkBool32* pSupported); + VkResult anv_GetPhysicalDeviceSurfaceCapabilitiesKHR(VkPhysicalDevice physicalDevice, VkSurfaceKHR surface, VkSurfaceCapabilitiesKHR* pSurfaceCapabilities); + VkResult anv_GetPhysicalDeviceSurfaceFormatsKHR(VkPhysicalDevice physicalDevice, VkSurfaceKHR surface, uint32_t* pSurfaceFormatCount, VkSurfaceFormatKHR* pSurfaceFormats); + VkResult anv_GetPhysicalDeviceSurfacePresentModesKHR(VkPhysicalDevice physicalDevice, VkSurfaceKHR surface, uint32_t* pPresentModeCount, VkPresentModeKHR* pPresentModes); +#ifdef VK_USE_PLATFORM_WAYLAND_KHR + VkResult anv_CreateWaylandSurfaceKHR(VkInstance instance, const VkWaylandSurfaceCreateInfoKHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSurfaceKHR* pSurface); +#endif // VK_USE_PLATFORM_WAYLAND_KHR +#ifdef VK_USE_PLATFORM_WAYLAND_KHR + VkBool32 anv_GetPhysicalDeviceWaylandPresentationSupportKHR(VkPhysicalDevice physicalDevice, uint32_t queueFamilyIndex, struct wl_display* display); +#endif // VK_USE_PLATFORM_WAYLAND_KHR +#ifdef VK_USE_PLATFORM_XLIB_KHR + VkResult anv_CreateXlibSurfaceKHR(VkInstance instance, const VkXlibSurfaceCreateInfoKHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSurfaceKHR* pSurface); +#endif // VK_USE_PLATFORM_XLIB_KHR +#ifdef VK_USE_PLATFORM_XLIB_KHR + VkBool32 anv_GetPhysicalDeviceXlibPresentationSupportKHR(VkPhysicalDevice physicalDevice, uint32_t queueFamilyIndex, Display* dpy, VisualID visualID); +#endif // VK_USE_PLATFORM_XLIB_KHR +#ifdef VK_USE_PLATFORM_XCB_KHR + VkResult anv_CreateXcbSurfaceKHR(VkInstance instance, const VkXcbSurfaceCreateInfoKHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSurfaceKHR* pSurface); +#endif // VK_USE_PLATFORM_XCB_KHR +#ifdef VK_USE_PLATFORM_XCB_KHR + VkBool32 anv_GetPhysicalDeviceXcbPresentationSupportKHR(VkPhysicalDevice physicalDevice, uint32_t queueFamilyIndex, xcb_connection_t* connection, xcb_visualid_t visual_id); +#endif // VK_USE_PLATFORM_XCB_KHR + VkResult anv_CreateDebugReportCallbackEXT(VkInstance instance, const VkDebugReportCallbackCreateInfoEXT* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDebugReportCallbackEXT* pCallback); + void anv_DestroyDebugReportCallbackEXT(VkInstance instance, VkDebugReportCallbackEXT callback, const VkAllocationCallbacks* pAllocator); + void anv_DebugReportMessageEXT(VkInstance instance, VkDebugReportFlagsEXT flags, VkDebugReportObjectTypeEXT objectType, uint64_t object, size_t location, int32_t messageCode, const char* pLayerPrefix, const char* pMessage); + void anv_GetPhysicalDeviceFeatures2(VkPhysicalDevice physicalDevice, VkPhysicalDeviceFeatures2* pFeatures); + void anv_GetPhysicalDeviceProperties2(VkPhysicalDevice physicalDevice, VkPhysicalDeviceProperties2* pProperties); + void anv_GetPhysicalDeviceFormatProperties2(VkPhysicalDevice physicalDevice, VkFormat format, VkFormatProperties2* pFormatProperties); + VkResult anv_GetPhysicalDeviceImageFormatProperties2(VkPhysicalDevice physicalDevice, const VkPhysicalDeviceImageFormatInfo2* pImageFormatInfo, VkImageFormatProperties2* pImageFormatProperties); + void anv_GetPhysicalDeviceQueueFamilyProperties2(VkPhysicalDevice physicalDevice, uint32_t* pQueueFamilyPropertyCount, VkQueueFamilyProperties2* pQueueFamilyProperties); + void anv_GetPhysicalDeviceMemoryProperties2(VkPhysicalDevice physicalDevice, VkPhysicalDeviceMemoryProperties2* pMemoryProperties); + void anv_GetPhysicalDeviceSparseImageFormatProperties2(VkPhysicalDevice physicalDevice, const VkPhysicalDeviceSparseImageFormatInfo2* pFormatInfo, uint32_t* pPropertyCount, VkSparseImageFormatProperties2* pProperties); + void anv_GetPhysicalDeviceExternalBufferProperties(VkPhysicalDevice physicalDevice, const VkPhysicalDeviceExternalBufferInfo* pExternalBufferInfo, VkExternalBufferProperties* pExternalBufferProperties); + void anv_GetPhysicalDeviceExternalSemaphoreProperties(VkPhysicalDevice physicalDevice, const VkPhysicalDeviceExternalSemaphoreInfo* pExternalSemaphoreInfo, VkExternalSemaphoreProperties* pExternalSemaphoreProperties); + void anv_GetPhysicalDeviceExternalFenceProperties(VkPhysicalDevice physicalDevice, const VkPhysicalDeviceExternalFenceInfo* pExternalFenceInfo, VkExternalFenceProperties* pExternalFenceProperties); + VkResult anv_ReleaseDisplayEXT(VkPhysicalDevice physicalDevice, VkDisplayKHR display); +#ifdef VK_USE_PLATFORM_XLIB_XRANDR_EXT + VkResult anv_AcquireXlibDisplayEXT(VkPhysicalDevice physicalDevice, Display* dpy, VkDisplayKHR display); +#endif // VK_USE_PLATFORM_XLIB_XRANDR_EXT +#ifdef VK_USE_PLATFORM_XLIB_XRANDR_EXT + VkResult anv_GetRandROutputDisplayEXT(VkPhysicalDevice physicalDevice, Display* dpy, RROutput rrOutput, VkDisplayKHR* pDisplay); +#endif // VK_USE_PLATFORM_XLIB_XRANDR_EXT + VkResult anv_GetPhysicalDeviceSurfaceCapabilities2EXT(VkPhysicalDevice physicalDevice, VkSurfaceKHR surface, VkSurfaceCapabilities2EXT* pSurfaceCapabilities); + VkResult anv_EnumeratePhysicalDeviceGroups(VkInstance instance, uint32_t* pPhysicalDeviceGroupCount, VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties); + VkResult anv_GetPhysicalDevicePresentRectanglesKHR(VkPhysicalDevice physicalDevice, VkSurfaceKHR surface, uint32_t* pRectCount, VkRect2D* pRects); + VkResult anv_GetPhysicalDeviceSurfaceCapabilities2KHR(VkPhysicalDevice physicalDevice, const VkPhysicalDeviceSurfaceInfo2KHR* pSurfaceInfo, VkSurfaceCapabilities2KHR* pSurfaceCapabilities); + VkResult anv_GetPhysicalDeviceSurfaceFormats2KHR(VkPhysicalDevice physicalDevice, const VkPhysicalDeviceSurfaceInfo2KHR* pSurfaceInfo, uint32_t* pSurfaceFormatCount, VkSurfaceFormat2KHR* pSurfaceFormats); + VkResult anv_GetPhysicalDeviceDisplayProperties2KHR(VkPhysicalDevice physicalDevice, uint32_t* pPropertyCount, VkDisplayProperties2KHR* pProperties); + VkResult anv_GetPhysicalDeviceDisplayPlaneProperties2KHR(VkPhysicalDevice physicalDevice, uint32_t* pPropertyCount, VkDisplayPlaneProperties2KHR* pProperties); + VkResult anv_GetDisplayModeProperties2KHR(VkPhysicalDevice physicalDevice, VkDisplayKHR display, uint32_t* pPropertyCount, VkDisplayModeProperties2KHR* pProperties); + VkResult anv_GetDisplayPlaneCapabilities2KHR(VkPhysicalDevice physicalDevice, const VkDisplayPlaneInfo2KHR* pDisplayPlaneInfo, VkDisplayPlaneCapabilities2KHR* pCapabilities); + VkResult anv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(VkPhysicalDevice physicalDevice, uint32_t* pTimeDomainCount, VkTimeDomainEXT* pTimeDomains); + + PFN_vkVoidFunction anv_GetDeviceProcAddr(VkDevice device, const char* pName); + PFN_vkVoidFunction gen7_GetDeviceProcAddr(VkDevice device, const char* pName); + PFN_vkVoidFunction gen75_GetDeviceProcAddr(VkDevice device, const char* pName); + PFN_vkVoidFunction gen8_GetDeviceProcAddr(VkDevice device, const char* pName); + PFN_vkVoidFunction gen9_GetDeviceProcAddr(VkDevice device, const char* pName); + PFN_vkVoidFunction gen10_GetDeviceProcAddr(VkDevice device, const char* pName); + PFN_vkVoidFunction gen11_GetDeviceProcAddr(VkDevice device, const char* pName); + void anv_DestroyDevice(VkDevice device, const VkAllocationCallbacks* pAllocator); + void gen7_DestroyDevice(VkDevice device, const VkAllocationCallbacks* pAllocator); + void gen75_DestroyDevice(VkDevice device, const VkAllocationCallbacks* pAllocator); + void gen8_DestroyDevice(VkDevice device, const VkAllocationCallbacks* pAllocator); + void gen9_DestroyDevice(VkDevice device, const VkAllocationCallbacks* pAllocator); + void gen10_DestroyDevice(VkDevice device, const VkAllocationCallbacks* pAllocator); + void gen11_DestroyDevice(VkDevice device, const VkAllocationCallbacks* pAllocator); + void anv_GetDeviceQueue(VkDevice device, uint32_t queueFamilyIndex, uint32_t queueIndex, VkQueue* pQueue); + void gen7_GetDeviceQueue(VkDevice device, uint32_t queueFamilyIndex, uint32_t queueIndex, VkQueue* pQueue); + void gen75_GetDeviceQueue(VkDevice device, uint32_t queueFamilyIndex, uint32_t queueIndex, VkQueue* pQueue); + void gen8_GetDeviceQueue(VkDevice device, uint32_t queueFamilyIndex, uint32_t queueIndex, VkQueue* pQueue); + void gen9_GetDeviceQueue(VkDevice device, uint32_t queueFamilyIndex, uint32_t queueIndex, VkQueue* pQueue); + void gen10_GetDeviceQueue(VkDevice device, uint32_t queueFamilyIndex, uint32_t queueIndex, VkQueue* pQueue); + void gen11_GetDeviceQueue(VkDevice device, uint32_t queueFamilyIndex, uint32_t queueIndex, VkQueue* pQueue); + VkResult anv_QueueSubmit(VkQueue queue, uint32_t submitCount, const VkSubmitInfo* pSubmits, VkFence fence); + VkResult gen7_QueueSubmit(VkQueue queue, uint32_t submitCount, const VkSubmitInfo* pSubmits, VkFence fence); + VkResult gen75_QueueSubmit(VkQueue queue, uint32_t submitCount, const VkSubmitInfo* pSubmits, VkFence fence); + VkResult gen8_QueueSubmit(VkQueue queue, uint32_t submitCount, const VkSubmitInfo* pSubmits, VkFence fence); + VkResult gen9_QueueSubmit(VkQueue queue, uint32_t submitCount, const VkSubmitInfo* pSubmits, VkFence fence); + VkResult gen10_QueueSubmit(VkQueue queue, uint32_t submitCount, const VkSubmitInfo* pSubmits, VkFence fence); + VkResult gen11_QueueSubmit(VkQueue queue, uint32_t submitCount, const VkSubmitInfo* pSubmits, VkFence fence); + VkResult anv_QueueWaitIdle(VkQueue queue); + VkResult gen7_QueueWaitIdle(VkQueue queue); + VkResult gen75_QueueWaitIdle(VkQueue queue); + VkResult gen8_QueueWaitIdle(VkQueue queue); + VkResult gen9_QueueWaitIdle(VkQueue queue); + VkResult gen10_QueueWaitIdle(VkQueue queue); + VkResult gen11_QueueWaitIdle(VkQueue queue); + VkResult anv_DeviceWaitIdle(VkDevice device); + VkResult gen7_DeviceWaitIdle(VkDevice device); + VkResult gen75_DeviceWaitIdle(VkDevice device); + VkResult gen8_DeviceWaitIdle(VkDevice device); + VkResult gen9_DeviceWaitIdle(VkDevice device); + VkResult gen10_DeviceWaitIdle(VkDevice device); + VkResult gen11_DeviceWaitIdle(VkDevice device); + VkResult anv_AllocateMemory(VkDevice device, const VkMemoryAllocateInfo* pAllocateInfo, const VkAllocationCallbacks* pAllocator, VkDeviceMemory* pMemory); + VkResult gen7_AllocateMemory(VkDevice device, const VkMemoryAllocateInfo* pAllocateInfo, const VkAllocationCallbacks* pAllocator, VkDeviceMemory* pMemory); + VkResult gen75_AllocateMemory(VkDevice device, const VkMemoryAllocateInfo* pAllocateInfo, const VkAllocationCallbacks* pAllocator, VkDeviceMemory* pMemory); + VkResult gen8_AllocateMemory(VkDevice device, const VkMemoryAllocateInfo* pAllocateInfo, const VkAllocationCallbacks* pAllocator, VkDeviceMemory* pMemory); + VkResult gen9_AllocateMemory(VkDevice device, const VkMemoryAllocateInfo* pAllocateInfo, const VkAllocationCallbacks* pAllocator, VkDeviceMemory* pMemory); + VkResult gen10_AllocateMemory(VkDevice device, const VkMemoryAllocateInfo* pAllocateInfo, const VkAllocationCallbacks* pAllocator, VkDeviceMemory* pMemory); + VkResult gen11_AllocateMemory(VkDevice device, const VkMemoryAllocateInfo* pAllocateInfo, const VkAllocationCallbacks* pAllocator, VkDeviceMemory* pMemory); + void anv_FreeMemory(VkDevice device, VkDeviceMemory memory, const VkAllocationCallbacks* pAllocator); + void gen7_FreeMemory(VkDevice device, VkDeviceMemory memory, const VkAllocationCallbacks* pAllocator); + void gen75_FreeMemory(VkDevice device, VkDeviceMemory memory, const VkAllocationCallbacks* pAllocator); + void gen8_FreeMemory(VkDevice device, VkDeviceMemory memory, const VkAllocationCallbacks* pAllocator); + void gen9_FreeMemory(VkDevice device, VkDeviceMemory memory, const VkAllocationCallbacks* pAllocator); + void gen10_FreeMemory(VkDevice device, VkDeviceMemory memory, const VkAllocationCallbacks* pAllocator); + void gen11_FreeMemory(VkDevice device, VkDeviceMemory memory, const VkAllocationCallbacks* pAllocator); + VkResult anv_MapMemory(VkDevice device, VkDeviceMemory memory, VkDeviceSize offset, VkDeviceSize size, VkMemoryMapFlags flags, void** ppData); + VkResult gen7_MapMemory(VkDevice device, VkDeviceMemory memory, VkDeviceSize offset, VkDeviceSize size, VkMemoryMapFlags flags, void** ppData); + VkResult gen75_MapMemory(VkDevice device, VkDeviceMemory memory, VkDeviceSize offset, VkDeviceSize size, VkMemoryMapFlags flags, void** ppData); + VkResult gen8_MapMemory(VkDevice device, VkDeviceMemory memory, VkDeviceSize offset, VkDeviceSize size, VkMemoryMapFlags flags, void** ppData); + VkResult gen9_MapMemory(VkDevice device, VkDeviceMemory memory, VkDeviceSize offset, VkDeviceSize size, VkMemoryMapFlags flags, void** ppData); + VkResult gen10_MapMemory(VkDevice device, VkDeviceMemory memory, VkDeviceSize offset, VkDeviceSize size, VkMemoryMapFlags flags, void** ppData); + VkResult gen11_MapMemory(VkDevice device, VkDeviceMemory memory, VkDeviceSize offset, VkDeviceSize size, VkMemoryMapFlags flags, void** ppData); + void anv_UnmapMemory(VkDevice device, VkDeviceMemory memory); + void gen7_UnmapMemory(VkDevice device, VkDeviceMemory memory); + void gen75_UnmapMemory(VkDevice device, VkDeviceMemory memory); + void gen8_UnmapMemory(VkDevice device, VkDeviceMemory memory); + void gen9_UnmapMemory(VkDevice device, VkDeviceMemory memory); + void gen10_UnmapMemory(VkDevice device, VkDeviceMemory memory); + void gen11_UnmapMemory(VkDevice device, VkDeviceMemory memory); + VkResult anv_FlushMappedMemoryRanges(VkDevice device, uint32_t memoryRangeCount, const VkMappedMemoryRange* pMemoryRanges); + VkResult gen7_FlushMappedMemoryRanges(VkDevice device, uint32_t memoryRangeCount, const VkMappedMemoryRange* pMemoryRanges); + VkResult gen75_FlushMappedMemoryRanges(VkDevice device, uint32_t memoryRangeCount, const VkMappedMemoryRange* pMemoryRanges); + VkResult gen8_FlushMappedMemoryRanges(VkDevice device, uint32_t memoryRangeCount, const VkMappedMemoryRange* pMemoryRanges); + VkResult gen9_FlushMappedMemoryRanges(VkDevice device, uint32_t memoryRangeCount, const VkMappedMemoryRange* pMemoryRanges); + VkResult gen10_FlushMappedMemoryRanges(VkDevice device, uint32_t memoryRangeCount, const VkMappedMemoryRange* pMemoryRanges); + VkResult gen11_FlushMappedMemoryRanges(VkDevice device, uint32_t memoryRangeCount, const VkMappedMemoryRange* pMemoryRanges); + VkResult anv_InvalidateMappedMemoryRanges(VkDevice device, uint32_t memoryRangeCount, const VkMappedMemoryRange* pMemoryRanges); + VkResult gen7_InvalidateMappedMemoryRanges(VkDevice device, uint32_t memoryRangeCount, const VkMappedMemoryRange* pMemoryRanges); + VkResult gen75_InvalidateMappedMemoryRanges(VkDevice device, uint32_t memoryRangeCount, const VkMappedMemoryRange* pMemoryRanges); + VkResult gen8_InvalidateMappedMemoryRanges(VkDevice device, uint32_t memoryRangeCount, const VkMappedMemoryRange* pMemoryRanges); + VkResult gen9_InvalidateMappedMemoryRanges(VkDevice device, uint32_t memoryRangeCount, const VkMappedMemoryRange* pMemoryRanges); + VkResult gen10_InvalidateMappedMemoryRanges(VkDevice device, uint32_t memoryRangeCount, const VkMappedMemoryRange* pMemoryRanges); + VkResult gen11_InvalidateMappedMemoryRanges(VkDevice device, uint32_t memoryRangeCount, const VkMappedMemoryRange* pMemoryRanges); + void anv_GetDeviceMemoryCommitment(VkDevice device, VkDeviceMemory memory, VkDeviceSize* pCommittedMemoryInBytes); + void gen7_GetDeviceMemoryCommitment(VkDevice device, VkDeviceMemory memory, VkDeviceSize* pCommittedMemoryInBytes); + void gen75_GetDeviceMemoryCommitment(VkDevice device, VkDeviceMemory memory, VkDeviceSize* pCommittedMemoryInBytes); + void gen8_GetDeviceMemoryCommitment(VkDevice device, VkDeviceMemory memory, VkDeviceSize* pCommittedMemoryInBytes); + void gen9_GetDeviceMemoryCommitment(VkDevice device, VkDeviceMemory memory, VkDeviceSize* pCommittedMemoryInBytes); + void gen10_GetDeviceMemoryCommitment(VkDevice device, VkDeviceMemory memory, VkDeviceSize* pCommittedMemoryInBytes); + void gen11_GetDeviceMemoryCommitment(VkDevice device, VkDeviceMemory memory, VkDeviceSize* pCommittedMemoryInBytes); + void anv_GetBufferMemoryRequirements(VkDevice device, VkBuffer buffer, VkMemoryRequirements* pMemoryRequirements); + void gen7_GetBufferMemoryRequirements(VkDevice device, VkBuffer buffer, VkMemoryRequirements* pMemoryRequirements); + void gen75_GetBufferMemoryRequirements(VkDevice device, VkBuffer buffer, VkMemoryRequirements* pMemoryRequirements); + void gen8_GetBufferMemoryRequirements(VkDevice device, VkBuffer buffer, VkMemoryRequirements* pMemoryRequirements); + void gen9_GetBufferMemoryRequirements(VkDevice device, VkBuffer buffer, VkMemoryRequirements* pMemoryRequirements); + void gen10_GetBufferMemoryRequirements(VkDevice device, VkBuffer buffer, VkMemoryRequirements* pMemoryRequirements); + void gen11_GetBufferMemoryRequirements(VkDevice device, VkBuffer buffer, VkMemoryRequirements* pMemoryRequirements); + VkResult anv_BindBufferMemory(VkDevice device, VkBuffer buffer, VkDeviceMemory memory, VkDeviceSize memoryOffset); + VkResult gen7_BindBufferMemory(VkDevice device, VkBuffer buffer, VkDeviceMemory memory, VkDeviceSize memoryOffset); + VkResult gen75_BindBufferMemory(VkDevice device, VkBuffer buffer, VkDeviceMemory memory, VkDeviceSize memoryOffset); + VkResult gen8_BindBufferMemory(VkDevice device, VkBuffer buffer, VkDeviceMemory memory, VkDeviceSize memoryOffset); + VkResult gen9_BindBufferMemory(VkDevice device, VkBuffer buffer, VkDeviceMemory memory, VkDeviceSize memoryOffset); + VkResult gen10_BindBufferMemory(VkDevice device, VkBuffer buffer, VkDeviceMemory memory, VkDeviceSize memoryOffset); + VkResult gen11_BindBufferMemory(VkDevice device, VkBuffer buffer, VkDeviceMemory memory, VkDeviceSize memoryOffset); + void anv_GetImageMemoryRequirements(VkDevice device, VkImage image, VkMemoryRequirements* pMemoryRequirements); + void gen7_GetImageMemoryRequirements(VkDevice device, VkImage image, VkMemoryRequirements* pMemoryRequirements); + void gen75_GetImageMemoryRequirements(VkDevice device, VkImage image, VkMemoryRequirements* pMemoryRequirements); + void gen8_GetImageMemoryRequirements(VkDevice device, VkImage image, VkMemoryRequirements* pMemoryRequirements); + void gen9_GetImageMemoryRequirements(VkDevice device, VkImage image, VkMemoryRequirements* pMemoryRequirements); + void gen10_GetImageMemoryRequirements(VkDevice device, VkImage image, VkMemoryRequirements* pMemoryRequirements); + void gen11_GetImageMemoryRequirements(VkDevice device, VkImage image, VkMemoryRequirements* pMemoryRequirements); + VkResult anv_BindImageMemory(VkDevice device, VkImage image, VkDeviceMemory memory, VkDeviceSize memoryOffset); + VkResult gen7_BindImageMemory(VkDevice device, VkImage image, VkDeviceMemory memory, VkDeviceSize memoryOffset); + VkResult gen75_BindImageMemory(VkDevice device, VkImage image, VkDeviceMemory memory, VkDeviceSize memoryOffset); + VkResult gen8_BindImageMemory(VkDevice device, VkImage image, VkDeviceMemory memory, VkDeviceSize memoryOffset); + VkResult gen9_BindImageMemory(VkDevice device, VkImage image, VkDeviceMemory memory, VkDeviceSize memoryOffset); + VkResult gen10_BindImageMemory(VkDevice device, VkImage image, VkDeviceMemory memory, VkDeviceSize memoryOffset); + VkResult gen11_BindImageMemory(VkDevice device, VkImage image, VkDeviceMemory memory, VkDeviceSize memoryOffset); + void anv_GetImageSparseMemoryRequirements(VkDevice device, VkImage image, uint32_t* pSparseMemoryRequirementCount, VkSparseImageMemoryRequirements* pSparseMemoryRequirements); + void gen7_GetImageSparseMemoryRequirements(VkDevice device, VkImage image, uint32_t* pSparseMemoryRequirementCount, VkSparseImageMemoryRequirements* pSparseMemoryRequirements); + void gen75_GetImageSparseMemoryRequirements(VkDevice device, VkImage image, uint32_t* pSparseMemoryRequirementCount, VkSparseImageMemoryRequirements* pSparseMemoryRequirements); + void gen8_GetImageSparseMemoryRequirements(VkDevice device, VkImage image, uint32_t* pSparseMemoryRequirementCount, VkSparseImageMemoryRequirements* pSparseMemoryRequirements); + void gen9_GetImageSparseMemoryRequirements(VkDevice device, VkImage image, uint32_t* pSparseMemoryRequirementCount, VkSparseImageMemoryRequirements* pSparseMemoryRequirements); + void gen10_GetImageSparseMemoryRequirements(VkDevice device, VkImage image, uint32_t* pSparseMemoryRequirementCount, VkSparseImageMemoryRequirements* pSparseMemoryRequirements); + void gen11_GetImageSparseMemoryRequirements(VkDevice device, VkImage image, uint32_t* pSparseMemoryRequirementCount, VkSparseImageMemoryRequirements* pSparseMemoryRequirements); + VkResult anv_QueueBindSparse(VkQueue queue, uint32_t bindInfoCount, const VkBindSparseInfo* pBindInfo, VkFence fence); + VkResult gen7_QueueBindSparse(VkQueue queue, uint32_t bindInfoCount, const VkBindSparseInfo* pBindInfo, VkFence fence); + VkResult gen75_QueueBindSparse(VkQueue queue, uint32_t bindInfoCount, const VkBindSparseInfo* pBindInfo, VkFence fence); + VkResult gen8_QueueBindSparse(VkQueue queue, uint32_t bindInfoCount, const VkBindSparseInfo* pBindInfo, VkFence fence); + VkResult gen9_QueueBindSparse(VkQueue queue, uint32_t bindInfoCount, const VkBindSparseInfo* pBindInfo, VkFence fence); + VkResult gen10_QueueBindSparse(VkQueue queue, uint32_t bindInfoCount, const VkBindSparseInfo* pBindInfo, VkFence fence); + VkResult gen11_QueueBindSparse(VkQueue queue, uint32_t bindInfoCount, const VkBindSparseInfo* pBindInfo, VkFence fence); + VkResult anv_CreateFence(VkDevice device, const VkFenceCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence); + VkResult gen7_CreateFence(VkDevice device, const VkFenceCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence); + VkResult gen75_CreateFence(VkDevice device, const VkFenceCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence); + VkResult gen8_CreateFence(VkDevice device, const VkFenceCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence); + VkResult gen9_CreateFence(VkDevice device, const VkFenceCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence); + VkResult gen10_CreateFence(VkDevice device, const VkFenceCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence); + VkResult gen11_CreateFence(VkDevice device, const VkFenceCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence); + void anv_DestroyFence(VkDevice device, VkFence fence, const VkAllocationCallbacks* pAllocator); + void gen7_DestroyFence(VkDevice device, VkFence fence, const VkAllocationCallbacks* pAllocator); + void gen75_DestroyFence(VkDevice device, VkFence fence, const VkAllocationCallbacks* pAllocator); + void gen8_DestroyFence(VkDevice device, VkFence fence, const VkAllocationCallbacks* pAllocator); + void gen9_DestroyFence(VkDevice device, VkFence fence, const VkAllocationCallbacks* pAllocator); + void gen10_DestroyFence(VkDevice device, VkFence fence, const VkAllocationCallbacks* pAllocator); + void gen11_DestroyFence(VkDevice device, VkFence fence, const VkAllocationCallbacks* pAllocator); + VkResult anv_ResetFences(VkDevice device, uint32_t fenceCount, const VkFence* pFences); + VkResult gen7_ResetFences(VkDevice device, uint32_t fenceCount, const VkFence* pFences); + VkResult gen75_ResetFences(VkDevice device, uint32_t fenceCount, const VkFence* pFences); + VkResult gen8_ResetFences(VkDevice device, uint32_t fenceCount, const VkFence* pFences); + VkResult gen9_ResetFences(VkDevice device, uint32_t fenceCount, const VkFence* pFences); + VkResult gen10_ResetFences(VkDevice device, uint32_t fenceCount, const VkFence* pFences); + VkResult gen11_ResetFences(VkDevice device, uint32_t fenceCount, const VkFence* pFences); + VkResult anv_GetFenceStatus(VkDevice device, VkFence fence); + VkResult gen7_GetFenceStatus(VkDevice device, VkFence fence); + VkResult gen75_GetFenceStatus(VkDevice device, VkFence fence); + VkResult gen8_GetFenceStatus(VkDevice device, VkFence fence); + VkResult gen9_GetFenceStatus(VkDevice device, VkFence fence); + VkResult gen10_GetFenceStatus(VkDevice device, VkFence fence); + VkResult gen11_GetFenceStatus(VkDevice device, VkFence fence); + VkResult anv_WaitForFences(VkDevice device, uint32_t fenceCount, const VkFence* pFences, VkBool32 waitAll, uint64_t timeout); + VkResult gen7_WaitForFences(VkDevice device, uint32_t fenceCount, const VkFence* pFences, VkBool32 waitAll, uint64_t timeout); + VkResult gen75_WaitForFences(VkDevice device, uint32_t fenceCount, const VkFence* pFences, VkBool32 waitAll, uint64_t timeout); + VkResult gen8_WaitForFences(VkDevice device, uint32_t fenceCount, const VkFence* pFences, VkBool32 waitAll, uint64_t timeout); + VkResult gen9_WaitForFences(VkDevice device, uint32_t fenceCount, const VkFence* pFences, VkBool32 waitAll, uint64_t timeout); + VkResult gen10_WaitForFences(VkDevice device, uint32_t fenceCount, const VkFence* pFences, VkBool32 waitAll, uint64_t timeout); + VkResult gen11_WaitForFences(VkDevice device, uint32_t fenceCount, const VkFence* pFences, VkBool32 waitAll, uint64_t timeout); + VkResult anv_CreateSemaphore(VkDevice device, const VkSemaphoreCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSemaphore* pSemaphore); + VkResult gen7_CreateSemaphore(VkDevice device, const VkSemaphoreCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSemaphore* pSemaphore); + VkResult gen75_CreateSemaphore(VkDevice device, const VkSemaphoreCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSemaphore* pSemaphore); + VkResult gen8_CreateSemaphore(VkDevice device, const VkSemaphoreCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSemaphore* pSemaphore); + VkResult gen9_CreateSemaphore(VkDevice device, const VkSemaphoreCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSemaphore* pSemaphore); + VkResult gen10_CreateSemaphore(VkDevice device, const VkSemaphoreCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSemaphore* pSemaphore); + VkResult gen11_CreateSemaphore(VkDevice device, const VkSemaphoreCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSemaphore* pSemaphore); + void anv_DestroySemaphore(VkDevice device, VkSemaphore semaphore, const VkAllocationCallbacks* pAllocator); + void gen7_DestroySemaphore(VkDevice device, VkSemaphore semaphore, const VkAllocationCallbacks* pAllocator); + void gen75_DestroySemaphore(VkDevice device, VkSemaphore semaphore, const VkAllocationCallbacks* pAllocator); + void gen8_DestroySemaphore(VkDevice device, VkSemaphore semaphore, const VkAllocationCallbacks* pAllocator); + void gen9_DestroySemaphore(VkDevice device, VkSemaphore semaphore, const VkAllocationCallbacks* pAllocator); + void gen10_DestroySemaphore(VkDevice device, VkSemaphore semaphore, const VkAllocationCallbacks* pAllocator); + void gen11_DestroySemaphore(VkDevice device, VkSemaphore semaphore, const VkAllocationCallbacks* pAllocator); + VkResult anv_CreateEvent(VkDevice device, const VkEventCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkEvent* pEvent); + VkResult gen7_CreateEvent(VkDevice device, const VkEventCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkEvent* pEvent); + VkResult gen75_CreateEvent(VkDevice device, const VkEventCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkEvent* pEvent); + VkResult gen8_CreateEvent(VkDevice device, const VkEventCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkEvent* pEvent); + VkResult gen9_CreateEvent(VkDevice device, const VkEventCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkEvent* pEvent); + VkResult gen10_CreateEvent(VkDevice device, const VkEventCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkEvent* pEvent); + VkResult gen11_CreateEvent(VkDevice device, const VkEventCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkEvent* pEvent); + void anv_DestroyEvent(VkDevice device, VkEvent event, const VkAllocationCallbacks* pAllocator); + void gen7_DestroyEvent(VkDevice device, VkEvent event, const VkAllocationCallbacks* pAllocator); + void gen75_DestroyEvent(VkDevice device, VkEvent event, const VkAllocationCallbacks* pAllocator); + void gen8_DestroyEvent(VkDevice device, VkEvent event, const VkAllocationCallbacks* pAllocator); + void gen9_DestroyEvent(VkDevice device, VkEvent event, const VkAllocationCallbacks* pAllocator); + void gen10_DestroyEvent(VkDevice device, VkEvent event, const VkAllocationCallbacks* pAllocator); + void gen11_DestroyEvent(VkDevice device, VkEvent event, const VkAllocationCallbacks* pAllocator); + VkResult anv_GetEventStatus(VkDevice device, VkEvent event); + VkResult gen7_GetEventStatus(VkDevice device, VkEvent event); + VkResult gen75_GetEventStatus(VkDevice device, VkEvent event); + VkResult gen8_GetEventStatus(VkDevice device, VkEvent event); + VkResult gen9_GetEventStatus(VkDevice device, VkEvent event); + VkResult gen10_GetEventStatus(VkDevice device, VkEvent event); + VkResult gen11_GetEventStatus(VkDevice device, VkEvent event); + VkResult anv_SetEvent(VkDevice device, VkEvent event); + VkResult gen7_SetEvent(VkDevice device, VkEvent event); + VkResult gen75_SetEvent(VkDevice device, VkEvent event); + VkResult gen8_SetEvent(VkDevice device, VkEvent event); + VkResult gen9_SetEvent(VkDevice device, VkEvent event); + VkResult gen10_SetEvent(VkDevice device, VkEvent event); + VkResult gen11_SetEvent(VkDevice device, VkEvent event); + VkResult anv_ResetEvent(VkDevice device, VkEvent event); + VkResult gen7_ResetEvent(VkDevice device, VkEvent event); + VkResult gen75_ResetEvent(VkDevice device, VkEvent event); + VkResult gen8_ResetEvent(VkDevice device, VkEvent event); + VkResult gen9_ResetEvent(VkDevice device, VkEvent event); + VkResult gen10_ResetEvent(VkDevice device, VkEvent event); + VkResult gen11_ResetEvent(VkDevice device, VkEvent event); + VkResult anv_CreateQueryPool(VkDevice device, const VkQueryPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkQueryPool* pQueryPool); + VkResult gen7_CreateQueryPool(VkDevice device, const VkQueryPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkQueryPool* pQueryPool); + VkResult gen75_CreateQueryPool(VkDevice device, const VkQueryPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkQueryPool* pQueryPool); + VkResult gen8_CreateQueryPool(VkDevice device, const VkQueryPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkQueryPool* pQueryPool); + VkResult gen9_CreateQueryPool(VkDevice device, const VkQueryPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkQueryPool* pQueryPool); + VkResult gen10_CreateQueryPool(VkDevice device, const VkQueryPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkQueryPool* pQueryPool); + VkResult gen11_CreateQueryPool(VkDevice device, const VkQueryPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkQueryPool* pQueryPool); + void anv_DestroyQueryPool(VkDevice device, VkQueryPool queryPool, const VkAllocationCallbacks* pAllocator); + void gen7_DestroyQueryPool(VkDevice device, VkQueryPool queryPool, const VkAllocationCallbacks* pAllocator); + void gen75_DestroyQueryPool(VkDevice device, VkQueryPool queryPool, const VkAllocationCallbacks* pAllocator); + void gen8_DestroyQueryPool(VkDevice device, VkQueryPool queryPool, const VkAllocationCallbacks* pAllocator); + void gen9_DestroyQueryPool(VkDevice device, VkQueryPool queryPool, const VkAllocationCallbacks* pAllocator); + void gen10_DestroyQueryPool(VkDevice device, VkQueryPool queryPool, const VkAllocationCallbacks* pAllocator); + void gen11_DestroyQueryPool(VkDevice device, VkQueryPool queryPool, const VkAllocationCallbacks* pAllocator); + VkResult anv_GetQueryPoolResults(VkDevice device, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount, size_t dataSize, void* pData, VkDeviceSize stride, VkQueryResultFlags flags); + VkResult gen7_GetQueryPoolResults(VkDevice device, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount, size_t dataSize, void* pData, VkDeviceSize stride, VkQueryResultFlags flags); + VkResult gen75_GetQueryPoolResults(VkDevice device, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount, size_t dataSize, void* pData, VkDeviceSize stride, VkQueryResultFlags flags); + VkResult gen8_GetQueryPoolResults(VkDevice device, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount, size_t dataSize, void* pData, VkDeviceSize stride, VkQueryResultFlags flags); + VkResult gen9_GetQueryPoolResults(VkDevice device, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount, size_t dataSize, void* pData, VkDeviceSize stride, VkQueryResultFlags flags); + VkResult gen10_GetQueryPoolResults(VkDevice device, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount, size_t dataSize, void* pData, VkDeviceSize stride, VkQueryResultFlags flags); + VkResult gen11_GetQueryPoolResults(VkDevice device, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount, size_t dataSize, void* pData, VkDeviceSize stride, VkQueryResultFlags flags); + VkResult anv_CreateBuffer(VkDevice device, const VkBufferCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkBuffer* pBuffer); + VkResult gen7_CreateBuffer(VkDevice device, const VkBufferCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkBuffer* pBuffer); + VkResult gen75_CreateBuffer(VkDevice device, const VkBufferCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkBuffer* pBuffer); + VkResult gen8_CreateBuffer(VkDevice device, const VkBufferCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkBuffer* pBuffer); + VkResult gen9_CreateBuffer(VkDevice device, const VkBufferCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkBuffer* pBuffer); + VkResult gen10_CreateBuffer(VkDevice device, const VkBufferCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkBuffer* pBuffer); + VkResult gen11_CreateBuffer(VkDevice device, const VkBufferCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkBuffer* pBuffer); + void anv_DestroyBuffer(VkDevice device, VkBuffer buffer, const VkAllocationCallbacks* pAllocator); + void gen7_DestroyBuffer(VkDevice device, VkBuffer buffer, const VkAllocationCallbacks* pAllocator); + void gen75_DestroyBuffer(VkDevice device, VkBuffer buffer, const VkAllocationCallbacks* pAllocator); + void gen8_DestroyBuffer(VkDevice device, VkBuffer buffer, const VkAllocationCallbacks* pAllocator); + void gen9_DestroyBuffer(VkDevice device, VkBuffer buffer, const VkAllocationCallbacks* pAllocator); + void gen10_DestroyBuffer(VkDevice device, VkBuffer buffer, const VkAllocationCallbacks* pAllocator); + void gen11_DestroyBuffer(VkDevice device, VkBuffer buffer, const VkAllocationCallbacks* pAllocator); + VkResult anv_CreateBufferView(VkDevice device, const VkBufferViewCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkBufferView* pView); + VkResult gen7_CreateBufferView(VkDevice device, const VkBufferViewCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkBufferView* pView); + VkResult gen75_CreateBufferView(VkDevice device, const VkBufferViewCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkBufferView* pView); + VkResult gen8_CreateBufferView(VkDevice device, const VkBufferViewCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkBufferView* pView); + VkResult gen9_CreateBufferView(VkDevice device, const VkBufferViewCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkBufferView* pView); + VkResult gen10_CreateBufferView(VkDevice device, const VkBufferViewCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkBufferView* pView); + VkResult gen11_CreateBufferView(VkDevice device, const VkBufferViewCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkBufferView* pView); + void anv_DestroyBufferView(VkDevice device, VkBufferView bufferView, const VkAllocationCallbacks* pAllocator); + void gen7_DestroyBufferView(VkDevice device, VkBufferView bufferView, const VkAllocationCallbacks* pAllocator); + void gen75_DestroyBufferView(VkDevice device, VkBufferView bufferView, const VkAllocationCallbacks* pAllocator); + void gen8_DestroyBufferView(VkDevice device, VkBufferView bufferView, const VkAllocationCallbacks* pAllocator); + void gen9_DestroyBufferView(VkDevice device, VkBufferView bufferView, const VkAllocationCallbacks* pAllocator); + void gen10_DestroyBufferView(VkDevice device, VkBufferView bufferView, const VkAllocationCallbacks* pAllocator); + void gen11_DestroyBufferView(VkDevice device, VkBufferView bufferView, const VkAllocationCallbacks* pAllocator); + VkResult anv_CreateImage(VkDevice device, const VkImageCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkImage* pImage); + VkResult gen7_CreateImage(VkDevice device, const VkImageCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkImage* pImage); + VkResult gen75_CreateImage(VkDevice device, const VkImageCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkImage* pImage); + VkResult gen8_CreateImage(VkDevice device, const VkImageCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkImage* pImage); + VkResult gen9_CreateImage(VkDevice device, const VkImageCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkImage* pImage); + VkResult gen10_CreateImage(VkDevice device, const VkImageCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkImage* pImage); + VkResult gen11_CreateImage(VkDevice device, const VkImageCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkImage* pImage); + void anv_DestroyImage(VkDevice device, VkImage image, const VkAllocationCallbacks* pAllocator); + void gen7_DestroyImage(VkDevice device, VkImage image, const VkAllocationCallbacks* pAllocator); + void gen75_DestroyImage(VkDevice device, VkImage image, const VkAllocationCallbacks* pAllocator); + void gen8_DestroyImage(VkDevice device, VkImage image, const VkAllocationCallbacks* pAllocator); + void gen9_DestroyImage(VkDevice device, VkImage image, const VkAllocationCallbacks* pAllocator); + void gen10_DestroyImage(VkDevice device, VkImage image, const VkAllocationCallbacks* pAllocator); + void gen11_DestroyImage(VkDevice device, VkImage image, const VkAllocationCallbacks* pAllocator); + void anv_GetImageSubresourceLayout(VkDevice device, VkImage image, const VkImageSubresource* pSubresource, VkSubresourceLayout* pLayout); + void gen7_GetImageSubresourceLayout(VkDevice device, VkImage image, const VkImageSubresource* pSubresource, VkSubresourceLayout* pLayout); + void gen75_GetImageSubresourceLayout(VkDevice device, VkImage image, const VkImageSubresource* pSubresource, VkSubresourceLayout* pLayout); + void gen8_GetImageSubresourceLayout(VkDevice device, VkImage image, const VkImageSubresource* pSubresource, VkSubresourceLayout* pLayout); + void gen9_GetImageSubresourceLayout(VkDevice device, VkImage image, const VkImageSubresource* pSubresource, VkSubresourceLayout* pLayout); + void gen10_GetImageSubresourceLayout(VkDevice device, VkImage image, const VkImageSubresource* pSubresource, VkSubresourceLayout* pLayout); + void gen11_GetImageSubresourceLayout(VkDevice device, VkImage image, const VkImageSubresource* pSubresource, VkSubresourceLayout* pLayout); + VkResult anv_CreateImageView(VkDevice device, const VkImageViewCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkImageView* pView); + VkResult gen7_CreateImageView(VkDevice device, const VkImageViewCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkImageView* pView); + VkResult gen75_CreateImageView(VkDevice device, const VkImageViewCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkImageView* pView); + VkResult gen8_CreateImageView(VkDevice device, const VkImageViewCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkImageView* pView); + VkResult gen9_CreateImageView(VkDevice device, const VkImageViewCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkImageView* pView); + VkResult gen10_CreateImageView(VkDevice device, const VkImageViewCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkImageView* pView); + VkResult gen11_CreateImageView(VkDevice device, const VkImageViewCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkImageView* pView); + void anv_DestroyImageView(VkDevice device, VkImageView imageView, const VkAllocationCallbacks* pAllocator); + void gen7_DestroyImageView(VkDevice device, VkImageView imageView, const VkAllocationCallbacks* pAllocator); + void gen75_DestroyImageView(VkDevice device, VkImageView imageView, const VkAllocationCallbacks* pAllocator); + void gen8_DestroyImageView(VkDevice device, VkImageView imageView, const VkAllocationCallbacks* pAllocator); + void gen9_DestroyImageView(VkDevice device, VkImageView imageView, const VkAllocationCallbacks* pAllocator); + void gen10_DestroyImageView(VkDevice device, VkImageView imageView, const VkAllocationCallbacks* pAllocator); + void gen11_DestroyImageView(VkDevice device, VkImageView imageView, const VkAllocationCallbacks* pAllocator); + VkResult anv_CreateShaderModule(VkDevice device, const VkShaderModuleCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkShaderModule* pShaderModule); + VkResult gen7_CreateShaderModule(VkDevice device, const VkShaderModuleCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkShaderModule* pShaderModule); + VkResult gen75_CreateShaderModule(VkDevice device, const VkShaderModuleCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkShaderModule* pShaderModule); + VkResult gen8_CreateShaderModule(VkDevice device, const VkShaderModuleCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkShaderModule* pShaderModule); + VkResult gen9_CreateShaderModule(VkDevice device, const VkShaderModuleCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkShaderModule* pShaderModule); + VkResult gen10_CreateShaderModule(VkDevice device, const VkShaderModuleCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkShaderModule* pShaderModule); + VkResult gen11_CreateShaderModule(VkDevice device, const VkShaderModuleCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkShaderModule* pShaderModule); + void anv_DestroyShaderModule(VkDevice device, VkShaderModule shaderModule, const VkAllocationCallbacks* pAllocator); + void gen7_DestroyShaderModule(VkDevice device, VkShaderModule shaderModule, const VkAllocationCallbacks* pAllocator); + void gen75_DestroyShaderModule(VkDevice device, VkShaderModule shaderModule, const VkAllocationCallbacks* pAllocator); + void gen8_DestroyShaderModule(VkDevice device, VkShaderModule shaderModule, const VkAllocationCallbacks* pAllocator); + void gen9_DestroyShaderModule(VkDevice device, VkShaderModule shaderModule, const VkAllocationCallbacks* pAllocator); + void gen10_DestroyShaderModule(VkDevice device, VkShaderModule shaderModule, const VkAllocationCallbacks* pAllocator); + void gen11_DestroyShaderModule(VkDevice device, VkShaderModule shaderModule, const VkAllocationCallbacks* pAllocator); + VkResult anv_CreatePipelineCache(VkDevice device, const VkPipelineCacheCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkPipelineCache* pPipelineCache); + VkResult gen7_CreatePipelineCache(VkDevice device, const VkPipelineCacheCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkPipelineCache* pPipelineCache); + VkResult gen75_CreatePipelineCache(VkDevice device, const VkPipelineCacheCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkPipelineCache* pPipelineCache); + VkResult gen8_CreatePipelineCache(VkDevice device, const VkPipelineCacheCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkPipelineCache* pPipelineCache); + VkResult gen9_CreatePipelineCache(VkDevice device, const VkPipelineCacheCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkPipelineCache* pPipelineCache); + VkResult gen10_CreatePipelineCache(VkDevice device, const VkPipelineCacheCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkPipelineCache* pPipelineCache); + VkResult gen11_CreatePipelineCache(VkDevice device, const VkPipelineCacheCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkPipelineCache* pPipelineCache); + void anv_DestroyPipelineCache(VkDevice device, VkPipelineCache pipelineCache, const VkAllocationCallbacks* pAllocator); + void gen7_DestroyPipelineCache(VkDevice device, VkPipelineCache pipelineCache, const VkAllocationCallbacks* pAllocator); + void gen75_DestroyPipelineCache(VkDevice device, VkPipelineCache pipelineCache, const VkAllocationCallbacks* pAllocator); + void gen8_DestroyPipelineCache(VkDevice device, VkPipelineCache pipelineCache, const VkAllocationCallbacks* pAllocator); + void gen9_DestroyPipelineCache(VkDevice device, VkPipelineCache pipelineCache, const VkAllocationCallbacks* pAllocator); + void gen10_DestroyPipelineCache(VkDevice device, VkPipelineCache pipelineCache, const VkAllocationCallbacks* pAllocator); + void gen11_DestroyPipelineCache(VkDevice device, VkPipelineCache pipelineCache, const VkAllocationCallbacks* pAllocator); + VkResult anv_GetPipelineCacheData(VkDevice device, VkPipelineCache pipelineCache, size_t* pDataSize, void* pData); + VkResult gen7_GetPipelineCacheData(VkDevice device, VkPipelineCache pipelineCache, size_t* pDataSize, void* pData); + VkResult gen75_GetPipelineCacheData(VkDevice device, VkPipelineCache pipelineCache, size_t* pDataSize, void* pData); + VkResult gen8_GetPipelineCacheData(VkDevice device, VkPipelineCache pipelineCache, size_t* pDataSize, void* pData); + VkResult gen9_GetPipelineCacheData(VkDevice device, VkPipelineCache pipelineCache, size_t* pDataSize, void* pData); + VkResult gen10_GetPipelineCacheData(VkDevice device, VkPipelineCache pipelineCache, size_t* pDataSize, void* pData); + VkResult gen11_GetPipelineCacheData(VkDevice device, VkPipelineCache pipelineCache, size_t* pDataSize, void* pData); + VkResult anv_MergePipelineCaches(VkDevice device, VkPipelineCache dstCache, uint32_t srcCacheCount, const VkPipelineCache* pSrcCaches); + VkResult gen7_MergePipelineCaches(VkDevice device, VkPipelineCache dstCache, uint32_t srcCacheCount, const VkPipelineCache* pSrcCaches); + VkResult gen75_MergePipelineCaches(VkDevice device, VkPipelineCache dstCache, uint32_t srcCacheCount, const VkPipelineCache* pSrcCaches); + VkResult gen8_MergePipelineCaches(VkDevice device, VkPipelineCache dstCache, uint32_t srcCacheCount, const VkPipelineCache* pSrcCaches); + VkResult gen9_MergePipelineCaches(VkDevice device, VkPipelineCache dstCache, uint32_t srcCacheCount, const VkPipelineCache* pSrcCaches); + VkResult gen10_MergePipelineCaches(VkDevice device, VkPipelineCache dstCache, uint32_t srcCacheCount, const VkPipelineCache* pSrcCaches); + VkResult gen11_MergePipelineCaches(VkDevice device, VkPipelineCache dstCache, uint32_t srcCacheCount, const VkPipelineCache* pSrcCaches); + VkResult anv_CreateGraphicsPipelines(VkDevice device, VkPipelineCache pipelineCache, uint32_t createInfoCount, const VkGraphicsPipelineCreateInfo* pCreateInfos, const VkAllocationCallbacks* pAllocator, VkPipeline* pPipelines); + VkResult gen7_CreateGraphicsPipelines(VkDevice device, VkPipelineCache pipelineCache, uint32_t createInfoCount, const VkGraphicsPipelineCreateInfo* pCreateInfos, const VkAllocationCallbacks* pAllocator, VkPipeline* pPipelines); + VkResult gen75_CreateGraphicsPipelines(VkDevice device, VkPipelineCache pipelineCache, uint32_t createInfoCount, const VkGraphicsPipelineCreateInfo* pCreateInfos, const VkAllocationCallbacks* pAllocator, VkPipeline* pPipelines); + VkResult gen8_CreateGraphicsPipelines(VkDevice device, VkPipelineCache pipelineCache, uint32_t createInfoCount, const VkGraphicsPipelineCreateInfo* pCreateInfos, const VkAllocationCallbacks* pAllocator, VkPipeline* pPipelines); + VkResult gen9_CreateGraphicsPipelines(VkDevice device, VkPipelineCache pipelineCache, uint32_t createInfoCount, const VkGraphicsPipelineCreateInfo* pCreateInfos, const VkAllocationCallbacks* pAllocator, VkPipeline* pPipelines); + VkResult gen10_CreateGraphicsPipelines(VkDevice device, VkPipelineCache pipelineCache, uint32_t createInfoCount, const VkGraphicsPipelineCreateInfo* pCreateInfos, const VkAllocationCallbacks* pAllocator, VkPipeline* pPipelines); + VkResult gen11_CreateGraphicsPipelines(VkDevice device, VkPipelineCache pipelineCache, uint32_t createInfoCount, const VkGraphicsPipelineCreateInfo* pCreateInfos, const VkAllocationCallbacks* pAllocator, VkPipeline* pPipelines); + VkResult anv_CreateComputePipelines(VkDevice device, VkPipelineCache pipelineCache, uint32_t createInfoCount, const VkComputePipelineCreateInfo* pCreateInfos, const VkAllocationCallbacks* pAllocator, VkPipeline* pPipelines); + VkResult gen7_CreateComputePipelines(VkDevice device, VkPipelineCache pipelineCache, uint32_t createInfoCount, const VkComputePipelineCreateInfo* pCreateInfos, const VkAllocationCallbacks* pAllocator, VkPipeline* pPipelines); + VkResult gen75_CreateComputePipelines(VkDevice device, VkPipelineCache pipelineCache, uint32_t createInfoCount, const VkComputePipelineCreateInfo* pCreateInfos, const VkAllocationCallbacks* pAllocator, VkPipeline* pPipelines); + VkResult gen8_CreateComputePipelines(VkDevice device, VkPipelineCache pipelineCache, uint32_t createInfoCount, const VkComputePipelineCreateInfo* pCreateInfos, const VkAllocationCallbacks* pAllocator, VkPipeline* pPipelines); + VkResult gen9_CreateComputePipelines(VkDevice device, VkPipelineCache pipelineCache, uint32_t createInfoCount, const VkComputePipelineCreateInfo* pCreateInfos, const VkAllocationCallbacks* pAllocator, VkPipeline* pPipelines); + VkResult gen10_CreateComputePipelines(VkDevice device, VkPipelineCache pipelineCache, uint32_t createInfoCount, const VkComputePipelineCreateInfo* pCreateInfos, const VkAllocationCallbacks* pAllocator, VkPipeline* pPipelines); + VkResult gen11_CreateComputePipelines(VkDevice device, VkPipelineCache pipelineCache, uint32_t createInfoCount, const VkComputePipelineCreateInfo* pCreateInfos, const VkAllocationCallbacks* pAllocator, VkPipeline* pPipelines); + void anv_DestroyPipeline(VkDevice device, VkPipeline pipeline, const VkAllocationCallbacks* pAllocator); + void gen7_DestroyPipeline(VkDevice device, VkPipeline pipeline, const VkAllocationCallbacks* pAllocator); + void gen75_DestroyPipeline(VkDevice device, VkPipeline pipeline, const VkAllocationCallbacks* pAllocator); + void gen8_DestroyPipeline(VkDevice device, VkPipeline pipeline, const VkAllocationCallbacks* pAllocator); + void gen9_DestroyPipeline(VkDevice device, VkPipeline pipeline, const VkAllocationCallbacks* pAllocator); + void gen10_DestroyPipeline(VkDevice device, VkPipeline pipeline, const VkAllocationCallbacks* pAllocator); + void gen11_DestroyPipeline(VkDevice device, VkPipeline pipeline, const VkAllocationCallbacks* pAllocator); + VkResult anv_CreatePipelineLayout(VkDevice device, const VkPipelineLayoutCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkPipelineLayout* pPipelineLayout); + VkResult gen7_CreatePipelineLayout(VkDevice device, const VkPipelineLayoutCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkPipelineLayout* pPipelineLayout); + VkResult gen75_CreatePipelineLayout(VkDevice device, const VkPipelineLayoutCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkPipelineLayout* pPipelineLayout); + VkResult gen8_CreatePipelineLayout(VkDevice device, const VkPipelineLayoutCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkPipelineLayout* pPipelineLayout); + VkResult gen9_CreatePipelineLayout(VkDevice device, const VkPipelineLayoutCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkPipelineLayout* pPipelineLayout); + VkResult gen10_CreatePipelineLayout(VkDevice device, const VkPipelineLayoutCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkPipelineLayout* pPipelineLayout); + VkResult gen11_CreatePipelineLayout(VkDevice device, const VkPipelineLayoutCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkPipelineLayout* pPipelineLayout); + void anv_DestroyPipelineLayout(VkDevice device, VkPipelineLayout pipelineLayout, const VkAllocationCallbacks* pAllocator); + void gen7_DestroyPipelineLayout(VkDevice device, VkPipelineLayout pipelineLayout, const VkAllocationCallbacks* pAllocator); + void gen75_DestroyPipelineLayout(VkDevice device, VkPipelineLayout pipelineLayout, const VkAllocationCallbacks* pAllocator); + void gen8_DestroyPipelineLayout(VkDevice device, VkPipelineLayout pipelineLayout, const VkAllocationCallbacks* pAllocator); + void gen9_DestroyPipelineLayout(VkDevice device, VkPipelineLayout pipelineLayout, const VkAllocationCallbacks* pAllocator); + void gen10_DestroyPipelineLayout(VkDevice device, VkPipelineLayout pipelineLayout, const VkAllocationCallbacks* pAllocator); + void gen11_DestroyPipelineLayout(VkDevice device, VkPipelineLayout pipelineLayout, const VkAllocationCallbacks* pAllocator); + VkResult anv_CreateSampler(VkDevice device, const VkSamplerCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSampler* pSampler); + VkResult gen7_CreateSampler(VkDevice device, const VkSamplerCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSampler* pSampler); + VkResult gen75_CreateSampler(VkDevice device, const VkSamplerCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSampler* pSampler); + VkResult gen8_CreateSampler(VkDevice device, const VkSamplerCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSampler* pSampler); + VkResult gen9_CreateSampler(VkDevice device, const VkSamplerCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSampler* pSampler); + VkResult gen10_CreateSampler(VkDevice device, const VkSamplerCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSampler* pSampler); + VkResult gen11_CreateSampler(VkDevice device, const VkSamplerCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSampler* pSampler); + void anv_DestroySampler(VkDevice device, VkSampler sampler, const VkAllocationCallbacks* pAllocator); + void gen7_DestroySampler(VkDevice device, VkSampler sampler, const VkAllocationCallbacks* pAllocator); + void gen75_DestroySampler(VkDevice device, VkSampler sampler, const VkAllocationCallbacks* pAllocator); + void gen8_DestroySampler(VkDevice device, VkSampler sampler, const VkAllocationCallbacks* pAllocator); + void gen9_DestroySampler(VkDevice device, VkSampler sampler, const VkAllocationCallbacks* pAllocator); + void gen10_DestroySampler(VkDevice device, VkSampler sampler, const VkAllocationCallbacks* pAllocator); + void gen11_DestroySampler(VkDevice device, VkSampler sampler, const VkAllocationCallbacks* pAllocator); + VkResult anv_CreateDescriptorSetLayout(VkDevice device, const VkDescriptorSetLayoutCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorSetLayout* pSetLayout); + VkResult gen7_CreateDescriptorSetLayout(VkDevice device, const VkDescriptorSetLayoutCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorSetLayout* pSetLayout); + VkResult gen75_CreateDescriptorSetLayout(VkDevice device, const VkDescriptorSetLayoutCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorSetLayout* pSetLayout); + VkResult gen8_CreateDescriptorSetLayout(VkDevice device, const VkDescriptorSetLayoutCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorSetLayout* pSetLayout); + VkResult gen9_CreateDescriptorSetLayout(VkDevice device, const VkDescriptorSetLayoutCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorSetLayout* pSetLayout); + VkResult gen10_CreateDescriptorSetLayout(VkDevice device, const VkDescriptorSetLayoutCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorSetLayout* pSetLayout); + VkResult gen11_CreateDescriptorSetLayout(VkDevice device, const VkDescriptorSetLayoutCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorSetLayout* pSetLayout); + void anv_DestroyDescriptorSetLayout(VkDevice device, VkDescriptorSetLayout descriptorSetLayout, const VkAllocationCallbacks* pAllocator); + void gen7_DestroyDescriptorSetLayout(VkDevice device, VkDescriptorSetLayout descriptorSetLayout, const VkAllocationCallbacks* pAllocator); + void gen75_DestroyDescriptorSetLayout(VkDevice device, VkDescriptorSetLayout descriptorSetLayout, const VkAllocationCallbacks* pAllocator); + void gen8_DestroyDescriptorSetLayout(VkDevice device, VkDescriptorSetLayout descriptorSetLayout, const VkAllocationCallbacks* pAllocator); + void gen9_DestroyDescriptorSetLayout(VkDevice device, VkDescriptorSetLayout descriptorSetLayout, const VkAllocationCallbacks* pAllocator); + void gen10_DestroyDescriptorSetLayout(VkDevice device, VkDescriptorSetLayout descriptorSetLayout, const VkAllocationCallbacks* pAllocator); + void gen11_DestroyDescriptorSetLayout(VkDevice device, VkDescriptorSetLayout descriptorSetLayout, const VkAllocationCallbacks* pAllocator); + VkResult anv_CreateDescriptorPool(VkDevice device, const VkDescriptorPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorPool* pDescriptorPool); + VkResult gen7_CreateDescriptorPool(VkDevice device, const VkDescriptorPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorPool* pDescriptorPool); + VkResult gen75_CreateDescriptorPool(VkDevice device, const VkDescriptorPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorPool* pDescriptorPool); + VkResult gen8_CreateDescriptorPool(VkDevice device, const VkDescriptorPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorPool* pDescriptorPool); + VkResult gen9_CreateDescriptorPool(VkDevice device, const VkDescriptorPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorPool* pDescriptorPool); + VkResult gen10_CreateDescriptorPool(VkDevice device, const VkDescriptorPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorPool* pDescriptorPool); + VkResult gen11_CreateDescriptorPool(VkDevice device, const VkDescriptorPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorPool* pDescriptorPool); + void anv_DestroyDescriptorPool(VkDevice device, VkDescriptorPool descriptorPool, const VkAllocationCallbacks* pAllocator); + void gen7_DestroyDescriptorPool(VkDevice device, VkDescriptorPool descriptorPool, const VkAllocationCallbacks* pAllocator); + void gen75_DestroyDescriptorPool(VkDevice device, VkDescriptorPool descriptorPool, const VkAllocationCallbacks* pAllocator); + void gen8_DestroyDescriptorPool(VkDevice device, VkDescriptorPool descriptorPool, const VkAllocationCallbacks* pAllocator); + void gen9_DestroyDescriptorPool(VkDevice device, VkDescriptorPool descriptorPool, const VkAllocationCallbacks* pAllocator); + void gen10_DestroyDescriptorPool(VkDevice device, VkDescriptorPool descriptorPool, const VkAllocationCallbacks* pAllocator); + void gen11_DestroyDescriptorPool(VkDevice device, VkDescriptorPool descriptorPool, const VkAllocationCallbacks* pAllocator); + VkResult anv_ResetDescriptorPool(VkDevice device, VkDescriptorPool descriptorPool, VkDescriptorPoolResetFlags flags); + VkResult gen7_ResetDescriptorPool(VkDevice device, VkDescriptorPool descriptorPool, VkDescriptorPoolResetFlags flags); + VkResult gen75_ResetDescriptorPool(VkDevice device, VkDescriptorPool descriptorPool, VkDescriptorPoolResetFlags flags); + VkResult gen8_ResetDescriptorPool(VkDevice device, VkDescriptorPool descriptorPool, VkDescriptorPoolResetFlags flags); + VkResult gen9_ResetDescriptorPool(VkDevice device, VkDescriptorPool descriptorPool, VkDescriptorPoolResetFlags flags); + VkResult gen10_ResetDescriptorPool(VkDevice device, VkDescriptorPool descriptorPool, VkDescriptorPoolResetFlags flags); + VkResult gen11_ResetDescriptorPool(VkDevice device, VkDescriptorPool descriptorPool, VkDescriptorPoolResetFlags flags); + VkResult anv_AllocateDescriptorSets(VkDevice device, const VkDescriptorSetAllocateInfo* pAllocateInfo, VkDescriptorSet* pDescriptorSets); + VkResult gen7_AllocateDescriptorSets(VkDevice device, const VkDescriptorSetAllocateInfo* pAllocateInfo, VkDescriptorSet* pDescriptorSets); + VkResult gen75_AllocateDescriptorSets(VkDevice device, const VkDescriptorSetAllocateInfo* pAllocateInfo, VkDescriptorSet* pDescriptorSets); + VkResult gen8_AllocateDescriptorSets(VkDevice device, const VkDescriptorSetAllocateInfo* pAllocateInfo, VkDescriptorSet* pDescriptorSets); + VkResult gen9_AllocateDescriptorSets(VkDevice device, const VkDescriptorSetAllocateInfo* pAllocateInfo, VkDescriptorSet* pDescriptorSets); + VkResult gen10_AllocateDescriptorSets(VkDevice device, const VkDescriptorSetAllocateInfo* pAllocateInfo, VkDescriptorSet* pDescriptorSets); + VkResult gen11_AllocateDescriptorSets(VkDevice device, const VkDescriptorSetAllocateInfo* pAllocateInfo, VkDescriptorSet* pDescriptorSets); + VkResult anv_FreeDescriptorSets(VkDevice device, VkDescriptorPool descriptorPool, uint32_t descriptorSetCount, const VkDescriptorSet* pDescriptorSets); + VkResult gen7_FreeDescriptorSets(VkDevice device, VkDescriptorPool descriptorPool, uint32_t descriptorSetCount, const VkDescriptorSet* pDescriptorSets); + VkResult gen75_FreeDescriptorSets(VkDevice device, VkDescriptorPool descriptorPool, uint32_t descriptorSetCount, const VkDescriptorSet* pDescriptorSets); + VkResult gen8_FreeDescriptorSets(VkDevice device, VkDescriptorPool descriptorPool, uint32_t descriptorSetCount, const VkDescriptorSet* pDescriptorSets); + VkResult gen9_FreeDescriptorSets(VkDevice device, VkDescriptorPool descriptorPool, uint32_t descriptorSetCount, const VkDescriptorSet* pDescriptorSets); + VkResult gen10_FreeDescriptorSets(VkDevice device, VkDescriptorPool descriptorPool, uint32_t descriptorSetCount, const VkDescriptorSet* pDescriptorSets); + VkResult gen11_FreeDescriptorSets(VkDevice device, VkDescriptorPool descriptorPool, uint32_t descriptorSetCount, const VkDescriptorSet* pDescriptorSets); + void anv_UpdateDescriptorSets(VkDevice device, uint32_t descriptorWriteCount, const VkWriteDescriptorSet* pDescriptorWrites, uint32_t descriptorCopyCount, const VkCopyDescriptorSet* pDescriptorCopies); + void gen7_UpdateDescriptorSets(VkDevice device, uint32_t descriptorWriteCount, const VkWriteDescriptorSet* pDescriptorWrites, uint32_t descriptorCopyCount, const VkCopyDescriptorSet* pDescriptorCopies); + void gen75_UpdateDescriptorSets(VkDevice device, uint32_t descriptorWriteCount, const VkWriteDescriptorSet* pDescriptorWrites, uint32_t descriptorCopyCount, const VkCopyDescriptorSet* pDescriptorCopies); + void gen8_UpdateDescriptorSets(VkDevice device, uint32_t descriptorWriteCount, const VkWriteDescriptorSet* pDescriptorWrites, uint32_t descriptorCopyCount, const VkCopyDescriptorSet* pDescriptorCopies); + void gen9_UpdateDescriptorSets(VkDevice device, uint32_t descriptorWriteCount, const VkWriteDescriptorSet* pDescriptorWrites, uint32_t descriptorCopyCount, const VkCopyDescriptorSet* pDescriptorCopies); + void gen10_UpdateDescriptorSets(VkDevice device, uint32_t descriptorWriteCount, const VkWriteDescriptorSet* pDescriptorWrites, uint32_t descriptorCopyCount, const VkCopyDescriptorSet* pDescriptorCopies); + void gen11_UpdateDescriptorSets(VkDevice device, uint32_t descriptorWriteCount, const VkWriteDescriptorSet* pDescriptorWrites, uint32_t descriptorCopyCount, const VkCopyDescriptorSet* pDescriptorCopies); + VkResult anv_CreateFramebuffer(VkDevice device, const VkFramebufferCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkFramebuffer* pFramebuffer); + VkResult gen7_CreateFramebuffer(VkDevice device, const VkFramebufferCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkFramebuffer* pFramebuffer); + VkResult gen75_CreateFramebuffer(VkDevice device, const VkFramebufferCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkFramebuffer* pFramebuffer); + VkResult gen8_CreateFramebuffer(VkDevice device, const VkFramebufferCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkFramebuffer* pFramebuffer); + VkResult gen9_CreateFramebuffer(VkDevice device, const VkFramebufferCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkFramebuffer* pFramebuffer); + VkResult gen10_CreateFramebuffer(VkDevice device, const VkFramebufferCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkFramebuffer* pFramebuffer); + VkResult gen11_CreateFramebuffer(VkDevice device, const VkFramebufferCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkFramebuffer* pFramebuffer); + void anv_DestroyFramebuffer(VkDevice device, VkFramebuffer framebuffer, const VkAllocationCallbacks* pAllocator); + void gen7_DestroyFramebuffer(VkDevice device, VkFramebuffer framebuffer, const VkAllocationCallbacks* pAllocator); + void gen75_DestroyFramebuffer(VkDevice device, VkFramebuffer framebuffer, const VkAllocationCallbacks* pAllocator); + void gen8_DestroyFramebuffer(VkDevice device, VkFramebuffer framebuffer, const VkAllocationCallbacks* pAllocator); + void gen9_DestroyFramebuffer(VkDevice device, VkFramebuffer framebuffer, const VkAllocationCallbacks* pAllocator); + void gen10_DestroyFramebuffer(VkDevice device, VkFramebuffer framebuffer, const VkAllocationCallbacks* pAllocator); + void gen11_DestroyFramebuffer(VkDevice device, VkFramebuffer framebuffer, const VkAllocationCallbacks* pAllocator); + VkResult anv_CreateRenderPass(VkDevice device, const VkRenderPassCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkRenderPass* pRenderPass); + VkResult gen7_CreateRenderPass(VkDevice device, const VkRenderPassCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkRenderPass* pRenderPass); + VkResult gen75_CreateRenderPass(VkDevice device, const VkRenderPassCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkRenderPass* pRenderPass); + VkResult gen8_CreateRenderPass(VkDevice device, const VkRenderPassCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkRenderPass* pRenderPass); + VkResult gen9_CreateRenderPass(VkDevice device, const VkRenderPassCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkRenderPass* pRenderPass); + VkResult gen10_CreateRenderPass(VkDevice device, const VkRenderPassCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkRenderPass* pRenderPass); + VkResult gen11_CreateRenderPass(VkDevice device, const VkRenderPassCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkRenderPass* pRenderPass); + void anv_DestroyRenderPass(VkDevice device, VkRenderPass renderPass, const VkAllocationCallbacks* pAllocator); + void gen7_DestroyRenderPass(VkDevice device, VkRenderPass renderPass, const VkAllocationCallbacks* pAllocator); + void gen75_DestroyRenderPass(VkDevice device, VkRenderPass renderPass, const VkAllocationCallbacks* pAllocator); + void gen8_DestroyRenderPass(VkDevice device, VkRenderPass renderPass, const VkAllocationCallbacks* pAllocator); + void gen9_DestroyRenderPass(VkDevice device, VkRenderPass renderPass, const VkAllocationCallbacks* pAllocator); + void gen10_DestroyRenderPass(VkDevice device, VkRenderPass renderPass, const VkAllocationCallbacks* pAllocator); + void gen11_DestroyRenderPass(VkDevice device, VkRenderPass renderPass, const VkAllocationCallbacks* pAllocator); + void anv_GetRenderAreaGranularity(VkDevice device, VkRenderPass renderPass, VkExtent2D* pGranularity); + void gen7_GetRenderAreaGranularity(VkDevice device, VkRenderPass renderPass, VkExtent2D* pGranularity); + void gen75_GetRenderAreaGranularity(VkDevice device, VkRenderPass renderPass, VkExtent2D* pGranularity); + void gen8_GetRenderAreaGranularity(VkDevice device, VkRenderPass renderPass, VkExtent2D* pGranularity); + void gen9_GetRenderAreaGranularity(VkDevice device, VkRenderPass renderPass, VkExtent2D* pGranularity); + void gen10_GetRenderAreaGranularity(VkDevice device, VkRenderPass renderPass, VkExtent2D* pGranularity); + void gen11_GetRenderAreaGranularity(VkDevice device, VkRenderPass renderPass, VkExtent2D* pGranularity); + VkResult anv_CreateCommandPool(VkDevice device, const VkCommandPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkCommandPool* pCommandPool); + VkResult gen7_CreateCommandPool(VkDevice device, const VkCommandPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkCommandPool* pCommandPool); + VkResult gen75_CreateCommandPool(VkDevice device, const VkCommandPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkCommandPool* pCommandPool); + VkResult gen8_CreateCommandPool(VkDevice device, const VkCommandPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkCommandPool* pCommandPool); + VkResult gen9_CreateCommandPool(VkDevice device, const VkCommandPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkCommandPool* pCommandPool); + VkResult gen10_CreateCommandPool(VkDevice device, const VkCommandPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkCommandPool* pCommandPool); + VkResult gen11_CreateCommandPool(VkDevice device, const VkCommandPoolCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkCommandPool* pCommandPool); + void anv_DestroyCommandPool(VkDevice device, VkCommandPool commandPool, const VkAllocationCallbacks* pAllocator); + void gen7_DestroyCommandPool(VkDevice device, VkCommandPool commandPool, const VkAllocationCallbacks* pAllocator); + void gen75_DestroyCommandPool(VkDevice device, VkCommandPool commandPool, const VkAllocationCallbacks* pAllocator); + void gen8_DestroyCommandPool(VkDevice device, VkCommandPool commandPool, const VkAllocationCallbacks* pAllocator); + void gen9_DestroyCommandPool(VkDevice device, VkCommandPool commandPool, const VkAllocationCallbacks* pAllocator); + void gen10_DestroyCommandPool(VkDevice device, VkCommandPool commandPool, const VkAllocationCallbacks* pAllocator); + void gen11_DestroyCommandPool(VkDevice device, VkCommandPool commandPool, const VkAllocationCallbacks* pAllocator); + VkResult anv_ResetCommandPool(VkDevice device, VkCommandPool commandPool, VkCommandPoolResetFlags flags); + VkResult gen7_ResetCommandPool(VkDevice device, VkCommandPool commandPool, VkCommandPoolResetFlags flags); + VkResult gen75_ResetCommandPool(VkDevice device, VkCommandPool commandPool, VkCommandPoolResetFlags flags); + VkResult gen8_ResetCommandPool(VkDevice device, VkCommandPool commandPool, VkCommandPoolResetFlags flags); + VkResult gen9_ResetCommandPool(VkDevice device, VkCommandPool commandPool, VkCommandPoolResetFlags flags); + VkResult gen10_ResetCommandPool(VkDevice device, VkCommandPool commandPool, VkCommandPoolResetFlags flags); + VkResult gen11_ResetCommandPool(VkDevice device, VkCommandPool commandPool, VkCommandPoolResetFlags flags); + VkResult anv_AllocateCommandBuffers(VkDevice device, const VkCommandBufferAllocateInfo* pAllocateInfo, VkCommandBuffer* pCommandBuffers); + VkResult gen7_AllocateCommandBuffers(VkDevice device, const VkCommandBufferAllocateInfo* pAllocateInfo, VkCommandBuffer* pCommandBuffers); + VkResult gen75_AllocateCommandBuffers(VkDevice device, const VkCommandBufferAllocateInfo* pAllocateInfo, VkCommandBuffer* pCommandBuffers); + VkResult gen8_AllocateCommandBuffers(VkDevice device, const VkCommandBufferAllocateInfo* pAllocateInfo, VkCommandBuffer* pCommandBuffers); + VkResult gen9_AllocateCommandBuffers(VkDevice device, const VkCommandBufferAllocateInfo* pAllocateInfo, VkCommandBuffer* pCommandBuffers); + VkResult gen10_AllocateCommandBuffers(VkDevice device, const VkCommandBufferAllocateInfo* pAllocateInfo, VkCommandBuffer* pCommandBuffers); + VkResult gen11_AllocateCommandBuffers(VkDevice device, const VkCommandBufferAllocateInfo* pAllocateInfo, VkCommandBuffer* pCommandBuffers); + void anv_FreeCommandBuffers(VkDevice device, VkCommandPool commandPool, uint32_t commandBufferCount, const VkCommandBuffer* pCommandBuffers); + void gen7_FreeCommandBuffers(VkDevice device, VkCommandPool commandPool, uint32_t commandBufferCount, const VkCommandBuffer* pCommandBuffers); + void gen75_FreeCommandBuffers(VkDevice device, VkCommandPool commandPool, uint32_t commandBufferCount, const VkCommandBuffer* pCommandBuffers); + void gen8_FreeCommandBuffers(VkDevice device, VkCommandPool commandPool, uint32_t commandBufferCount, const VkCommandBuffer* pCommandBuffers); + void gen9_FreeCommandBuffers(VkDevice device, VkCommandPool commandPool, uint32_t commandBufferCount, const VkCommandBuffer* pCommandBuffers); + void gen10_FreeCommandBuffers(VkDevice device, VkCommandPool commandPool, uint32_t commandBufferCount, const VkCommandBuffer* pCommandBuffers); + void gen11_FreeCommandBuffers(VkDevice device, VkCommandPool commandPool, uint32_t commandBufferCount, const VkCommandBuffer* pCommandBuffers); + VkResult anv_BeginCommandBuffer(VkCommandBuffer commandBuffer, const VkCommandBufferBeginInfo* pBeginInfo); + VkResult gen7_BeginCommandBuffer(VkCommandBuffer commandBuffer, const VkCommandBufferBeginInfo* pBeginInfo); + VkResult gen75_BeginCommandBuffer(VkCommandBuffer commandBuffer, const VkCommandBufferBeginInfo* pBeginInfo); + VkResult gen8_BeginCommandBuffer(VkCommandBuffer commandBuffer, const VkCommandBufferBeginInfo* pBeginInfo); + VkResult gen9_BeginCommandBuffer(VkCommandBuffer commandBuffer, const VkCommandBufferBeginInfo* pBeginInfo); + VkResult gen10_BeginCommandBuffer(VkCommandBuffer commandBuffer, const VkCommandBufferBeginInfo* pBeginInfo); + VkResult gen11_BeginCommandBuffer(VkCommandBuffer commandBuffer, const VkCommandBufferBeginInfo* pBeginInfo); + VkResult anv_EndCommandBuffer(VkCommandBuffer commandBuffer); + VkResult gen7_EndCommandBuffer(VkCommandBuffer commandBuffer); + VkResult gen75_EndCommandBuffer(VkCommandBuffer commandBuffer); + VkResult gen8_EndCommandBuffer(VkCommandBuffer commandBuffer); + VkResult gen9_EndCommandBuffer(VkCommandBuffer commandBuffer); + VkResult gen10_EndCommandBuffer(VkCommandBuffer commandBuffer); + VkResult gen11_EndCommandBuffer(VkCommandBuffer commandBuffer); + VkResult anv_ResetCommandBuffer(VkCommandBuffer commandBuffer, VkCommandBufferResetFlags flags); + VkResult gen7_ResetCommandBuffer(VkCommandBuffer commandBuffer, VkCommandBufferResetFlags flags); + VkResult gen75_ResetCommandBuffer(VkCommandBuffer commandBuffer, VkCommandBufferResetFlags flags); + VkResult gen8_ResetCommandBuffer(VkCommandBuffer commandBuffer, VkCommandBufferResetFlags flags); + VkResult gen9_ResetCommandBuffer(VkCommandBuffer commandBuffer, VkCommandBufferResetFlags flags); + VkResult gen10_ResetCommandBuffer(VkCommandBuffer commandBuffer, VkCommandBufferResetFlags flags); + VkResult gen11_ResetCommandBuffer(VkCommandBuffer commandBuffer, VkCommandBufferResetFlags flags); + void anv_CmdBindPipeline(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipeline pipeline); + void gen7_CmdBindPipeline(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipeline pipeline); + void gen75_CmdBindPipeline(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipeline pipeline); + void gen8_CmdBindPipeline(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipeline pipeline); + void gen9_CmdBindPipeline(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipeline pipeline); + void gen10_CmdBindPipeline(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipeline pipeline); + void gen11_CmdBindPipeline(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipeline pipeline); + void anv_CmdSetViewport(VkCommandBuffer commandBuffer, uint32_t firstViewport, uint32_t viewportCount, const VkViewport* pViewports); + void gen7_CmdSetViewport(VkCommandBuffer commandBuffer, uint32_t firstViewport, uint32_t viewportCount, const VkViewport* pViewports); + void gen75_CmdSetViewport(VkCommandBuffer commandBuffer, uint32_t firstViewport, uint32_t viewportCount, const VkViewport* pViewports); + void gen8_CmdSetViewport(VkCommandBuffer commandBuffer, uint32_t firstViewport, uint32_t viewportCount, const VkViewport* pViewports); + void gen9_CmdSetViewport(VkCommandBuffer commandBuffer, uint32_t firstViewport, uint32_t viewportCount, const VkViewport* pViewports); + void gen10_CmdSetViewport(VkCommandBuffer commandBuffer, uint32_t firstViewport, uint32_t viewportCount, const VkViewport* pViewports); + void gen11_CmdSetViewport(VkCommandBuffer commandBuffer, uint32_t firstViewport, uint32_t viewportCount, const VkViewport* pViewports); + void anv_CmdSetScissor(VkCommandBuffer commandBuffer, uint32_t firstScissor, uint32_t scissorCount, const VkRect2D* pScissors); + void gen7_CmdSetScissor(VkCommandBuffer commandBuffer, uint32_t firstScissor, uint32_t scissorCount, const VkRect2D* pScissors); + void gen75_CmdSetScissor(VkCommandBuffer commandBuffer, uint32_t firstScissor, uint32_t scissorCount, const VkRect2D* pScissors); + void gen8_CmdSetScissor(VkCommandBuffer commandBuffer, uint32_t firstScissor, uint32_t scissorCount, const VkRect2D* pScissors); + void gen9_CmdSetScissor(VkCommandBuffer commandBuffer, uint32_t firstScissor, uint32_t scissorCount, const VkRect2D* pScissors); + void gen10_CmdSetScissor(VkCommandBuffer commandBuffer, uint32_t firstScissor, uint32_t scissorCount, const VkRect2D* pScissors); + void gen11_CmdSetScissor(VkCommandBuffer commandBuffer, uint32_t firstScissor, uint32_t scissorCount, const VkRect2D* pScissors); + void anv_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth); + void gen7_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth); + void gen75_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth); + void gen8_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth); + void gen9_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth); + void gen10_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth); + void gen11_CmdSetLineWidth(VkCommandBuffer commandBuffer, float lineWidth); + void anv_CmdSetDepthBias(VkCommandBuffer commandBuffer, float depthBiasConstantFactor, float depthBiasClamp, float depthBiasSlopeFactor); + void gen7_CmdSetDepthBias(VkCommandBuffer commandBuffer, float depthBiasConstantFactor, float depthBiasClamp, float depthBiasSlopeFactor); + void gen75_CmdSetDepthBias(VkCommandBuffer commandBuffer, float depthBiasConstantFactor, float depthBiasClamp, float depthBiasSlopeFactor); + void gen8_CmdSetDepthBias(VkCommandBuffer commandBuffer, float depthBiasConstantFactor, float depthBiasClamp, float depthBiasSlopeFactor); + void gen9_CmdSetDepthBias(VkCommandBuffer commandBuffer, float depthBiasConstantFactor, float depthBiasClamp, float depthBiasSlopeFactor); + void gen10_CmdSetDepthBias(VkCommandBuffer commandBuffer, float depthBiasConstantFactor, float depthBiasClamp, float depthBiasSlopeFactor); + void gen11_CmdSetDepthBias(VkCommandBuffer commandBuffer, float depthBiasConstantFactor, float depthBiasClamp, float depthBiasSlopeFactor); + void anv_CmdSetBlendConstants(VkCommandBuffer commandBuffer, const float blendConstants[4]); + void gen7_CmdSetBlendConstants(VkCommandBuffer commandBuffer, const float blendConstants[4]); + void gen75_CmdSetBlendConstants(VkCommandBuffer commandBuffer, const float blendConstants[4]); + void gen8_CmdSetBlendConstants(VkCommandBuffer commandBuffer, const float blendConstants[4]); + void gen9_CmdSetBlendConstants(VkCommandBuffer commandBuffer, const float blendConstants[4]); + void gen10_CmdSetBlendConstants(VkCommandBuffer commandBuffer, const float blendConstants[4]); + void gen11_CmdSetBlendConstants(VkCommandBuffer commandBuffer, const float blendConstants[4]); + void anv_CmdSetDepthBounds(VkCommandBuffer commandBuffer, float minDepthBounds, float maxDepthBounds); + void gen7_CmdSetDepthBounds(VkCommandBuffer commandBuffer, float minDepthBounds, float maxDepthBounds); + void gen75_CmdSetDepthBounds(VkCommandBuffer commandBuffer, float minDepthBounds, float maxDepthBounds); + void gen8_CmdSetDepthBounds(VkCommandBuffer commandBuffer, float minDepthBounds, float maxDepthBounds); + void gen9_CmdSetDepthBounds(VkCommandBuffer commandBuffer, float minDepthBounds, float maxDepthBounds); + void gen10_CmdSetDepthBounds(VkCommandBuffer commandBuffer, float minDepthBounds, float maxDepthBounds); + void gen11_CmdSetDepthBounds(VkCommandBuffer commandBuffer, float minDepthBounds, float maxDepthBounds); + void anv_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t compareMask); + void gen7_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t compareMask); + void gen75_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t compareMask); + void gen8_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t compareMask); + void gen9_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t compareMask); + void gen10_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t compareMask); + void gen11_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t compareMask); + void anv_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t writeMask); + void gen7_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t writeMask); + void gen75_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t writeMask); + void gen8_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t writeMask); + void gen9_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t writeMask); + void gen10_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t writeMask); + void gen11_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t writeMask); + void anv_CmdSetStencilReference(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t reference); + void gen7_CmdSetStencilReference(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t reference); + void gen75_CmdSetStencilReference(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t reference); + void gen8_CmdSetStencilReference(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t reference); + void gen9_CmdSetStencilReference(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t reference); + void gen10_CmdSetStencilReference(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t reference); + void gen11_CmdSetStencilReference(VkCommandBuffer commandBuffer, VkStencilFaceFlags faceMask, uint32_t reference); + void anv_CmdBindDescriptorSets(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipelineLayout layout, uint32_t firstSet, uint32_t descriptorSetCount, const VkDescriptorSet* pDescriptorSets, uint32_t dynamicOffsetCount, const uint32_t* pDynamicOffsets); + void gen7_CmdBindDescriptorSets(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipelineLayout layout, uint32_t firstSet, uint32_t descriptorSetCount, const VkDescriptorSet* pDescriptorSets, uint32_t dynamicOffsetCount, const uint32_t* pDynamicOffsets); + void gen75_CmdBindDescriptorSets(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipelineLayout layout, uint32_t firstSet, uint32_t descriptorSetCount, const VkDescriptorSet* pDescriptorSets, uint32_t dynamicOffsetCount, const uint32_t* pDynamicOffsets); + void gen8_CmdBindDescriptorSets(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipelineLayout layout, uint32_t firstSet, uint32_t descriptorSetCount, const VkDescriptorSet* pDescriptorSets, uint32_t dynamicOffsetCount, const uint32_t* pDynamicOffsets); + void gen9_CmdBindDescriptorSets(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipelineLayout layout, uint32_t firstSet, uint32_t descriptorSetCount, const VkDescriptorSet* pDescriptorSets, uint32_t dynamicOffsetCount, const uint32_t* pDynamicOffsets); + void gen10_CmdBindDescriptorSets(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipelineLayout layout, uint32_t firstSet, uint32_t descriptorSetCount, const VkDescriptorSet* pDescriptorSets, uint32_t dynamicOffsetCount, const uint32_t* pDynamicOffsets); + void gen11_CmdBindDescriptorSets(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipelineLayout layout, uint32_t firstSet, uint32_t descriptorSetCount, const VkDescriptorSet* pDescriptorSets, uint32_t dynamicOffsetCount, const uint32_t* pDynamicOffsets); + void anv_CmdBindIndexBuffer(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkIndexType indexType); + void gen7_CmdBindIndexBuffer(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkIndexType indexType); + void gen75_CmdBindIndexBuffer(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkIndexType indexType); + void gen8_CmdBindIndexBuffer(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkIndexType indexType); + void gen9_CmdBindIndexBuffer(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkIndexType indexType); + void gen10_CmdBindIndexBuffer(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkIndexType indexType); + void gen11_CmdBindIndexBuffer(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkIndexType indexType); + void anv_CmdBindVertexBuffers(VkCommandBuffer commandBuffer, uint32_t firstBinding, uint32_t bindingCount, const VkBuffer* pBuffers, const VkDeviceSize* pOffsets); + void gen7_CmdBindVertexBuffers(VkCommandBuffer commandBuffer, uint32_t firstBinding, uint32_t bindingCount, const VkBuffer* pBuffers, const VkDeviceSize* pOffsets); + void gen75_CmdBindVertexBuffers(VkCommandBuffer commandBuffer, uint32_t firstBinding, uint32_t bindingCount, const VkBuffer* pBuffers, const VkDeviceSize* pOffsets); + void gen8_CmdBindVertexBuffers(VkCommandBuffer commandBuffer, uint32_t firstBinding, uint32_t bindingCount, const VkBuffer* pBuffers, const VkDeviceSize* pOffsets); + void gen9_CmdBindVertexBuffers(VkCommandBuffer commandBuffer, uint32_t firstBinding, uint32_t bindingCount, const VkBuffer* pBuffers, const VkDeviceSize* pOffsets); + void gen10_CmdBindVertexBuffers(VkCommandBuffer commandBuffer, uint32_t firstBinding, uint32_t bindingCount, const VkBuffer* pBuffers, const VkDeviceSize* pOffsets); + void gen11_CmdBindVertexBuffers(VkCommandBuffer commandBuffer, uint32_t firstBinding, uint32_t bindingCount, const VkBuffer* pBuffers, const VkDeviceSize* pOffsets); + void anv_CmdDraw(VkCommandBuffer commandBuffer, uint32_t vertexCount, uint32_t instanceCount, uint32_t firstVertex, uint32_t firstInstance); + void gen7_CmdDraw(VkCommandBuffer commandBuffer, uint32_t vertexCount, uint32_t instanceCount, uint32_t firstVertex, uint32_t firstInstance); + void gen75_CmdDraw(VkCommandBuffer commandBuffer, uint32_t vertexCount, uint32_t instanceCount, uint32_t firstVertex, uint32_t firstInstance); + void gen8_CmdDraw(VkCommandBuffer commandBuffer, uint32_t vertexCount, uint32_t instanceCount, uint32_t firstVertex, uint32_t firstInstance); + void gen9_CmdDraw(VkCommandBuffer commandBuffer, uint32_t vertexCount, uint32_t instanceCount, uint32_t firstVertex, uint32_t firstInstance); + void gen10_CmdDraw(VkCommandBuffer commandBuffer, uint32_t vertexCount, uint32_t instanceCount, uint32_t firstVertex, uint32_t firstInstance); + void gen11_CmdDraw(VkCommandBuffer commandBuffer, uint32_t vertexCount, uint32_t instanceCount, uint32_t firstVertex, uint32_t firstInstance); + void anv_CmdDrawIndexed(VkCommandBuffer commandBuffer, uint32_t indexCount, uint32_t instanceCount, uint32_t firstIndex, int32_t vertexOffset, uint32_t firstInstance); + void gen7_CmdDrawIndexed(VkCommandBuffer commandBuffer, uint32_t indexCount, uint32_t instanceCount, uint32_t firstIndex, int32_t vertexOffset, uint32_t firstInstance); + void gen75_CmdDrawIndexed(VkCommandBuffer commandBuffer, uint32_t indexCount, uint32_t instanceCount, uint32_t firstIndex, int32_t vertexOffset, uint32_t firstInstance); + void gen8_CmdDrawIndexed(VkCommandBuffer commandBuffer, uint32_t indexCount, uint32_t instanceCount, uint32_t firstIndex, int32_t vertexOffset, uint32_t firstInstance); + void gen9_CmdDrawIndexed(VkCommandBuffer commandBuffer, uint32_t indexCount, uint32_t instanceCount, uint32_t firstIndex, int32_t vertexOffset, uint32_t firstInstance); + void gen10_CmdDrawIndexed(VkCommandBuffer commandBuffer, uint32_t indexCount, uint32_t instanceCount, uint32_t firstIndex, int32_t vertexOffset, uint32_t firstInstance); + void gen11_CmdDrawIndexed(VkCommandBuffer commandBuffer, uint32_t indexCount, uint32_t instanceCount, uint32_t firstIndex, int32_t vertexOffset, uint32_t firstInstance); + void anv_CmdDrawIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, uint32_t drawCount, uint32_t stride); + void gen7_CmdDrawIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, uint32_t drawCount, uint32_t stride); + void gen75_CmdDrawIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, uint32_t drawCount, uint32_t stride); + void gen8_CmdDrawIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, uint32_t drawCount, uint32_t stride); + void gen9_CmdDrawIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, uint32_t drawCount, uint32_t stride); + void gen10_CmdDrawIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, uint32_t drawCount, uint32_t stride); + void gen11_CmdDrawIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, uint32_t drawCount, uint32_t stride); + void anv_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, uint32_t drawCount, uint32_t stride); + void gen7_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, uint32_t drawCount, uint32_t stride); + void gen75_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, uint32_t drawCount, uint32_t stride); + void gen8_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, uint32_t drawCount, uint32_t stride); + void gen9_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, uint32_t drawCount, uint32_t stride); + void gen10_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, uint32_t drawCount, uint32_t stride); + void gen11_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, uint32_t drawCount, uint32_t stride); + void anv_CmdDispatch(VkCommandBuffer commandBuffer, uint32_t groupCountX, uint32_t groupCountY, uint32_t groupCountZ); + void gen7_CmdDispatch(VkCommandBuffer commandBuffer, uint32_t groupCountX, uint32_t groupCountY, uint32_t groupCountZ); + void gen75_CmdDispatch(VkCommandBuffer commandBuffer, uint32_t groupCountX, uint32_t groupCountY, uint32_t groupCountZ); + void gen8_CmdDispatch(VkCommandBuffer commandBuffer, uint32_t groupCountX, uint32_t groupCountY, uint32_t groupCountZ); + void gen9_CmdDispatch(VkCommandBuffer commandBuffer, uint32_t groupCountX, uint32_t groupCountY, uint32_t groupCountZ); + void gen10_CmdDispatch(VkCommandBuffer commandBuffer, uint32_t groupCountX, uint32_t groupCountY, uint32_t groupCountZ); + void gen11_CmdDispatch(VkCommandBuffer commandBuffer, uint32_t groupCountX, uint32_t groupCountY, uint32_t groupCountZ); + void anv_CmdDispatchIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset); + void gen7_CmdDispatchIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset); + void gen75_CmdDispatchIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset); + void gen8_CmdDispatchIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset); + void gen9_CmdDispatchIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset); + void gen10_CmdDispatchIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset); + void gen11_CmdDispatchIndirect(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset); + void anv_CmdCopyBuffer(VkCommandBuffer commandBuffer, VkBuffer srcBuffer, VkBuffer dstBuffer, uint32_t regionCount, const VkBufferCopy* pRegions); + void gen7_CmdCopyBuffer(VkCommandBuffer commandBuffer, VkBuffer srcBuffer, VkBuffer dstBuffer, uint32_t regionCount, const VkBufferCopy* pRegions); + void gen75_CmdCopyBuffer(VkCommandBuffer commandBuffer, VkBuffer srcBuffer, VkBuffer dstBuffer, uint32_t regionCount, const VkBufferCopy* pRegions); + void gen8_CmdCopyBuffer(VkCommandBuffer commandBuffer, VkBuffer srcBuffer, VkBuffer dstBuffer, uint32_t regionCount, const VkBufferCopy* pRegions); + void gen9_CmdCopyBuffer(VkCommandBuffer commandBuffer, VkBuffer srcBuffer, VkBuffer dstBuffer, uint32_t regionCount, const VkBufferCopy* pRegions); + void gen10_CmdCopyBuffer(VkCommandBuffer commandBuffer, VkBuffer srcBuffer, VkBuffer dstBuffer, uint32_t regionCount, const VkBufferCopy* pRegions); + void gen11_CmdCopyBuffer(VkCommandBuffer commandBuffer, VkBuffer srcBuffer, VkBuffer dstBuffer, uint32_t regionCount, const VkBufferCopy* pRegions); + void anv_CmdCopyImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageCopy* pRegions); + void gen7_CmdCopyImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageCopy* pRegions); + void gen75_CmdCopyImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageCopy* pRegions); + void gen8_CmdCopyImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageCopy* pRegions); + void gen9_CmdCopyImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageCopy* pRegions); + void gen10_CmdCopyImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageCopy* pRegions); + void gen11_CmdCopyImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageCopy* pRegions); + void anv_CmdBlitImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageBlit* pRegions, VkFilter filter); + void gen7_CmdBlitImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageBlit* pRegions, VkFilter filter); + void gen75_CmdBlitImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageBlit* pRegions, VkFilter filter); + void gen8_CmdBlitImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageBlit* pRegions, VkFilter filter); + void gen9_CmdBlitImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageBlit* pRegions, VkFilter filter); + void gen10_CmdBlitImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageBlit* pRegions, VkFilter filter); + void gen11_CmdBlitImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageBlit* pRegions, VkFilter filter); + void anv_CmdCopyBufferToImage(VkCommandBuffer commandBuffer, VkBuffer srcBuffer, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkBufferImageCopy* pRegions); + void gen7_CmdCopyBufferToImage(VkCommandBuffer commandBuffer, VkBuffer srcBuffer, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkBufferImageCopy* pRegions); + void gen75_CmdCopyBufferToImage(VkCommandBuffer commandBuffer, VkBuffer srcBuffer, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkBufferImageCopy* pRegions); + void gen8_CmdCopyBufferToImage(VkCommandBuffer commandBuffer, VkBuffer srcBuffer, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkBufferImageCopy* pRegions); + void gen9_CmdCopyBufferToImage(VkCommandBuffer commandBuffer, VkBuffer srcBuffer, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkBufferImageCopy* pRegions); + void gen10_CmdCopyBufferToImage(VkCommandBuffer commandBuffer, VkBuffer srcBuffer, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkBufferImageCopy* pRegions); + void gen11_CmdCopyBufferToImage(VkCommandBuffer commandBuffer, VkBuffer srcBuffer, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkBufferImageCopy* pRegions); + void anv_CmdCopyImageToBuffer(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkBuffer dstBuffer, uint32_t regionCount, const VkBufferImageCopy* pRegions); + void gen7_CmdCopyImageToBuffer(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkBuffer dstBuffer, uint32_t regionCount, const VkBufferImageCopy* pRegions); + void gen75_CmdCopyImageToBuffer(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkBuffer dstBuffer, uint32_t regionCount, const VkBufferImageCopy* pRegions); + void gen8_CmdCopyImageToBuffer(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkBuffer dstBuffer, uint32_t regionCount, const VkBufferImageCopy* pRegions); + void gen9_CmdCopyImageToBuffer(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkBuffer dstBuffer, uint32_t regionCount, const VkBufferImageCopy* pRegions); + void gen10_CmdCopyImageToBuffer(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkBuffer dstBuffer, uint32_t regionCount, const VkBufferImageCopy* pRegions); + void gen11_CmdCopyImageToBuffer(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkBuffer dstBuffer, uint32_t regionCount, const VkBufferImageCopy* pRegions); + void anv_CmdUpdateBuffer(VkCommandBuffer commandBuffer, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize dataSize, const void* pData); + void gen7_CmdUpdateBuffer(VkCommandBuffer commandBuffer, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize dataSize, const void* pData); + void gen75_CmdUpdateBuffer(VkCommandBuffer commandBuffer, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize dataSize, const void* pData); + void gen8_CmdUpdateBuffer(VkCommandBuffer commandBuffer, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize dataSize, const void* pData); + void gen9_CmdUpdateBuffer(VkCommandBuffer commandBuffer, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize dataSize, const void* pData); + void gen10_CmdUpdateBuffer(VkCommandBuffer commandBuffer, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize dataSize, const void* pData); + void gen11_CmdUpdateBuffer(VkCommandBuffer commandBuffer, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize dataSize, const void* pData); + void anv_CmdFillBuffer(VkCommandBuffer commandBuffer, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize size, uint32_t data); + void gen7_CmdFillBuffer(VkCommandBuffer commandBuffer, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize size, uint32_t data); + void gen75_CmdFillBuffer(VkCommandBuffer commandBuffer, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize size, uint32_t data); + void gen8_CmdFillBuffer(VkCommandBuffer commandBuffer, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize size, uint32_t data); + void gen9_CmdFillBuffer(VkCommandBuffer commandBuffer, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize size, uint32_t data); + void gen10_CmdFillBuffer(VkCommandBuffer commandBuffer, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize size, uint32_t data); + void gen11_CmdFillBuffer(VkCommandBuffer commandBuffer, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize size, uint32_t data); + void anv_CmdClearColorImage(VkCommandBuffer commandBuffer, VkImage image, VkImageLayout imageLayout, const VkClearColorValue* pColor, uint32_t rangeCount, const VkImageSubresourceRange* pRanges); + void gen7_CmdClearColorImage(VkCommandBuffer commandBuffer, VkImage image, VkImageLayout imageLayout, const VkClearColorValue* pColor, uint32_t rangeCount, const VkImageSubresourceRange* pRanges); + void gen75_CmdClearColorImage(VkCommandBuffer commandBuffer, VkImage image, VkImageLayout imageLayout, const VkClearColorValue* pColor, uint32_t rangeCount, const VkImageSubresourceRange* pRanges); + void gen8_CmdClearColorImage(VkCommandBuffer commandBuffer, VkImage image, VkImageLayout imageLayout, const VkClearColorValue* pColor, uint32_t rangeCount, const VkImageSubresourceRange* pRanges); + void gen9_CmdClearColorImage(VkCommandBuffer commandBuffer, VkImage image, VkImageLayout imageLayout, const VkClearColorValue* pColor, uint32_t rangeCount, const VkImageSubresourceRange* pRanges); + void gen10_CmdClearColorImage(VkCommandBuffer commandBuffer, VkImage image, VkImageLayout imageLayout, const VkClearColorValue* pColor, uint32_t rangeCount, const VkImageSubresourceRange* pRanges); + void gen11_CmdClearColorImage(VkCommandBuffer commandBuffer, VkImage image, VkImageLayout imageLayout, const VkClearColorValue* pColor, uint32_t rangeCount, const VkImageSubresourceRange* pRanges); + void anv_CmdClearDepthStencilImage(VkCommandBuffer commandBuffer, VkImage image, VkImageLayout imageLayout, const VkClearDepthStencilValue* pDepthStencil, uint32_t rangeCount, const VkImageSubresourceRange* pRanges); + void gen7_CmdClearDepthStencilImage(VkCommandBuffer commandBuffer, VkImage image, VkImageLayout imageLayout, const VkClearDepthStencilValue* pDepthStencil, uint32_t rangeCount, const VkImageSubresourceRange* pRanges); + void gen75_CmdClearDepthStencilImage(VkCommandBuffer commandBuffer, VkImage image, VkImageLayout imageLayout, const VkClearDepthStencilValue* pDepthStencil, uint32_t rangeCount, const VkImageSubresourceRange* pRanges); + void gen8_CmdClearDepthStencilImage(VkCommandBuffer commandBuffer, VkImage image, VkImageLayout imageLayout, const VkClearDepthStencilValue* pDepthStencil, uint32_t rangeCount, const VkImageSubresourceRange* pRanges); + void gen9_CmdClearDepthStencilImage(VkCommandBuffer commandBuffer, VkImage image, VkImageLayout imageLayout, const VkClearDepthStencilValue* pDepthStencil, uint32_t rangeCount, const VkImageSubresourceRange* pRanges); + void gen10_CmdClearDepthStencilImage(VkCommandBuffer commandBuffer, VkImage image, VkImageLayout imageLayout, const VkClearDepthStencilValue* pDepthStencil, uint32_t rangeCount, const VkImageSubresourceRange* pRanges); + void gen11_CmdClearDepthStencilImage(VkCommandBuffer commandBuffer, VkImage image, VkImageLayout imageLayout, const VkClearDepthStencilValue* pDepthStencil, uint32_t rangeCount, const VkImageSubresourceRange* pRanges); + void anv_CmdClearAttachments(VkCommandBuffer commandBuffer, uint32_t attachmentCount, const VkClearAttachment* pAttachments, uint32_t rectCount, const VkClearRect* pRects); + void gen7_CmdClearAttachments(VkCommandBuffer commandBuffer, uint32_t attachmentCount, const VkClearAttachment* pAttachments, uint32_t rectCount, const VkClearRect* pRects); + void gen75_CmdClearAttachments(VkCommandBuffer commandBuffer, uint32_t attachmentCount, const VkClearAttachment* pAttachments, uint32_t rectCount, const VkClearRect* pRects); + void gen8_CmdClearAttachments(VkCommandBuffer commandBuffer, uint32_t attachmentCount, const VkClearAttachment* pAttachments, uint32_t rectCount, const VkClearRect* pRects); + void gen9_CmdClearAttachments(VkCommandBuffer commandBuffer, uint32_t attachmentCount, const VkClearAttachment* pAttachments, uint32_t rectCount, const VkClearRect* pRects); + void gen10_CmdClearAttachments(VkCommandBuffer commandBuffer, uint32_t attachmentCount, const VkClearAttachment* pAttachments, uint32_t rectCount, const VkClearRect* pRects); + void gen11_CmdClearAttachments(VkCommandBuffer commandBuffer, uint32_t attachmentCount, const VkClearAttachment* pAttachments, uint32_t rectCount, const VkClearRect* pRects); + void anv_CmdResolveImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageResolve* pRegions); + void gen7_CmdResolveImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageResolve* pRegions); + void gen75_CmdResolveImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageResolve* pRegions); + void gen8_CmdResolveImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageResolve* pRegions); + void gen9_CmdResolveImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageResolve* pRegions); + void gen10_CmdResolveImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageResolve* pRegions); + void gen11_CmdResolveImage(VkCommandBuffer commandBuffer, VkImage srcImage, VkImageLayout srcImageLayout, VkImage dstImage, VkImageLayout dstImageLayout, uint32_t regionCount, const VkImageResolve* pRegions); + void anv_CmdSetEvent(VkCommandBuffer commandBuffer, VkEvent event, VkPipelineStageFlags stageMask); + void gen7_CmdSetEvent(VkCommandBuffer commandBuffer, VkEvent event, VkPipelineStageFlags stageMask); + void gen75_CmdSetEvent(VkCommandBuffer commandBuffer, VkEvent event, VkPipelineStageFlags stageMask); + void gen8_CmdSetEvent(VkCommandBuffer commandBuffer, VkEvent event, VkPipelineStageFlags stageMask); + void gen9_CmdSetEvent(VkCommandBuffer commandBuffer, VkEvent event, VkPipelineStageFlags stageMask); + void gen10_CmdSetEvent(VkCommandBuffer commandBuffer, VkEvent event, VkPipelineStageFlags stageMask); + void gen11_CmdSetEvent(VkCommandBuffer commandBuffer, VkEvent event, VkPipelineStageFlags stageMask); + void anv_CmdResetEvent(VkCommandBuffer commandBuffer, VkEvent event, VkPipelineStageFlags stageMask); + void gen7_CmdResetEvent(VkCommandBuffer commandBuffer, VkEvent event, VkPipelineStageFlags stageMask); + void gen75_CmdResetEvent(VkCommandBuffer commandBuffer, VkEvent event, VkPipelineStageFlags stageMask); + void gen8_CmdResetEvent(VkCommandBuffer commandBuffer, VkEvent event, VkPipelineStageFlags stageMask); + void gen9_CmdResetEvent(VkCommandBuffer commandBuffer, VkEvent event, VkPipelineStageFlags stageMask); + void gen10_CmdResetEvent(VkCommandBuffer commandBuffer, VkEvent event, VkPipelineStageFlags stageMask); + void gen11_CmdResetEvent(VkCommandBuffer commandBuffer, VkEvent event, VkPipelineStageFlags stageMask); + void anv_CmdWaitEvents(VkCommandBuffer commandBuffer, uint32_t eventCount, const VkEvent* pEvents, VkPipelineStageFlags srcStageMask, VkPipelineStageFlags dstStageMask, uint32_t memoryBarrierCount, const VkMemoryBarrier* pMemoryBarriers, uint32_t bufferMemoryBarrierCount, const VkBufferMemoryBarrier* pBufferMemoryBarriers, uint32_t imageMemoryBarrierCount, const VkImageMemoryBarrier* pImageMemoryBarriers); + void gen7_CmdWaitEvents(VkCommandBuffer commandBuffer, uint32_t eventCount, const VkEvent* pEvents, VkPipelineStageFlags srcStageMask, VkPipelineStageFlags dstStageMask, uint32_t memoryBarrierCount, const VkMemoryBarrier* pMemoryBarriers, uint32_t bufferMemoryBarrierCount, const VkBufferMemoryBarrier* pBufferMemoryBarriers, uint32_t imageMemoryBarrierCount, const VkImageMemoryBarrier* pImageMemoryBarriers); + void gen75_CmdWaitEvents(VkCommandBuffer commandBuffer, uint32_t eventCount, const VkEvent* pEvents, VkPipelineStageFlags srcStageMask, VkPipelineStageFlags dstStageMask, uint32_t memoryBarrierCount, const VkMemoryBarrier* pMemoryBarriers, uint32_t bufferMemoryBarrierCount, const VkBufferMemoryBarrier* pBufferMemoryBarriers, uint32_t imageMemoryBarrierCount, const VkImageMemoryBarrier* pImageMemoryBarriers); + void gen8_CmdWaitEvents(VkCommandBuffer commandBuffer, uint32_t eventCount, const VkEvent* pEvents, VkPipelineStageFlags srcStageMask, VkPipelineStageFlags dstStageMask, uint32_t memoryBarrierCount, const VkMemoryBarrier* pMemoryBarriers, uint32_t bufferMemoryBarrierCount, const VkBufferMemoryBarrier* pBufferMemoryBarriers, uint32_t imageMemoryBarrierCount, const VkImageMemoryBarrier* pImageMemoryBarriers); + void gen9_CmdWaitEvents(VkCommandBuffer commandBuffer, uint32_t eventCount, const VkEvent* pEvents, VkPipelineStageFlags srcStageMask, VkPipelineStageFlags dstStageMask, uint32_t memoryBarrierCount, const VkMemoryBarrier* pMemoryBarriers, uint32_t bufferMemoryBarrierCount, const VkBufferMemoryBarrier* pBufferMemoryBarriers, uint32_t imageMemoryBarrierCount, const VkImageMemoryBarrier* pImageMemoryBarriers); + void gen10_CmdWaitEvents(VkCommandBuffer commandBuffer, uint32_t eventCount, const VkEvent* pEvents, VkPipelineStageFlags srcStageMask, VkPipelineStageFlags dstStageMask, uint32_t memoryBarrierCount, const VkMemoryBarrier* pMemoryBarriers, uint32_t bufferMemoryBarrierCount, const VkBufferMemoryBarrier* pBufferMemoryBarriers, uint32_t imageMemoryBarrierCount, const VkImageMemoryBarrier* pImageMemoryBarriers); + void gen11_CmdWaitEvents(VkCommandBuffer commandBuffer, uint32_t eventCount, const VkEvent* pEvents, VkPipelineStageFlags srcStageMask, VkPipelineStageFlags dstStageMask, uint32_t memoryBarrierCount, const VkMemoryBarrier* pMemoryBarriers, uint32_t bufferMemoryBarrierCount, const VkBufferMemoryBarrier* pBufferMemoryBarriers, uint32_t imageMemoryBarrierCount, const VkImageMemoryBarrier* pImageMemoryBarriers); + void anv_CmdPipelineBarrier(VkCommandBuffer commandBuffer, VkPipelineStageFlags srcStageMask, VkPipelineStageFlags dstStageMask, VkDependencyFlags dependencyFlags, uint32_t memoryBarrierCount, const VkMemoryBarrier* pMemoryBarriers, uint32_t bufferMemoryBarrierCount, const VkBufferMemoryBarrier* pBufferMemoryBarriers, uint32_t imageMemoryBarrierCount, const VkImageMemoryBarrier* pImageMemoryBarriers); + void gen7_CmdPipelineBarrier(VkCommandBuffer commandBuffer, VkPipelineStageFlags srcStageMask, VkPipelineStageFlags dstStageMask, VkDependencyFlags dependencyFlags, uint32_t memoryBarrierCount, const VkMemoryBarrier* pMemoryBarriers, uint32_t bufferMemoryBarrierCount, const VkBufferMemoryBarrier* pBufferMemoryBarriers, uint32_t imageMemoryBarrierCount, const VkImageMemoryBarrier* pImageMemoryBarriers); + void gen75_CmdPipelineBarrier(VkCommandBuffer commandBuffer, VkPipelineStageFlags srcStageMask, VkPipelineStageFlags dstStageMask, VkDependencyFlags dependencyFlags, uint32_t memoryBarrierCount, const VkMemoryBarrier* pMemoryBarriers, uint32_t bufferMemoryBarrierCount, const VkBufferMemoryBarrier* pBufferMemoryBarriers, uint32_t imageMemoryBarrierCount, const VkImageMemoryBarrier* pImageMemoryBarriers); + void gen8_CmdPipelineBarrier(VkCommandBuffer commandBuffer, VkPipelineStageFlags srcStageMask, VkPipelineStageFlags dstStageMask, VkDependencyFlags dependencyFlags, uint32_t memoryBarrierCount, const VkMemoryBarrier* pMemoryBarriers, uint32_t bufferMemoryBarrierCount, const VkBufferMemoryBarrier* pBufferMemoryBarriers, uint32_t imageMemoryBarrierCount, const VkImageMemoryBarrier* pImageMemoryBarriers); + void gen9_CmdPipelineBarrier(VkCommandBuffer commandBuffer, VkPipelineStageFlags srcStageMask, VkPipelineStageFlags dstStageMask, VkDependencyFlags dependencyFlags, uint32_t memoryBarrierCount, const VkMemoryBarrier* pMemoryBarriers, uint32_t bufferMemoryBarrierCount, const VkBufferMemoryBarrier* pBufferMemoryBarriers, uint32_t imageMemoryBarrierCount, const VkImageMemoryBarrier* pImageMemoryBarriers); + void gen10_CmdPipelineBarrier(VkCommandBuffer commandBuffer, VkPipelineStageFlags srcStageMask, VkPipelineStageFlags dstStageMask, VkDependencyFlags dependencyFlags, uint32_t memoryBarrierCount, const VkMemoryBarrier* pMemoryBarriers, uint32_t bufferMemoryBarrierCount, const VkBufferMemoryBarrier* pBufferMemoryBarriers, uint32_t imageMemoryBarrierCount, const VkImageMemoryBarrier* pImageMemoryBarriers); + void gen11_CmdPipelineBarrier(VkCommandBuffer commandBuffer, VkPipelineStageFlags srcStageMask, VkPipelineStageFlags dstStageMask, VkDependencyFlags dependencyFlags, uint32_t memoryBarrierCount, const VkMemoryBarrier* pMemoryBarriers, uint32_t bufferMemoryBarrierCount, const VkBufferMemoryBarrier* pBufferMemoryBarriers, uint32_t imageMemoryBarrierCount, const VkImageMemoryBarrier* pImageMemoryBarriers); + void anv_CmdBeginQuery(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, VkQueryControlFlags flags); + void gen7_CmdBeginQuery(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, VkQueryControlFlags flags); + void gen75_CmdBeginQuery(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, VkQueryControlFlags flags); + void gen8_CmdBeginQuery(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, VkQueryControlFlags flags); + void gen9_CmdBeginQuery(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, VkQueryControlFlags flags); + void gen10_CmdBeginQuery(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, VkQueryControlFlags flags); + void gen11_CmdBeginQuery(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, VkQueryControlFlags flags); + void anv_CmdEndQuery(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query); + void gen7_CmdEndQuery(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query); + void gen75_CmdEndQuery(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query); + void gen8_CmdEndQuery(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query); + void gen9_CmdEndQuery(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query); + void gen10_CmdEndQuery(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query); + void gen11_CmdEndQuery(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query); + void anv_CmdBeginConditionalRenderingEXT(VkCommandBuffer commandBuffer, const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin); + void gen7_CmdBeginConditionalRenderingEXT(VkCommandBuffer commandBuffer, const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin); + void gen75_CmdBeginConditionalRenderingEXT(VkCommandBuffer commandBuffer, const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin); + void gen8_CmdBeginConditionalRenderingEXT(VkCommandBuffer commandBuffer, const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin); + void gen9_CmdBeginConditionalRenderingEXT(VkCommandBuffer commandBuffer, const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin); + void gen10_CmdBeginConditionalRenderingEXT(VkCommandBuffer commandBuffer, const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin); + void gen11_CmdBeginConditionalRenderingEXT(VkCommandBuffer commandBuffer, const VkConditionalRenderingBeginInfoEXT* pConditionalRenderingBegin); + void anv_CmdEndConditionalRenderingEXT(VkCommandBuffer commandBuffer); + void gen7_CmdEndConditionalRenderingEXT(VkCommandBuffer commandBuffer); + void gen75_CmdEndConditionalRenderingEXT(VkCommandBuffer commandBuffer); + void gen8_CmdEndConditionalRenderingEXT(VkCommandBuffer commandBuffer); + void gen9_CmdEndConditionalRenderingEXT(VkCommandBuffer commandBuffer); + void gen10_CmdEndConditionalRenderingEXT(VkCommandBuffer commandBuffer); + void gen11_CmdEndConditionalRenderingEXT(VkCommandBuffer commandBuffer); + void anv_CmdResetQueryPool(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount); + void gen7_CmdResetQueryPool(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount); + void gen75_CmdResetQueryPool(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount); + void gen8_CmdResetQueryPool(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount); + void gen9_CmdResetQueryPool(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount); + void gen10_CmdResetQueryPool(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount); + void gen11_CmdResetQueryPool(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount); + void anv_CmdWriteTimestamp(VkCommandBuffer commandBuffer, VkPipelineStageFlagBits pipelineStage, VkQueryPool queryPool, uint32_t query); + void gen7_CmdWriteTimestamp(VkCommandBuffer commandBuffer, VkPipelineStageFlagBits pipelineStage, VkQueryPool queryPool, uint32_t query); + void gen75_CmdWriteTimestamp(VkCommandBuffer commandBuffer, VkPipelineStageFlagBits pipelineStage, VkQueryPool queryPool, uint32_t query); + void gen8_CmdWriteTimestamp(VkCommandBuffer commandBuffer, VkPipelineStageFlagBits pipelineStage, VkQueryPool queryPool, uint32_t query); + void gen9_CmdWriteTimestamp(VkCommandBuffer commandBuffer, VkPipelineStageFlagBits pipelineStage, VkQueryPool queryPool, uint32_t query); + void gen10_CmdWriteTimestamp(VkCommandBuffer commandBuffer, VkPipelineStageFlagBits pipelineStage, VkQueryPool queryPool, uint32_t query); + void gen11_CmdWriteTimestamp(VkCommandBuffer commandBuffer, VkPipelineStageFlagBits pipelineStage, VkQueryPool queryPool, uint32_t query); + void anv_CmdCopyQueryPoolResults(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize stride, VkQueryResultFlags flags); + void gen7_CmdCopyQueryPoolResults(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize stride, VkQueryResultFlags flags); + void gen75_CmdCopyQueryPoolResults(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize stride, VkQueryResultFlags flags); + void gen8_CmdCopyQueryPoolResults(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize stride, VkQueryResultFlags flags); + void gen9_CmdCopyQueryPoolResults(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize stride, VkQueryResultFlags flags); + void gen10_CmdCopyQueryPoolResults(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize stride, VkQueryResultFlags flags); + void gen11_CmdCopyQueryPoolResults(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t firstQuery, uint32_t queryCount, VkBuffer dstBuffer, VkDeviceSize dstOffset, VkDeviceSize stride, VkQueryResultFlags flags); + void anv_CmdPushConstants(VkCommandBuffer commandBuffer, VkPipelineLayout layout, VkShaderStageFlags stageFlags, uint32_t offset, uint32_t size, const void* pValues); + void gen7_CmdPushConstants(VkCommandBuffer commandBuffer, VkPipelineLayout layout, VkShaderStageFlags stageFlags, uint32_t offset, uint32_t size, const void* pValues); + void gen75_CmdPushConstants(VkCommandBuffer commandBuffer, VkPipelineLayout layout, VkShaderStageFlags stageFlags, uint32_t offset, uint32_t size, const void* pValues); + void gen8_CmdPushConstants(VkCommandBuffer commandBuffer, VkPipelineLayout layout, VkShaderStageFlags stageFlags, uint32_t offset, uint32_t size, const void* pValues); + void gen9_CmdPushConstants(VkCommandBuffer commandBuffer, VkPipelineLayout layout, VkShaderStageFlags stageFlags, uint32_t offset, uint32_t size, const void* pValues); + void gen10_CmdPushConstants(VkCommandBuffer commandBuffer, VkPipelineLayout layout, VkShaderStageFlags stageFlags, uint32_t offset, uint32_t size, const void* pValues); + void gen11_CmdPushConstants(VkCommandBuffer commandBuffer, VkPipelineLayout layout, VkShaderStageFlags stageFlags, uint32_t offset, uint32_t size, const void* pValues); + void anv_CmdBeginRenderPass(VkCommandBuffer commandBuffer, const VkRenderPassBeginInfo* pRenderPassBegin, VkSubpassContents contents); + void gen7_CmdBeginRenderPass(VkCommandBuffer commandBuffer, const VkRenderPassBeginInfo* pRenderPassBegin, VkSubpassContents contents); + void gen75_CmdBeginRenderPass(VkCommandBuffer commandBuffer, const VkRenderPassBeginInfo* pRenderPassBegin, VkSubpassContents contents); + void gen8_CmdBeginRenderPass(VkCommandBuffer commandBuffer, const VkRenderPassBeginInfo* pRenderPassBegin, VkSubpassContents contents); + void gen9_CmdBeginRenderPass(VkCommandBuffer commandBuffer, const VkRenderPassBeginInfo* pRenderPassBegin, VkSubpassContents contents); + void gen10_CmdBeginRenderPass(VkCommandBuffer commandBuffer, const VkRenderPassBeginInfo* pRenderPassBegin, VkSubpassContents contents); + void gen11_CmdBeginRenderPass(VkCommandBuffer commandBuffer, const VkRenderPassBeginInfo* pRenderPassBegin, VkSubpassContents contents); + void anv_CmdNextSubpass(VkCommandBuffer commandBuffer, VkSubpassContents contents); + void gen7_CmdNextSubpass(VkCommandBuffer commandBuffer, VkSubpassContents contents); + void gen75_CmdNextSubpass(VkCommandBuffer commandBuffer, VkSubpassContents contents); + void gen8_CmdNextSubpass(VkCommandBuffer commandBuffer, VkSubpassContents contents); + void gen9_CmdNextSubpass(VkCommandBuffer commandBuffer, VkSubpassContents contents); + void gen10_CmdNextSubpass(VkCommandBuffer commandBuffer, VkSubpassContents contents); + void gen11_CmdNextSubpass(VkCommandBuffer commandBuffer, VkSubpassContents contents); + void anv_CmdEndRenderPass(VkCommandBuffer commandBuffer); + void gen7_CmdEndRenderPass(VkCommandBuffer commandBuffer); + void gen75_CmdEndRenderPass(VkCommandBuffer commandBuffer); + void gen8_CmdEndRenderPass(VkCommandBuffer commandBuffer); + void gen9_CmdEndRenderPass(VkCommandBuffer commandBuffer); + void gen10_CmdEndRenderPass(VkCommandBuffer commandBuffer); + void gen11_CmdEndRenderPass(VkCommandBuffer commandBuffer); + void anv_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCount, const VkCommandBuffer* pCommandBuffers); + void gen7_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCount, const VkCommandBuffer* pCommandBuffers); + void gen75_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCount, const VkCommandBuffer* pCommandBuffers); + void gen8_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCount, const VkCommandBuffer* pCommandBuffers); + void gen9_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCount, const VkCommandBuffer* pCommandBuffers); + void gen10_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCount, const VkCommandBuffer* pCommandBuffers); + void gen11_CmdExecuteCommands(VkCommandBuffer commandBuffer, uint32_t commandBufferCount, const VkCommandBuffer* pCommandBuffers); + VkResult anv_CreateSwapchainKHR(VkDevice device, const VkSwapchainCreateInfoKHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSwapchainKHR* pSwapchain); + VkResult gen7_CreateSwapchainKHR(VkDevice device, const VkSwapchainCreateInfoKHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSwapchainKHR* pSwapchain); + VkResult gen75_CreateSwapchainKHR(VkDevice device, const VkSwapchainCreateInfoKHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSwapchainKHR* pSwapchain); + VkResult gen8_CreateSwapchainKHR(VkDevice device, const VkSwapchainCreateInfoKHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSwapchainKHR* pSwapchain); + VkResult gen9_CreateSwapchainKHR(VkDevice device, const VkSwapchainCreateInfoKHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSwapchainKHR* pSwapchain); + VkResult gen10_CreateSwapchainKHR(VkDevice device, const VkSwapchainCreateInfoKHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSwapchainKHR* pSwapchain); + VkResult gen11_CreateSwapchainKHR(VkDevice device, const VkSwapchainCreateInfoKHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSwapchainKHR* pSwapchain); + void anv_DestroySwapchainKHR(VkDevice device, VkSwapchainKHR swapchain, const VkAllocationCallbacks* pAllocator); + void gen7_DestroySwapchainKHR(VkDevice device, VkSwapchainKHR swapchain, const VkAllocationCallbacks* pAllocator); + void gen75_DestroySwapchainKHR(VkDevice device, VkSwapchainKHR swapchain, const VkAllocationCallbacks* pAllocator); + void gen8_DestroySwapchainKHR(VkDevice device, VkSwapchainKHR swapchain, const VkAllocationCallbacks* pAllocator); + void gen9_DestroySwapchainKHR(VkDevice device, VkSwapchainKHR swapchain, const VkAllocationCallbacks* pAllocator); + void gen10_DestroySwapchainKHR(VkDevice device, VkSwapchainKHR swapchain, const VkAllocationCallbacks* pAllocator); + void gen11_DestroySwapchainKHR(VkDevice device, VkSwapchainKHR swapchain, const VkAllocationCallbacks* pAllocator); + VkResult anv_GetSwapchainImagesKHR(VkDevice device, VkSwapchainKHR swapchain, uint32_t* pSwapchainImageCount, VkImage* pSwapchainImages); + VkResult gen7_GetSwapchainImagesKHR(VkDevice device, VkSwapchainKHR swapchain, uint32_t* pSwapchainImageCount, VkImage* pSwapchainImages); + VkResult gen75_GetSwapchainImagesKHR(VkDevice device, VkSwapchainKHR swapchain, uint32_t* pSwapchainImageCount, VkImage* pSwapchainImages); + VkResult gen8_GetSwapchainImagesKHR(VkDevice device, VkSwapchainKHR swapchain, uint32_t* pSwapchainImageCount, VkImage* pSwapchainImages); + VkResult gen9_GetSwapchainImagesKHR(VkDevice device, VkSwapchainKHR swapchain, uint32_t* pSwapchainImageCount, VkImage* pSwapchainImages); + VkResult gen10_GetSwapchainImagesKHR(VkDevice device, VkSwapchainKHR swapchain, uint32_t* pSwapchainImageCount, VkImage* pSwapchainImages); + VkResult gen11_GetSwapchainImagesKHR(VkDevice device, VkSwapchainKHR swapchain, uint32_t* pSwapchainImageCount, VkImage* pSwapchainImages); + VkResult anv_AcquireNextImageKHR(VkDevice device, VkSwapchainKHR swapchain, uint64_t timeout, VkSemaphore semaphore, VkFence fence, uint32_t* pImageIndex); + VkResult gen7_AcquireNextImageKHR(VkDevice device, VkSwapchainKHR swapchain, uint64_t timeout, VkSemaphore semaphore, VkFence fence, uint32_t* pImageIndex); + VkResult gen75_AcquireNextImageKHR(VkDevice device, VkSwapchainKHR swapchain, uint64_t timeout, VkSemaphore semaphore, VkFence fence, uint32_t* pImageIndex); + VkResult gen8_AcquireNextImageKHR(VkDevice device, VkSwapchainKHR swapchain, uint64_t timeout, VkSemaphore semaphore, VkFence fence, uint32_t* pImageIndex); + VkResult gen9_AcquireNextImageKHR(VkDevice device, VkSwapchainKHR swapchain, uint64_t timeout, VkSemaphore semaphore, VkFence fence, uint32_t* pImageIndex); + VkResult gen10_AcquireNextImageKHR(VkDevice device, VkSwapchainKHR swapchain, uint64_t timeout, VkSemaphore semaphore, VkFence fence, uint32_t* pImageIndex); + VkResult gen11_AcquireNextImageKHR(VkDevice device, VkSwapchainKHR swapchain, uint64_t timeout, VkSemaphore semaphore, VkFence fence, uint32_t* pImageIndex); + VkResult anv_QueuePresentKHR(VkQueue queue, const VkPresentInfoKHR* pPresentInfo); + VkResult gen7_QueuePresentKHR(VkQueue queue, const VkPresentInfoKHR* pPresentInfo); + VkResult gen75_QueuePresentKHR(VkQueue queue, const VkPresentInfoKHR* pPresentInfo); + VkResult gen8_QueuePresentKHR(VkQueue queue, const VkPresentInfoKHR* pPresentInfo); + VkResult gen9_QueuePresentKHR(VkQueue queue, const VkPresentInfoKHR* pPresentInfo); + VkResult gen10_QueuePresentKHR(VkQueue queue, const VkPresentInfoKHR* pPresentInfo); + VkResult gen11_QueuePresentKHR(VkQueue queue, const VkPresentInfoKHR* pPresentInfo); + void anv_CmdPushDescriptorSetKHR(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipelineLayout layout, uint32_t set, uint32_t descriptorWriteCount, const VkWriteDescriptorSet* pDescriptorWrites); + void gen7_CmdPushDescriptorSetKHR(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipelineLayout layout, uint32_t set, uint32_t descriptorWriteCount, const VkWriteDescriptorSet* pDescriptorWrites); + void gen75_CmdPushDescriptorSetKHR(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipelineLayout layout, uint32_t set, uint32_t descriptorWriteCount, const VkWriteDescriptorSet* pDescriptorWrites); + void gen8_CmdPushDescriptorSetKHR(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipelineLayout layout, uint32_t set, uint32_t descriptorWriteCount, const VkWriteDescriptorSet* pDescriptorWrites); + void gen9_CmdPushDescriptorSetKHR(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipelineLayout layout, uint32_t set, uint32_t descriptorWriteCount, const VkWriteDescriptorSet* pDescriptorWrites); + void gen10_CmdPushDescriptorSetKHR(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipelineLayout layout, uint32_t set, uint32_t descriptorWriteCount, const VkWriteDescriptorSet* pDescriptorWrites); + void gen11_CmdPushDescriptorSetKHR(VkCommandBuffer commandBuffer, VkPipelineBindPoint pipelineBindPoint, VkPipelineLayout layout, uint32_t set, uint32_t descriptorWriteCount, const VkWriteDescriptorSet* pDescriptorWrites); + void anv_TrimCommandPool(VkDevice device, VkCommandPool commandPool, VkCommandPoolTrimFlags flags); + void gen7_TrimCommandPool(VkDevice device, VkCommandPool commandPool, VkCommandPoolTrimFlags flags); + void gen75_TrimCommandPool(VkDevice device, VkCommandPool commandPool, VkCommandPoolTrimFlags flags); + void gen8_TrimCommandPool(VkDevice device, VkCommandPool commandPool, VkCommandPoolTrimFlags flags); + void gen9_TrimCommandPool(VkDevice device, VkCommandPool commandPool, VkCommandPoolTrimFlags flags); + void gen10_TrimCommandPool(VkDevice device, VkCommandPool commandPool, VkCommandPoolTrimFlags flags); + void gen11_TrimCommandPool(VkDevice device, VkCommandPool commandPool, VkCommandPoolTrimFlags flags); + VkResult anv_GetMemoryFdKHR(VkDevice device, const VkMemoryGetFdInfoKHR* pGetFdInfo, int* pFd); + VkResult gen7_GetMemoryFdKHR(VkDevice device, const VkMemoryGetFdInfoKHR* pGetFdInfo, int* pFd); + VkResult gen75_GetMemoryFdKHR(VkDevice device, const VkMemoryGetFdInfoKHR* pGetFdInfo, int* pFd); + VkResult gen8_GetMemoryFdKHR(VkDevice device, const VkMemoryGetFdInfoKHR* pGetFdInfo, int* pFd); + VkResult gen9_GetMemoryFdKHR(VkDevice device, const VkMemoryGetFdInfoKHR* pGetFdInfo, int* pFd); + VkResult gen10_GetMemoryFdKHR(VkDevice device, const VkMemoryGetFdInfoKHR* pGetFdInfo, int* pFd); + VkResult gen11_GetMemoryFdKHR(VkDevice device, const VkMemoryGetFdInfoKHR* pGetFdInfo, int* pFd); + VkResult anv_GetMemoryFdPropertiesKHR(VkDevice device, VkExternalMemoryHandleTypeFlagBits handleType, int fd, VkMemoryFdPropertiesKHR* pMemoryFdProperties); + VkResult gen7_GetMemoryFdPropertiesKHR(VkDevice device, VkExternalMemoryHandleTypeFlagBits handleType, int fd, VkMemoryFdPropertiesKHR* pMemoryFdProperties); + VkResult gen75_GetMemoryFdPropertiesKHR(VkDevice device, VkExternalMemoryHandleTypeFlagBits handleType, int fd, VkMemoryFdPropertiesKHR* pMemoryFdProperties); + VkResult gen8_GetMemoryFdPropertiesKHR(VkDevice device, VkExternalMemoryHandleTypeFlagBits handleType, int fd, VkMemoryFdPropertiesKHR* pMemoryFdProperties); + VkResult gen9_GetMemoryFdPropertiesKHR(VkDevice device, VkExternalMemoryHandleTypeFlagBits handleType, int fd, VkMemoryFdPropertiesKHR* pMemoryFdProperties); + VkResult gen10_GetMemoryFdPropertiesKHR(VkDevice device, VkExternalMemoryHandleTypeFlagBits handleType, int fd, VkMemoryFdPropertiesKHR* pMemoryFdProperties); + VkResult gen11_GetMemoryFdPropertiesKHR(VkDevice device, VkExternalMemoryHandleTypeFlagBits handleType, int fd, VkMemoryFdPropertiesKHR* pMemoryFdProperties); + VkResult anv_GetSemaphoreFdKHR(VkDevice device, const VkSemaphoreGetFdInfoKHR* pGetFdInfo, int* pFd); + VkResult gen7_GetSemaphoreFdKHR(VkDevice device, const VkSemaphoreGetFdInfoKHR* pGetFdInfo, int* pFd); + VkResult gen75_GetSemaphoreFdKHR(VkDevice device, const VkSemaphoreGetFdInfoKHR* pGetFdInfo, int* pFd); + VkResult gen8_GetSemaphoreFdKHR(VkDevice device, const VkSemaphoreGetFdInfoKHR* pGetFdInfo, int* pFd); + VkResult gen9_GetSemaphoreFdKHR(VkDevice device, const VkSemaphoreGetFdInfoKHR* pGetFdInfo, int* pFd); + VkResult gen10_GetSemaphoreFdKHR(VkDevice device, const VkSemaphoreGetFdInfoKHR* pGetFdInfo, int* pFd); + VkResult gen11_GetSemaphoreFdKHR(VkDevice device, const VkSemaphoreGetFdInfoKHR* pGetFdInfo, int* pFd); + VkResult anv_ImportSemaphoreFdKHR(VkDevice device, const VkImportSemaphoreFdInfoKHR* pImportSemaphoreFdInfo); + VkResult gen7_ImportSemaphoreFdKHR(VkDevice device, const VkImportSemaphoreFdInfoKHR* pImportSemaphoreFdInfo); + VkResult gen75_ImportSemaphoreFdKHR(VkDevice device, const VkImportSemaphoreFdInfoKHR* pImportSemaphoreFdInfo); + VkResult gen8_ImportSemaphoreFdKHR(VkDevice device, const VkImportSemaphoreFdInfoKHR* pImportSemaphoreFdInfo); + VkResult gen9_ImportSemaphoreFdKHR(VkDevice device, const VkImportSemaphoreFdInfoKHR* pImportSemaphoreFdInfo); + VkResult gen10_ImportSemaphoreFdKHR(VkDevice device, const VkImportSemaphoreFdInfoKHR* pImportSemaphoreFdInfo); + VkResult gen11_ImportSemaphoreFdKHR(VkDevice device, const VkImportSemaphoreFdInfoKHR* pImportSemaphoreFdInfo); + VkResult anv_GetFenceFdKHR(VkDevice device, const VkFenceGetFdInfoKHR* pGetFdInfo, int* pFd); + VkResult gen7_GetFenceFdKHR(VkDevice device, const VkFenceGetFdInfoKHR* pGetFdInfo, int* pFd); + VkResult gen75_GetFenceFdKHR(VkDevice device, const VkFenceGetFdInfoKHR* pGetFdInfo, int* pFd); + VkResult gen8_GetFenceFdKHR(VkDevice device, const VkFenceGetFdInfoKHR* pGetFdInfo, int* pFd); + VkResult gen9_GetFenceFdKHR(VkDevice device, const VkFenceGetFdInfoKHR* pGetFdInfo, int* pFd); + VkResult gen10_GetFenceFdKHR(VkDevice device, const VkFenceGetFdInfoKHR* pGetFdInfo, int* pFd); + VkResult gen11_GetFenceFdKHR(VkDevice device, const VkFenceGetFdInfoKHR* pGetFdInfo, int* pFd); + VkResult anv_ImportFenceFdKHR(VkDevice device, const VkImportFenceFdInfoKHR* pImportFenceFdInfo); + VkResult gen7_ImportFenceFdKHR(VkDevice device, const VkImportFenceFdInfoKHR* pImportFenceFdInfo); + VkResult gen75_ImportFenceFdKHR(VkDevice device, const VkImportFenceFdInfoKHR* pImportFenceFdInfo); + VkResult gen8_ImportFenceFdKHR(VkDevice device, const VkImportFenceFdInfoKHR* pImportFenceFdInfo); + VkResult gen9_ImportFenceFdKHR(VkDevice device, const VkImportFenceFdInfoKHR* pImportFenceFdInfo); + VkResult gen10_ImportFenceFdKHR(VkDevice device, const VkImportFenceFdInfoKHR* pImportFenceFdInfo); + VkResult gen11_ImportFenceFdKHR(VkDevice device, const VkImportFenceFdInfoKHR* pImportFenceFdInfo); + VkResult anv_DisplayPowerControlEXT(VkDevice device, VkDisplayKHR display, const VkDisplayPowerInfoEXT* pDisplayPowerInfo); + VkResult gen7_DisplayPowerControlEXT(VkDevice device, VkDisplayKHR display, const VkDisplayPowerInfoEXT* pDisplayPowerInfo); + VkResult gen75_DisplayPowerControlEXT(VkDevice device, VkDisplayKHR display, const VkDisplayPowerInfoEXT* pDisplayPowerInfo); + VkResult gen8_DisplayPowerControlEXT(VkDevice device, VkDisplayKHR display, const VkDisplayPowerInfoEXT* pDisplayPowerInfo); + VkResult gen9_DisplayPowerControlEXT(VkDevice device, VkDisplayKHR display, const VkDisplayPowerInfoEXT* pDisplayPowerInfo); + VkResult gen10_DisplayPowerControlEXT(VkDevice device, VkDisplayKHR display, const VkDisplayPowerInfoEXT* pDisplayPowerInfo); + VkResult gen11_DisplayPowerControlEXT(VkDevice device, VkDisplayKHR display, const VkDisplayPowerInfoEXT* pDisplayPowerInfo); + VkResult anv_RegisterDeviceEventEXT(VkDevice device, const VkDeviceEventInfoEXT* pDeviceEventInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence); + VkResult gen7_RegisterDeviceEventEXT(VkDevice device, const VkDeviceEventInfoEXT* pDeviceEventInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence); + VkResult gen75_RegisterDeviceEventEXT(VkDevice device, const VkDeviceEventInfoEXT* pDeviceEventInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence); + VkResult gen8_RegisterDeviceEventEXT(VkDevice device, const VkDeviceEventInfoEXT* pDeviceEventInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence); + VkResult gen9_RegisterDeviceEventEXT(VkDevice device, const VkDeviceEventInfoEXT* pDeviceEventInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence); + VkResult gen10_RegisterDeviceEventEXT(VkDevice device, const VkDeviceEventInfoEXT* pDeviceEventInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence); + VkResult gen11_RegisterDeviceEventEXT(VkDevice device, const VkDeviceEventInfoEXT* pDeviceEventInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence); + VkResult anv_RegisterDisplayEventEXT(VkDevice device, VkDisplayKHR display, const VkDisplayEventInfoEXT* pDisplayEventInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence); + VkResult gen7_RegisterDisplayEventEXT(VkDevice device, VkDisplayKHR display, const VkDisplayEventInfoEXT* pDisplayEventInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence); + VkResult gen75_RegisterDisplayEventEXT(VkDevice device, VkDisplayKHR display, const VkDisplayEventInfoEXT* pDisplayEventInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence); + VkResult gen8_RegisterDisplayEventEXT(VkDevice device, VkDisplayKHR display, const VkDisplayEventInfoEXT* pDisplayEventInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence); + VkResult gen9_RegisterDisplayEventEXT(VkDevice device, VkDisplayKHR display, const VkDisplayEventInfoEXT* pDisplayEventInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence); + VkResult gen10_RegisterDisplayEventEXT(VkDevice device, VkDisplayKHR display, const VkDisplayEventInfoEXT* pDisplayEventInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence); + VkResult gen11_RegisterDisplayEventEXT(VkDevice device, VkDisplayKHR display, const VkDisplayEventInfoEXT* pDisplayEventInfo, const VkAllocationCallbacks* pAllocator, VkFence* pFence); + VkResult anv_GetSwapchainCounterEXT(VkDevice device, VkSwapchainKHR swapchain, VkSurfaceCounterFlagBitsEXT counter, uint64_t* pCounterValue); + VkResult gen7_GetSwapchainCounterEXT(VkDevice device, VkSwapchainKHR swapchain, VkSurfaceCounterFlagBitsEXT counter, uint64_t* pCounterValue); + VkResult gen75_GetSwapchainCounterEXT(VkDevice device, VkSwapchainKHR swapchain, VkSurfaceCounterFlagBitsEXT counter, uint64_t* pCounterValue); + VkResult gen8_GetSwapchainCounterEXT(VkDevice device, VkSwapchainKHR swapchain, VkSurfaceCounterFlagBitsEXT counter, uint64_t* pCounterValue); + VkResult gen9_GetSwapchainCounterEXT(VkDevice device, VkSwapchainKHR swapchain, VkSurfaceCounterFlagBitsEXT counter, uint64_t* pCounterValue); + VkResult gen10_GetSwapchainCounterEXT(VkDevice device, VkSwapchainKHR swapchain, VkSurfaceCounterFlagBitsEXT counter, uint64_t* pCounterValue); + VkResult gen11_GetSwapchainCounterEXT(VkDevice device, VkSwapchainKHR swapchain, VkSurfaceCounterFlagBitsEXT counter, uint64_t* pCounterValue); + void anv_GetDeviceGroupPeerMemoryFeatures(VkDevice device, uint32_t heapIndex, uint32_t localDeviceIndex, uint32_t remoteDeviceIndex, VkPeerMemoryFeatureFlags* pPeerMemoryFeatures); + void gen7_GetDeviceGroupPeerMemoryFeatures(VkDevice device, uint32_t heapIndex, uint32_t localDeviceIndex, uint32_t remoteDeviceIndex, VkPeerMemoryFeatureFlags* pPeerMemoryFeatures); + void gen75_GetDeviceGroupPeerMemoryFeatures(VkDevice device, uint32_t heapIndex, uint32_t localDeviceIndex, uint32_t remoteDeviceIndex, VkPeerMemoryFeatureFlags* pPeerMemoryFeatures); + void gen8_GetDeviceGroupPeerMemoryFeatures(VkDevice device, uint32_t heapIndex, uint32_t localDeviceIndex, uint32_t remoteDeviceIndex, VkPeerMemoryFeatureFlags* pPeerMemoryFeatures); + void gen9_GetDeviceGroupPeerMemoryFeatures(VkDevice device, uint32_t heapIndex, uint32_t localDeviceIndex, uint32_t remoteDeviceIndex, VkPeerMemoryFeatureFlags* pPeerMemoryFeatures); + void gen10_GetDeviceGroupPeerMemoryFeatures(VkDevice device, uint32_t heapIndex, uint32_t localDeviceIndex, uint32_t remoteDeviceIndex, VkPeerMemoryFeatureFlags* pPeerMemoryFeatures); + void gen11_GetDeviceGroupPeerMemoryFeatures(VkDevice device, uint32_t heapIndex, uint32_t localDeviceIndex, uint32_t remoteDeviceIndex, VkPeerMemoryFeatureFlags* pPeerMemoryFeatures); + VkResult anv_BindBufferMemory2(VkDevice device, uint32_t bindInfoCount, const VkBindBufferMemoryInfo* pBindInfos); + VkResult gen7_BindBufferMemory2(VkDevice device, uint32_t bindInfoCount, const VkBindBufferMemoryInfo* pBindInfos); + VkResult gen75_BindBufferMemory2(VkDevice device, uint32_t bindInfoCount, const VkBindBufferMemoryInfo* pBindInfos); + VkResult gen8_BindBufferMemory2(VkDevice device, uint32_t bindInfoCount, const VkBindBufferMemoryInfo* pBindInfos); + VkResult gen9_BindBufferMemory2(VkDevice device, uint32_t bindInfoCount, const VkBindBufferMemoryInfo* pBindInfos); + VkResult gen10_BindBufferMemory2(VkDevice device, uint32_t bindInfoCount, const VkBindBufferMemoryInfo* pBindInfos); + VkResult gen11_BindBufferMemory2(VkDevice device, uint32_t bindInfoCount, const VkBindBufferMemoryInfo* pBindInfos); + VkResult anv_BindImageMemory2(VkDevice device, uint32_t bindInfoCount, const VkBindImageMemoryInfo* pBindInfos); + VkResult gen7_BindImageMemory2(VkDevice device, uint32_t bindInfoCount, const VkBindImageMemoryInfo* pBindInfos); + VkResult gen75_BindImageMemory2(VkDevice device, uint32_t bindInfoCount, const VkBindImageMemoryInfo* pBindInfos); + VkResult gen8_BindImageMemory2(VkDevice device, uint32_t bindInfoCount, const VkBindImageMemoryInfo* pBindInfos); + VkResult gen9_BindImageMemory2(VkDevice device, uint32_t bindInfoCount, const VkBindImageMemoryInfo* pBindInfos); + VkResult gen10_BindImageMemory2(VkDevice device, uint32_t bindInfoCount, const VkBindImageMemoryInfo* pBindInfos); + VkResult gen11_BindImageMemory2(VkDevice device, uint32_t bindInfoCount, const VkBindImageMemoryInfo* pBindInfos); + void anv_CmdSetDeviceMask(VkCommandBuffer commandBuffer, uint32_t deviceMask); + void gen7_CmdSetDeviceMask(VkCommandBuffer commandBuffer, uint32_t deviceMask); + void gen75_CmdSetDeviceMask(VkCommandBuffer commandBuffer, uint32_t deviceMask); + void gen8_CmdSetDeviceMask(VkCommandBuffer commandBuffer, uint32_t deviceMask); + void gen9_CmdSetDeviceMask(VkCommandBuffer commandBuffer, uint32_t deviceMask); + void gen10_CmdSetDeviceMask(VkCommandBuffer commandBuffer, uint32_t deviceMask); + void gen11_CmdSetDeviceMask(VkCommandBuffer commandBuffer, uint32_t deviceMask); + VkResult anv_GetDeviceGroupPresentCapabilitiesKHR(VkDevice device, VkDeviceGroupPresentCapabilitiesKHR* pDeviceGroupPresentCapabilities); + VkResult gen7_GetDeviceGroupPresentCapabilitiesKHR(VkDevice device, VkDeviceGroupPresentCapabilitiesKHR* pDeviceGroupPresentCapabilities); + VkResult gen75_GetDeviceGroupPresentCapabilitiesKHR(VkDevice device, VkDeviceGroupPresentCapabilitiesKHR* pDeviceGroupPresentCapabilities); + VkResult gen8_GetDeviceGroupPresentCapabilitiesKHR(VkDevice device, VkDeviceGroupPresentCapabilitiesKHR* pDeviceGroupPresentCapabilities); + VkResult gen9_GetDeviceGroupPresentCapabilitiesKHR(VkDevice device, VkDeviceGroupPresentCapabilitiesKHR* pDeviceGroupPresentCapabilities); + VkResult gen10_GetDeviceGroupPresentCapabilitiesKHR(VkDevice device, VkDeviceGroupPresentCapabilitiesKHR* pDeviceGroupPresentCapabilities); + VkResult gen11_GetDeviceGroupPresentCapabilitiesKHR(VkDevice device, VkDeviceGroupPresentCapabilitiesKHR* pDeviceGroupPresentCapabilities); + VkResult anv_GetDeviceGroupSurfacePresentModesKHR(VkDevice device, VkSurfaceKHR surface, VkDeviceGroupPresentModeFlagsKHR* pModes); + VkResult gen7_GetDeviceGroupSurfacePresentModesKHR(VkDevice device, VkSurfaceKHR surface, VkDeviceGroupPresentModeFlagsKHR* pModes); + VkResult gen75_GetDeviceGroupSurfacePresentModesKHR(VkDevice device, VkSurfaceKHR surface, VkDeviceGroupPresentModeFlagsKHR* pModes); + VkResult gen8_GetDeviceGroupSurfacePresentModesKHR(VkDevice device, VkSurfaceKHR surface, VkDeviceGroupPresentModeFlagsKHR* pModes); + VkResult gen9_GetDeviceGroupSurfacePresentModesKHR(VkDevice device, VkSurfaceKHR surface, VkDeviceGroupPresentModeFlagsKHR* pModes); + VkResult gen10_GetDeviceGroupSurfacePresentModesKHR(VkDevice device, VkSurfaceKHR surface, VkDeviceGroupPresentModeFlagsKHR* pModes); + VkResult gen11_GetDeviceGroupSurfacePresentModesKHR(VkDevice device, VkSurfaceKHR surface, VkDeviceGroupPresentModeFlagsKHR* pModes); + VkResult anv_AcquireNextImage2KHR(VkDevice device, const VkAcquireNextImageInfoKHR* pAcquireInfo, uint32_t* pImageIndex); + VkResult gen7_AcquireNextImage2KHR(VkDevice device, const VkAcquireNextImageInfoKHR* pAcquireInfo, uint32_t* pImageIndex); + VkResult gen75_AcquireNextImage2KHR(VkDevice device, const VkAcquireNextImageInfoKHR* pAcquireInfo, uint32_t* pImageIndex); + VkResult gen8_AcquireNextImage2KHR(VkDevice device, const VkAcquireNextImageInfoKHR* pAcquireInfo, uint32_t* pImageIndex); + VkResult gen9_AcquireNextImage2KHR(VkDevice device, const VkAcquireNextImageInfoKHR* pAcquireInfo, uint32_t* pImageIndex); + VkResult gen10_AcquireNextImage2KHR(VkDevice device, const VkAcquireNextImageInfoKHR* pAcquireInfo, uint32_t* pImageIndex); + VkResult gen11_AcquireNextImage2KHR(VkDevice device, const VkAcquireNextImageInfoKHR* pAcquireInfo, uint32_t* pImageIndex); + void anv_CmdDispatchBase(VkCommandBuffer commandBuffer, uint32_t baseGroupX, uint32_t baseGroupY, uint32_t baseGroupZ, uint32_t groupCountX, uint32_t groupCountY, uint32_t groupCountZ); + void gen7_CmdDispatchBase(VkCommandBuffer commandBuffer, uint32_t baseGroupX, uint32_t baseGroupY, uint32_t baseGroupZ, uint32_t groupCountX, uint32_t groupCountY, uint32_t groupCountZ); + void gen75_CmdDispatchBase(VkCommandBuffer commandBuffer, uint32_t baseGroupX, uint32_t baseGroupY, uint32_t baseGroupZ, uint32_t groupCountX, uint32_t groupCountY, uint32_t groupCountZ); + void gen8_CmdDispatchBase(VkCommandBuffer commandBuffer, uint32_t baseGroupX, uint32_t baseGroupY, uint32_t baseGroupZ, uint32_t groupCountX, uint32_t groupCountY, uint32_t groupCountZ); + void gen9_CmdDispatchBase(VkCommandBuffer commandBuffer, uint32_t baseGroupX, uint32_t baseGroupY, uint32_t baseGroupZ, uint32_t groupCountX, uint32_t groupCountY, uint32_t groupCountZ); + void gen10_CmdDispatchBase(VkCommandBuffer commandBuffer, uint32_t baseGroupX, uint32_t baseGroupY, uint32_t baseGroupZ, uint32_t groupCountX, uint32_t groupCountY, uint32_t groupCountZ); + void gen11_CmdDispatchBase(VkCommandBuffer commandBuffer, uint32_t baseGroupX, uint32_t baseGroupY, uint32_t baseGroupZ, uint32_t groupCountX, uint32_t groupCountY, uint32_t groupCountZ); + VkResult anv_CreateDescriptorUpdateTemplate(VkDevice device, const VkDescriptorUpdateTemplateCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorUpdateTemplate* pDescriptorUpdateTemplate); + VkResult gen7_CreateDescriptorUpdateTemplate(VkDevice device, const VkDescriptorUpdateTemplateCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorUpdateTemplate* pDescriptorUpdateTemplate); + VkResult gen75_CreateDescriptorUpdateTemplate(VkDevice device, const VkDescriptorUpdateTemplateCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorUpdateTemplate* pDescriptorUpdateTemplate); + VkResult gen8_CreateDescriptorUpdateTemplate(VkDevice device, const VkDescriptorUpdateTemplateCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorUpdateTemplate* pDescriptorUpdateTemplate); + VkResult gen9_CreateDescriptorUpdateTemplate(VkDevice device, const VkDescriptorUpdateTemplateCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorUpdateTemplate* pDescriptorUpdateTemplate); + VkResult gen10_CreateDescriptorUpdateTemplate(VkDevice device, const VkDescriptorUpdateTemplateCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorUpdateTemplate* pDescriptorUpdateTemplate); + VkResult gen11_CreateDescriptorUpdateTemplate(VkDevice device, const VkDescriptorUpdateTemplateCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDescriptorUpdateTemplate* pDescriptorUpdateTemplate); + void anv_DestroyDescriptorUpdateTemplate(VkDevice device, VkDescriptorUpdateTemplate descriptorUpdateTemplate, const VkAllocationCallbacks* pAllocator); + void gen7_DestroyDescriptorUpdateTemplate(VkDevice device, VkDescriptorUpdateTemplate descriptorUpdateTemplate, const VkAllocationCallbacks* pAllocator); + void gen75_DestroyDescriptorUpdateTemplate(VkDevice device, VkDescriptorUpdateTemplate descriptorUpdateTemplate, const VkAllocationCallbacks* pAllocator); + void gen8_DestroyDescriptorUpdateTemplate(VkDevice device, VkDescriptorUpdateTemplate descriptorUpdateTemplate, const VkAllocationCallbacks* pAllocator); + void gen9_DestroyDescriptorUpdateTemplate(VkDevice device, VkDescriptorUpdateTemplate descriptorUpdateTemplate, const VkAllocationCallbacks* pAllocator); + void gen10_DestroyDescriptorUpdateTemplate(VkDevice device, VkDescriptorUpdateTemplate descriptorUpdateTemplate, const VkAllocationCallbacks* pAllocator); + void gen11_DestroyDescriptorUpdateTemplate(VkDevice device, VkDescriptorUpdateTemplate descriptorUpdateTemplate, const VkAllocationCallbacks* pAllocator); + void anv_UpdateDescriptorSetWithTemplate(VkDevice device, VkDescriptorSet descriptorSet, VkDescriptorUpdateTemplate descriptorUpdateTemplate, const void* pData); + void gen7_UpdateDescriptorSetWithTemplate(VkDevice device, VkDescriptorSet descriptorSet, VkDescriptorUpdateTemplate descriptorUpdateTemplate, const void* pData); + void gen75_UpdateDescriptorSetWithTemplate(VkDevice device, VkDescriptorSet descriptorSet, VkDescriptorUpdateTemplate descriptorUpdateTemplate, const void* pData); + void gen8_UpdateDescriptorSetWithTemplate(VkDevice device, VkDescriptorSet descriptorSet, VkDescriptorUpdateTemplate descriptorUpdateTemplate, const void* pData); + void gen9_UpdateDescriptorSetWithTemplate(VkDevice device, VkDescriptorSet descriptorSet, VkDescriptorUpdateTemplate descriptorUpdateTemplate, const void* pData); + void gen10_UpdateDescriptorSetWithTemplate(VkDevice device, VkDescriptorSet descriptorSet, VkDescriptorUpdateTemplate descriptorUpdateTemplate, const void* pData); + void gen11_UpdateDescriptorSetWithTemplate(VkDevice device, VkDescriptorSet descriptorSet, VkDescriptorUpdateTemplate descriptorUpdateTemplate, const void* pData); + void anv_CmdPushDescriptorSetWithTemplateKHR(VkCommandBuffer commandBuffer, VkDescriptorUpdateTemplate descriptorUpdateTemplate, VkPipelineLayout layout, uint32_t set, const void* pData); + void gen7_CmdPushDescriptorSetWithTemplateKHR(VkCommandBuffer commandBuffer, VkDescriptorUpdateTemplate descriptorUpdateTemplate, VkPipelineLayout layout, uint32_t set, const void* pData); + void gen75_CmdPushDescriptorSetWithTemplateKHR(VkCommandBuffer commandBuffer, VkDescriptorUpdateTemplate descriptorUpdateTemplate, VkPipelineLayout layout, uint32_t set, const void* pData); + void gen8_CmdPushDescriptorSetWithTemplateKHR(VkCommandBuffer commandBuffer, VkDescriptorUpdateTemplate descriptorUpdateTemplate, VkPipelineLayout layout, uint32_t set, const void* pData); + void gen9_CmdPushDescriptorSetWithTemplateKHR(VkCommandBuffer commandBuffer, VkDescriptorUpdateTemplate descriptorUpdateTemplate, VkPipelineLayout layout, uint32_t set, const void* pData); + void gen10_CmdPushDescriptorSetWithTemplateKHR(VkCommandBuffer commandBuffer, VkDescriptorUpdateTemplate descriptorUpdateTemplate, VkPipelineLayout layout, uint32_t set, const void* pData); + void gen11_CmdPushDescriptorSetWithTemplateKHR(VkCommandBuffer commandBuffer, VkDescriptorUpdateTemplate descriptorUpdateTemplate, VkPipelineLayout layout, uint32_t set, const void* pData); + void anv_GetBufferMemoryRequirements2(VkDevice device, const VkBufferMemoryRequirementsInfo2* pInfo, VkMemoryRequirements2* pMemoryRequirements); + void gen7_GetBufferMemoryRequirements2(VkDevice device, const VkBufferMemoryRequirementsInfo2* pInfo, VkMemoryRequirements2* pMemoryRequirements); + void gen75_GetBufferMemoryRequirements2(VkDevice device, const VkBufferMemoryRequirementsInfo2* pInfo, VkMemoryRequirements2* pMemoryRequirements); + void gen8_GetBufferMemoryRequirements2(VkDevice device, const VkBufferMemoryRequirementsInfo2* pInfo, VkMemoryRequirements2* pMemoryRequirements); + void gen9_GetBufferMemoryRequirements2(VkDevice device, const VkBufferMemoryRequirementsInfo2* pInfo, VkMemoryRequirements2* pMemoryRequirements); + void gen10_GetBufferMemoryRequirements2(VkDevice device, const VkBufferMemoryRequirementsInfo2* pInfo, VkMemoryRequirements2* pMemoryRequirements); + void gen11_GetBufferMemoryRequirements2(VkDevice device, const VkBufferMemoryRequirementsInfo2* pInfo, VkMemoryRequirements2* pMemoryRequirements); + void anv_GetImageMemoryRequirements2(VkDevice device, const VkImageMemoryRequirementsInfo2* pInfo, VkMemoryRequirements2* pMemoryRequirements); + void gen7_GetImageMemoryRequirements2(VkDevice device, const VkImageMemoryRequirementsInfo2* pInfo, VkMemoryRequirements2* pMemoryRequirements); + void gen75_GetImageMemoryRequirements2(VkDevice device, const VkImageMemoryRequirementsInfo2* pInfo, VkMemoryRequirements2* pMemoryRequirements); + void gen8_GetImageMemoryRequirements2(VkDevice device, const VkImageMemoryRequirementsInfo2* pInfo, VkMemoryRequirements2* pMemoryRequirements); + void gen9_GetImageMemoryRequirements2(VkDevice device, const VkImageMemoryRequirementsInfo2* pInfo, VkMemoryRequirements2* pMemoryRequirements); + void gen10_GetImageMemoryRequirements2(VkDevice device, const VkImageMemoryRequirementsInfo2* pInfo, VkMemoryRequirements2* pMemoryRequirements); + void gen11_GetImageMemoryRequirements2(VkDevice device, const VkImageMemoryRequirementsInfo2* pInfo, VkMemoryRequirements2* pMemoryRequirements); + void anv_GetImageSparseMemoryRequirements2(VkDevice device, const VkImageSparseMemoryRequirementsInfo2* pInfo, uint32_t* pSparseMemoryRequirementCount, VkSparseImageMemoryRequirements2* pSparseMemoryRequirements); + void gen7_GetImageSparseMemoryRequirements2(VkDevice device, const VkImageSparseMemoryRequirementsInfo2* pInfo, uint32_t* pSparseMemoryRequirementCount, VkSparseImageMemoryRequirements2* pSparseMemoryRequirements); + void gen75_GetImageSparseMemoryRequirements2(VkDevice device, const VkImageSparseMemoryRequirementsInfo2* pInfo, uint32_t* pSparseMemoryRequirementCount, VkSparseImageMemoryRequirements2* pSparseMemoryRequirements); + void gen8_GetImageSparseMemoryRequirements2(VkDevice device, const VkImageSparseMemoryRequirementsInfo2* pInfo, uint32_t* pSparseMemoryRequirementCount, VkSparseImageMemoryRequirements2* pSparseMemoryRequirements); + void gen9_GetImageSparseMemoryRequirements2(VkDevice device, const VkImageSparseMemoryRequirementsInfo2* pInfo, uint32_t* pSparseMemoryRequirementCount, VkSparseImageMemoryRequirements2* pSparseMemoryRequirements); + void gen10_GetImageSparseMemoryRequirements2(VkDevice device, const VkImageSparseMemoryRequirementsInfo2* pInfo, uint32_t* pSparseMemoryRequirementCount, VkSparseImageMemoryRequirements2* pSparseMemoryRequirements); + void gen11_GetImageSparseMemoryRequirements2(VkDevice device, const VkImageSparseMemoryRequirementsInfo2* pInfo, uint32_t* pSparseMemoryRequirementCount, VkSparseImageMemoryRequirements2* pSparseMemoryRequirements); + VkResult anv_CreateSamplerYcbcrConversion(VkDevice device, const VkSamplerYcbcrConversionCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSamplerYcbcrConversion* pYcbcrConversion); + VkResult gen7_CreateSamplerYcbcrConversion(VkDevice device, const VkSamplerYcbcrConversionCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSamplerYcbcrConversion* pYcbcrConversion); + VkResult gen75_CreateSamplerYcbcrConversion(VkDevice device, const VkSamplerYcbcrConversionCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSamplerYcbcrConversion* pYcbcrConversion); + VkResult gen8_CreateSamplerYcbcrConversion(VkDevice device, const VkSamplerYcbcrConversionCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSamplerYcbcrConversion* pYcbcrConversion); + VkResult gen9_CreateSamplerYcbcrConversion(VkDevice device, const VkSamplerYcbcrConversionCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSamplerYcbcrConversion* pYcbcrConversion); + VkResult gen10_CreateSamplerYcbcrConversion(VkDevice device, const VkSamplerYcbcrConversionCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSamplerYcbcrConversion* pYcbcrConversion); + VkResult gen11_CreateSamplerYcbcrConversion(VkDevice device, const VkSamplerYcbcrConversionCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkSamplerYcbcrConversion* pYcbcrConversion); + void anv_DestroySamplerYcbcrConversion(VkDevice device, VkSamplerYcbcrConversion ycbcrConversion, const VkAllocationCallbacks* pAllocator); + void gen7_DestroySamplerYcbcrConversion(VkDevice device, VkSamplerYcbcrConversion ycbcrConversion, const VkAllocationCallbacks* pAllocator); + void gen75_DestroySamplerYcbcrConversion(VkDevice device, VkSamplerYcbcrConversion ycbcrConversion, const VkAllocationCallbacks* pAllocator); + void gen8_DestroySamplerYcbcrConversion(VkDevice device, VkSamplerYcbcrConversion ycbcrConversion, const VkAllocationCallbacks* pAllocator); + void gen9_DestroySamplerYcbcrConversion(VkDevice device, VkSamplerYcbcrConversion ycbcrConversion, const VkAllocationCallbacks* pAllocator); + void gen10_DestroySamplerYcbcrConversion(VkDevice device, VkSamplerYcbcrConversion ycbcrConversion, const VkAllocationCallbacks* pAllocator); + void gen11_DestroySamplerYcbcrConversion(VkDevice device, VkSamplerYcbcrConversion ycbcrConversion, const VkAllocationCallbacks* pAllocator); + void anv_GetDeviceQueue2(VkDevice device, const VkDeviceQueueInfo2* pQueueInfo, VkQueue* pQueue); + void gen7_GetDeviceQueue2(VkDevice device, const VkDeviceQueueInfo2* pQueueInfo, VkQueue* pQueue); + void gen75_GetDeviceQueue2(VkDevice device, const VkDeviceQueueInfo2* pQueueInfo, VkQueue* pQueue); + void gen8_GetDeviceQueue2(VkDevice device, const VkDeviceQueueInfo2* pQueueInfo, VkQueue* pQueue); + void gen9_GetDeviceQueue2(VkDevice device, const VkDeviceQueueInfo2* pQueueInfo, VkQueue* pQueue); + void gen10_GetDeviceQueue2(VkDevice device, const VkDeviceQueueInfo2* pQueueInfo, VkQueue* pQueue); + void gen11_GetDeviceQueue2(VkDevice device, const VkDeviceQueueInfo2* pQueueInfo, VkQueue* pQueue); + void anv_GetDescriptorSetLayoutSupport(VkDevice device, const VkDescriptorSetLayoutCreateInfo* pCreateInfo, VkDescriptorSetLayoutSupport* pSupport); + void gen7_GetDescriptorSetLayoutSupport(VkDevice device, const VkDescriptorSetLayoutCreateInfo* pCreateInfo, VkDescriptorSetLayoutSupport* pSupport); + void gen75_GetDescriptorSetLayoutSupport(VkDevice device, const VkDescriptorSetLayoutCreateInfo* pCreateInfo, VkDescriptorSetLayoutSupport* pSupport); + void gen8_GetDescriptorSetLayoutSupport(VkDevice device, const VkDescriptorSetLayoutCreateInfo* pCreateInfo, VkDescriptorSetLayoutSupport* pSupport); + void gen9_GetDescriptorSetLayoutSupport(VkDevice device, const VkDescriptorSetLayoutCreateInfo* pCreateInfo, VkDescriptorSetLayoutSupport* pSupport); + void gen10_GetDescriptorSetLayoutSupport(VkDevice device, const VkDescriptorSetLayoutCreateInfo* pCreateInfo, VkDescriptorSetLayoutSupport* pSupport); + void gen11_GetDescriptorSetLayoutSupport(VkDevice device, const VkDescriptorSetLayoutCreateInfo* pCreateInfo, VkDescriptorSetLayoutSupport* pSupport); + #ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult anv_GetSwapchainGrallocUsageANDROID(VkDevice device, VkFormat format, VkImageUsageFlags imageUsage, int* grallocUsage); + VkResult gen7_GetSwapchainGrallocUsageANDROID(VkDevice device, VkFormat format, VkImageUsageFlags imageUsage, int* grallocUsage); + VkResult gen75_GetSwapchainGrallocUsageANDROID(VkDevice device, VkFormat format, VkImageUsageFlags imageUsage, int* grallocUsage); + VkResult gen8_GetSwapchainGrallocUsageANDROID(VkDevice device, VkFormat format, VkImageUsageFlags imageUsage, int* grallocUsage); + VkResult gen9_GetSwapchainGrallocUsageANDROID(VkDevice device, VkFormat format, VkImageUsageFlags imageUsage, int* grallocUsage); + VkResult gen10_GetSwapchainGrallocUsageANDROID(VkDevice device, VkFormat format, VkImageUsageFlags imageUsage, int* grallocUsage); + VkResult gen11_GetSwapchainGrallocUsageANDROID(VkDevice device, VkFormat format, VkImageUsageFlags imageUsage, int* grallocUsage); +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult anv_AcquireImageANDROID(VkDevice device, VkImage image, int nativeFenceFd, VkSemaphore semaphore, VkFence fence); + VkResult gen7_AcquireImageANDROID(VkDevice device, VkImage image, int nativeFenceFd, VkSemaphore semaphore, VkFence fence); + VkResult gen75_AcquireImageANDROID(VkDevice device, VkImage image, int nativeFenceFd, VkSemaphore semaphore, VkFence fence); + VkResult gen8_AcquireImageANDROID(VkDevice device, VkImage image, int nativeFenceFd, VkSemaphore semaphore, VkFence fence); + VkResult gen9_AcquireImageANDROID(VkDevice device, VkImage image, int nativeFenceFd, VkSemaphore semaphore, VkFence fence); + VkResult gen10_AcquireImageANDROID(VkDevice device, VkImage image, int nativeFenceFd, VkSemaphore semaphore, VkFence fence); + VkResult gen11_AcquireImageANDROID(VkDevice device, VkImage image, int nativeFenceFd, VkSemaphore semaphore, VkFence fence); +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult anv_QueueSignalReleaseImageANDROID(VkQueue queue, uint32_t waitSemaphoreCount, const VkSemaphore* pWaitSemaphores, VkImage image, int* pNativeFenceFd); + VkResult gen7_QueueSignalReleaseImageANDROID(VkQueue queue, uint32_t waitSemaphoreCount, const VkSemaphore* pWaitSemaphores, VkImage image, int* pNativeFenceFd); + VkResult gen75_QueueSignalReleaseImageANDROID(VkQueue queue, uint32_t waitSemaphoreCount, const VkSemaphore* pWaitSemaphores, VkImage image, int* pNativeFenceFd); + VkResult gen8_QueueSignalReleaseImageANDROID(VkQueue queue, uint32_t waitSemaphoreCount, const VkSemaphore* pWaitSemaphores, VkImage image, int* pNativeFenceFd); + VkResult gen9_QueueSignalReleaseImageANDROID(VkQueue queue, uint32_t waitSemaphoreCount, const VkSemaphore* pWaitSemaphores, VkImage image, int* pNativeFenceFd); + VkResult gen10_QueueSignalReleaseImageANDROID(VkQueue queue, uint32_t waitSemaphoreCount, const VkSemaphore* pWaitSemaphores, VkImage image, int* pNativeFenceFd); + VkResult gen11_QueueSignalReleaseImageANDROID(VkQueue queue, uint32_t waitSemaphoreCount, const VkSemaphore* pWaitSemaphores, VkImage image, int* pNativeFenceFd); +#endif // VK_USE_PLATFORM_ANDROID_KHR + VkResult anv_GetCalibratedTimestampsEXT(VkDevice device, uint32_t timestampCount, const VkCalibratedTimestampInfoEXT* pTimestampInfos, uint64_t* pTimestamps, uint64_t* pMaxDeviation); + VkResult gen7_GetCalibratedTimestampsEXT(VkDevice device, uint32_t timestampCount, const VkCalibratedTimestampInfoEXT* pTimestampInfos, uint64_t* pTimestamps, uint64_t* pMaxDeviation); + VkResult gen75_GetCalibratedTimestampsEXT(VkDevice device, uint32_t timestampCount, const VkCalibratedTimestampInfoEXT* pTimestampInfos, uint64_t* pTimestamps, uint64_t* pMaxDeviation); + VkResult gen8_GetCalibratedTimestampsEXT(VkDevice device, uint32_t timestampCount, const VkCalibratedTimestampInfoEXT* pTimestampInfos, uint64_t* pTimestamps, uint64_t* pMaxDeviation); + VkResult gen9_GetCalibratedTimestampsEXT(VkDevice device, uint32_t timestampCount, const VkCalibratedTimestampInfoEXT* pTimestampInfos, uint64_t* pTimestamps, uint64_t* pMaxDeviation); + VkResult gen10_GetCalibratedTimestampsEXT(VkDevice device, uint32_t timestampCount, const VkCalibratedTimestampInfoEXT* pTimestampInfos, uint64_t* pTimestamps, uint64_t* pMaxDeviation); + VkResult gen11_GetCalibratedTimestampsEXT(VkDevice device, uint32_t timestampCount, const VkCalibratedTimestampInfoEXT* pTimestampInfos, uint64_t* pTimestamps, uint64_t* pMaxDeviation); + VkResult anv_CreateRenderPass2KHR(VkDevice device, const VkRenderPassCreateInfo2KHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkRenderPass* pRenderPass); + VkResult gen7_CreateRenderPass2KHR(VkDevice device, const VkRenderPassCreateInfo2KHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkRenderPass* pRenderPass); + VkResult gen75_CreateRenderPass2KHR(VkDevice device, const VkRenderPassCreateInfo2KHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkRenderPass* pRenderPass); + VkResult gen8_CreateRenderPass2KHR(VkDevice device, const VkRenderPassCreateInfo2KHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkRenderPass* pRenderPass); + VkResult gen9_CreateRenderPass2KHR(VkDevice device, const VkRenderPassCreateInfo2KHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkRenderPass* pRenderPass); + VkResult gen10_CreateRenderPass2KHR(VkDevice device, const VkRenderPassCreateInfo2KHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkRenderPass* pRenderPass); + VkResult gen11_CreateRenderPass2KHR(VkDevice device, const VkRenderPassCreateInfo2KHR* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkRenderPass* pRenderPass); + void anv_CmdBeginRenderPass2KHR(VkCommandBuffer commandBuffer, const VkRenderPassBeginInfo* pRenderPassBegin, const VkSubpassBeginInfoKHR* pSubpassBeginInfo); + void gen7_CmdBeginRenderPass2KHR(VkCommandBuffer commandBuffer, const VkRenderPassBeginInfo* pRenderPassBegin, const VkSubpassBeginInfoKHR* pSubpassBeginInfo); + void gen75_CmdBeginRenderPass2KHR(VkCommandBuffer commandBuffer, const VkRenderPassBeginInfo* pRenderPassBegin, const VkSubpassBeginInfoKHR* pSubpassBeginInfo); + void gen8_CmdBeginRenderPass2KHR(VkCommandBuffer commandBuffer, const VkRenderPassBeginInfo* pRenderPassBegin, const VkSubpassBeginInfoKHR* pSubpassBeginInfo); + void gen9_CmdBeginRenderPass2KHR(VkCommandBuffer commandBuffer, const VkRenderPassBeginInfo* pRenderPassBegin, const VkSubpassBeginInfoKHR* pSubpassBeginInfo); + void gen10_CmdBeginRenderPass2KHR(VkCommandBuffer commandBuffer, const VkRenderPassBeginInfo* pRenderPassBegin, const VkSubpassBeginInfoKHR* pSubpassBeginInfo); + void gen11_CmdBeginRenderPass2KHR(VkCommandBuffer commandBuffer, const VkRenderPassBeginInfo* pRenderPassBegin, const VkSubpassBeginInfoKHR* pSubpassBeginInfo); + void anv_CmdNextSubpass2KHR(VkCommandBuffer commandBuffer, const VkSubpassBeginInfoKHR* pSubpassBeginInfo, const VkSubpassEndInfoKHR* pSubpassEndInfo); + void gen7_CmdNextSubpass2KHR(VkCommandBuffer commandBuffer, const VkSubpassBeginInfoKHR* pSubpassBeginInfo, const VkSubpassEndInfoKHR* pSubpassEndInfo); + void gen75_CmdNextSubpass2KHR(VkCommandBuffer commandBuffer, const VkSubpassBeginInfoKHR* pSubpassBeginInfo, const VkSubpassEndInfoKHR* pSubpassEndInfo); + void gen8_CmdNextSubpass2KHR(VkCommandBuffer commandBuffer, const VkSubpassBeginInfoKHR* pSubpassBeginInfo, const VkSubpassEndInfoKHR* pSubpassEndInfo); + void gen9_CmdNextSubpass2KHR(VkCommandBuffer commandBuffer, const VkSubpassBeginInfoKHR* pSubpassBeginInfo, const VkSubpassEndInfoKHR* pSubpassEndInfo); + void gen10_CmdNextSubpass2KHR(VkCommandBuffer commandBuffer, const VkSubpassBeginInfoKHR* pSubpassBeginInfo, const VkSubpassEndInfoKHR* pSubpassEndInfo); + void gen11_CmdNextSubpass2KHR(VkCommandBuffer commandBuffer, const VkSubpassBeginInfoKHR* pSubpassBeginInfo, const VkSubpassEndInfoKHR* pSubpassEndInfo); + void anv_CmdEndRenderPass2KHR(VkCommandBuffer commandBuffer, const VkSubpassEndInfoKHR* pSubpassEndInfo); + void gen7_CmdEndRenderPass2KHR(VkCommandBuffer commandBuffer, const VkSubpassEndInfoKHR* pSubpassEndInfo); + void gen75_CmdEndRenderPass2KHR(VkCommandBuffer commandBuffer, const VkSubpassEndInfoKHR* pSubpassEndInfo); + void gen8_CmdEndRenderPass2KHR(VkCommandBuffer commandBuffer, const VkSubpassEndInfoKHR* pSubpassEndInfo); + void gen9_CmdEndRenderPass2KHR(VkCommandBuffer commandBuffer, const VkSubpassEndInfoKHR* pSubpassEndInfo); + void gen10_CmdEndRenderPass2KHR(VkCommandBuffer commandBuffer, const VkSubpassEndInfoKHR* pSubpassEndInfo); + void gen11_CmdEndRenderPass2KHR(VkCommandBuffer commandBuffer, const VkSubpassEndInfoKHR* pSubpassEndInfo); +#ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult anv_GetAndroidHardwareBufferPropertiesANDROID(VkDevice device, const struct AHardwareBuffer* buffer, VkAndroidHardwareBufferPropertiesANDROID* pProperties); + VkResult gen7_GetAndroidHardwareBufferPropertiesANDROID(VkDevice device, const struct AHardwareBuffer* buffer, VkAndroidHardwareBufferPropertiesANDROID* pProperties); + VkResult gen75_GetAndroidHardwareBufferPropertiesANDROID(VkDevice device, const struct AHardwareBuffer* buffer, VkAndroidHardwareBufferPropertiesANDROID* pProperties); + VkResult gen8_GetAndroidHardwareBufferPropertiesANDROID(VkDevice device, const struct AHardwareBuffer* buffer, VkAndroidHardwareBufferPropertiesANDROID* pProperties); + VkResult gen9_GetAndroidHardwareBufferPropertiesANDROID(VkDevice device, const struct AHardwareBuffer* buffer, VkAndroidHardwareBufferPropertiesANDROID* pProperties); + VkResult gen10_GetAndroidHardwareBufferPropertiesANDROID(VkDevice device, const struct AHardwareBuffer* buffer, VkAndroidHardwareBufferPropertiesANDROID* pProperties); + VkResult gen11_GetAndroidHardwareBufferPropertiesANDROID(VkDevice device, const struct AHardwareBuffer* buffer, VkAndroidHardwareBufferPropertiesANDROID* pProperties); +#endif // VK_USE_PLATFORM_ANDROID_KHR +#ifdef VK_USE_PLATFORM_ANDROID_KHR + VkResult anv_GetMemoryAndroidHardwareBufferANDROID(VkDevice device, const VkMemoryGetAndroidHardwareBufferInfoANDROID* pInfo, struct AHardwareBuffer** pBuffer); + VkResult gen7_GetMemoryAndroidHardwareBufferANDROID(VkDevice device, const VkMemoryGetAndroidHardwareBufferInfoANDROID* pInfo, struct AHardwareBuffer** pBuffer); + VkResult gen75_GetMemoryAndroidHardwareBufferANDROID(VkDevice device, const VkMemoryGetAndroidHardwareBufferInfoANDROID* pInfo, struct AHardwareBuffer** pBuffer); + VkResult gen8_GetMemoryAndroidHardwareBufferANDROID(VkDevice device, const VkMemoryGetAndroidHardwareBufferInfoANDROID* pInfo, struct AHardwareBuffer** pBuffer); + VkResult gen9_GetMemoryAndroidHardwareBufferANDROID(VkDevice device, const VkMemoryGetAndroidHardwareBufferInfoANDROID* pInfo, struct AHardwareBuffer** pBuffer); + VkResult gen10_GetMemoryAndroidHardwareBufferANDROID(VkDevice device, const VkMemoryGetAndroidHardwareBufferInfoANDROID* pInfo, struct AHardwareBuffer** pBuffer); + VkResult gen11_GetMemoryAndroidHardwareBufferANDROID(VkDevice device, const VkMemoryGetAndroidHardwareBufferInfoANDROID* pInfo, struct AHardwareBuffer** pBuffer); +#endif // VK_USE_PLATFORM_ANDROID_KHR + void anv_CmdDrawIndirectCountKHR(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkBuffer countBuffer, VkDeviceSize countBufferOffset, uint32_t maxDrawCount, uint32_t stride); + void gen7_CmdDrawIndirectCountKHR(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkBuffer countBuffer, VkDeviceSize countBufferOffset, uint32_t maxDrawCount, uint32_t stride); + void gen75_CmdDrawIndirectCountKHR(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkBuffer countBuffer, VkDeviceSize countBufferOffset, uint32_t maxDrawCount, uint32_t stride); + void gen8_CmdDrawIndirectCountKHR(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkBuffer countBuffer, VkDeviceSize countBufferOffset, uint32_t maxDrawCount, uint32_t stride); + void gen9_CmdDrawIndirectCountKHR(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkBuffer countBuffer, VkDeviceSize countBufferOffset, uint32_t maxDrawCount, uint32_t stride); + void gen10_CmdDrawIndirectCountKHR(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkBuffer countBuffer, VkDeviceSize countBufferOffset, uint32_t maxDrawCount, uint32_t stride); + void gen11_CmdDrawIndirectCountKHR(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkBuffer countBuffer, VkDeviceSize countBufferOffset, uint32_t maxDrawCount, uint32_t stride); + void anv_CmdDrawIndexedIndirectCountKHR(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkBuffer countBuffer, VkDeviceSize countBufferOffset, uint32_t maxDrawCount, uint32_t stride); + void gen7_CmdDrawIndexedIndirectCountKHR(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkBuffer countBuffer, VkDeviceSize countBufferOffset, uint32_t maxDrawCount, uint32_t stride); + void gen75_CmdDrawIndexedIndirectCountKHR(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkBuffer countBuffer, VkDeviceSize countBufferOffset, uint32_t maxDrawCount, uint32_t stride); + void gen8_CmdDrawIndexedIndirectCountKHR(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkBuffer countBuffer, VkDeviceSize countBufferOffset, uint32_t maxDrawCount, uint32_t stride); + void gen9_CmdDrawIndexedIndirectCountKHR(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkBuffer countBuffer, VkDeviceSize countBufferOffset, uint32_t maxDrawCount, uint32_t stride); + void gen10_CmdDrawIndexedIndirectCountKHR(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkBuffer countBuffer, VkDeviceSize countBufferOffset, uint32_t maxDrawCount, uint32_t stride); + void gen11_CmdDrawIndexedIndirectCountKHR(VkCommandBuffer commandBuffer, VkBuffer buffer, VkDeviceSize offset, VkBuffer countBuffer, VkDeviceSize countBufferOffset, uint32_t maxDrawCount, uint32_t stride); + void anv_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer, uint32_t firstBinding, uint32_t bindingCount, const VkBuffer* pBuffers, const VkDeviceSize* pOffsets, const VkDeviceSize* pSizes); + void gen7_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer, uint32_t firstBinding, uint32_t bindingCount, const VkBuffer* pBuffers, const VkDeviceSize* pOffsets, const VkDeviceSize* pSizes); + void gen75_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer, uint32_t firstBinding, uint32_t bindingCount, const VkBuffer* pBuffers, const VkDeviceSize* pOffsets, const VkDeviceSize* pSizes); + void gen8_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer, uint32_t firstBinding, uint32_t bindingCount, const VkBuffer* pBuffers, const VkDeviceSize* pOffsets, const VkDeviceSize* pSizes); + void gen9_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer, uint32_t firstBinding, uint32_t bindingCount, const VkBuffer* pBuffers, const VkDeviceSize* pOffsets, const VkDeviceSize* pSizes); + void gen10_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer, uint32_t firstBinding, uint32_t bindingCount, const VkBuffer* pBuffers, const VkDeviceSize* pOffsets, const VkDeviceSize* pSizes); + void gen11_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer, uint32_t firstBinding, uint32_t bindingCount, const VkBuffer* pBuffers, const VkDeviceSize* pOffsets, const VkDeviceSize* pSizes); + void anv_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstCounterBuffer, uint32_t counterBufferCount, const VkBuffer* pCounterBuffers, const VkDeviceSize* pCounterBufferOffsets); + void gen7_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstCounterBuffer, uint32_t counterBufferCount, const VkBuffer* pCounterBuffers, const VkDeviceSize* pCounterBufferOffsets); + void gen75_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstCounterBuffer, uint32_t counterBufferCount, const VkBuffer* pCounterBuffers, const VkDeviceSize* pCounterBufferOffsets); + void gen8_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstCounterBuffer, uint32_t counterBufferCount, const VkBuffer* pCounterBuffers, const VkDeviceSize* pCounterBufferOffsets); + void gen9_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstCounterBuffer, uint32_t counterBufferCount, const VkBuffer* pCounterBuffers, const VkDeviceSize* pCounterBufferOffsets); + void gen10_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstCounterBuffer, uint32_t counterBufferCount, const VkBuffer* pCounterBuffers, const VkDeviceSize* pCounterBufferOffsets); + void gen11_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstCounterBuffer, uint32_t counterBufferCount, const VkBuffer* pCounterBuffers, const VkDeviceSize* pCounterBufferOffsets); + void anv_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstCounterBuffer, uint32_t counterBufferCount, const VkBuffer* pCounterBuffers, const VkDeviceSize* pCounterBufferOffsets); + void gen7_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstCounterBuffer, uint32_t counterBufferCount, const VkBuffer* pCounterBuffers, const VkDeviceSize* pCounterBufferOffsets); + void gen75_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstCounterBuffer, uint32_t counterBufferCount, const VkBuffer* pCounterBuffers, const VkDeviceSize* pCounterBufferOffsets); + void gen8_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstCounterBuffer, uint32_t counterBufferCount, const VkBuffer* pCounterBuffers, const VkDeviceSize* pCounterBufferOffsets); + void gen9_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstCounterBuffer, uint32_t counterBufferCount, const VkBuffer* pCounterBuffers, const VkDeviceSize* pCounterBufferOffsets); + void gen10_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstCounterBuffer, uint32_t counterBufferCount, const VkBuffer* pCounterBuffers, const VkDeviceSize* pCounterBufferOffsets); + void gen11_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer, uint32_t firstCounterBuffer, uint32_t counterBufferCount, const VkBuffer* pCounterBuffers, const VkDeviceSize* pCounterBufferOffsets); + void anv_CmdBeginQueryIndexedEXT(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, VkQueryControlFlags flags, uint32_t index); + void gen7_CmdBeginQueryIndexedEXT(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, VkQueryControlFlags flags, uint32_t index); + void gen75_CmdBeginQueryIndexedEXT(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, VkQueryControlFlags flags, uint32_t index); + void gen8_CmdBeginQueryIndexedEXT(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, VkQueryControlFlags flags, uint32_t index); + void gen9_CmdBeginQueryIndexedEXT(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, VkQueryControlFlags flags, uint32_t index); + void gen10_CmdBeginQueryIndexedEXT(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, VkQueryControlFlags flags, uint32_t index); + void gen11_CmdBeginQueryIndexedEXT(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, VkQueryControlFlags flags, uint32_t index); + void anv_CmdEndQueryIndexedEXT(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, uint32_t index); + void gen7_CmdEndQueryIndexedEXT(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, uint32_t index); + void gen75_CmdEndQueryIndexedEXT(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, uint32_t index); + void gen8_CmdEndQueryIndexedEXT(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, uint32_t index); + void gen9_CmdEndQueryIndexedEXT(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, uint32_t index); + void gen10_CmdEndQueryIndexedEXT(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, uint32_t index); + void gen11_CmdEndQueryIndexedEXT(VkCommandBuffer commandBuffer, VkQueryPool queryPool, uint32_t query, uint32_t index); + void anv_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer, uint32_t instanceCount, uint32_t firstInstance, VkBuffer counterBuffer, VkDeviceSize counterBufferOffset, uint32_t counterOffset, uint32_t vertexStride); + void gen7_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer, uint32_t instanceCount, uint32_t firstInstance, VkBuffer counterBuffer, VkDeviceSize counterBufferOffset, uint32_t counterOffset, uint32_t vertexStride); + void gen75_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer, uint32_t instanceCount, uint32_t firstInstance, VkBuffer counterBuffer, VkDeviceSize counterBufferOffset, uint32_t counterOffset, uint32_t vertexStride); + void gen8_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer, uint32_t instanceCount, uint32_t firstInstance, VkBuffer counterBuffer, VkDeviceSize counterBufferOffset, uint32_t counterOffset, uint32_t vertexStride); + void gen9_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer, uint32_t instanceCount, uint32_t firstInstance, VkBuffer counterBuffer, VkDeviceSize counterBufferOffset, uint32_t counterOffset, uint32_t vertexStride); + void gen10_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer, uint32_t instanceCount, uint32_t firstInstance, VkBuffer counterBuffer, VkDeviceSize counterBufferOffset, uint32_t counterOffset, uint32_t vertexStride); + void gen11_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer, uint32_t instanceCount, uint32_t firstInstance, VkBuffer counterBuffer, VkDeviceSize counterBufferOffset, uint32_t counterOffset, uint32_t vertexStride); + VkResult anv_CreateDmaBufImageINTEL(VkDevice device, const VkDmaBufImageCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDeviceMemory* pMem, VkImage* pImage); + VkResult gen7_CreateDmaBufImageINTEL(VkDevice device, const VkDmaBufImageCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDeviceMemory* pMem, VkImage* pImage); + VkResult gen75_CreateDmaBufImageINTEL(VkDevice device, const VkDmaBufImageCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDeviceMemory* pMem, VkImage* pImage); + VkResult gen8_CreateDmaBufImageINTEL(VkDevice device, const VkDmaBufImageCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDeviceMemory* pMem, VkImage* pImage); + VkResult gen9_CreateDmaBufImageINTEL(VkDevice device, const VkDmaBufImageCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDeviceMemory* pMem, VkImage* pImage); + VkResult gen10_CreateDmaBufImageINTEL(VkDevice device, const VkDmaBufImageCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDeviceMemory* pMem, VkImage* pImage); + VkResult gen11_CreateDmaBufImageINTEL(VkDevice device, const VkDmaBufImageCreateInfo* pCreateInfo, const VkAllocationCallbacks* pAllocator, VkDeviceMemory* pMem, VkImage* pImage); diff --git a/prebuilt-intermediates/vulkan/anv_extensions.c b/prebuilt-intermediates/vulkan/anv_extensions.c new file mode 100644 index 00000000000..493ee57e4e4 --- /dev/null +++ b/prebuilt-intermediates/vulkan/anv_extensions.c @@ -0,0 +1,251 @@ +/* + * Copyright 2017 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + +#include "anv_private.h" + +#include "vk_util.h" + +/* Convert the VK_USE_PLATFORM_* defines to booleans */ +#ifdef VK_USE_PLATFORM_ANDROID_KHR +# undef VK_USE_PLATFORM_ANDROID_KHR +# define VK_USE_PLATFORM_ANDROID_KHR true +#else +# define VK_USE_PLATFORM_ANDROID_KHR false +#endif +#ifdef VK_USE_PLATFORM_WAYLAND_KHR +# undef VK_USE_PLATFORM_WAYLAND_KHR +# define VK_USE_PLATFORM_WAYLAND_KHR true +#else +# define VK_USE_PLATFORM_WAYLAND_KHR false +#endif +#ifdef VK_USE_PLATFORM_XCB_KHR +# undef VK_USE_PLATFORM_XCB_KHR +# define VK_USE_PLATFORM_XCB_KHR true +#else +# define VK_USE_PLATFORM_XCB_KHR false +#endif +#ifdef VK_USE_PLATFORM_XLIB_KHR +# undef VK_USE_PLATFORM_XLIB_KHR +# define VK_USE_PLATFORM_XLIB_KHR true +#else +# define VK_USE_PLATFORM_XLIB_KHR false +#endif +#ifdef VK_USE_PLATFORM_DISPLAY_KHR +# undef VK_USE_PLATFORM_DISPLAY_KHR +# define VK_USE_PLATFORM_DISPLAY_KHR true +#else +# define VK_USE_PLATFORM_DISPLAY_KHR false +#endif +#ifdef VK_USE_PLATFORM_XLIB_XRANDR_EXT +# undef VK_USE_PLATFORM_XLIB_XRANDR_EXT +# define VK_USE_PLATFORM_XLIB_XRANDR_EXT true +#else +# define VK_USE_PLATFORM_XLIB_XRANDR_EXT false +#endif + +/* And ANDROID too */ +#ifdef ANDROID +# undef ANDROID +# define ANDROID true +#else +# define ANDROID false +#endif + +#define ANV_HAS_SURFACE (VK_USE_PLATFORM_WAYLAND_KHR || VK_USE_PLATFORM_XCB_KHR || VK_USE_PLATFORM_XLIB_KHR || VK_USE_PLATFORM_DISPLAY_KHR) + +static const uint32_t MAX_API_VERSION = VK_MAKE_VERSION(1, 1, 96); + +VkResult anv_EnumerateInstanceVersion( + uint32_t* pApiVersion) +{ + *pApiVersion = MAX_API_VERSION; + return VK_SUCCESS; +} + +const VkExtensionProperties anv_instance_extensions[ANV_INSTANCE_EXTENSION_COUNT] = { + {"VK_KHR_device_group_creation", 1}, + {"VK_KHR_display", 23}, + {"VK_KHR_external_fence_capabilities", 1}, + {"VK_KHR_external_memory_capabilities", 1}, + {"VK_KHR_external_semaphore_capabilities", 1}, + {"VK_KHR_get_display_properties2", 1}, + {"VK_KHR_get_physical_device_properties2", 1}, + {"VK_KHR_get_surface_capabilities2", 1}, + {"VK_KHR_surface", 25}, + {"VK_KHR_wayland_surface", 6}, + {"VK_KHR_xcb_surface", 6}, + {"VK_KHR_xlib_surface", 6}, + {"VK_EXT_acquire_xlib_display", 1}, + {"VK_EXT_debug_report", 8}, + {"VK_EXT_direct_mode_display", 1}, + {"VK_EXT_display_surface_counter", 1}, +}; + +const struct anv_instance_extension_table anv_instance_extensions_supported = { + .KHR_device_group_creation = true, + .KHR_display = VK_USE_PLATFORM_DISPLAY_KHR, + .KHR_external_fence_capabilities = true, + .KHR_external_memory_capabilities = true, + .KHR_external_semaphore_capabilities = true, + .KHR_get_display_properties2 = VK_USE_PLATFORM_DISPLAY_KHR, + .KHR_get_physical_device_properties2 = true, + .KHR_get_surface_capabilities2 = ANV_HAS_SURFACE, + .KHR_surface = ANV_HAS_SURFACE, + .KHR_wayland_surface = VK_USE_PLATFORM_WAYLAND_KHR, + .KHR_xcb_surface = VK_USE_PLATFORM_XCB_KHR, + .KHR_xlib_surface = VK_USE_PLATFORM_XLIB_KHR, + .EXT_acquire_xlib_display = VK_USE_PLATFORM_XLIB_XRANDR_EXT, + .EXT_debug_report = true, + .EXT_direct_mode_display = VK_USE_PLATFORM_DISPLAY_KHR, + .EXT_display_surface_counter = VK_USE_PLATFORM_DISPLAY_KHR, +}; + +uint32_t +anv_physical_device_api_version(struct anv_physical_device *device) +{ + uint32_t version = 0; + + uint32_t override = vk_get_version_override(); + if (override) + return MIN2(override, MAX_API_VERSION); + + if (!(true)) + return version; + version = VK_MAKE_VERSION(1, 0, 96); + + if (!(device->has_syncobj_wait)) + return version; + version = VK_MAKE_VERSION(1, 1, 96); + + return version; +} + +const VkExtensionProperties anv_device_extensions[ANV_DEVICE_EXTENSION_COUNT] = { + {"VK_ANDROID_external_memory_android_hardware_buffer", 3}, + {"VK_ANDROID_native_buffer", 5}, + {"VK_KHR_8bit_storage", 1}, + {"VK_KHR_16bit_storage", 1}, + {"VK_KHR_bind_memory2", 1}, + {"VK_KHR_create_renderpass2", 1}, + {"VK_KHR_dedicated_allocation", 1}, + {"VK_KHR_depth_stencil_resolve", 1}, + {"VK_KHR_descriptor_update_template", 1}, + {"VK_KHR_device_group", 1}, + {"VK_KHR_draw_indirect_count", 1}, + {"VK_KHR_driver_properties", 1}, + {"VK_KHR_external_fence", 1}, + {"VK_KHR_external_fence_fd", 1}, + {"VK_KHR_external_memory", 1}, + {"VK_KHR_external_memory_fd", 1}, + {"VK_KHR_external_semaphore", 1}, + {"VK_KHR_external_semaphore_fd", 1}, + {"VK_KHR_get_memory_requirements2", 1}, + {"VK_KHR_image_format_list", 1}, + {"VK_KHR_incremental_present", 1}, + {"VK_KHR_maintenance1", 1}, + {"VK_KHR_maintenance2", 1}, + {"VK_KHR_maintenance3", 1}, + {"VK_KHR_multiview", 1}, + {"VK_KHR_push_descriptor", 1}, + {"VK_KHR_relaxed_block_layout", 1}, + {"VK_KHR_sampler_mirror_clamp_to_edge", 1}, + {"VK_KHR_sampler_ycbcr_conversion", 1}, + {"VK_KHR_shader_draw_parameters", 1}, + {"VK_KHR_storage_buffer_storage_class", 1}, + {"VK_KHR_swapchain", 68}, + {"VK_KHR_variable_pointers", 1}, + {"VK_EXT_calibrated_timestamps", 1}, + {"VK_EXT_conditional_rendering", 1}, + {"VK_EXT_display_control", 1}, + {"VK_EXT_external_memory_dma_buf", 1}, + {"VK_EXT_global_priority", 1}, + {"VK_EXT_pci_bus_info", 2}, + {"VK_EXT_post_depth_coverage", 1}, + {"VK_EXT_queue_family_foreign", 1}, + {"VK_EXT_sampler_filter_minmax", 1}, + {"VK_EXT_scalar_block_layout", 1}, + {"VK_EXT_shader_viewport_index_layer", 1}, + {"VK_EXT_shader_stencil_export", 1}, + {"VK_EXT_transform_feedback", 1}, + {"VK_EXT_vertex_attribute_divisor", 3}, + {"VK_GOOGLE_decorate_string", 1}, + {"VK_GOOGLE_hlsl_functionality1", 1}, +}; + +void +anv_physical_device_get_supported_extensions(const struct anv_physical_device *device, + struct anv_device_extension_table *extensions) +{ + *extensions = (struct anv_device_extension_table) { + .ANDROID_external_memory_android_hardware_buffer = ANDROID, + .ANDROID_native_buffer = ANDROID, + .KHR_8bit_storage = device->info.gen >= 8, + .KHR_16bit_storage = device->info.gen >= 8, + .KHR_bind_memory2 = true, + .KHR_create_renderpass2 = true, + .KHR_dedicated_allocation = true, + .KHR_depth_stencil_resolve = true, + .KHR_descriptor_update_template = true, + .KHR_device_group = true, + .KHR_draw_indirect_count = true, + .KHR_driver_properties = true, + .KHR_external_fence = device->has_syncobj_wait, + .KHR_external_fence_fd = device->has_syncobj_wait, + .KHR_external_memory = true, + .KHR_external_memory_fd = true, + .KHR_external_semaphore = true, + .KHR_external_semaphore_fd = true, + .KHR_get_memory_requirements2 = true, + .KHR_image_format_list = true, + .KHR_incremental_present = ANV_HAS_SURFACE, + .KHR_maintenance1 = true, + .KHR_maintenance2 = true, + .KHR_maintenance3 = true, + .KHR_multiview = true, + .KHR_push_descriptor = true, + .KHR_relaxed_block_layout = true, + .KHR_sampler_mirror_clamp_to_edge = true, + .KHR_sampler_ycbcr_conversion = true, + .KHR_shader_draw_parameters = true, + .KHR_storage_buffer_storage_class = true, + .KHR_swapchain = ANV_HAS_SURFACE, + .KHR_variable_pointers = true, + .EXT_calibrated_timestamps = true, + .EXT_conditional_rendering = device->info.gen >= 8 || device->info.is_haswell, + .EXT_display_control = VK_USE_PLATFORM_DISPLAY_KHR, + .EXT_external_memory_dma_buf = true, + .EXT_global_priority = device->has_context_priority, + .EXT_pci_bus_info = true, + .EXT_post_depth_coverage = device->info.gen >= 9, + .EXT_queue_family_foreign = ANDROID, + .EXT_sampler_filter_minmax = device->info.gen >= 9, + .EXT_scalar_block_layout = !ANDROID, + .EXT_shader_viewport_index_layer = true, + .EXT_shader_stencil_export = device->info.gen >= 9, + .EXT_transform_feedback = true, + .EXT_vertex_attribute_divisor = true, + .GOOGLE_decorate_string = !ANDROID, + .GOOGLE_hlsl_functionality1 = !ANDROID, + }; +} diff --git a/prebuilt-intermediates/vulkan/anv_extensions.h b/prebuilt-intermediates/vulkan/anv_extensions.h new file mode 100644 index 00000000000..e9ccca8aeb7 --- /dev/null +++ b/prebuilt-intermediates/vulkan/anv_extensions.h @@ -0,0 +1,129 @@ +/* + * Copyright 2017 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the + * "Software"), to deal in the Software without restriction, including + * without limitation the rights to use, copy, modify, merge, publish, + * distribute, sub license, and/or sell copies of the Software, and to + * permit persons to whom the Software is furnished to do so, subject to + * the following conditions: + * + * The above copyright notice and this permission notice (including the + * next paragraph) shall be included in all copies or substantial portions + * of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS + * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF + * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. + * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR + * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, + * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE + * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + */ + + +#ifndef ANV_EXTENSIONS_H +#define ANV_EXTENSIONS_H + +#include "stdbool.h" + +#define ANV_INSTANCE_EXTENSION_COUNT 16 + +extern const VkExtensionProperties anv_instance_extensions[]; + +struct anv_instance_extension_table { + union { + bool extensions[ANV_INSTANCE_EXTENSION_COUNT]; + struct { + bool KHR_device_group_creation; + bool KHR_display; + bool KHR_external_fence_capabilities; + bool KHR_external_memory_capabilities; + bool KHR_external_semaphore_capabilities; + bool KHR_get_display_properties2; + bool KHR_get_physical_device_properties2; + bool KHR_get_surface_capabilities2; + bool KHR_surface; + bool KHR_wayland_surface; + bool KHR_xcb_surface; + bool KHR_xlib_surface; + bool EXT_acquire_xlib_display; + bool EXT_debug_report; + bool EXT_direct_mode_display; + bool EXT_display_surface_counter; + }; + }; +}; + +extern const struct anv_instance_extension_table anv_instance_extensions_supported; + + +#define ANV_DEVICE_EXTENSION_COUNT 49 + +extern const VkExtensionProperties anv_device_extensions[]; + +struct anv_device_extension_table { + union { + bool extensions[ANV_DEVICE_EXTENSION_COUNT]; + struct { + bool ANDROID_external_memory_android_hardware_buffer; + bool ANDROID_native_buffer; + bool KHR_8bit_storage; + bool KHR_16bit_storage; + bool KHR_bind_memory2; + bool KHR_create_renderpass2; + bool KHR_dedicated_allocation; + bool KHR_depth_stencil_resolve; + bool KHR_descriptor_update_template; + bool KHR_device_group; + bool KHR_draw_indirect_count; + bool KHR_driver_properties; + bool KHR_external_fence; + bool KHR_external_fence_fd; + bool KHR_external_memory; + bool KHR_external_memory_fd; + bool KHR_external_semaphore; + bool KHR_external_semaphore_fd; + bool KHR_get_memory_requirements2; + bool KHR_image_format_list; + bool KHR_incremental_present; + bool KHR_maintenance1; + bool KHR_maintenance2; + bool KHR_maintenance3; + bool KHR_multiview; + bool KHR_push_descriptor; + bool KHR_relaxed_block_layout; + bool KHR_sampler_mirror_clamp_to_edge; + bool KHR_sampler_ycbcr_conversion; + bool KHR_shader_draw_parameters; + bool KHR_storage_buffer_storage_class; + bool KHR_swapchain; + bool KHR_variable_pointers; + bool EXT_calibrated_timestamps; + bool EXT_conditional_rendering; + bool EXT_display_control; + bool EXT_external_memory_dma_buf; + bool EXT_global_priority; + bool EXT_pci_bus_info; + bool EXT_post_depth_coverage; + bool EXT_queue_family_foreign; + bool EXT_sampler_filter_minmax; + bool EXT_scalar_block_layout; + bool EXT_shader_viewport_index_layer; + bool EXT_shader_stencil_export; + bool EXT_transform_feedback; + bool EXT_vertex_attribute_divisor; + bool GOOGLE_decorate_string; + bool GOOGLE_hlsl_functionality1; + }; + }; +}; + +struct anv_physical_device; + +void +anv_physical_device_get_supported_extensions(const struct anv_physical_device *device, + struct anv_device_extension_table *extensions); + +#endif /* ANV_EXTENSIONS_H */ diff --git a/src/intel/Android.vulkan.mk b/src/intel/Android.vulkan.mk index 73586803552..e6d9fc73c0c 100644 --- a/src/intel/Android.vulkan.mk +++ b/src/intel/Android.vulkan.mk @@ -19,6 +19,7 @@ # DEALINGS IN THE SOFTWARE. LOCAL_PATH := $(call my-dir) +prebuilt_intermediates := $(MESA_TOP)/prebuilt-intermediates include $(CLEAR_VARS) include $(LOCAL_PATH)/Makefile.sources @@ -79,21 +80,27 @@ $(intermediates)/vulkan/dummy.c: @echo "Gen Dummy: $(PRIVATE_MODULE) <= $(notdir $(@))" $(hide) touch $@ -$(intermediates)/vulkan/anv_entrypoints.h: $(intermediates)/vulkan/dummy.c \ +#$(intermediates)/vulkan/anv_entrypoints.h: $(intermediates)/vulkan/dummy.c \ $(ANV_ENTRYPOINTS_GEN_SCRIPT) \ $(ANV_EXTENSIONS_SCRIPT) \ $(VULKAN_API_XML) - $(MESA_PYTHON2) $(ANV_ENTRYPOINTS_GEN_SCRIPT) \ +# $(MESA_PYTHON2) $(ANV_ENTRYPOINTS_GEN_SCRIPT) \ --outdir $(dir $@) \ --xml $(VULKAN_API_XML) +$(intermediates)/vulkan/anv_entrypoints.h: $(prebuilt_intermediates)/vulkan/anv_entrypoints.h + @mkdir -p $(dir $@) + @cp -f $< $@ -$(intermediates)/vulkan/anv_extensions.h: $(ANV_ENTRYPOINTS_GEN_SCRIPT) \ +#$(intermediates)/vulkan/anv_extensions.h: $(ANV_ENTRYPOINTS_GEN_SCRIPT) \ $(ANV_EXTENSIONS_SCRIPT) \ $(VULKAN_API_XML) - @mkdir -p $(dir $@) - $(MESA_PYTHON2) $(ANV_EXTENSIONS_GEN_SCRIPT) \ +# @mkdir -p $(dir $@) +# $(MESA_PYTHON2) $(ANV_EXTENSIONS_GEN_SCRIPT) \ --xml $(VULKAN_API_XML) \ --out-h $@ +$(intermediates)/vulkan/anv_extensions.h: $(prebuilt_intermediates)/vulkan/anv_extensions.h + @mkdir -p $(dir $@) + @cp -f $< $@ LOCAL_EXPORT_C_INCLUDE_DIRS := \ $(intermediates) @@ -272,22 +279,31 @@ LOCAL_WHOLE_STATIC_LIBRARIES := \ LOCAL_GENERATED_SOURCES += $(intermediates)/vulkan/anv_entrypoints.c LOCAL_GENERATED_SOURCES += $(intermediates)/vulkan/anv_extensions.c -$(intermediates)/vulkan/anv_entrypoints.c: $(ANV_ENTRYPOINTS_GEN_SCRIPT) \ +#$(intermediates)/vulkan/anv_entrypoints.c: $(ANV_ENTRYPOINTS_GEN_SCRIPT) \ $(ANV_EXTENSIONS_SCRIPT) \ $(VULKAN_API_XML) - @mkdir -p $(dir $@) - $(MESA_PYTHON2) $(ANV_ENTRYPOINTS_GEN_SCRIPT) \ +# @mkdir -p $(dir $@) +# $(MESA_PYTHON2) $(ANV_ENTRYPOINTS_GEN_SCRIPT) \ --xml $(VULKAN_API_XML) \ --outdir $(dir $@) -$(intermediates)/vulkan/anv_extensions.c: $(ANV_EXTENSIONS_GEN_SCRIPT) \ +$(intermediates)/vulkan/anv_entrypoints.c: $(prebuilt_intermediates)/vulkan/anv_entrypoints.c + @mkdir -p $(dir $@) + @cp -f $< $@ + + +#$(intermediates)/vulkan/anv_extensions.c: $(ANV_EXTENSIONS_GEN_SCRIPT) \ $(ANV_EXTENSIONS_SCRIPT) \ $(VULKAN_API_XML) - @mkdir -p $(dir $@) - $(MESA_PYTHON2) $(ANV_EXTENSIONS_GEN_SCRIPT) \ +# @mkdir -p $(dir $@) +# $(MESA_PYTHON2) $(ANV_EXTENSIONS_GEN_SCRIPT) \ --xml $(VULKAN_API_XML) \ --out-c $@ +$(intermediates)/vulkan/anv_extensions.c: $(prebuilt_intermediates)/vulkan/anv_extensions.c + @mkdir -p $(dir $@) + @cp -f $< $@ + LOCAL_SHARED_LIBRARIES := $(ANV_SHARED_LIBRARIES) LOCAL_HEADER_LIBRARIES += $(VULKAN_COMMON_HEADER_LIBRARIES) diff --git a/src/vulkan/Android.mk b/src/vulkan/Android.mk index 99dd3f56313..7588d468551 100644 --- a/src/vulkan/Android.mk +++ b/src/vulkan/Android.mk @@ -34,6 +34,7 @@ LOCAL_MODULE := libmesa_vulkan_util LOCAL_MODULE_CLASS := STATIC_LIBRARIES intermediates := $(call local-generated-sources-dir) +prebuilt_intermediates := $(MESA_TOP)/prebuilt-intermediates LOCAL_C_INCLUDES := \ $(MESA_TOP)/include/vulkan \ @@ -65,6 +66,13 @@ $(LOCAL_GENERATED_SOURCES): $(MESA_TOP)/src/vulkan/util/gen_enum_to_str.py \ LOCAL_EXPORT_C_INCLUDE_DIRS := \ $(intermediates) +$(intermediates)/util/vk_enum_to_str.c: $(prebuilt_intermediates)/util/vk_enum_to_str.c + @mkdir -p $(dir $@) + @cp -f $< $@ +$(intermediates)/util/vk_enum_to_str.h: $(prebuilt_intermediates)/util/vk_enum_to_str.h + @mkdir -p $(dir $@) + @cp -f $< $@ + ifeq ($(filter $(MESA_ANDROID_MAJOR_VERSION), 4 5 6 7),) LOCAL_SHARED_LIBRARIES += libnativewindow endif From 525b9b6389b324a39161ee309fae3ead4c2be229 Mon Sep 17 00:00:00 2001 From: renchenglei Date: Fri, 31 May 2019 10:53:01 +0800 Subject: [PATCH 27/27] Add xmlpool/options.h back in the list of intermediate prebuilt source files commit 092675ffa035 ("mesa3d: dragonboards: add format_srgb.c to prebuilts") overrides the list of locally generated source files(LOCAL_GENERATED_SOURCES) and we run into following build error: external/mesa3d/src/util/xmlpool.h:103:10: fatal error: 'xmlpool/options.h' file not found Currently in src/util/Android.mk, LOCAL_GENERATED_SOURCES list is populated as --> LOCAL_GENERATED_SOURCES := $(UTIL_GENERATED_SOURCES) LOCAL_GENERATED_SOURCES += $(MESA_DRI_OPTIONS_H) LOCAL_GENERATED_SOURCES := $(MESA_FORMAT_SRGB_C) The last assignment ":=" effectively overrides the existing LOCAL_GENERATED_SOURCES list including MESA_DRI_OPTIONS_H, hence causing xmlpool/options.h file not found build error. We fix the build by populating the LOCAL_GENERATED_SOURCES as: LOCAL_GENERATED_SOURCES := $(UTIL_GENERATED_SOURCES) LOCAL_GENERATED_SOURCES := $(MESA_DRI_OPTIONS_H) LOCAL_GENERATED_SOURCES += $(MESA_FORMAT_SRGB_C) As for UTIL_GENERATED_SOURCES, since AOSP master build system has started to police the use of non-hermetic tools from the system PATH, see commit 5e0738226596 ("Add prebuilt-intermediates for xmlpool) for reference, it is highly unlikely that we are going to use UTIL_GENERATED_SOURCES ever agin. So it is safe to assume and keep overriding the list of those util generated source files, at least for now. Change-Id: I173037f9303c849533037ac0abd09faf9544ce80 Signed-off-by: Amit Pundir --- src/util/Android.mk | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/util/Android.mk b/src/util/Android.mk index 5dac1f9f5f6..eb49443a7e5 100644 --- a/src/util/Android.mk +++ b/src/util/Android.mk @@ -70,14 +70,14 @@ $(intermediates)/xmlpool/options.h: $(prebuilt_intermediates)/xmlpool/options.h @cp -f $< $@ MESA_DRI_OPTIONS_H := $(intermediates)/xmlpool/options.h -LOCAL_GENERATED_SOURCES += $(MESA_DRI_OPTIONS_H) +LOCAL_GENERATED_SOURCES := $(MESA_DRI_OPTIONS_H) $(intermediates)/format_srgb.c: $(prebuilt_intermediates)/util/format_srgb.c @mkdir -p $(dir $@) @cp -f $< $@ MESA_FORMAT_SRGB_C := $(intermediates)/format_srgb.c -LOCAL_GENERATED_SOURCES := $(MESA_FORMAT_SRGB_C) +LOCAL_GENERATED_SOURCES += $(MESA_FORMAT_SRGB_C) include $(MESA_COMMON_MK) include $(BUILD_STATIC_LIBRARY)